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jevinskie/aes-over-pcie | source/pcie_top.vhd | 1 | 2,351 | -- File name: pcie_top.vhd
-- Created: 2009-04-13
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: PCIe top level
use work.pcie.all;
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pcie_top is
port (
clk : in std_logic;
nrst : in std_logic;
rx_data : in byte; --
rx_data_k : in std_logic; --
rx_status : in std_logic_vector(2 downto 0); --
rx_elec_idle : in std_logic;
phy_status : in std_logic;
rx_valid : in std_logic; --
tx_data_aes : in byte;
aes_done : in std_logic; --
tx_detect_rx : out std_logic;
tx_elec_idle : out std_logic;
tx_comp : out std_logic;
rx_pol : out std_logic;
power_down : out std_logic_vector(1 downto 0);
tx_data : out byte; --
tx_data_k : out std_logic; --
got_key : out std_logic; --
got_pt : out std_logic;--
send_ct : out std_logic--
);
end entity pcie_top;
architecture structural of pcie_top is
signal state_d, state_q : state_type;
signal subblock : subblock_type;
signal i : g_index;
signal num_shifts : index;
signal filtered : slice;
signal round_num : round_type;
signal round_key : key_type;
signal enc_key : key_type;
signal sub_bytes_out : byte;
signal shift_rows_out : row;
signal mix_columns_out : col;
signal add_round_key_out : byte;
signal load_out : byte;
signal filtered_key : byte;
signal start_key : std_logic;
signal key_done : std_logic;
signal sbox_lookup : byte;
begin
tx_elec_idle <= '0';
tx_detect_rx <= '0';
tx_comp <= '0';
rx_pol <= '0';
power_down <= "00";
bridge_b : entity work.bridge(behavioral) port map (
clk => clk, nrst => nrst, rx_data => rx_data,
tx_data_aes => tx_data_aes, rx_data_k => rx_data_k,
tx_data => tx_data, tx_data_k => tx_data_k,
got_key => got_key, got_pt => got_pt, send_ct => send_ct,
aes_done => aes_done
);
end architecture structural;
| bsd-3-clause | 76e9fa593c9525b3afa6e49d4fd2bed4 | 0.524883 | 3.224966 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/cntr_incr_decr_addn_f.vhd | 2 | 11,435 | -------------------------------------------------------------------------------
-- $Id: cntr_incr_decr_addn_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cntr_incr_decr_addn_f.vhd
--
-- Description: This counter can increment, decrement or skip ahead
-- by an arbitrary amount.
--
-- If Reset is active, the value Cnt synchronously resets
-- to all ones. (This reset value, different than the
-- customary reset value of zero, caters to the original
-- application of cntr_incr_decr_addn_f as the address
-- counter for srl_fifo_rbu_f.)
--
-- Otherwise, on each Clk, one is added to Cnt if Incr is
-- asserted and one is subtracted if Decr is asserted. (If
-- both are asserted, then there is no change to Cnt.)
--
-- If Decr is not asserted, then the input value,
-- Nm_to_add, is added. (Simultaneous assertion of Incr
-- would add one more.) If Decr is asserted, then
-- N_to_add, is ignored, i.e., it is possible to decrement
-- by one or add N, but not both, and Decr overrides.
--
-- The value that Cnt will take on at the next clock
-- is available as Cnt_p1.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
--
-- History:
-- FLO 12/30/05 First Version.
--
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity cntr_incr_decr_addn_f is
generic (
C_SIZE : natural;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic; -- Note: the counter resets to all ones!
Incr : in std_logic;
Decr : in std_logic;
N_to_add : in std_logic_vector(C_SIZE-1 downto 0);
Cnt : out std_logic_vector(C_SIZE-1 downto 0);
Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0)
);
end entity cntr_incr_decr_addn_f;
---(
library proc_common_v3_00_a;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture imp of cntr_incr_decr_addn_f is
use proc_common_v3_00_a.family_support;
use family_support.all; -- primitives_type, primitive_array_type, supported
constant COUNTER_PRIMS_AVAIL : boolean :=
supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS));
signal cnt_i : std_logic_vector(Cnt'range);
signal cnt_i_p1 : std_logic_vector(Cnt'range);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
begin -- architecture imp
---(
STRUCTURAL_A_GEN : if COUNTER_PRIMS_AVAIL = true generate
signal hsum_A : std_logic_vector(Cnt'range);
signal cry : std_logic_vector(Cnt'length downto 0);
begin
---(
cry(0) <= Incr;
Addr_Counters : for I in cnt_i'range generate
hsum_A(I) <= ((Decr or N_to_add(i)) xor cnt_i(I));
MUXCY_L_I : component MUXCY_L
port map (
DI => cnt_i(I),
CI => cry(I),
S => hsum_A(I),
LO => cry(I+1));
XORCY_I : component XORCY
port map (
LI => hsum_A(I),
CI => cry(I),
O => cnt_i_p1(I));
FDS_I : component FDS
port map (
Q => cnt_i(I),
C => Clk,
D => cnt_i_p1(I),
S => Reset);
end generate Addr_Counters;
---)
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate
--
CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr
) is
--
function qual_n_to_add(N_to_add : std_logic_vector;
Decr : std_logic
) return UNSIGNED is
variable r: UNSIGNED(N_to_add'range);
begin
for i in r'range loop
r(i) := N_to_add(i) or Decr;
end loop;
return r;
end;
--
function to_singleton_unsigned(s : std_logic) return unsigned is
variable r : unsigned(0 to 0) := (others => s);
begin
return r;
end;
--
begin
cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i)
+ qual_n_to_add(N_to_add, Decr)
+ to_singleton_unsigned(Incr)
);
end process;
--
CNT_I_PROC : process(Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
cnt_i <= (others => '1');
else
cnt_i <= cnt_i_p1;
end if;
end if;
end process;
--
end generate INFERRED_GEN;
---)
Cnt <= cnt_i;
Cnt_p1 <= cnt_i_p1;
end architecture imp;
---)
| bsd-3-clause | 0d3ab9a0720bb966ad7e6e20cdd92df3 | 0.437079 | 4.742845 | false | false | false | false |
iocoder/graduation | hardware/pit/pit.vhd | 1 | 1,528 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pit is
Port (
CLK : in STD_LOGIC;
IRQ : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1');
end pit;
architecture Behavioral of pit is
signal count : integer range 0 to 1000000000 := 0;
signal cur : integer range 0 to 1000000000 := 0;
signal irqen : boolean := false;
begin
process (CLK)
begin
if ( CLK = '1' and CLK'event ) then
-- update counter
if (cur = count) then
cur <= 0;
else
cur <= cur + 1;
end if;
-- interrupt pin
if (count = 0) then
IRQ <= '0';
elsif (cur = count and irqen) then
IRQ <= '1';
elsif (IAK = '1') then
IRQ <= '0';
end if;
-- bus interface
if (CS = '1') then
if (RW = '1') then
count <= to_integer(unsigned(Din));
irqen <= true;
else
Dout <= std_logic_vector(to_unsigned(cur, 32));
end if;
else
Dout <= x"00000000";
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 4f9539d21062aaa73882aa7c22a13a91 | 0.474476 | 3.717762 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_plbv46_bridge_v1_01_a/hdl/vhdl/opb_plbv46_bridge.vhd | 3 | 35,705 | -------------------------------------------------------------------------------
-- $Id: opb_plbv46_bridge.vhd,v 1.1.2.1 2008/12/17 19:04:49 mlovejoy Exp $
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-- Filename: opb_plbv46_bridge.vhd
--
-- Description: This bridge accepts OPB master transactions directed at any
-- one of up-to four address ranges and bridges them to the
-- PLBV46 bus. Write transactions are accepted immediately and
-- posted to an internal write buffer. The write data is
-- transported to the PLBV46 bus as soon as it is ready. Read
-- requests are satisfied through a prefetch mechanism. Once
-- the read prefetch has completed on the PLBV46 bus and data
-- from the read has been buffered internal to the bridge an
-- OPB request that matches the address of the original
-- prefetch can claim the buffer contents.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-------------------------------------------------------------------------------
-- Author: TRD
-- Revision: $Revision: 1.1.2.1 $
-- Date: $11/06/2006$
--
-- History:
-- TRD 11/06/2006 Initial V46 Version
-- MLL 09/02/2008 Rev`d to proc_common v3, added coverage/off/on
-- statements, new v1.01.a version and CHANGELOG
-- removed
-- MLL 12/17/2008 Legal header updated
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.proc_common_pkg.ALL; -- need log2()
USE proc_common_v3_00_a.family.ALL; -- need C_FAMILY definitions
LIBRARY opb_plbv46_bridge_v1_01_a;
LIBRARY plbv46_master_burst_v1_01_a;
-------------------------------------------------------------------------------
ENTITY opb_plbv46_bridge IS
GENERIC (
-- OPB Address range definition
C_NUM_ADDR_RNG : integer RANGE 1 TO 4 := 1; -- Number of Address Ranges
C_RNG0_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG0_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG1_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG1_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG2_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG2_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG3_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG3_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
-- BRIDGE CONFIGURATION
C_BUS_CLOCK_PERIOD_RATIO : integer RANGE 1 TO 2 := 1;
C_PREFETCH_TIMEOUT : integer RANGE 1 TO 32 := 10; -- prefetch timeout counter size (bits)
-- PLB I/O Specification
C_MPLB_AWIDTH : integer RANGE 32 TO 64 := 32; -- Used Address bits out of the available 64 bits of PLBV46 addressing
C_MPLB_DWIDTH : integer RANGE 32 TO 128 := 32; --Width of the PLB Data Bus to which the Master is attached
C_MPLB_NATIVE_DWIDTH : integer RANGE 32 TO 128 := 32; --Specifies the internal native data width of the Master
C_FAMILY : string := "virtex4" -- Xilinx FPGA Family Type spartan3, virtex4,virtex5
);
PORT (
-------------------------------------------------------------------------
-- PLBV46 Bus Master Interface
-------------------------------------------------------------------------
-- System Ports
MPLB_Clk : IN std_logic;
MPLB_Rst : IN std_logic;
MD_Error : OUT std_logic;
-- Master Request/Qualifiers to PLB V4.6 (outputs)
M_request : OUT std_logic;
M_priority : OUT std_logic_vector(0 TO 1);
M_busLock : OUT std_logic;
M_RNW : OUT std_logic;
M_BE : OUT std_logic_vector(0 TO (C_MPLB_DWIDTH/8) - 1);
M_MSize : OUT std_logic_vector(0 TO 1);
M_size : OUT std_logic_vector(0 TO 3);
M_type : OUT std_logic_vector(0 TO 2);
M_ABus : OUT std_logic_vector(0 TO 31);
M_wrBurst : OUT std_logic;
M_rdBurst : OUT std_logic;
M_wrDBus : OUT std_logic_vector(0 TO C_MPLB_DWIDTH-1);
-- PLB Reply to Master (inputs)
PLB_MAddrAck : IN std_logic;
PLB_MSSize : IN std_logic_vector(0 TO 1);
PLB_MRearbitrate : IN std_logic;
PLB_MTimeout : IN std_logic;
PLB_MRdErr : IN std_logic;
PLB_MWrErr : IN std_logic;
PLB_MRdDBus : IN std_logic_vector(0 TO C_MPLB_DWIDTH-1);
PLB_MRdDAck : IN std_logic;
PLB_MRdBTerm : IN std_logic;
PLB_MWrDAck : IN std_logic;
PLB_MWrBTerm : IN std_logic;
-- Included PLB ports but unused in the design
M_TAttribute : OUT std_logic_vector(0 TO 15);
M_lockErr : OUT std_logic;
M_abort : OUT std_logic;
M_UABus : OUT std_logic_vector(0 TO 31);
PLB_MBusy : IN std_logic;
PLB_MIRQ : IN std_logic;
PLB_MRdWdAddr : IN std_logic_vector(0 TO 3);
--------------------------------------------------------------------------
-- OPB Bus Slave Interface
--------------------------------------------------------------------------
-- System Interface
SOPB_rst : IN std_logic; -- opb reset
SOPB_clk : IN std_logic; -- opb clock
-- Slave ports
OPB_Select : IN std_logic; -- OPB select
OPB_RNW : IN std_logic; -- OPB Read not Write
OPB_BE : IN std_logic_vector(0 TO (32/8)-1); -- OPB transaction byte enables
OPB_seqAddr : IN std_logic; -- OPB sequential address
OPB_DBus : IN std_logic_vector(0 TO 32-1); -- OPB master data bus
OPB_ABus : IN std_logic_vector(0 TO 32-1); -- OPB Slave address bus
Sl_xferAck : OUT std_logic; -- OPB Slave transfer acknowledgement
Sl_errAck : OUT std_logic; -- OPB Slave transaction error acknowledgement
Sl_retry : OUT std_logic; -- OPB Slave transaction retry
Sl_ToutSup : OUT std_logic; -- OPB Slave timeout suppress
Sl_DBus : OUT std_logic_vector(0 TO 32-1) -- OPB Slave data BUS
);
-- Platform Specification Attributes
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST OF opb_plbv46_bridge : ENTITY IS "TRUE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE OF opb_plbv46_bridge : ENTITY IS "BRIDGE";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE OF opb_plbv46_bridge : ENTITY IS "HDL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL OF opb_plbv46_bridge : ENTITY IS "VHDL";
-- ATTRIBUTE BUSIF : string;
-- ATTRIBUTE BUSIF OF C_RNG0_BASEADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG0_HIGHADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG1_BASEADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG1_HIGHADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG2_BASEADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG2_HIGHADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG3_BASEADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG3_HIGHADDR : CONSTANT IS "SOPB";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS OF SOPB_rst : SIGNAL IS "RST";
ATTRIBUTE SIGIS OF SOPB_clk : SIGNAL IS "CLK";
ATTRIBUTE SIGIS OF MPLB_rst : SIGNAL IS "RST";
ATTRIBUTE SIGIS OF MPLB_clk : SIGNAL IS "CLK";
END ENTITY opb_plbv46_bridge;
ARCHITECTURE syn OF opb_plbv46_bridge IS
CONSTANT C_MPLB_SMALLEST_SLAVE : integer RANGE 32 TO 128 := 32;
CONSTANT C_INHIBIT_CC_BLE_INCLUSION : integer RANGE 0 TO 1 := 0;
-- IP Master Request/Qualifiers
SIGNAL IP2Bus_MstRd_Req : std_logic; -- [In]
SIGNAL IP2Bus_MstWr_Req : std_logic; -- [In]
SIGNAL IP2Bus_Mst_Addr : std_logic_vector(0 TO
C_MPLB_AWIDTH-1); -- [in]
SIGNAL IP2Bus_Mst_Length : std_logic_vector(0 TO 11); -- [in]
SIGNAL IP2Bus_Mst_BE : std_logic_vector(0 TO
(C_MPLB_NATIVE_DWIDTH/8) -1); -- [in]
SIGNAL IP2Bus_Mst_Type : std_logic; -- [in]
SIGNAL IP2Bus_Mst_Lock : std_logic; -- [In]
SIGNAL IP2Bus_Mst_Reset : std_logic; -- [In]
-- IP Master Primary Read Request Status Reply
SIGNAL Bus2IP_Mst_CmdAck : std_logic; -- [Out]
SIGNAL Bus2IP_Mst_Cmplt : std_logic; -- [Out]
SIGNAL Bus2IP_Mst_Error : std_logic; -- [Out]
SIGNAL Bus2IP_Mst_Rearbitrate : std_logic; -- [Out]
SIGNAL Bus2IP_Mst_Cmd_Timeout : std_logic; -- [out]
-- IP Master Primary Read LocalLink Interface
SIGNAL Bus2IP_MstRd_d : std_logic_vector(0 TO
C_MPLB_NATIVE_DWIDTH-1); -- [out]
SIGNAL Bus2IP_MstRd_rem : std_logic_vector(0 TO
(C_MPLB_NATIVE_DWIDTH/8)-1); -- [out]
SIGNAL Bus2IP_MstRd_sof_n : std_logic; -- [Out]
SIGNAL Bus2IP_MstRd_eof_n : std_logic; -- [Out]
SIGNAL Bus2IP_MstRd_src_rdy_n : std_logic; -- [Out]
SIGNAL Bus2IP_MstRd_src_dsc_n : std_logic; -- [Out]
SIGNAL IP2Bus_MstRd_dst_rdy_n : std_logic; -- [In]
SIGNAL IP2Bus_MstRd_dst_dsc_n : std_logic; -- [In]
-- IP Master Primary Write LocalLink Interface
SIGNAL IP2Bus_MstWr_d : std_logic_vector(0 TO
C_MPLB_NATIVE_DWIDTH-1); -- [In]
SIGNAL IP2Bus_MstWr_rem : std_logic_vector(0 TO
(C_MPLB_NATIVE_DWIDTH/8)-1) := (OTHERS => '1'); -- [In]
SIGNAL IP2Bus_MstWr_sof_n : std_logic; -- [In]
SIGNAL IP2Bus_MstWr_eof_n : std_logic; -- [In]
SIGNAL IP2Bus_MstWr_src_rdy_n : std_logic; -- [In]
SIGNAL IP2Bus_MstWr_src_dsc_n : std_logic; -- [In]
SIGNAL Bus2IP_MstWr_dst_rdy_n : std_logic; -- [Out]
SIGNAL Bus2IP_MstWr_dst_dsc_n : std_logic; -- [Out]
-- OPB slave to Bridge Interface
SIGNAL brdg_block : std_logic; -- [IN] bridge block
SIGNAL brdg_prefetch_cmplt : std_logic; -- [IN] bridge prefetch complete
SIGNAL brdg_prefetch_status : std_logic; -- [IN] bridge prefetch status
SIGNAL brdg_prefetch_addr : std_logic_vector(0 TO 31); -- [IN] bridge prefetch address
SIGNAL opbs_prefetch_req : std_logic; -- [OUT] opb slave prefetch request
SIGNAL opbs_type : std_logic; -- [OUT] opb slave transaction request type
SIGNAL opbs_prefetch_clr : std_logic; -- [OUT] opb slave prefetch clear
SIGNAL opbs_postedwr_clr : std_logic; -- [OUT] opb slave posted write clear
SIGNAL opbs_trans_addr : std_logic_vector(0 TO 31); -- [OUT] opb slave transaction address
SIGNAL opbs_length : std_logic_vector(0 TO 11); -- [OUT] opb slave transaction length
SIGNAL opbs_postedwrt_req : std_logic; -- [OUT] opb slave posted write request
SIGNAL opbs_be : std_logic_vector(0 TO 3); -- [OUT] opb slave byte enable
-- Local Link Read Buffer
SIGNAL bfs_data : std_logic_vector(0 TO 31); -- [IN] Read data output to user logic
SIGNAL bfs_sof_n : std_logic; -- [IN] Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
SIGNAL bfs_eof_n : std_logic; -- [IN] Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
SIGNAL bfs_src_rdy_n : std_logic; -- [IN] Asserts active low to indicate the presence of valid data on signal bfs_data.
SIGNAL bfs_src_dsc_n : std_logic; -- [IN] Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
SIGNAL bfs_dst_rdy_n : std_logic; -- [OUT] Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
SIGNAL bfs_dst_dsc_n : std_logic; -- [OUT] Active low signal that the read local link destination needs to discontinue the transfer.
SIGNAL brdg_rd_bf_rst : std_logic; -- [IN]
-- Local Link Write Buffer
SIGNAL bfd_data : std_logic_vector(0 TO 31); -- [OUT]
SIGNAL bfd_sof_n : std_logic; -- [OUT]
SIGNAL bfd_eof_n : std_logic; -- [OUT]
SIGNAL bfd_src_rdy_n : std_logic; -- [OUT]
SIGNAL bfd_src_dsc_n : std_logic; -- [OUT]
SIGNAL bfd_dst_rdy_n : std_logic; -- [IN]
SIGNAL bfd_dst_dsc_n : std_logic; -- [IN]
SIGNAL brdg_wr_bf_rst : std_logic; -- [IN]
BEGIN
x_plbv46_master_burst : ENTITY plbv46_master_burst_v1_01_a.plbv46_master_burst
GENERIC MAP (
-- PLB Parameters
C_MPLB_AWIDTH => C_MPLB_AWIDTH, -- [INTEGER range 32 to 36]
-- Number of PLBV46 Address Bus bits actually used.
C_MPLB_DWIDTH => C_MPLB_DWIDTH, -- [INTEGER range 32 to 128]
-- Width of the PLBV46 Data Bus Attachment (in bits)
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH, -- [INTEGER range 32 to 32]
-- Set this equal to largest data bus width needed by IPIF
-- and IP elements.
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
-- Indicates the Native Data Width of the smallest slave
-- on the PLB connected to this Master. If this parameter's
-- value is less than the native Data width of the Master,
-- then the Conversion Cycle and Burst Length Expansion
-- Adapter will be included in the Master's implementation.
C_INHIBIT_CC_BLE_INCLUSION => C_INHIBIT_CC_BLE_INCLUSION,
-- This parameter will inhibit the automatic inclusion
-- of the Conversion Cycle and Burst length Expansion
-- Adapter. This override is useful if the connected PLB has
-- narrow Slaves attached to it but this Master will not access
-- those narrow Slaves.
-- FPGA Family Parameter
C_FAMILY => C_FAMILY) -- [String]
PORT MAP (
-- System Ports
MPLB_Clk => MPLB_Clk, -- [In std_logic]
MPLB_Rst => MPLB_Rst, -- [In std_logic]
MD_Error => MD_Error, -- [Out std_logic]
-- Master Request/Qualifiers to PLB V4.6 (outputs)
M_request => M_request, -- [out std_logic]
M_priority => M_priority, -- [out std_logic_vector(0 to 1)]
M_busLock => M_busLock, -- [out std_logic]
M_RNW => M_RNW, -- [out std_logic]
M_BE => M_BE, -- [out std_logic_vector(0 to (C_MPLB_DWIDTH/8) - 1)]
M_MSize => M_MSize, -- [out std_logic_vector(0 to 1)]
M_size => M_size, -- [out std_logic_vector(0 to 3)]
M_type => M_type, -- [out std_logic_vector(0 to 2)]
M_ABus => M_ABus, -- [out std_logic_vector(0 to 31)]
M_wrBurst => M_wrBurst, -- [out std_logic]
M_rdBurst => M_rdBurst, -- [out std_logic]
M_wrDBus => M_wrDBus, -- [out std_logic_vector(0 to C_MPLB_DWIDTH-1)]
-- PLB Reply to Master (inputs)
PLB_MAddrAck => PLB_MAddrAck, -- [in std_logic]
PLB_MSSize => PLB_MSSize, -- [in std_logic_vector(0 to 1)]
PLB_MRearbitrate => PLB_MRearbitrate, -- [in std_logic]
PLB_MTimeout => PLB_MTimeout, -- [in std_logic]
PLB_MRdErr => PLB_MRdErr, -- [in std_logic]
PLB_MWrErr => PLB_MWrErr, -- [in std_logic]
PLB_MRdDBus => PLB_MRdDBus, -- [in std_logic_vector(0 to C_MPLB_DWIDTH-1)]
PLB_MRdDAck => PLB_MRdDAck, -- [in std_logic]
PLB_MRdBTerm => PLB_MRdBTerm, -- [in std_logic]
PLB_MWrDAck => PLB_MWrDAck, -- [in std_logic]
PLB_MWrBTerm => PLB_MWrBTerm, -- [in std_logic]
-- Included PLB ports but unused in the design
M_TAttribute => M_TAttribute, -- [out std_logic_vector(0 to 15)]
M_lockErr => M_lockErr, -- [out std_logic]
M_abort => M_abort, -- [out std_logic]
M_UABus => M_UABus, -- [out std_logic_vector(0 to 31)]
PLB_MBusy => PLB_MBusy, -- [in std_logic]
PLB_MIRQ => PLB_MIRQ, -- [in std_logic]
PLB_MRdWdAddr => PLB_MRdWdAddr, -- [in std_logic_vector(0 to 3)]
-- IP Master Request/Qualifiers
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req, -- [In std_logic]
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req, -- [In std_logic]
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr, -- [in std_logic_vector(0 toC_MPLB_AWIDTH-1)]
IP2Bus_Mst_Length => IP2Bus_Mst_Length, -- [in std_logic_vector(0 to 11)]
IP2Bus_Mst_BE => IP2Bus_Mst_BE, -- [in std_logic_vector(0 to(C_MPLB_NATIVE_DWIDTH/8) -1)]
IP2Bus_Mst_Type => IP2Bus_Mst_Type, -- [in std_logic]
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock, -- [In std_logic]
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset, -- [In std_logic]
-- IP Master Primary Read Request Status Reply
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck, -- [Out std_logic]
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt, -- [Out std_logic]
Bus2IP_Mst_Error => Bus2IP_Mst_Error, -- [Out std_logic]
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate, -- [Out std_logic]
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout, -- [out std_logic]
-- IP Master Primary Read LocalLink Interface
Bus2IP_MstRd_d => Bus2IP_MstRd_d, -- [out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1)]
Bus2IP_MstRd_rem => OPEN, -- [out std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1)]
Bus2IP_MstRd_sof_n => Bus2IP_MstRd_sof_n, -- [Out std_logic]
Bus2IP_MstRd_eof_n => Bus2IP_MstRd_eof_n, -- [Out std_logic]
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n, -- [Out std_logic]
Bus2IP_MstRd_src_dsc_n => Bus2IP_MstRd_src_dsc_n, -- [Out std_logic]
IP2Bus_MstRd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n, -- [In std_logic]
IP2Bus_MstRd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n, -- [In std_logic]
-- IP Master Primary Write LocalLink Interface
IP2Bus_MstWr_d => IP2Bus_MstWr_d, -- [In std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1)]
IP2Bus_MstWr_rem => IP2Bus_MstWr_rem, -- [In std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1)]
IP2Bus_MstWr_sof_n => IP2Bus_MstWr_sof_n, -- [In std_logic]
IP2Bus_MstWr_eof_n => IP2Bus_MstWr_eof_n, -- [In std_logic]
IP2Bus_MstWr_src_rdy_n => IP2Bus_MstWr_src_rdy_n, -- [In std_logic]
IP2Bus_MstWr_src_dsc_n => IP2Bus_MstWr_src_dsc_n, -- [In std_logic]
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n, -- [Out std_logic]
Bus2IP_MstWr_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n); -- [Out std_logic]
x_rd_buffer : ENTITY opb_plbv46_bridge_v1_01_a.buffer_x16
GENERIC MAP (
C_FAMILY => C_FAMILY) -- [string] Xilinx FPGA Family Type spartan3, virtex4, virtex5
PORT MAP (
-- Source Interface (from the OPB slave)
bfs_data => bfs_data, -- [OUT std_logic_vector(0 TO 31)] Read data output to user logic
bfs_sof_n => bfs_sof_n, -- [OUT std_logic] Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n => bfs_eof_n, -- [OUT std_logic] Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n => bfs_src_rdy_n, -- [OUT std_logic] Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n => bfs_src_dsc_n, -- [OUT std_logic] Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n => bfs_dst_rdy_n, -- [IN std_logic] Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n => bfs_dst_dsc_n, -- [IN std_logic] Active low signal that the read local link destination needs to discontinue the transfer.
-- Destination (Sink) Interface (to the plbv46_master_burst)
bfd_data => Bus2IP_MstRd_d, -- [IN std_logic_vector(0 TO 31)]
bfd_sof_n => Bus2IP_MstRd_sof_n, -- [IN std_logic]
bfd_eof_n => Bus2IP_MstRd_eof_n, -- [IN std_logic]
bfd_src_rdy_n => Bus2IP_MstRd_src_rdy_n, -- [IN std_logic]
bfd_src_dsc_n => Bus2IP_MstRd_src_dsc_n, -- [IN std_logic]
bfd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n, -- [OUT std_logic]
bfd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n, -- [OUT std_logic]
-- System Interface
rst => brdg_rd_bf_rst, -- [IN std_logic] reset
clk => MPLB_clk); -- [IN std_logic] clock
x_wr_buffer : ENTITY opb_plbv46_bridge_v1_01_a.buffer_x16
GENERIC MAP (
C_FAMILY => C_FAMILY) -- [string] Xilinx FPGA Family Type spartan3, virtex4, virtex5
PORT MAP (
-- Source Interface (from the plbv46_master_burst)
bfs_data => IP2Bus_MstWr_d, -- [OUT std_logic_vector(0 TO 31)] Read data output to user logic
bfs_sof_n => IP2Bus_MstWr_sof_n, -- [OUT std_logic] Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n => IP2Bus_MstWr_eof_n, -- [OUT std_logic] Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n => IP2Bus_MstWr_src_rdy_n, -- [OUT std_logic] Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n => IP2Bus_MstWr_src_dsc_n, -- [OUT std_logic] Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n, -- [IN std_logic] Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n, -- [IN std_logic] Active low signal that the read local link destination needs to discontinue the transfer.
-- Destination (Sink) Interface (to the opb_slave)
bfd_data => bfd_data, -- [IN std_logic_vector(0 TO 31)]
bfd_sof_n => bfd_sof_n, -- [IN std_logic]
bfd_eof_n => bfd_eof_n, -- [IN std_logic]
bfd_src_rdy_n => bfd_src_rdy_n, -- [IN std_logic]
bfd_src_dsc_n => bfd_src_dsc_n, -- [IN std_logic]
bfd_dst_rdy_n => bfd_dst_rdy_n, -- [OUT std_logic]
bfd_dst_dsc_n => bfd_dst_dsc_n, -- [OUT std_logic]
-- System Interface
rst => brdg_wr_bf_rst, -- [IN std_logic] reset
clk => MPLB_clk); -- [IN std_logic] clock
x_bridge : ENTITY opb_plbv46_bridge_v1_01_a.bridge
GENERIC MAP (
-- BRIDGE CONFIGURATION
C_PREFETCH_TIMEOUT => C_PREFETCH_TIMEOUT, --
-- System wide Specification
C_FAMILY => C_FAMILY) -- [string] Xilinx FPGA Family Type spartan3, virtex4, virtex5
PORT MAP (
-- PLBV46 Master Burst Interface
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req, -- [OUT std_logic] User Logic Read Request
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req, -- [OUT std_logic] User Logic Write Request
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr, -- [OUT std_logic_vector(0 TO 32-1)] User Logic Request Address
IP2Bus_Mst_BE => IP2Bus_Mst_BE, -- [OUT std_logic_vector(0 TO (32/8)-1)] User Logic Request Byte Enables (only used during single data beat requests)
IP2Bus_Mst_Length => IP2Bus_Mst_Length, -- [OUT std_logic_vector(0 TO 11)]
IP2Bus_Mst_Type => IP2Bus_Mst_Type, -- [OUT std_logic] User Logic Request Type Indicator
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock, -- [OUT std_logic] User Logic Bus Lock Request
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset, -- [OUT std_logic] Optional User Logic Reset Request.
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck, -- [IN std_logic] Command Acknowledge Status
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt, -- [IN std_logic] Command Complete Status
Bus2IP_Mst_Error => Bus2IP_Mst_Error, -- [IN std_logic] Command Error Status
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate, -- [IN std_logic] Command Rearbitrate Status
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout, -- [IN std_logic] Command Timeout Status
-- opb_slave Interface
opbs_prefetch_req => opbs_prefetch_req, -- [IN std_logic] opb slave prefetch request
opbs_type => opbs_type, -- [IN std_logic] opb slave transaction request type
opbs_prefetch_clr => opbs_prefetch_clr, -- [IN std_logic] opb slave prefetch clear
opbs_postedwr_clr => opbs_postedwr_clr, -- [IN std_logic] opb slave posted write clear
opbs_length => opbs_length, -- [IN std_logic_vector(0 TO 11)] opb slave transaction length
opbs_postedwrt_req => opbs_postedwrt_req, -- [IN std_logic] opb slave posted write request
opbs_trans_addr => opbs_trans_addr, -- [IN std_logic_vector(0 TO 31)] opb slave transaction address
opbs_be => opbs_be, -- [IN std_logic_vector(0 TO 3)] opb slave byte enable
brdg_block => brdg_block, -- [OUT std_logic] bridge block
brdg_prefetch_cmplt => brdg_prefetch_cmplt, -- [OUT std_logic] bridge prefetch complete
brdg_prefetch_status => brdg_prefetch_status, -- [OUT std_logic] bridge prefetch status
-- Buffer Interface
brdg_wr_bf_rst => brdg_wr_bf_rst, -- [OUT std_logic] bridge write buffer reset
brdg_rd_bf_rst => brdg_rd_bf_rst, -- [OUT std_logic] bridge read buffer reset
-- System
MPLB_rst => MPLB_rst, -- [IN std_logic] plb reset
MPLB_clk => MPLB_clk); -- [IN std_logic] plb clock
x_opb_slave : ENTITY opb_plbv46_bridge_v1_01_a.opb_slave
GENERIC MAP (
-- OPB Address range definition
C_NUM_ADDR_RNG => C_NUM_ADDR_RNG, -- [integer RANGE 1 TO 4] Number of Address Ranges
C_RNG0_BASEADDR => C_RNG0_BASEADDR, -- [std_logic_vector(0 TO 31)] Address range definition base address
C_RNG0_HIGHADDR => C_RNG0_HIGHADDR, -- [std_logic_vector(0 TO 31)] Address range definition high address
C_RNG1_BASEADDR => C_RNG1_BASEADDR, -- [std_logic_vector(0 TO 31)] Address range definition base address
C_RNG1_HIGHADDR => C_RNG1_HIGHADDR, -- [std_logic_vector(0 TO 31)] Address range definition high address
C_RNG2_BASEADDR => C_RNG2_BASEADDR, -- [std_logic_vector(0 TO 31)] Address range definition base address
C_RNG2_HIGHADDR => C_RNG2_HIGHADDR, -- [std_logic_vector(0 TO 31)] Address range definition high address
C_RNG3_BASEADDR => C_RNG3_BASEADDR, -- [std_logic_vector(0 TO 31)] Address range definition base address
C_RNG3_HIGHADDR => C_RNG3_HIGHADDR, -- [std_logic_vector(0 TO 31)] Address range definition high address
-- BRIDGE CONFIGURATION
C_BUS_CLOCK_PERIOD_RATIO => C_BUS_CLOCK_PERIOD_RATIO, -- [integer RANGE 1 TO 2]
-- PLB I/O Specification
C_FAMILY => C_FAMILY) -- [string] Xilinx FPGA Family Type spartan3, virtex4, virtex5
PORT MAP (
-- OPBS Interface
brdg_block => brdg_block, -- [IN std_logic] bridge block
brdg_prefetch_cmplt => brdg_prefetch_cmplt, -- [IN std_logic] bridge prefetch complete
brdg_prefetch_status => brdg_prefetch_status, -- [IN std_logic] bridge prefetch status
opbs_prefetch_req => opbs_prefetch_req, -- [OUT std_logic] opb slave prefetch request
opbs_type => opbs_type, -- [OUT std_logic] opb slave transaction request type
opbs_prefetch_clr => opbs_prefetch_clr, -- [OUT std_logic] opb slave prefetch clear
opbs_postedwr_clr => opbs_postedwr_clr, -- [OUT std_logic] opb slave posted write clear
opbs_trans_addr => opbs_trans_addr, -- [OUT std_logic_vector(0 TO 31)] opb slave transaction address
opbs_length => opbs_length, -- [OUT std_logic_vector(0 TO 11)] opb slave transaction length
opbs_postedwrt_req => opbs_postedwrt_req, -- [OUT std_logic] opb slave posted write request
opbs_be => opbs_be, -- [OUT std_logic_vector(0 TO 3)] opb slave byte enable
-- Local Link Read Buffer
bfs_data => bfs_data, -- [IN std_logic_vector(0 TO 31)] Read data output to user logic
bfs_sof_n => bfs_sof_n, -- [IN std_logic] Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n => bfs_eof_n, -- [IN std_logic] Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n => bfs_src_rdy_n, -- [IN std_logic] Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n => bfs_src_dsc_n, -- [IN std_logic] Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n => bfs_dst_rdy_n, -- [OUT std_logic] Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n => bfs_dst_dsc_n, -- [OUT std_logic] Active low signal that the read local link destination needs to discontinue the transfer.
-- Local Link Write Buffer
bfd_data => bfd_data, -- [OUT std_logic_vector(0 TO 31)]
bfd_sof_n => bfd_sof_n, -- [OUT std_logic]
bfd_eof_n => bfd_eof_n, -- [OUT std_logic]
bfd_src_rdy_n => bfd_src_rdy_n, -- [OUT std_logic]
bfd_src_dsc_n => bfd_src_dsc_n, -- [OUT std_logic]
bfd_dst_rdy_n => bfd_dst_rdy_n, -- [IN std_logic]
bfd_dst_dsc_n => bfd_dst_dsc_n, -- [IN std_logic]
-- OPB Slave Interface
OPB_Select => OPB_Select, -- [IN std_logic] OPB Master select
OPB_RNW => OPB_RNW, -- [IN std_logic] OPB Read not Write
OPB_BE => OPB_BE, -- [IN std_logic_vector(0 TO (32/8)-1)] OPB transaction byte enables
OPB_seqAddr => OPB_seqAddr, -- [IN std_logic] OPB sequential address
OPB_DBus => OPB_DBus, -- [IN std_logic_vector(0 TO 32-1)] OPB master data bus
OPB_ABus => OPB_ABus, -- [IN std_logic_vector(0 TO 32-1)] OPB Slave address bus
Sl_xferAck => Sl_xferAck, -- [OUT std_logic] OPB Slave transfer acknowledgement
Sl_errAck => Sl_errAck, -- [OUT std_logic] OPB Slave transaction error acknowledgement
Sl_retry => Sl_retry, -- [OUT std_logic] OPB Slave transaction retry
Sl_ToutSup => Sl_ToutSup, -- [OUT std_logic] OPB Slave timeout suppress
Sl_DBus => Sl_DBus, -- [OUT std_logic_vector(0 TO 32-1)] OPB Slave data BUS
-- System Interface
MPLB_rst => MPLB_rst, -- [IN std_logic] plb reset
MPLB_clk => MPLB_clk, -- [IN std_logic] plb clock
SOPB_rst => SOPB_rst, -- [IN std_logic] opbv46 reset
SOPB_clk => SOPB_clk); -- [IN std_logic] opbv46 clock
END ARCHITECTURE syn;
| bsd-3-clause | 2851524c3c80db32fb463f6f5e5a3979 | 0.576642 | 3.597119 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/common/ShiftReg.vhd | 1 | 900 | library ieee;
use ieee.std_logic_1164.all;
--Library synplify;
--use synplify.attributes.all;
entity ShiftReg is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector(width-1 downto 0);
Q : out std_logic_vector(width-1 downto 0) := ( others => '0' );
S : out std_logic_vector(width-1 downto 0)
);
end ShiftReg;
architecture behave of ShiftReg is
type ram_memtype is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal mem : ram_memtype := (others => (others => '0'));
-- attribute syn_srlstyle of mem : signal is "select_srl";
begin
mem(0) <= D;
process(clk)
begin
if rising_edge(clk) then
if ce = '1' then
mem(depth downto 1) <= mem(depth-1 downto 0);
Q <= mem (depth-1);
end if;
end if;
end process;
S <= mem(depth);
end behave; | gpl-2.0 | 9e2f95251bda8da0bf4a8b2400ffa846 | 0.617778 | 2.848101 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/opb_SynchManager_v1_00_c/hdl/vhdl/master.vhd | 2 | 9,915 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity master is
generic
(
C_BASEADDR : std_logic_vector := x"00000000";
C_HIGHADDR : std_logic_vector := x"FFFFFFFF";
C_SCHED_BASEADDR : std_logic_vector := x"00000000";
C_RESULT_BASEADDR : std_logic_vector := x"00000000";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 6;
C_NUM_CE : integer := 4
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RNW : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : in std_logic;
send_id : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : out std_logic;
saddr : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sena : out std_logic;
swea : out std_logic;
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end master;
architecture behavioral of master is
constant THR_BIT : integer := log2( C_NUM_THREADS );
type send_state is
(
IDLE,
SENDING
);
type queue_state is
(
IDLE,
DONE,
GETWAIT,
GETDONE
);
signal send_cs : send_state;
signal send_ns : send_state;
signal queue_cs : queue_state;
signal queue_ns : queue_state;
signal send_rdy : std_logic;
signal send_valid : std_logic;
signal send_validn : std_logic;
signal send_cur : std_logic_vector(0 to THR_BIT-1);
signal send_curn : std_logic_vector(0 to THR_BIT-1);
signal send_first : std_logic_vector(0 to THR_BIT-1);
signal send_firstn : std_logic_vector(0 to THR_BIT-1);
signal send_last : std_logic_vector(0 to THR_BIT-1);
signal send_lastn : std_logic_vector(0 to THR_BIT-1);
signal send_count : std_logic_vector(0 to THR_BIT-1);
signal send_countn : std_logic_vector(0 to THR_BIT-1);
begin
-- System reset only takes one clock cycle so were always "done"
system_resetdone <= '1';
queue_update : process(Bus2IP_Clk) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
queue_cs <= IDLE;
send_count <= (others => '0');
send_first <= (others => '0');
send_last <= (others => '0');
send_cur <= (others => '0');
send_valid <= '0';
else
queue_cs <= queue_ns;
send_count <= send_countn;
send_first <= send_firstn;
send_last <= send_lastn;
send_cur <= send_curn;
send_valid <= send_validn;
end if;
end if;
end process queue_update;
queue_controller : process(Bus2IP_Clk,queue_cs, send_cur, send_last, send_first, send_count, send_ena, send_id, send_rdy, sinext) is
begin
sena <= '0';
swea <= '0';
saddr <= (others => '0');
sonext <= (others => '0');
queue_ns <= queue_cs;
send_curn <= send_cur;
send_lastn <= send_last;
send_firstn <= send_first;
send_countn <= send_count;
send_validn <= '0';
case queue_cs is
when IDLE =>
if( send_ena = '1' ) then
if( send_count = zero(THR_BIT) ) then
send_firstn <= send_id;
else
sena <= '1';
swea <= '1';
saddr <= send_last;
sonext <= send_id;
end if;
send_lastn <= send_id;
send_countn <= send_count+1;
send_ack <= '1';
queue_ns <= DONE;
elsif( send_rdy = '1' and send_count /= zero(THR_BIT) ) then
send_curn <= send_first;
send_validn <= '1';
sena <= '1';
saddr <= send_first;
queue_ns <= GETWAIT;
end if;
when DONE =>
send_ack <= '1';
if( send_ena = '0' ) then
queue_ns <= IDLE;
end if;
when GETWAIT => null;
queue_ns <= GETDONE;
when GETDONE =>
send_firstn <= sinext;
send_countn <= send_count-1;
queue_ns <= IDLE;
end case;
end process queue_controller;
send_update : process (Bus2IP_Clk,send_ns) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
send_cs <= IDLE;
else
send_cs <= send_ns;
end if;
end if;
end process send_update;
send_controller : process (Bus2IP_MstLastAck,send_cs,send_valid,send_cur) is
begin
send_ns <= send_cs;
send_rdy <= '0';
IP2IP_Addr <= (others => '0');
IP2Bus_Addr <= (others => '0');
IP2Bus_MstBE <= (others => '0');
IP2Bus_MstBurst <= '0';
IP2Bus_MstBusLock <= '0';
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
case send_cs is
when IDLE =>
send_rdy <= '1';
if( send_valid = '1' ) then
IP2Bus_Addr <= add_thread(C_SCHED_BASEADDR,send_cur);
IP2Bus_MstRdReq <= '1';
IP2Bus_MstBE <= (others => '1');
IP2IP_Addr <= C_RESULT_BASEADDR;
send_ns <= SENDING;
end if;
when SENDING =>
IP2Bus_Addr <= add_thread(C_SCHED_BASEADDR,send_cur);
IP2Bus_MstRdReq <= '1';
IP2Bus_MstBE <= (others => '1');
IP2IP_Addr <= C_RESULT_BASEADDR;
if( Bus2IP_MstLastAck = '1' ) then
send_ns <= IDLE;
end if;
end case;
end process send_controller;
end behavioral;
| bsd-3-clause | c30c6caf8a5af55b6bf5a7145374649a | 0.501362 | 3.905081 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/unlock_fsm.vhd | 11 | 8,349 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity unlock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1);
sysrst : in std_logic;
rstdone : out std_logic;
sena : out std_logic;
sid : out std_logic_vector(0 to C_TWIDTH-1);
sack : in std_logic
);
end unlock_fsm;
architecture behavioral of unlock_fsm is
-- A type for the states in the unlock fsm
type unlock_state is
(
IDLE,
READ_MUTEX,
DONE_MUTEX,
READ_THREAD,
DONE_THREAD
);
-- Declare signals for the unlock fsm
signal unlock_cs : unlock_state;
signal unlock_ns : unlock_state;
signal hold_minext : std_logic_vector(0 to C_TWIDTH-1);
signal hold_minext_nxt : std_logic_vector(0 to C_TWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
unlock_update : process (clk,rst,sysrst,unlock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
unlock_cs <= IDLE;
hold_minext <= (others => '0');
else
unlock_cs <= unlock_ns;
hold_minext <= hold_minext_nxt;
end if;
end if;
end process unlock_update;
unlock_controller : process (unlock_cs,start,mutex,micount,mikind,miowner,milast,minext,tinext,hold_minext) is
begin
unlock_ns <= unlock_cs;
hold_minext_nxt <= (others => '0');
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
sena <= '0';
sid <= (others => '0');
case unlock_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
unlock_ns <= READ_MUTEX;
end if;
when READ_MUTEX =>
unlock_ns <= DONE_MUTEX;
when DONE_MUTEX =>
if( mikind = SYNCH_RECURS and micount /= one(C_CWIDTH) and micount /= zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
mocount <= micount - 1;
mokind <= mikind;
monext <= minext;
molast <= milast;
finish <= '1';
unlock_ns <= IDLE;
elsif( micount = one(C_CWIDTH) ) then
if( milast = miowner ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= (others => '0');
mocount <= (others => '0');
mokind <= mikind;
monext <= (others => '0');
molast <= (others => '0');
finish <= '1';
unlock_ns <= IDLE;
else
toaddr <= minext;
toena <= '1';
towea <= '0';
unlock_ns <= READ_THREAD;
hold_minext_nxt <= minext;
end if;
else
data(0) <= '1';
finish <= '1';
unlock_ns <= IDLE;
end if;
when READ_THREAD =>
hold_minext_nxt <= hold_minext;
unlock_ns <= DONE_THREAD;
when DONE_THREAD =>
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= hold_minext;
mocount <= one(C_CWIDTH);
mokind <= mikind;
molast <= milast;
monext <= tinext;
sena <= '1';
sid <= hold_minext;
finish <= '1';
unlock_ns <= IDLE;
end case;
end process unlock_controller;
end behavioral;
| bsd-3-clause | 5b38080df2de0094fa1a31cd0840b8ea | 0.467601 | 4.445687 | false | false | false | false |
iocoder/graduation | hardware/vga/ppuseq.vhd | 1 | 18,456 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ppuseq is
Port (CLK : in STD_LOGIC;
SE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : in STD_LOGIC_VECTOR (15 downto 0);
PPU_HSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_VSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC := '0';
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC := '0';
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC := '0';
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC := '0';
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4Read : out STD_LOGIC := '0';
VRAM4Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM4Data : in STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : in STD_LOGIC;
SprWR : in STD_LOGIC;
SprAddr : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : in STD_LOGIC;
PalWR : in STD_LOGIC;
PalAddr : in STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
Color : out STD_LOGIC_VECTOR ( 5 downto 0) := "000000");
end ppuseq;
architecture Dataflow of ppuseq is
signal phase : integer := 0;
signal counter : integer := 0;
signal PatAddr1 : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatAddr2 : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatAddr : STD_LOGIC_VECTOR (12 downto 0) := "0" & x"000";
signal PatRead : STD_LOGIC := '0';
signal PatData : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
-- sprites
type sprites_t is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0);
signal sprites : sprites_t := (others => x"00");
signal sprindex : integer := 0;
signal sprdata : STD_LOGIC_VECTOR (7 downto 0) := x"00";
type sprcache_t is array (0 to 7) of STD_LOGIC_VECTOR (31 downto 0);
signal sprcache : sprcache_t := (others => x"00000000");
signal lastSprRD : STD_LOGIC := '0';
signal lastSprWR : STD_LOGIC := '0';
-- palette
type palette_t is array (0 to 15) of STD_LOGIC_VECTOR (5 downto 0);
signal PatPal : palette_t := (others => "000000"); -- pattern palette
signal SprPal : palette_t := (others => "000000"); -- sprite palette
signal lastPalRD : STD_LOGIC := '0';
signal lastPalWR : STD_LOGIC := '0';
attribute ram_style: string;
attribute ram_style of sprites : signal is "block";
-- attribute ram_style of sprcache : signal is "block";
begin
PatAddr <= PatAddr1 when phase = 2 else PatAddr2;
VRAM0Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM1Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM2Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM3Addr <= PatAddr(11 downto 4) & PatAddr(2 downto 0);
VRAM0Read <= (NOT PatAddr(12));
VRAM1Read <= (NOT PatAddr(12));
VRAM2Read <= ( PatAddr(12));
VRAM3Read <= ( PatAddr(12));
PatData( 7 downto 0) <= VRAM0Data or VRAM2Data;
PatData(15 downto 8) <= VRAM1Data or VRAM3Data;
process (CLK)
variable tcolor : STD_LOGIC_VECTOR ( 3 downto 0) := "0000";
variable scolor : STD_LOGIC_VECTOR ( 3 downto 0) := "0000";
variable ashift : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
variable bshift : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
variable n : integer := 0;
variable m : integer := 0;
variable sstate : integer := 0;
variable cur_y : integer := 0;
variable spr_y : integer := 0;
variable max_y : integer := 0;
variable row : integer := 0;
variable cur_x : integer := 0;
variable spr0x : integer := 0;
variable spr1x : integer := 0;
variable spr2x : integer := 0;
variable spr3x : integer := 0;
variable spr4x : integer := 0;
variable spr5x : integer := 0;
variable spr6x : integer := 0;
variable spr7x : integer := 0;
variable offset : integer := 0;
variable sprindx : integer := 0;
variable V : STD_LOGIC := '0'; -- vert. nametable
variable H : STD_LOGIC := '0'; -- hori. nametable
variable VT : STD_LOGIC_VECTOR ( 4 downto 0); -- vert. tile index
variable HT : STD_LOGIC_VECTOR ( 4 downto 0); -- hori. tile index
variable FV : STD_LOGIC_VECTOR ( 2 downto 0); -- vert. pixel index
variable FH : STD_LOGIC_VECTOR ( 2 downto 0); -- hori. pixel index
begin
if (CLK = '1' and CLK'event ) then
-- sprite processing
if (SE = '0' or phase = 0 or phase = 4) then
-- make use of hblank time by loading
if (n < 64 and m < 8) then
if (sstate = 0) then
-- current sprite in range?
spr_y := conv_integer(unsigned(sprdata))+1;
if (PPU_CTRL(5) = '0') then
max_y := spr_y + 8;
else
max_y := spr_y + 16;
end if;
if (cur_y >= spr_y and cur_y < max_y) then
-- in range
row := cur_y-spr_y;
sstate := 1;
sprindex <= sprindex + 2;
else
-- skip
n := n + 1;
sprindex <= sprindex + 4;
end if;
elsif (sstate = 1) then
-- store sprite attributes
sprcache(m)(15 downto 8) <= sprdata;
if (sprdata(7) = '1') then
if (PPU_CTRL(5) = '0') then
row := 7 - row;
else
row := 15 - row;
end if;
end if;
sprindex <= sprindex + 1;
sstate := 2;
elsif (sstate = 2) then
-- store sprite X
if (m = 0) then
spr0x:=conv_integer(unsigned(sprdata));
elsif (m = 1) then
spr1x:=conv_integer(unsigned(sprdata));
elsif (m = 2) then
spr2x:=conv_integer(unsigned(sprdata));
elsif (m = 3) then
spr3x:=conv_integer(unsigned(sprdata));
elsif (m = 4) then
spr4x:=conv_integer(unsigned(sprdata));
elsif (m = 5) then
spr5x:=conv_integer(unsigned(sprdata));
elsif (m = 6) then
spr6x:=conv_integer(unsigned(sprdata));
elsif (m = 7) then
spr7x:=conv_integer(unsigned(sprdata));
end if;
sprcache(m)(7 downto 0) <= sprdata;
sprindex <= sprindex - 2;
sstate := 3;
elsif (sstate = 3) then
--load color bit 0
if (PPU_CTRL(5) = '0') then
PatAddr2 <= PPU_CTRL(3) &
sprdata &
"0" &
conv_std_logic_vector(row,3);
elsif (row < 8) then
PatAddr2 <= sprdata(0) &
sprdata(7 downto 1) & "0" &
"0" &
conv_std_logic_vector(row,3);
else
PatAddr2 <= sprdata(0) &
sprdata(7 downto 1) & "1" &
"0" &
conv_std_logic_vector(row-8,3);
end if;
PatRead <= '1';
sprindex <= sprindex + 1;
sstate := 4;
elsif (sstate = 4) then
sstate := 5;
elsif (sstate = 5) then
-- read color bit 0
if (sprdata(6) = '0') then
sprcache(m)(16) <= PatData(7);
sprcache(m)(17) <= PatData(6);
sprcache(m)(18) <= PatData(5);
sprcache(m)(19) <= PatData(4);
sprcache(m)(20) <= PatData(3);
sprcache(m)(21) <= PatData(2);
sprcache(m)(22) <= PatData(1);
sprcache(m)(23) <= PatData(0);
sprcache(m)(24) <= PatData(15);
sprcache(m)(25) <= PatData(14);
sprcache(m)(26) <= PatData(13);
sprcache(m)(27) <= PatData(12);
sprcache(m)(28) <= PatData(11);
sprcache(m)(29) <= PatData(10);
sprcache(m)(30) <= PatData(9);
sprcache(m)(31) <= PatData(8);
else
sprcache(m)(31 downto 16) <= PatData;
end if;
-- next sprite
m := m + 1;
n := n + 1;
sprindex <= sprindex + 2;
sstate := 0;
end if;
end if;
end if;
-- rendering
if (SE = '0') then
-- reset state machine counters
phase <= 0;
counter <= 0;
-- reset color
if (phase /= 0) then
color <= "111111";
else
color <= "000000";
end if;
else
if (phase = 0) then
-- here we introduce little delay so that next line
-- is drawn in the middle of screen.
color <= "111111";
if (counter < 64) then
counter <= counter + 1;
else
counter <= 0;
phase <= 1;
-- beginning of a new row. Is this the first scanline?
if (Y = x"0000") then
-- first line on screen, reset vertical
V := PPU_CTRL(1);
VT := PPU_VSCR(7 downto 3);
FV := PPU_VSCR(2 downto 0);
elsif (Y(0) = '0') then
if (FV /= "111") then
-- next pixel inside the tile
FV := conv_std_logic_vector(
conv_integer(unsigned(FV))+1,3);
else
-- next tile
FV := "000";
if (VT /= "11101") then
-- next tile inside window
VT := conv_std_logic_vector(
conv_integer(unsigned(VT))+1,5);
else
-- next window
VT := "00000";
V := NOT V;
end if;
end if;
end if;
-- reset horizontal counters
H := PPU_CTRL(0);
HT := PPU_HSCR(7 downto 3);
FH := PPU_HSCR(2 downto 0);
-- pipelining, read patIndex of first pixel
VRAM4Read <= '1';
PatRead <= '1';
VRAM4Addr <= H & VT & HT;
end if;
elsif (phase = 1) then
-- load lowest 2 bits of color
PatAddr1 <= PPU_CTRL(4) & VRAM4Data(7 downto 0) & "0" & FV;
-- load associated attribute
VRAM4Addr <= H & "1111" & VT(4 downto 2) & HT(4 downto 2);
-- early calculation for shifts
bshift := FH;
ashift := VT(1)&HT(1)&"0";
-- prepare next column:
if (FH /= "111") then
-- next pixel inside the tile
FH := conv_std_logic_vector(
conv_integer(unsigned(FH))+1,3);
else
-- next tile
FH := "000";
if (HT /= "11111") then
-- next tile inside window
HT := conv_std_logic_vector(
conv_integer(unsigned(HT))+1,5);
else
-- next window
HT := "00000";
H := NOT H;
end if;
end if;
-- find matching sprite, if any
if (counter >= spr0x and counter < (spr0x+8)) then
sprindx := 0;
elsif (counter >= spr1x and counter < (spr1x+8)) then
sprindx := 1;
elsif (counter >= spr2x and counter < (spr2x+8)) then
sprindx := 2;
elsif (counter >= spr3x and counter < (spr3x+8)) then
sprindx := 3;
elsif (counter >= spr4x and counter < (spr4x+8)) then
sprindx := 4;
elsif (counter >= spr5x and counter < (spr5x+8)) then
sprindx := 5;
elsif (counter >= spr6x and counter < (spr6x+8)) then
sprindx := 6;
elsif (counter >= spr7x and counter < (spr7x+8)) then
sprindx := 7;
else
sprindx := 8;
end if;
-- go to next step
phase <= 2;
elsif (phase = 2) then
-- read tile color
tcolor(0) := PatData( 7-conv_integer(unsigned(bshift)));
tcolor(1) := PatData(15-conv_integer(unsigned(bshift)));
tcolor(2) := VRAM4Data(conv_integer(unsigned(ashift))+0);
tcolor(3) := VRAM4Data(conv_integer(unsigned(ashift))+1);
-- continue sprite evaluation
if (sprindx < 8) then
offset := counter -
conv_integer(unsigned(sprcache(sprindx)(7 downto 0)));
scolor(0) := sprcache(sprindx)(16+offset);
scolor(1) := sprcache(sprindx)(24+offset);
scolor(2) := sprcache(sprindx)(8);
scolor(3) := sprcache(sprindx)(9);
else
scolor := "0000";
end if;
-- output color
if (scolor(0) = '1' or scolor(1) = '1') then
-- sprite
color <= SprPal(conv_integer(unsigned(scolor)));
elsif (tcolor(1) = '0' and tcolor(0) = '0') then
-- background color
color <= PatPal(0);
else
color <= PatPal(conv_integer(unsigned(tcolor)));
end if;
-- load next pat index
VRAM4Addr <= H & VT & HT;
-- move to next state
if (counter < 255) then
counter <= counter + 1;
phase <= 1;
else
phase <= 3;
end if;
elsif (phase = 3) then
phase <= 4;
-- reset sprite cache
n := 0;
m := 0;
sstate := 0;
cur_y := conv_integer(unsigned(Y(9 downto 1)));
spr0x := 255;
spr1x := 255;
spr2x := 255;
spr3x := 255;
spr4x := 255;
spr5x := 255;
spr6x := 255;
spr7x := 255;
sprindex <= 0;
else
VRAM4Read <= '0';
PatRead <= '0';
color <= "111111";
end if;
end if;
end if;
end process;
-- sprite access
process (CLK)
begin
if (CLK = '0' and CLK'event ) then
if (lastSprRD /= SprRD and SprRD='1') then
-- read
SprDataOut <= sprites(conv_integer(unsigned(SprAddr)));
end if;
sprdata <= sprites(sprindex);
if (lastSprWR /= SprWR and SprWR='1') then
-- write
sprites(conv_integer(unsigned(SprAddr))) <= SprDataIn;
end if;
lastSprRD <= SprRD;
lastSprWR <= SprWR;
end if;
end process;
-- palette access
process (CLK)
begin
if (CLK = '0' and CLK'event ) then
if (lastPalRD /= PalRD and PalRD='1') then
-- read
if (PalAddr(4) = '0') then
PalDataOut(5 downto 0) <= PatPal(
conv_integer(unsigned(PalAddr(3 downto 0))));
else
PalDataOut(5 downto 0) <= SprPal(
conv_integer(unsigned(PalAddr(3 downto 0))));
end if;
end if;
if (lastPalWR /= PalWR and PalWR='1') then
-- write
if (PalAddr(4) = '0') then
PatPal(conv_integer(unsigned(PalAddr(3 downto 0))))
<= PalDataIn(5 downto 0);
else
SprPal(conv_integer(unsigned(PalAddr(3 downto 0))))
<= PalDataIn(5 downto 0);
end if;
end if;
lastPalRD <= PalRD;
lastPalWR <= PalWR;
end if;
end process;
end Dataflow;
| gpl-3.0 | cd38d240986e274bd49937c27420f64f | 0.426365 | 4.269257 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_sort_v1_00_a/hdl/vhdl/hw_acc_sort.vhd | 2 | 5,371 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_sort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_sort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_sort is
component mergesort is
port
(
array0_addr0 : out std_logic_vector(0 to (32 - 1));
array0_dIN0 : out std_logic_vector(0 to (32 - 1));
array0_dOUT0 : in std_logic_vector(0 to (32 - 1));
array0_rENA0 : out std_logic;
array0_wENA0 : out std_logic;
array1_addr0 : out std_logic_vector(0 to (32 - 1));
array1_dIN0 : out std_logic_vector(0 to (32 - 1));
array1_dOUT0 : in std_logic_vector(0 to (32 - 1));
array1_rENA0 : out std_logic;
array1_wENA0 : out std_logic;
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal reset_sig : std_logic;
signal in_BRAM_A_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_A_wEN : std_logic;
signal in_BRAM_B_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_B_wEN : std_logic;
signal in_BRAM_C_addr : std_logic_vector(0 to (32 - 1));
signal in_BRAM_C_wEN : std_logic;
-- Architecture Section
begin
reset_sig <= rst or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
BRAM_A_addr <= in_BRAM_A_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_A_wEN <= in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN&in_BRAM_A_WEN;
BRAM_B_addr <= in_BRAM_B_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_B_wEN <= in_BRAM_B_WEN&in_BRAM_B_WEN&in_BRAM_B_WEN&in_BRAM_B_WEN;
BRAM_C_addr <= in_BRAM_C_addr(2 to 31) & "00"; --The external memory is organized in this way.
BRAM_C_wEN <= in_BRAM_C_WEN&in_BRAM_C_WEN&in_BRAM_C_WEN&in_BRAM_C_WEN;
uut : mergesort
port map (
array0_addr0 => in_BRAM_A_addr,
array0_dIN0 => BRAM_A_dout,
array0_dOUT0 => BRAM_A_din,
array0_rENA0 => BRAM_A_en,
array0_wENA0 => in_BRAM_A_wen,
array1_addr0 => in_BRAM_B_addr,
array1_dIN0 => BRAM_B_dout,
array1_dOUT0 => BRAM_B_din,
array1_rENA0 => BRAM_B_en,
array1_wENA0 => in_BRAM_B_wen,
chan1_channelDataIn => FSL0_M_Data,
chan1_channelDataOut => FSL0_S_Data,
chan1_exists => FSL0_S_Exists,
chan1_full => FSL0_M_Full,
chan1_channelRead => FSL0_S_Read,
chan1_channelWrite => FSL0_M_Write,
clock_sig => clk,
reset_sig => reset_sig
);
end architecture implementation;
| bsd-3-clause | aa41de4cf4e8ea1b0d340dc0ba0e2e09 | 0.565816 | 2.917436 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/switch_fab_1.vhd | 1 | 4,026 | ---------------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------------
-- File : switch_fab_1.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 13/08/07
---------------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------------
-- Description :
--!\reqid
--!\upreqid
---------------------------------------------------------------------
--!\hierarchy
--!\endofhierarchy
---------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------
-- History
---------------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: switch_fab_1.vhd,v $
-- Revision 1.4 2015/06/15 16:39:52 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.3 2009/07/29 14:05:11 FLenhardt
-- Fixed bug (WB slave strobe had been activated without addressing)
--
-- Revision 1.2 2007/08/13 17:04:22 FWombacher
-- fixed typos
--
-- Revision 1.1 2007/08/13 16:28:20 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_1 IS
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- wb-bus #0
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
-- wb-bus to slave
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_1;
ARCHITECTURE switch_fab_1_arch OF switch_fab_1 IS
SIGNAL wbi_slave_stb : std_logic;
BEGIN
wbi_slave_cyc <= cyc_0;
wbi_slave.stb <= wbi_slave_stb;
ack_0 <= wbo_slave.ack AND wbi_slave_stb;
err_0 <= wbo_slave.err AND wbi_slave_stb;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave_stb <= '0';
END IF;
END IF;
END PROCESS;
END switch_fab_1_arch;
| gpl-3.0 | 6383defb0e3daea5be135d8d1319d2cf | 0.479384 | 3.950932 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd | 2 | 9,382 | -------------------------------------------------------------------------------
-- $Id: or_gate128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate128.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate128.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate128.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 07/11/05
-- ^^^^^^
-- Adjusted range on C_BUS_WIDTH to support 128 bit dwidths
-- Renamed to or_gate128.vhd
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate128 is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 128 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate128;
architecture imp of or_gate128 is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
| bsd-3-clause | 50775b9397cb122d066cbd8ca97e1a33 | 0.416223 | 4.924934 | false | false | false | false |
jevinskie/aes-over-pcie | source/tb_sbox.vhd | 1 | 1,675 | -- File name: tb_sbox.vhd
-- Created: 2009-02-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: S-Box tester
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_sbox is
generic (
clk_per : time := 4 ns
);
end entity tb_sbox;
architecture test of tb_sbox is
signal clk : std_logic := '0';
signal lut_a, lut_b : byte;
signal data_a, data_b : byte;
signal pipe_a, pipe_b : byte;
signal stop : std_logic := '1';
signal gold : byte;
begin
lut : entity work.sbox(lut) port map (
clk => clk, a => lut_a, b => lut_b
);
data : entity work.sbox(dataflow) port map (
clk => clk, a => data_a, b => data_b
);
pipe : entity work.sbox(pipelined) port map (
clk => clk, a => pipe_a, b => pipe_b
);
-- clock when stop isnt asserted
clk <= not clk and not stop after clk_per/2;
process
begin
for i in 0 to 255 loop
lut_a <= to_unsigned(i, 8);
data_a <= to_unsigned(i, 8);
wait for 10 ns;
gold <= work.aes.sbox(i);
assert lut_b = work.aes.sbox(i);
assert data_b = work.aes.sbox(i);
end loop;
stop <= '0';
for i in 0 to 256 loop
if (i <= 255) then
pipe_a <= to_unsigned(i, 8);
end if;
wait for clk_per;
if (i >= 1) then
gold <= work.aes.sbox(i-1);
assert pipe_b = work.aes.sbox(i-1);
end if;
end loop;
stop <= '1';
wait;
end process;
end architecture test;
| bsd-3-clause | 6f4b967e033543232dd2d580516803da | 0.521791 | 3.221154 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_hthread_reset_core_v1_00_a/hdl/vhdl/axi_hthread_reset_core.vhd | 2 | 20,283 | ------------------------------------------------------------------------------
-- axi_hthread_reset_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_hthread_reset_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Jun 24 19:32:07 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_hthread_reset_core_v1_00_a;
use axi_hthread_reset_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity axi_hthread_reset_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"0000FFFF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_hthread_reset_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_hthread_reset_core is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant RST_NUM_CE : integer := 1;
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG + RST_NUM_CE;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (RST_NUM_CE), -- number of ce for soft reset space
1 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 8;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant RST_CS_INDEX : integer := 0;
constant RST_CE_INDEX : integer := USER_NUM_REG;
constant USER_SLV_CS_INDEX : integer := 1;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Reset : std_logic;
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_hthread_reset_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
reset_port0 => reset_port0,
reset_response_port0 => reset_response_port0,
reset_port1 => reset_port1,
reset_response_port1 => reset_response_port1,
reset_port2 => reset_port2,
reset_response_port2 => reset_response_port2,
reset_port3 => reset_port3,
reset_response_port3 => reset_response_port3,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS (1 downto 0) is
when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "10" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
end IMP;
| bsd-3-clause | 368a4a36838347e76268b675ccbb5859 | 0.458956 | 4.082729 | false | false | false | false |
iocoder/graduation | hardware/vga/dac.vhd | 1 | 3,847 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dac is
Port (DE : in STD_LOGIC;
MODE : in STD_LOGIC;
COLOR : in STD_LOGIC_VECTOR (5 downto 0);
R : out STD_LOGIC_VECTOR (2 downto 0);
G : out STD_LOGIC_VECTOR (2 downto 0);
B : out STD_LOGIC_VECTOR (1 downto 0));
end dac;
architecture Behavioral of dac is
type vga_palette_t is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0);
signal vga_palette : vga_palette_t := (
-- RRRGGGBB
"00000000", -- 0 BLACK
"00000010", -- 1 BLUE
"00010100", -- 2 GREEN
"00010110", -- 3 CYAN
"10100000", -- 4 RED
"10100010", -- 5 VIOLET
"10101000", -- 6 BROWN
"10110110", -- 7 GRAY
"01001001", -- 8 GRAY DARK
"01001011", -- 9 LIGHT BLUE
"01011101", -- A LIGHT GREEN
"01011111", -- B LIGHT CYAN
"11101001", -- C LIGHT RED
"11101011", -- D LIGHT VIOLET
"11111101", -- E YELLOW
"11111111" -- F WHITE
);
type ppu_palette_t is array (0 to 63) of STD_LOGIC_VECTOR (7 downto 0);
signal ppu_palette : ppu_palette_t := (
"01101101",
"00100010",
"00000010",
"01000010",
"10000001",
"10100000",
"10100000",
"01100000",
"01000100",
"00001000",
"00001000",
"00000100",
"00000101",
"00000000",
"00000000",
"00000000",
"10110110",
"00001111",
"00100111",
"10000011",
"10100010",
"11100001",
"11000100",
"11001000",
"10001100",
"00010000",
"00010100",
"00010000",
"00010010",
"00000000",
"00000000",
"00000000",
"11111111",
"00110111",
"01010011",
"11010011",
"11101111",
"11101110",
"11101101",
"11110000",
"11110100",
"10011000",
"01011001",
"01011110",
"00011111",
"01101101",
"00000000",
"00000000",
"11111111",
"10111111",
"11011011",
"11011011",
"11111011",
"11111011",
"11110110",
"11111010",
"11111110",
"11111110",
"10111110",
"10111111",
"10011111",
"11011011",
"00000000",
"00000000"
);
begin
B(0) <= '0' when DE = '0' else
vga_palette(conv_integer(unsigned(COLOR)))(0) when MODE = '0' else
ppu_palette(conv_integer(unsigned(COLOR)))(0);
B(1) <= '0' when DE = '0' else
vga_palette(conv_integer(unsigned(COLOR)))(1) when MODE = '0' else
ppu_palette(conv_integer(unsigned(COLOR)))(1);
G(0) <= '0' when DE = '0' else
vga_palette(conv_integer(unsigned(COLOR)))(2) when MODE = '0' else
ppu_palette(conv_integer(unsigned(COLOR)))(2);
G(1) <= '0' when DE = '0' else
vga_palette(conv_integer(unsigned(COLOR)))(3) when MODE = '0' else
ppu_palette(conv_integer(unsigned(COLOR)))(3);
G(2) <= '0' when DE = '0' else
vga_palette(conv_integer(unsigned(COLOR)))(4) when MODE = '0' else
ppu_palette(conv_integer(unsigned(COLOR)))(4);
R(0) <= '0' when DE = '0' else
vga_palette(conv_integer(unsigned(COLOR)))(5) when MODE = '0' else
ppu_palette(conv_integer(unsigned(COLOR)))(5);
R(1) <= '0' when DE = '0' else
vga_palette(conv_integer(unsigned(COLOR)))(6) when MODE = '0' else
ppu_palette(conv_integer(unsigned(COLOR)))(6);
R(2) <= '0' when DE = '0' else
vga_palette(conv_integer(unsigned(COLOR)))(7) when MODE = '0' else
ppu_palette(conv_integer(unsigned(COLOR)))(7);
end Behavioral;
| gpl-3.0 | 3486f080609f88deae86b3fae490e414 | 0.514947 | 3.619003 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_occ_counter_top.vhd | 3 | 12,665 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- DET 2001-08-30 First Version
--
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_v20_v1_10_d.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
| bsd-3-clause | 57bf5cb9213a55d1e0a07c2ae744916b | 0.433004 | 4.515152 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/family.vhd | 3 | 21,228 | -- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/opb_v20/opb_v20_v1_10_d/hdl/src/vhdl/Attic/family.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
--------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- END_CHANGELOG
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
package family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end family;
package body family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end family;
| bsd-3-clause | 675bbbe155eb9463ef83e3f568057a12 | 0.557236 | 4.623829 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_factorial.vhd | 2 | 17,219 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Factorial
-- Computes the factorial of the inputed number (cast to an int), using
-- a recursive algorithm.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory function
-- intrfc2thrd_value 32 bits memory
-- intrfc2thrd_function 16 bits control
-- thrd2intrfc_goWait 1 bit control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_START,
READ_ARGUMENT,
PUSH_ARGUMENT,
CALL_FACTORIAL,
READ_FACTORIAL_RETURN,
PUSH_RETURN,
CALL_EXIT,
FACTORIAL_1,
FACTORIAL_2,
FACTORIAL_3,
FACTORIAL_4,
FACTORIAL_5,
FACTORIAL_6,
FACTORIAL_7,
FACTORIAL_8,
FACTORIAL_9,
FACTORIAL_END,
ERROR_STATE,
WAIT_STATE );
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_READ_FACTORIAL_RETURN : std_logic_vector(0 to 15) := x"0007";
constant U_FACTORIAL_1 : std_logic_vector(0 to 15) := x"0101";
constant U_FACTORIAL_7 : std_logic_vector(0 to 15) := x"0107";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
-- constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
-- constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
-- constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
-- constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
-- constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
-- constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
-- constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
-- constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
-- constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal argument, argument_next : std_logic_vector(0 to 31);
signal varOne, varOne_next : std_logic_vector(0 to 31);
signal varTwo, varTwo_next : std_logic_vector(0 to 31);
signal result, result_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
argument <= argument_next;
varOne <= varOne_next;
varTwo <= varTwo_next;
result <= result_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_FACTORIAL_1 =>
current_state <= FACTORIAL_1;
when U_READ_FACTORIAL_RETURN =>
current_state <= READ_FACTORIAL_RETURN;
when U_FACTORIAL_7 =>
current_state <= FACTORIAL_7;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
-- next_state <= current_state;
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
argument_next <= argument;
varOne_next <= varOne;
varTwo_next <= varTwo;
result_next <= result;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
result_next <= Z32;
argument_next <= Z32;
varOne_next <= Z32;
varTwo_next <= Z32;
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- Ask the HWTI the value of the passed in argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
return_state_next <= READ_ARGUMENT;
next_state <= WAIT_STATE;
when READ_ARGUMENT => --0004
-- read the value of the passed in argument
argument_next <= toUser_value;
next_state <= PUSH_ARGUMENT;
when PUSH_ARGUMENT => --0005
-- push the argument, for the factorial function, on the stack
thrd2intrfc_value <= argument;
thrd2intrfc_opcode <= OPCODE_PUSH;
return_state_next <= CALL_FACTORIAL;
next_state <= WAIT_STATE;
when CALL_FACTORIAL => -- 0006
-- make a call to the factorial function
thrd2intrfc_function <= U_FACTORIAL_1;
thrd2intrfc_value <= Z32(0 to 15) & U_READ_FACTORIAL_RETURN;
thrd2intrfc_opcode <= OPCODE_CALL;
return_state_next <= READ_FACTORIAL_RETURN;
next_state <= WAIT_STATE;
when READ_FACTORIAL_RETURN => -- 0007
-- read the return value
result_next <= toUser_value;
next_state <= PUSH_RETURN;
when PUSH_RETURN => -- 0008
-- Push a return value
thrd2intrfc_value <= result;
thrd2intrfc_opcode <= OPCODE_PUSH;
return_state_next <= CALL_EXIT;
next_state <= WAIT_STATE;
when CALL_EXIT => -- 000A
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when ERROR_STATE =>
next_state <= ERROR_STATE;
-----------------------------------------------------------------------
-- Factorial function
-- computes the factorial of the input parameter using recursion
-----------------------------------------------------------------------
when FACTORIAL_1 => -- 0101
-- Read the passed in parameter
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
return_state_next <= FACTORIAL_2;
next_state <= WAIT_STATE;
when FACTORIAL_2 => -- 0102
-- store the passed in parameter in a register
varOne_next <= intrfc2thrd_value;
next_state <= FACTORIAL_3;
when FACTORIAL_3 => -- 0103
-- Declare one variable
thrd2intrfc_value <= x"00000001";
thrd2intrfc_opcode <= OPCODE_DECLARE;
return_state_next <= FACTORIAL_4;
next_state <= WAIT_STATE;
when FACTORIAL_4 => -- 0104
-- store the register as a saved variable
thrd2intrfc_value <= varOne;
thrd2intrfc_address <= Z32;
thrd2intrfc_opcode <= OPCODE_WRITE;
return_state_next <= FACTORIAL_5;
next_state <= WAIT_STATE;
when FACTORIAL_5 => -- 0105
-- check if param <= 1
case varOne is
when x"00000001" =>
-- return a 1
thrd2intrfc_value <= x"00000001";
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when Z32 =>
-- return a 1
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when others =>
-- recursively call factorial, prepare by pushing param-1
thrd2intrfc_value <= (varOne - 1);
thrd2intrfc_opcode <= OPCODE_PUSH;
return_state_next <= FACTORIAL_6;
next_state <= WAIT_STATE;
end case;
when FACTORIAL_6 => -- 0106
-- recursively call factorial
thrd2intrfc_value <= Z32(0 to 15) & U_FACTORIAL_7;
thrd2intrfc_function <= U_FACTORIAL_1;
thrd2intrfc_opcode <= OPCODE_CALL;
return_state_next <= FACTORIAL_7;
next_state <= WAIT_STATE;
when FACTORIAL_7 => -- 0107
-- read the return value, save to a register
-- TODO, change this to multipliation
varTwo_next <= toUser_value;
-- read the save variable
thrd2intrfc_address <= Z32;
thrd2intrfc_opcode <= OPCODE_READ;
return_state_next <= FACTORIAL_8;
next_state <= WAIT_STATE;
when FACTORIAL_8 => -- 0108
-- store the variable back to varOne
varOne_next <= toUser_value;
next_state <= FACTORIAL_9;
when FACTORIAL_9 => -- 0109
-- return
thrd2intrfc_value <= varTwo + varOne;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= FACTORIAL_END;
when FACTORIAL_END => -- 010A
-- if everything is working, should never reach this state
next_state <= FACTORIAL_END;
when WAIT_STATE =>
next_state <= return_state;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | f872b0c07e442350fa5c28610fa0986b | 0.574656 | 4.229673 | false | false | false | false |
myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/simulation/FiFo512Core32W32R_synth.vhd | 1 | 11,563 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.FiFo512Core32W32R_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY FiFo512Core32W32R_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF FiFo512Core32W32R_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: FiFo512Core32W32R_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: FiFo512Core32W32R_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: FiFo512Core32W32R_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
FiFo512Core32W32R_inst : FiFo512Core32W32R_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | 0b8c31a76c716c9d1683dd4690d710c3 | 0.448845 | 3.966724 | false | false | false | false |
jevinskie/aes-over-pcie | source/tb_aes_rcu.vhd | 1 | 2,425 | -- File name: tb_aes_rcu.vhd
-- Created: 4/4/2009
-- Author: Zachary Curosh
-- Lab Section: 337-02
-- Version: 1.0 Initial Test Bench
use work.aes.all;
library ieee;
--library gold_lib; --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all; --UNCOMMENT if you're using a GOLD model
entity tb_aes_rcu is
generic (clk_per : time := 4 ns);
end tb_aes_rcu ;
architecture TEST of tb_aes_rcu is
-- Insert signals Declarations here
signal clk : std_logic := '0';
signal nrst : std_logic;
signal p : g_index;
signal subblock : subblock_type;
signal encryption_key : key_type;
signal stop : std_logic := '1';
signal sbox_lookup, sbox_return : byte;
signal round_key : key_type;
signal start_key : std_logic;
signal key_done : std_logic;
signal go : std_logic;
signal done: std_logic;
signal current_round: round_type;
begin
behavioral: entity work.aes_rcu (behavioral) port map(
clk => clk,
nrst => nrst,
p => p,
subblock => subblock,
start_key => start_key,
key_done => done,
current_round => current_round,
got_pt => open,
got_key => open
);
keysched: entity work.key_scheduler(behavioral) port map(
clk => clk,
nrst => nrst,
sbox_lookup=>sbox_lookup,
sbox_return=>sbox_return,
round => current_round,
key_load,
round_key => round_key,
go => start_key,
done => done
);
data : entity work.sbox(dataflow) port map (
clk => clk, a => sbox_lookup, b => sbox_return
);
-- GOLD: <GOLD_NAME> port map(<put mappings here>);
-- clock when stop isnt asserted
clk <= not clk and not stop after clk_per/2;
process
begin
encryption_key <= ((x"00", x"00", x"00", x"00"), (x"00", x"00",
x"00", x"00"), (x"00", x"00", x"00", x"00"),
(x"00", x"00", x"00", x"00"));
-- start the clock
stop <= '0';
nrst <= '0';
wait for clk_per*4;
nrst <= '1';
wait for clk_per*2;
wait for clk_per*3000;
-- stop the clock
stop <= '1';
wait;
end process;
end TEST;
| bsd-3-clause | 8e879a4882dd7178438188b85e0d4f41 | 0.515052 | 3.608631 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zcpsmDecode.vhd | 1 | 1,048 | library ieee;
use ieee.std_logic_1164.all;
entity zcpsmDecode is
port (
port_id_H : in std_logic_vector(3 downto 0);
ce : out std_logic_vector(15 downto 0)
);
end zcpsmDecode;
architecture behave of zcpsmDecode is
begin
decode : process( port_id_H )
begin
case port_id_H is
when X"0" => ce <= X"0001";
when X"1" => ce <= X"0002";
when X"2" => ce <= X"0004";
when X"3" => ce <= X"0008";
when X"4" => ce <= X"0010";
when X"5" => ce <= X"0020";
when X"6" => ce <= X"0040";
when X"7" => ce <= X"0080";
when X"8" => ce <= X"0100";
when X"9" => ce <= X"0200";
when X"A" => ce <= X"0400";
when X"B" => ce <= X"0800";
when X"C" => ce <= X"1000";
when X"D" => ce <= X"2000";
when X"E" => ce <= X"4000";
when X"F" => ce <= X"8000";
when others => ce <= X"0000";
end case;
end process;
end behave; | gpl-2.0 | e572e1a50693d399e42a006133812c30 | 0.435115 | 3.119048 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/wbmon64.vhd | 1 | 25,437 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : wbmon64.vhd
-- Author : Michael Ernst
-- Email :
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 21/09/04
---------------------------------------------------------------
-- Simulator : Modelsim Altera 5.8g
-- Synthesis : --
---------------------------------------------------------------
-- Description : This Wishbone Monitor asserts that all signals
-- and transaction on a wishbone bus are handled
-- correct. It outputs errors on std_out and the
-- rest into a file
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- Version| Author | Mod. Date | Changes Made:
-- v0.1 | Ernst | 21/09/04 | first code
--
-- $Revision: 1.5 $
--
-- $Log: wbmon64.vhd,v $
-- Revision 1.5 2015/06/15 16:40:06 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Removed bte signals from wishbone monitor
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.4 2010/03/01 09:28:36 SKrieger
-- R: Evaluation of master outputs / slave inputs should be done when stb and cyc are both different from '0'.
-- M: Changed accordingly
--
-- Revision 1.3 2009/09/30 07:14:35 mmiehling
-- added cti=011 support
--
-- Revision 1.2 2008/12/08 09:30:30 mmiehling
-- added unaligned read burst support
--
-- Revision 1.1 2008/10/08 17:25:49 mmiehling
-- Initial Revision
--
-- Revision 1.1 2008/09/16 09:33:52 mmiehling
-- Initial Revision
--
-- Revision 1.5 2008/07/04 11:25:09 mernst
-- - Added enable signal for simulation (use signal_force to deactivate output temporarily)
-- - Data lines are only checked while they have to be valid now
--
-- Revision 1.4 2007/11/20 11:55:46 FWombacher
-- Cosmetics: Removed obsoltete address decoding
--
-- Revision 1.3 2005/09/15 08:18:17 flenhardt
-- Fixed bug in error indication
--
-- Revision 1.2 2005/04/29 08:23:05 MMiehling
-- added reset values
--
-- Revision 1.1 2005/02/07 13:09:30 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
--
--Errorcoding:
--
-- 0x00
-- Acknowledge without Strobe or cycle:
-- an Acknowledge was given by the module alltough the module was not
-- addressed with strobe or cycle
--
-- 0x01
-- Address changed during transaction!
-- The address changed during a normal cycle or within a burst cycle
-- Not if it happens in a burst cycle it only asserts inside a single
-- transaction of the burst, address increment is handled in error 0x09
--
-- 0x02
-- Data in of slave changed during transaction!
-- data in of the slave changed during a write cycle
--
-- 0x03
-- Select Bits changed during transaction!
--
-- 0x04
-- CTI changed during transaction!
--
-- 0x05
-- Burst with not allowed cti:
-- in the current wishbone specification only cti of 000,010,111 are defined
--
-- 0x07
-- WE changed during burst!
--
-- 0x08
-- SEL changed during burst!
--
-- 0x09
-- wrong address increment or address changed during burst cycle:
-- the address has to increment by 4 in burst mode
--
-- 0x0a
-- Missing End Of Burst:
-- the end of a burst has to be shown by setting cti to 111 in the last
-- burst cycle. This signal is missing here
--
-- 0x0b
-- We changed during transaction!
--
-- 0x0c
-- Sel changed during transaction!
--
-- 0x0d
-- Strobe went low without acknowledge:
-- no acknowledge was given by the module but strobe was reset to 0
--
-- 0x0e
-- U Z X in statement
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
USE std.textio.all;
USE ieee.std_logic_textio.all;
-- synthesis translate_on
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY wbmon64 IS
GENERIC(
wbname : string := "wbmon";
-- Output Settings
sets : std_logic_vector(3 DOWNTO 0) := "1110";
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout : integer := 100
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
adr : IN std_logic_vector(31 DOWNTO 0);
sldat_i : IN std_logic_vector(63 DOWNTO 0);
sldat_o : IN std_logic_vector(63 DOWNTO 0);
cti : IN std_logic_vector(2 DOWNTO 0);
sel : IN std_logic_vector(7 DOWNTO 0);
cyc : IN std_logic;
stb : IN std_logic;
ack : IN std_logic;
err : IN std_logic;
we : IN std_logic;
er : OUT std_logic;
co : OUT std_logic_vector(7 DOWNTO 0)
);
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
);
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(63 DOWNTO 0);
ende : string := "OK"
);
END wbmon64;
ARCHITECTURE wbmon64_arch OF wbmon64 IS
function to_string
(
constant val : in std_logic_vector
) return string is
constant reglen : INTEGER := val'LENGTH;
variable result_str : string(1 to reglen);
variable slv : std_logic_vector(1 to reglen) := val;
begin
for i in reglen downto 1 loop
case slv(i) is
when 'U' => result_str(i) := 'U';
when 'X' => result_str(i) := 'X';
when '0' => result_str(i) := '0';
when '1' => result_str(i) := '1';
when 'Z' => result_str(i) := 'Z';
when 'W' => result_str(i) := 'W';
when 'L' => result_str(i) := 'L';
when 'H' => result_str(i) := 'H';
when '-' => result_str(i) := '-';
when others => -- an unknown std_logic value was passed
assert false
report "to_string -- unknown std_logic_vector value"
severity error;
end case;
end loop;
return result_str;
end;
FUNCTION to_hstring
(
CONSTANT val : in std_logic_vector(31 DOWNTO 0)
) RETURN string is
CONSTANT reglen : natural := 7;
VARIABLE result_str : string(1 to reglen + 1);
VARIABLE slv : std_logic_vector(31 DOWNTO 0) := val;
VARIABLE temp : std_logic_vector(3 DOWNTO 0);
BEGIN
FOR i in reglen DOWNTO 0 LOOP
temp := slv(i*4 + 3 DOWNTO (i *4));
CASE temp IS
WHEN "0000" => result_str(8 - i) := '0';
WHEN "0001" => result_str(8 - i) := '1';
WHEN "0010" => result_str(8 - i) := '2';
WHEN "0011" => result_str(8 - i) := '3';
WHEN "0100" => result_str(8 - i) := '4';
WHEN "0101" => result_str(8 - i) := '5';
WHEN "0110" => result_str(8 - i) := '6';
WHEN "0111" => result_str(8 - i) := '7';
WHEN "1000" => result_str(8 - i) := '8';
WHEN "1001" => result_str(8 - i) := '9';
WHEN "1010" => result_str(8 - i) := 'a';
WHEN "1011" => result_str(8 - i) := 'b';
WHEN "1100" => result_str(8 - i) := 'c';
WHEN "1101" => result_str(8 - i) := 'd';
WHEN "1110" => result_str(8 - i) := 'e';
WHEN "1111" => result_str(8 - i) := 'f';
WHEN others => result_str(8 - i) := ' ';
-- an unknown std_logic value was passed
END CASE;
END LOOP;
RETURN result_str;
END;
FUNCTION to_hstring64
(
CONSTANT val : in std_logic_vector(63 DOWNTO 0)
) RETURN string is
VARIABLE temp : string (1 TO 16);
BEGIN
temp := to_hstring(val(63 DOWNTO 32))&to_hstring(val(31 DOWNTO 0));
RETURN temp;
END;
PROCEDURE outp(
VARIABLE e : OUT std_logic;
VARIABLE c : OUT std_logic_vector(7 DOWNTO 0);
message : string := "Unknown Error";
code : std_logic_vector(7 DOWNTO 0):= x"FF";
enable : std_logic;
sev : severity_level := NOTE;
condition : boolean := FALSE
)
IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
VARIABLE ol : line;
-- synthesis translate_on
BEGIN
IF NOT(condition) AND enable = '1' THEN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " 0x");
hwrite(wl, code);
WRITELINE(Output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
IF (sev = ERROR) THEN
e := '1';
c := code;
END IF;
END IF;
END;
PROCEDURE outp_cycle(
message : string := "Not Defined";
sev : severity_level := NOTE;
adr : std_logic_vector(31 DOWNTO 0);
data : std_logic_vector(63 DOWNTO 0);
ende : string := "OK"
) IS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Append_Mode
IS wbname & "_transcript.txt"; -- Write- File
VARIABLE wl : line;
-- synthesis translate_on
BEGIN
-- synthesis translate_off
IF (sets(0) = '1' AND sev = NOTE) OR (sets(1) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" DATA: "));
IF sel(7) = '1' THEN
hwrite(wl,data(63 DOWNTO 56));
END IF;
IF sel(6) = '1' THEN
hwrite(wl,data(55 DOWNTO 48));
END IF;
IF sel(5) = '1' THEN
hwrite(wl,data(47 DOWNTO 40));
END IF;
IF sel(4) = '1' THEN
hwrite(wl,data(39 DOWNTO 32));
END IF;
IF sel(3) = '1' THEN
hwrite(wl,data(31 DOWNTO 24));
END IF;
IF sel(2) = '1' THEN
hwrite(wl,data(23 DOWNTO 16));
END IF;
IF sel(1) = '1' THEN
hwrite(wl,data(15 DOWNTO 8));
END IF;
IF sel(0) = '1' THEN
hwrite(wl,data(7 DOWNTO 0));
END IF;
write(wl,string'(" SEL: "));
hwrite(wl, sel);
-- Output ende
WRITE(wl, ende);
WRITELINE(output, wl);
END IF;
IF (sets(2) = '1' AND sev = NOTE) OR (sets(3) = '1' AND sev = ERROR) THEN
-- Output Notes to Modelsim
WRITE(wl, wbname & ": (" & severity_level'image(sev) & ") (");
WRITE(wl,now, justified=>right,field =>10, unit=> ns );
WRITE(wl, ") " & message & " ADR: ");
-- Output Data
hwrite(wl, adr, justified=> left);
write(wl,string'(" DATA: "));
IF sel(7) = '1' THEN
hwrite(wl,data(63 DOWNTO 56));
END IF;
IF sel(6) = '1' THEN
hwrite(wl,data(55 DOWNTO 48));
END IF;
IF sel(5) = '1' THEN
hwrite(wl,data(47 DOWNTO 40));
END IF;
IF sel(4) = '1' THEN
hwrite(wl,data(39 DOWNTO 32));
END IF;
IF sel(3) = '1' THEN
hwrite(wl,data(31 DOWNTO 24));
END IF;
IF sel(2) = '1' THEN
hwrite(wl,data(23 DOWNTO 16));
END IF;
IF sel(1) = '1' THEN
hwrite(wl,data(15 DOWNTO 8));
END IF;
IF sel(0) = '1' THEN
hwrite(wl,data(7 DOWNTO 0));
END IF;
write(wl,string'(" SEL: "));
hwrite(wl, sel);
-- Output ende
WRITE(wl, ende);
WRITELINE(DataOut, wl);
END IF;
-- synthesis translate_on
END;
-- SIGNALS
-- synthesis translate_off
FILE DataOut: TEXT OPEN Write_Mode
IS wbname & "_transcript.txt"; -- Write- File
-- synthesis translate_on
TYPE wb_state_type IS (IDLE, CYCLE, BURST);
SIGNAL wb_state : wb_state_type;
SIGNAL adr_s : std_logic_vector(31 DOWNTO 0);
SIGNAL sldat_i_s : std_logic_vector(63 DOWNTO 0);
SIGNAL we_s : std_logic;
SIGNAL cti_s : std_logic_vector(2 DOWNTO 0);
SIGNAL sel_s : std_logic_vector (7 DOWNTO 0);
SIGNAL cti_b : std_logic_vector(2 DOWNTO 0);
SIGNAL sldat_i_b : std_logic_vector(63 DOWNTO 0);
SIGNAL new_b : std_logic;
SIGNAL enable : std_logic;
BEGIN
enable <= '1';
-- synthesis translate_off
PROCESS(clk)
VARIABLE burst : string (1 TO 5);
BEGIN
IF rising_edge(clk) THEN
IF (cti /= "000") THEN
burst := "Burst";
ELSE
burst := " ";
END IF;
IF (ack = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> OK");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> OK");
END IF;
END IF;
IF (err = '1' AND stb = '1' AND cyc = '1') THEN
-- Output write or read actions
IF (we = '1') THEN
outp_cycle("Write Cycle " & burst, NOTE, adr, sldat_i, " --> ERROR");
ELSE
outp_cycle("Read Cycle " & burst, NOTE, adr, sldat_o, " --> ERROR");
END IF;
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
-- Create Cycle start time
PROCESS(clk)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF (rst = '1') THEN
sel_s <= (OTHERS => '0');
adr_s <= (OTHERS => '0');
sldat_i_s <= (OTHERS => '0');
sldat_i_b <= (OTHERS => '0');
we_s <= '0';
new_b <= '0';
e := '0';
c := (OTHERS => '0');
er <= '0';
co <= (OTHERS => '0');
cti_b <= (OTHERS => '0');
cti_s <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
CASE wb_state IS
WHEN IDLE =>
IF (stb = '1' AND cyc = '1') THEN
IF (cti = "111" OR cti = "000") THEN
-- Normal Cycle SAVE DATA
wb_state <= CYCLE;
cti_s <= cti;
adr_s <= adr;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "010") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' THEN
adr_s <= adr + 8;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSIF (cti = "011") THEN
-- Burst cycle SAVE DATA
wb_state <= BURST;
new_b <= '1';
cti_b <= cti;
sldat_i_b <= sldat_i;
IF ack = '1' AND adr(4 DOWNTO 3) = "11" THEN
adr_s <= adr - 24;
ELSIF ack = '1' THEN
adr_s <= adr + 8;
ELSE
adr_s <= adr;
END IF;
we_s <= we;
sel_s <= sel;
sldat_i_s <= sldat_i;
ELSE
outp(e,c,"Unsupported CTI " & to_string(cti),x"05", enable , ERROR);
END IF;
IF ack = '1' THEN
IF cti /= "010" AND cti /= "011" THEN
-- stay in idle if single cycle with acknowledge
wb_state <= IDLE;
END IF;
END IF;
ELSE
IF ack = '1' THEN
outp(e,c,"acknowledge without cycle and/or strobe",x"00", enable , ERROR);
END IF;
END IF;
WHEN BURST =>
IF (cti /= "010" AND cti /= "011" AND cti /="111") THEN
-- ERROR missing End of burst
outp(e,c,"Missing end of burst", x"0a", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
-- CHECK SIGNALS which can change after ack
IF (new_b = '1') THEN
cti_b <= cti;
sldat_i_b <= sldat_i;
new_b <= '0';
ELSE
outp(e,c,"CTI changed during burst cycle ("&to_string(cti)&" sb "&to_string(cti_b)&")", x"04", enable , ERROR, cti = cti_b);
outp(e,c,
"Master Data Out changed during burst cycle (0x"&to_hstring64(sldat_i)&" sb 0x"&to_hstring64(sldat_i_b)&")",
x"02",
enable ,
ERROR,
sldat_i = sldat_i_b OR we = '0');
END IF;
IF (ack = '1' AND cti = "111") THEN
-- End of Burst
wb_state <= IDLE;
ELSIF (ack = '1' AND (cti = "011" OR cti_b = "011") AND adr_s(4 DOWNTO 3) = "11") THEN
-- Addrress Increment on acknowledge for unaligned burst
adr_s <= adr_s - 24;
new_b <= '1';
wb_state <= BURST;
ELSIF (ack = '1') THEN
-- Addrress Increment on acknowledge
adr_s <= adr_s + 8;
new_b <= '1';
wb_state <= BURST;
END IF;
-- CHECK SIGNALS:
-- we has to stay the same throughout the burst
outp(e,c,"We changed during burst (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"07", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during burst (0x"&to_hstring(adr)&" sb 0x"&to_hstring(adr_s)&")", x"09", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during burst ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"08", enable , ERROR, sel = sel_s);
WHEN CYCLE =>
IF (stb = '0') THEN
outp(e,c,"Strobe went low without Acknowledge ", x"0d", enable , ERROR);
wb_state <= IDLE;
END IF;
IF (ack = '1') THEN
wb_state <= IDLE;
END IF;
-- we has to stay the same throughout the burst
outp(e,c,"We changed during cycle (" & std_logic'image(we) & " sb " & std_logic'image(we_s) & ")", x"0b", enable , ERROR, we = we_s);
-- adr has to be adr_s which is inremented automatically
outp(e,c,"Adr changed or increment wrong during cycle (0x"&to_hstring(adr)&" sb 0x"&to_hstring(adr_s)&")", x"01", enable , ERROR, adr = adr_s);
-- sel has to stay the same
outp(e,c,"Sel changed during cycle ("&to_string(sel)&" sb "&to_string(sel_s)&")", x"0c", enable , ERROR, sel = sel_s);
outp(e,c,"CTI changed during cycle ("&to_string(cti)&" sb "&to_string(cti_s)&")", x"04", enable , ERROR, cti = cti_s);
outp(e,c,"Master Data Out changed during cycle (0x"&to_hstring64(sldat_i)&" sb 0x"&to_hstring64(sldat_i_s)&")", x"02", enable , ERROR, sldat_i = sldat_i_s OR we = '0');
WHEN OTHERS =>
ASSERT FALSE REPORT "AHH OHHHHHHH" SEVERITY failure;
END CASE;
co <= c;
er <= e;
END IF;
END PROCESS;
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS( clk, rst, cyc, stb, we, ack, err, cti, adr, sldat_i, sldat_o)
VARIABLE c : std_logic_vector(7 DOWNTO 0);
VARIABLE e : std_logic;
BEGIN
IF(NOT (NOW = 0 ps)) THEN
IF (rst = '0' OR rst = 'U') AND (cyc = 'U' OR cyc = 'Z' OR cyc = 'X') THEN
outp(e,c,"cyc is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (clk = 'U' OR clk = 'Z' OR clk = 'X') THEN
outp(e,c,"clk is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (stb = 'U' OR stb = 'Z' OR stb = 'X') THEN
outp(e,c,"stb is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (we = 'U' OR we = 'Z' OR we = 'X') AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"we is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (ack = 'U' OR ack = 'Z' OR ack = 'X') THEN
outp(e,c,"ack is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND (err = 'U' OR err = 'Z' OR err = 'X') THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sel) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"err is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(cti) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"cti is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(adr) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"adr is 'U', 'Z' or 'X'", x"0e", enable , ERROR);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_i) AND cyc /= '0' AND stb /= '0' THEN
outp(e,c,"data_in is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
IF (rst = '0' OR rst = 'U') AND is_x(sldat_o) AND ack /= '0' THEN
outp(e,c,"data_o is 'U', 'Z' or 'X'", x"0e", enable, error);
END IF;
END IF;
END PROCESS;
-- synthesis translate_on
END wbmon64_arch; | gpl-3.0 | 7e32a9f3d094e41aa4f6aa0d7e32cb58 | 0.460314 | 3.807364 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/opb_SynchManager_v1_00_c/hdl/vhdl/slave.vhd | 2 | 27,541 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RNW : in std_logic;
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
Bus2IP_ArData : in std_logic_vector(0 to C_MAX_AR_DWIDTH-1);
Bus2IP_ArBE : in std_logic_vector(0 to C_MAX_AR_DWIDTH/8-1);
Bus2IP_ArCS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
IP2Bus_ArData : out std_logic_vector(0 to C_MAX_AR_DWIDTH-1);
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_ArCS(0);
alias unlock_start : std_logic is Bus2IP_ArCS(1);
alias trylock_start : std_logic is Bus2IP_ArCS(2);
alias owner_start : std_logic is Bus2IP_ArCS(3);
alias kind_start : std_logic is Bus2IP_ArCS(4);
alias count_start : std_logic is Bus2IP_ArCS(5);
alias result_start : std_logic is Bus2IP_ArCS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_ToutSup <= '1'; -- Never suppress the time out
IP2Bus_Retry <= '0'; -- Never cause a retry operation
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
IP2Bus_RdAck <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_ArData <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
| bsd-3-clause | 7f97de4ab256f107eb2892820d69f023 | 0.513961 | 4.084384 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/user_logic_tb.vhd | 9 | 6,785 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:59:18 06/17/2009
-- Design Name:
-- Module Name: /home/jagron/uark_research/uark_ht_trunk/src/hardware/MyRepository/pcores/plb_cond_vars_v1_00_a/hdl/vhdl//user_logic_tb.vhd
-- Project Name: ise_proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: user_logic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY user_logic_tb IS
END user_logic_tb;
ARCHITECTURE behavior OF user_logic_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT user_logic
PORT(
Soft_Reset : IN std_logic;
Reset_Done : OUT std_logic;
Bus2IP_Clk : IN std_logic;
Bus2IP_Reset : IN std_logic;
Bus2IP_Addr : IN std_logic_vector(0 to 31);
Bus2IP_Data : IN std_logic_vector(0 to 31);
Bus2IP_BE : IN std_logic_vector(0 to 3);
Bus2IP_RdCE : IN std_logic_vector(0 to 4);
Bus2IP_WrCE : IN std_logic_vector(0 to 4);
IP2Bus_Data : OUT std_logic_vector(0 to 31);
IP2Bus_RdAck : OUT std_logic;
IP2Bus_WrAck : OUT std_logic;
IP2Bus_Error : OUT std_logic;
IP2Bus_MstRd_Req : OUT std_logic;
IP2Bus_MstWr_Req : OUT std_logic;
IP2Bus_Mst_Addr : OUT std_logic_vector(0 to 31);
IP2Bus_Mst_BE : OUT std_logic_vector(0 to 3);
IP2Bus_Mst_Lock : OUT std_logic;
IP2Bus_Mst_Reset : OUT std_logic;
Bus2IP_Mst_CmdAck : IN std_logic;
Bus2IP_Mst_Cmplt : IN std_logic;
Bus2IP_Mst_Error : IN std_logic;
Bus2IP_Mst_Rearbitrate : IN std_logic;
Bus2IP_Mst_Cmd_Timeout : IN std_logic;
Bus2IP_MstRd_d : IN std_logic_vector(0 to 31);
Bus2IP_MstRd_src_rdy_n : IN std_logic;
IP2Bus_MstWr_d : OUT std_logic_vector(0 to 31);
Bus2IP_MstWr_dst_rdy_n : IN std_logic
);
END COMPONENT;
--Inputs
signal Soft_Reset : std_logic := '0';
signal Bus2IP_Clk : std_logic := '0';
signal Bus2IP_Reset : std_logic := '0';
signal Bus2IP_Addr : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_Data : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_BE : std_logic_vector(0 to 3) := (others => '0');
signal Bus2IP_RdCE : std_logic_vector(0 to 4) := (others => '0');
signal Bus2IP_WrCE : std_logic_vector(0 to 4) := (others => '0');
signal Bus2IP_Mst_CmdAck : std_logic := '0';
signal Bus2IP_Mst_Cmplt : std_logic := '0';
signal Bus2IP_Mst_Error : std_logic := '0';
signal Bus2IP_Mst_Rearbitrate : std_logic := '0';
signal Bus2IP_Mst_Cmd_Timeout : std_logic := '0';
signal Bus2IP_MstRd_d : std_logic_vector(0 to 31) := (others => '0');
signal Bus2IP_MstRd_src_rdy_n : std_logic := '0';
signal Bus2IP_MstWr_dst_rdy_n : std_logic := '0';
--Outputs
signal Reset_Done : std_logic;
signal IP2Bus_Data : std_logic_vector(0 to 31);
signal IP2Bus_RdAck : std_logic;
signal IP2Bus_WrAck : std_logic;
signal IP2Bus_Error : std_logic;
signal IP2Bus_MstRd_Req : std_logic;
signal IP2Bus_MstWr_Req : std_logic;
signal IP2Bus_Mst_Addr : std_logic_vector(0 to 31);
signal IP2Bus_Mst_BE : std_logic_vector(0 to 3);
signal IP2Bus_Mst_Lock : std_logic;
signal IP2Bus_Mst_Reset : std_logic;
signal IP2Bus_MstWr_d : std_logic_vector(0 to 31);
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: user_logic PORT MAP (
Soft_Reset => Soft_Reset,
Reset_Done => Reset_Done,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n
);
Bus2IP_Clk_process :process
begin
Bus2IP_Clk <= '0';
wait for clock_period/2;
Bus2IP_Clk <= '1';
wait for clock_period/2;
end process;
ACK_proc : process
begin
wait until IP2Bus_MstRd_Req = '1';
Bus2IP_Mst_Cmplt <= '1';
Bus2IP_Mst_CmdAck <= '1';
wait until IP2Bus_MstRd_Req = '0';
Bus2IP_Mst_Cmplt <= '0';
Bus2IP_Mst_CmdAck <= '0';
wait for 5*clock_period;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clock_period*10;
-- Reset the core
Soft_Reset <= '1';
wait until Reset_Done = '1';
wait for clock_period*5;
Soft_Reset <= '0';
wait for 5*clock_period;
-- Perform an ENQ
Bus2IP_Addr <= x"11140100";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Perform an ENQ
Bus2IP_Addr <= x"11140300";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
-- Perform a DEQ-ALL
Bus2IP_Addr <= x"11160000";
Bus2IP_RdCE <= (others => '1');
wait until IP2Bus_RdAck = '1';
Bus2IP_Addr <= (others => '0');
Bus2IP_RdCE <= (others => '0');
wait for 10*clock_period;
wait;
end process;
END;
| bsd-3-clause | d08cde1decf2bd55c313d87a6fd47f8e | 0.594252 | 2.941049 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/address_decoder.vhd | 3 | 24,702 | -------------------------------------------------------------------------------
-- $Id: address_decoder.vhd,v 1.3 2003/05/19 05:19:19 ostlerf Exp $
-------------------------------------------------------------------------------
-- address_decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
--
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification, target data bus size, and ce number.
--
-------------------------------------------------------------------------------
--
-- -- address_decoder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
-- DET 02-12-2002 -- First version
--
--
-- FLO 03-11-2002 -- Modified for use with OPB IPIF
--
-- ToDo List
-- (1) Disable CE, CS if the byte-enable pattern doesn't match the size, or
-- alternatively, generate an error.
--
--
-- FLO 05/16/2003
-- ^^^^^^
-- Fixed pselect component declaration with generic C_BAR as a constrained
-- array. The pselect instance was being tied to the pselect entity with
-- C_BAR declared as an unconstrained array. ModelSim 7.2b detected
-- this error but earlier ModelSims, Synplify and XST allow it.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_unsigned.CONV_INTEGER; --Used in byte count compare 2 MA2SA_Num
--use ieee.std_logic_arith.conv_std_logic_vector;
library Unisim;
use Unisim.vcomponents.all;
--use Unisim.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
use proc_common_v1_00_b.pselect;
--use proc_common_v1_00_b.or_gate;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : Integer := 32;
C_USE_REG_OUTPUTS : Boolean := true;
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
-- := (
-- X"1000_0000", -- IP user0 base address
-- X"1000_01FF", -- IP user0 high address
-- X"1000_0200", -- IP user1 base address
-- X"1000_02FF", -- IP user1 high address
-- X"1000_2000", -- IP user2 base address
-- X"1000_20FF", -- IP user2 high address
-- X"1000_2100", -- IPIF Interrupt base address
-- X"1000_21ff", -- IPIF Interrupt high address
-- X"1000_2200", -- IPIF Reset base address
-- X"1000_22FF", -- IPIF Reset high address
-- X"1000_2300", -- IPIF WrFIFO Registers base address
-- X"1000_23FF", -- IPIF WrFIFO Registers high address
-- X"7000_0000", -- IPIF WrFIFO Data base address
-- X"7000_00FF", -- IPIF WrFIFO Data high address
-- X"8000_0000", -- IPIF RdFIFO Registers base address
-- X"8FFF_FFFF", -- IPIF RdFIFO Registers high address
-- X"9000_0000", -- IPIF RdFIFO Data base address
-- X"9FFF_FFFF" -- IPIF RdFIFO Data high address
-- )
;
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
-- := (
-- 64 , -- User0 data width
-- 64 , -- User1 data width
-- 64 , -- User2 data width
-- 32 , -- IPIF Interrupt data width
-- 32 , -- IPIF Reset data width
-- 32 , -- IPIF WrFIFO Registers data width
-- 64 , -- IPIF WrFIFO Data data width
-- 32 , -- IPIF RdFIFO Registers data width
-- 64 -- IPIF RdFIFO Data width
-- )
;
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
-- := (
-- 8, -- User0 CE Number
-- 1, -- User1 CE Number
-- 1, -- User2 CE Number
-- 16, -- IPIF Interrupt CE Number
-- 1, -- IPIF Reset CE Number
-- 2, -- IPIF WrFIFO Registers CE Number
-- 1, -- IPIF WrFIFO Data data CE Number
-- 2, -- IPIF RdFIFO Registers CE Number
-- 1 -- IPIF RdFIFO Data CE Number
-- )
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
Address_In : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid : In std_logic;
Bus_RNW : In std_logic;
IP2Bus_RdAck_mx : In std_logic;
IP2Bus_WrAck_mx : In std_logic;
Bus2IP_Burst : In std_logic;
Addr_Match : Out std_logic;
CS_Out : Out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
CS_Size : Out std_logic_vector(0 to 2);
CE_Out : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
RdCE_Out : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Devicesel_inh_opb : in std_logic;
Devicesel_inh_mstr : in std_logic
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of integer;
type size_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
std_logic_vector(0 to 2);
-- functions ------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then return i;
end if;
end loop;
return(C_BUS_AWIDTH);
end function Addr_Bits;
function Get_Addr_Bits (baseaddrs : SLV64_ARRAY_TYPE)
return decode_bit_array_type is
Variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits(
baseaddrs(i*2)( baseaddrs(0)'length-C_BUS_AWIDTH
to baseaddrs(0)'length-1
),
baseaddrs(i*2+1)( baseaddrs(0)'length-C_BUS_AWIDTH
to baseaddrs(0)'length-1
)
);
end loop;
return(num_bits);
end function Get_Addr_Bits;
function encode_size (size : integer) return std_logic_vector is
Variable enc_size : Std_logic_vector(0 to 2);
begin
Case size Is
When 8 =>
enc_size := "001";
When 16 =>
enc_size := "010";
When 32 =>
enc_size := "011";
When 64 =>
enc_size := "100";
When 128 =>
enc_size := "101";
When others =>
enc_size := "000";
End case;
return(enc_size);
end function encode_size;
--ToDo, remove
-- function bool2int(b: boolean) return integer is
-- type tab_type is array (false to true) of integer;
-- constant tab : tab_type := (false => 0, true => 1);
-- begin
-- return tab(b);
-- end bool2int;
--
--
-------------------------------------------------------------------------------
---- Function calc_start_ce_index
----
---- This function is used to process the array specifying the number of Chip
---- Enables required for a Base Address specification. The CE Size array is
---- input to the function and an integer index representing the index of the
---- target module in the ce_num_array. An integer is returned reflecting the
---- starting index of the assigned Chip Enables within the CE, RdCE, and
---- WrCE Buses.
-------------------------------------------------------------------------------
-- function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
-- index : integer) return integer is
-- Variable ce_num_sum : integer := 0;
-- begin
-- for i in 0 to index-1 loop
-- ce_num_sum := ce_num_sum + ce_num_array(i)
-- + bool2int(ce_num_array(i)=0);
-- End loop;
-- return(ce_num_sum);
-- end function calc_start_ce_index;
--
--
-------------------------------------------------------------------------------
---- Function calc_num_ce
----
---- This function is used to process the array specifying the number of Chip
---- Enables required for a Base Address specification. The array is input to
---- the function and an integer is returned reflecting the total number of
---- Chip Enables required for the CE, RdCE, and WrCE Buses
-------------------------------------------------------------------------------
-- function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
-- Variable ce_num_sum : integer := 0;
-- begin
-- for i in 0 to (ce_num_array'length)-1 loop
-- ce_num_sum := ce_num_sum + ce_num_array(i)
-- + bool2int(ce_num_array(i)=0);
-- End loop;
-- return(ce_num_sum);
-- end function calc_num_ce;
-- Components------------------------------------------------------------------
component pselect is
generic (
C_AB : integer;
C_AW : integer;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end component pselect;
component or_gate is
generic (
C_OR_WIDTH : natural;
C_BUS_WIDTH : natural;
C_USE_LUT_OR : boolean
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end component or_gate;
-- constants
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
Constant DECODE_BITS : decode_bit_array_type := Get_Addr_Bits(C_ARD_ADDR_RANGE_ARRAY);
Constant NUM_SIZES : integer := C_ARD_DWIDTH_ARRAY'length;
Constant NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- Signals
signal CS_Out_i : std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal CE_Out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal CS_Size_i : std_logic_vector(0 to 2);
signal CS_Size_array : size_array_type;
Signal size_or_bus : std_logic_vector(0 to (3*NUM_SIZES)-1);
Signal decode_hit : std_logic_vector(0 to 0);
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Universal Address Decode Block
-----------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
begin
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: pselect
generic map (
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(bar_index*2)
( C_ARD_ADDR_RANGE_ARRAY(0)'length-C_BUS_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
A => Address_In, -- [in]
AValid => Address_Valid, -- [in]
CS => CS_Out_i(bar_index) -- [out]
);
-- Generate the size outputs
Assign_size : process (CS_Out_i(bar_index))
Begin
If (CS_Out_i(bar_index) = '1') Then
CS_Size_array(bar_index) <= encode_size(C_ARD_DWIDTH_ARRAY(bar_index));
else
CS_Size_array(bar_index) <= (others => '0');
End if;
End process; -- assign_size
-------------------------------------------------------------------------
-- Now expand the individual chip enables for each base address.
-------------------------------------------------------------------------
DECODE_REGBITS: for ce_index in
0 to C_ARD_NUM_CE_ARRAY(bar_index)
- 1
generate
Constant NEXT_CE_INDEX_START : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_DECODE_ADDR_SIZE : Integer range 0 to 15 := log2(C_ARD_NUM_CE_ARRAY(bar_index));
begin
---------------------------------------------------------------------
-- There is only one CE required so just use the output of the
-- pselect as the CE.
---------------------------------------------------------------------
CE_IS_CS : if (CE_DECODE_ADDR_SIZE = 0) generate
Constant ARRAY_INDEX : integer := ce_index;
Constant BASEADDR_INDEX : integer := bar_index;
begin
CE_Out_i(NEXT_CE_INDEX_START+ARRAY_INDEX) <= CS_Out_i(BASEADDR_INDEX);
end generate CE_IS_CS;
---------------------------------------------------------------------
-- Multiple CEs are required so expand and decode as needed by the
-- specified number of CEs.
---------------------------------------------------------------------
CE_EXPAND : if (CE_DECODE_ADDR_SIZE > 0) generate
Constant ARRAY_INDEX : integer := ce_index;
Constant BASEADDR_INDEX : integer := bar_index;
constant CE_DECODE_SKIP_BITS : Integer range 0 to 8 := log2(C_ARD_DWIDTH_ARRAY(BASEADDR_INDEX)/8);
constant CE_ADDR_WIDTH : Integer range 0 to 31 := CE_DECODE_ADDR_SIZE + CE_DECODE_SKIP_BITS;
constant ADDR_START_INDEX : integer range 0 to 31 := C_BUS_AWIDTH-CE_ADDR_WIDTH;
constant ADDR_END_INDEX : integer range 0 to 31 := C_BUS_AWIDTH-CE_DECODE_SKIP_BITS-1;
Signal compare_address : std_logic_vector(0 to CE_DECODE_ADDR_SIZE-1);
begin
INDIVIDUAL_CE_GEN : process (Address_In, CS_Out_i(BASEADDR_INDEX), compare_address)
Begin
compare_address <= Address_In(ADDR_START_INDEX to ADDR_END_INDEX);
if compare_address = ARRAY_INDEX then
CE_Out_i(NEXT_CE_INDEX_START+ARRAY_INDEX) <= CS_Out_i(BASEADDR_INDEX);
else
CE_Out_i(NEXT_CE_INDEX_START+ARRAY_INDEX) <= '0';
end if;
End process INDIVIDUAL_CE_GEN;
end generate CE_EXPAND;
end generate DECODE_REGBITS;
end generate MEM_DECODE_GEN;
OR_CS_Size : process (CS_Size_array)
Begin
for i in 0 to NUM_SIZES-1 loop
size_or_bus(3*i to 3*i+2) <= CS_Size_array(i);
End loop;
End process; -- OR_CS_SIZE
I_OR_SIZES : or_gate
generic map(
C_OR_WIDTH => NUM_SIZES,
C_BUS_WIDTH => 3,
C_USE_LUT_OR => TRUE
)
port map(
A => size_or_bus,
Y => CS_Size_i
);
I_OR_CS : or_gate
generic map(
C_OR_WIDTH => NUM_BASE_ADDRS,
C_BUS_WIDTH => 1,
C_USE_LUT_OR => TRUE
)
port map(
A => CS_Out_i,
Y => decode_hit
);
-------------------------------------------------------------------------------
-- end of decoder block
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Non-Registered Outputs Selection
-------------------------------------------------------------------------------
NOREG_OUTPUTS : if (C_USE_REG_OUTPUTS = False) generate
-- Assign output signals to combinational signals
Addr_Match <= decode_hit(0) ;
CS_Out <= CS_Out_i ;
CS_Size <= CS_Size_i ;
CE_Out <= CE_Out_i ;
SET_NOREG_RW_CE : process (CE_Out_i, Bus_RNW)
Begin
for i in 0 to NUM_CE_SIGNALS-1 loop
RdCE_Out(i) <= CE_Out_i(i) and Bus_RNW;
WrCE_Out(i) <= CE_Out_i(i) and not(Bus_RNW);
End loop;
End process; -- SET_NOREG_RW_CE
end generate NOREG_OUTPUTS;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- PLB REQUIRED REGISTERING
-------------------------------------------------------------------------------
-- The following logic is required by the PLB. It latches and holds the
-- signals necesary for the completion of the data phase of a PLB access.
-- It also generates the correct RdCE and WrCE timing for interfacing to
-- legacy OPB modules
-------------------------------------------------------------------------------
REGISTER_OUTPUTS : if (C_USE_REG_OUTPUTS = True) generate
signal CS_Out_i_reg : std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal CE_Out_i_reg : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal RdCE_Out_i_reg : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal WrCE_Out_i_reg : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal CS_Size_i_reg : std_logic_vector(0 to 2);
Signal decode_hit_reg : std_logic;
signal ff_reset : std_logic;
signal rdce_reset : std_logic;
signal wrce_reset : std_logic;
begin
ff_reset <= '1' when (Bus2IP_Burst = '0' and ( IP2Bus_WrAck_mx = '1'
or IP2Bus_RdAck_mx = '1'
)
)
or Bus_rst = '1' or
(Devicesel_inh_opb or Devicesel_inh_mstr) = '1'
else '0' ;
rdce_reset <= '1' when (Bus2IP_Burst = '0' and IP2Bus_RdAck_mx = '1')
or Bus_rst = '1'
or Bus_RNW = '0' or
(Devicesel_inh_opb or Devicesel_inh_mstr) = '1' else '0';
wrce_reset <= '1' when (Bus2IP_Burst = '0' and IP2Bus_WrAck_mx = '1')
or Bus_rst = '1'
or Bus_RNW = '1' or
(Devicesel_inh_opb or Devicesel_inh_mstr) = '1'
else '0';
REGCS_GEN: for i in 0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 generate
REGCS_FF_I: FDR
port map (
Q => CS_Out_i_reg(i),
C => Bus_clk,
D => CS_Out_i(i),
R => ff_reset
);
end generate REGCS_GEN;
REGCS_SIZE_GEN: for i in 0 to 2 generate
REGCS_SIZE_FF_I: FDR
port map (
D => CS_Size_i(i),
C => Bus_clk,
Q => CS_Size_i_reg(i),
R => ff_reset
);
end generate REGCS_SIZE_GEN;
REGCE_GEN: for i in 0 to NUM_CE_SIGNALS-1 generate
REGCE_FF_I: FDR
port map (
D => CE_Out_i(i),
C => Bus_clk,
Q => CE_Out_i_reg(i),
R => ff_reset
);
REGRDCE_FF_I: FDR
port map (
D => CE_Out_i(i),
C => Bus_clk,
Q => RdCE_Out_i_reg(i),
R => rdce_reset
);
REGWRCE_FF_I: FDR
port map (
D => CE_Out_i(i),
C => Bus_clk,
Q => WrCE_Out_i_reg(i),
R => wrce_reset
);
end generate REGCE_GEN;
-- -- Register the CS and CE signals
-- REGCS_PROCESS: process(Bus_clk)
-- begin
--
-- if (Bus_clk'event and Bus_clk='1') then
-- if (Bus2IP_Burst = '0' and ( IP2Bus_WrAck_mx = '1'
-- or IP2Bus_RdAck_mx = '1'
-- )
-- )
-- or Bus_rst = '1'
-- then
-- CS_Out_i_reg <= (others => '0');
-- CS_Size_i_reg <= (others => '0');
-- CE_Out_i_reg <= (others => '0');
-- else
-- CS_Out_i_reg <= CS_Out_i;
-- CS_Size_i_reg <= CS_Size_i;
-- CE_Out_i_reg <= CE_Out_i;
-- end if;
-- end if;
--
-- if (Bus_clk'event and Bus_clk='1') then
-- if (Bus2IP_Burst = '0' and IP2Bus_RdAck_mx = '1')
-- or Bus_rst = '1'
-- or Bus_RNW = '0'
-- then
-- RdCE_Out_i_reg <= (others => '0');
-- else
-- RdCE_Out_i_reg <= CE_Out_i;
-- end if;
-- end if;
--
-- if (Bus_clk'event and Bus_clk='1') then
-- if (Bus2IP_Burst = '0' and IP2Bus_WrAck_mx = '1')
-- or Bus_rst = '1'
-- or Bus_RNW = '1'
-- then
-- WrCE_Out_i_reg <= (others => '0');
-- else
-- WrCE_Out_i_reg <= CE_Out_i;
-- end if;
-- end if;
--
-- end process;
-- Register the Decode hit signal
REG_DECODE_HIT : process (Bus_clk)
Begin
if (Bus_clk'event and Bus_clk='1') then
if Bus_rst = '1' then
decode_hit_reg <= '0';
else
decode_hit_reg <= decode_hit(0);
end if;
end if;
End process; -- REG_DECODE_HIT
-- Assign output signals to registered signals
Addr_Match <= decode_hit_reg ;
CS_Out <= CS_Out_i_reg ;
CS_Size <= CS_Size_i_reg ;
CE_Out <= CE_Out_i_reg ;
RdCE_Out <= RdCE_Out_i_reg ;
WrCE_Out <= WrCE_Out_i_reg ;
end generate REGISTER_OUTPUTS;
-------------------------------------------------------------------------------
end architecture IMP;
| bsd-3-clause | f01648fe536a4bd70bd89c63ac68a612 | 0.433325 | 4.038914 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_idea_v1_00_a/hdl/vhdl/hw_acc_idea.vhd | 2 | 5,245 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_idea is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_idea;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_idea is
component idea_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal reset_sig : std_logic;
-- Architecture Section
begin
reset_sig <= RST or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
uut : idea_chan
port map (
Vector_A_addr0 => BRAM_A_addr,
Vector_A_dIN0 => BRAM_A_dOUT,
Vector_A_dOUT0 => BRAM_A_dIN,
Vector_A_rENA0 => BRAM_A_en,
Vector_A_wENA0 => BRAM_A_wEN,
Vector_B_addr0 => BRAM_B_addr,
Vector_B_dIN0 => BRAM_B_dOUT,
Vector_B_dOUT0 => BRAM_B_dIN,
Vector_B_rENA0 => BRAM_B_en,
Vector_B_wENA0 => BRAM_B_wEN,
Vector_C_addr0 => BRAM_C_addr,
Vector_C_dIN0 => BRAM_C_dOUT,
Vector_C_dOUT0 => BRAM_C_dIN,
Vector_C_rENA0 => BRAM_C_en,
Vector_C_wENA0 => BRAM_C_wEN,
chan1_channelDataIn => FSL0_M_Data,
chan1_channelDataOut => FSL0_S_Data,
chan1_exists => FSL0_S_Exists,
chan1_full => FSL0_M_Full,
chan1_channelRead => FSL0_S_Read,
chan1_channelWrite => FSL0_M_Write,
clock_sig => Clk,
reset_sig => reset_sig
);
end architecture implementation;
| bsd-3-clause | bb87a428f0644c9c1fb26a5d75c15b82 | 0.564156 | 2.816864 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/core/logical.vhd | 1 | 602 | library ieee;
use ieee.std_logic_1164.all;
ENTITY logical IS
generic (
width : integer
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
B: IN std_logic_VECTOR(width-1 downto 0);
OP: IN std_logic_vector( 1 downto 0);
S: OUT std_logic_VECTOR(width-1 downto 0)
);
END logical;
ARCHITECTURE behavior OF logical IS
begin
process( A, B, OP )
begin
case OP is
when "00" =>
S<=B;
when "01" =>
S<=A and B;
when "10" =>
S<=A or B;
when "11" =>
S<=A xor B;
when others =>
null;
end case;
end process;
end behavior;
| gpl-2.0 | 4431d2a6a8b81d689a3449eb2177044c | 0.569767 | 2.711712 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/join_1.vhd | 2 | 18,097 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: join_1.c
-- reg4 = value
-- reg5 = returnValue
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
-- data->value = 1
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
-- store 1 to data->value
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= arg + x"00000004";
thrd2intrfc_value <= x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, &data->value );
when STATE_3 =>
-- push &data_value
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, &data->returnValue );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push &data->returnValue
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
-- data->value++
when STATE_12 =>
-- load the current value of value
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- increment value
reg4_next <= intrfc2thrd_value + x"00000001";
next_state <= STATE_14;
when STATE_14 =>
-- store value back to its address
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= arg + x"00000004";
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
-- if (data->value != data->returnValue ) retVal = SUCCESS;
-- else retVal = FAILURE;
when STATE_15 =>
-- load the value of returnValue
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
if ( intrfc2thrd_value = reg4 ) then
retVal_next <= x"00000001";
else
retVal_next <= Z32;
end if;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | ef9292aeb6632e1df0bfc491dd9943fc | 0.547991 | 3.785983 | false | false | false | false |
jevinskie/aes-over-pcie | source/shift_rows_p.vhd | 1 | 1,037 | -- File name: shift_rows_p.vhd
-- Created: 2009-04-26
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: parallel shift_rows
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shift_rows_p is
port (
d_in : in state_type;
d_out : out state_type
);
end entity shift_rows_p;
architecture behavioral of shift_rows_p is
type row_array is array (index) of row;
signal in_rows, out_rows : row_array;
begin
gen_shift_rows:
for i in index generate
shift_rows_b: entity work.shift_rows(dataflow) port map (
data_in => in_rows(i), num_shifts => i, data_out => out_rows(i)
);
end generate gen_shift_rows;
process(d_in, out_rows)
begin
for i in index loop
for j in index loop
in_rows(i)(j) <= d_in(i, j);
d_out(i, j) <= out_rows(i)(j);
end loop;
end loop;
end process;
end architecture behavioral;
| bsd-3-clause | 00a1e5236344628e08a401b08e3cfcd6 | 0.599807 | 3.171254 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_dpram_select.vhd | 2 | 118,964 | -------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
| bsd-3-clause | 0aa344354a2a38eccf802c29ce69ff61 | 0.371575 | 4.808763 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/g_eth/g_ethtx_output.vhd | 1 | 19,068 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity g_ethtx_output is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 16;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(7 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_rdata : in std_logic_vector(31 downto 0);
dma_start : out std_logic;
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
localtime : in std_logic_vector(31 downto 0)
);
end g_ethtx_output;
architecture arch_ethtx_output of g_ethtx_output is
component crc8_blkrom
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component fifo_async_almost_full
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
almost_full : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async_almost_full use entity WORK.fifo_async_almost_full(fast_write);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
constant INFO_LENGTH : natural := 8;
signal ce : std_logic;
signal ce_d1 : std_logic;
signal ce_ext : std_logic;
signal ce_ext_d1 : std_logic;
signal ce_ext_d2 : std_logic;
signal txd_buf : std_logic_vector(7 downto 0);
signal txen_buf : std_logic;
signal txd_buf_d1 : std_logic_vector(7 downto 0);
signal txen_buf_d1 : std_logic;
signal TxFIFO_clr : std_logic;
signal TxFIFO_wea : std_logic;
signal TxFIFO_dia : std_logic_vector(31 downto 0);
signal TxFIFO_rdb : std_logic;
signal TxFIFO_rdb_d1 : std_logic;
signal TxFIFO_dob : std_logic_vector(31 downto 0);
signal TxFIFO_almost_full : std_logic;
signal TxFIFO_empty : std_logic;
signal TxFIFO_DN : std_logic_vector(3 downto 0);
signal busy : std_logic;
signal byte_cnt : std_logic_vector(11 downto 0);
signal byte_cnt_d1 : std_logic_vector(11 downto 0);
signal byte_cnt_ext : std_logic_vector(11 downto 0);
signal byte_cnt_ext_d1 : std_logic_vector(11 downto 0);
signal byte_cnt_ext_d2 : std_logic_vector(11 downto 0);
signal head_length : std_logic_vector(7 downto 0);
signal data_length : std_logic_vector(10 downto 0);
signal source_select : std_logic;
signal head_rd_block : std_logic;
signal info_ena : std_logic;
signal info_ena_d1 : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal info_cnt_d1 : integer range 0 to INFO_LENGTH;
signal data_ena : std_logic;
signal data_ena_d8 : std_logic;
signal data_ena_ext : std_logic;
signal data_ena_ext_d1 : std_logic;
signal data_ena_ext_d2 : std_logic;
signal data_ena_ext_d6 : std_logic;
signal data_ena_ext_d8 : std_logic;
signal data_ena_ext_d12 : std_logic;
signal data_ena_ext_d13 : std_logic;
signal head_ena : std_logic;
signal head_ena_d1 : std_logic;
signal buff_ena : std_logic;
signal buff_ena_d1 : std_logic;
signal info_start : std_logic;
signal data_start : std_logic;
signal data_start_ext : std_logic;
signal data_start_ext_wren : std_logic;
signal dword_data_int : std_logic_vector(31 downto 0);
signal dword_data_ext : std_logic_vector(31 downto 0);
signal byte_data : std_logic_vector(7 downto 0);
signal byte_data_buf : std_logic_vector(31 downto 0);
signal byte_data_dly : std_logic_vector(7 downto 0);
signal head_rden : std_logic;
signal head_rdata : std_logic_vector(7 downto 0);
signal head_rdata_buf : std_logic_vector(23 downto 0);
signal head_raddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal buff_rden : std_logic;
signal buff_rden_d1 : std_logic;
signal buff_raddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata_buf : std_logic_vector(31 downto 0);
signal crc_din : std_logic_vector(7 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crc_reg_d1 : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(7 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal v0 : std_logic_vector(0 downto 0);
signal v1 : std_logic_vector(0 downto 0);
signal v2 : std_logic_vector(0 downto 0);
signal v3 : std_logic_vector(0 downto 0);
signal localtime_reg : std_logic_vector(31 downto 0);
signal crc_reg_dly : std_logic_vector(7 downto 0);
signal IFG_cnt : std_logic_vector(4 downto 0);
signal IFG_busy : std_logic;
signal m4_TxFIFO_DN : std_logic_vector( 3 downto 0 );
signal s_N_Empty : std_logic;
signal s_N_Empty_TxClk : std_logic;
signal s_N_Empty_TxClk_D1 : std_logic;
begin
p_info_start : process(clk, reset)
begin
if reset = '1' then
info_start <= '0';
source_select <= '0';
ce_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if busy = '0' then
if tx_queue_empty = '0' then
info_start <= '1';
source_select <= '0';
elsif db_queue_empty = '0' then
info_start <= '1';
source_select <= '1';
end if;
else
info_start <= '0';
end if;
end if;
ce_d1 <= ce;
end if;
end process;
busy <= info_start or info_ena or data_start or data_ena or data_ena_d8 or data_ena_ext or data_ena_ext_d13 or IFG_busy;
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
info_ena <= '0';
info_cnt <= 0;
info_ena_d1 <= '0';
info_cnt_d1 <= 0;
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
info_ena <= '1';
elsif info_cnt = INFO_LENGTH - 1 then
info_ena <= '0';
end if;
if info_ena = '0' then
info_cnt <= 0;
else
info_cnt <= info_cnt + 1;
end if;
end if;
info_ena_d1 <= info_ena;
info_cnt_d1 <= info_cnt;
end if;
end process;
------------------------------------------------------------------------------
data_start <= '1' when info_cnt = INFO_LENGTH else '0';
p_byte_cnt : process(clk, reset)
begin
if reset = '1' then
data_ena <= '0';
byte_cnt <= (others => '0');
byte_cnt_d1 <= (others=>'0');
head_ena_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
data_ena <= '1';
elsif buff_ena = '0' and byte_cnt >= data_length-1 then
data_ena <= '0';
elsif buff_ena = '1' and byte_cnt >= data_length - 4 then
data_ena <= '0';
end if;
if data_start = '1' then
byte_cnt <= (others => '0');
elsif head_ena = '1' then
byte_cnt <= byte_cnt + 1;
elsif buff_ena = '1' then
byte_cnt <= byte_cnt + 4;
end if;
end if;
byte_cnt_d1 <= byte_cnt;
head_ena_d1 <= head_ena;
end if;
end process;
head_ena <= '1' when data_ena = '1' and byte_cnt < head_length else '0';
buff_ena <= '1' when data_ena = '1' and byte_cnt >= head_length else '0';
------------------------------------------------------------------------------
head_rden <= (info_ena or head_ena) and ce;
p_head_raddr : process(clk, reset)
begin
if reset = '1' then
head_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
head_raddr_buf <= (others => '0');
elsif head_rden = '1' then
head_raddr_buf <= head_raddr_buf + 1;
end if;
end if;
end if;
end process;
tx_head_raddr <= head_raddr_buf;
db_head_raddr <= head_raddr_buf;
head_rdata <= tx_head_rdata when source_select = '0' else db_head_rdata;
head_rd_block <= '1' when byte_cnt = head_length else '0';
tx_head_rd_block <= head_rd_block and ce and (not source_select);
db_head_rd_block <= head_rd_block and ce and source_select;
p_get_info : process(clk, reset)
begin
if reset = '1' then
head_length <= (others => '0');
data_length <= (others => '0');
dma_start_addr <= (others => '0');
dma_step <= (others => '0');
elsif rising_edge(clk) then
if ce_d1 = '1' then
if info_ena_d1 = '1' then
case info_cnt_d1 is
when 0 =>
head_length(7 downto 0) <= head_rdata;
when 1 =>
data_length(7 downto 0) <= head_rdata;
when 2 =>
data_length(10 downto 8) <= head_rdata(2 downto 0);
when 3 =>
dma_start_addr(7 downto 0) <= head_rdata;
when 4 =>
dma_start_addr(15 downto 8) <= head_rdata;
when 5 =>
dma_start_addr(23 downto 16) <= head_rdata;
when 6 =>
dma_start_addr(31 downto 24) <= head_rdata;
when 7 =>
dma_step <= head_rdata;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
dma_start <= '1' when info_cnt_d1 = INFO_LENGTH and ce_d1 = '1' and data_length /= head_length else '0';
dma_length <= EXT(data_length, 16) - EXT(head_length, 16);
-----------------------------------------------------------------------------
p_get_head : process(clk, reset)
begin
if reset = '1' then
head_rdata_buf <= (others=>'0');
elsif rising_edge(clk) then
if ce_d1 = '1' then
if head_ena_d1 = '1' then
if byte_cnt_d1(1 downto 0) = "00" then
head_rdata_buf <= head_rdata & X"0000";
else
head_rdata_buf <= head_rdata & head_rdata_buf(23 downto 8);
end if;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
buff_rden <= buff_ena and ce;
p_buff_raddr : process(clk, reset)
begin
if reset = '1' then
buff_raddr_buf <= (others => '0');
buff_rdata_buf <= (others=>'0');
buff_ena_d1 <= '0';
buff_rden_d1 <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
buff_raddr_buf <= (others => '0');
elsif buff_rden = '1' then
buff_raddr_buf <= buff_raddr_buf + 1;
end if;
buff_rdata_buf <= buff_rdata;
end if;
buff_ena_d1 <= buff_ena;
buff_rden_d1 <= buff_rden;
end if;
end process;
buff_raddr <= buff_raddr_buf;
------------------------------------------------------------------------------
dword_data_int <= buff_rdata_buf when buff_ena_d1 = '1' else
head_rdata & head_rdata_buf when head_ena_d1 = '1' else
(others=>'0');
ce <= not TxFIFO_almost_full;
TxFIFO_clr <= '1' when data_start = '1' else '0';
TxFIFO_wea <= '1' when (head_ena_d1 = '1' and byte_cnt_d1(1 downto 0) = "11") or buff_rden_d1 = '1' else '0';
TxFIFO_dia <= dword_data_int;
u_txclk_sync : fifo_async_almost_full
generic map(
depth => 16,
awidth => 4,
dwidth => 32,
ram_type => "DIS_RAM"
)
port map(
reset => reset,
clr => TxFIFO_clr,
clka => clk,
wea => TxFIFO_wea,
dia => TxFIFO_dia,
clkb => txclk,
rdb => TxFIFO_rdb,
dob => TxFIFO_dob,
empty => TxFIFO_empty,
almost_full => TxFIFO_almost_full,
full => open,
dn => TxFIFO_DN
);
dword_data_ext <= TxFIFO_dob;
TxFIFO_rdb <= data_ena_ext and ce_ext when byte_cnt_ext(1 downto 0) = "00" else '0';
-------------------------------------------------------------------------------------------------------
data_start_ext_wren <= (not head_ena) and head_ena_d1;
ASYNCWRITE_data_start_ext : ASYNCWRITE
port map(
reset => reset,
async_clk => clk,
sync_clk => txclk,
async_wren => data_start_ext_wren,
trigger => '1',
sync_wren => data_start_ext,
over => open,
flag => open
);
ce_ext <= '1';
p_byte_cnt_ext : process(txclk, reset)
begin
if reset = '1' then
ce_ext_d1 <= '0';
ce_ext_d2 <= '0';
data_ena_ext <= '0';
data_ena_ext_d1 <= '0';
data_ena_ext_d2 <= '0';
byte_cnt_ext <= (others => '0');
byte_cnt_ext_d1 <= (others=>'0');
byte_cnt_ext_d2 <= (others=>'0');
TxFIFO_rdb_d1 <= '0';
elsif rising_edge(txclk) then
if ce_ext = '1' then
if data_start_ext = '1' then
data_ena_ext <= '1';
elsif byte_cnt_ext = data_length - 1 then
data_ena_ext <= '0';
end if;
if data_start_ext = '1' then
byte_cnt_ext <= (others => '0');
else
byte_cnt_ext <= byte_cnt_ext + 1;
end if;
end if;
ce_ext_d1 <= ce_ext;
ce_ext_d2 <= ce_ext_d1;
data_ena_ext_d1 <= data_ena_ext;
data_ena_ext_d2 <= data_ena_ext_d1;
byte_cnt_ext_d1 <= byte_cnt_ext;
byte_cnt_ext_d2 <= byte_cnt_ext_d1;
TxFIFO_rdb_d1 <= TxFIFO_rdb;
end if;
end process;
p_byte_data_buf : process(txclk, reset)
begin
if reset = '1' then
byte_data_buf <= (others => '0');
elsif rising_edge(txclk) then
if ce_ext_d1 = '1' then
if TxFIFO_rdb_d1 = '1' then
byte_data_buf <= TxFIFO_dob;
else
byte_data_buf <= X"00" & byte_data_buf(31 downto 8);
end if;
end if;
end if;
end process;
p_localtime : process(reset, txclk)
begin
if reset = '1' then
localtime_reg <= (others => '0');
elsif rising_edge(txclk) then
if byte_cnt_ext = 7 then
localtime_reg <= localtime;
end if;
end if;
end process;
byte_data <= localtime_reg(31 downto 24) when byte_cnt_ext_d1 = 14 and source_select = '0' else
localtime_reg(23 downto 16) when byte_cnt_ext_d1 = 15 and source_select = '0' else
localtime_reg(15 downto 8) when byte_cnt_ext_d1 = 16 and source_select = '0' else
localtime_reg(7 downto 0) when byte_cnt_ext_d1 = 17 and source_select = '0' else
TxFIFO_dob(7 downto 0) when byte_cnt_ext_d1(1 downto 0) = "00" else
byte_data_buf(15 downto 8);
u_crc_rom : CRC8_BlkRom
port map(
clk => txclk,
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 24);
crc_din <= (others => '0') when data_ena_ext_d1 = '0' else
not (byte_data(0) & byte_data(1) & byte_data(2) & byte_data(3) & byte_data(4) & byte_data(5) & byte_data(6) & byte_data(7)) when byte_cnt_ext_d1 < 4 else
byte_data(0) & byte_data(1) & byte_data(2) & byte_data(3) & byte_data(4) & byte_data(5) & byte_data(6) & byte_data(7);
crc_reg <= (others=>'0') when data_start_ext = '1' and ce_ext = '1' else
crc_reg_d1 xor crcrom_dout when (data_ena_ext_d2 = '1' or data_ena_ext_d6 = '1') and ce_ext_d2 = '1' else
crc_reg_d1;
p_calc_crc : process(txclk, reset)
begin
if reset = '1' then
crc_reg_d1 <= (others => '0');
elsif rising_edge(txclk) then
if ce_ext_d1 = '1' then
if data_start_ext = '1' then
crc_reg_d1 <= (others => '0');
else
crc_reg_d1 <= (crc_reg(23 downto 0) & crc_din);
end if;
else
crc_reg_d1 <= crc_reg(23 downto 0) & crc_din;
end if;
end if;
end process;
------------------------------------------------------------------------------
u_nibble_data_dly : ShiftReg
generic map(
WIDTH => 8,
DEPTH => 7
)
port map(
clk => txclk,
ce => '1',
D => byte_data,
Q => byte_data_dly,
S => open
);
u_crc_reg_dly : ShiftReg
generic map(
WIDTH => 8,
DEPTH => 3
)
port map(
clk => txclk,
ce => '1',
D => crc_reg(31 downto 24),
Q => crc_reg_dly(7 downto 0),
S => open
);
u_data_ena_d0 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8
)
port map(
clk => clk,
ce => '1',
D(0) => data_ena,
Q(0) => data_ena_d8,
S => open
);
u_data_ena_d1 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 4
)
port map(
clk => txclk,
ce => '1',
D => v0,
Q => v1,
S => open
);
u_data_ena_d2 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 2
)
port map(
clk => txclk,
ce => '1',
D => v1,
Q => v2,
S => open
);
u_data_ena_d3 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 4
)
port map(
clk => txclk,
ce => '1',
D => v2,
Q => v3,
S => open
);
v0(0) <= data_ena_ext_d2;
data_ena_ext_d6 <= v1(0);
data_ena_ext_d8 <= v2(0);
data_ena_ext_d12 <= v3(0);
txd_buf <= "01010101" when data_ena_ext = '1' and byte_cnt_ext < 7 else
"11010101" when data_ena_ext = '1' and byte_cnt_ext = 7 else
--
byte_data_dly when data_ena_ext_d8 = '1' else
not(crc_reg_dly(0) & crc_reg_dly(1) & crc_reg_dly(2) & crc_reg_dly(3) & crc_reg_dly(4) & crc_reg_dly(5) & crc_reg_dly(6) & crc_reg_dly(7));
txen_buf <= data_ena_ext or data_ena_ext_d12;
------------------------------------------------------------------------------
p_mii_dout : process(reset, txclk)
begin
if ( reset = '1' ) then
txen <= '0';
txd <= ( others => '0' );
elsif rising_edge(txclk) then
txen <= txen_buf;
txd <= txd_buf;
end if;
end process;
p_ifg_count : process(txclk, reset)
begin
if reset = '1' then
IFG_cnt <= "00000";
data_ena_ext_d13 <= '0';
elsif rising_edge(txclk) then
data_ena_ext_d13 <= data_ena_ext_d12;
if IFG_busy = '1' then
IFG_cnt <= IFG_cnt + '1';
else
IFG_cnt <= "00000";
end if;
end if;
end process;
p_ifg_busy_flag : process(txclk, reset)
begin
if reset = '1' then
IFG_busy <= '0';
elsif rising_edge(txclk) then
if data_ena_ext_d12 = '0' and data_ena_ext_d13 = '1' then
IFG_busy <= '1';
elsif IFG_cnt = "11111" then
IFG_busy <= '0';
end if;
end if;
end process;
end arch_ethtx_output;
| gpl-2.0 | cc35436e434573d7c24cf4b75444f04b | 0.554279 | 2.682611 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_indi_if_ctrl_regs.vhd | 1 | 18,320 | ---------------------------------------------------------------
-- Title : 16z126-01 Indirect Interface Control Registers
-- Project : 16z126-01
---------------------------------------------------------------
-- File : z126_01_indi_if_ctrl_regs.vhd
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
-- The state machine transforms an wishbone access from the
-- slave input to a wishbone master access to the master output.
-- The state machine consits of one address and one data
-- register in order to realize an indirect memory access.
-- The indirect memory access is initiated at the wishbone
-- slave input and is transformed to an wishbone master output
-- (in order to access an 16z100 Module)
--
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_top
-- z126_01_indi_if_ctrl_regs
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: z126_01_indi_if_ctrl_regs.vhd,v $
-- Revision 1.3 2014/11/24 16:44:12 AGeissler
-- R1: Complex FSM for WBM to remote update controller and WBM to PASMI interface
-- M1: Simplified the FSM by reduced states
-- R2: Misleading signal name
-- M2: Renamed signal adr_reg to ctrl_reg
-- R3: Unused signal
-- M3: Removed ctrl_busy_q
-- R4: Code optimization
-- M4: Moved signal reconfig_int into write access condition of the wishbone bus
-- slave
--
-- Revision 1.2 2014/03/05 11:19:36 AGeissler
-- R: Missing reset for signal
-- M: Added reset
--
-- Revision 1.1 2014/03/03 17:49:41 AGeissler
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY z126_01_indi_if_ctrl_regs IS
PORT (
clk : IN std_logic; -- Wishbone clock (66 MHz)
rst : IN std_logic; -- Reset
-- wishbone signals master interface (ru_ctrl interface)
wbm_ru_cyc : OUT std_logic;
wbm_ru_ack : IN std_logic;
wbm_ru_we : OUT std_logic;
wbm_ru_sel : OUT std_logic_vector(3 DOWNTO 0);
wbm_ru_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ru_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : OUT std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : IN std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : IN std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- wishbone signals master interface (wb2pasmi interface)
wbm_stb : OUT std_logic; -- strobe
wbm_adr : OUT std_logic_vector(31 DOWNTO 0); -- address
wbm_ack : IN std_logic; -- acknowledge
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
wbm_cyc : OUT std_logic; -- chip select
-- wishbone signals slave interface (indirect interface)
wbs_stb : IN std_logic; -- strobe
wbs_ack : OUT std_logic; -- acknowledge
wbs_we : IN std_logic; -- write=1 read=0
wbs_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc : IN std_logic; -- chip select
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr : IN std_logic_vector(31 DOWNTO 0); -- address
-- ctrl signals from registers
ctrl_read_sid : OUT std_logic;
ctrl_sector_protect : OUT std_logic;
ctrl_write : OUT std_logic;
ctrl_read_status : OUT std_logic;
ctrl_sector_erase : OUT std_logic;
ctrl_bulk_erase : OUT std_logic;
ctrl_illegal_write : IN std_logic;
ctrl_illegal_erase : IN std_logic;
ctrl_busy : IN std_logic
);
END z126_01_indi_if_ctrl_regs;
ARCHITECTURE z126_01_indi_if_ctrl_regs_arch OF z126_01_indi_if_ctrl_regs IS
TYPE wb_states IS (IDLE, PER_REQ, ACKNOWLEDGE);
SIGNAL ctrl_reg : std_logic_vector(31 DOWNTO 0); -- control register
SIGNAL flash_adr : std_logic_vector(23 DOWNTO 0); -- flash adress register
SIGNAL reconfig_int : std_logic;
SIGNAL wbs_ack_int : std_logic;
SIGNAL wbm_state : wb_states := IDLE;
SIGNAL wbm_start : std_logic;
SIGNAL wbm_done : std_logic;
SIGNAL wbm_cyc_int : std_logic;
SIGNAL wbm_ru_state : wb_states := IDLE;
SIGNAL wbm_ru_start : std_logic;
SIGNAL wbm_ru_done : std_logic;
SIGNAL ctrl_read_sid_q : std_logic;
SIGNAL ctrl_sector_protect_q : std_logic;
SIGNAL ctrl_sector_erase_q : std_logic;
SIGNAL ctrl_bulk_erase_q : std_logic;
SIGNAL ctrl_read_status_q : std_logic;
SIGNAL ctrl_illegal_write_q : std_logic;
SIGNAL ctrl_illegal_erase_q : std_logic;
BEGIN
-- wishbone connection to remote update controller
wbm_ru_dat_o <= wbs_dat_i;
wbm_ru_sel <= wbs_sel;
wbm_ru_we <= wbs_we;
-- control signals to wb2pasmi module
ctrl_read_sid <= ctrl_read_sid_q;
ctrl_sector_protect <= ctrl_sector_protect_q;
ctrl_read_status <= ctrl_read_status_q;
ctrl_sector_erase <= ctrl_sector_erase_q;
ctrl_bulk_erase <= ctrl_bulk_erase_q;
-- control register of indirect interface
ctrl_reg <= reconfig_int & ctrl_busy & ctrl_illegal_erase_q & ctrl_illegal_write_q & "0000" & flash_adr;
wbm_cyc <= wbm_cyc_int;
wbm_stb <= wbm_cyc_int;
wbm_adr <= x"00" & ctrl_reg(23 DOWNTO 0);
wbs_ack <= wbs_ack_int;
reg_reconfig <= reconfig_int; -- reconfiguration is generated from bit 31 of ctrl_reg
-- Process for register access
z126_01_wbs_regs: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
flash_adr <= (OTHERS => '0');
ctrl_read_sid_q <= '0';
ctrl_sector_protect_q <= '0';
ctrl_read_status_q <= '0';
ctrl_sector_erase_q <= '0';
ctrl_bulk_erase_q <= '0';
ctrl_write <= '0';
ctrl_illegal_write_q <= '0';
ctrl_illegal_erase_q <= '0';
reconfig_int <= '0';
wbs_ack_int <= '0';
wbm_start <= '0';
wbm_ru_start <= '0';
wbs_dat_o <= (OTHERS => '0');
ELSIF clk'EVENT AND clk ='1' THEN
----------------------------------------
-- write access to indirect interface --
----------------------------------------
IF wbs_stb = '1' AND wbs_cyc = '1' AND wbs_ack_int = '0' AND wbs_we = '1' THEN
IF wbs_adr(3 DOWNTO 2) = "00" THEN -- Write to Address Register 0x00
wbs_ack_int <= '1'; -- Issue acknowledge immediately
wbm_start <= '0'; -- Don't perform a wishbone master access
IF wbs_sel(0) = '1' THEN
flash_adr(7 DOWNTO 0) <= wbs_dat_i(7 DOWNTO 0);
END IF;
IF wbs_sel(1) = '1' THEN
flash_adr(15 DOWNTO 8) <= wbs_dat_i(15 DOWNTO 8);
END IF;
IF wbs_sel(2) = '1' THEN
flash_adr(23 DOWNTO 16) <= wbs_dat_i(23 DOWNTO 16);
END IF;
IF wbs_sel(3) = '1' THEN
ctrl_read_sid_q <= wbs_dat_i(25);
ctrl_sector_protect_q <= wbs_dat_i(26);
ctrl_read_status_q <= wbs_dat_i(27);
ctrl_sector_erase_q <= wbs_dat_i(28);
ctrl_bulk_erase_q <= wbs_dat_i(29);
ctrl_write <= wbs_dat_i(30);
reconfig_int <= wbs_dat_i(31); -- Bit 31 indicates reconfiguration
ctrl_illegal_write_q <= '0'; -- reset status bits
ctrl_illegal_erase_q <= '0';
END IF;
ELSIF wbs_adr(3 DOWNTO 2) = "01" THEN -- write to data register 0x04
wbs_ack_int <= wbm_done; -- issue acknowledge when wb access is done
wbm_start <= NOT wbm_done; -- start wisbone master access when
-- no former access is in work
flash_adr <= flash_adr;
ctrl_read_sid_q <= '0';
ctrl_sector_protect_q <= ctrl_sector_protect_q;
ctrl_read_status_q <= '0';
ctrl_sector_erase_q <= ctrl_sector_erase_q;
ctrl_bulk_erase_q <= ctrl_bulk_erase_q;
ctrl_write <= '0';
ctrl_illegal_write_q <= ctrl_illegal_write_q;
ctrl_illegal_erase_q <= ctrl_illegal_erase_q;
ELSIF wbs_adr(3 DOWNTO 2) = "10" THEN -- board status register (read-only)
wbs_ack_int <= '1'; -- Issue acknowledge immediately
ELSIF wbs_adr(3 DOWNTO 2) = "11" THEN
-- write boot address of remote update controller
-- perform wishbone master access to ru_ctrl
wbs_ack_int <= wbm_ru_done;
wbm_ru_start <= NOT wbm_ru_done;
END IF;
---------------------------------------
-- read access to indirect interface --
---------------------------------------
ELSIF wbs_stb = '1' AND wbs_cyc = '1' AND wbs_ack_int = '0' AND wbs_we = '0' THEN
CASE wbs_adr(3 DOWNTO 2) IS
WHEN "00" => -- read 0x00 Control Register
wbm_start <= '0'; -- Don't perform a wishbone master access
wbs_ack_int <= '1'; -- Issue acknowledge immediately
flash_adr <= flash_adr;
ctrl_read_sid_q <= '0';
ctrl_sector_protect_q <= '0';
ctrl_read_status_q <= '0';
ctrl_sector_erase_q <= '0';
ctrl_bulk_erase_q <= '0';
ctrl_write <= '0';
ctrl_illegal_write_q <= ctrl_illegal_write_q;
ctrl_illegal_erase_q <= ctrl_illegal_erase_q;
WHEN "01" => -- read 0x04 Data Register
wbm_start <= NOT wbm_done;
wbs_ack_int <= wbm_done;
flash_adr <= flash_adr;
ctrl_read_sid_q <= ctrl_read_sid_q;
ctrl_sector_protect_q <= '0';
ctrl_write <= '0';
ctrl_read_status_q <= ctrl_read_status_q;
ctrl_sector_erase_q <= '0';
ctrl_bulk_erase_q <= '0';
ctrl_illegal_write_q <= ctrl_illegal_write_q;
ctrl_illegal_erase_q <= ctrl_illegal_erase_q;
WHEN "10" => -- read 0x08 board status register (read-only)
wbs_ack_int <= '1'; -- issue acknowledge immediately
WHEN "11" => -- "11" = 0x0C
-- read boot address of remote update controller
-- perform wishbone master access to ru_ctrl
wbm_ru_start <= NOT wbm_ru_done;
wbs_ack_int <= wbm_ru_done;
WHEN OTHERS =>
wbs_ack_int <= '1'; -- issue acknowledge immediately
END CASE;
ELSE
wbs_ack_int <= '0';
wbm_start <= '0';
wbm_ru_start <= '0';
flash_adr <= flash_adr;
ctrl_read_sid_q <= ctrl_read_sid_q;
ctrl_sector_protect_q <= ctrl_sector_protect_q;
ctrl_read_status_q <= ctrl_read_status_q;
ctrl_sector_erase_q <= ctrl_sector_erase_q;
ctrl_bulk_erase_q <= ctrl_bulk_erase_q;
ctrl_write <= '0';
IF ctrl_illegal_write = '1' THEN
ctrl_illegal_write_q <= '1';
ELSE
ctrl_illegal_write_q <= ctrl_illegal_write_q;
END IF;
IF ctrl_illegal_erase = '1' THEN
ctrl_illegal_erase_q <= '1';
ELSE
ctrl_illegal_erase_q <= ctrl_illegal_erase_q;
END IF;
END IF;
-- wbs data out (read)
IF wbs_adr(3 DOWNTO 2) = "00" THEN
wbs_dat_o <= ctrl_reg;
ELSIF wbs_adr(3 DOWNTO 2) = "01" THEN
wbs_dat_o <= wbm_dat_i;
ELSIF wbs_adr(3 DOWNTO 2) = "10" THEN
wbs_dat_o <= x"000000" & "0" & reg_reconfig_cond & reg_board_status;
ELSIF wbs_adr(3 DOWNTO 2) = "11" THEN
wbs_dat_o <= wbm_ru_dat_i;
END IF;
END IF;
END PROCESS z126_01_wbs_regs;
-- generating wishbone master access for remote update unit
z126_01_wbm_ru_fsm_proc: PROCESS(clk, rst)
BEGIN
IF rst ='1' THEN
wbm_ru_done <= '0';
wbm_ru_state <= IDLE;
wbm_ru_cyc <= '0';
ELSIF clk'EVENT AND clk ='1' THEN
CASE wbm_ru_state IS
WHEN IDLE =>
wbm_ru_done <= '0';
IF wbm_ru_start = '1' THEN
wbm_ru_state <= PER_REQ;
wbm_ru_cyc <= '1';
ELSE
wbm_ru_state <= IDLE;
wbm_ru_cyc <= '0';
END IF;
WHEN PER_REQ =>
IF wbm_ru_ack = '1' THEN
wbm_ru_state <= ACKNOWLEDGE;
wbm_ru_cyc <= '0';
wbm_ru_done <= '1';
ELSE
wbm_ru_state <= PER_REQ;
wbm_ru_cyc <= '1';
wbm_ru_done <= '0';
END IF;
WHEN ACKNOWLEDGE =>
wbm_ru_state <= IDLE;
wbm_ru_cyc <= '0';
wbm_ru_done <= '0';
-- coverage off
WHEN OTHERS =>
wbm_ru_state <= IDLE;
wbm_ru_cyc <= '0';
wbm_ru_done <= '0';
ASSERT FALSE REPORT "Undecoded State" SEVERITY WARNING;
-- coverage on
END CASE;
END IF;
END PROCESS z126_01_wbm_ru_fsm_proc;
-- state machine for generating wishbone master access from a wishbone slave access
z126_01_wbm_fsm_proc: PROCESS(clk, rst)
BEGIN
IF rst ='1' THEN
wbm_cyc_int <= '0';
wbm_done <= '0';
wbm_state <= IDLE;
ELSIF clk'EVENT AND clk ='1' THEN
CASE wbm_state IS
WHEN IDLE =>
wbm_done <= '0';
IF wbm_start = '1' THEN
wbm_state <= PER_REQ;
wbm_cyc_int <= '1';
ELSE
wbm_state <= IDLE;
wbm_cyc_int <= '0';
END IF;
WHEN PER_REQ =>
IF wbm_ack = '1' THEN
wbm_state <= ACKNOWLEDGE;
wbm_done <= '1';
wbm_cyc_int <= '0';
ELSE
wbm_state <= PER_REQ;
wbm_done <= '0';
wbm_cyc_int <= '1';
END IF;
WHEN ACKNOWLEDGE =>
wbm_state <= IDLE;
wbm_done <= '0';
wbm_cyc_int <= '0';
-- coverage off
WHEN OTHERS =>
wbm_state <= IDLE;
wbm_done <= '0';
wbm_cyc_int <= '0';
ASSERT FALSE REPORT "Undecoded State" SEVERITY WARNING;
-- coverage on
END CASE;
END IF;
END PROCESS z126_01_wbm_fsm_proc;
END z126_01_indi_if_ctrl_regs_arch;
| gpl-3.0 | 8c69440d2dfa77fe63db4c5ecedc6965 | 0.4494 | 4.15608 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/z091_01_wb_master.vhd | 1 | 39,113 | --------------------------------------------------------------------------------
-- Title : internal Wishbone master module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : wb_master.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 16.11.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- handles Wishbone accesses, writes data from rx_module and returns read
-- data to tx_module
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- * wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
library work;
use work.src_utils_pkg.all;
entity z091_01_wb_master is
generic(
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011"; -- = 1019 DW
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Rx Module
rx_fifo_wr_out : in std_logic_vector(31 downto 0);
rx_fifo_wr_empty : in std_logic;
rx_fifo_wr_rd_enable : out std_logic;
-- Tx Module
tx_fifo_c_head_full : in std_logic;
tx_fifo_c_data_full : in std_logic;
tx_fifo_c_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_c_head_enable : out std_logic;
tx_fifo_c_data_enable : out std_logic;
tx_fifo_c_head_in : out std_logic_vector(31 downto 0);
tx_fifo_c_data_in : out std_logic_vector(31 downto 0);
tx_fifo_c_data_clr : out std_logic;
tx_fifo_c_head_clr : out std_logic;
-- Wishbone
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic; -- wbm_tga(0)=1 if ECRC error occured
--wb_bar_dec : out std_logic_vector(6 downto 0); -- decoded BAR for wb_adr_dec.vhd mwawrik: no longer necessary
-- error
ecrc_err_in : in std_logic; -- input from error module
err_tag_id : in std_logic_vector(7 downto 0);
ecrc_err_out : out std_logic -- output of 16z091-01
);
end entity z091_01_wb_master;
-- ****************************************************************************
architecture z091_01_wb_master_arch of z091_01_wb_master is
component z091_01_wb_adr_dec
generic(
NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
);
port (
pci_cyc_i : in std_logic_vector(6 downto 0);
wbm_adr_o_q : in std_logic_vector(31 downto 2);
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
);
end component;
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
PREPARE_FIFO, IDLE, GET_HEADER_0, GET_HEADER_1, GET_HEADER_2, GET_WR_DATA, START_TRANS,
TRANSMIT, WAIT_ON_FIFO, PUT_HEADER_0, PUT_HEADER_1, PUT_HEADER_2, GET_Z
);
signal state : fsm_state;
-------------------------------------------------------------------------------
-- constants ------------------------------------------------------------------
constant ADDR_INCR : std_logic_vector(13 downto 0) := "00000000000100"; -- address increment for burst access
-------------------------------------------------------------------------------
-- internal signals -----------------------------------------------------------
signal get_data : std_logic;
signal decode_header : std_logic_vector(1 downto 0); -- 00 = idle, 01 = H0, 10 = H1, 11 = H3
signal data_to_wb : std_logic;
signal data_to_fifo : std_logic;
signal listen_to_ack : std_logic;
signal write_header : std_logic_vector(1 downto 0); -- 00 = idle, 01 = H0, 10 = H1, 11 = H3
signal wr_en_int : std_logic; -- write flag, 0 = read, 1 = write
signal attr_int : std_logic_vector(2 downto 0);
signal tc_int : std_logic_vector(2 downto 0);
signal req_id_int : std_logic_vector(15 downto 0);
signal addr_int : std_logic_vector(31 downto 0);
signal tag_id_int : std_logic_vector(7 downto 0);
signal first_dw_int : std_logic_vector(3 downto 0);
signal last_dw_int : std_logic_vector(3 downto 0);
signal length_int : std_logic_vector(9 downto 0);
signal data_q : std_logic_vector(31 downto 0);
signal data_qq : std_logic_vector(31 downto 0);
signal cnt_len_wb : std_logic_vector(10 downto 0); -- count amount of data tranfered through wishbone
signal cnt_len_fifo : std_logic_vector(10 downto 0); -- count amount of data taken from fifo
signal addr_offset : std_logic_vector(13 downto 0);
signal wait_clk : integer range 2 downto 0 := 0;
signal q_to_wbm : std_logic_vector(1 downto 0);
signal wbm_ack_int : std_logic;
signal err_tag_id_int : std_logic_vector(7 downto 0);
signal byte_count_int : std_logic_vector(11 downto 0);
signal suspend : std_logic;
signal goto_start : std_logic;
signal bar_dec_int : std_logic_vector(6 downto 0); -- decode which BAR was hit, only one bit may be set at a time
signal aligned_int : std_logic;
signal transmission : std_logic;
signal io_wr_int : std_logic;
signal wb_bar_dec_int : std_logic_vector(6 downto 0);
signal wb_bar_dec_int_d : std_logic_vector(6 downto 0);
signal ecrc_err_int : std_logic;
signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
-------------------------------------------------------------------------------
begin
z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
)
port map(
pci_cyc_i => wb_bar_dec_int,
wbm_adr_o_q => addr_int(31 downto 2),
wbm_cyc_o => wbm_cyc_o_int
);
wb_bar_dec_int <= bar_dec_int when (state = START_TRANS) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B
and tx_fifo_c_data_full = '0' and goto_start = '0') else
(OTHERS => '0') when (state = IDLE) or
(state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
state = GET_Z or state = PUT_HEADER_0
else
wb_bar_dec_int_d;
--wb_bar_dec <= wb_bar_dec_int_d; --mwawrik: no longer necessary because out-pin wb_bar_dec removed
ecrc_err_int <= '0' when wb_rst = '1' else
'0' when state = TRANSMIT else
'1' when state /= TRANSMIT and ecrc_err_in = '1';
-------------------------------------------------------------------------------
fsm_trans : process(wb_rst, wb_clk)
begin
if(wb_rst = '1') then
state <= IDLE;
elsif(wb_clk'event and wb_clk = '1') then
case state is
when IDLE =>
if(rx_fifo_wr_empty = '0') then
state <= PREPARE_FIFO;
else
state <= IDLE;
end if;
when PREPARE_FIFO =>
state <= GET_HEADER_0;
when GET_HEADER_0 =>
state <= GET_HEADER_1;
when GET_HEADER_1 =>
state <= GET_HEADER_2;
when GET_HEADER_2 =>
if((tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1') and wr_en_int = '0') then
state <= WAIT_ON_FIFO;
elsif(rx_fifo_wr_out(2) = '0') then
------------------------
-- transfer is aligned
------------------------
state <= GET_Z;
elsif(rx_fifo_wr_out(2) = '1' and wr_en_int = '1') then
state <= GET_WR_DATA;
elsif(rx_fifo_wr_out(2) = '1' and wr_en_int = '0') then
state <= START_TRANS;
end if;
when GET_WR_DATA =>
if(length_int = ONE_10B or ((length_int > ONE_10B or length_int = ZERO_10B) and wait_clk = 1)) then
state <= START_TRANS;
else
state <= GET_WR_DATA;
end if;
when START_TRANS =>
if(cnt_len_wb > ZERO_11B) then
state <= TRANSMIT;
elsif(cnt_len_wb <= ZERO_11B and wbm_ack = '1' and wr_en_int = '1') then
state <= IDLE;
elsif(cnt_len_wb <= ZERO_11B and (wbm_ack = '1' or wr_en_int = '0')) then
state <= START_TRANS;
end if;
when TRANSMIT =>
if(wbm_ack = '1' and (wr_en_int = '0' or (io_wr_int = '1' and aligned_int = '0')) and ((tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B) or cnt_len_wb = ZERO_11B)) then
state <= PUT_HEADER_0;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and wr_en_int = '1' and ((addr_int(2) = '0' and length_int(0) = '0') or
(addr_int(2) = '1' and length_int(0) = '1'))) then
state <= IDLE;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and wr_en_int = '1' and ((addr_int(2) = '0' and length_int(0) = '1') or
(addr_int(2) = '1' and length_int(0) = '0') or (io_wr_int = '1' and aligned_int = '1'))) then
state <= GET_Z;
else
state <= TRANSMIT;
end if;
when WAIT_ON_FIFO =>
if(tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and tx_fifo_c_data_full = '0' and goto_start = '1') then
state <= START_TRANS;
elsif(tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and tx_fifo_c_data_full = '0' and goto_start = '0') then
state <= TRANSMIT;
else
state <= WAIT_ON_FIFO;
end if;
when PUT_HEADER_0 =>
state <= PUT_HEADER_1;
when PUT_HEADER_1 =>
if(wr_en_int = '0' or io_wr_int = '1') then
state <= PUT_HEADER_2;
else
state <= IDLE;
end if;
when PUT_HEADER_2 =>
if(wait_clk = 1 and suspend = '0') then
state <= IDLE;
elsif(suspend = '1') then
state <= WAIT_ON_FIFO;
else
state <= PUT_HEADER_2;
end if;
when GET_Z =>
if(io_wr_int = '1' and aligned_int = '1' and transmission = '0') then
state <= PUT_HEADER_0;
elsif(transmission = '1' and wr_en_int = '1') then
state <= GET_WR_DATA;
elsif(transmission = '1' and wr_en_int = '0') then
state <= START_TRANS;
else
state <= IDLE;
end if;
-- coverage off
when others =>
-- synthesis translate_off
report "reached unknown FSM state in process fsm_trans of z091_01_wb_master.vhd" severity error;
-- synthesis translate_on
state <= IDLE;
-- coverage on
end case;
end if;
end process fsm_trans;
-------------------------------------------------------------------------------
fsm_out : process(wb_rst, wb_clk)
begin
if(wb_rst = '1') then
rx_fifo_wr_rd_enable <= '0';
tx_fifo_c_head_enable <= '0';
tx_fifo_c_data_enable <= '0';
tx_fifo_c_data_clr <= '1';
tx_fifo_c_head_clr <= '1';
wbm_stb <= '0';
wbm_cyc_o <= (others => '0');
wbm_we <= '0';
wbm_sel <= (others => '0');
wbm_adr <= (others => '0');
wbm_cti <= (others => '0');
wbm_tga <= '0';
ecrc_err_out <= '0';
get_data <= '0';
decode_header <= (others => '0');
data_to_wb <= '0';
data_to_fifo <= '0';
listen_to_ack <= '0';
write_header <= (others => '0');
cnt_len_wb <= (others => '0');
cnt_len_fifo <= (others => '0');
addr_offset <= (others => '0');
wait_clk <= 0;
q_to_wbm <= (others => '0');
wbm_ack_int <= '0';
err_tag_id_int <= x"FF"; -- init with a value greater than allowed 32 tags
byte_count_int <= (others => '0');
suspend <= '0';
goto_start <= '0';
aligned_int <= '0';
transmission <= '0';
elsif(wb_clk'event and wb_clk = '1') then
wb_bar_dec_int_d <= wb_bar_dec_int;
if(state = PREPARE_FIFO) then
transmission <= '1';
elsif(state = TRANSMIT) then
transmission <= '0';
end if;
-- determine data alignment which decides whether first packet after header2 is empty or contains first data packet
if(state = GET_HEADER_2 and rx_fifo_wr_out(2) = '0') then
aligned_int <= '1';
elsif(state = IDLE) then
aligned_int <= '0';
end if;
if((state = IDLE and rx_fifo_wr_empty = '1') or state = START_TRANS or state = WAIT_ON_FIFO or
(state = GET_Z and (transmission = '0' or wr_en_int = '0' or (wr_en_int = '1' and aligned_int = '1' and length_int = ONE_10B))) or
(state = GET_HEADER_2 and (wr_en_int = '0' or (wr_en_int = '1' and length_int = ONE_10B and rx_fifo_wr_out(2) = '1'))) or
(state = TRANSMIT and wbm_ack = '1' and cnt_len_fifo = ONE_11B) or
(state = GET_WR_DATA and ((length_int = TWO_10B and wait_clk = 0) or (length_int = THREE_10B and wait_clk = 1))) or
(state = TRANSMIT and wbm_ack = '0')
) then
rx_fifo_wr_rd_enable <= '0';
elsif((state = IDLE and rx_fifo_wr_empty = '0') or
(state = GET_Z and transmission = '1' and wr_en_int = '1') or
(state = TRANSMIT and wbm_ack = '1' and wr_en_int = '1' and ((cnt_len_wb = ZERO_11B and ((addr_int(2) = '0' and length_int(0) = '1') or
(addr_int(2) = '1' and length_int(0) = '0'))) or cnt_len_fifo > ONE_11B))) then
rx_fifo_wr_rd_enable <= '1';
end if;
if(state = IDLE or state = GET_Z or (state = WAIT_ON_FIFO and wait_clk = 1)) then
tx_fifo_c_head_enable <= '0';
elsif(state = PUT_HEADER_0) then
tx_fifo_c_head_enable <= '1';
end if;
if(state = IDLE or (state = PUT_HEADER_2 and length_int(0) = '1')) then
tx_fifo_c_data_enable <= '0';
elsif(state = TRANSMIT or state = PUT_HEADER_0 or (state = PUT_HEADER_1 and length_int(0) = '0') ) then
tx_fifo_c_data_enable <= wbm_ack_int;
end if;
if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
(state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ZERO_11B or (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and
cnt_len_wb /= ZERO_11B and wr_en_int = '0'))) ) then
wbm_stb <= '0';
elsif(state = START_TRANS or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0') ) then
wbm_stb <= '1';
end if;
--wbm_cyc never used before and now it is removed
--if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B) or
-- (state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ZERO_11B or (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and
-- cnt_len_wb /= ZERO_11B and wr_en_int = '0'))) ) then
-- wbm_cyc <= '0';
--elsif(state = START_TRANS or
-- (state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
-- tx_fifo_c_data_full = '0' and goto_start = '0') ) then
-- wbm_cyc <= '1';
--end if;
if(state = IDLE or (cnt_len_wb = ZERO_11B and wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')))) then
wbm_we <= '0';
elsif(state = START_TRANS and wr_en_int = '1') then
wbm_we <= '1';
end if;
if(state = IDLE or (cnt_len_wb = ZERO_11B and wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')))) then
wbm_sel <= (others => '0');
elsif(state = START_TRANS) then
wbm_sel <= first_dw_int;
elsif(state = TRANSMIT and wbm_ack = '1' and cnt_len_wb > ONE_11B) then
wbm_sel <= x"F";
elsif(state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ONE_11B) then
wbm_sel <= last_dw_int;
end if;
----------------------------------------
-- manage Wishbone address
-- add addr_offset during transmission
----------------------------------------
if(state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) then
wbm_adr <= addr_int + addr_offset;
--else
--wbm_adr <= addr_int;
end if;
-- calculate address offset
if(state = IDLE) then
addr_offset <= (others => '0');
elsif(state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) then
addr_offset <= addr_offset + ADDR_INCR;
end if;
-- add wbm_cyc_o to be registered
if((state = START_TRANS and suspend = '0' and length_int /= ONE_10B) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb > ZERO_11B) ) then
wbm_cti <= "010";
wbm_cyc_o <= wbm_cyc_o_int;
elsif((state = START_TRANS and suspend = '0' and length_int = ONE_10B) or
(state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ONE_11B or (tx_fifo_c_data_usedw = SUSPEND_FIFO_ACCESS and
wr_en_int = '0'))) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb <= ZERO_11B) ) then
wbm_cti <= "111";
wbm_cyc_o <= wbm_cyc_o_int;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')) ) then
wbm_cti <= "000";
wbm_cyc_o <= (OTHERS=>'0');
end if;
if(state = IDLE or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
wbm_tga <= '0';
elsif(state = START_TRANS and err_tag_id_int = tag_id_int) then
wbm_tga <= '1';
end if;
if(state = IDLE or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
ecrc_err_out <= '0';
elsif(state = START_TRANS and ecrc_err_int = '1' and err_tag_id_int = tag_id_int) then
ecrc_err_out <= '1';
end if;
if(state = IDLE or state = START_TRANS or (state = GET_HEADER_2 and wr_en_int = '0') or (state = GET_WR_DATA and length_int = ONE_10B) or
(state = TRANSMIT and ((wbm_ack = '0' or wr_en_int = '0' or cnt_len_wb = ZERO_11B) or (wbm_ack = '1' and cnt_len_wb = ZERO_11B))) ) then
get_data <= '0';
elsif((state = GET_HEADER_2 and rx_fifo_wr_out(2) = '1' and wr_en_int = '1') or (state = GET_WR_DATA and length_int /= ONE_10B) or
(state = TRANSMIT and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb > ZERO_11B) or
(state = GET_Z and aligned_int = '1' and wr_en_int = '1')
) then
get_data <= '1';
end if;
if(state = IDLE or state = GET_WR_DATA or state = START_TRANS or state = GET_HEADER_2) then
decode_header <= (others => '0');
elsif(state = PREPARE_FIFO) then
decode_header <= "01";
elsif(state = GET_HEADER_0) then
decode_header <= "10";
elsif(state = GET_HEADER_1) then
decode_header <= "11";
end if;
if(state = IDLE or state = START_TRANS or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
data_to_wb <= '0';
elsif(state = GET_WR_DATA and wr_en_int = '1' and (length_int = ONE_10B or wait_clk = 1)) then
data_to_wb <= '1';
end if;
if(state = IDLE or (state = START_TRANS and wbm_ack = '1' and wr_en_int = '1' and cnt_len_wb = ZERO_11B)) then
data_to_fifo <= '0';
elsif(wr_en_int = '0' and (state = START_TRANS or state = TRANSMIT)) then
data_to_fifo <= '1';
end if;
if(state = IDLE or
(wbm_ack = '1' and cnt_len_wb = ZERO_11B and ((state = START_TRANS and wr_en_int = '1') or state = TRANSMIT)) ) then
listen_to_ack <= '0';
elsif(state = START_TRANS and wr_en_int = '1') then
listen_to_ack <= '1';
end if;
if(state = IDLE) then
write_header <= (others => '0');
elsif(state = TRANSMIT and wbm_ack = '1' and (wr_en_int = '0' or io_wr_int = '1') and (cnt_len_wb = ZERO_11B or
(tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B)) ) then
write_header <= "01";
elsif(state = PUT_HEADER_0) then
write_header <= "10";
elsif(state = PUT_HEADER_1 and (wr_en_int = '0' or io_wr_int = '1')) then
write_header <= "11";
end if;
-- calculate length counters for Wishbone transactions and decrement when necessary
if(state = IDLE) then
cnt_len_wb <= (others => '0');
elsif(state = GET_HEADER_1 and length_int = ZERO_10B) then
cnt_len_wb <= '1' & length_int;
elsif(state = GET_HEADER_1 and length_int /= ZERO_10B) then
cnt_len_wb <= '0' & length_int;
elsif(cnt_len_wb > ZERO_11B and (state = START_TRANS or (state = TRANSMIT and wbm_ack = '1')) ) then
cnt_len_wb <= cnt_len_wb - ONE_11B;
end if;
-- calculate length counters for FIFO transactions and decrement when necessary
if(state = IDLE) then
cnt_len_fifo <= (others => '0');
elsif(state = GET_HEADER_1 and length_int = ZERO_10B) then
cnt_len_fifo <= '1' & length_int;
elsif(state = GET_HEADER_1 and length_int /= ZERO_10B) then
cnt_len_fifo <= '0' & length_int;
elsif(wr_en_int = '1' and cnt_len_fifo > ZERO_11B and (state = GET_WR_DATA or state = START_TRANS or
(state = TRANSMIT and wbm_ack = '1')) ) then
cnt_len_fifo <= cnt_len_fifo - ONE_11B;
end if;
if(state = IDLE or state = GET_HEADER_1 or state = PUT_HEADER_1 or (state = PUT_HEADER_2 and suspend = '1') or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0') ) then
wait_clk <= 0;
elsif(state = GET_WR_DATA or (state = WAIT_ON_FIFO and wait_clk < 1) or (state = PUT_HEADER_2 and suspend = '0')) then
wait_clk <= wait_clk + 1;
end if;
if(state = IDLE) then
q_to_wbm <= (others => '0');
elsif((state = GET_HEADER_1 and length_int = ONE_10B) or (state = TRANSMIT and wbm_ack = '1')) then
q_to_wbm <= "01";
elsif((state = GET_HEADER_1 and length_int /= ONE_10B) or (state = TRANSMIT and wbm_ack = '0')) then
q_to_wbm <= "10";
end if;
if(state = IDLE or (wbm_ack = '0' and wr_en_int = '0' and (state = TRANSMIT or state = PUT_HEADER_0 or state = PUT_HEADER_1))) then
wbm_ack_int <= '0';
elsif(wbm_ack = '1' and wr_en_int = '0' and (state = TRANSMIT or state = PUT_HEADER_0 or state = PUT_HEADER_1)) then
wbm_ack_int <= '1';
end if;
-- capture ecrc error
if(state = IDLE and ecrc_err_in = '0') then
err_tag_id_int <= (others => '0');
elsif(ecrc_err_in = '1' and (state = IDLE or state = GET_HEADER_0 or state = GET_HEADER_1 or state = GET_HEADER_2 or
state = GET_WR_DATA)) then
err_tag_id_int <= err_tag_id;
end if;
-- calculate byte count
-- correct byte count value according to first_dw_int value as defined in PCIe base specification in state PUT_HEADER_0
if(state = IDLE) then
byte_count_int <= (others => '0');
elsif(wbm_ack = '1' and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1' and cnt_len_wb = 0))) then
byte_count_int <= byte_count_int + FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and (first_dw_int = ZERO_04B or first_dw_int = EIGHT_04B or first_dw_int = FOUR_04B or first_dw_int = TWO_04B or first_dw_int = ONE_04B)) then
byte_count_int <= ONE_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and (first_dw_int = C_04B or first_dw_int = SIX_04B or first_dw_int = THREE_04B)) then
byte_count_int <= TWO_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and ((first_dw_int(3) = '1' and first_dw_int(1 downto 0) = TWO_02B) or (first_dw_int(3 downto 2) = ONE_02B and first_dw_int(0) = '1'))) then
byte_count_int <= THREE_12B;
elsif(state = PUT_HEADER_0 and length_int = ONE_10B and first_dw_int(3) = '1' and first_dw_int(0) = '1') then
byte_count_int <= FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int(1 downto 0) = TWO_02B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - ONE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(1 downto 0) = TWO_02B and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - TWO_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(0) = '1' and last_dw_int = ONE_04B) or (first_dw_int(1 downto 0) = ONE_02B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3 downto 2) = ONE_02B) or (first_dw_int = EIGHT_04B and last_dw_int(3) = '1'))) then
byte_count_int <= byte_count_int - THREE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int(1 downto 0) = TWO_02B and last_dw_int = ONE_04B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int = EIGHT_04B and last_dw_int(3 downto 2) = ONE_02B))) then
byte_count_int <= byte_count_int - FOUR_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and ((first_dw_int = EIGHT_04B and last_dw_int(3 downto 1) = ONE_03B) or (first_dw_int(2 downto 0) = FOUR_03B and last_dw_int = ONE_04B))) then
byte_count_int <= byte_count_int - FIVE_12B;
elsif(state = PUT_HEADER_0 and length_int /= ONE_10B and first_dw_int = EIGHT_04B and last_dw_int = ONE_04B) then
byte_count_int <= byte_count_int - SIX_12B;
end if;
-- suspend all actions when FIFO is full until there is space in FIFO again
if(state = IDLE or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0')) then
suspend <= '0';
elsif((state = GET_HEADER_2 and (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1') and wr_en_int = '0') or
(state = TRANSMIT and wbm_ack = '1' and tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS and cnt_len_wb /= ZERO_11B and
wr_en_int = '0')) then
suspend <= '1';
end if;
if(state = IDLE or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '1')) then
goto_start <= '0';
elsif(state = GET_HEADER_2 and (tx_fifo_c_data_usedw > SUSPEND_FIFO_ACCESS or tx_fifo_c_data_full = '1')) then
goto_start <= '1';
end if;
if(state = IDLE) then
tx_fifo_c_data_clr <= '0';
tx_fifo_c_head_clr <= '0';
end if;
end if;
end process fsm_out;
-------------------------------------------------------------------------------
data_path : process(wb_clk, wb_rst, wbm_ack)
begin
if(wb_rst = '1') then
-- ports:
tx_fifo_c_head_in <= (others => '0');
tx_fifo_c_data_in <= (others => '0');
wbm_dat_o <= (others => '0');
-- signals:
data_q <= (others => '0');
data_qq <= (others => '0');
wr_en_int <= '0';
attr_int <= (others => '0');
tc_int <= (others => '0');
req_id_int <= (others => '0');
addr_int <= (others => '0');
tag_id_int <= (others => '0');
first_dw_int <= (others => '0');
last_dw_int <= (others => '0');
length_int <= (others => '0');
bar_dec_int <= (others => '0');
io_wr_int <= '0';
else
if(wb_clk'event and wb_clk = '1') then
if(decode_header = "01") then
-- decode which BAR was hit
case rx_fifo_wr_out(28 downto 26) is
when "000" =>
bar_dec_int(0) <= '1';
bar_dec_int(6 downto 1) <= (others => '0');
when "001" =>
bar_dec_int(0) <= '0';
bar_dec_int(1) <= '1';
bar_dec_int(6 downto 2) <= (others => '0');
when "010" =>
bar_dec_int(1 downto 0) <= (others => '0');
bar_dec_int(2) <= '1';
bar_dec_int(6 downto 3) <= (others => '0');
when "011" =>
bar_dec_int(2 downto 0) <= (others => '0');
bar_dec_int(3) <= '1';
bar_dec_int(6 downto 4) <= (others => '0');
when "100" =>
bar_dec_int(3 downto 0) <= (others => '0');
bar_dec_int(4) <= '1';
bar_dec_int(6 downto 5) <= (others => '0');
when "101" =>
bar_dec_int(4 downto 0) <= (others => '0');
bar_dec_int(5) <= '1';
bar_dec_int(6) <= '0';
when "110" =>
bar_dec_int(5 downto 0) <= (others => '0');
bar_dec_int(6) <= '1';
-- coverage off
when others =>
bar_dec_int <= (0 => '1', others => '0');
-- synthesis translate_off
report "Error while decoding BAR" severity error;
-- synthesis translate_on
-- coverage on
end case;
-- split value of data bus into its components
wr_en_int <= rx_fifo_wr_out(31);
io_wr_int <= rx_fifo_wr_out(30) and rx_fifo_wr_out(31);
first_dw_int <= rx_fifo_wr_out(17 downto 14);
last_dw_int <= rx_fifo_wr_out(13 downto 10);
length_int <= rx_fifo_wr_out(9 downto 0);
tag_id_int <= rx_fifo_wr_out(25 downto 18);
elsif(decode_header = "10") then
attr_int <= rx_fifo_wr_out(21 downto 19);
tc_int <= rx_fifo_wr_out(18 downto 16);
req_id_int <= rx_fifo_wr_out(15 downto 0);
elsif(decode_header = "11") then
addr_int <= rx_fifo_wr_out;
end if;
-- manage data registering pipeline
if(get_data = '1' and wr_en_int = '1') then
data_q <= rx_fifo_wr_out;
data_qq <= data_q;
elsif(get_data = '1' and wr_en_int = '0') then
data_q <= wbm_dat_i;
end if;
-- route registered data signals to output port
if(listen_to_ack = '1' and wbm_ack = '1') then
case q_to_wbm is
when "01" =>
wbm_dat_o <= data_q;
when "10" =>
wbm_dat_o <= data_qq;
when "11" =>
-- coverage off
when others =>
-- synthesis translate_off
report "Reached undecoded state of signal q_to_wbm" severity error;
-- synthesis translate_on
-- coverage on
end case;
elsif(data_to_wb = '1') then
case q_to_wbm is
when "01" =>
wbm_dat_o <= data_q;
when "10" =>
wbm_dat_o <= data_qq;
when "11" =>
-- coverage off
when others =>
-- synthesis translate_off
report "Reached undecoded state of signal q_to_wbm" severity error;
-- synthesis translate_on
-- coverage on
end case;
elsif(data_to_fifo = '1') then
data_q <= wbm_dat_i;
tx_fifo_c_data_in <= data_q;
end if;
-- asseble tx data packet
if(write_header = "01") then
tx_fifo_c_head_in(31 downto 29) <= attr_int;
tx_fifo_c_head_in(28 downto 26) <= tc_int;
tx_fifo_c_head_in(25 downto 18) <= tag_id_int;
tx_fifo_c_head_in(17 downto 14) <= first_dw_int;
tx_fifo_c_head_in(13 downto 10) <= last_dw_int;
tx_fifo_c_head_in(9 downto 0) <= length_int;
elsif(write_header = "10") then
tx_fifo_c_head_in <= addr_int;
elsif(write_header = "11") then
tx_fifo_c_head_in(31 downto 29) <= (others => '0');
tx_fifo_c_head_in(28) <= io_wr_int;
if(io_wr_int = '1') then
tx_fifo_c_head_in(27 downto 16) <= "000000000100";
else
tx_fifo_c_head_in(27 downto 16) <= byte_count_int;
end if;
tx_fifo_c_head_in(15 downto 0) <= req_id_int;
else
tx_fifo_c_head_in <= (others => '0');
end if;
end if;
end if;
end process data_path;
-------------------------------------------------------------------------------
end architecture z091_01_wb_master_arch;
| gpl-3.0 | 1d88fe8f6e841716dfd2474311b26092 | 0.470099 | 3.562204 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/dma_sg_cmp.vhd | 2 | 18,692 | -------------------------------------------------------------------------------
-- $Id: dma_sg_cmp.vhd,v 1.2 2003/03/12 01:04:29 ostlerf Exp $
-------------------------------------------------------------------------------
-- Package with component declarations to support the DMA Scatter/Gather entity
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg_cmp.vhd
--
-- Description: Components instantiated within dma_sg are declared here.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg_cmp.vhds
-- dma_sg_pkg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- FLO 01/30/03
-- ^^^^^^
-- Changed the dma_sg component to correspond to a changes made to the entity
-- when fixed DMASG as a 32-bit device.
-- ~~~~~~
--
-- FLO 03/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.INTEGER_ARRAY_TYPE;
package dma_sg_cmp is
component dma_sg is
-- Four channel, 0123, simple sg tx rx coalesc.
generic (
C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
C_IPIF_ABUS_WIDTH : natural :=15;
C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
-- The time unit, in nanoseconds, that applies to
-- the Packet Wait Bound register. The specified value of this
-- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- simulations.
C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
: INTEGER_ARRAY_TYPE
:= ( 0, 1, 2, 3 );
-- The leftmost defined bit of the LENGTH field, assuming
-- big endian bit numbering and a LSB at bit 31.
-- If the channel is a packet channel, it is assumed that
-- the number bits defined in the LENGTH register is also
-- enough bits to hold the length of a maximum sized packet.
-- ToDo, current impl requires all channels to be the same length.
C_DMA_LENGTH_WIDTH
: INTEGER_ARRAY_TYPE
:= ( 11, 11, 11, 11 );
C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 3)
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3800",
X"0000_0000_0000_4800" );
C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 3)
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3804",
X"0000_0000_0000_4804" );
C_INTR_COALESCE
: INTEGER_ARRAY_TYPE
:= ( 0, 0, 1, 1 );
C_DEV_BLK_ID : integer := 0;
C_DMA_BASEADDR : std_logic_vector
:= X"0000_0000_0000_0000";
C_DMA_ALLOW_BURST : boolean := true;
C_MA2SA_NUM_WIDTH : INTEGER := 4;
C_WFIFO_VACANCY_WIDTH : integer := 10
);
-- Two channel, 23, tx rx coalesc.
-- generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 10000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 2, 3 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1800",
-- X"0000_0000_0000_2800" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1804",
-- X"0000_0000_0000_2804" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 1, 1 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_ALLOW_BURST : boolean := true;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- Two channel, 00, simple DMA only
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_ALLOW_BURST : boolean := 1;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- Three channel, 000, simple DMA only
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0, 0 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0, 0 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_ALLOW_BURST : boolean := 1;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- One channel version. (under construction)
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 2, 3 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1800", X"0000_0000_0000_2800" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1804", X"0000_0000_0000_2804" );
--
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 1, 1 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_ALLOW_BURST : boolean := true;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
port (
DMA2Bus_Data : out std_logic_vector(0 to 31);
DMA2Bus_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1 );
DMA2Bus_MstBE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
DMA2Bus_MstWrReq : out std_logic;
DMA2Bus_MstRdReq : out std_logic;
DMA2Bus_MstNum : out std_logic_vector(
0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : out std_logic;
DMA2Bus_MstBusLock : out std_logic;
DMA2Bus_MstLoc2Loc : out std_logic;
DMA2IP_Addr : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
DMA2Bus_WrAck : out std_logic;
DMA2Bus_RdAck : out std_logic;
DMA2Bus_Retry : out std_logic;
DMA2Bus_Error : out std_logic;
DMA2Bus_ToutSup : out std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Mstr_sel_ma : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Freeze : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_Burst : in std_logic;
WFIFO2DMA_Vacancy : in std_logic_vector(0 to C_WFIFO_VACANCY_WIDTH-1);
Bus2IP_MstLastAck : in std_logic;
DMA_RdCE : in std_logic;
DMA_WrCE : in std_logic;
IP2DMA_RxStatus_Empty : in std_logic;
IP2DMA_RxLength_Empty : in std_logic;
IP2DMA_TxStatus_Empty : in std_logic;
IP2DMA_TxLength_Full : in std_logic;
IP2Bus_DMA_Req : in std_logic;
Bus2IP_DMA_Ack : out std_logic;
DMA2Intr_Intr : out std_logic_vector(0 to 1)
);
end component;
component ctrl_reg_0_to_6
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector(0 to 6);
q : out std_logic_vector(0 to 6)
);
end component;
component ctrl_reg_0_to_0
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
-- XGR_E33 d : in std_logic_vector(0 to 0);
-- XGR_E33 q : out std_logic_vector(0 to 0)
d : in std_logic;
q : out std_logic
);
end component;
component SRL_FIFO
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end component;
component ld_arith_reg
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset to left (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset to left of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end component;
end package;
| bsd-3-clause | 745de2e1e25bc9644be94ed886810292 | 0.461962 | 3.628106 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/queue/zcpsm2fifo.vhd | 1 | 3,023 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity zcpsm2fifo is
generic(
BLOCK_AWIDTH : integer;
DWIDTH : integer
);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
fifo_wr_block : out std_logic;
fifo_wren : out std_logic;
fifo_waddr : out std_logic_vector(BLOCK_AWIDTH - 1 downto 0);
fifo_wdata : out std_logic_vector(DWIDTH - 1 downto 0);
fifo_full : in std_logic;
fifo_empty : in std_logic
);
end entity;
architecture behave of zcpsm2fifo is
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
signal zcpsm_we : std_logic;
signal zcpsm_re : std_logic;
signal zcpsm_addr : std_logic_vector(3 downto 0);
signal wr_block_en : std_logic;
signal fifo_waddr_reg : std_logic_vector(BLOCK_AWIDTH - 1 downto 0);
-- signal flag_LastFrame : std_logic;
constant PORT_IO_ADDR : std_logic_vector(3 downto 0) := X"0";
constant PORT_IO_DATA : std_logic_vector(3 downto 0) := X"1";
constant PORT_QUEUE_STATUS : std_logic_vector(3 downto 0) := X"2";
-- constant PORT_LAST_FRAME : std_logic_vector(3 downto 0) := X"3";
constant PORT_WR_BLOCK : std_logic_vector(3 downto 0) := X"4";
begin
zcpsm_we <= zcpsm_ce and zcpsm_write_strobe;
zcpsm_re <= zcpsm_ce and zcpsm_read_strobe;
zcpsm_addr <= '0' & zcpsm_port_id(3 downto 1);
zcpsm_in_port <= "000000" & fifo_empty & fifo_full when zcpsm_ce = '1' and zcpsm_addr = PORT_QUEUE_STATUS else (others => 'Z');
-- flag_LastFrame <= '1' when zcpsm_ce = '1' and zcpsm_addr = PORT_LAST_FRAME else '0';
u_wr_block : asyncwrite
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => wr_block_en,
trigger => '1',
sync_wren => fifo_wr_block,
over => open,
flag => open
);
wr_block_en <= '1' when zcpsm_we = '1' and zcpsm_addr = PORT_WR_BLOCK else '0';
process(zcpsm_clk, reset)
begin
if reset = '1' then
fifo_waddr_reg <= (others => '0');
elsif rising_edge(zcpsm_clk) then
if zcpsm_we = '1' and zcpsm_addr = PORT_IO_ADDR then
fifo_waddr_reg <= zcpsm_out_port(BLOCK_AWIDTH - 1 downto 0);
elsif zcpsm_we = '1' and zcpsm_addr = PORT_IO_DATA then
fifo_waddr_reg <= fifo_waddr_reg + 1;
end if;
end if;
end process;
fifo_wren <= '1' when zcpsm_we = '1' and zcpsm_addr = PORT_IO_DATA else '0';
fifo_waddr <= fifo_waddr_reg;
fifo_wdata <= zcpsm_out_port;
end behave;
| gpl-2.0 | dea44da08c5a377cd9e30741ff4514a6 | 0.625868 | 2.60379 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/dma/tx_dma_ctrl.vhd | 1 | 5,607 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_ctrl is
generic(
DWIDTH : natural; -- 8
RD_CYCLE : natural; -- 1
RD_DELAY : natural; -- 1
RAM_AWIDTH : natural
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- start_raddr : in std_logic_vector(23 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
-- raddr : out std_logic_vector(23 downto 0);
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector(DWIDTH - 1 downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector(DWIDTH - 1 downto 0)
);
end entity;
architecture behave of dma_ctrl is
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
signal length_reg : std_logic_vector(15 downto 0);
signal start_waddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal start_raddr_reg : std_logic_vector(23 downto 0);
signal start_raddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal wstep_reg : std_logic_vector(7 downto 0);
signal rstep_reg : std_logic_vector(7 downto 0);
signal busy_buf : std_logic;
signal cycle_cnt : std_logic_vector(7 downto 0);
signal cnt : std_logic_vector(15 downto 0);
signal rden_buf : std_logic;
-- signal raddr_buf : std_logic_vector(23 downto 0);
signal raddr_buf : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal wren_buf : std_logic;
signal waddr_buf : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal rd_start : std_logic;
signal wr_start : std_logic;
signal rd_ctrl : std_logic_vector(1 downto 0);
signal wr_ctrl : std_logic_vector(1 downto 0);
begin
-- DMA Status
process(clk, reset)
begin
if reset = '1' then
length_reg <= (others => '0');
start_waddr_reg <= (others => '0');
start_raddr_reg <= (others => '0');
wstep_reg <= (others => '0');
rstep_reg <= (others => '0');
elsif rising_edge(clk) then
if start = '1' then
length_reg <= length;
start_waddr_reg <= start_waddr;
start_raddr_reg <= start_raddr;
wstep_reg <= wstep;
rstep_reg <= rstep;
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
busy_buf <= '0';
elsif rising_edge(clk) then
if start = '1' then
busy_buf <= '1';
elsif cnt = length_reg and cycle_cnt = RD_CYCLE - 1 then
busy_buf <= '0';
end if;
end if;
end process;
busy <= busy_buf;
process(clk, reset)
begin
if reset = '1' then
cycle_cnt <= (others => '0');
elsif rising_edge(clk) then
if busy_buf = '1' and ena = '1' then
if cycle_cnt = RD_CYCLE - 1 then
cycle_cnt <= (others => '0');
else
cycle_cnt <= cycle_cnt + 1;
end if;
else
cycle_cnt <= (others => '0');
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
cnt <= X"0000";
elsif rising_edge(clk) then
if start = '1' then
cnt <= X"0001";
elsif busy_buf = '1' and ena = '1' and cycle_cnt = RD_CYCLE - 1 then
cnt <= cnt + 1;
end if;
end if;
end process;
-- Read Ctrl
process(clk, reset)
begin
if reset = '1' then
rden_buf <= '0';
elsif rising_edge(clk) then
if busy_buf = '1' and ena = '1' and cycle_cnt = RD_CYCLE - 1 and cnt < length_reg then
rden_buf <= '1';
else
rden_buf <= '0';
end if;
end if;
end process;
-- process(clk, reset)
-- begin
-- if reset = '1' then
-- raddr_buf <= (others => '0');
-- elsif rising_edge(clk) then
-- if rd_start = '1' then
-- raddr_buf <= start_raddr_reg;
-- elsif rden_buf = '1' then
-- raddr_buf <= raddr_buf + rstep_reg;
-- end if;
-- end if;
-- end process;
process(clk, reset)
begin
if reset = '1' then
raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if rd_start = '1' then
raddr_buf <= start_raddr_reg;
elsif rden_buf = '1' then
raddr_buf <= raddr_buf + rstep_reg;
end if;
end if;
end process;
raddr <= raddr_buf;
-- Write Ctrl
u_wr_ctrl : shiftreg
generic map(
width => 2,
depth => RD_DELAY + RD_CYCLE -- 100M RD_DELAY ??? a4a881d4
)
port map(
clk => clk,
ce => '1',
D => rd_ctrl,
Q => wr_ctrl,
S => open
);
rd_ctrl(0) <= rden_buf;
rd_ctrl(1) <= rd_start;
wren_buf <= wr_ctrl(0);
wr_start <= wr_ctrl(1);
process(clk, reset)
begin
if reset = '1' then
waddr_buf <= (others => '0');
elsif rising_edge(clk) then
if wr_start = '1' then
waddr_buf <= start_waddr_reg;
elsif wren_buf = '1' then
waddr_buf <= waddr_buf + wstep_reg;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
rd_start <= start;
wren <= wr_start or wren_buf;
end if;
end process;
waddr <= waddr_buf;
wdata <= rdata;
end behave;
| gpl-2.0 | 3cb7e51f856718306edfd48ab53442aa | 0.573569 | 2.657346 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/bram_if_cntlr_v1_00_a/hdl/vhdl/bram_if.vhd | 2 | 11,456 | -------------------------------------------------------------------------------
-- $Id: bram_if.vhd,v 1.4 2003/05/20 21:22:04 anitas Exp $
-------------------------------------------------------------------------------
-- bram_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: bram_if.vhd
-- Version: v1.00a
-- Description: This design module is for a simple byte addressable memory
-- using the Xilinx BRAM primitives present in Xilinx FPGA
-- devices.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- bram_if.vhd
-------------------------------------------------------------------------------
-- Author: DAB
-- Revision: $Revision: 1.4 $
-- Date: $4/5/2002$
--
-- History:
-- dab 6/12/2002 Initial Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v1_00_b;
Use proc_common_v1_00_b.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_IPIF_DWIDTH -- IPIC data width
-- C_IPIF_AWIDTH -- IPIC address width
--
-- Definition of Ports:
-- -- Clock and reset
-- bus_reset -- Reset
-- bus_clk -- PLB/OPB clock
-- -- IPIC
-- Bus2IP_BE -- Processor bus byte enables
-- Bus2IP_Addr -- Processor bus address
-- Bus2IP_Data -- Processor data
-- Bus2IP_BRAM_CS -- BRAM is being accessed
-- Bus2IP_RNW -- Processor read not write
-- Bus2IP_WrReq -- Processor write request
-- Bus2IP_RdReq -- Processor read request
--
-- -- IPIC outputs
-- IP2Bus_Data -- Data to processor bus
-- IP2Bus_RdAck -- Read acknowledge
-- IP2Bus_WrAck -- Write acknowledge
-- IP2Bus_Retry -- Retry indicator
-- IP2Bus_ToutSup -- Suppress watch dog timer
--
-- -- BRAM interface signals
-- BRAM_Rst -- BRAM reset
-- BRAM_CLK -- BRAM clock
-- BRAM_EN -- BRAM chip enable
-- BRAM_WEN -- BRAM write enable
-- BRAM_Addr -- BRAM address
-- BRAM_Dout -- BRAM write data
-- BRAM_Din -- BRAM read data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity bram_if is
generic (
C_IPIF_AWIDTH : Integer := 32;
-- The width if the IPIF address bus
C_IPIF_DWIDTH : Integer := 64
-- The width of the IPIF data bus
);
port (
-- input ports
bus_reset : in std_logic;
bus_clk : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_BRAM_CS : in std_logic;
Bus2IP_RNW : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
-- Output ports
IP2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
--BRAM Ports
BRAM_Rst : out std_logic;
BRAM_CLK : out std_logic;
BRAM_EN : out std_logic;
BRAM_WEN : out std_logic_vector(0 to C_IPIF_DWIDTH/8-1); --Qualified WE
BRAM_Addr : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
BRAM_Dout : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
BRAM_Din : in std_logic_vector(0 to C_IPIF_DWIDTH-1)
);
end entity bram_if;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of bram_if is
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function "and" ( l : std_logic_vector; r : std_logic )
return std_logic_vector is
variable rex : std_logic_vector(l'range);
begin
rex := (others=>r);
return( l and rex );
end function "and";
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
signal IP2Bus_Data_i : std_logic_vector(0 to C_IPIF_DWIDTH-1);
Signal IP2Bus_RdAck_i : std_logic;
Signal IP2Bus_WrAck_i : std_logic;
Signal address_bus_i : std_logic_vector(0 to C_IPIF_AWIDTH-1);
Signal write_data_i : std_logic_vector(0 to C_IPIF_DWIDTH-1);
Signal read_data_i : std_logic_vector(0 to C_IPIF_DWIDTH-1);
Signal read_enable : std_logic;
Signal read_enable_dly1 : std_logic;
Signal BRAM_QWEN : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin -- (architecture implementation)
-- (Misc Assignments)
address_bus_i <= Bus2IP_ADDR;
write_data_i <= Bus2IP_Data;
read_enable <= Bus2IP_BRAM_CS and Bus2IP_RdReq;
IP2Bus_Data <= IP2Bus_Data_i;
IP2Bus_RdAck <= IP2Bus_RdAck_i;
IP2Bus_WrAck <= Bus2IP_BRAM_CS and Bus2IP_WrReq;
IP2Bus_Retry <= '0';
IP2Bus_Error <= '0';
IP2Bus_ToutSup <= '0';
BRAM_QWEN <= (Bus2IP_BE and Bus2IP_WrReq);
-------------------------------------------------------------
-- Synchronous Process
--
-- Label: GEN_RD_ACK
--
-- Process Description:
-- This process generates the read acknowledge 1 clock after
-- read enable signal is presented to the BRAM block. The
-- BRAM block primitive has a 1 clock delay from read enable
-- to data out.
---------------------------------------------------------------
GEN_RD_ACK : process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (bus_reset = '1') then
read_enable_dly1 <= '0';
else
read_enable_dly1 <= read_enable;
end if;
if (bus_reset = '1') then
IP2Bus_RdAck_i <= '0';
elsif (read_enable_dly1 = '0' and
read_enable = '1') then
IP2Bus_RdAck_i <= '1';
else
IP2Bus_RdAck_i <= '0';
end if;
else
null;
end if;
end process GEN_RD_ACK;
-------------------------------------------------------------
-- Assign the read data
--
-- No mux is necessary since the bram data is the only data
-- source
-------------------------------------------------------------
IP2Bus_Data_i <= read_data_i;
------------------------------------------------------------
-- Label: CONNECT_BRAM
--
-- Concurrent signal assignments to connect the BRAM
-- interface
------------------------------------------------------------
-- Port A signals
BRAM_Rst <= bus_reset;
BRAM_Clk <= bus_clk;
BRAM_EN <= Bus2IP_BRAM_CS;
BRAM_WEN <= BRAM_QWEN;
BRAM_Addr <= address_bus_i;
BRAM_Dout <= write_data_i;
read_data_i <= BRAM_Din;
end implementation;
| bsd-3-clause | 43d845d58c0127844c8bde9b80542f7e | 0.409829 | 4.571429 | false | false | false | false |
jevinskie/aes-over-pcie | source/key_scheduler.vhd | 1 | 9,583 | -- File name: key_scheduler.vhd
-- Created: 2009-03-30
-- Author: Matt Swanson
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael KeyScheduler
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity key_scheduler is
port (
clk : in std_logic;
nrst : in std_logic;
go : in std_logic;
round : in round_type;
key_data : in byte;
key_index : in g_index;
key_load : in std_logic;
round_key : out key_type;
done : out std_logic
);
type rcon_array is array (0 to 10) of byte;
constant rcon_tbl : rcon_array :=
(
x"8d", x"01", x"02", x"04", x"08", x"10", x"20", x"40",
x"80", x"1b", x"36"
);
end key_scheduler;
architecture behavioral of key_scheduler is
type state_type is (
idle, load_key, rotate, sub_bytes, add_cols, rcon, be_done
);
signal state : state_type;
signal next_state : state_type;
signal cur_key : key_type;
signal next_cur_key : key_type;
signal new_key : key_type;
signal next_new_key : key_type;
signal c : index;
signal next_c : index;
signal c_clr : std_logic;
signal c_up : std_logic;
signal r : index;
signal next_r : index;
signal r_clr : std_logic;
signal sbox_return_reged : byte;
signal sbox_lookup, sbox_return : byte;
begin
sbox_b : entity work.sbox(dataflow) port map (
clk => clk, a => sbox_lookup, b => sbox_return
);
-- leda C_1406 off
state_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
cur_key <= next_cur_key;
new_key <= next_new_key;
end if;
end process state_reg;
-- leda C_1406 on
state_nsl : process(state, go, r, c, round)
begin
next_state <= idle;
case state is
when idle =>
if (go = '1' and round = 0) then
next_state <= load_key;
elsif (go = '1') then
next_state <= rotate;
else
next_state <= idle;
end if;
when load_key =>
next_state <= be_done;
when rotate =>
next_state <= sub_bytes;
when sub_bytes =>
if (r /= 3) then
next_state <= sub_bytes;
else
next_state <= rcon;
end if;
when rcon =>
next_state <= add_cols;
when add_cols =>
if (r = 3 and c = 3) then
next_state <= be_done;
else
next_state <= add_cols;
end if;
when be_done =>
next_state <= idle;
end case;
end process state_nsl;
state_out : process(state, cur_key, new_key, key_data,
key_index, key_load,
sbox_return_reged, c, r, round)
variable temp_index : index;
begin
next_cur_key <= cur_key;
next_new_key <= new_key;
c_up <= '0';
c_clr <= '0';
r_clr <= '0';
done <= '0';
sbox_lookup <= (others => '-');
case state is
when idle =>
if (key_load = '1') then
next_new_key(key_index mod 4, key_index / 4) <= key_data;
end if;
when load_key =>
-- nothing
when rotate =>
r_clr <= '1';
c_clr <= '1';
sbox_lookup <= cur_key(1, 3);
for i in index loop
next_new_key(i, 0) <= cur_key(to_integer(to_unsigned(i, 2) + 1), 3);
end loop;
when sub_bytes =>
sbox_lookup <= new_key(to_integer(to_unsigned(r, 2) + 1), 0);
next_new_key(r, c) <= sbox_return_reged;
when rcon =>
-- leda DFT_021 off
next_new_key(0, 0) <= new_key(0, 0) xor rcon_tbl(round);
-- leda DFT_021 on
c_clr <= '1';
r_clr <= '1';
when add_cols =>
if (c = 0) then
temp_index := 0;
else
temp_index := c - 1;
end if;
next_new_key(r, c) <= new_key(r, temp_index) xor cur_key(r, c);
if (r = 3) then
c_up <= '1';
end if;
when be_done =>
next_cur_key <= new_key;
done <= '1';
end case;
end process state_out;
-- leda C_1406 off
c_counter_reg : process(clk)
begin
if rising_edge(clk) then
c <= next_c;
end if;
end process c_counter_reg;
-- leda C_1406 on
c_counter_nsl : process(c, c_up, c_clr)
begin
if (c_clr = '1') then
next_c <= 0;
elsif (c_up = '1') then
next_c <= to_integer(to_unsigned(c, 2) + 1);
else
next_c <= c;
end if;
end process c_counter_nsl;
-- leda C_1406 off
r_counter_reg : process(clk)
begin
if rising_edge(clk) then
r <= next_r;
end if;
end process r_counter_reg;
-- leda C_1406 on
-- leda C_1406 off
sbox_return_reg : process(clk)
begin
if rising_edge(clk) then
sbox_return_reged <= sbox_return;
end if;
end process sbox_return_reg;
-- leda C_1406 on
r_counter_nsl : process(r, r_clr)
begin
if (r_clr = '1') then
next_r <= 0;
else
next_r <= to_integer(to_unsigned(r, 2) + 1);
end if;
end process r_counter_nsl;
round_key <= cur_key;
end behavioral;
architecture behavioral_p of key_scheduler is
type state_type is (
idle, load_key, rot_sub_rcon, add_cols, be_done
);
signal state : state_type;
signal next_state : state_type;
signal cur_key : key_type;
signal next_cur_key : key_type;
signal new_key : key_type;
signal next_new_key : key_type;
signal c : index;
signal next_c : index;
signal c_clr : std_logic;
signal c_up : std_logic;
signal sbox_lookup, sbox_return : col;
begin
gen_sbox : for i in index generate
sbox_b : entity work.sbox(dataflow) port map (
clk => clk, a => sbox_lookup(i), b => sbox_return(i)
);
end generate gen_sbox;
process(cur_key)
begin
for i in index loop
sbox_lookup(i) <= cur_key(to_integer(to_unsigned(i, 2) + 1), 3);
end loop;
end process;
-- leda C_1406 off
state_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
cur_key <= next_cur_key;
new_key <= next_new_key;
end if;
end process state_reg;
-- leda C_1406 on
state_nsl : process(state, go, c, round)
begin
next_state <= idle;
case state is
when idle =>
if (go = '1' and round = 0) then
next_state <= load_key;
elsif (go = '1') then
next_state <= rot_sub_rcon;
else
next_state <= idle;
end if;
when load_key =>
next_state <= be_done;
when rot_sub_rcon =>
next_state <= add_cols;
when add_cols =>
if (c = 3) then
next_state <= be_done;
else
next_state <= add_cols;
end if;
when be_done =>
next_state <= idle;
end case;
end process state_nsl;
state_out : process(state, cur_key, new_key, key_data,
key_index, key_load,
sbox_return, c, round)
variable temp_index : index;
begin
next_cur_key <= cur_key;
next_new_key <= new_key;
c_up <= '0';
c_clr <= '0';
done <= '0';
case state is
when idle =>
if (key_load = '1') then
next_new_key(key_index mod 4, key_index / 4) <= key_data;
end if;
when load_key =>
-- nothing
when rot_sub_rcon =>
for i in index loop
if (i = 0) then
next_new_key(i, 0) <= sbox_return(i) xor rcon_tbl(round);
else
next_new_key(i, 0) <= sbox_return(i);
end if;
end loop;
c_clr <= '1';
when add_cols =>
if (c = 0) then
temp_index := 0;
else
temp_index := c - 1;
end if;
for r in index loop
next_new_key(r, c) <= new_key(r, temp_index) xor cur_key(r, c);
end loop;
c_up <= '1';
when be_done =>
next_cur_key <= new_key;
done <= '1';
end case;
end process state_out;
-- leda C_1406 off
c_counter_reg : process(clk)
begin
if rising_edge(clk) then
c <= next_c;
end if;
end process c_counter_reg;
-- leda C_1406 on
c_counter_nsl : process(c, c_up, c_clr)
begin
if (c_clr = '1') then
next_c <= 0;
elsif (c_up = '1') then
next_c <= to_integer(to_unsigned(c, 2) + 1);
else
next_c <= c;
end if;
end process c_counter_nsl;
round_key <= cur_key;
end behavioral_p;
| bsd-3-clause | ac3a8a4095ce0b2d3fde36da058bffc0 | 0.468538 | 3.52965 | false | false | false | false |
jevinskie/aes-over-pcie | source/pcie.vhd | 1 | 6,035 | -- File name: pcie.vhd
-- Created: 2009-04-13
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: PCIe package
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pcie is
attribute enum_encoding: STRING;
subtype dword is unsigned(31 downto 0);
subtype word is unsigned(15 downto 0);
subtype seq_number_type is unsigned(11 downto 0);
type rx_status_type is (
rx_data_ok, skp_add, skp_rem, rx_detect, eight_ten_error,
elastic_buf_over, elastic_buf_under, rx_disparity_error
);
--attribute enum_encoding of rx_status_type : type is
-- "000 001 010 011 100 101 110 111";
type power_down_type is (p0, p0s, p1, p2);
--attribute enum_encoding of power_down_type : type is
-- "00 01 10 11";
type symbol_type is (idl);
--attribute enum_encoding of symbol_type : type is
-- "01111100";
function crc_gen(data : byte; crc : word) return word;
function lcrc_gen(data : byte; lcrc : dword) return dword;
end pcie;
package body pcie is
function crc_gen (
data : byte;
crc : word
) return word is
variable d : byte;
variable c : word;
variable newcrc : word;
begin
d := data;
c := crc;
newcrc(0) := d(6) xor d(3) xor d(0) xor c(8) xor c(11) xor c(14);
newcrc(1) := d(7) xor d(6) xor d(4) xor d(3) xor d(1) xor d(0) xor c(8) xor c(9) xor c(11) xor c(12) xor c(14) xor c(15);
newcrc(2) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0) xor c(8) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
newcrc(3) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
newcrc(4) := d(7) xor d(5) xor d(4) xor d(2) xor d(0) xor c(8) xor c(10) xor c(12) xor c(13) xor c(15);
newcrc(5) := d(6) xor d(5) xor d(3) xor d(1) xor c(9) xor c(11) xor c(13) xor c(14);
newcrc(6) := d(7) xor d(6) xor d(4) xor d(2) xor c(10) xor c(12) xor c(14) xor c(15);
newcrc(7) := d(7) xor d(5) xor d(3) xor c(11) xor c(13) xor c(15);
newcrc(8) := d(6) xor d(4) xor c(0) xor c(12) xor c(14);
newcrc(9) := d(7) xor d(5) xor c(1) xor c(13) xor c(15);
newcrc(10) := d(6) xor c(2) xor c(14);
newcrc(11) := d(7) xor c(3) xor c(15);
newcrc(12) := c(4);
newcrc(13) := d(6) xor d(3) xor d(0) xor c(5) xor c(8) xor c(11) xor c(14);
newcrc(14) := d(7) xor d(4) xor d(1) xor c(6) xor c(9) xor c(12) xor c(15);
newcrc(15) := d(5) xor d(2) xor c(7) xor c(10) xor c(13);
return newcrc;
end crc_gen;
function lcrc_gen (
data : byte;
lcrc : dword
) return dword is
variable d : byte;
variable c : dword;
variable newcrc : dword;
begin
d := data;
c := lcrc;
newcrc(0) := d(6) xor d(0) xor c(24) xor c(30);
newcrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor c(24) xor c(25) xor c(30) xor c(31);
newcrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor c(24) xor c(25) xor c(26) xor c(30) xor c(31);
newcrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor c(25) xor c(26) xor c(27) xor c(31);
newcrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30);
newcrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31);
newcrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31);
newcrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31);
newcrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(24) xor c(25) xor c(27) xor c(28);
newcrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor c(1) xor c(25) xor c(26) xor c(28) xor c(29);
newcrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor c(2) xor c(24) xor c(26) xor c(27) xor c(29);
newcrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor c(3) xor c(24) xor c(25) xor c(27) xor c(28);
newcrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor c(4) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30);
newcrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor c(5) xor c(25) xor c(26) xor c(27) xor c(29) xor c(30) xor c(31);
newcrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(6) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31);
newcrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor c(7) xor c(27) xor c(28) xor c(29) xor c(31);
newcrc(16) := d(5) xor d(4) xor d(0) xor c(8) xor c(24) xor c(28) xor c(29);
newcrc(17) := d(6) xor d(5) xor d(1) xor c(9) xor c(25) xor c(29) xor c(30);
newcrc(18) := d(7) xor d(6) xor d(2) xor c(10) xor c(26) xor c(30) xor c(31);
newcrc(19) := d(7) xor d(3) xor c(11) xor c(27) xor c(31);
newcrc(20) := d(4) xor c(12) xor c(28);
newcrc(21) := d(5) xor c(13) xor c(29);
newcrc(22) := d(0) xor c(14) xor c(24);
newcrc(23) := d(6) xor d(1) xor d(0) xor c(15) xor c(24) xor c(25) xor c(30);
newcrc(24) := d(7) xor d(2) xor d(1) xor c(16) xor c(25) xor c(26) xor c(31);
newcrc(25) := d(3) xor d(2) xor c(17) xor c(26) xor c(27);
newcrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor c(18) xor c(24) xor c(27) xor c(28) xor c(30);
newcrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor c(19) xor c(25) xor c(28) xor c(29) xor c(31);
newcrc(28) := d(6) xor d(5) xor d(2) xor c(20) xor c(26) xor c(29) xor c(30);
newcrc(29) := d(7) xor d(6) xor d(3) xor c(21) xor c(27) xor c(30) xor c(31);
newcrc(30) := d(7) xor d(4) xor c(22) xor c(28) xor c(31);
newcrc(31) := d(5) xor c(23) xor c(29);
return newcrc;
end lcrc_gen;
end pcie;
| bsd-3-clause | 1f0dc72f32c894e3ebe82e0612168232 | 0.534051 | 2.365739 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_thread_manager_v1_00_a/devl/bfmsim/simulation/behavioral/my_core_wrapper.vhd | 3 | 6,563 | -------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_thread_manager_tb_v1_00_a;
use plb_thread_manager_tb_v1_00_a.all;
entity my_core_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
Sl_MIRQ : out std_logic_vector(0 to 0);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end my_core_wrapper;
architecture STRUCTURE of my_core_wrapper is
component plb_thread_manager_tb is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_AWIDTH : integer;
C_SPLB_DWIDTH : integer;
C_SPLB_NUM_MASTERS : integer;
C_SPLB_MID_WIDTH : integer;
C_SPLB_NATIVE_DWIDTH : integer;
C_SPLB_P2P : integer;
C_SPLB_SUPPORT_BURSTS : integer;
C_SPLB_SMALLEST_MASTER : integer;
C_SPLB_CLK_PERIOD_PS : integer;
C_INCLUDE_DPHASE_TIMER : integer;
C_FAMILY : string
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to (31));
PLB_UABus : in std_logic_vector(0 to (31));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8-1));
PLB_MSize : in std_logic_vector(0 to (1));
PLB_size : in std_logic_vector(0 to (3));
PLB_type : in std_logic_vector(0 to (2));
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to (1));
PLB_rdPendPri : in std_logic_vector(0 to (1));
PLB_reqPri : in std_logic_vector(0 to (1));
PLB_TAttribute : in std_logic_vector(0 to (15));
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to (1));
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to (3));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
begin
my_core : plb_thread_manager_tb
generic map (
C_BASEADDR => X"30000000",
C_HIGHADDR => X"3000ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 128,
C_SPLB_NUM_MASTERS => 1,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_SMALLEST_MASTER => 128,
C_SPLB_CLK_PERIOD_PS => 10000,
C_INCLUDE_DPHASE_TIMER => 0,
C_FAMILY => "virtex5"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
SYNCH_IN => SYNCH_IN,
SYNCH_OUT => SYNCH_OUT
);
end architecture STRUCTURE;
| bsd-3-clause | aa50ca7a29da5c0a265268dcac5aeb23 | 0.584184 | 3.206155 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/rdpfifo_dp_cntl.vhd | 3 | 28,824 | -------------------------------------------------------------------------------
-- $Id: rdpfifo_dp_cntl.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--rdpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: rdpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Read Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the RPFIFO design.
--
--
-- rdpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET August 15, 2001 -- Initial version adapted from pt design
--
-- DET Sept. 21, 2001 -- Size Optimized redesign and parameterization
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_top;
use opb_ipif_v2_00_h.pf_occ_counter_top;
use opb_ipif_v2_00_h.pf_adder;
-------------------------------------------------------------------------------
entity rdpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 9;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port (
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_rd_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end rdpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of rdpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
-- shared signals
signal sig_normal_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
----------------- start architecture logic ------------------------------------
begin
------------------------------------------------------------------------------
-- Generate the Read PFIFO with packetizing features included
------------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (
reset1,
normal_op,
packet_op,
rest1,
mark1,
rls1,
pkt_update,
nml_update
);
--INTERNAL SIGNALS
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_write : std_logic;
signal ld_addr_write_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
begin
--Misc I/O Assignments
Full <= int_full;
Almost_Full <= int_almost_full;
Empty <= int_empty; -- Align Empty flag with the DP occupancy
Almost_Empty <= int_almost_empty; -- Align Almost_Empty flag with the
-- DP occupancy
Occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr; -- currently combinitorial
RdAck <= inc_rd_addr; -- currently combinitorial
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-----------------------------------------------------------------------
-- Main Transition sequence state machine
-----------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_mark_into_write <= '0';
ld_addr_write_into_mark <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_mark_into_write <= '0';
ld_addr_write_into_mark <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
Case trans_state Is
When reset1 =>
trans_state <= normal_op;
hold_ack <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
trans_state <= pkt_update;
hold_ack <= '1';
ld_addr_mark_into_write <= '1'; -- load the mark address into
-- the wr cntr
ld_occ_mark_into_norm <= '1'; -- load the marked occupancy
-- into the normal occupancy
-- cntr
When mark1 =>
trans_state <= pkt_update;
hold_ack <= '1';
ld_occ_norm_into_mark <= '1'; -- load the normal occupancy
-- into mark occupancy cntr
ld_addr_write_into_mark <= '1'; -- load the write address
-- into mark register
When rls1 =>
trans_state <= nml_update;
hold_ack <= '1';
ld_occ_norm_into_mark <= '1'; -- load the normal occupancy
-- into mark occupancy cntr
ld_addr_write_into_mark <= '1'; -- load the write address
-- into mark register
When nml_update =>
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking operations
-- This counter establishes the empty flag states
--------------------------------------------------------------------------
inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc <= decr_rd_addr or inc_mark_addr;
I_MARK_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the full flag states.
--------------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
--------------------------------------------------------------------------
-- Register and delay Full/Empty flags
--------------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
int_full_dly1 <= '0';
int_full_dly2 <= '0';
int_almost_empty_dly1 <= '0';
int_empty_dly1 <= '1';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
int_almost_empty_dly1 <= int_almost_empty;
int_empty_dly1 <= int_empty;
Else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
--------------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and not(hold_ack)
and not(rd_backup and int_almost_full)
and enable_wr_addr_inc;
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_write,
Load_value => mark_address,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Read Address Counter Logic
-----------------------------------------------------------------------
-- Detect end of burst read by IP and set backup condition
-----------------------------------------------------------------------
DETECT_RDCNT_BACKUP : process (Burst_rd_xfer, RdReq, int_empty_dly1)
Begin
if (Burst_rd_xfer = '1'
and RdReq = '0'
and int_empty_dly1 = '0') then
rd_backup <= '1';
else
rd_backup <= '0';
end if;
End process; -- DETECT_RDCNT_BACKUP
inc_rd_addr <= RdReq
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
sig_zeros <= (others => '0');
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_wr_addr
and enable_mark_addr_inc;
I_MARKREG_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => ld_addr_write_into_mark,
Load_value => write_address,
Count_Down => '0',
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
--------------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
------------------------------------------------------------------------------
-- Generate the Read PFIFO with no packetizing features
------------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
--Internal Signals
signal int_almost_full : std_logic;
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal write_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal occ_load_value : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
--Misc I/O Assignments
Full <= int_full;
Almost_Full <= int_almost_full;
Empty <= int_empty; -- Align Empty flag with the DP occupancy
Almost_Empty <= int_almost_empty; -- Align Almost_Empty flag with the
-- DP occupancy
Occupancy <= sig_normal_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr; -- currently combinitorial
RdAck <= inc_rd_addr; -- currently combinitorial
DeadLock <= int_full and int_empty; -- both full and empty at the
-- same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty and full flag states.
--------------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
--------------------------------------------------------------------------
-- Register and delay Full/Empty flags
--------------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
int_full_dly1 <= '0';
int_full_dly2 <= '0';
int_almost_empty_dly1 <= '0';
int_empty_dly1 <= '1';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
int_almost_empty_dly1 <= int_almost_empty;
int_empty_dly1 <= int_empty;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
-----------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and not(rd_backup and int_almost_full);
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
-------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Read Address Counter Logic
--------------------------------------------------------------------
-- Detect end of burst read by IP and set backup condition
--------------------------------------------------------------------
DETECT_RDCNT_BACKUP : process (Burst_rd_xfer, RdReq, int_empty_dly1)
Begin
if (Burst_rd_xfer = '1'
and RdReq = '0'
and int_empty_dly1 = '0') then
rd_backup <= '1';
else
rd_backup <= '0';
end if;
End process; -- DETECT_RDCNT_BACKUP
inc_rd_addr <= RdReq
and not(int_empty)
and not(int_empty_dly1);
decr_rd_addr <= rd_backup;
sig_zeros <= (others => '0');
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
----------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_ipif_v2_00_h.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
--Carry_Out => ,
Ain => slv_max_vacancy,
Bin => sig_normal_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
| bsd-3-clause | 0ab6404fc027c9f647f1cfdd1e05c68f | 0.404246 | 4.47995 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/queue/fifo_block.vhd | 1 | 6,241 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ft a : wr_block and rd_block must be synchronized with clk
entity fifo_block is
generic (
DWIDTH : integer; -- 8
BLOCK_AWIDTH : integer; -- 5
FIFO_AWIDTH : integer; -- 2
RAM_TYPE : string(1 to 7)
);
port (
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
wr_block : in std_logic;
wr_clk : in std_logic;
wren : in std_logic;
waddr : in std_logic_vector(BLOCK_AWIDTH - 1 downto 0);
wdata : in std_logic_vector(DWIDTH - 1 downto 0);
rd_block : in std_logic;
rd_clk : in std_logic; -- zcpsm_clk
raddr : in std_logic_vector(BLOCK_AWIDTH - 1 downto 0); -- ÓÉzcpsmÌṩ
rdata : out std_logic_vector(DWIDTH - 1 downto 0); -- Ìṩ¸øzcpsm
full : out std_logic;
empty : out std_logic
);
end fifo_block;
architecture behave of fifo_block is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal wp_block : std_logic_vector(FIFO_AWIDTH - 1 downto 0) := (others => '0');
signal rp_block : std_logic_vector(FIFO_AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal ram_waddr : std_logic_vector(FIFO_AWIDTH + BLOCK_AWIDTH - 1 downto 0) := (others => '0');
signal ram_raddr : std_logic_vector(FIFO_AWIDTH + BLOCK_AWIDTH - 1 downto 0) := (others => '0');
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
signal rdata_buf : std_logic_vector(DWIDTH - 1 downto 0);
constant FIFO_DEPTH : natural := 2 ** FIFO_AWIDTH;
constant BLOCK_DEPTH : natural := 2 ** BLOCK_AWIDTH;
begin
use_block_ram : if RAM_TYPE = "BLK_RAM" generate
ram : blockdram
generic map(
depth => FIFO_DEPTH * BLOCK_DEPTH,
Dwidth => DWIDTH,
Awidth => FIFO_AWIDTH + BLOCK_AWIDTH
)
port map(
addra => ram_waddr,
clka => wr_clk,
addrb => ram_raddr,
clkb => rd_clk,
dia => wdata,
wea => ram_we,
dob => rdata
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => FIFO_DEPTH * BLOCK_DEPTH,
Dwidth => DWIDTH,
Awidth => FIFO_AWIDTH + BLOCK_AWIDTH
)
port map(
A => ram_waddr,
CLK => wr_clk,
D => wdata,
WE => ram_we,
DPRA => ram_raddr,
DPO => rdata_buf,
QDPO => open
);
process(rd_clk)
begin
if rising_edge(rd_clk) then
rdata <= rdata_buf;
end if;
end process;
end generate use_dis_ram;
g_multi_block : if FIFO_AWIDTH > 0 generate
ram_we <= wren and (not full_flag); -- ram_write_enable
ram_waddr <= wp_block & waddr; -- ram_write_addr
ram_raddr <= rp_block & raddr; -- ram_read_addr
WritePointerCtrl : process(clk, reset) -- УÑé´íÎóʱ°ü¶ªÆú
begin
if reset = '1' then
wp_block <= (others => '0');
elsif rising_edge(clk) then
if clr = '1' then
wp_block <= (others => '0');
elsif full_flag = '0' and wr_block = '1' then -- ·ÇÂúʱ£¬Ò»¸öÒÔÌ«°ü·¢ËÍÍê±ÏдÊý¾Ý¿éµØÖ·¼Ó1
wp_block <= wp_block + 1;
end if;
end if;
end process;
ReadPointerCtrl : process(clk, reset)
begin
if reset = '1' then
rp_block <= (others => '0');
elsif rising_edge(clk) then
if clr = '1' then
rp_block <= (others => '0');
elsif empty_flag = '0' and rd_block = '1' then -- ·Ç¿Õʱ£¬¶ÁÊý¾Ý¿éµØÖ·¼Ó1
rp_block <= rp_block + 1;
end if;
end if;
end process;
GetEmptyFlag : process(clk, reset)
begin
if reset = '1' then
empty_flag <= '1';
elsif rising_edge(clk) then
if clr = '1' then
empty_flag <= '1';
elsif (wp_block = rp_block) and (wr_block = '1') then
empty_flag <= '0';
elsif (wp_block = rp_block + 1) and (rd_block = '1'and wr_block = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(clk, reset)
begin
if reset = '1' then
full_flag <= '0';
elsif rising_edge(clk) then
if clr = '1' then
full_flag <= '0';
elsif (wp_block = rp_block - 1) and (wr_block = '1' and rd_block = '0') then
full_flag <= '1';
elsif (wp_block = rp_block) and (rd_block = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
end generate;
g_single_block : if FIFO_AWIDTH = 0 generate
ram_we <= wren and (not full_flag);
ram_waddr <= waddr;
ram_raddr <= raddr;
GetEmptyFlag : process(clk, reset)
begin
if reset = '1' then
empty_flag <= '1';
elsif rising_edge(clk) then
if clr = '1' then
empty_flag <= '1';
elsif wr_block = '1' then
empty_flag <= '0';
elsif rd_block = '1'and wr_block = '0' then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(clk, reset)
begin
if reset = '1' then
full_flag <= '0';
elsif rising_edge(clk) then
if clr = '1' then
full_flag <= '0';
elsif wr_block = '1' and rd_block = '0' then
full_flag <= '1';
elsif rd_block = '1' then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
end generate;
end behave;
| gpl-2.0 | 435a61be16d5916061afd44cd1ac8291 | 0.560647 | 2.724138 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_du.vhd | 1 | 52,800 | --------------------------------------------------------------------------------
-- Title : Data Unit of VME-Bridge
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_du.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13/01/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This unit handles the data path.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- vme_ctrl
-- vme_du
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.8 $
--
-- $Log: vme_du.vhd,v $
-- Revision 1.8 2015/09/16 09:20:05 mwawrik
-- Added generic USE_LONGADD
--
-- Revision 1.7 2014/04/17 07:35:25 MMiehling
-- added generic LONGADD_SIZE
--
-- Revision 1.6 2013/09/12 08:45:23 mmiehling
-- support of address modifier supervisory, non-privileged data/program for A16, A24 and A32
--
-- Revision 1.5 2012/11/15 09:43:53 MMiehling
-- connected each interrupt source to interface in order to support edge triggered msi
--
-- Revision 1.4 2012/11/12 08:13:10 MMiehling
-- bugfix locmon: improved handling of adr(4:3) for stable results
--
-- Revision 1.3 2012/09/25 11:21:43 MMiehling
-- added wbm_err signal for error signalling from pcie to vme
--
-- Revision 1.2 2012/08/27 12:57:13 MMiehling
-- general rework of d64 slave access handling
-- rework of reset handling
--
-- Revision 1.1 2012/03/29 10:14:39 MMiehling
-- Initial Revision
--
-- Revision 1.11 2006/06/02 15:48:59 MMiehling
-- changed default of arbitration => now not fair is default
--
-- Revision 1.10 2005/02/04 13:44:17 mmiehling
-- added combinations of addr3+4
--
-- Revision 1.9 2004/11/02 11:29:58 mmiehling
-- improved timing and area
-- moved dma_reg to vme_du
--
-- Revision 1.8 2004/07/27 17:15:42 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.7 2003/12/17 15:51:48 MMiehling
-- byte swapping in "not swapped" mode was wrong
--
-- Revision 1.6 2003/12/01 10:03:55 MMiehling
-- added d64
--
-- Revision 1.5 2003/07/14 08:38:10 MMiehling
-- changed mail_irq; added lwordn
--
-- Revision 1.4 2003/06/24 13:47:10 MMiehling
-- added rst_aonly; changed vme_data_in_reg sampling (lwordn)
--
-- Revision 1.3 2003/06/13 10:06:38 MMiehling
-- added address bits 3+4 for locmon; changed locsta register
--
-- Revision 1.2 2003/04/22 11:03:02 MMiehling
-- changed irq and address map for locmon
--
-- Revision 1.1 2003/04/01 13:04:43 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY vme_du IS
GENERIC (
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
-- dma
dma_sta : OUT std_logic_vector(9 DOWNTO 0);
clr_dma_en : IN std_logic;
set_dma_err : IN std_logic;
dma_act_bd : IN std_logic_vector(7 DOWNTO 4);
-- arbiter
sel_reg_data_in : IN std_logic; -- mux select signal for wbb/vme register access
sel_loc_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select signal for 0=reg, 1=vme data_out
en_wbm_dat_o : IN std_logic; -- enable for wbm_dat_o
-- requester
brl : OUT std_logic_vector(1 DOWNTO 0); -- bus request leve
-- vme_au
int_adr : IN std_logic_vector(18 DOWNTO 0); -- internal adress for reg
int_be : IN std_logic_vector(3 DOWNTO 0); -- internal byte enables
vme_adr_out : IN std_logic_vector(31 DOWNTO 0); -- vme adress lines
byte_routing : IN std_logic; -- mux select for byte routing
vme_adr_in : OUT std_logic_vector(31 DOWNTO 0); -- vme adress input lines
my_iack : IN std_logic;
d64 : IN std_logic; -- indicates d64 mblt
vam_reg : IN std_logic_vector(5 DOWNTO 0); -- registered vam_in for location monitoring and berr_adr (registered with en_vme_adr_in)
vme_adr_in_reg : IN std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring and berr_adr (registered with en_vme_adr_in)
sl_writen_reg : IN std_logic; -- vme read/wrtie signal (registered with en_vme_adr_in)
iackn_in_reg : IN std_logic; -- iack signal (registered with en_vme_adr_in)
-- sys_arbiter
lwordn : IN std_logic; -- stored for vme slave access
-- ctrl_mux
write_flag : IN std_logic; -- write flag for register write access
-- master
oe_vd : IN std_logic; -- output enable for vme data
oe_va : IN std_logic; -- output enable for vme adress
second_word : IN std_logic; -- indicates data phase of d64
-- slave
sel_vme_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select for vme data out
en_vme_data_out_reg : IN std_logic; -- register enable for vme data out
en_vme_data_out_reg_high: IN std_logic; -- register enable for vme data out high long
en_vme_data_in_reg : IN std_logic; -- register enable for vme data in
en_vme_data_in_reg_high : IN std_logic; -- register enable for vme data in high long
clr_intreq : IN std_logic; -- clear interrupt request (intr(3) <= '0'
-- wbb_slave
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0); -- indicates dma(1) or normal(0) access
swap : IN std_logic; -- swapps bytes when enabled
-- wbb_master
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0);
sel_wbm_dat_o : IN std_logic; -- selects between low and high d32
-- register out
longadd : OUT std_logic_vector(7 DOWNTO 0); -- upper 3 address bits for A32 mode or dependent on LONGADD_SIZE
mstr_reg : OUT std_logic_vector(13 DOWNTO 0); -- master register (aonly, postwr, iberr, berr, req, rmw, A16_MODE, A24_MODE, A32_MODE)
sysc_reg : OUT std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
slv16_reg : OUT std_logic_vector(4 DOWNTO 0); -- slave A16 base address register
slv24_reg : OUT std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
slv32_reg : OUT std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
slv24_pci_q : OUT std_logic_vector(15 DOWNTO 0); -- slave A24 base address register for PCI
slv32_pci_q : OUT std_logic_vector(23 DOWNTO 0); -- slave A32 base address register for PCI
intr_reg : OUT std_logic_vector(3 DOWNTO 0); -- interrupt request register
pci_offset_q : OUT std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
-- register bits
set_berr : IN std_logic; -- if bit is set => berr bit will be set
rst_rmw : IN std_logic; -- if bit is set => rmw bit will be cleared
set_sysc : IN std_logic; -- if bit is set => sysc bit will be set
set_ato : IN std_logic; -- if bit is set => ato bit will be set
clr_sysr : IN std_logic; -- if bit is set => sysr bit will be cleared
mail_irq : IN std_logic_vector(7 DOWNTO 0); -- mailbox interrupt flags
loc_am_0 : OUT std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_am_1 : OUT std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_irq_0 : IN std_logic; -- loc-monitor #0 - irq
loc_irq_1 : IN std_logic; -- loc-monitor #1 - irq
loc_rw_0 : OUT std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_rw_1 : OUT std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_adr_0 : OUT std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
loc_adr_1 : OUT std_logic_vector(31 DOWNTO 0); -- location monitor #1 adress
loc_sel : IN std_logic_vector(1 DOWNTO 0); -- these bits are loaded with combinations of address bits [4:3] if locmon hit address
rst_aonly : IN std_logic; -- resets aonly bit
clr_locmon : OUT std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
-- irq pins
irq_i_n : IN std_logic_vector(7 DOWNTO 1);
irq_o_n : OUT std_logic_vector(7 DOWNTO 1);
acfailn : IN std_logic; -- ACFAIL# input from Power Supply
--vme
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
vd : INOUT std_logic_vector(31 DOWNTO 0);
va : INOUT std_logic_vector(31 DOWNTO 0)
);
END vme_du;
ARCHITECTURE vme_du_arch OF vme_du IS
CONSTANT null_vec : std_logic_vector(23 DOWNTO 0):="000000000000000000000000";
SIGNAL reg_data_in : std_logic_vector(31 DOWNTO 0);
SIGNAL reg_data_out : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_data_in_reg_mux : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_data_in_reg : std_logic_vector(63 DOWNTO 0);
SIGNAL vme_data_out_reg : std_logic_vector(63 DOWNTO 0);
SIGNAL vd_in : std_logic_vector(31 DOWNTO 0);
SIGNAL vd_in_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL vd_in_reg_int : std_logic_vector(31 DOWNTO 0);
SIGNAL vd_out_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL va_in : std_logic_vector(31 DOWNTO 0);
SIGNAL va_in_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL va_out_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL wbs_dat_o_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL mstr_int : std_logic_vector(13 DOWNTO 0);
SIGNAL longadd_int : std_logic_vector(7 DOWNTO 0);
SIGNAL intr_int : std_logic_vector(3 DOWNTO 0);
SIGNAL intid_int : std_logic_vector(7 DOWNTO 0);
SIGNAL istat : std_logic_vector(7 DOWNTO 0);
SIGNAL imask : std_logic_vector(7 DOWNTO 0);
SIGNAL sysc_reg_int : std_logic_vector(2 DOWNTO 0);
SIGNAL mail_irqe : std_logic_vector(7 DOWNTO 0);
SIGNAL mail_irq_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL locsta_0 : std_logic_vector(5 DOWNTO 0);
SIGNAL locsta_1 : std_logic_vector(5 DOWNTO 0);
SIGNAL loc_adr_0_int : std_logic_vector(31 DOWNTO 0);
SIGNAL loc_adr_1_int : std_logic_vector(31 DOWNTO 0);
SIGNAL slv16_reg_int : std_logic_vector(4 DOWNTO 0);
SIGNAL slv24_reg_int : std_logic_vector(15 DOWNTO 0);
SIGNAL slv32_reg_int : std_logic_vector(23 DOWNTO 0);
SIGNAL slv24_pci_q_int : std_logic_vector(15 DOWNTO 0);
SIGNAL slv32_pci_q_int : std_logic_vector(23 DOWNTO 0);
SIGNAL pci_offset_int : std_logic_vector(31 DOWNTO 12);
SIGNAL acfailn_regd : std_logic;
SIGNAL irqregd : std_logic_vector(7 DOWNTO 1);
SIGNAL acfst : std_logic;
SIGNAL wbm_dat_i_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL dma_sta_int : std_logic_vector(9 DOWNTO 0);
SIGNAL test : std_logic_vector(20 DOWNTO 0):="000000000000000000000";
SIGNAL swap_byte_routing : std_logic_vector(1 DOWNTO 0);
SIGNAL vad_sel : std_logic_vector(2 DOWNTO 0);
SIGNAL loc_irq_0_q : std_logic; -- loc-monitor #0 - irq
SIGNAL loc_irq_1_q : std_logic; -- loc-monitor #1 - irq
SIGNAL loc_sel_0_int : std_logic_vector(1 DOWNTO 0);
SIGNAL loc_sel_1_int : std_logic_vector(1 DOWNTO 0);
SIGNAL set_dma_err_q : std_logic;
SIGNAL ga_q : std_logic_vector(5 DOWNTO 0); -- geographical addresses and parity
SIGNAL slot_nr : std_logic_vector(4 DOWNTO 0); -- slot number
SIGNAL brl_int : std_logic_vector(1 DOWNTO 0); -- bus request level
SIGNAL berr_vam : std_logic_vector(5 downto 0);
SIGNAL berr_adr : std_logic_vector(31 downto 0);
SIGNAL berr_rw : std_logic;
SIGNAL berr_iack : std_logic;
BEGIN
vme_adr_in <= va_in_reg;
longadd <= longadd_int WHEN USE_LONGADD ELSE longadd_int(2 DOWNTO 0)&"00000";
pci_offset_q <= pci_offset_int & "0000000000";
vme_irq <= istat;
vd_proc : PROCESS(vd_out_reg, vd, oe_vd)
BEGIN
IF oe_vd = '1' THEN
vd <= vd_out_reg;
vd_in <= vd;
ELSE
vd <= (OTHERS => 'Z');
vd_in <= vd;
END IF;
END PROCESS vd_proc;
va_proc : PROCESS(va_out_reg, va, oe_va)
BEGIN
IF oe_va = '1' THEN
va <= va_out_reg;
va_in <= va;
ELSE
va <= (OTHERS => 'Z');
va_in <= va;
END IF;
END PROCESS va_proc;
-- swap = 1, byte_routing = 1 => 3210
-- swap = 1, byte_routing = 0 => 1032
-- byte_routing = 1 => 2301
-- byte_routing = 0 => 0123
swap_byte_routing <= swap & byte_routing;
PROCESS (vd_in_reg_int, swap_byte_routing)
BEGIN
CASE swap_byte_routing IS
WHEN "01" => vme_data_in_reg_mux <= vd_in_reg_int(31 DOWNTO 0);
WHEN "00" => vme_data_in_reg_mux <= vd_in_reg_int(15 DOWNTO 0) & vd_in_reg_int(31 DOWNTO 16);
WHEN "11" => vme_data_in_reg_mux <= vd_in_reg_int(23 DOWNTO 16) & vd_in_reg_int(31 DOWNTO 24) & vd_in_reg_int(7 DOWNTO 0) & vd_in_reg_int(15 DOWNTO 8);
WHEN "10" => vme_data_in_reg_mux <= vd_in_reg_int(7 DOWNTO 0) & vd_in_reg_int(15 DOWNTO 8) & vd_in_reg_int(23 DOWNTO 16) & vd_in_reg_int(31 DOWNTO 24);
WHEN OTHERS => vme_data_in_reg_mux <= vd_in_reg_int(7 DOWNTO 0) & vd_in_reg_int(15 DOWNTO 8) & vd_in_reg_int(23 DOWNTO 16) & vd_in_reg_int(31 DOWNTO 24);
END CASE;
END PROCESS;
reg_data_in <= wbs_dat_i WHEN sel_reg_data_in = '1' ELSE vme_data_in_reg(31 DOWNTO 0);
wbs_dat_o <= wbs_dat_o_reg;
vd_in_reg_int <= va_in_reg WHEN d64 = '1' AND en_vme_data_in_reg_high = '1' ELSE vd_in_reg;
reg : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
vd_in_reg <= (OTHERS => '0');
vd_out_reg <= (OTHERS => '0');
vme_data_in_reg <= (OTHERS => '0');
vme_data_out_reg <= (OTHERS => '0');
va_out_reg <= (OTHERS => '0');
va_in_reg <= (OTHERS => '0');
wbs_dat_o_reg <= (OTHERS => '0');
wbm_dat_o <= (OTHERS => '0');
wbm_dat_i_reg <= (OTHERS => '0');
ga_q <= (OTHERS => '0');
slot_nr <= (OTHERS => '0');
ELSIF clk'EVENT and clk = '1' THEN
-- synchronization registers
ga_q <= gap & ga;
CASE ga_q IS
WHEN "111110" => slot_nr <= conv_std_logic_vector(1 ,5);
WHEN "111101" => slot_nr <= conv_std_logic_vector(2 ,5);
WHEN "011100" => slot_nr <= conv_std_logic_vector(3 ,5);
WHEN "111011" => slot_nr <= conv_std_logic_vector(4 ,5);
WHEN "011010" => slot_nr <= conv_std_logic_vector(5 ,5);
WHEN "011001" => slot_nr <= conv_std_logic_vector(6 ,5);
WHEN "111000" => slot_nr <= conv_std_logic_vector(7 ,5);
WHEN "110111" => slot_nr <= conv_std_logic_vector(8 ,5);
WHEN "010110" => slot_nr <= conv_std_logic_vector(9 ,5);
WHEN "010101" => slot_nr <= conv_std_logic_vector(10,5);
WHEN "110100" => slot_nr <= conv_std_logic_vector(11,5);
WHEN "010011" => slot_nr <= conv_std_logic_vector(12,5);
WHEN "110010" => slot_nr <= conv_std_logic_vector(13,5);
WHEN "110001" => slot_nr <= conv_std_logic_vector(14,5);
WHEN "010000" => slot_nr <= conv_std_logic_vector(15,5);
WHEN "101111" => slot_nr <= conv_std_logic_vector(16,5);
WHEN "001110" => slot_nr <= conv_std_logic_vector(17,5);
WHEN "001101" => slot_nr <= conv_std_logic_vector(18,5);
WHEN "101100" => slot_nr <= conv_std_logic_vector(19,5);
WHEN "001011" => slot_nr <= conv_std_logic_vector(20,5);
WHEN "101010" => slot_nr <= conv_std_logic_vector(21,5);
WHEN OTHERS => slot_nr <= conv_std_logic_vector(30,5); -- amnesia address
END CASE;
IF wbm_ack_i = '1' THEN
wbm_dat_i_reg <= wbm_dat_i;
ELSIF wbm_err_i = '1' THEN
wbm_dat_i_reg <= x"eeee_eeee"; -- should indicate 'error'
END IF;
IF en_wbm_dat_o = '1' AND sel_wbm_dat_o = '0' THEN -- low long
wbm_dat_o <= vme_data_in_reg(31 DOWNTO 0);
ELSIF en_wbm_dat_o = '1' AND sel_wbm_dat_o = '1' THEN -- high long
wbm_dat_o <= vme_data_in_reg(63 DOWNTO 32);
END IF;
vd_in_reg <= vd_in;
IF swap = '1' AND d64 = '1' THEN
-- swapping for d64: high and low 4 byte are swapped
IF en_vme_data_in_reg_high = '1' THEN
vme_data_in_reg(31 DOWNTO 0) <= va_in_reg(7 DOWNTO 0) & va_in_reg(15 DOWNTO 8) & va_in_reg(23 DOWNTO 16) & va_in_reg(31 DOWNTO 24);
END IF;
IF en_vme_data_in_reg = '1' THEN
vme_data_in_reg(63 DOWNTO 32) <= vd_in_reg(7 DOWNTO 0) & vd_in_reg(15 DOWNTO 8) & vd_in_reg(23 DOWNTO 16) & vd_in_reg(31 DOWNTO 24);
END IF;
ELSE
IF en_vme_data_in_reg = '1' AND (lwordn = '0' OR (lwordn = '1' AND byte_routing = '0')) THEN
vme_data_in_reg(31 DOWNTO 16) <= vme_data_in_reg_mux(31 DOWNTO 16);
END IF;
IF en_vme_data_in_reg = '1' AND (lwordn = '0' OR (lwordn = '1' AND byte_routing = '1')) THEN
vme_data_in_reg(15 DOWNTO 0) <= vme_data_in_reg_mux(15 DOWNTO 0);
END IF;
IF en_vme_data_in_reg_high = '1' THEN
vme_data_in_reg(63 DOWNTO 32) <= vme_data_in_reg_mux(31 DOWNTO 0);
END IF;
END IF;
-- DATA output
IF swap = '1' THEN
IF d64 = '1' THEN -- data phase for d64 mblt 7654
vd_out_reg <= vme_data_out_reg(39 DOWNTO 32) & vme_data_out_reg(47 DOWNTO 40) & vme_data_out_reg(55 DOWNTO 48) & vme_data_out_reg(63 DOWNTO 56);
ELSIF byte_routing = '1' THEN -- data phase with byte routing 0123
vd_out_reg <= vme_data_out_reg(23 DOWNTO 16) & vme_data_out_reg(31 DOWNTO 24) & vme_data_out_reg(7 DOWNTO 0) & vme_data_out_reg(15 DOWNTO 8);
ELSE -- data phase with byte routing 2301
vd_out_reg <= vme_data_out_reg(7 DOWNTO 0) & vme_data_out_reg(15 DOWNTO 8) & vme_data_out_reg(23 DOWNTO 16) & vme_data_out_reg(31 DOWNTO 24);
END IF;
ELSE
IF byte_routing = '1' THEN
vd_out_reg <= vme_data_out_reg(31 DOWNTO 0);-- data phase with byte routing 3210
ELSE
vd_out_reg <= vme_data_out_reg(15 DOWNTO 0) & vme_data_out_reg(31 DOWNTO 16);-- data phase with byte routing 1032
END IF;
END IF;
-- ADDRESS output
IF swap = '1' THEN
IF second_word = '1' AND d64 = '1' THEN -- master d64 data phases
va_out_reg <= vme_data_out_reg(7 DOWNTO 0) & vme_data_out_reg(15 DOWNTO 8) & vme_data_out_reg(23 DOWNTO 16) & vme_data_out_reg(31 DOWNTO 24);
ELSE -- master address phase
va_out_reg <= vme_adr_out;
END IF;
ELSE
IF second_word = '1' AND d64 = '1' THEN -- master d64 data phases
va_out_reg <= vme_data_out_reg(63 DOWNTO 32);
ELSE -- master address phase
va_out_reg <= vme_adr_out;
END IF;
END IF;
va_in_reg <= va_in;
IF en_vme_data_out_reg = '1' THEN
IF my_iack = '1' THEN -- vme slave iack read access
vme_data_out_reg(31 DOWNTO 0) <= intid_int & intid_int & intid_int & intid_int;
ELSIF sel_vme_data_out = "10" THEN -- vme slave read access from registers
vme_data_out_reg(31 DOWNTO 0) <= reg_data_out;
ELSIF sel_vme_data_out = "01" THEN -- vme master write access
vme_data_out_reg(31 DOWNTO 0) <= wbs_dat_i;
ELSE -- vme slave read access
vme_data_out_reg(31 DOWNTO 0) <= wbm_dat_i_reg;
END IF;
END IF;
IF en_vme_data_out_reg_high = '1' THEN
IF sel_vme_data_out = "01" THEN
vme_data_out_reg(63 DOWNTO 32) <= wbs_dat_i; -- vme master 64-bit write access
ELSE
vme_data_out_reg(63 DOWNTO 32) <= wbm_dat_i_reg; -- vme slave 64-bit read access
END IF;
END IF;
IF sel_loc_data_out(0) = '0' THEN
wbs_dat_o_reg <= reg_data_out;
ELSIF sel_loc_data_out(1) = '0' THEN
wbs_dat_o_reg <= vme_data_in_reg(31 DOWNTO 0);
ELSE
wbs_dat_o_reg <= vme_data_in_reg(63 DOWNTO 32);
END IF;
END IF;
END PROCESS reg;
----------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------
reg_out : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
reg_data_out <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
CASE int_adr(6 DOWNTO 2) IS
WHEN "00000" => reg_data_out <= x"000000" & "0000" & intr_int; -- 0x000
WHEN "00001" => reg_data_out <= x"000000" & intid_int; -- 0x004
WHEN "00010" => reg_data_out <= x"000000" & istat; -- 0x008
WHEN "00011" => reg_data_out <= x"000000" & imask; -- 0x00c
WHEN "00100" => reg_data_out <= x"0000" & "00" & mstr_int; -- 0x010
WHEN "00101" => reg_data_out <= x"0000" & slv24_reg_int(15 DOWNTO 8) & "000" & slv24_reg_int(4 DOWNTO 0); -- 0x014
WHEN "00110" => reg_data_out <= x"000000" & "00000" & sysc_reg_int; -- 0x018
WHEN "00111" => reg_data_out <= x"000000" & longadd_int; -- 0x01c
WHEN "01000" => reg_data_out <= x"000000" & mail_irqe; -- 0x020
WHEN "01001" => reg_data_out <= x"000000" & mail_irq_reg; -- 0x024
WHEN "01010" => reg_data_out <= pci_offset_int(31 DOWNTO 12) & x"000"; -- 0x028
WHEN "01011" => reg_data_out <= x"000000" & dma_sta_int(7 DOWNTO 0); -- 0x02c
WHEN "01100" => reg_data_out <= x"000000" & "000" & slv16_reg_int; -- 0x030
WHEN "01101" => reg_data_out <= x"00" & slv32_reg_int(23 DOWNTO 8) & "000" & slv32_reg_int(4 DOWNTO 0); -- 0x034
WHEN "01110" => reg_data_out <= x"000000" & loc_sel_0_int & locsta_0; -- 0x038
WHEN "01111" => reg_data_out <= x"000000" & loc_sel_1_int & locsta_1; -- 0x03c
WHEN "10000" => reg_data_out <= loc_adr_0_int(31 DOWNTO 0); -- 0x040
WHEN "10001" => reg_data_out <= loc_adr_1_int(31 DOWNTO 0); -- 0x044
WHEN "10010" => reg_data_out <= x"0000" & slv24_pci_q_int(15 DOWNTO 8) & "000" & slv24_pci_q_int(4 DOWNTO 0); -- 0x048
WHEN "10011" => reg_data_out <= x"00" & slv32_pci_q_int(23 DOWNTO 8) & "000" & slv32_pci_q_int(4 DOWNTO 0); -- 0x04c
WHEN "10100" => reg_data_out <= x"0000" & "000" & slot_nr & "00" & ga_q; -- 0x050
WHEN "10101" => reg_data_out <= x"0000_000" & "00" & brl_int; -- 0x054
WHEN "10110" => reg_data_out <= berr_adr; -- 0x058
WHEN "10111" => reg_data_out <= x"0000_00" & berr_iack & berr_rw & berr_vam; -- 0x05c
WHEN OTHERS => reg_data_out <= (OTHERS => '0');
END CASE;
END IF;
END PROCESS reg_out;
-------------------------------------------------------------------------------
-- dma_sta_int register 0x2c
sta :PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
dma_sta_int(3 DOWNTO 0) <= (OTHERS => '0');
dma_sta_int(9 DOWNTO 8) <= (OTHERS => '0');
set_dma_err_q <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
set_dma_err_q <= set_dma_err;
IF clr_dma_en = '1' THEN
dma_sta_int(0) <= '0';
dma_sta_int(8) <= '0';
ELSIF write_flag = '1' AND int_be(0) = '1' AND int_adr(6 DOWNTO 2) = "01011" THEN
dma_sta_int(0) <= reg_data_in(0);
dma_sta_int(8) <= reg_data_in(0);
ELSE
dma_sta_int(8) <= '0';
END IF;
IF write_flag = '1' AND int_be(0) = '1' AND int_adr(6 DOWNTO 2) = "01011" THEN
dma_sta_int(1) <= reg_data_in(1);
END IF;
IF clr_dma_en = '1' AND dma_sta_int(1) = '1' THEN
dma_sta_int(2) <= '1';
ELSIF write_flag = '1' AND int_be(0) = '1' AND int_adr(6 DOWNTO 2) = "01011" AND reg_data_in(2) = '1' THEN
dma_sta_int(2) <= '0';
END IF;
IF set_dma_err = '1' AND set_dma_err_q = '0' THEN
dma_sta_int(3) <= '1';
dma_sta_int(9) <= '0';
ELSIF write_flag = '1' AND int_be(0) = '1' AND int_adr(6 DOWNTO 2) = "01011" AND reg_data_in(3) = '1' THEN
dma_sta_int(3) <= '0';
dma_sta_int(9) <= '1';
ELSE
dma_sta_int(9) <= '0';
END IF;
END IF;
END PROCESS sta;
dma_sta_int(7 DOWNTO 4) <= dma_act_bd;
dma_sta <= dma_sta_int;
-------------------------------------------------------------------------------
int_id : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
intid_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00001" AND int_be(0) = '1' THEN
intid_int(7 DOWNTO 0) <= reg_data_in(7 DOWNTO 0);
END IF;
END IF;
END PROCESS int_id;
-------------------------------------------------------------------------------
-- PCI-offset register
-------------------------------------------------------------------------------
pci_o : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
pci_offset_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01010" AND int_be(1) = '1' THEN
pci_offset_int(15 DOWNTO 12) <= reg_data_in(15 DOWNTO 12);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01010" AND int_be(2) = '1' THEN
pci_offset_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01010" AND int_be(3) = '1' THEN
pci_offset_int(31 DOWNTO 24) <= reg_data_in(31 DOWNTO 24);
END IF;
END IF;
END PROCESS pci_o;
-------------------------------------------------------------------------------
-- Slave A24 Base address for PCI
-------------------------------------------------------------------------------
sl24_pci : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv24_pci_q_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10010" AND int_be(0) = '1' THEN
slv24_pci_q_int(4 DOWNTO 0) <= reg_data_in(4 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10010" AND int_be(1) = '1' THEN
slv24_pci_q_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
slv24_pci_q_int(7 DOWNTO 5) <= (OTHERS => '0');
END IF;
END PROCESS sl24_pci;
slv24_pci_q <= slv24_pci_q_int(15 DOWNTO 8) & "000" & slv24_pci_q_int(4 DOWNTO 0) ;
-------------------------------------------------------------------------------
-- Slave A32 Base address for PCI
-------------------------------------------------------------------------------
sl32_pci : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv32_pci_q_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10011" AND int_be(0) = '1' THEN
slv32_pci_q_int(4 DOWNTO 0) <= reg_data_in(4 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10011" AND int_be(1) = '1' THEN
slv32_pci_q_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10011" AND int_be(2) = '1' THEN
slv32_pci_q_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
slv32_pci_q_int(7 DOWNTO 5) <= (OTHERS => '0');
END IF;
END PROCESS sl32_pci;
slv32_pci_q <= slv32_pci_q_int(23 DOWNTO 8) & "000" & slv32_pci_q_int(4 DOWNTO 0);
-------------------------------------------------------------------------------
-- Here is the Interrupt Request Register:
-- Consists of (INTEN, IL2-0)
-------------------------------------------------------------------------------
int_r : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
intr_int <= (OTHERS => '0');
irq_o_n <= "1111111";
ELSIF clk'EVENT AND clk = '1' THEN
IF clr_intreq = '1' THEN
intr_int(3) <= '0';
intr_int(2 DOWNTO 0) <= intr_int(2 DOWNTO 0);
ELSIF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00000" AND int_be(0) = '1' THEN
intr_int(3 DOWNTO 0) <= reg_data_in(3 DOWNTO 0);
END IF;
IF intr_int(3) = '1' THEN
CASE intr_int(2 DOWNTO 0) IS
WHEN "001" => irq_o_n <= "1111110";
WHEN "010" => irq_o_n <= "1111101";
WHEN "011" => irq_o_n <= "1111011";
WHEN "100" => irq_o_n <= "1110111";
WHEN "101" => irq_o_n <= "1101111";
WHEN "110" => irq_o_n <= "1011111";
WHEN "111" => irq_o_n <= "0111111";
WHEN OTHERS => irq_o_n <= "1111111";
END CASE;
ELSE
irq_o_n <= "1111111";
END IF;
END IF;
END PROCESS int_r;
intr_reg <= intr_int;
-------------------------------------------------------------------------------
-- The IMASK Register. '0' means interrupt is masked, '1' means it is enabled.
-------------------------------------------------------------------------------
i_mask : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
imask <= (OTHERS => '0');
istat <= (OTHERS => '0');
berr_irq <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00011" AND int_be(0) = '1' THEN
imask <= reg_data_in(7 DOWNTO 0);
END IF;
istat <= (irqregd & acfst) AND imask;
IF mstr_int(3) = '1' AND mstr_int(2) = '1' THEN
berr_irq <= '1';
ELSE
berr_irq <= '0';
END IF;
END IF;
END PROCESS i_mask;
-------------------------------------------------------------------------------
-- Here is the Interrupt Status Register:
-- Consists of (IRQ7-1, ACFST )
-------------------------------------------------------------------------------
regirq : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
irqregd <= (OTHERS => '0');
acfailn_regd <= '1';
acfst <= '0';
ELSIF clk'event AND clk = '1' THEN
irqregd <= NOT irq_i_n;
acfailn_regd <= acfailn;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00010" AND int_be(0) = '1' THEN
acfst <= '0';
ELSIF (acfailn_regd = '0') THEN
acfst <= '1';
END IF;
END IF;
END PROCESS regirq;
-------------------------------------------------------------------------------
-- Here is the Master Register:
-- Consists of (AONLY-bit, POSTWR-bit, IBERR-bit, BERR-bit, REQ-bit, RMW-bit
-- A16_MODE, A24_MODE, A32_MODE)
-------------------------------------------------------------------------------
mstr_int(7) <= '0'; -- unused
-- RMW-bit:
rmwena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(0) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(0) <= reg_data_in(0);
ELSIF rst_rmw = '1' THEN
mstr_int(0) <= '0';
END IF;
END IF;
END PROCESS rmwena;
-- REQ-bit:
rwdena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(1) <= '0'; -- default is ROR
ELSIF clk'event AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(1) <= reg_data_in(1);
END IF;
END IF;
END PROCESS rwdena;
-- BERR-bit and BERR_ADR/BERR_ACC
berrena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(2) <= '0';
berr_vam <= (OTHERS => '0');
berr_adr <= (OTHERS => '0');
berr_rw <= '0';
berr_iack <= '0';
ELSIF (clk'event AND clk = '1') THEN
-- set bus error bit/irq for single and DMA accesses which causes an vme bus error
IF set_berr = '1' THEN
mstr_int(2) <= '1';
ELSIF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND reg_data_in(2) = '1' AND int_be(0) = '1' THEN -- write '1' to berr bit
mstr_int(2) <= '0';
END IF;
IF set_berr = '1' THEN
berr_vam <= vam_reg;
berr_adr <= vme_adr_in_reg & "00";
berr_rw <= sl_writen_reg;
berr_iack <= NOT iackn_in_reg;
ELSIF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND reg_data_in(2) = '1' AND int_be(0) = '1' THEN -- write '1' to berr bit
berr_vam <= (OTHERS => '0');
berr_adr <= (OTHERS => '0');
berr_rw <= '0';
berr_iack <= '0';
END IF;
END IF;
END PROCESS berrena;
-- IBERR-bit:
iberrena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(3) <= '0';
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(3) <= reg_data_in(3);
END IF;
END IF;
END PROCESS iberrena;
-- POSTWR-bit:
postwrena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(4) <= '0';
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(4) <= reg_data_in(4);
END IF;
END IF;
END PROCESS postwrena;
-- AONLY-bit:
aonlyena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(5) <= '0';
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(5) <= reg_data_in(5);
ELSIF rst_aonly = '1' THEN
mstr_int(5) <= '0';
END IF;
END IF;
END PROCESS aonlyena;
-- Fair_requester-bit:
fair : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(6) <= '0'; -- default not fair
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(6) <= reg_data_in(6);
END IF;
END IF;
END PROCESS fair;
-- A16_MODE-bit:
a16 : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(9 DOWNTO 8) <= "00"; -- default = non-privileged (AM=0x29)
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(1) = '1' THEN
mstr_int(9 DOWNTO 8) <= reg_data_in(9 DOWNTO 8);
END IF;
END IF;
END PROCESS a16;
-- A24_MODE-bit:
a24 : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(11 DOWNTO 10) <= "00"; -- default = non-privileged (AM=0x39)
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(1) = '1' THEN
mstr_int(11 DOWNTO 10) <= reg_data_in(11 DOWNTO 10);
END IF;
END IF;
END PROCESS a24;
-- A32_MODE-bit:
a32 : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(13 DOWNTO 12) <= "00"; -- default = non-privileged (AM=0x09)
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(1) = '1' THEN
mstr_int(13 DOWNTO 12) <= reg_data_in(13 DOWNTO 12);
END IF;
END IF;
END PROCESS a32;
mstr_reg <= mstr_int;
-------------------------------------------------------------------------------
-- Here is the System Control Register:
-- Consists of (ATO-bit, SYSR-bit, SYSC-bit)
-------------------------------------------------------------------------------
-- ato-bit
atoena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sysc_reg_int(2) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00110" AND reg_data_in(2) = '1' AND int_be(0) = '1' THEN
sysc_reg_int(2) <= '0';
ELSIF set_ato = '1' THEN
sysc_reg_int(2) <= '1';
END IF;
END IF;
END PROCESS atoena;
-- sysr-bit
sysrena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sysc_reg_int(1) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00110" AND int_be(0) = '1' THEN
sysc_reg_int(1) <= reg_data_in(1);
ELSIF clr_sysr = '1' THEN
sysc_reg_int(1) <= '0';
END IF;
END IF;
END PROCESS sysrena;
-- sysc-bit
syscena : PROCESS (clk, startup_rst)
BEGIN
IF startup_rst = '1' THEN
sysc_reg_int(0) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF set_sysc = '1' THEN
sysc_reg_int(0) <= '1';
ELSIF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00110" AND int_be(0) = '1' THEN
sysc_reg_int(0) <= reg_data_in(0);
END IF;
END IF;
END PROCESS syscena;
sysc_reg <= sysc_reg_int;
---------------------------------------------------------------------------
-- slave base address register
slv24_r : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv24_reg_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00101" AND int_be(0) = '1' THEN
slv24_reg_int(4 DOWNTO 0) <= reg_data_in(4 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00101" AND int_be(1) = '1' THEN
slv24_reg_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
slv24_reg_int(7 DOWNTO 5) <= (OTHERS => '0');
END IF;
END PROCESS slv24_r;
slv24_reg <= slv24_reg_int(15 DOWNTO 8) & "000" & slv24_reg_int(4 DOWNTO 0);
slv16_r : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv16_reg_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01100" AND int_be(0) = '1' THEN
slv16_reg_int <= reg_data_in(4 DOWNTO 0);
END IF;
END IF;
END PROCESS slv16_r;
slv16_reg <= slv16_reg_int;
slv32_r : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv32_reg_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01101" AND int_be(0) = '1' THEN
slv32_reg_int(4 DOWNTO 0) <= reg_data_in(4 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01101" AND int_be(1) = '1' THEN
slv32_reg_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01101" AND int_be(2) = '1' THEN
slv32_reg_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
slv32_reg_int(7 DOWNTO 5) <= (OTHERS => '0');
END IF;
END PROCESS slv32_r;
slv32_reg <= slv32_reg_int(23 DOWNTO 8) & "000" & slv32_reg_int(4 DOWNTO 0);
long_add : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
longadd_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00111" AND int_be(0) = '1' THEN
longadd_int <= reg_data_in(7 DOWNTO 0);
END IF;
END IF;
END PROCESS long_add;
mail_ie : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
mail_irqe <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01000" AND int_be(0) = '1' THEN
mail_irqe <= reg_data_in(7 DOWNTO 0);
END IF;
END IF;
END PROCESS mail_ie;
mail_ir : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
mail_irq_reg <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01001" AND int_be(0) = '1' THEN
IF reg_data_in(0) = '1' THEN
mail_irq_reg(0) <= '0';
END IF;
IF reg_data_in(1) = '1' THEN
mail_irq_reg(1) <= '0';
END IF;
IF reg_data_in(2) = '1' THEN
mail_irq_reg(2) <= '0';
END IF;
IF reg_data_in(3) = '1' THEN
mail_irq_reg(3) <= '0';
END IF;
IF reg_data_in(4) = '1' THEN
mail_irq_reg(4) <= '0';
END IF;
IF reg_data_in(5) = '1' THEN
mail_irq_reg(5) <= '0';
END IF;
IF reg_data_in(6) = '1' THEN
mail_irq_reg(6) <= '0';
END IF;
IF reg_data_in(7) = '1' THEN
mail_irq_reg(7) <= '0';
END IF;
ELSE
IF mail_irqe(0)= '1' AND mail_irq(0)= '1' THEN
mail_irq_reg(0) <= '1';
END IF;
IF mail_irqe(1)= '1' AND mail_irq(1)= '1' THEN
mail_irq_reg(1) <= '1';
END IF;
IF mail_irqe(2)= '1' AND mail_irq(2)= '1' THEN
mail_irq_reg(2) <= '1';
END IF;
IF mail_irqe(3)= '1' AND mail_irq(3)= '1' THEN
mail_irq_reg(3) <= '1';
END IF;
IF mail_irqe(4)= '1' AND mail_irq(4)= '1' THEN
mail_irq_reg(4) <= '1';
END IF;
IF mail_irqe(5)= '1' AND mail_irq(5)= '1' THEN
mail_irq_reg(5) <= '1';
END IF;
IF mail_irqe(6)= '1' AND mail_irq(6)= '1' THEN
mail_irq_reg(6) <= '1';
END IF;
IF mail_irqe(7)= '1' AND mail_irq(7)= '1' THEN
mail_irq_reg(7) <= '1';
END IF;
END IF;
END IF;
END PROCESS mail_ir;
mailbox_irq(0) <= '1' WHEN mail_irq_reg(0) = '1' OR mail_irq_reg(1) = '1' OR mail_irq_reg(2) = '1' OR mail_irq_reg(3) = '1' ELSE '0';
mailbox_irq(1) <= '1' WHEN mail_irq_reg(4) = '1' OR mail_irq_reg(5) = '1' OR mail_irq_reg(6) = '1' OR mail_irq_reg(7) = '1' ELSE '0';
-- clear address combination bits when clear status bit
clr_locmon(0) <= '1' WHEN write_flag = '1' AND int_adr(6 DOWNTO 2) = "01110" AND int_be(0) = '1' AND reg_data_in(3) = '1' ELSE '0';
clr_locmon(1) <= '1' WHEN write_flag = '1' AND int_adr(6 DOWNTO 2) = "01111" AND int_be(0) = '1' AND reg_data_in(3) = '1' ELSE '0';
loc_sta0 : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
locsta_0 <= (OTHERS => '0');
locmon_irq(0) <= '0';
loc_irq_0_q <= '0';
loc_sel_0_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
loc_irq_0_q <= loc_irq_0;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01110" AND int_be(0) = '1' THEN
locsta_0(5 DOWNTO 4) <= reg_data_in(5 DOWNTO 4);
locsta_0(2 DOWNTO 0) <= reg_data_in(2 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01110" AND int_be(0) = '1' AND reg_data_in(3) = '1' THEN
locsta_0(3) <= '0';
loc_sel_0_int <= (OTHERS => '0');
ELSIF loc_irq_0 = '1' AND loc_irq_0_q = '0' THEN
locsta_0(3) <= '1';
loc_sel_0_int <= loc_sel;
END IF;
IF locsta_0(0) = '1' AND locsta_0(3) = '1' THEN
locmon_irq(0) <= '1';
ELSE
locmon_irq(0) <= '0';
END IF;
END IF;
END PROCESS loc_sta0;
loc_rw_0 <= locsta_0(5 DOWNTO 4);
loc_am_0 <= locsta_0(2 DOWNTO 1);
loc_sta1 : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
locsta_1 <= (OTHERS => '0');
locmon_irq(1) <= '0';
loc_irq_1_q <= '0';
loc_sel_1_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
loc_irq_1_q <= loc_irq_1;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01111" AND int_be(0) = '1' THEN
locsta_1(5 DOWNTO 4) <= reg_data_in(5 DOWNTO 4);
locsta_1(2 DOWNTO 0) <= reg_data_in(2 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01111" AND int_be(0) = '1' AND reg_data_in(3) = '1' THEN
locsta_1(3) <= '0';
loc_sel_1_int <= (OTHERS => '0');
ELSIF loc_irq_1 = '1' AND loc_irq_1_q = '0' THEN
locsta_1(3) <= '1';
loc_sel_1_int <= loc_sel;
END IF;
IF locsta_1(0) = '1' AND locsta_1(3) = '1' THEN
locmon_irq(1) <= '1';
ELSE
locmon_irq(1) <= '0';
END IF;
END IF;
END PROCESS loc_sta1;
loc_rw_1 <= locsta_1(5 DOWNTO 4);
loc_am_1 <= locsta_1(2 DOWNTO 1);
loc_adr0 : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
loc_adr_0_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10000" THEN
IF int_be(0) = '1' THEN
loc_adr_0_int(7 DOWNTO 0) <= reg_data_in(7 DOWNTO 0);
END IF;
IF int_be(1) = '1' THEN
loc_adr_0_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
IF int_be(2) = '1' THEN
loc_adr_0_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
IF int_be(3) = '1' THEN
loc_adr_0_int(31 DOWNTO 24) <= reg_data_in(31 DOWNTO 24);
END IF;
END IF;
END IF;
END PROCESS loc_adr0;
-- loc_adr_0 <= loc_adr_0_int(7 DOWNTO 0) & loc_adr_0_int(15 DOWNTO 8) & loc_adr_0_int(23 DOWNTO 16) & loc_adr_0_int(31 DOWNTO 24);
loc_adr_0 <= loc_adr_0_int;
loc_adr1 : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
loc_adr_1_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10001" THEN
IF int_be(0) = '1' THEN
loc_adr_1_int(7 DOWNTO 0) <= reg_data_in(7 DOWNTO 0);
END IF;
IF int_be(1) = '1' THEN
loc_adr_1_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
IF int_be(2) = '1' THEN
loc_adr_1_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
IF int_be(3) = '1' THEN
loc_adr_1_int(31 DOWNTO 24) <= reg_data_in(31 DOWNTO 24);
END IF;
END IF;
END IF;
END PROCESS loc_adr1;
-- loc_adr_1 <= loc_adr_1_int(7 DOWNTO 0) & loc_adr_1_int(15 DOWNTO 8) & loc_adr_1_int(23 DOWNTO 16) & loc_adr_1_int(31 DOWNTO 24);
loc_adr_1 <= loc_adr_1_int;
brl_pr : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
brl_int <= (OTHERS => '1'); -- default request level is 3 to be compatible to old implementations
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10101" THEN
IF int_be(0) = '1' THEN
brl_int <= reg_data_in(1 DOWNTO 0);
END IF;
END IF;
END IF;
END PROCESS brl_pr;
brl <= brl_int;
END vme_du_arch;
| gpl-3.0 | 42d8625c6a1f9e84c1b8e26f01cf0ac8 | 0.481193 | 3.384832 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zProg2Bram.vhd | 1 | 911 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zProg2Bram is
port (
BRAM_PORTA_addr : in STD_LOGIC_VECTOR ( 12 downto 0 );
BRAM_PORTA_clk : in STD_LOGIC;
BRAM_PORTA_din : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : in STD_LOGIC;
BRAM_PORTA_rst : in STD_LOGIC;
BRAM_PORTA_we : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_we : out std_logic;
prog_clk : out std_logic;
prog_addr : out std_logic_vector( 9 downto 0 );
prog_din : out std_logic_vector( 17 downto 0 )
);
end zProg2Bram;
architecture STRUCTURE of zProg2Bram is
begin
prog_clk <= BRAM_PORTA_clk;
prog_addr <= BRAM_PORTA_addr( 11 downto 2 );
prog_we <= BRAM_PORTA_en when (BRAM_PORTA_addr( 1 downto 0) = "00") and ( BRAM_PORTA_we = "1111" ) else '0';
prog_din <= BRAM_PORTA_din( 17 downto 0 );
end STRUCTURE;
| gpl-2.0 | 91f28d29e7f2a309b0f43b3f223d74f3 | 0.635565 | 2.977124 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_ipif.vhd | 3 | 20,369 | -- $Id: opb_ipif.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_ipif.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ipif.vhd
-- Version: v3.01a
-- Description: Slave OPB IPIF with the following services:
-- MIR/Reset register
-- Interrupts
-- Read and Write Packet FIFOs
--
-------------------------------------------------------------------------------
-- Structure: opb_ipif
-- -- opb_bam
-- -- reset_mir
-- -- interrupt_control
-- -- rdpfifo_top
-- -- wrpfifo_top
-- -- opb_be_gen
-- -- write_buffer
-- -- srl_fifo3
-- -- brst_addr_cntr
-- -- brst_addr_cntr_reg
-- -- opb_flex_addr_cntr
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Gmm_SP1
--
-- Version 3.01.a is an update to use new common libraries and
-- incorporates write buffer logic and address counter logic.
-- This version also fixes various functionality issues.
--
-- Fixed various issues with IPIC signals when Write Buffer services
-- were used. Also, fixed issues with dynamic switching of IP2Bus_PostedWrInh
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Gmm_SP2
--
-- Fixed IP2RFIFO_Data and WFIFO2IP_Data size to be based on C_ARD_DWIDTH_ARRAY
-- generic instead of being hard coded to a size of 32 bits.
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP1
--
-- Removed a long combinatorial path on Sln_xferAck to help improve Fmax
-- timing.
--
-- Removed a long combinatorial path on Sln_Retry to help improve Fmax
-- timing.
--
-- Broke up a long timing path through the address decode stage to help
-- improve Fmax timing.
--
-- Fixed issue with IP2Bus_Postedwrinh_s2 negating incorrectly which would
-- in certain cases cause a write cycle to no be acknowledged.
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Im_SP1
--
-- Removed some unused signals and added a missing signal to a sensitiviy
-- list for minor code clean up.
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
--
-- FLO 05/19/03
-- ^^^^^^
-- Initial version.
-- ~~~~~~
--
-- ALS 10/21/03
-- ^^^^^^
-- Creation of version v3_00_b to include read and write packet FIFOs.
-- Also modified code for direct entity instantiation.
-- ~~~~~~
-- ALS 11/18/03
-- ^^^^^^
-- Creation of version v3_01_a to modify generics and some ports to align
-- with the PLB IPIF. Added look-ahead address counter for read bursts and write
-- buffer for write bursts.
-- ~~~~~~~
--
-- ALS 04/09/04
-- ^^^^^^
-- Removed vectorization of IP2Bus signals
-- ~~~~~~~
-- GAB 04/15/04
-- ^^^^^^
-- Updated to use proc_common_v2_00_a
-- Added change log
-- ~~~~~~~
-- GAB 08/10/04
-- ^^^^^^
-- - Modified port range for IP2RFIFO_Data and WFIFO2IP_Data to be based on
-- the C_ARD_DWIDTH_ARRAY generic and not hard coded. Fixes CR191551
-- ~~~~~~~
-- GAB 07/06/05
-- ^^^^^^
-- Removed xfer_abort signal from Sln_xferack logic to help improve timing.
-- ~~~~~~~
-- GAB 08/05/05
-- ^^^^^^
-- Fixed issue with IP2Bus_Postedwrinh_s2 getting reset with OPB_Select would
-- negate. IP2Bus_Postedwrinh_s2 should only negat based on UserIP.
-- ~~~~~~~
-- GAB 09/21/05
-- ^^^^^^
-- Fixed long timing path issue with Sln_Retry signal and cycle aborts. Modified
-- logic to suppress sln_xferack_s1 with cycle_abort for models where out-pipe was
-- included.
-- ~~~~~~~
-- GAB 10/12/05
-- ^^^^^^
-- Incorperated rev C mods into rev A to fix slow timing path with the address
-- decode. The modification simply shifts the input pipe stage for the address
-- to after the address decode. Therefore the functionality does not change
-- nor does the latency. This fix only improves pipeline 5 and 7 (i.e. any
-- with a model with a input pipeline stage).
-- ~~~~~~~
-- GAB 5/19/06
-- ^^^^^^
-- Removed unused last_wr_xferack, last_wr_xferack_d1,
-- and last_wr_xferack_d2 from opb_bam.vhd
-- Added bus2ip_rnw_s1 signal to SLN_XFERACK_PROC process's sinsitivity list
-- in opb_bam.vhd
-- This fixes CR231744.
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_bam;
use opb_v20_v1_10_d.ipif_pkg.all;
use opb_v20_v1_10_d.proc_common_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_ipif is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE
:=( 0 => IPIF_INTR,
1 => IPIF_RST,
2 => USER_00 );
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:=( x"0000_0000_6000_0000",
x"0000_0000_6000_003F",
x"0000_0000_6000_0040",
x"0000_0000_6000_0043",
x"0000_0000_6000_0100",
x"0000_0000_6000_01FF" );
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
:=( 32,
32,
32 );
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:=( 16,
1,
8 );
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE
:=( 0 => (others => 0),
1 => (others => 0),
2 => (others => 0) );
C_PIPELINE_MODEL : integer := 7;
C_DEV_BLK_ID : integer := 1;
C_DEV_MIR_ENABLE : integer := 0;
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string
:= "virtexe";
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE
:=( 5,
1 );
C_DEV_BURST_ENABLE : integer := 0;
C_INCLUDE_ADDR_CNTR : integer := 0;
C_INCLUDE_WR_BUF : integer := 0
);
port
(
-- OPB signals
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
-- IPIC signals (address, data, acknowledge)
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1);
Bus2IP_AddrValid : out std_logic;
Bus2IP_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_OPB_DWIDTH-1);
IP2Bus_Ack : in std_logic;
IP2Bus_AddrAck : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_ToutSup : in std_logic;
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
-- IPIC signals (Read Packet FIFO)
IP2RFIFO_Data : in std_logic_vector(0 to C_ARD_DWIDTH_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA)) - 1) := (others => '0');
IP2RFIFO_WrMark : in std_logic := '0';
IP2RFIFO_WrRelease : in std_logic := '0';
IP2RFIFO_WrReq : in std_logic := '0';
IP2RFIFO_WrRestore : in std_logic := '0';
RFIFO2IP_AlmostFull : out std_logic;
RFIFO2IP_Full : out std_logic;
RFIFO2IP_Vacancy : out std_logic_vector(0 to bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe
(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA))) - 1);
RFIFO2IP_WrAck : out std_logic;
-- IPIC signals (Write Packet FIFO)
IP2WFIFO_RdMark : in std_logic := '0';
IP2WFIFO_RdRelease : in std_logic := '0';
IP2WFIFO_RdReq : in std_logic := '0';
IP2WFIFO_RdRestore : in std_logic := '0';
WFIFO2IP_AlmostEmpty: out std_logic;
WFIFO2IP_Data : out std_logic_vector(0 to C_ARD_DWIDTH_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA)) - 1);
WFIFO2IP_Empty : out std_logic;
WFIFO2IP_Occupancy : out std_logic_vector(0 to bits_needed_for_occ(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe
(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA))) - 1);
WFIFO2IP_RdAck : out std_logic;
-- interrupts
IP2Bus_IntrEvent : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
IP2INTC_Irpt : out std_logic;
-- Software test breakpoint signal
Freeze : in std_logic;
Bus2IP_Freeze : out std_logic;
-- clocks and reset
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic
);
end entity opb_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of opb_ipif is
begin ------------------------------------------------------------------------
OPB_BAM_I : entity opb_v20_v1_10_d.opb_bam
generic map
(
C_ARD_ID_ARRAY => C_ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => C_ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => C_ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => C_PIPELINE_MODEL,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => C_DEV_BURST_ENABLE,
-- set this just for initial testing
C_INCLUDE_ADDR_CNTR => C_INCLUDE_ADDR_CNTR,
C_INCLUDE_WR_BUF => C_INCLUDE_WR_BUF
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sln_DBus,
Sln_xferAck => Sln_xferAck,
Sln_errAck => Sln_errAck,
Sln_retry => Sln_retry,
Sln_toutSup => Sln_toutSup,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_CE => Bus2IP_CE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_AddrValid => Bus2IP_AddrValid,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_Burst => Bus2IP_Burst,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_Ack => IP2Bus_Ack,
IP2Bus_AddrAck => IP2Bus_AddrAck,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Retry => IP2Bus_Retry,
IP2Bus_ToutSup => IP2Bus_ToutSup,
IP2Bus_PostedWrInh => IP2Bus_PostedWrInh,
IP2RFIFO_Data => IP2RFIFO_Data,
IP2RFIFO_WrMark => IP2RFIFO_WrMark,
IP2RFIFO_WrRelease => IP2RFIFO_WrRelease,
IP2RFIFO_WrReq => IP2RFIFO_WrReq,
IP2RFIFO_WrRestore => IP2RFIFO_WrRestore,
RFIFO2IP_AlmostFull => RFIFO2IP_AlmostFull,
RFIFO2IP_Full => RFIFO2IP_Full,
RFIFO2IP_Vacancy => RFIFO2IP_Vacancy,
RFIFO2IP_WrAck => RFIFO2IP_WrAck,
IP2WFIFO_RdMark => IP2WFIFO_RdMark,
IP2WFIFO_RdRelease => IP2WFIFO_RdRelease,
IP2WFIFO_RdReq => IP2WFIFO_RdReq,
IP2WFIFO_RdRestore => IP2WFIFO_RdRestore,
WFIFO2IP_AlmostEmpty => WFIFO2IP_AlmostEmpty,
WFIFO2IP_Data => WFIFO2IP_Data,
WFIFO2IP_Empty => WFIFO2IP_Empty,
WFIFO2IP_Occupancy => WFIFO2IP_Occupancy,
WFIFO2IP_RdAck => WFIFO2IP_RdAck,
IP2Bus_IntrEvent => IP2Bus_IntrEvent,
IP2INTC_Irpt => IP2INTC_Irpt,
Freeze => Freeze,
Bus2IP_Freeze => Bus2IP_Freeze,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => Bus2IP_Clk,
IP2Bus_Clk => IP2Bus_Clk,
Reset => Reset,
Bus2IP_Reset => Bus2IP_Reset
);
end architecture imp;
| bsd-3-clause | 95d55a560d612dd76598eb62005f3b79 | 0.459227 | 4.193741 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_thread_manager_smp_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 73,049 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
--
-- Title Thread Manager
--
-- 26 Jul 2004: Mike Finley: Original author
-- 08 Jun 2005: Erik Anderson: Changes for new interface between TM and
-- Scheduler. Also adding function isQueue().
-- 15 Apr 2009: Jim Stevens: Ported to PLB version 4.6.
--
---------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_NUM_CPUS : integer := 2;
C_RESET_TIMEOUT : natural := 4096
);
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 0);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
-- current_thread for CPU 0 = tm2sch_cpu_thread_id(0 to 7)
-- current_thread for CPU 1 = tm2sch_cpu_thread_id(8 to 15)
-- current_thread for CPU N = tm2sch_cpu_thread_id(8*(N-1) to 8*N-1)
tm2sch_cpu_thread_id : out std_logic_vector(0 to (8 * C_NUM_CPUS) - 1);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Define the memory map for each register, Address[16 to 21]
constant C_CLEAR_THREAD : std_logic_vector(0 to 5) := "000000";
constant C_JOIN_THREAD : std_logic_vector(0 to 5) := "000001";
constant C_READ_THREAD : std_logic_vector(0 to 5) := "000011";
constant C_ADD_THREAD : std_logic_vector(0 to 5) := "000100";
constant C_CREATE_THREAD_J : std_logic_vector(0 to 5) := "000101";
constant C_CREATE_THREAD_D : std_logic_vector(0 to 5) := "000110";
constant C_EXIT_THREAD : std_logic_vector(0 to 5) := "000111";
constant C_NEXT_THREAD : std_logic_vector(0 to 5) := "001000";
constant C_YIELD_THREAD : std_logic_vector(0 to 5) := "001001";
constant C_READ_DEBUG_1 : std_logic_vector(0 to 5) := "001111";
constant C_CURRENT_THREAD : std_logic_vector(0 to 5) := "010000";
constant C_EXCEPTION_ADDR : std_logic_vector(0 to 5) := "010011";
constant C_EXCEPTION_REG : std_logic_vector(0 to 5) := "010100";
constant C_SOFT_START : std_logic_vector(0 to 5) := "010101";
constant C_SOFT_STOP : std_logic_vector(0 to 5) := "010110";
constant C_SOFT_RESET : std_logic_vector(0 to 5) := "010111";
constant C_IS_QUEUED : std_logic_vector(0 to 5) := "011001";
constant C_SCHED_LINES : std_logic_vector(0 to 5) := "011010";
constant C_IS_DETACHED : std_logic_vector(0 to 5) := "011000";
constant C_READ_DEBUG_0 : std_logic_vector(0 to 5) := "011011";
constant C_ASSIGN_CPU : std_logic_vector(0 to 5) := "011111";
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
constant OPCODE_IS_QUEUED : std_logic_vector(0 to 5) := "000001";
constant OPCODE_ENQUEUE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DEQUEUE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_IS_EMPTY : std_logic_vector(0 to 5) := "000110";
constant OPCODE_IDLE_REQ : std_logic_vector(0 to 5) := "001100";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant H32 : std_logic_vector(0 to 31) := (others => '1');
constant MAX_QUEUE_SIZE : std_logic_vector(0 to 7) := (others => '1');
constant TOUT_CYCLES : natural := 3; -- assert timeout suppress
signal cycle_count : std_logic_vector(0 to 15);
signal timeout_expired : std_logic;
-- Extended Thread Error Codes returned in lower 4 bits
constant ERROR_IN_STATUS : std_logic_vector(0 to 3) := "0001";
constant THREAD_ALREADY_TERMINATED : std_logic_vector(0 to 3) := "0011";
constant THREAD_ALREADY_QUEUED : std_logic_vector(0 to 3) := "0101";
constant ERROR_FROM_SCHEDULER : std_logic_vector(0 to 3) := "0111";
constant JOIN_ERROR_CHILD_JOINED : std_logic_vector(0 to 3) := "1001";
constant JOIN_ERROR_NOT_CHILD : std_logic_vector(0 to 3) := "1011";
constant JOIN_ERROR_CHILD_DETACHED : std_logic_vector(0 to 3) := "1101";
constant JOIN_ERROR_CHILD_NOT_USED : std_logic_vector(0 to 3) := "1111";
constant JOIN_ERROR_UNKNOWN : std_logic_vector(0 to 3) := "0001";
constant CLEAR_ERROR_NOT_USED : std_logic_vector(0 to 3) := "1001";
-- Exception "cause" returned in Exception register
constant EXCEPTION_WRITE_TO_READ_ONLY : std_logic_vector(0 to 3) := "0001";
constant EXCEPTION_UNDEFINED_ADDRESS : std_logic_vector(0 to 3) := "0010";
constant EXCEPTION_TO_SOFT_RESET : std_logic_vector(0 to 3) := "0011";
constant EXCEPTION_TO_SCHD_ISQUEUED : std_logic_vector(0 to 3) := "0100";
constant EXCEPTION_TO_SCHD_ENQUEUE : std_logic_vector(0 to 3) := "0101";
constant EXCEPTION_TO_SCHD_DEQUEUE : std_logic_vector(0 to 3) := "0110";
constant EXCEPTION_TO_SCHD_ISEMPTY : std_logic_vector(0 to 3) := "0111";
constant EXCEPTION_TO_SCHD_NEXT_THREAD : std_logic_vector(0 to 3) := "1000";
constant EXCEPTION_SCHD_INVALID_THREAD : std_logic_vector(0 to 3) := "1001";
constant EXCEPTION_TO_IDLE_REQUEST : std_logic_vector(0 to 3) := "1010";
constant EXCEPTION_ILLEGAL_STATE : std_logic_vector(0 to 3) := "1111";
-- BRAM constants
constant BRAM_ADDRESS_BITS : integer := 9;
constant BRAM_DATA_BITS : integer := 32;
-- Address,Cause for access exceptions
signal Exception_Address : std_logic_vector(0 to 31);
signal Exception_Address_next : std_logic_vector(0 to 31);
signal Exception_Cause : std_logic_vector(0 to 3);
signal Exception_Cause_next : std_logic_vector(0 to 3);
signal access_error : std_logic;
-- Debug control signals
-- Soft reset signals, LSB = SWTM reset; reset IP(s) if '1'
-- Resets done, handshake from IPs if done resetting(1)
-- core_stop, halt state machines at next appropriate point if '1'
signal soft_resets : std_logic_vector(0 to 4);
signal soft_resets_next : std_logic_vector(0 to 4);
signal resets_done : std_logic_vector(0 to 4);
signal reset_status : std_logic_vector(0 to 4);
signal reset_status_next : std_logic_vector(0 to 4);
signal core_stop : std_logic;
signal core_stop_next : std_logic;
-- Local copy of port signal TM2SCH_current_cpu_tid
-- Current thread: bits 0..7 = ID, bit 8 = '1' = invalid
signal current_thread_id_reg : std_logic_vector(0 to 9*C_NUM_CPUS - 1);
signal current_thread_id_reg_next : std_logic_vector(0 to 9*C_NUM_CPUS - 1);
-- Local copy of port signal SCH2TM_next_tid_valid
signal Next_Thread_Valid_reg : std_logic_vector(0 to C_NUM_CPUS - 1);
-- Local copy of port signal SCH2TM_next_cpu_tid
signal next_thread_id_reg : std_logic_vector(0 to 8*C_NUM_CPUS - 1);
-- This signal stores information about which CPU we are currently using
alias current_CPU : std_logic_vector(0 to 1) is Bus2IP_Addr(14 to 15);
signal current_CPU_int : integer;
-- Debug Registers
signal debug_reg_0 : std_logic_vector(0 to 31);
signal debug_reg_next_0 : std_logic_vector(0 to 31);
signal debug_reg_1 : std_logic_vector(0 to 31);
signal debug_reg_next_1 : std_logic_vector(0 to 31);
-- CPUID that is sent to the CPU
signal set_cpu_num : std_logic_vector(0 to 1);
signal set_cpu_num_next : std_logic_vector(0 to 1);
-- internal signals
signal next_ID : std_logic_vector(0 to 8);
signal next_ID_next : std_logic_vector(0 to 8);
signal temp_thread_id : std_logic_vector(0 to 7);
signal temp_thread_id_next : std_logic_vector(0 to 7);
signal reset_ID : std_logic_vector(0 to 8);
type swtm_state_type is
(IDLE_STATE,
SOFT_RESET_WRITE_INIT,
SOFT_RESET_INIT_TABLE,
SOFT_RESET_WAIT,
READ_THREAD_INIT,
READ_THREAD_RD_WAIT,
READ_THREAD_DONE,
CREATE_THREAD_INIT,
CT_NEW_ID_RD_WAIT,
CT_NEW_ID_AVAILABLE,
CT_ENTRY_RD_WAIT,
CT_ENTRY_AVAILABLE,
CT_DONE,
CLEAR_THREAD_INIT,
CLEAR_ENTRY_RD_WAIT,
CLEAR_ENTRY_AVAIABLE,
DEALLOCATE_ID,
DEALLOCATE_NEXT_ENTRY_RD_WAIT,
DEALLOCATE_NEXT_ENTRY_AVAIL,
CURRENT_THREAD_INIT,
CURRENT_THREAD_WAIT_FOR_CPUID,
CURRENT_THREAD_WAIT_FINISHED,
JOIN_THREAD_INIT,
JOIN_RD_ENTRY_RD_WAIT,
JOIN_RD_ENTRY_AVAILABLE,
IS_QUEUED_INIT,
IS_QUEUED_DONE,
IS_DETACHED_THREAD_INIT,
IS_DETACHED_ENTRY_RD_WAIT,
IS_DETACHED_ENTRY_AVAILABLE,
NEXT_THREAD_INIT,
NEXT_THREAD_WAIT4_SCHEDULER,
NEXT_THREAD_RD_WAIT,
NEXT_THREAD_AVAILABLE,
NEXT_THREAD_CHECK_DEQUEUE,
NEXT_THREAD_CHECK_IDLE,
NEXT_THREAD_CHECK_QUEUE_EMPTY,
NEXT_THREAD_IDLE_WAIT_ACK,
NEXT_THREAD_IDLE_WAIT_COMPLETE,
NEXT_THREAD_IDLE_REQ,
NEXT_THREAD_CHECK_IDLE_REQ,
ADD_THREAD_INIT,
AT_ENTRY_RD_WAIT,
AT_ENTRY_AVAILABLE,
AT_ISQUEUED_WAIT,
AT_CHECK_ISQUEUE,
AT_ENQUEUE_WAIT,
AT_CHECK_ENQUEUE,
ISQUEUED_WAIT_ACK,
ISQUEUED_WAIT_COMPLETE,
ASSIGN_CPU_INIT,
READ_DEBUG_0,
READ_DEBUG_1,
ENQUEUE_WAIT_ACK,
ENQUEUE_WAIT_COMPLETE,
DEQUEUE_WAIT_ACK,
DEQUEUE_WAIT_COMPLETE,
IS_QUEUE_EMPTY_WAIT_ACK,
IS_QUEUE_EMPTY_WAIT_COMPLETE,
YIELD_THREAD_INIT,
YIELD_CURRENT_THREAD_RD_WAIT,
YIELD_CURRENT_THREAD_AVAILABLE,
YIELD_CHECK_QUEUE_EMPTY,
YIELD_ENQUEUE,
YIELD_CHECK_ENQUEUE,
YIELD_IS_IDLE_WAIT_ACK,
YIELD_IS_IDLE_WAIT_COMPLETE,
YIELD_CHECK_IDLE,
YIELD_CHECK_IS_IDLE_REQ,
-- YIELD_dummy_is_queued,
YIELD_DEQUEUE,
YIELD_DEQUEUE_IDLE,
YIELD_CHECK_DEQUEUE,
EXIT_THREAD_INIT,
EXIT_THREAD_RD_WAIT,
EXIT_THREAD_AVAIABLE,
EXIT_DEALLOCATE,
EXIT_NEXT_THREAD_RD_WAIT,
EXIT_NEXT_THREAD_AVAILABLE,
EXIT_READ_PARENT,
EXIT_READ_PARENT_WAIT,
EXIT_READ_PARENT_AVAILABLE,
EXIT_CHECK_ENQUEUE,
RAISE_EXCEPTION,
END_TRANSACTION,
END_TRANSACTION_WAIT
);
signal current_state, next_state : swtm_state_type := IDLE_STATE;
signal return_state, return_state_next : swtm_state_type := IDLE_STATE;
signal bus_data_out : std_logic_vector(0 to 31);
signal bus_data_out_next : std_logic_vector(0 to 31);
signal current_status : std_logic_vector(0 to 31);
signal current_status_next : std_logic_vector(0 to 31);
signal Swtm_Reset_Done : std_logic;
signal Swtm_Reset_Done_next : std_logic;
signal new_ID : std_logic_vector(0 to 7);
signal new_ID_next : std_logic_vector(0 to 7);
signal tm2sch_request_next : std_logic;
signal tm2sch_request_reg : std_logic;
signal tm2sch_data_next : std_logic_vector(0 to 7);
signal tm2sch_data_reg : std_logic_vector(0 to 7);
signal tm2sch_opcode_next : std_logic_vector(0 to 5);
signal tm2sch_opcode_reg : std_logic_vector(0 to 5);
-- Signals for thread table BRAM
signal ENA : std_logic;
signal WEA : std_logic;
signal ADDRA : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1);
signal DIA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
signal DOA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
alias addr : std_logic_vector(0 to 5) is Bus2IP_Addr(16 to 21);
signal my_ack : std_logic;
---------------------------------------------------------------------------
-- Component Instantiation of inferred dual ported block RAM
---------------------------------------------------------------------------
component infer_bram_dual_port is
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port
(
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIB : in std_logic_vector(0 to DATA_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_bram_dual_port;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
current_CPU_int <= conv_integer(current_CPU);
---------------------------------------------------------------------------
-- Entitiy instantiation of dual prot BRAM for thread table
---------------------------------------------------------------------------
thread_table_bram : infer_bram_dual_port
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA,
CLKB => Bus2IP_Clk,
ENB => sch2tm_ENB,
WEB => sch2tm_WEB,
ADDRB => sch2tm_ADDRB,
DIB => sch2tm_DIB,
DOB => tm2sch_DOB
);
tm2sch_opcode <= tm2sch_opcode_reg;
tm2sch_data <= tm2sch_data_reg;
tm2sch_request <= tm2sch_request_reg;
Soft_Stop <= core_stop;
Scheduler_Reset <= soft_resets(3);
Semaphore_Reset <= soft_resets(2);
SpinLock_Reset <= soft_resets(1);
User_IP_Reset <= soft_resets(0);
Access_Intr <= access_error;
CYCLE_PROC : process (Bus2IP_Clk, Bus2IP_CS) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
if( Bus2IP_CS(0) = '0' ) then
cycle_count <= (others => '0');
else
cycle_count <= cycle_count + 1;
end if;
end if;
end process CYCLE_PROC;
-- Create a counter for the number of elapsed cycles
-- in each bus transaction. Assert TimeOut suppress
-- when count = TOUT_CYCLES
CYCLE_CONTROL : process( cycle_count ) is
begin
IP2Bus_Error <= '0'; -- no error
-- Count the number of elapsed clock cycles in transaction
if cycle_count < C_RESET_TIMEOUT then
timeout_expired <= '0';
else
timeout_expired <= '1';
end if;
end process CYCLE_CONTROL;
RESET_PROC : process (Bus2IP_Clk, addr, current_state)
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( addr = C_SOFT_RESET and current_state = SOFT_RESET_WRITE_INIT ) then
reset_ID <= (others => '0');
else
reset_ID <= reset_ID + 1;
end if;
end if;
end process;
ACK_PROC : process(my_ack, Bus2IP_RdCE, Bus2IP_WrCE)
begin
if (Bus2IP_RdCE(0) = '1') then
IP2Bus_RdAck <= my_ack;
else
IP2Bus_RdAck <= '0';
end if;
if (Bus2IP_WrCE(0) = '1') then
IP2Bus_WrAck <= my_ack;
else
IP2Bus_WrAck <= '0';
end if;
end process;
SWTM_STATE_PROC : process (Bus2IP_Clk, core_stop_next, new_ID_next, next_ID_next, temp_thread_id_next,
current_thread_id_reg_next, Current_status_next, soft_resets_next, reset_status_next,
Swtm_Reset_Done_next, Scheduler_Reset_Done, Semaphore_Reset_Done, SpinLock_Reset_Done,
User_IP_Reset_Done, next_state, return_state_next, Bus2IP_Reset,Exception_Cause_next) is
begin
if (Bus2IP_Clk'event and (Bus2IP_Clk = '1')) then
core_stop <= core_stop_next;
new_ID <= new_ID_next;
next_ID <= next_ID_next;
temp_thread_id <= temp_thread_id_next;
current_thread_id_reg <= current_thread_id_reg_next;
for i in 0 to (C_NUM_CPUS - 1) loop
tm2sch_cpu_thread_id((8 * i) to ((8 * i) + 7)) <= current_thread_id_reg_next((9 * i) to ((9 * i) + 7));
end loop;
tm2sch_data_reg <= tm2sch_data_next;
tm2sch_opcode_reg <= tm2sch_opcode_next;
tm2sch_request_reg <= tm2sch_request_next;
current_status <= current_status_next;
Exception_Address <= Exception_Address_next;
Exception_Cause <= Exception_Cause_next;
soft_resets <= soft_resets_next;
reset_status <= reset_status_next;
bus_data_out <= bus_data_out_next;
Swtm_Reset_Done <= Swtm_Reset_Done_next;
resets_done(4) <= Swtm_Reset_Done_next;
resets_done(3) <= Scheduler_Reset_Done;
resets_done(2) <= Semaphore_Reset_Done;
resets_done(1) <= SpinLock_Reset_Done;
resets_done(0) <= User_IP_Reset_Done;
return_state <= return_state_next;
debug_reg_0 <= debug_reg_next_0;
debug_reg_1 <= debug_reg_next_1;
set_cpu_num <= set_cpu_num_next;
if( Bus2IP_Reset = '1' ) then
current_state <= IDLE_STATE;
else
current_state <= next_state;
end if;
end if;
end process SWTM_STATE_PROC;
SWTM_LOGIC_PROC : process (current_state, core_stop, new_ID, next_ID, current_thread_id_reg, current_status,
reset_status, Swtm_Reset_Done, soft_resets, Bus2IP_Addr, Bus2IP_Data, Exception_Address,
Bus2IP_WrCE, addr, Bus2IP_RdCE, reset_ID, resets_done, timeout_expired, DOA,
sch2tm_next_id_valid, sch2tm_next_id, sch2tm_busy, bus_data_out, Exception_Cause,
tm2sch_request_reg, tm2sch_data_reg, tm2sch_opcode_reg, temp_thread_id, debug_reg_0,
debug_reg_1, set_cpu_num, return_state, sch2tm_data, current_CPU_int) is
begin
-- -------------------------------------------------
-- default output signal assignments
-- -------------------------------------------------
my_ack <= '0'; -- pulse(010) to end bus transaction
access_error <= '0'; -- pulse(010) for access error interrupt
IP2Bus_Data <= (others => '0');
ADDRA <= (others => '0');
ENA <= '0';
WEA <= '0';
DIA <= (others => '0');
-- -------------------------------------------------
-- default register assignments
-- -------------------------------------------------
next_state <= current_state;
return_state_next <= return_state;
core_stop_next <= core_stop;
new_ID_next <= new_ID;
next_ID_next <= next_ID;
temp_thread_id_next <= temp_thread_id;
current_thread_id_reg_next <= current_thread_id_reg;
current_status_next <= current_status;
Exception_Address_next <= Exception_Address;
reset_status_next <= reset_status;
Swtm_Reset_Done_next <= Swtm_Reset_Done;
Exception_Cause_next <= Exception_Cause;
tm2sch_request_next <= tm2sch_request_reg;
tm2sch_data_next <= tm2sch_data_reg;
tm2sch_opcode_next <= tm2sch_opcode_reg;
bus_data_out_next <= bus_data_out;
soft_resets_next <= soft_resets;
debug_reg_next_0 <= debug_reg_0;
debug_reg_next_1 <= debug_reg_1;
set_cpu_num_next <= set_cpu_num;
case current_state is
-- Command (addr) decode whenever we are waiting for something new to do.
when IDLE_STATE =>
bus_data_out_next <= (others => '0');
if (Bus2IP_WrCE(0) = '1') then
case addr is
when C_SOFT_START =>
debug_reg_next_0 <= Z32(0 to 14) & '1' & Z32(16 to 30) & '1';
-- Any write to soft_start address clears
-- all soft reset signals and the Soft_Stop signal
soft_resets_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset done
core_stop_next <= '0'; -- clear core_stop
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
debug_reg_next_0 <= Z32(0 to 15) & '1' & Z32(17 to 30) & '1';
-- write any data to Soft_Stop to assert the Soft_Stop signal
core_stop_next <= '1';
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
debug_reg_next_0 <= Z32(0 to 16) & '1' & Z32(18 to 30) & '1';
next_state <= SOFT_RESET_WRITE_INIT;
when C_READ_THREAD =>
if (core_stop = '1') then
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '1';
ENA <= '1';
DIA <= Bus2IP_Data(0 to 31);
next_state <= END_TRANSACTION;
else
Exception_Cause_next <= EXCEPTION_WRITE_TO_READ_ONLY;
next_state <= RAISE_EXCEPTION;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
elsif (Bus2IP_RdCE(0) = '1') then
case addr is
when C_SOFT_START =>
debug_reg_next_0 <= Z32(0 to 14) & '1' & Z32(16 to 31);
bus_data_out_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
debug_reg_next_0 <= Z32(0 to 15) & '1' & Z32(17 to 31);
-- returns signal level in LSB on read
bus_data_out_next <= Z32(0 to 30) & core_stop;
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
debug_reg_next_0 <= Z32(0 to 16) & '1' & Z32(18 to 31);
-- returns 1's in bit positions that failed
bus_data_out_next <= Z32(0 to 26) & reset_status;
next_state <= END_TRANSACTION;
when C_EXCEPTION_ADDR =>
debug_reg_next_0 <= Z32(0 to 12) & '1' & Z32(14 to 31);
bus_data_out_next <= Exception_Address;
Exception_Address_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_EXCEPTION_REG =>
debug_reg_next_0 <= Z32(0 to 13) & '1' & Z32(15 to 31);
bus_data_out_next <= Z32(0 to 27) & Exception_Cause;
Exception_Cause_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SCHED_LINES =>
debug_reg_next_0 <= Z32(0 to 17) & '1' & Z32(19 to 31);
bus_data_out_next <= Z32(0 to 6) & sch2tm_busy & sch2tm_data & Z32(16 to 22) & sch2tm_next_id_valid & sch2tm_next_id;
next_state <= END_TRANSACTION;
when C_CURRENT_THREAD => next_state <= CURRENT_THREAD_INIT;
when C_READ_THREAD => next_state <= READ_THREAD_INIT;
when C_CREATE_THREAD_D => next_state <= CREATE_THREAD_INIT;
when C_CREATE_THREAD_J => next_state <= CREATE_THREAD_INIT;
when C_CLEAR_THREAD => next_state <= CLEAR_THREAD_INIT;
when C_JOIN_THREAD => next_state <= JOIN_THREAD_INIT;
when C_IS_DETACHED => next_state <= IS_DETACHED_THREAD_INIT;
when C_IS_QUEUED => next_state <= IS_QUEUED_INIT;
when C_NEXT_THREAD => next_state <= NEXT_THREAD_INIT;
when C_ADD_THREAD => next_state <= ADD_THREAD_INIT;
when C_YIELD_THREAD => next_state <= YIELD_THREAD_INIT;
when C_EXIT_THREAD => next_state <= EXIT_THREAD_INIT;
when C_ASSIGN_CPU => next_state <= ASSIGN_CPU_INIT;
when C_READ_DEBUG_0 => next_state <= READ_DEBUG_0;
when C_READ_DEBUG_1 => next_state <= READ_DEBUG_1;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
end if;
-- Read/Write to the soft resets register (1 bit per IP)
-- Write '1' to reset, reads '1' if timeout error occured
-- before IP reports finished
--
-- SW Thread Manager = bit#4 (LSB)
-- Scheduler = bit#3
-- Semaphore = bit#2
-- SpinLock = bit#1
-- User_IP = bit#0
when SOFT_RESET_WRITE_INIT =>
soft_resets_next <= Bus2IP_Data(27 to 31);
reset_status_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset_done
debug_reg_next_1 <= "01011010" & Z32(8 to 26) & Bus2IP_Data(27 to 31);
if (Bus2IP_Data(31) = '1') then -- soft_resets(4)
debug_reg_next_1 <= "10100101" & Z32(8 to 26) & Bus2IP_Data(27 to 31);
-- Perform a soft reset on SWTM
bus_data_out_next <= (others => '0');
new_ID_next <= (others => '0');
next_ID_next <= (others => '0');
temp_thread_id_next <= (others => '0');
set_cpu_num_next <= (others => '0');
for i in 0 to (C_NUM_CPUS - 1) loop
current_thread_id_reg_next((9 * i) to ((9 * i) + 8)) <= Z32(0 to 7) & '1';
end loop;
core_stop_next <= '0';
tm2sch_opcode_next <= OPCODE_NOOP;
tm2sch_data_next <= (others => '0');
tm2sch_request_next <= '0';
next_state <= SOFT_RESET_INIT_TABLE;
else
next_state <= SOFT_RESET_WAIT;
end if;
-- Initialize the thread ID table to all zeros
-- and the next available stack to 0..255
when SOFT_RESET_INIT_TABLE =>
debug_reg_next_1 <= debug_reg_1(0 to 7) & reset_ID & Z32(17 to 31);
ADDRA <= reset_ID;
ENA <= '1';
WEA <= '1';
if( reset_ID(0) = '0' ) then
-- init available ID stack & thread ID table
DIA <= reset_ID(1 to 8) & Z32(0 to 23);
else
-- Clear 2nd half of table (unused)
DIA <= Z32(0 to 31);
end if;
if( reset_ID = H32(0 to 8) ) then
swtm_reset_done_next<= '1'; -- done
next_state <= soft_reset_wait;
end if;
-- Wait for all IPs to finish initialization or
-- the maximum time to be exceeded then ack to finish transaction
when SOFT_RESET_WAIT =>
if (resets_done = soft_resets) then -- done
next_state <= END_TRANSACTION;
elsif (timeout_expired = '1') then
reset_status_next <= (resets_done xor soft_resets);
Exception_Cause_next <= EXCEPTION_TO_SOFT_RESET;
next_state <= RAISE_EXCEPTION; -- timeout
else
next_state <= current_state;
end if;
when CURRENT_THREAD_INIT =>
debug_reg_next_0 <= Z32(0 to 9) & '1' & Z32(11 to 31);
next_state <= CURRENT_THREAD_WAIT_FOR_CPUID;
when CURRENT_THREAD_WAIT_FOR_CPUID =>
-- idle state, waiting for the cpuid to process correctly
next_state <= CURRENT_THREAD_WAIT_FINISHED;
when CURRENT_THREAD_WAIT_FINISHED =>
debug_reg_next_0 <= debug_reg_0(0 to 13) & current_CPU & Z32(16 to 31);
debug_reg_next_1 <= current_thread_id_reg(0 to 7) & current_thread_id_reg(9 to 16) & Z32(16 to 31);
bus_data_out_next <= Z32(0 to 22) & current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 8));
next_state <= END_TRANSACTION;
when READ_DEBUG_0 =>
-- write debug info out to bus
bus_data_out_next <= debug_reg_0;
next_state <= END_TRANSACTION;
when READ_DEBUG_1 =>
-- write debug info out to bus
bus_data_out_next <= debug_reg_1;
next_state <= END_TRANSACTION;
----------------------------
-- ASSIGN_CPU_INIT: begin
----------------------------
-- Assigns a unique identifier to the requesting processor
-- returns zero or one on the bus, could be easily modified to return values for more than two processors
when ASSIGN_CPU_INIT =>
-- Put the CPU number out on the bus
bus_data_out_next <= Z32(0 to 29) & set_cpu_num;
-- If set_cpu_num is one then reset back to zero - two processor system
if(set_cpu_num = x"1") then
set_cpu_num_next <= "00";
else
set_cpu_num_next <= set_cpu_num + 1;
end if;
next_state <= END_TRANSACTION;
----------------------------
-- ASSIGN_CPU_INIT: end
----------------------------
when READ_THREAD_INIT =>
debug_reg_next_0 <= Z32(0 to 3) & '1' & Z32(5 to 31);
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '0';
ENA <= '1';
next_state <= READ_THREAD_RD_WAIT;
when READ_THREAD_RD_WAIT =>
next_state <= READ_THREAD_DONE;
when READ_THREAD_DONE =>
bus_data_out_next <= DOA;
next_state <= END_TRANSACTION;
when CREATE_THREAD_INIT =>
--debug_reg_next_0 <= Z32(0 to 5) & '1' & Z32(7 to 31);
debug_reg_next_0 <= "1111" & Z32(4 to 22) & next_ID;
if next_ID(0) = '1' then
debug_reg_next_0 <= "0111" & Z32(4 to 22) & next_ID;
-- No IDs available, return with error bit set
bus_data_out_next <= Z32(0 to 30) & '1';
next_state <= END_TRANSACTION;
else
debug_reg_next_0 <= "1011" & Z32(4 to 22) & next_ID;
-- Read next ID from stack
ADDRA <= next_ID;
ENA <= '1';
next_state <= CT_NEW_ID_RD_WAIT;
end if;
when CT_NEW_ID_RD_WAIT =>
next_state <= CT_NEW_ID_AVAILABLE;
when CT_NEW_ID_AVAILABLE =>
debug_reg_next_1 <= DOA(0 to 7) & "1111" & Z32(12 to 31);
new_ID_next <= DOA(0 to 7); -- save new ID#
ADDRA <= '0' & DOA(0 to 7); -- point to new thread
ENA <= '1';
next_state <= CT_ENTRY_RD_WAIT;
when CT_ENTRY_RD_WAIT =>
next_state <= CT_ENTRY_AVAILABLE;
when CT_ENTRY_AVAILABLE =>
ADDRA <= '0' & new_ID;
ENA <= '1';
WEA <= '1'; -- enable write to bram
-- Determine if the thread to create is DETACHED / JOINABLE
if addr = C_CREATE_THREAD_D then -- set new thread status
debug_reg_next_0 <= "1100" & Z32(4 to 22) & next_ID;
-- Create detached
DIA <= DOA(0 to 7) & Z32(0 to 7) &
Z32(0 to 7) & "1011" & Z32(0 to 3);
else
debug_reg_next_0 <= "1101" & Z32(4 to 22) & next_ID;
-- Create joinable
DIA <= DOA(0 to 7) & Z32(0 to 7) &
current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 7)) & "0011" & Z32(0 to 3);
end if;
next_state <= CT_DONE;
when CT_DONE =>
-- Return new ID with no error,
bus_data_out_next <= Z32(0 to 22) & new_ID & '0';
-- Point to next available ID
next_ID_next <= next_ID + 1;
next_state <= END_TRANSACTION;
when CLEAR_THREAD_INIT =>
debug_reg_next_0 <= Z32(0 to 1) & '1' & Z32(3 to 31);
-- Clear the encoded thread ID if it is used and exited
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= CLEAR_ENTRY_RD_WAIT;
when CLEAR_ENTRY_RD_WAIT =>
next_state <= CLEAR_ENTRY_AVAIABLE ;
when CLEAR_ENTRY_AVAIABLE =>
if (DOA(26 to 27) = "10") then -- used and exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1'; -- clear old status but
DIA <= DOA(0 to 7) & Z32(0 to 23); -- preserve ID stack
next_state <= DEALLOCATE_ID;
else
-- Error occurred, return thread status w/ LSB=1
bus_data_out_next <= DOA(0 to 27) & CLEAR_ERROR_NOT_USED;
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_ID =>
if (next_ID /= Z32(0 to 8)) then
ADDRA <= next_ID - 1;
ENA <= '1';
next_ID_next <= next_ID - 1;
next_state <= DEALLOCATE_NEXT_ENTRY_RD_WAIT;
else
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_NEXT_ENTRY_RD_WAIT =>
next_state <= DEALLOCATE_NEXT_ENTRY_AVAIL;
when DEALLOCATE_NEXT_ENTRY_AVAIL =>
-- put ID back on stack, preserve other bits
ADDRA <= next_ID;
ENA <= '1';
WEA <= '1';
DIA <= Bus2IP_Addr(22 to 29) & DOA(8 to 31);
next_state <= END_TRANSACTION;
when JOIN_THREAD_INIT =>
debug_reg_next_0 <= Z32(0 to 2) & '1' & Z32(4 to 31);
-- Join on the encoded thread ID if its PID = current_thread
-- and its status = used,~joined,~detached
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= JOIN_RD_ENTRY_RD_WAIT;
when JOIN_RD_ENTRY_RD_WAIT =>
next_state <= JOIN_RD_ENTRY_AVAILABLE;
when JOIN_RD_ENTRY_AVAILABLE =>
debug_reg_next_1 <= DOA;
if ((DOA(16 to 23) & '0' = current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 8))) and -- PID = current thread
(DOA(24 to 25) = "00") and -- ~detached,~joined
(DOA(26 to 27) /= "00")) then -- not unused
if DOA(27) = '0' then
-- Thread has already exited, return a WARNING code
bus_data_out_next <= Z32(0 to 27) & THREAD_ALREADY_TERMINATED;
next_state <= END_TRANSACTION;
else
-- Thread has not exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1';
debug_reg_next_0 <= debug_reg_0(0 to 3) & "110011001100" & Z32(16 to 31);
-- Clear old status but
-- Set joined bit and preserve all other bits
DIA <= DOA(0 to 24) & '1' & DOA(26 to 31);
next_state <= END_TRANSACTION;
end if;
else
-- An error occured. Determine the error and return correct error code.
if( DOA(24) = '1' ) then
-- Trying to join on a detached thread
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_DETACHED;
elsif ( DOA(24 to 25) = "01" ) then
-- Trying to join on a thread that is already joined
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_JOINED;
elsif( DOA(26) = '0' ) then
-- Trying to join on a thread that is not used
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_NOT_USED;
elsif( DOA(16 to 23) & '0' /= current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 8))) then
-- Trying to join to a thread that is not the current thread's child
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_NOT_CHILD;
else
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_UNKNOWN;
end if;
next_state <= END_TRANSACTION;
end if;
when IS_DETACHED_THREAD_INIT =>
debug_reg_next_0 <= Z32(0 to 10) & '1' & Z32(12 to 31);
-- Returns a 1 if the encoded thread ID is detached, else returns 0
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= IS_DETACHED_ENTRY_RD_WAIT;
when IS_DETACHED_ENTRY_RD_WAIT =>
next_state <= IS_DETACHED_ENTRY_AVAILABLE;
when IS_DETACHED_ENTRY_AVAILABLE =>
if (DOA(24) = '1' and DOA(26) = '1') then
-- Thread is detached, return 1
bus_data_out_next <= Z32(0 to 29) & "10"; -- The 0 in the last bit indicates no error
else
-- Thread is not detached, or not used, return 0
bus_data_out_next <= Z32;
end if;
next_state <= END_TRANSACTION;
when IS_QUEUED_INIT =>
debug_reg_next_0 <= Z32(0 to 11) & '1' & Z32(13 to 31);
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29); -- thread ID
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= IS_QUEUED_DONE;
when IS_QUEUED_DONE =>
bus_data_out_next <= Z32(0 to 22) & sch2tm_data & '0';
next_state <= END_TRANSACTION;
when NEXT_THREAD_INIT =>
debug_reg_next_0 <= Z32(0 to 7) & '1' & Z32(9 to 31);
-- Return to the caller the value of the next thread to run
if sch2tm_next_id_valid = '1' then
debug_reg_next_0 <= "01" & Z32(2 to 7) & debug_reg_0(8) & Z32(9 to 31);
-- The next thread has been identified,
-- read from Scheduler and check thread status
-- as stored by SWTM for consistency
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
else
debug_reg_next_0 <= "10" & Z32(2 to 7) & debug_reg_0(8) & Z32(9 to 31);
next_state <= NEXT_THREAD_CHECK_IDLE;
end if;
----------------------------
-- START OF IDLE ADDITIONS
-- The scheduler can't put an idle_thread_id in the next_thread_reg because the wrong processor might dequeue it,
-- therefore these states have been added to check if the R2RQ is empty and if it is then start running the correct
-- idle thread for the requesting processor
----------------------------
when NEXT_THREAD_CHECK_IDLE =>
-- Check to see if the scheduler's queue is empty
debug_reg_next_0 <= debug_reg_0(0 to 8) & "1" & Z32(10 to 31);
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_IS_EMPTY;
tm2sch_data_next <= Z32(0 to 7);
next_state <= IS_QUEUE_EMPTY_WAIT_ACK;
return_state_next <= NEXT_THREAD_CHECK_QUEUE_EMPTY;
when NEXT_THREAD_CHECK_QUEUE_EMPTY =>
if (sch2tm_data(7) = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 9) & "1" & Z32(11 to 31);
-- Queue is empty
next_state <= NEXT_THREAD_IDLE_REQ;
else
debug_reg_next_0 <= debug_reg_0(0 to 9) & "0" & Z32(11 to 31);
-- Queue is not empty
next_state <= NEXT_THREAD_WAIT4_SCHEDULER;
end if;
when NEXT_THREAD_IDLE_REQ =>
debug_reg_next_0 <= debug_reg_0(0 to 10) & "1" & Z32(12 to 31);
-- request idle thread id here
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_IDLE_REQ;
-- Tell scheduler which CPU is requesting the operation
-- From MSB to LSB - 00000 & current_CPU
tm2sch_data_next <= Z32(2 to 7) & current_CPU;
next_state <= NEXT_THREAD_IDLE_WAIT_ACK;
return_state_next <= NEXT_THREAD_CHECK_IDLE_REQ;
when NEXT_THREAD_IDLE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the is queue empty request
if sch2tm_busy = '0' then
debug_reg_next_0 <= debug_reg_0(0 to 11) & "01" & Z32(14 to 31);
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 11) & "10" & Z32(14 to 31);
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_IDLE_REQUEST;
next_state <= RAISE_EXCEPTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 11) & "11" & Z32(14 to 31);
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= NEXT_THREAD_IDLE_WAIT_COMPLETE;
end if;
when NEXT_THREAD_IDLE_WAIT_COMPLETE =>
-- Wait for the scheduler to complete the is queue empty request
if sch2tm_busy = '1' then
debug_reg_next_0 <= debug_reg_0(0 to 13) & "01" & Z32(16 to 31);
-- Scheduler has not yet completed request
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 13) & "10" & Z32(16 to 31);
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_IDLE_REQUEST;
next_state <= RAISE_EXCEPTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 13) & "11" & Z32(16 to 31);
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when NEXT_THREAD_CHECK_IDLE_REQ =>
debug_reg_next_0 <= debug_reg_0(0 to 15) & "1" & Z32(17 to 23) & sch2tm_data;
if(sch2tm_data = x"FF") then
-- Return an error on the bus - this means that the idle_thread for this processor is not valid
Exception_Cause_next <= EXCEPTION_TO_IDLE_REQUEST;
next_state <= RAISE_EXCEPTION;
else
-- Idle thread is valid, update the current thread id register
current_thread_id_reg_next((9 * current_CPU_int) to ((9 * current_CPU_int) + 8)) <= sch2tm_data & '0';
-- Return Idle Thread ID on the Bus
bus_data_out_next <= Z32(0 to 22) & sch2tm_data & '0';
next_state <= END_TRANSACTION;
end if;
----------------------------
-- END OF IDLE ADDITIONS
----------------------------
when NEXT_THREAD_WAIT4_SCHEDULER =>
if (sch2tm_next_id_valid = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 1) & "001" & Z32(5 to 7) & debug_reg_0(8) & Z32(9 to 31);
-- Scheduler has made a scheduling decision
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 1) & "010" & Z32(5 to 7) & debug_reg_0(8) & Z32(9 to 31);
-- Timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_NEXT_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
else
debug_reg_next_0 <= debug_reg_0(0 to 1) & "100" & Z32(5 to 7) & debug_reg_0(8) & Z32(9 to 31);
-- Continue waiting for scheduler
next_state <= current_state;
end if;
when NEXT_THREAD_RD_WAIT =>
next_state <= NEXT_THREAD_AVAILABLE;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Request Dequeue operation from scheduler
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
when NEXT_THREAD_AVAILABLE =>
if (DOA(26 to 27) = "11") then
-- Thread status is used and not exited
debug_reg_next_0 <= debug_reg_0(0 to 4) & "111" & debug_reg_0(8) & Z32(9 to 31);
-- Dequeue the next_thread_id from the scheduler's queue
current_thread_id_reg_next((9 * current_CPU_int) to ((9 * current_CPU_int) + 8)) <= sch2tm_next_id & '0';
-- Tell scheduler which CPU to dequeue from
-- From MSB to LSB - 00000 & current_CPU
tm2sch_data_next <= Z32(2 to 7) & current_CPU;
--tm2sch_data_next <= current_CPU & Z32(2 to 7);
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_DEQUEUE;
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= NEXT_THREAD_CHECK_DEQUEUE;
else
debug_reg_next_0 <= debug_reg_0(0 to 4) & "010" & debug_reg_0(8) & Z32(9 to 31);
-- TM and SCHEDULER disagree if thread was used and not exited
-- Return thread ID, set error bit and raise exception
bus_data_out_next <= Z32(0 to 22) & sch2tm_next_id & '1';
Exception_Cause_next <= EXCEPTION_SCHD_INVALID_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
end if;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of Dequeue Request
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
when NEXT_THREAD_CHECK_DEQUEUE =>
-- Perform a check to make sure scheduler completed successfully
if sch2tm_data(7) = '1' then
debug_reg_next_0 <= debug_reg_0(0 to 15) & "01" & Z32(18 to 31);
-- Error during dequeue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 15) & "10" & Z32(18 to 31);
-- Dequeue completed correctly
debug_reg_next_0 <= debug_reg_0(0 to 17) & "1111" & Z32(22 to 31);
-- Return the value of the next thread id (which by now is in the current_thread_id_reg register)
--bus_data_out_next <= Z32(0 to 22) & sch2tm_next_id & '0';
bus_data_out_next <= Z32(0 to 22) & current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 7)) & '0';
next_state <= END_TRANSACTION;
end if;
when ADD_THREAD_INIT =>
debug_reg_next_0 <= Z32(0 to 4) & '1' & Z32(6 to 31);
-- If the thread is !used or exited return error
-- call scheduler to check queued status
-- If queued return error
-- call scheduler to enqueue thread ID
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- encoded thread ID
ENA <= '1';
next_state <= AT_ENTRY_RD_WAIT;
when AT_ENTRY_RD_WAIT =>
next_state <= AT_ENTRY_AVAILABLE;
when AT_ENTRY_AVAILABLE =>
-- Check to see if the thread is used and !exited
if (DOA(26 to 27) = "11") then
debug_reg_next_0 <= "01" & Z32(2 to 4) & debug_reg_0(5) & Z32(6 to 31);
-- Thread is used and not exited
-- call scheduler isQueued
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= AT_CHECK_ISQUEUE;
else
debug_reg_next_0 <= "10" & Z32(2 to 4) & debug_reg_0(5) & Z32(6 to 31);
-- Thread is unused or exited (or both)
-- Operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Request Enqueue operation from the scheduler
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
when AT_CHECK_ISQUEUE =>
-- Check to see if the thread is queued
if sch2tm_data(7) = '0' then
debug_reg_next_0 <= debug_reg_0(0 to 8) & "01" & Z32(11 to 31);
-- Thread is not queued, call scheduler's enqueue
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= AT_CHECK_ENQUEUE;
else
debug_reg_next_0 <= debug_reg_0(0 to 8) & "10" & Z32(11 to 31);
-- Thread is queued, return error
bus_data_out_next <= DOA(0 to 7) & sch2tm_data & DOA(16 to 27) & THREAD_ALREADY_QUEUED;
next_state <= END_TRANSACTION;
end if;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of Enqueue Request
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
when AT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
debug_reg_next_0 <= debug_reg_0(0 to 16) & "01" & Z32(19 to 31);
-- Error during enqueue
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 16) & "10" & Z32(19 to 31);
-- Enqueue completed correctly
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 31);
next_state <= END_TRANSACTION;
end if;
when ISQUEUED_WAIT_ACK =>
-- wait for the scheduler to acknowledge the isQueued request
if sch2tm_busy = '0' then
debug_reg_next_0 <= debug_reg_0(0 to 1) & "001" & debug_reg_0(5) & Z32(6 to 31);
-- Scheduler has not yet responded to request
next_state <= current_state;
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 1) & "010" & debug_reg_0(5) & Z32(6 to 31);
-- Timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 1) & "100" & debug_reg_0(5) & Z32(6 to 31);
-- Scheduler acknowledged request, lower request line
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ISQUEUED_WAIT_COMPLETE;
end if;
when ISQUEUED_WAIT_COMPLETE =>
-- Wait for the scheduler to complete the isQueued request
if sch2tm_busy = '1' then
debug_reg_next_0 <= debug_reg_0(0 to 5) & "001" & Z32(9 to 31);
-- Scheduler has not yet completed request
next_state <= current_state;
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 5) & "010" & Z32(9 to 31);
-- Timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 5) & "100" & Z32(9 to 31);
-- Scheduler finished request, and (should) have data on data_return line
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when ENQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the enqueue request
if sch2tm_busy = '0' then
debug_reg_next_0 <= debug_reg_0(0 to 8) & "01" & Z32(11 to 31);
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 8) & "10" & Z32(11 to 31);
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 8) & "11" & Z32(11 to 31);
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ENQUEUE_WAIT_COMPLETE;
end if;
when ENQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the enqueue request
if sch2tm_busy = '1' then
debug_reg_next_0 <= debug_reg_0(0 to 10) & "01" & Z32(13 to 31);
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 10) & "10" & Z32(13 to 31);
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 10) & "11" & Z32(13 to 31);
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when DEQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the dequeue request
if sch2tm_busy = '0' then
debug_reg_next_0 <= debug_reg_0(0 to 8) & "01" & Z32(11 to 31);
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 8) & "10" & Z32(11 to 31);
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 8) & "11" & Z32(11 to 31);
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= DEQUEUE_WAIT_COMPLETE;
end if;
when DEQUEUE_WAIT_COMPLETE =>
-- Wait for the scheduler to complete the dequeue request
if sch2tm_busy = '1' then
debug_reg_next_0 <= debug_reg_0(0 to 10) & "01" & Z32(13 to 31);
-- Scheduler has not yet completed request
elsif (timeout_expired = '1') then
debug_reg_next_0 <= debug_reg_0(0 to 10) & "10" & Z32(13 to 31);
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
debug_reg_next_0 <= debug_reg_0(0 to 10) & "11" & Z32(13 to 31);
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when IS_QUEUE_EMPTY_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the is queue empty request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= IS_QUEUE_EMPTY_WAIT_COMPLETE;
end if;
when IS_QUEUE_EMPTY_WAIT_COMPLETE =>
-- Wait for the scheduler to complete the is queue empty request
if sch2tm_busy = '1' then
-- Scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when YIELD_THREAD_INIT =>
debug_reg_next_1 <= '1' & Z32(1 to 31);
-- Retrieve the status of the current cpu thread
ADDRA <= '0' & current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 7));
ENA <= '1';
next_state <= YIELD_CURRENT_THREAD_RD_WAIT;
when YIELD_CURRENT_THREAD_RD_WAIT =>
next_state <= YIELD_CURRENT_THREAD_AVAILABLE;
when YIELD_CURRENT_THREAD_AVAILABLE =>
-- Check to see if thread's status is used,~exited,~queued
if (DOA(26 to 27) = "11") then
debug_reg_next_1 <= debug_reg_1(0) & '0' & Z32(2 to 31);
-- Check to see if the scheduler's queue is empty
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_IS_EMPTY;
tm2sch_data_next <= Z32(0 to 7);
next_state <= IS_QUEUE_EMPTY_WAIT_ACK;
return_state_next <= YIELD_CHECK_QUEUE_EMPTY;
else
debug_reg_next_1 <= debug_reg_1(0) & '1' & Z32(2 to 31);
-- Operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when YIELD_CHECK_QUEUE_EMPTY =>
if (sch2tm_data(7) = '1') then
debug_reg_next_1 <= debug_reg_1(0 to 1) & '0' & Z32(3 to 31);
-- Queue is empty, return the current thread id
bus_data_out_next <= Z32(0 to 22) & current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 8));
next_state <= END_TRANSACTION;
else
debug_reg_next_1 <= debug_reg_1(0 to 1) & '1' & Z32(3 to 31);
next_state <= YIELD_ENQUEUE;
end if;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Request Enqueue operation from the scheduler
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
when YIELD_ENQUEUE =>
debug_reg_next_1 <= debug_reg_1(0 to 7) & "0" & Z32(9 to 31);
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_data_next <= current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 7));
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_ENQUEUE;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of Enqueue request
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
when YIELD_CHECK_ENQUEUE =>
if (sch2tm_data(7) = '0') then
debug_reg_next_1 <= debug_reg_1(0 to 12) & "0" & Z32(14 to 31);
-- ENQ was successful, now DEQ to get next scheduling decision
-- update the currently running thread to the one that is scheduled to run next (AKA to be DEQ'd)
current_thread_id_reg_next((9 * current_CPU_int) to ((9 * current_CPU_int) + 8)) <= sch2tm_next_id & '0';
--next_state <= YIELD_dummy_is_queued;
next_state <= YIELD_DEQUEUE;
else
debug_reg_next_1 <= debug_reg_1(0 to 12) & "1" & Z32(14 to 31);
-- ENQ failed, return error to caller
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
end if;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Request Dequeue operation from scheduler
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
when YIELD_DEQUEUE =>
debug_reg_next_1 <= debug_reg_1(0 to 7) & "1" & debug_reg_1(9 to 31);
current_thread_id_reg_next((9 * current_CPU_int) to ((9 * current_CPU_int) + 8)) <= sch2tm_next_id & '0';
-- Tell scheduler which CPU to dequeue from
tm2sch_data_next <= Z32(2 to 7) & current_CPU;
--tm2sch_data_next <= current_CPU & Z32(2 to 7);
tm2sch_request_next <= '1'; -- request the DEQ operation to remove the thread to run from Q
tm2sch_opcode_next <= OPCODE_DEQUEUE;
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_DEQUEUE;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of Dequeue request
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
when YIELD_CHECK_DEQUEUE =>
if (sch2tm_data(7) = '1') then
debug_reg_next_1 <= debug_reg_1(0 to 8) & "0" & debug_reg_1(10 to 31);
-- Error during DEQ...
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
debug_reg_next_1 <= debug_reg_1(0 to 8) & "1" & debug_reg_1(10 to 31);
-- DEQ completed successfully, end operation
-- Return the value of the next thread id (which by now is in the current_thread_id_reg register)
--bus_data_out_next <= Z32(0 to 22) & sch2tm_next_id & '0';
bus_data_out_next <= Z32(0 to 22) & current_thread_id_reg((9 * current_CPU_int) to ((9 * current_CPU_int) + 7)) & '0';
next_state <= END_TRANSACTION;
end if;
when EXIT_THREAD_INIT =>
debug_reg_next_0 <= Z32(0 to 6) & '1' & Z32(8 to 31);
bus_data_out_next <= Z32; -- change if failure occurs
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
next_state <= EXIT_THREAD_RD_WAIT;
when EXIT_THREAD_RD_WAIT =>
next_state <= EXIT_THREAD_AVAIABLE;
when EXIT_THREAD_AVAIABLE =>
-- Full entry for the current_thread is required in later states
current_status_next <= DOA(0 to 31);
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
WEA <= '1';
if (DOA(24) = '1') then
-- Thread is detached
-- Make the thread status used and exited.
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
elsif (DOA(25) = '1') then
-- Thread is joined
-- Make the thread status used and exited, and wake the parent
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= EXIT_READ_PARENT;
else
-- Thread is not detached and still joinable
-- Set the thread status to used and exited
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
end if;
when EXIT_READ_PARENT =>
-- The thread that is exiting was joined, wake the parent up
ADDRA <= '0' & current_status(16 to 23);
ENA <= '1';
next_state <= EXIT_READ_PARENT_WAIT;
when EXIT_READ_PARENT_WAIT =>
next_state <= EXIT_READ_PARENT_AVAILABLE;
when EXIT_READ_PARENT_AVAILABLE =>
-- Make sure the parent thread is used and not exited
if (DOA(26 to 27) = "11") then
-- Parent thread is used and not exited.
-- Add the parent thread tothe scheduler's queue
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= current_status(16 to 23);
return_state_next <= EXIT_CHECK_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
else
-- Parent thread is either unused or exited, neither of which it should be
-- Operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when EXIT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- Error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- Enqueue completed correctly
bus_data_out_next <= Z32(0 to 31);
next_state <= END_TRANSACTION;
end if;
when RAISE_EXCEPTION =>
-- NOTE !!! You must assign Exception_Cause
-- where-ever you assign next_state <= RAISE_EXCEPTION;
Exception_Address_next <= Bus2IP_Addr(0 to 31); -- save address
access_error <= '1'; -- assert interrupt
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION =>
IP2Bus_Data <= bus_data_out;
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION_WAIT =>
if( Bus2IP_RdCE(0) ='0' and Bus2IP_WrCE(0)='0' ) then
next_state <= IDLE_STATE;
else
next_state <= current_state;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_ILLEGAL_STATE;
next_state <= RAISE_EXCEPTION;
end case; -- case current_state
end process SWTM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause | 24352eb27cc59c3ad33ec3097f8a125a | 0.508275 | 3.747256 | false | false | false | false |
michaelmiehling/A25_VME | Source/wb_pkg.vhd | 1 | 63,058 | ---------------------------------------------------------------
-- Title : system unit package
-- Project : Embedded System Module
---------------------------------------------------------------
-- File : wb_pkg.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 17/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Package for wishbone bus functions.
-- Consists of data mux for x chip selects.
-- Wishbone bus input and output type definition.
-- This package is used for wb_bus (busmaker).
--
-- Switch-fab naming convention is:
-- All signal names are based on the source of the signal
-- (wbo_slave = output singals of slave)
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: wb_pkg.vhd,v $
-- Revision 1.2 2013/09/12 08:55:07 mmiehling
-- added bit 8 for enhanced address modifier support of DMA
--
-- Revision 1.1 2012/03/29 10:21:19 MMiehling
-- Initial Revision
--
-- Revision 1.11 2009/07/29 14:05:13 FLenhardt
-- Fixed bug in SWITCH_FAB (WB slave strobe had been activated without addressing)
--
-- Revision 1.10 2007/08/24 11:15:23 FLenhardt
-- Re-added procedure SWITCH_FAB for backward compatibility
--
-- Revision 1.9 2007/08/13 16:28:35 MMiehling
-- moved switch_fab to entity switch_fab_1
--
-- Revision 1.8 2007/08/13 13:58:58 FWombacher
-- fixed typos
--
-- Revision 1.7 2007/08/13 10:14:26 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.6 2006/05/18 16:14:32 twickleder
-- added data_mux for 23 slaves
--
-- Revision 1.5 2006/05/09 11:57:29 twickleder
-- added data_mux for 21 and 22 slaves
--
-- Revision 1.4 2006/02/24 16:09:39 TWickleder
-- Added DATA_MUX procedure with 20 data inputs
--
-- Revision 1.3 2006/02/17 13:54:20 flenhardt
-- Added DATA_MUX procedure with 19 data inputs
--
-- Revision 1.2 2005/12/13 13:48:56 flenhardt
-- Added DATA_MUX procedure with 18 data inputs
--
-- Revision 1.1 2004/08/13 15:16:09 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:52 mmiehling
-- Initial Revision
--
-- Revision 1.6 2004/07/27 17:06:24 mmiehling
-- multifunction added
--
-- Revision 1.4 2004/05/13 14:21:25 MMiehling
-- multifunction device
--
-- Revision 1.3 2004/04/29 15:07:22 MMiehling
-- removed switch_fab from pkg, now new entity
--
-- Revision 1.2 2004/04/27 09:37:42 MMiehling
-- now correct signal names and wb-types
--
-- Revision 1.3 2004/04/14 16:54:50 MMiehling
-- now correct switch_fab io's
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE wb_pkg IS
TYPE wbo_type IS record
stb : std_logic;
sel : std_logic_vector(3 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
tga : std_logic_vector(8 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
bte : std_logic_vector(1 DOWNTO 0);
END record;
TYPE wbi_type IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
END record;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_22 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) ;
END wb_pkg;
PACKAGE BODY wb_pkg IS
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "01" => data_out <= data_in_0;
WHEN "10" => data_out <= data_in_1;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "001" => data_out <= data_in_0;
WHEN "010" => data_out <= data_in_1;
WHEN "100" => data_out <= data_in_2;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0001" => data_out <= data_in_0;
WHEN "0010" => data_out <= data_in_1;
WHEN "0100" => data_out <= data_in_2;
WHEN "1000" => data_out <= data_in_3;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00001" => data_out <= data_in_0;
WHEN "00010" => data_out <= data_in_1;
WHEN "00100" => data_out <= data_in_2;
WHEN "01000" => data_out <= data_in_3;
WHEN "10000" => data_out <= data_in_4;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000001" => data_out <= data_in_0;
WHEN "000010" => data_out <= data_in_1;
WHEN "000100" => data_out <= data_in_2;
WHEN "001000" => data_out <= data_in_3;
WHEN "010000" => data_out <= data_in_4;
WHEN "100000" => data_out <= data_in_5;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000001" => data_out <= data_in_0;
WHEN "0000010" => data_out <= data_in_1;
WHEN "0000100" => data_out <= data_in_2;
WHEN "0001000" => data_out <= data_in_3;
WHEN "0010000" => data_out <= data_in_4;
WHEN "0100000" => data_out <= data_in_5;
WHEN "1000000" => data_out <= data_in_6;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000001" => data_out <= data_in_0;
WHEN "00000010" => data_out <= data_in_1;
WHEN "00000100" => data_out <= data_in_2;
WHEN "00001000" => data_out <= data_in_3;
WHEN "00010000" => data_out <= data_in_4;
WHEN "00100000" => data_out <= data_in_5;
WHEN "01000000" => data_out <= data_in_6;
WHEN "10000000" => data_out <= data_in_7;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000001" => data_out <= data_in_0;
WHEN "000000010" => data_out <= data_in_1;
WHEN "000000100" => data_out <= data_in_2;
WHEN "000001000" => data_out <= data_in_3;
WHEN "000010000" => data_out <= data_in_4;
WHEN "000100000" => data_out <= data_in_5;
WHEN "001000000" => data_out <= data_in_6;
WHEN "010000000" => data_out <= data_in_7;
WHEN "100000000" => data_out <= data_in_8;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000001" => data_out <= data_in_0;
WHEN "0000000010" => data_out <= data_in_1;
WHEN "0000000100" => data_out <= data_in_2;
WHEN "0000001000" => data_out <= data_in_3;
WHEN "0000010000" => data_out <= data_in_4;
WHEN "0000100000" => data_out <= data_in_5;
WHEN "0001000000" => data_out <= data_in_6;
WHEN "0010000000" => data_out <= data_in_7;
WHEN "0100000000" => data_out <= data_in_8;
WHEN "1000000000" => data_out <= data_in_9;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000001" => data_out <= data_in_0;
WHEN "00000000010" => data_out <= data_in_1;
WHEN "00000000100" => data_out <= data_in_2;
WHEN "00000001000" => data_out <= data_in_3;
WHEN "00000010000" => data_out <= data_in_4;
WHEN "00000100000" => data_out <= data_in_5;
WHEN "00001000000" => data_out <= data_in_6;
WHEN "00010000000" => data_out <= data_in_7;
WHEN "00100000000" => data_out <= data_in_8;
WHEN "01000000000" => data_out <= data_in_9;
WHEN "10000000000" => data_out <= data_in_10;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000001" => data_out <= data_in_0;
WHEN "000000000010" => data_out <= data_in_1;
WHEN "000000000100" => data_out <= data_in_2;
WHEN "000000001000" => data_out <= data_in_3;
WHEN "000000010000" => data_out <= data_in_4;
WHEN "000000100000" => data_out <= data_in_5;
WHEN "000001000000" => data_out <= data_in_6;
WHEN "000010000000" => data_out <= data_in_7;
WHEN "000100000000" => data_out <= data_in_8;
WHEN "001000000000" => data_out <= data_in_9;
WHEN "010000000000" => data_out <= data_in_10;
WHEN "100000000000" => data_out <= data_in_11;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000001" => data_out <= data_in_0;
WHEN "0000000000010" => data_out <= data_in_1;
WHEN "0000000000100" => data_out <= data_in_2;
WHEN "0000000001000" => data_out <= data_in_3;
WHEN "0000000010000" => data_out <= data_in_4;
WHEN "0000000100000" => data_out <= data_in_5;
WHEN "0000001000000" => data_out <= data_in_6;
WHEN "0000010000000" => data_out <= data_in_7;
WHEN "0000100000000" => data_out <= data_in_8;
WHEN "0001000000000" => data_out <= data_in_9;
WHEN "0010000000000" => data_out <= data_in_10;
WHEN "0100000000000" => data_out <= data_in_11;
WHEN "1000000000000" => data_out <= data_in_12;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000001" => data_out <= data_in_0;
WHEN "00000000000010" => data_out <= data_in_1;
WHEN "00000000000100" => data_out <= data_in_2;
WHEN "00000000001000" => data_out <= data_in_3;
WHEN "00000000010000" => data_out <= data_in_4;
WHEN "00000000100000" => data_out <= data_in_5;
WHEN "00000001000000" => data_out <= data_in_6;
WHEN "00000010000000" => data_out <= data_in_7;
WHEN "00000100000000" => data_out <= data_in_8;
WHEN "00001000000000" => data_out <= data_in_9;
WHEN "00010000000000" => data_out <= data_in_10;
WHEN "00100000000000" => data_out <= data_in_11;
WHEN "01000000000000" => data_out <= data_in_12;
WHEN "10000000000000" => data_out <= data_in_13;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000001" => data_out <= data_in_0;
WHEN "000000000000010" => data_out <= data_in_1;
WHEN "000000000000100" => data_out <= data_in_2;
WHEN "000000000001000" => data_out <= data_in_3;
WHEN "000000000010000" => data_out <= data_in_4;
WHEN "000000000100000" => data_out <= data_in_5;
WHEN "000000001000000" => data_out <= data_in_6;
WHEN "000000010000000" => data_out <= data_in_7;
WHEN "000000100000000" => data_out <= data_in_8;
WHEN "000001000000000" => data_out <= data_in_9;
WHEN "000010000000000" => data_out <= data_in_10;
WHEN "000100000000000" => data_out <= data_in_11;
WHEN "001000000000000" => data_out <= data_in_12;
WHEN "010000000000000" => data_out <= data_in_13;
WHEN "100000000000000" => data_out <= data_in_14;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000001" => data_out <= data_in_0;
WHEN "0000000000000010" => data_out <= data_in_1;
WHEN "0000000000000100" => data_out <= data_in_2;
WHEN "0000000000001000" => data_out <= data_in_3;
WHEN "0000000000010000" => data_out <= data_in_4;
WHEN "0000000000100000" => data_out <= data_in_5;
WHEN "0000000001000000" => data_out <= data_in_6;
WHEN "0000000010000000" => data_out <= data_in_7;
WHEN "0000000100000000" => data_out <= data_in_8;
WHEN "0000001000000000" => data_out <= data_in_9;
WHEN "0000010000000000" => data_out <= data_in_10;
WHEN "0000100000000000" => data_out <= data_in_11;
WHEN "0001000000000000" => data_out <= data_in_12;
WHEN "0010000000000000" => data_out <= data_in_13;
WHEN "0100000000000000" => data_out <= data_in_14;
WHEN "1000000000000000" => data_out <= data_in_15;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000001" => data_out <= data_in_0;
WHEN "00000000000000010" => data_out <= data_in_1;
WHEN "00000000000000100" => data_out <= data_in_2;
WHEN "00000000000001000" => data_out <= data_in_3;
WHEN "00000000000010000" => data_out <= data_in_4;
WHEN "00000000000100000" => data_out <= data_in_5;
WHEN "00000000001000000" => data_out <= data_in_6;
WHEN "00000000010000000" => data_out <= data_in_7;
WHEN "00000000100000000" => data_out <= data_in_8;
WHEN "00000001000000000" => data_out <= data_in_9;
WHEN "00000010000000000" => data_out <= data_in_10;
WHEN "00000100000000000" => data_out <= data_in_11;
WHEN "00001000000000000" => data_out <= data_in_12;
WHEN "00010000000000000" => data_out <= data_in_13;
WHEN "00100000000000000" => data_out <= data_in_14;
WHEN "01000000000000000" => data_out <= data_in_15;
WHEN "10000000000000000" => data_out <= data_in_16;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000100" => data_out <= data_in_2;
WHEN "000000000000001000" => data_out <= data_in_3;
WHEN "000000000000010000" => data_out <= data_in_4;
WHEN "000000000000100000" => data_out <= data_in_5;
WHEN "000000000001000000" => data_out <= data_in_6;
WHEN "000000000010000000" => data_out <= data_in_7;
WHEN "000000000100000000" => data_out <= data_in_8;
WHEN "000000001000000000" => data_out <= data_in_9;
WHEN "000000010000000000" => data_out <= data_in_10;
WHEN "000000100000000000" => data_out <= data_in_11;
WHEN "000001000000000000" => data_out <= data_in_12;
WHEN "000010000000000000" => data_out <= data_in_13;
WHEN "000100000000000000" => data_out <= data_in_14;
WHEN "001000000000000000" => data_out <= data_in_15;
WHEN "010000000000000000" => data_out <= data_in_16;
WHEN "100000000000000000" => data_out <= data_in_17;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000100000" => data_out <= data_in_5;
WHEN "0000000000001000000" => data_out <= data_in_6;
WHEN "0000000000010000000" => data_out <= data_in_7;
WHEN "0000000000100000000" => data_out <= data_in_8;
WHEN "0000000001000000000" => data_out <= data_in_9;
WHEN "0000000010000000000" => data_out <= data_in_10;
WHEN "0000000100000000000" => data_out <= data_in_11;
WHEN "0000001000000000000" => data_out <= data_in_12;
WHEN "0000010000000000000" => data_out <= data_in_13;
WHEN "0000100000000000000" => data_out <= data_in_14;
WHEN "0001000000000000000" => data_out <= data_in_15;
WHEN "0010000000000000000" => data_out <= data_in_16;
WHEN "0100000000000000000" => data_out <= data_in_17;
WHEN "1000000000000000000" => data_out <= data_in_18;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000100000" => data_out <= data_in_5;
WHEN "00000000000001000000" => data_out <= data_in_6;
WHEN "00000000000010000000" => data_out <= data_in_7;
WHEN "00000000000100000000" => data_out <= data_in_8;
WHEN "00000000001000000000" => data_out <= data_in_9;
WHEN "00000000010000000000" => data_out <= data_in_10;
WHEN "00000000100000000000" => data_out <= data_in_11;
WHEN "00000001000000000000" => data_out <= data_in_12;
WHEN "00000010000000000000" => data_out <= data_in_13;
WHEN "00000100000000000000" => data_out <= data_in_14;
WHEN "00001000000000000000" => data_out <= data_in_15;
WHEN "00010000000000000000" => data_out <= data_in_16;
WHEN "00100000000000000000" => data_out <= data_in_17;
WHEN "01000000000000000000" => data_out <= data_in_18;
WHEN "10000000000000000000" => data_out <= data_in_19;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000000100" => data_out <= data_in_2;
WHEN "000000000000000001000" => data_out <= data_in_3;
WHEN "000000000000000010000" => data_out <= data_in_4;
WHEN "000000000000000100000" => data_out <= data_in_5;
WHEN "000000000000001000000" => data_out <= data_in_6;
WHEN "000000000000010000000" => data_out <= data_in_7;
WHEN "000000000000100000000" => data_out <= data_in_8;
WHEN "000000000001000000000" => data_out <= data_in_9;
WHEN "000000000010000000000" => data_out <= data_in_10;
WHEN "000000000100000000000" => data_out <= data_in_11;
WHEN "000000001000000000000" => data_out <= data_in_12;
WHEN "000000010000000000000" => data_out <= data_in_13;
WHEN "000000100000000000000" => data_out <= data_in_14;
WHEN "000001000000000000000" => data_out <= data_in_15;
WHEN "000010000000000000000" => data_out <= data_in_16;
WHEN "000100000000000000000" => data_out <= data_in_17;
WHEN "001000000000000000000" => data_out <= data_in_18;
WHEN "010000000000000000000" => data_out <= data_in_19;
WHEN "100000000000000000000" => data_out <= data_in_20;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000000100000" => data_out <= data_in_5;
WHEN "0000000000000001000000" => data_out <= data_in_6;
WHEN "0000000000000010000000" => data_out <= data_in_7;
WHEN "0000000000000100000000" => data_out <= data_in_8;
WHEN "0000000000001000000000" => data_out <= data_in_9;
WHEN "0000000000010000000000" => data_out <= data_in_10;
WHEN "0000000000100000000000" => data_out <= data_in_11;
WHEN "0000000001000000000000" => data_out <= data_in_12;
WHEN "0000000010000000000000" => data_out <= data_in_13;
WHEN "0000000100000000000000" => data_out <= data_in_14;
WHEN "0000001000000000000000" => data_out <= data_in_15;
WHEN "0000010000000000000000" => data_out <= data_in_16;
WHEN "0000100000000000000000" => data_out <= data_in_17;
WHEN "0001000000000000000000" => data_out <= data_in_18;
WHEN "0010000000000000000000" => data_out <= data_in_19;
WHEN "0100000000000000000000" => data_out <= data_in_20;
WHEN "1000000000000000000000" => data_out <= data_in_21;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_1 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_2 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_3 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_4 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_5 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_6 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_7 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_8 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_9 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_10 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_11 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_12 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_13 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_14 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_15 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_16 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_17 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_18 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_19 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_20 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_21 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_in_22 : IN std_logic_vector(31 DOWNTO 0);
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000000100000" => data_out <= data_in_5;
WHEN "00000000000000001000000" => data_out <= data_in_6;
WHEN "00000000000000010000000" => data_out <= data_in_7;
WHEN "00000000000000100000000" => data_out <= data_in_8;
WHEN "00000000000001000000000" => data_out <= data_in_9;
WHEN "00000000000010000000000" => data_out <= data_in_10;
WHEN "00000000000100000000000" => data_out <= data_in_11;
WHEN "00000000001000000000000" => data_out <= data_in_12;
WHEN "00000000010000000000000" => data_out <= data_in_13;
WHEN "00000000100000000000000" => data_out <= data_in_14;
WHEN "00000001000000000000000" => data_out <= data_in_15;
WHEN "00000010000000000000000" => data_out <= data_in_16;
WHEN "00000100000000000000000" => data_out <= data_in_17;
WHEN "00001000000000000000000" => data_out <= data_in_18;
WHEN "00010000000000000000000" => data_out <= data_in_19;
WHEN "00100000000000000000000" => data_out <= data_in_20;
WHEN "01000000000000000000000" => data_out <= data_in_21;
WHEN "10000000000000000000000" => data_out <= data_in_22;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) IS
BEGIN
IF rst = '1' THEN
wbi_slave.stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave.stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave.stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave.stb <= '0';
ELSE
wbi_slave.stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave.stb <= '0';
END IF;
END IF;
wbi_slave_cyc <= cyc_0;
ack_0 <= wbo_slave.ack;
err_0 <= wbo_slave.err;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.bte <= wbo_0.bte;
wbi_slave.tga <= wbo_0.tga;
END switch_fab;
END;
| gpl-3.0 | 875dc552d905ba8246b1873b1b00f358 | 0.61962 | 2.969392 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/tx_module.vhd | 1 | 21,593 | --------------------------------------------------------------------------------
-- Title : Tx Module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_module.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 13.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- combines the modules tx_put_data, tx_compl_timeout and tx_ctrl
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- * tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tx_module is
generic(
DEVICE_FAMILY : string := "unused";
TX_HEADER_FIFO_DEPTH : natural := 32; -- valid values are: 2^(TX_HEADER_LPM_WIDTHU-1) < TX_HEADER_FIFO_DEPTH <= 2^(TX_HEADER_LPM_WIDTHU)
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(TX_DATA_LPM_WIDTHU-1) < TX_DATA_FIFO_DEPTH <= 2^(TX_DATA_LPM_WIDTHU)
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
rst : in std_logic;
wb_clk : in std_logic;
wb_rst : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
-- IP Core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
-- Rx Module
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- Wishbone Master
tx_fifo_c_data_clr : in std_logic;
tx_fifo_c_head_clr : in std_logic;
tx_fifo_c_head_enable : in std_logic;
tx_fifo_c_data_enable : in std_logic;
tx_fifo_c_head_in : in std_logic_vector(31 downto 0);
tx_fifo_c_data_in : in std_logic_vector(31 downto 0);
tx_fifo_c_head_full : out std_logic;
tx_fifo_c_data_full : out std_logic;
tx_fifo_c_data_usedw : out std_logic_vector(9 downto 0);
-- Wishbone Slave
tx_fifo_wr_head_clr : in std_logic;
tx_fifo_wr_head_enable : in std_logic;
tx_fifo_wr_head_in : in std_logic_vector(31 downto 0);
tx_fifo_w_data_clr : in std_logic;
tx_fifo_w_data_enable : in std_logic;
tx_fifo_w_data_in : in std_logic_vector(31 downto 0);
tx_fifo_wr_head_full : out std_logic;
tx_fifo_w_data_full : out std_logic;
tx_fifo_w_data_usedw : out std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : out std_logic_vector(4 downto 0);
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0);
-- error
tx_compl_abort : out std_logic;
tx_timeout : out std_logic
);
end entity tx_module;
-- ****************************************************************************
architecture tx_module_arch of tx_module is
-- internal signals -----------------------------------------------------------
signal aligned_int : std_logic;
signal data_len_int : std_logic_vector(9 downto 0);
signal wr_rd_int : std_logic; -- 0: write, 1: read
signal posted_int : std_logic; -- 0: non-posted, 1: posted
signal byte_count_int : std_logic_vector(11 downto 0);
signal orig_addr_int : std_logic_vector(31 downto 0);
signal tx_tag_nbr_int : std_logic_vector(7 downto 0);
signal get_header_int : std_logic;
signal make_header_int : std_logic;
signal data_enable_int : std_logic;
signal start_int : std_logic;
signal start_tag_nbr_int : std_logic_vector(4 downto 0);
signal c_wrrd_int : std_logic;
signal completer_id_int : std_logic_vector(15 downto 0);
signal own_id_int : std_logic_vector(15 downto 0);
signal get_next_header_int : std_logic;
signal abort_compl_int : std_logic;
signal send_len_int : std_logic_vector(9 downto 0);
signal send_addr_int : std_logic_vector(31 downto 0);
signal payload_loop_int : std_logic;
signal first_last_full_int : std_logic_vector(1 downto 0);
signal io_write_int : std_logic;
-- FIFO:
signal tx_fifo_c_head_empty_int : std_logic;
signal tx_fifo_c_head_enable_int : std_logic;
signal tx_fifo_c_head_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_c_data_empty_int : std_logic;
signal tx_fifo_c_data_enable_int : std_logic;
signal tx_fifo_c_data_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_wr_head_empty_int : std_logic;
signal tx_fifo_wr_head_enable_int : std_logic;
signal tx_fifo_wr_head_out_int : std_logic_vector(63 downto 0);
signal tx_fifo_w_data_enable_int : std_logic;
signal tx_fifo_w_data_empty_int : std_logic;
signal tx_fifo_w_data_out_int : std_logic_vector(63 downto 0);
signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_c_out : std_logic_vector (9 downto 0);
signal tx_wrusedw_w_out : std_logic_vector (9 downto 0);
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component tx_ctrl
port(
clk : in std_logic;
rst : in std_logic;
-- IP core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
pme_to_cr : out std_logic;
-- FIFO
tx_c_head_empty : in std_logic;
tx_wr_head_empty : in std_logic;
tx_c_data_empty : in std_logic;
tx_wr_data_empty : in std_logic;
tx_c_head_enable : out std_logic;
tx_wr_head_enable : out std_logic;
tx_c_data_enable : out std_logic;
tx_wr_data_enable : out std_logic;
-- tx_put_data
aligned : in std_logic;
data_len : in std_logic_vector(9 downto 0);
wr_rd : in std_logic; -- 0: write, 1: read
posted : in std_logic; -- 0: non-posted, 1: posted
byte_count : in std_logic_vector(11 downto 0);
io_write : in std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : in std_logic_vector(31 downto 0);
tx_tag_nbr : out std_logic_vector(7 downto 0);
get_header : out std_logic;
get_next_header : out std_logic;
make_header : out std_logic;
data_enable : out std_logic;
c_wrrd : out std_logic;
completer_id : out std_logic_vector(15 downto 0);
own_id : out std_logic_vector(15 downto 0);
abort_compl : out std_logic;
send_len : out std_logic_vector(9 downto 0);
send_addr : out std_logic_vector(31 downto 0);
payload_loop : out std_logic;
first_last_full : out std_logic_vector(1 downto 0);
-- tx_compl_timeout
start : out std_logic;
start_tag_nbr : out std_logic_vector(4 downto 0);
-- error
compl_abort : out std_logic;
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0)
);
end component;
component tx_put_data
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
tx_st_data0 : out std_logic_vector(63 downto 0);
-- FIFO
tx_c_head_out : in std_logic_vector(63 downto 0);
tx_c_data_out : in std_logic_vector(63 downto 0);
tx_wr_head_out : in std_logic_vector(63 downto 0);
tx_wr_data_out : in std_logic_vector(63 downto 0);
-- tx_ctrl
data_enable : in std_logic;
tag_nbr : in std_logic_vector(7 downto 0);
req_id : in std_logic_vector(15 downto 0);
completer_id : in std_logic_vector(15 downto 0);
c_wrrd : in std_logic; -- 0: completion, 1: write/read
get_header : in std_logic;
get_next_header : in std_logic;
make_header : in std_logic;
abort_compl : in std_logic;
send_len : in std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : in std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : in std_logic; -- =0: no loop, =1: loop -> keep most header info
first_last_full : in std_logic_vector(1 downto 0);
data_length : out std_logic_vector(9 downto 0);
aligned : out std_logic;
wr_rd : out std_logic; -- 0: write, 1: read
posted : out std_logic; -- 0: non-posted, 1: posted
byte_count : out std_logic_vector(11 downto 0);
io_write : out std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : out std_logic_vector(31 downto 0)
);
end component;
component tx_compl_timeout
generic(
CLOCK_TIME : time := 8 ns; -- clock cycle time
TIMEOUT_TIME : integer := 25
);
port(
clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
-- tx_ctrl
tag_nbr_in : in std_logic_vector(4 downto 0);
start : in std_logic;
-- RxModule
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- error
timeout : out std_logic
);
end component;
component generic_dcfifo_mixedw
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end component;
-------------------------------------------------------------------------------
begin
-- instanciate components -----------------------------------------------------
tx_ctrl_comp : tx_ctrl
port map(
clk => clk,
rst => rst,
-- IP core
tx_st_ready0 => tx_st_ready0,
tx_fifo_full0 => tx_fifo_full0,
tx_fifo_empty0 => tx_fifo_empty0,
tx_fifo_rdptr0 => tx_fifo_rdptr0,
tx_fifo_wrptr0 => tx_fifo_wrptr0,
pme_to_sr => pme_to_sr,
tx_st_err0 => tx_st_err0,
tx_st_valid0 => tx_st_valid0,
tx_st_sop0 => tx_st_sop0,
tx_st_eop0 => tx_st_eop0,
pme_to_cr => pme_to_cr,
-- FIFO
tx_c_head_empty => tx_fifo_c_head_empty_int,
tx_wr_head_empty => tx_fifo_wr_head_empty_int,
tx_c_data_empty => tx_fifo_c_data_empty_int,
tx_wr_data_empty => tx_fifo_w_data_empty_int,
tx_c_head_enable => tx_fifo_c_head_enable_int,
tx_wr_head_enable => tx_fifo_wr_head_enable_int,
tx_c_data_enable => tx_fifo_c_data_enable_int,
tx_wr_data_enable => tx_fifo_w_data_enable_int,
-- tx_put_data
aligned => aligned_int,
data_len => data_len_int,
wr_rd => wr_rd_int, -- 0: write, 1: read
posted => posted_int, -- 0: non-posted, 1: posted
byte_count => byte_count_int,
io_write => io_write_int,
orig_addr => orig_addr_int,
tx_tag_nbr => tx_tag_nbr_int,
get_header => get_header_int,
get_next_header => get_next_header_int,
make_header => make_header_int,
data_enable => data_enable_int,
c_wrrd => c_wrrd_int,
completer_id => completer_id_int,
own_id => own_id_int,
abort_compl => abort_compl_int,
send_len => send_len_int,
send_addr => send_addr_int,
payload_loop => payload_loop_int,
first_last_full => first_last_full_int,
-- tx_compl_timeout
start => start_int,
start_tag_nbr => start_tag_nbr_int,
-- error
compl_abort => tx_compl_abort,
-- init
bus_dev_func => bus_dev_func,
max_payload => max_payload
);
tx_put_data_comp : tx_put_data
port map(
clk => clk,
rst => rst,
-- IP Core
tx_st_data0 => tx_st_data0,
-- FIFO
tx_c_head_out => tx_fifo_c_head_out_int,
tx_c_data_out => tx_fifo_c_data_out_int,
tx_wr_head_out => tx_fifo_wr_head_out_int,
tx_wr_data_out => tx_fifo_w_data_out_int,
-- tx_ctrl
data_enable => data_enable_int,
tag_nbr => tx_tag_nbr_int,
req_id => own_id_int,
completer_id => completer_id_int,
c_wrrd => c_wrrd_int,
get_header => get_header_int,
get_next_header => get_next_header_int,
make_header => make_header_int,
abort_compl => abort_compl_int,
send_len => send_len_int,
send_addr => send_addr_int,
payload_loop => payload_loop_int,
first_last_full => first_last_full_int,
data_length => data_len_int,
aligned => aligned_int,
wr_rd => wr_rd_int,
posted => posted_int,
byte_count => byte_count_int,
io_write => io_write_int,
orig_addr => orig_addr_int
);
tx_compl_timeout_comp : tx_compl_timeout
generic map(
CLOCK_TIME => 8 ns, -- clock cycle time
TIMEOUT_TIME => 25
)
port map(
clk => clk,
clk_500 => clk_500,
rst => rst,
-- tx_ctrl
tag_nbr_in => start_tag_nbr_int,
start => start_int,
-- RxModule
rx_tag_nbr => rx_tag_nbr,
rx_tag_rcvd => rx_tag_rcvd,
-- error
timeout => tx_timeout
);
------------------------------------------------
tx_c_header_fifo : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_c_head_clr,
data => tx_fifo_c_head_in,
rdclk => clk,
rdreq => tx_fifo_c_head_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_c_head_enable,
q => tx_fifo_c_head_out_int,
rdempty => tx_fifo_c_head_empty_int,
wrfull => tx_fifo_c_head_full,
wrusedw => open);
tx_wr_header_fifo : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_HEADER_LPM_WIDTHU,
g_q_width => 64,
g_q_widthu => TX_HEADER_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_wr_head_clr,
data => tx_fifo_wr_head_in,
rdclk => clk,
rdreq => tx_fifo_wr_head_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_wr_head_enable,
q => tx_fifo_wr_head_out_int,
rdempty => tx_fifo_wr_head_empty_int,
wrfull => tx_fifo_wr_head_full,
wrusedw => tx_fifo_wr_head_usedw);
------------------------------------------------
tx_c_data_fifo : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_c_data_clr,
data => tx_fifo_c_data_in,
rdclk => clk,
rdreq => tx_fifo_c_data_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_c_data_enable,
q => tx_fifo_c_data_out_int,
rdempty => tx_fifo_c_data_empty_int,
wrfull => tx_fifo_c_data_full,
wrusedw => tx_wrusedw_c);
tx_w_data_fifo : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
g_data_width => 32,
g_data_widthu => TX_DATA_LPM_WIDTHU,
g_q_width => 64,
g_q_widthu => TX_DATA_LPM_WIDTHU-1,
g_showahead => "OFF")
port map (
aclr => tx_fifo_w_data_clr,
data => tx_fifo_w_data_in,
rdclk => clk,
rdreq => tx_fifo_w_data_enable_int,
wrclk => wb_clk,
wrreq => tx_fifo_w_data_enable,
q => tx_fifo_w_data_out_int,
rdempty => tx_fifo_w_data_empty_int,
wrfull => tx_fifo_w_data_full,
wrusedw => tx_wrusedw_w);
-------------------------------------------------------------------------------
tx_wrusedw_c_out <= conv_std_logic_vector(conv_integer(tx_wrusedw_c),10);
tx_wrusedw_w_out <= conv_std_logic_vector(conv_integer(tx_wrusedw_w),10);
tx_fifo_c_data_usedw <= tx_wrusedw_c_out;
tx_fifo_w_data_usedw <= tx_wrusedw_w_out;
-------------------------------------------------------------------------------
end architecture tx_module_arch;
| gpl-3.0 | 5c345671308bc0f7df676fdc889ffcea | 0.48224 | 3.522512 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/peripherals/wishbone_mem.vhd | 1 | 3,958 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:35:25 10/04/2013
-- Design Name:
-- Module Name: wishbone_mem - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_mem is
generic( mem_size : positive := 3;
wb_size : natural := 16 ; -- Data port size for wishbone
wb_addr_size : natural := 16 -- Data port size for wishbone
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(wb_addr_size-1 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic
);
end wishbone_mem;
architecture Behavioral of wishbone_mem is
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal write_mem : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
write_mem <= wbs_strobe and wbs_write and wbs_cycle ;
ram0 : dpram_NxN
generic map(SIZE => mem_size, NBIT => wb_size, ADDR_WIDTH=> wb_addr_size)
port map(
clk => gls_clk,
we => write_mem ,
di => wbs_writedata,
a => wbs_address ,
dpra => X"0000",
spo => wbs_readdata,
dpo => open
);
end Behavioral;
| lgpl-3.0 | 9ced33b8d9d4ea8c8cf1ca0113b48b6d | 0.590955 | 3.591652 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_hthreads_timer_v1_00_a/hdl/vhdl/user_logic.vhd | 9 | 9,363 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Jun 29 12:13:20 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_counter_reg : std_logic_vector(0 to 2*C_SLV_DWIDTH-1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s) and counter
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_counter_reg <= (others => '0');
else
slv_counter_reg <= slv_counter_reg + 1;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_counter_reg ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_counter_reg(0 to C_SLV_DWIDTH-1); -- Upper bits
when "01" => slv_ip2bus_data <= slv_counter_reg(C_SLV_DWIDTH to 2*C_SLV_DWIDTH-1); -- Lower bits
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause | ff7d27f439dca7d43657f73e85d51d99 | 0.468226 | 4.558423 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/owner_fsm.vhd | 11 | 5,733 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity owner_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end owner_fsm;
architecture behavioral of owner_fsm is
-- A type for the states in the owner fsm
type owner_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the owner fsm
signal owner_cs : owner_state;
signal owner_ns : owner_state;
-- Alias owner output
alias odata : std_logic_vector(0 to C_TWIDTH-1) is data(C_DWIDTH-C_TWIDTH to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
owner_update : process(clk,rst,sysrst,owner_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
owner_cs <= IDLE;
else
owner_cs <= owner_ns;
end if;
end if;
end process owner_update;
owner_controller : process(owner_cs,start,mutex,miowner) is
begin
owner_ns <= owner_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case owner_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
owner_ns <= READ;
end if;
when READ =>
owner_ns <= DONE;
when DONE =>
finish <= '1';
odata <= miowner;
owner_ns <= IDLE;
end case;
end process owner_controller;
end behavioral;
| bsd-3-clause | 99cb685e44eb98eb025842a000ab6b1f | 0.532531 | 4.181619 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr.vhd | 2 | 12,278 |
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr.vhd
--
-- Description: This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n is false,
-- Dout increments by one each time Cnt_en is true at
-- the positive edge of Clk.
--
-- The implementation has a one-LUT delay (via the XORCY)
-- in direct pass-through mode and the same delay plus
-- carry-chain propogation in count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 05/30/2003 -- First version
--
-- <initials> <date>
-- ^^^^^^
-- Description of changes. If multiple lines are needed to fully describe
-- the changes made to the design, these lines should align with each other.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic
);
end direct_path_cntr;
library unisim;
use unisim.all;
architecture imp of direct_path_cntr is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
component FDE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component FDE;
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
begin
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
signal gen_cry: std_logic;
begin
gen_cry <= '1' when j = C_WIDTH-1 else '0'; -- cntrl increments
-- at LSB
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
LSB_LUT_GEN: if j = C_WIDTH-1 generate
begin
lut_out(j) <= not q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
--
NON_LSB_LUT_GEN: if j /= C_WIDTH-1 generate
begin
lut_out(j) <= q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
------------------------------------------------------------------------
-- Propagate the carry out.
------------------------------------------------------------------------
LSB_MUXCY_GEN: if j = C_WIDTH-1 generate
signal sel_cntr_and_Load_n : std_logic;
begin
I_MULT_AND : MULT_AND
port map (
LO => sel_cntr_and_Load_n,
I1 => sel_cntr,
I0 => Load_n
);
MUXCY_i1: MUXCY
port map (
DI => sel_cntr_and_Load_n,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
NON_LSB_MUXCY_GEN: if j /= C_WIDTH-1 generate
begin
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDRE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
| bsd-3-clause | 383105a226bf246774e855ee22d63e36 | 0.421648 | 4.872222 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_wait_1.vhd | 2 | 21,679 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_wait_1.c
-- reg1 = i
-- reg2 = * mutex
-- reg3 = * cond
-- reg4 = * start_num
-- reg5 = * havelock_num
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of cond
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg4_next <= intrfc2thrd_value;
-- Read the address of havelock_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 12;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg5_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 16;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- hthread_create( &data->thread, NULL, data->function, (void *) data );
when STATE_6 =>
reg6_next <= intrfc2thrd_value;
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
-- while( *(data->start_num) != THREAD_NUM ) hthread_yield();
when STATE_11 =>
-- Read the value of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
case intrfc2thrd_value is
when x"00000001" => next_state <= STATE_14;
when others => next_state <= STATE_13;
end case;
when STATE_13 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->mutex );
when STATE_14 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_16;
next_state <= WAIT_STATE;
-- retVal = *(data->waken_num);
when STATE_16 =>
-- Read the value of waken_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
-- hthread_cond_signal( data->cond );
when STATE_17 =>
retVal_next <= intrfc2thrd_value;
-- push data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_cond_signal
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->mutex );
when STATE_19 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_21 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000014";
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_23;
when STATE_23 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_24 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_25;
next_state <= WAIT_STATE;
when STATE_25 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 4a80d18a201a66b4e6916c89adaefdb3 | 0.549702 | 3.689415 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/create_4.vhd | 2 | 17,232 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_4.c
-- reg6 = * function
-- reg7 = thread
-- reg4 = childVal
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, &data->childVal );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push &data->childVal
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
-- if (data->childVal == data->thread ) retVal = SUCCESS;
-- else retVal = FAILURE;
when STATE_12 =>
-- Load the value of data->childThread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
if ( intrfc2thrd_value = reg7 ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 922313f02a9f011634a7fc601d54580d | 0.54422 | 3.808177 | false | false | false | false |
xdsopl/vhdl | toggle.vhd | 1 | 833 | -- toggle - toggle output on rising edge of clock
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity toggle is
port (
reset : in std_logic := '0';
clock : in std_logic;
output : out std_logic
);
end toggle;
architecture rtl of toggle is
signal state : std_logic := '0';
begin
state <= '0' when reset = '1' else not state when rising_edge(clock) else state;
output <= state;
end rtl;
| cc0-1.0 | 4e0714332c22995e01131541b39d9161 | 0.733493 | 3.685841 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/soft_reset.vhd | 2 | 13,931 | -------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
| bsd-3-clause | b3883f5950b9a9c5a7ec8901de00e985 | 0.401192 | 4.87951 | false | false | false | false |
jevinskie/aes-over-pcie | source/reduce_pack.vhd | 1 | 13,366 | -- --------------------------------------------------------------------
--
-- Copyright 2002 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE [Draft] Standard 1076.3
-- reduce_pkg
-- This source file may not be copied, sold, or included
-- with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this
-- [draft] standard and may be distributed in compiled form in any manner so
-- long as the compiled form does not allow direct decompilation of the
-- original source file. This source file may be copied for individaul use
-- between licensed users.
--
-- The IEEE disclaims any responsibility or liability for damages resulting
-- from misinterpretation or misue of said information by the user.
--
-- [This source file represents a portion of the IEEE Draft Standard and is
-- unapproved and subject to change.]
--
-- < statement about permission to modify >
--
-- Title : REDUCE_PKG < IEEE std # 1076.3 >
--
-- Library : This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL/Synthesis, PAR 1076.3
--
-- Purpose : Reduction operations. This allows a vector to
-- be collapsed into a signle bit. Similar to the built
-- in functions in Verilog.
--
-- Limitation:
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 1.3
-- Date : 8 July 2002
-- Added "to_x01" on all inputs.
-- Made "and_reduce" return a "1" in the NULL case.
-- -------------------------------------------------------------------------
-- Version: 1.2
-- Date : 21 June 2002
-- Fixed some basic logic errors.
-- -------------------------------------------------------------------------
-- Version: 1.1
-- Date : 13 May 2002
-- Modified to deal with null arrays, added IEEE header.
-- -------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
-- Package definition
package reduce_Pack is
FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_ULOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
-- bit_vector versions
FUNCTION and_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : BIT_VECTOR) RETURN BIT;
-- Result subtype: BIT.
-- Result: Result of xnor'ing all of the bits of the vector.
end reduce_Pack;
-- Package body.
package body reduce_Pack is
-- done in a recursively called function.
function and_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '1'; -- Change for version 1.3
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) and BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper and Lower;
end if;
end if;
return Result;
end;
function nand_reduce (arg : std_logic_vector )
return std_logic is
begin
return not and_reduce (arg);
end;
function or_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) or BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper or Lower;
end if;
end if;
return Result;
end;
function nor_reduce (arg : std_logic_vector )
return std_logic is
begin
return not or_reduce ( arg );
end;
function xor_reduce (arg : std_logic_vector )
return std_logic is
variable Upper, Lower : std_logic;
variable Half : integer;
variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
variable Result : std_logic;
begin
if (arg'LENGTH < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := BUS_int ( BUS_int'right ) xor BUS_int ( BUS_int'left );
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := Upper xor Lower;
end if;
end if;
return Result;
end;
function xnor_reduce (arg : std_logic_vector )
return std_logic is
begin
return not xor_reduce ( arg );
end;
function and_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : SIGNED )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : UNSIGNED )
return std_logic is
begin
return and_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : SIGNED )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function nand_reduce (arg : UNSIGNED )
return std_logic is
begin
return nand_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : SIGNED )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function or_reduce (arg : UNSIGNED )
return std_logic is
begin
return or_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : SIGNED )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function nor_reduce (arg : UNSIGNED )
return std_logic is
begin
return nor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : SIGNED )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xor_reduce (arg : UNSIGNED )
return std_logic is
begin
return xor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : std_ulogic_vector )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : SIGNED )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function xnor_reduce (arg : UNSIGNED )
return std_logic is
begin
return xnor_reduce (std_logic_vector ( arg ));
end;
function and_reduce (arg : bit_vector )
return bit is
begin
return to_bit (and_reduce (to_stdlogicvector ( arg )));
end;
function nand_reduce (arg : bit_vector )
return bit is
begin
return to_bit (nand_reduce (to_stdlogicvector ( arg )));
end;
function or_reduce (arg : bit_vector )
return bit is
begin
return to_bit (or_reduce (to_stdlogicvector ( arg )));
end;
function nor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (nor_reduce (to_stdlogicvector ( arg )));
end;
function xor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (xor_reduce (to_stdlogicvector ( arg )));
end;
function xnor_reduce (arg : bit_vector )
return bit is
begin
return to_bit (xnor_reduce (to_stdlogicvector ( arg )));
end;
end reduce_Pack;
| bsd-3-clause | 71e8ef28e3191f2db5593737030d36d5 | 0.624645 | 3.748177 | false | false | false | false |
jevinskie/aes-over-pcie | source/tb_add_round_key.vhd | 1 | 1,873 | -- File name: tb_add_round_key.vhd
-- Created: 3/31/2009
-- Author: Zachary Curosh
-- Lab Section: 337-02
-- Version: 1.0 Initial Test Bench
use work.aes.all;
library ieee;
--library gold_lib; --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all; --UNCOMMENT if you're using a GOLD model
entity tb_add_round_key is
end tb_add_round_key;
architecture TEST of tb_add_round_key is
function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
return STD_LOGIC_VECTOR is
variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
variable tmp : INTEGER;
begin
tmp := X;
for i in 0 to NumBits-1 loop
if (tmp mod 2)=1 then
res(i) := '1';
else
res(i) := '0';
end if;
tmp := tmp/2;
end loop;
return res;
end;
component add_round_key
PORT(
data_in : in byte;
key_in : in byte;
data_out : out byte
);
end component;
-- Insert signals Declarations here
signal data_in : byte;
signal key_in : byte;
signal data_out : byte;
-- signal <name> : <type>;
begin
DUT: add_round_key port map(
data_in => data_in,
key_in => key_in,
data_out => data_out
);
-- GOLD: <GOLD_NAME> port map(<put mappings here>);
process
begin
-- Insert TEST BENCH Code Here
data_in <= x"a3";
key_in <= x"54";
wait for 10 ns;
data_in <= "11111111";
key_in <= "11111111";
wait for 10 ns;
data_in <= "00000000";
key_in <= "11111111";
wait for 10 ns;
data_in <= "11111111";
key_in <= "00000000";
wait for 10 ns;
data_in <= "10101010";
key_in <= "01010101";
wait for 10 ns;
data_in <= x"23";
key_in <= x"b7";
wait;
end process;
end TEST; | bsd-3-clause | 0053410a3de4675aabe14567812ee4eb | 0.548318 | 3.338681 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/conv_funs_pkg.vhd | 2 | 15,319 | -------------------------------------------------------------------------------
-- $Id: conv_funs_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
----------------------------------------------------------------------------
-- conv_funs_pkg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
----------------------------------------------------------------------------
-- Filename: conv_funs_pkg.vhd
--
-- Description:
-- Various string conversion functions.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- conv_funs_pkg.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: unknown
-- Revision: $Revision: 1.1.4.1 $
-- Date: $1/1/2002$
--
-- History:
-- XXX 1/1/2002 Initial Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package conv_funs_pkg is
-- hex string to std_logic_vector
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- octal string to std_logic_vector
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- binary string to std_logic_vector
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- string to std_logic_vector
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
end conv_funs_pkg;
--
--------------------------------------------------------------------------------
--
package body conv_funs_pkg is
type basetype is (binary, octal, decimal, hex);
function max(x, y : INTEGER) return INTEGER is
begin
if x > y then return x; else return y; end if;
end max;
function MIN(x, y : INTEGER) return INTEGER is
begin
if x < y then return x; else return y; end if;
end MIN;
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*4, result will be truncated on the left
-- if instring is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*4, return_length);
variable char_ptr : INTEGER range -3 to max(instring'LENGTH*4, return_length) := max(instring'LENGTH*4, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*4, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-3 to char_ptr) := "0000";
when '1' => return_vector(char_ptr-3 to char_ptr) := "0001";
when '2' => return_vector(char_ptr-3 to char_ptr) := "0010";
when '3' => return_vector(char_ptr-3 to char_ptr) := "0011";
when '4' => return_vector(char_ptr-3 to char_ptr) := "0100";
when '5' => return_vector(char_ptr-3 to char_ptr) := "0101";
when '6' => return_vector(char_ptr-3 to char_ptr) := "0110";
when '7' => return_vector(char_ptr-3 to char_ptr) := "0111";
when '8' => return_vector(char_ptr-3 to char_ptr) := "1000";
when '9' => return_vector(char_ptr-3 to char_ptr) := "1001";
when 'a'|'A' => return_vector(char_ptr-3 to char_ptr) := "1010";
when 'b'|'B' => return_vector(char_ptr-3 to char_ptr) := "1011";
when 'c'|'C' => return_vector(char_ptr-3 to char_ptr) := "1100";
when 'd'|'D' => return_vector(char_ptr-3 to char_ptr) := "1101";
when 'e'|'E' => return_vector(char_ptr-3 to char_ptr) := "1110";
when 'f'|'F' => return_vector(char_ptr-3 to char_ptr) := "1111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-3 to char_ptr) := "UUUU";
-- when 'X' => return_vector(char_ptr-3 to char_ptr) := "XXXX";
-- when 'Z' => return_vector(char_ptr-3 to char_ptr) := "ZZZZ";
-- when 'W' => return_vector(char_ptr-3 to char_ptr) := "WWWW";
-- when 'H' => return_vector(char_ptr-3 to char_ptr) := "HHHH";
-- when 'L' => return_vector(char_ptr-3 to char_ptr) := "LLLL";
-- when '-' => return_vector(char_ptr-3 to char_ptr) := "----";
-- but synplicity does
when '_' => char_ptr := char_ptr + 4;
when others =>
assert FALSE
report lf &
"hex_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '----'"
severity WARNING;
return_vector(char_ptr-3 to char_ptr) := "----";
end case;
char_ptr := char_ptr - 4;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end hex_string_to_slv;
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*3, result will be truncated on the left
-- if instring is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*3, return_length);
variable char_ptr : INTEGER range -2 to max(instring'LENGTH*3, return_length) := max(instring'LENGTH*3, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*3, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-2 to char_ptr) := "000";
when '1' => return_vector(char_ptr-2 to char_ptr) := "001";
when '2' => return_vector(char_ptr-2 to char_ptr) := "010";
when '3' => return_vector(char_ptr-2 to char_ptr) := "011";
when '4' => return_vector(char_ptr-2 to char_ptr) := "100";
when '5' => return_vector(char_ptr-2 to char_ptr) := "101";
when '6' => return_vector(char_ptr-2 to char_ptr) := "110";
when '7' => return_vector(char_ptr-2 to char_ptr) := "111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-2 to char_ptr) := "UUU";
-- when 'X' => return_vector(char_ptr-2 to char_ptr) := "XXX";
-- when 'Z' => return_vector(char_ptr-2 to char_ptr) := "ZZZ";
-- when 'W' => return_vector(char_ptr-2 to char_ptr) := "WWW";
-- when 'H' => return_vector(char_ptr-2 to char_ptr) := "HHH";
-- when 'L' => return_vector(char_ptr-2 to char_ptr) := "LLL";
-- when '-' => return_vector(char_ptr-2 to char_ptr) := "---";
-- but synplicity does
when '_' => char_ptr := char_ptr + 3;
when others =>
assert FALSE
report lf &
"oct_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '---'"
severity WARNING;
return_vector(char_ptr-2 to char_ptr) := "---";
end case;
char_ptr := char_ptr - 3;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end oct_string_to_slv;
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length, result will be truncated on the left
-- if instring is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH, return_length);
variable char_ptr : INTEGER range 0 to max(instring'LENGTH, return_length)+1 := max(instring'LENGTH, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr) := '0';
when '1' => return_vector(char_ptr) := '1';
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr) := 'U';
-- when 'X' => return_vector(char_ptr) := 'X';
-- when 'Z' => return_vector(char_ptr) := 'Z';
-- when 'W' => return_vector(char_ptr) := 'W';
-- when 'H' => return_vector(char_ptr) := 'H';
-- when 'L' => return_vector(char_ptr) := 'L';
-- when '-' => return_vector(char_ptr) := '-';
-- but synplicity does
when '_' => char_ptr := char_ptr + 1;
when others =>
assert FALSE
report lf &
"bin_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '-'"
severity WARNING;
return_vector(char_ptr) := '-';
end case;
char_ptr := char_ptr - 1;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end bin_string_to_slv;
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
variable instring_length : POSITIVE := instring'LENGTH;
variable temp_string : STRING(1 to instring'LENGTH-2);
begin -- function string_to_std_logic_vector
if instring(1) = '0' and (instring(2) = 'x' or instring(2) = 'X') then
temp_string := instring(3 to instring_length);
return hex_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'o' or instring(2) = 'O') then
temp_string := instring(3 to instring_length);
return oct_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'b' or instring(2) = 'B') then
temp_string := instring(3 to instring_length);
return bin_string_to_slv(temp_string, return_length);
else
return bin_string_to_slv(instring, return_length);
end if;
end function string_to_std_logic_vector;
end conv_funs_pkg;
| bsd-3-clause | c14e0aa125047d9f893e6a2cc90da4f7 | 0.50186 | 4.080714 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/misc/zcpsmIO2bus16.vhd | 1 | 2,797 | ----------------------------
-- 2011/04/26:
-- debug_read_strobe¿ØÖÆÐźÅÔÚ zcpsm_read_strobe = '1' ʱ²úÉú¡£
-------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity zcpsmIO2bus16 is
port(
reset : in std_logic;
debug_port_id : out std_logic_vector(15 downto 0);
debug_write_strobe : out std_logic;
debug_out_port : out std_logic_vector(15 downto 0);
debug_read_strobe : out std_logic;
debug_in_port : in std_logic_vector(15 downto 0);
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end entity;
architecture behave of zcpsmIO2bus16 is
constant PORT_zcpsmIO2bus16_ADDR_L : std_logic_vector(3 downto 0) := X"0";
constant PORT_zcpsmIO2bus16_ADDR_H : std_logic_vector(3 downto 0) := X"1";
constant PORT_zcpsmIO2bus16_DATA_L : std_logic_vector(3 downto 0) := X"2";
constant PORT_zcpsmIO2bus16_DATA_H : std_logic_vector(3 downto 0) := X"3";
begin
AddrReg : process(zcpsm_clk, reset)
begin
if reset = '1' then
debug_port_id <= (others => '0');
elsif rising_edge(zcpsm_clk) then
if zcpsm_ce = '1' and zcpsm_write_strobe = '1' then
if zcpsm_port_id(3 downto 0) = PORT_zcpsmIO2bus16_ADDR_L then
debug_port_id(7 downto 0) <= zcpsm_out_port;
elsif zcpsm_port_id(3 downto 0) = PORT_zcpsmIO2bus16_ADDR_H then
debug_port_id(15 downto 8) <= zcpsm_out_port;
end if;
end if;
end if;
end process;
WriteIO : process(zcpsm_clk, reset)
begin
if reset = '1' then
debug_write_strobe <= '0';
debug_out_port <= (others => '0');
elsif rising_edge(zcpsm_clk) then
if zcpsm_ce = '1' and zcpsm_write_strobe = '1' and zcpsm_port_id(3 downto 0) = PORT_zcpsmIO2bus16_DATA_H then
debug_write_strobe <= '1';
else
debug_write_strobe <= '0';
end if;
if zcpsm_ce = '1' and zcpsm_write_strobe = '1' then
if zcpsm_port_id(3 downto 0) = PORT_zcpsmIO2bus16_DATA_L then
debug_out_port(7 downto 0) <= zcpsm_out_port;
elsif zcpsm_port_id(3 downto 0) = PORT_zcpsmIO2bus16_DATA_H then
debug_out_port(15 downto 8) <= zcpsm_out_port;
end if;
end if;
end if;
end process;
debug_read_strobe <= '1' when zcpsm_ce = '1' and zcpsm_read_strobe = '1' else '0';
zcpsm_in_port <= debug_in_port(7 downto 0) when zcpsm_ce = '1' and zcpsm_port_id(3 downto 0) = PORT_zcpsmIO2bus16_DATA_L else
debug_in_port(15 downto 8) when zcpsm_ce = '1' and zcpsm_port_id(3 downto 0) = PORT_zcpsmIO2bus16_DATA_H else
(others => 'Z');
end behave;
| gpl-2.0 | 32dc6a48d736c0b1dac6336dbecd1eb0 | 0.623168 | 2.643667 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl_fifo2.vhd | 2 | 14,431 | -------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
| bsd-3-clause | 53b67903e19cd08691b9314932c5c116 | 0.461992 | 4.338845 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_switch_fab_2.vhd | 1 | 10,288 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : z126_01_switch_fab_2.vhd
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
-- This module is derived from switch_fab_2.vhd of the 16z100-.
-- It contaions an additional arbitration of control
-- signals for the z126_01_wb2pasmi.vhd module in the 16z126-01
-- design.
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: z126_01_switch_fab_2.vhd,v $
-- Revision 1.1 2014/03/03 17:49:53 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.z126_01_wb_pkg.ALL;
USE work.z126_01_pkg.ALL;
ENTITY z126_01_switch_fab_2 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
ctrlmo_0 : IN ctrl_wb2pasmi_out_type;
ctrlmi_0 : OUT ctrl_wb2pasmi_in_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
ctrlmo_1 : IN ctrl_wb2pasmi_out_type;
ctrlmi_1 : OUT ctrl_wb2pasmi_in_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic;
ctrlso_0 : IN ctrl_wb2pasmi_in_type;
ctrlsi_0 : OUT ctrl_wb2pasmi_out_type
);
END z126_01_switch_fab_2;
ARCHITECTURE z126_01_switch_fab_2_arch OF z126_01_switch_fab_2 IS
SUBTYPE sw_states IS std_logic_vector(1 DOWNTO 0);
CONSTANT sw_0 : sw_states := "01";
CONSTANT sw_1 : sw_states := "10";
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL wbi_slave_stb : std_logic;
BEGIN
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.bte, wbo_1.bte)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.bte <= wbo_0.bte;
WHEN sw_1 => wbi_slave.bte <= wbo_1.bte;
WHEN OTHERS => wbi_slave.bte <= wbo_0.bte;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
-- mux for wb2pasmi control signals
PROCESS( sw_state, ctrlmo_0, ctrlmo_1)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
ctrlsi_0.read_sid <= ctrlmo_0.read_sid;
ctrlsi_0.sector_protect <= ctrlmo_0.sector_protect;
ctrlsi_0.write <= ctrlmo_0.write;
ctrlsi_0.read_status <= ctrlmo_0.read_status;
ctrlsi_0.sector_erase <= ctrlmo_0.sector_erase;
ctrlsi_0.bulk_erase <= ctrlmo_0.bulk_erase;
WHEN sw_1 =>
ctrlsi_0.read_sid <= ctrlmo_1.read_sid;
ctrlsi_0.sector_protect <= ctrlmo_1.sector_protect;
ctrlsi_0.write <= ctrlmo_1.write;
ctrlsi_0.read_status <= ctrlmo_1.read_status;
ctrlsi_0.sector_erase <= ctrlmo_1.sector_erase;
ctrlsi_0.bulk_erase <= ctrlmo_1.bulk_erase;
WHEN OTHERS =>
ctrlsi_0.read_sid <= ctrlmo_0.read_sid;
ctrlsi_0.sector_protect <= ctrlmo_0.sector_protect;
ctrlsi_0.write <= ctrlmo_0.write;
ctrlsi_0.read_status <= ctrlmo_0.read_status;
ctrlsi_0.sector_erase <= ctrlmo_0.sector_erase;
ctrlsi_0.bulk_erase <= ctrlmo_0.bulk_erase;
END CASE;
END PROCESS;
ctrlmi_0.illegal_write <= ctrlso_0.illegal_write WHEN sw_state = sw_0 ELSE '0';
ctrlmi_0.illegal_erase <= ctrlso_0.illegal_erase WHEN sw_state = sw_0 ELSE '0';
ctrlmi_0.busy <= ctrlso_0.busy WHEN sw_state = sw_0 ELSE '0';
ctrlmi_1.illegal_write <= ctrlso_0.illegal_write WHEN sw_state = sw_1 ELSE '0';
ctrlmi_1.illegal_erase <= ctrlso_0.illegal_erase WHEN sw_state = sw_1 ELSE '0';
ctrlmi_1.busy <= ctrlso_0.busy WHEN sw_state = sw_1 ELSE '0';
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
END z126_01_switch_fab_2_arch;
| gpl-3.0 | 79903f58c1485196ecaa8c3bee6e4304 | 0.472784 | 3.59972 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu.vhd | 2 | 18,239 | -------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v3_00_a;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v3_00_a.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
| bsd-3-clause | 57d3b6d22ad4d7492e941558075c6077 | 0.470092 | 4.478026 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/condattr_init_2.vhd | 2 | 16,727 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_init_2.c
-- arg = * data
-- reg1 = * cond
-- reg2 = * cond_attr
-- The return value should be the condattr->num set by either the
-- software main thread, or the bfl in case of simulation.
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_condattr_t * condattr = (hthread_condattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the value of cond
thrd2intrfc_address <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg1_next <= intrfc2thrd_value;
-- Read the value of cond_attr
thrd2intrfc_address <= arg + 4;
thrd2intrfc_opcode <= OPCODE_LOAD;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_condattr_init( data->attr );
when STATE_3 =>
reg2_next <= intrfc2thrd_value;
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_condattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CONDATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- hthread_cond_init( data->cond, data->attr );
when STATE_5 =>
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- Push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Call hthread_condattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- data->attr->num = 4;
when STATE_8 =>
-- Store '4' for the value of attr->num
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_value <= x"00000004";
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
--retVal = data->cond->num
when STATE_9 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg1;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 4061bbe5e18789cb0ce15b88c59216ce | 0.546601 | 3.790392 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_destroy_5.vhd | 2 | 16,451 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_destroy_5.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mtuex= (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_mutex_init( mutex, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( mutex )
when STATE_4 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( mutex )
when STATE_6 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- retVal = hthread_mutex_destroy( mutex );
when STATE_8 =>
-- Push the argument to hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- Call hthread_mutex_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
when STATE_10 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | a8aa8f83638a6ecb2da9a0f7492919cd | 0.546471 | 3.78532 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd | 2 | 12,535 | -------------------------------------------------------------------------------
-- $Id: pselect.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
| bsd-3-clause | 72de08a1e6765d17bf215d22e6dbc326 | 0.399122 | 5.327242 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/dma/dma2rxtask.vhd | 1 | 2,351 | ---------------------------------------------------------------------------------------------------
--
-- Title : dma2rxtask
-- Design : eth_new
-- Author : lihf
-- Company : wireless
--
---------------------------------------------------------------------------------------------------
--
-- File : dma2rxtask.vhd
-- Generated : Fri Sep 8 11:59:12 2006
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {dma2rxtask} architecture {arch_dma2rxtask}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity dma2rxtask is
port(
reset : in std_logic;
zcpsm_clk : in std_logic;
busy : in std_logic;
lastframe : in std_logic;
rxtask_wr_block : out std_logic
);
end dma2rxtask;
--}} End of automatically maintained section
architecture arch_dma2rxtask of dma2rxtask is
signal lastframe_flag : std_logic;
signal task_wr_block_reg: std_logic;
signal busy_flag : std_logic;
begin
rxtask_wr_block <= task_wr_block_reg;
process(reset, zcpsm_clk)
begin
if reset = '1' then
busy_flag <= '0';
elsif rising_edge(zcpsm_clk) then
if busy = '1' then
busy_flag <= '1';
else
busy_flag <= '0';
end if;
end if;
end process;
process(reset, zcpsm_clk)
begin
if reset = '1' then
lastframe_flag <= '0';
elsif rising_edge(zcpsm_clk) then
if lastframe = '1' then
lastframe_flag <= '1';
elsif lastframe_flag = '1' and busy = '0' then
lastframe_flag <= '0';
end if;
end if;
end process;
process(reset, zcpsm_clk)
begin
if reset = '1' then
task_wr_block_reg <= '0';
elsif rising_edge(zcpsm_clk) then
if lastframe_flag = '1' and busy = '0' then
-- if busy = '0' then
task_wr_block_reg <= '1';
-- end if;
elsif task_wr_block_reg = '1' then
task_wr_block_reg <= '0';
end if;
end if;
end process;
-- enter your statements here --
end arch_dma2rxtask;
| gpl-2.0 | eb517c3f5f1fcd80b6cb2e48f761d6b6 | 0.483624 | 3.368195 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_arb_pkg.vhd | 3 | 18,956 | -------------------------------------------------------------------------------
-- $Id: opb_arb_pkg.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_arb_pkg.vhd - Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_arb_pkg.vhd
-- Version: v1.02e
-- Description: This file contains the constants used in the design of the
-- OPB bus arbiter.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This is a global file used throughout the hierarchy of the
-- OPB bus arbiter design
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 10/12/01
-- ^^^^^^
-- Added Addr_bits function and constant IPIF_ABUS_WIDTH.
-- ~~~~~~
-- ALS 10/16/01
-- ^^^^^^
-- Modified Addr_Bits function to pass in the size of the address bus.
-- ~~~~~~
-- ALS 10/17/01
-- ^^^^^^
-- Added MAX2 function which returns the greater of two numbers.
-- ~~~~~~
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package opb_arb_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type TARGET_FAMILY_TYPE is (VIRTEX, VIRTEXII);
type CHAR_TO_INT_TYPE is array (character) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function Addr_Bits (x,y : std_logic_vector; addr_width : integer) return integer;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string;
function Get_Reg_File_Area (Target : TARGET_FAMILY_TYPE) return natural;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- set the size of the IPIF Address bus
-- since the register offset is 256 and each address range has to be a power
-- of two, the address range of the opb arbiter is 512, therefore the
-- IPIF address bus size is 9 bits.
constant IPIF_ABUS_WIDTH : integer := 9;
-- set control register bit locations
-- Note that the parked master ID is right justified in the register and the
-- size of this field varies with the number of masters and is therefore not
-- set in this package. CTRL_FIELD indicates the number of bits in the control
-- register that are left justified and don't vary with the number of masters
constant CTRL_FIELD : integer := 5;
constant DPEN_LOC : integer := 0; -- dynamic priority enable
constant DPENRW_LOC : integer := 1; -- dpe read/write
constant PEN_LOC : integer := 2; -- park enable
constant PENRW_LOC : integer := 3; -- pen read/write
constant PMN_LOC : integer := 4; -- park on master not last
constant PRV_LOC : integer := 5; -- priority registers valid
-- number of clock cycles after OPB_select asserts before arbiter times out if
-- OPB_xferAck or OPB_retry are not asserted
constant OPB_TIMEOUT_CNT : integer := 16;
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end opb_arb_pkg;
package body opb_arb_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- This function converts an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector; addr_width:integer)
return integer is
variable addr_nor : std_logic_vector(0 to addr_width-1);
begin
addr_nor := x xor y;
for i in 0 to addr_width-1
loop
if addr_nor(i) = '1' then return i;
end if;
end loop;
return addr_width;
end function Addr_Bits;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2
--
-- The for loop is a workaround for the bug in XST in which variables set in
-- a loop with an exit statement can't be returned as a constant.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
variable out_num : integer := 0;
variable val : integer := 1;
begin
if in_num = 0 then
out_num := 0;
else
for j in 0 to 8 loop -- for loop for XST
if val >= in_num then null;
else
val := val*2;
end if;
end loop;
out_num := val;
end if;
return out_num;
end function pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2
--
-- The log2 function returns the number of bits required to encode x choices.
-- This function is used to determine the number of bits required to encode the
-- master IDs.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 8 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-------------------------------------------------------------------------------
-- Function Get_RLOC_Name
--
-- This function calculates the proper RLOC value based on the FPGA target
-- family.
-------------------------------------------------------------------------------
--
function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
Y : integer;
X : integer) return string is
variable Col : integer;
variable Row : integer;
variable S : integer;
begin
if Target = VIRTEX then
Row := -Y;
Col := X/2;
S := 1 - (X mod 2);
return 'R' & itoa(Row) &
'C' & itoa(Col) &
".S" & itoa(S);
elsif Target = VIRTEXII then
return 'X' & itoa(X) & 'Y' & itoa(Y);
end if;
end Get_RLOC_Name;
-------------------------------------------------------------------------------
-- Function Get_Reg_File_Area
--
-- This function returns the number of slices in x that each bit of the
-- Register_File occupies
-------------------------------------------------------------------------------
function Get_Reg_File_Area (Target : TARGET_FAMILY_TYPE) return natural is
begin -- function Get_Y_Area
if Target = VIRTEX then
return 6;
elsif target = VIRTEXII then
return 4;
end if;
end function Get_Reg_File_Area;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
-- ASCII value - 42 TBD
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body opb_arb_pkg;
| bsd-3-clause | 0336eae3b14bf444a03228450f726920 | 0.472779 | 4.62793 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/ipif_steer.vhd | 3 | 18,833 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer.vhd,v 1.1 2003/05/07 21:48:34 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Steer is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64
C_SMALLEST : integer := 32; -- 8, 16, 32, 64
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity IPIF_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Steer is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| bsd-3-clause | a179d04cfdf8897f17230558a784c3e2 | 0.411034 | 3.644862 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_dma_du.vhd | 1 | 9,460 | --------------------------------------------------------------------------------
-- Title : Data unit of DMA controller
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_dma_du.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 17/09/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module consists of the data switching for the dma.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_dma
-- vme_dma_du
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_dma_du.vhd,v $
-- Revision 1.2 2013/09/12 08:45:25 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.1 2012/03/29 10:14:44 MMiehling
-- Initial Revision
--
-- Revision 1.4 2006/05/18 14:02:22 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:24 mmiehling
-- Initial Revision
--
-- Revision 1.3 2004/08/13 15:41:12 mmiehling
-- removed dma-slave and improved timing
--
-- Revision 1.2 2004/07/27 17:23:22 mmiehling
-- removed slave port
--
-- Revision 1.1 2004/07/15 09:28:50 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_dma_du IS
PORT (
rst : IN std_logic;
clk : IN std_logic;
dma_sta : IN std_logic_vector(9 DOWNTO 0);
irq_o : OUT std_logic; -- irq for cpu; asserted when done or error (if enabled)
arbit_slv : IN std_logic; -- if set, dma_slv has access and vica verse
slv_ack : IN std_logic; -- if set, write from slave side will be done
mstr_ack : IN std_logic; -- if set, write from master side will be done
-- slave signals
adr_i : IN std_logic_vector(6 DOWNTO 2);
sel_i : IN std_logic_vector(3 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
we_i : IN std_logic;
ack_o : IN std_logic;
-- wb_master singals
adr_o : IN std_logic_vector(6 DOWNTO 2);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vme_dma_au
dma_act_bd : IN std_logic_vector(7 DOWNTO 4); -- active bd number
dma_dest_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd destination adress
dma_sour_adr : OUT std_logic_vector(31 DOWNTO 2); -- active bd source adress
dma_sour_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the source device
dma_dest_device : OUT std_logic_vector(2 DOWNTO 0); -- selects the destination device
dma_vme_am : OUT std_logic_vector(4 DOWNTO 0); -- type of dma transmission
blk_sgl : OUT std_logic; -- indicates if DMA transfer should be done as block or single accesses
inc_sour : OUT std_logic; -- indicates if source adress should be incremented
inc_dest : OUT std_logic; -- indicates if destination adress should be incremented
dma_size : OUT std_logic_vector(15 DOWNTO 0); -- size of data package
clr_dma_act_bd : OUT std_logic; -- clears dma_act_bd if dma_mstr has done without error or
-- when dma_err will be cleared
-- dma_mstr
set_dma_err : IN std_logic; -- sets dma error bit if vme error
clr_dma_en : IN std_logic; -- clears dma en bit if dma_mstr has done
dma_en : OUT std_logic; -- starts dma_mstr, if 0 => clears dma_act_bd counter
dma_null : OUT std_logic; -- indicates the last bd
en_mstr_dat_i_reg : IN std_logic -- enable for data in
);
END vme_dma_du;
ARCHITECTURE vme_dma_du_arch OF vme_dma_du IS
SIGNAL dma_sta_int : std_logic_vector(7 DOWNTO 0);
SIGNAL act_bd_conf_int : std_logic_vector(31 DOWNTO 0);
SIGNAL int_data : std_logic_vector(31 DOWNTO 0);
SIGNAL int_adr : std_logic_vector(6 DOWNTO 2);
SIGNAL dma_err : std_logic;
SIGNAL dma_irq : std_logic;
SIGNAL dma_ien : std_logic;
SIGNAL dma_en_int : std_logic;
SIGNAL write_flag_mstr : std_logic;
SIGNAL mstr_dat_i_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL dma_dest_adr_int : std_logic_vector(31 DOWNTO 0);
SIGNAL dma_sour_adr_int : std_logic_vector(31 DOWNTO 0);
SIGNAL dma_size_reg : std_logic_vector(15 DOWNTO 0);
BEGIN
clr_dma_act_bd <= '1' WHEN (clr_dma_en = '1' AND set_dma_err = '0') OR dma_sta(9) = '1' ELSE '0';
dma_en <= dma_sta(0);
irq_o <= dma_sta(2);
dma_dest_adr <= dma_dest_adr_int(31 DOWNTO 2);
dma_sour_adr <= dma_sour_adr_int(31 DOWNTO 2);
dma_size <= dma_size_reg;
dma_sour_device <= act_bd_conf_int(18 DOWNTO 16);
dma_dest_device <= act_bd_conf_int(14 DOWNTO 12);
dma_vme_am <= act_bd_conf_int(8 DOWNTO 4);
blk_sgl <= '1' WHEN act_bd_conf_int(7 DOWNTO 4) = "0001" or act_bd_conf_int(7 DOWNTO 4) = "0101" ELSE -- A16 does not provide block mode => always single will be selected
'0' WHEN act_bd_conf_int(7 DOWNTO 4) = "1100" ELSE -- A24D64 does not provide single mode => always block will be selected
'0' WHEN act_bd_conf_int(7 DOWNTO 4) = "1110" ELSE -- A32D64 does not provide single mode => always block will be selected
act_bd_conf_int(3);
inc_sour <= act_bd_conf_int(2);
inc_dest <= act_bd_conf_int(1);
dma_null <= act_bd_conf_int(0);
int_data <= mstr_dat_i_reg;
int_adr <= adr_o;
write_flag_mstr <= '1' WHEN mstr_ack = '1' ELSE '0';
slv_dat_o <= (OTHERS => '0');
outdec : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
mstr_dat_i_reg <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF en_mstr_dat_i_reg = '1' THEN
mstr_dat_i_reg <= mstr_dat_i;
END IF;
END IF;
END PROCESS outdec;
-- dma_dest_adr_int 0x48
dest : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
dma_dest_adr_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF (write_flag_mstr = '1' AND int_adr(3 DOWNTO 2) = "00") THEN
dma_dest_adr_int(31 DOWNTO 0) <= int_data(31 DOWNTO 0);
END IF;
END IF;
END PROCESS dest;
-- dma_sour_adr_int 0x4c
sour: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
dma_sour_adr_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF (write_flag_mstr = '1' AND int_adr(3 DOWNTO 2) = "01") THEN
dma_sour_adr_int(31 DOWNTO 0) <= int_data(31 DOWNTO 0);
END IF;
END IF;
END PROCESS sour;
-- dma_size 0x50
siz : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
dma_size_reg <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF (write_flag_mstr = '1' AND int_adr(3 DOWNTO 2) = "10") THEN
dma_size_reg(15 DOWNTO 0) <= int_data(15 DOWNTO 0);
END IF;
END IF;
END PROCESS siz;
-- act_bd_conf_int 0x54
conf: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
act_bd_conf_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF (write_flag_mstr = '1' AND int_adr(3 DOWNTO 2) = "11") THEN
act_bd_conf_int(31 DOWNTO 0) <= int_data(31 DOWNTO 0);
END IF;
END IF;
END PROCESS conf;
END vme_dma_du_arch;
| gpl-3.0 | 0a769c4bd56b93bb7e0664bdc7299226 | 0.504334 | 3.770426 | false | false | false | false |
1995parham/Learning | vhdl/crc/crc_t.vhd | 1 | 1,252 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 23-02-2016
-- Module Name: crc_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity crc_t is
end entity;
architecture arch_crc_t of crc_t is
-- G(x) Function
constant G : std_logic_vector(3 downto 0) := "1011";
-- CRC Component definition
component crc is
generic (g : std_logic_vector);
port (d, clk : in std_logic;
r : buffer std_logic_vector(g'high - 1 downto g'low));
end component;
-- Middle signals
signal clk, d : std_logic := '0';
signal r : std_logic_vector(2 downto 0);
signal data : std_logic_vector(10 downto 0) := "10101100000";
signal run : std_logic := '1';
-- CRC Component configuration
for all:crc use entity work.crc(arch_crc);
begin
clk <= not clk after 50 ns when run = '1';
crc_1 : crc generic map (G) port map (d, clk, r);
process (clk)
variable I : natural := data'high + 1;
begin
if clk = '1' and clk'event then
if I > data'low then
I := I - 1;
d <= data(I);
else
run <= '0';
end if;
end if;
end process;
end architecture;
| gpl-2.0 | 943ce2abeabe72f334ddf59fa482e44d | 0.553514 | 3.218509 | false | false | false | false |
EnricoGiordano1992/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/xps_icapi_v1_01_a/hdl/vhdl/icap_wrapper.vhd | 3 | 10,911 | -------------------------------------------------------------------------------
-- icap_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESIM -- Parameter is TRUE for ReSim-based simulation
-- C_FAMILY -- target FPGA family
-------------------------------------------------------------------------------
-- --inputs
--
-- Icap_clk -- ICAP clock
-- Icap_ce -- ICAP chip enable
-- Icap_we -- ICAP write enable
-- Icap_datain -- ICAP configuration data in
--
-- --outputs
--
-- Icap_busy -- ICAP busy qualifier
-- Icap_dataout -- ICAP configuration readback data out
-------------------------------------------------------------------------------
entity icap_wrapper is
generic(
C_RESIM : integer := 1;
C_GEN_BITSWAP : integer := 1;
C_FAMILY : string := "virtex5"
);
port(
Icap_clk : in std_logic;
Icap_ce : in std_logic;
Icap_we : in std_logic;
Icap_datain : in std_logic_vector(31 downto 0);
Icap_busy : out std_logic;
Icap_dataout : out std_logic_vector(31 downto 0)
);
attribute KEEP : string;
attribute KEEP of Icap_ce : signal is "TRUE";
attribute KEEP of Icap_we : signal is "TRUE";
attribute KEEP of Icap_datain : signal is "TRUE";
attribute KEEP of Icap_dataout : signal is "TRUE";
attribute KEEP of Icap_busy : signal is "TRUE";
end icap_wrapper;
architecture imp of icap_wrapper is
component ICAP_VIRTEX4 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX5 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX6 is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CSB : in std_logic;
RDWRB : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX4_WRAPPER is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX5_WRAPPER is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CE : in std_logic;
WRITE : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
component ICAP_VIRTEX6_WRAPPER is
generic(
ICAP_WIDTH : string := "X8"
);
port(
CLK : in std_logic;
CSB : in std_logic;
RDWRB : in std_logic;
I : in std_logic_vector(31 downto 0);
BUSY : out std_logic;
O : out std_logic_vector(31 downto 0)
);
end component;
signal Icap_datain_bs : std_logic_vector(31 downto 0);
signal Icap_dataout_bs : std_logic_vector(31 downto 0);
begin -- architecture imp
-----------------------------------------------------------------------------
-- GEN_UNISIM
-----------------------------------------------------------------------------
-- Implement using ICAP instance on chip
-- Simulate using unisim model (black box)
GEN_UNISIM : if C_RESIM = 0 generate
GEN_VIRTEX4 : if (C_FAMILY="virtex4") generate
ICAP_VERTEX4_I : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X32")
port map (
CLK => Icap_clk,
CE => Icap_ce,
WRITE => Icap_we,
I => Icap_datain_bs,
BUSY => Icap_busy,
O => Icap_dataout_bs
);
end generate GEN_VIRTEX4;
GEN_VIRTEX5 : if (C_FAMILY="virtex5") generate
ICAP_VERTEX5_I : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => "X32")
port map (
CLK => icap_clk,
CE => icap_ce,
WRITE => icap_we,
I => icap_datain_bs,
BUSY => icap_busy,
O => icap_dataout_bs
);
end generate GEN_VIRTEX5;
GEN_VIRTEX6 : if (C_FAMILY="virtex6") generate
ICAP_VERTEX6_I : ICAP_VIRTEX6
generic map (
ICAP_WIDTH => "X32")
port map (
CLK => icap_clk,
CSB => icap_ce,
RDWRB => icap_we,
I => icap_datain_bs,
BUSY => icap_busy,
O => icap_dataout_bs
);
end generate GEN_VIRTEX6;
end generate GEN_UNISIM;
-----------------------------------------------------------------------------
-- GEN_RESIM:
-----------------------------------------------------------------------------
-- Implement using ICAP instance on chip
-- Simulate using ReSim model
GEN_RESIM : if C_RESIM = 1 generate
GEN_VIRTEX4 : if (C_FAMILY="virtex4") generate
ICAP_VIRTEX4_I : ICAP_VIRTEX4_WRAPPER
generic map (
ICAP_WIDTH => "X32"
)
port map (
CLK => icap_clk, -- I: clock
CE => icap_ce, -- I: clock enable
WRITE => icap_we, -- I: write enable
I => icap_datain_bs, -- I: configuration data
BUSY => icap_busy, -- O: busy
O => icap_dataout_bs -- O: configuration readback data
);
end generate GEN_VIRTEX4;
GEN_VIRTEX5 : if (C_FAMILY="virtex5") generate
ICAP_VIRTEX5_I : ICAP_VIRTEX5_WRAPPER
generic map (
ICAP_WIDTH => "X32"
)
port map (
CLK => icap_clk, -- I: clock
CE => icap_ce, -- I: clock enable
WRITE => icap_we, -- I: write enable
I => icap_datain_bs, -- I: configuration data
BUSY => icap_busy, -- O: busy
O => icap_dataout_bs -- O: configuration readback data
);
end generate GEN_VIRTEX5;
GEN_VIRTEX6 : if (C_FAMILY="virtex6") generate
ICAP_VIRTEX6_I : ICAP_VIRTEX6_WRAPPER
generic map (
ICAP_WIDTH => "X32"
)
port map (
CLK => icap_clk, -- I: clock
CSB => icap_ce, -- I: clock enable
RDWRB => icap_we, -- I: write enable
I => icap_datain_bs, -- I: configuration data
BUSY => icap_busy, -- O: busy
O => icap_dataout_bs -- O: configuration readback data
);
end generate GEN_VIRTEX6;
end generate GEN_RESIM;
-----------------------------------------------------------------------------
-- GEN_BITSWAP:
-----------------------------------------------------------------------------
----SystemVerilog Syntax
----
----generate begin : gen_i_bitswap
---- genvar j;
---- for (j = 0; j <= 3; j = j + 1) begin : mirror_j
---- genvar i;
---- for (i = 0; i <= 7; i = i + 1) begin : mirror_i
---- assign I_bs[j * 8 + i] = I[j * 8 + 7 - i];
---- end
---- end
----end endgenerate
----
----generate begin : gen_o_bitswap
---- genvar j;
---- for (j = 0; j <= 3; j = j + 1) begin : mirror_j
---- genvar i;
---- for (i = 0; i <= 7; i = i + 1) begin : mirror_i
---- assign O[j * 8 + i] = O_bs[j * 8 + 7 - i];
---- end
---- end
----end endgenerate
GEN_NO_BITSWAP : if ((C_FAMILY = "virtex4") or (C_GEN_BITSWAP = 0)) generate
Icap_datain_bs <= Icap_datain;
Icap_dataout <= Icap_dataout_bs;
end generate GEN_NO_BITSWAP;
GEN_VERITEX5_BS : if ((C_FAMILY = "virtex5") and (C_GEN_BITSWAP = 1)) generate
process(Icap_datain) begin
for j in 0 to 3 loop
for i in 0 to 7 loop
Icap_datain_bs(j * 8 + i) <= Icap_datain(j * 8 + 7 - i);
end loop;
end loop;
end process;
process(Icap_dataout_bs) begin
for j in 0 to 3 loop
for i in 0 to 7 loop
Icap_dataout(j * 8 + i) <= Icap_dataout_bs(j * 8 + 7 - i);
end loop;
end loop;
end process;
end generate GEN_VERITEX5_BS;
GEN_VERITEX6_BS : if ((C_FAMILY = "virtex6") and (C_GEN_BITSWAP = 1)) generate
process(Icap_datain) begin
for j in 0 to 3 loop
for i in 0 to 7 loop
Icap_datain_bs(j * 8 + i) <= Icap_datain(j * 8 + 7 - i);
end loop;
end loop;
end process;
process(Icap_dataout_bs) begin
for j in 0 to 3 loop
for i in 0 to 7 loop
Icap_dataout(j * 8 + i) <= Icap_dataout_bs(j * 8 + 7 - i);
end loop;
end loop;
end process;
end generate GEN_VERITEX6_BS;
end architecture imp;
| bsd-3-clause | 049d0122edd2e8cfd7f335320ed9a3dd | 0.409037 | 4.154989 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_thread_manager_v1_00_a/devl/bfmsim/simulation/behavioral/bfm_monitor_wrapper.vhd | 3 | 16,448 | -------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv46_monitor_bfm_v1_00_a.all;
entity bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 0);
M_priority : in std_logic_vector(0 to 1);
M_buslock : in std_logic_vector(0 to 0);
M_RNW : in std_logic_vector(0 to 0);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 3);
M_type : in std_logic_vector(0 to 2);
M_TAttribute : in std_logic_vector(0 to 15);
M_lockErr : in std_logic_vector(0 to 0);
M_abort : in std_logic_vector(0 to 0);
M_UABus : in std_logic_vector(0 to 31);
M_ABus : in std_logic_vector(0 to 31);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 0);
M_rdBurst : in std_logic_vector(0 to 0);
PLB_MAddrAck : in std_logic_vector(0 to 0);
PLB_MRearbitrate : in std_logic_vector(0 to 0);
PLB_MTimeout : in std_logic_vector(0 to 0);
PLB_MBusy : in std_logic_vector(0 to 0);
PLB_MRdErr : in std_logic_vector(0 to 0);
PLB_MWrErr : in std_logic_vector(0 to 0);
PLB_MIRQ : in std_logic_vector(0 to 0);
PLB_MWrDAck : in std_logic_vector(0 to 0);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic_vector(0 to 0);
PLB_MRdBTerm : in std_logic_vector(0 to 0);
PLB_MWrBTerm : in std_logic_vector(0 to 0);
PLB_Mssize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 1);
PLB_wrPrim : in std_logic_vector(0 to 1);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 255);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 0);
PLB_SMRdErr : in std_logic_vector(0 to 0);
PLB_SMWrErr : in std_logic_vector(0 to 0);
PLB_SMIRQ : in std_logic_vector(0 to 0);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end bfm_monitor_wrapper;
architecture STRUCTURE of bfm_monitor_wrapper is
component plbv46_monitor_bfm is
generic (
PLB_MONITOR_NUM : std_logic_vector(0 to 3);
PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31);
C_MON_PLB_AWIDTH : integer;
C_MON_PLB_DWIDTH : integer;
C_MON_PLB_NUM_MASTERS : integer;
C_MON_PLB_NUM_SLAVES : integer;
C_MON_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_buslock : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_RNW : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_BE : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_DWIDTH/8)-1));
M_msize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_size : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
M_type : in std_logic_vector(0 to ((3*C_MON_PLB_NUM_MASTERS)-1));
M_TAttribute : in std_logic_vector(0 to 16*C_MON_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_UABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_ABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_rdBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MAddrAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MTimeout : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Mssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_wrPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_MasterID : in std_logic_vector(0 to C_MON_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_MON_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wait : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_MBusy : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MRdErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MWrErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MIRQ : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_ssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_SLAVES)-1));
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to C_MON_PLB_DWIDTH-1);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
begin
bfm_monitor : plbv46_monitor_bfm
generic map (
PLB_MONITOR_NUM => B"0000",
PLB_SLAVE0_ADDR_LO_0 => X"00000000",
PLB_SLAVE0_ADDR_HI_0 => X"00000000",
PLB_SLAVE1_ADDR_LO_0 => X"00000000",
PLB_SLAVE1_ADDR_HI_0 => X"00000000",
PLB_SLAVE2_ADDR_LO_0 => X"00000000",
PLB_SLAVE2_ADDR_HI_0 => X"00000000",
PLB_SLAVE3_ADDR_LO_0 => X"00000000",
PLB_SLAVE3_ADDR_HI_0 => X"00000000",
PLB_SLAVE4_ADDR_LO_0 => X"00000000",
PLB_SLAVE4_ADDR_HI_0 => X"00000000",
PLB_SLAVE5_ADDR_LO_0 => X"00000000",
PLB_SLAVE5_ADDR_HI_0 => X"00000000",
PLB_SLAVE6_ADDR_LO_0 => X"00000000",
PLB_SLAVE6_ADDR_HI_0 => X"00000000",
PLB_SLAVE7_ADDR_LO_0 => X"00000000",
PLB_SLAVE7_ADDR_HI_0 => X"00000000",
PLB_SLAVE0_ADDR_LO_1 => X"00000000",
PLB_SLAVE0_ADDR_HI_1 => X"00000000",
PLB_SLAVE1_ADDR_LO_1 => X"00000000",
PLB_SLAVE1_ADDR_HI_1 => X"00000000",
PLB_SLAVE2_ADDR_LO_1 => X"00000000",
PLB_SLAVE2_ADDR_HI_1 => X"00000000",
PLB_SLAVE3_ADDR_LO_1 => X"00000000",
PLB_SLAVE3_ADDR_HI_1 => X"00000000",
PLB_SLAVE4_ADDR_LO_1 => X"00000000",
PLB_SLAVE4_ADDR_HI_1 => X"00000000",
PLB_SLAVE5_ADDR_LO_1 => X"00000000",
PLB_SLAVE5_ADDR_HI_1 => X"00000000",
PLB_SLAVE6_ADDR_LO_1 => X"00000000",
PLB_SLAVE6_ADDR_HI_1 => X"00000000",
PLB_SLAVE7_ADDR_LO_1 => X"00000000",
PLB_SLAVE7_ADDR_HI_1 => X"00000000",
C_MON_PLB_AWIDTH => 32,
C_MON_PLB_DWIDTH => 128,
C_MON_PLB_NUM_MASTERS => 1,
C_MON_PLB_NUM_SLAVES => 2,
C_MON_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_Mssize => PLB_Mssize,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_MasterID => PLB_MasterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ,
Sl_ssize => Sl_ssize,
PLB_SaddrAck => PLB_SaddrAck,
PLB_Swait => PLB_Swait,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_SwrDAck => PLB_SwrDAck,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SMBusy => PLB_SMBusy,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMIRQ => PLB_SMIRQ,
PLB_Sssize => PLB_Sssize
);
end architecture STRUCTURE;
| bsd-3-clause | 427553447fe6e83718f1473b1a002d22 | 0.607855 | 2.91115 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/interrupt_control.vhd | 3 | 38,408 | -------------------------------------------------------------------------------
-- $Id: interrupt_control.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
--interrupt_control.vhd version v1.00b
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- GAB 04/14/04
-- ^^^^^^
-- Updated to proc_common_v2_00_a
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- need 'conv_std_logic_vector' conversion function
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.proc_common_pkg.all;
use opb_v20_v1_10_d.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_INTERRUPT_REG_NUM : INTEGER := 16;
-- Number of IPIF Interrupt sources (not including IP or the
-- two latched IPIF ISR inputs)
C_NUM_IPIF_IRPT_SRC : INTEGER := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2, -- pass through (inverting)
3, -- registered level (non-inverting)
4, -- registered level (inverting)
5, -- positive edge detect
6 -- negative edge detect
);
C_INCLUDE_DEV_PENCODER : BOOLEAN := true;-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : Boolean := true; -- Specifies device ISC hierarchy
--Exclusion of Device ISC requires exclusion of Priority encoder
C_IRPT_DBUS_WIDTH : INTEGER := 32
);
port(
-- Inputs From the IPIF Bus
Bus2IP_Clk_i : In std_logic; -- Master timing clock from the IPIF
Bus2IP_Data_sa : In std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Bus2IP_RdReq_sa : In std_logic;
Bus2IP_Reset_i : In std_logic; -- Master Reset from the IPIF reset block
Bus2IP_WrReq_sa : In std_logic;
Interrupt_RdCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
Interrupt_WrCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
IPIF_Reg_Interrupts : In std_logic_vector(0 to 1);
-- Interrupt inputs from the IPIF sources that will get registered in this design
IPIF_Lvl_Interrupts : In std_logic_vector(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Level Interrupt inputs from the IPIF sources
-- Inputs from the IP Interface
IP2Bus_IntrEvent : In std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Interrupt inputs from the IP
-- Final Device Interrupt Output
Intr2Bus_DevIntr : Out std_logic;
-- Device interrupt output to the Master Interrupt Controller
-- Status Reply Outputs to the Bus
Intr2Bus_DBus : Out std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Intr2Bus_WrAck : Out std_logic;
Intr2Bus_RdAck : Out std_logic;
Intr2Bus_Error : Out std_logic;
Intr2Bus_Retry : Out std_logic;
Intr2Bus_ToutSup : Out std_logic
);
end interrupt_control ;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
--TYPES
-- no Types
-- CONSTANTS
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer range 0 to 15 := 0;
Constant DEVICE_IPR : integer range 0 to 15 := 1;
Constant DEVICE_IER : integer range 0 to 15 := 2;
Constant DEVICE_IAR : integer range 0 to 15 := 3;
Constant DEVICE_SIE : integer range 0 to 15 := 4;
Constant DEVICE_CIE : integer range 0 to 15 := 5;
Constant DEVICE_IIR : integer range 0 to 15 := 6;
Constant DEVICE_GIE : integer range 0 to 15 := 7;
Constant IP_ISR : integer range 0 to 15 := 8;
Constant IP_IPR : integer range 0 to 15 := 9;
Constant IP_IER : integer range 0 to 15 := 10;
Constant IP_IAR : integer range 0 to 15 := 11;
Constant IP_SIE : integer range 0 to 15 := 12;
Constant IP_CIE : integer range 0 to 15 := 13;
Constant IP_IIR : integer range 0 to 15 := 14;
Constant IP_GIE : integer range 0 to 15 := 15;
-- Generic to constant mapping
Constant IRPT_DBUS_WIDTH : Integer := C_IRPT_DBUS_WIDTH - 1;
Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
--INTERNAL SIGNALS
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector(IRPT_DBUS_WIDTH downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_rdack_d1 : std_logic;
Signal irpt_wrack : std_logic;
signal irpt_wrack_d1 : std_logic;
signal ip_irpt_status_reg : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector(PRIORITY_ENC_WIDTH-1 downto 0);
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start architecture logic -------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_RdAck <= irpt_rdack;
Intr2Bus_WrAck <= irpt_wrack;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to IRPT_DBUS_WIDTH loop
Intr2Bus_DBus(IRPT_DBUS_WIDTH-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk_i)
begin
If (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk_i)
begin
If (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1') Then -- toggle selected ISR bits from the DBus inputs
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data_sa(IRPT_DBUS_WIDTH-irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1') Then -- load input data from the DBus inputs
ip_irpt_enable_reg <= Bus2IP_Data_sa(IRPT_DBUS_WIDTH-IP_IRPT_HIGH_INDEX
to IRPT_DBUS_WIDTH);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1') Then -- load input data from the DBus inputs
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= (Bus2IP_Data_sa(IRPT_DBUS_WIDTH-i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1') Then -- load input data from the DBus inputs
ipif_irpt_enable_reg <= Bus2IP_Data_sa(IRPT_DBUS_WIDTH-IPIF_IRPT_HIGH_INDEX to IRPT_DBUS_WIDTH);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1') Then -- load input data from the DBus inputs
ipif_glbl_irpt_enable_reg <= Bus2IP_Data_sa(0);
-- Enable bit is loaded from the DBus MSB
--Placed at bit-0 MSB by Glenn Baxter
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= conv_std_logic_vector(irpt_position, PRIORITY_ENC_WIDTH);
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= conv_std_logic_vector(NO_INTR_VALUE, PRIORITY_ENC_WIDTH);
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE)
Begin
irpt_wrack <= Interrupt_WrCE(DEVICE_ISR) or
Interrupt_WrCE(DEVICE_IER) or
Interrupt_WrCE(DEVICE_GIE) or
Interrupt_WrCE(IP_ISR) or
Interrupt_WrCE(IP_IER);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE)
Begin
irpt_wrack <= Interrupt_WrCE(DEVICE_GIE) or
Interrupt_WrCE(IP_ISR) or
Interrupt_WrCE(IP_IER);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
GEN_SINGLE_CLK_WRACK : process(Bus2IP_Clk_i)
begin
if(Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1')then
if(Bus2IP_Reset_i = '1')then
irpt_wrack_d1 <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
end if;
end if;
end process GEN_SINGLE_CLK_WRACK;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1') Then
irpt_read_data(PRIORITY_ENC_WIDTH-1 downto 0) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_rdack <= ipif_pri_encode_present; -- set the acknowledge handshake depending on
-- priority encoder presence
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1') Then
irpt_read_data(IRPT_DBUS_WIDTH) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1') Then
irpt_read_data(IRPT_DBUS_WIDTH) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| bsd-3-clause | 4a7a4d15fe04150592ee0adb2faf322c | 0.49008 | 4.512218 | false | false | false | false |
EnricoGiordano1992/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/ipif_v1_00_a/hdl/vhdl/plbv46_slave_burst_wrapper_128.vhd | 3 | 21,245 | ------------------------------------------------------------------------------
-- plbv46_slave_burst_wrapper.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_burst_v1_01_a;
use plbv46_slave_burst_v1_01_a.plbv46_slave_burst;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plbv46_slave_burst_wrapper is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 128;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 1;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5";
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_MEM_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM_HIGHADDR : std_logic_vector := X"00000000"
-- ADD USER GENERICS ABOVE THIS LINE ---------------
);
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER PORTS BELOW THIS LINE ------------------
Bus2IP_Clk : out std_logic;
Bus2IP_Reset : out std_logic;
Bus2IP_Addr : out std_logic_vector(0 to 32-1);
Bus2IP_CS : out std_logic;
Bus2IP_RNW : out std_logic;
Bus2IP_Data : out std_logic_vector(0 to 128-1);
Bus2IP_BE : out std_logic_vector(0 to 128/8-1);
Bus2IP_Burst : out std_logic;
Bus2IP_BurstLength : out std_logic_vector(0 to 8); -- 8=log2(16*(128/8))
Bus2IP_RdReq : out std_logic;
Bus2IP_WrReq : out std_logic;
IP2Bus_AddrAck : in std_logic;
IP2Bus_Data : in std_logic_vector(0 to 128-1);
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
IP2Bus_Error : in std_logic
-- ADD USER PORTS ABOVE THIS LINE ------------------
);
end entity plbv46_slave_burst_wrapper;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plbv46_slave_burst_wrapper is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant PADDING_ZEROS : std_logic_vector(0 to 127) := (others => '0');
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
PADDING_ZEROS(0 to 31) & C_MEM_BASEADDR, -- user logic memory space 0 base address
PADDING_ZEROS(0 to 31) & C_MEM_HIGHADDR -- user logic memory space 0 high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1 -- number of ce for user logic memory space 0 (always 1 chip enable)
);
------------------------------------------
-- Cache line addressing mode (for cacheline read operations)
-- 0 = target word first on reads
-- 1 = line word first on reads
------------------------------------------
constant IPIF_CACHLINE_ADDR_MODE : integer := 0;
------------------------------------------
-- Number of storage locations for the write buffer
-- Valid depths are 0, 16, 32, or 64
-- 0 = no write buffer implemented
------------------------------------------
constant IPIF_WR_BUFFER_DEPTH : integer := 0;
------------------------------------------
-- The type out of the Bus2IP_BurstLength signal
-- 0 = length is in actual byte number
-- 1 = length is in data beats - 1
------------------------------------------
constant IPIF_BURSTLENGTH_TYPE : integer := 0;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_CS_INDEX : integer := 0;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
-- NOT USED: signal ipif_Bus2IP_Clk : std_logic;
-- NOT USED: signal ipif_Bus2IP_Reset : std_logic;
-- NOT USED: signal ipif_IP2Bus_WrAck : std_logic;
-- NOT USED: signal ipif_IP2Bus_RdAck : std_logic;
-- NOT USED: signal ipif_IP2Bus_AddrAck : std_logic;
-- NOT USED: signal ipif_IP2Bus_Error : std_logic;
-- NOT USED: signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
-- NOT USED: signal ipif_Bus2IP_RNW : std_logic;
-- NOT USED: signal ipif_Bus2IP_Burst : std_logic;
-- NOT USED: signal ipif_Bus2IP_WrReq : std_logic;
-- NOT USED: signal ipif_Bus2IP_RdReq : std_logic;
--
-- BITWIDTH ADAPTION:
--
-- Bitwidth of plbv46_slave_burst is variable depending on the C_SPLB_DWIDTH/C_SPLB_NATIVE_DWIDTH
-- Bitwidth of plbv46_slave_burst_wrapper_128 is tuned for 128bit systemc modules
--
-- The following signals may have different bitwidth between
-- plbv46_slave_burst and plbv46_slave_burst_wrapper_128. And MSBs of them may not be connected
--
signal ipif_IP2Bus_Data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_BE : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
signal ipif_Bus2IP_BurstLength : std_logic_vector(0 to log2(16*(C_SPLB_DWIDTH/8)));
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
begin
------------------------------------------
-- instantiate plbv46_slave_burst
------------------------------------------
PLBV46_SLAVE_BURST_I : entity plbv46_slave_burst_v1_01_a.plbv46_slave_burst
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_CACHLINE_ADDR_MODE => IPIF_CACHLINE_ADDR_MODE,
C_WR_BUFFER_DEPTH => IPIF_WR_BUFFER_DEPTH,
C_BURSTLENGTH_TYPE => IPIF_BURSTLENGTH_TYPE,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data, ---- FOR BITWIDTH ADAPTION
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_AddrAck => IP2Bus_AddrAck,
IP2Bus_Error => IP2Bus_Error,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data, ---- FOR BITWIDTH ADAPTION
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE, ---- FOR BITWIDTH ADAPTION
Bus2IP_Burst => Bus2IP_Burst,
Bus2IP_BurstLength => ipif_Bus2IP_BurstLength, ---- FOR BITWIDTH ADAPTION
Bus2IP_WrReq => Bus2IP_WrReq,
Bus2IP_RdReq => Bus2IP_RdReq,
Bus2IP_CS => ipif_Bus2IP_CS ---- FOR BITWIDTH ADAPTION
);
ipif_IP2Bus_Data <= IP2Bus_Data(128-C_SPLB_NATIVE_DWIDTH to 128-1);
Bus2IP_Data <= PADDING_ZEROS(C_SPLB_NATIVE_DWIDTH to 128-1) & ipif_Bus2IP_Data;
Bus2IP_BE <= PADDING_ZEROS(C_SPLB_NATIVE_DWIDTH/8 to 16-1) & ipif_Bus2IP_BE;
Bus2IP_BurstLength <= PADDING_ZEROS(log2(16*(C_SPLB_DWIDTH/8))+1 to 8) & ipif_Bus2IP_BurstLength;
Bus2IP_CS <= ipif_Bus2IP_CS(USER_CS_INDEX);
end IMP;
| bsd-3-clause | eddf86185930ef1a45297c2fd3c959eb | 0.456813 | 4.39037 | false | false | false | false |
a4a881d4/zcpsm | src/testbench/simrom.vhd | 1 | 1,618 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2015/03/01 00:47:15
-- Design Name:
-- Module Name: simrom - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity simrom is
Port ( clk : in STD_LOGIC);
end simrom;
architecture Behavioral of simrom is
signal addr : std_logic_vector( 9 downto 0 ):=(others=>'0');
signal dout : std_logic_vector( 17 downto 0 );
component zcpsmProgRom
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port (
clk : in std_logic;
addr : in std_logic_vector( AWIDTH-1 downto 0 );
dout : out std_logic_vector( 17 downto 0 )
);
end component;
begin
arom : zcpsmProgRom
generic map(
AWIDTH => 10,
PROG => "E:\zhaom\works\zcpsm\.work\ethtxrom.bit"
)
port map(
clk => clk,
addr => addr,
dout => dout
);
process(clk)
begin
if clk'event and clk = '1' then
addr<=addr+1;
end if;
end process;
end Behavioral;
| gpl-2.0 | 0b307d685b27e800150733778bd2df0e | 0.584672 | 3.635955 | false | false | false | false |
1995parham/Learning | vhdl/register/register.vhd | 1 | 1,004 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: register.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity n_register is
generic (N : integer := 8);
port (d : in std_logic_vector(N - 1 downto 0);
clk, s_sync, r_sync : in std_logic;
s_async, r_async : in std_logic;
q : out std_logic_vector(N - 1 downto 0));
end entity n_register;
architecture beh_arch_n_register of n_register is
begin
process (clk, s_async, r_async)
begin
if s_async = '1' then
q <= (others => '1');
elsif r_async = '1' then
q <= (others => '0');
end if;
if clk = '1' and clk'event then
if s_sync = '1' then
q <= (others => '1');
elsif r_sync = '1' then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process;
end architecture beh_arch_n_register;
| gpl-2.0 | bd06b61a69c41d8b7d585e565d1d1f55 | 0.50498 | 3.127726 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/core/pcStack.vhd | 1 | 1,404 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- pragma translate_off
--library synplify;
--use synplify.attributes.all;
-- pragma translate_on
entity pcstack is
generic(
depth:integer:=16;
awidth:integer:=4;
width:integer:=8
);
port (
reset : in std_logic;
clk: in std_logic;
en: in std_logic;
pop_push: in std_logic;
din: in std_logic_vector(width-1 downto 0);
dout: out std_logic_vector(width-1 downto 0)
);
end pcstack;
architecture behavior of pcstack is
type mem is array(0 to depth-1) of std_logic_vector(width-1 downto 0);
signal ram: mem:=(others=>(others=>'0'));
signal addr:std_logic_vector( awidth-1 downto 0 ):=(others=>'0');
component StackP is
generic (
width : integer
);
port(
reset: in std_logic;
en: in std_logic;
clk: in std_logic;
pop_push: in std_logic;
addr: out std_logic_vector(width-1 downto 0)
);
end component;
begin
astackP:stackP
generic map(
width => awidth
)
port map(
reset => reset,
en => en,
clk => clk,
pop_push => pop_push,
addr => addr
);
dout <= ram(conv_integer(addr));
process(clk)
begin
if rising_edge(clk) then
if en='1' and pop_push='1' then
--push stack
ram(conv_integer(addr))<=din;
end if;
end if;
end process;
end behavior;
| gpl-2.0 | caeab24d91322b928fc9bc43f6bacf7c | 0.624644 | 2.726214 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/or_with_enable_f.vhd | 2 | 11,970 | -------------------------------------------------------------------------------
-- $Id: or_with_enable_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_with_enable_f
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_with_enable_f.vhd
--
-- Description: Y <= or_reduce(OR_bits) and Enable
--
-- i.e., OR together the OR_bits and AND the result with Enable.
--
-- The implementation uses a single LUT if possible.
-- Otherwise, if C_FAMILY supports the carry chain concept,
-- it uses a minimal number of LUTs on a carry chain.
-- The native LUT size of C_FAMILY is taken into account.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 05/06/06 -- First version
-- ~~~~~~
-- FLO 05/25/06
-- ^^^^^^
-- -Using native_lut_size function from family_support.
-- -Moved C_FAMILY to end of generics.
-- -Minor cleanup.
-- ~~~~~~
-- FLO 11/17/07
-- ^^^^^^
-- -Work around because XST doesn't yet support or_reduce with null argument.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity or_with_enable_f is
generic (
C_OR_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
OR_bits : in std_logic_vector(0 to C_OR_WIDTH-1);
Enable : in std_logic;
Y : out std_logic
);
end or_with_enable_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
-- Makes visible the function 'supported' and related types,
-- including enumeration literals for the unisim primitives (e.g.
-- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.).
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture implementation of or_with_enable_f is
----------------------------------------------------------------------------
-- Here is determined the largest LUT width supported by the target family.
-- If no LUT is supported, the width is set to a very large number, which,
-- as things are structured, will cause an inferred implementation
-- to be used.
----------------------------------------------------------------------------
constant LUT_SIZE : integer := native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => integer'high
);
----------------------------------------------------------------------------
-- Here is determined which structural or inferred implementation to use.
----------------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and
OR_bits'length + 1 > LUT_SIZE;
-- Structural implementation not needed if the number of logic
-- inputs, i.e., the Enable plus the number of bits to be ORed,
-- will fit into a single LUT.
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
----------------------------------------------------------------------------
-- Reduction OR function.
----------------------------------------------------------------------------
function or_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r or v(i);
end loop;
return r;
end;
----------------------------------------------------------------------------
-- Signal to recast OR_bits into a local array whose index bounds and
-- direction are known.
----------------------------------------------------------------------------
signal OB : std_logic_vector(0 to OR_bits'length-1);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
OB <= OR_bits;
----------------------------------------------------------------------------
-- Inferred implementation.
----------------------------------------------------------------------------
INFERRED_GEN : if USE_INFERRED generate
begin
Y <= Enable and or_reduce(OB);
end generate INFERRED_GEN;
----------------------------------------------------------------------------
-- Structural implementation.
----------------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
constant NUM_PURE_OR_LUTS : positive := (OB'length / LUT_SIZE);
signal cy : std_logic_vector(0 to NUM_PURE_OR_LUTS);
signal final_lut : std_logic;
begin
--
cy(0) <= '0';
--
PURE_OR_GEN : for i in 0 to NUM_PURE_OR_LUTS-1 generate
signal lut : std_logic;
begin
lut <= not or_reduce(OB(i*LUT_SIZE to (i+1)*LUT_SIZE-1));
--
I_MUXCY : component MUXCY
port map (O =>cy(i+1),
CI=>cy(i),
DI=>'1',
S =>lut);
end generate;
--
XST_WA_GEN : if (OB'length mod LUT_SIZE) = 0 generate begin
final_lut <= Enable;
end generate;
--
ORIG_GEN : if (OB'length mod LUT_SIZE) /= 0 generate begin
final_lut <= Enable
and not or_reduce(OB(NUM_PURE_OR_LUTS*LUT_SIZE to OB'right));
end generate;
--
I_MUXCY_FINAL : component MUXCY
port map (O =>Y,
CI=>cy(NUM_PURE_OR_LUTS),
DI=>Enable,
S =>final_lut);
--
end generate STRUCTURAL_A_GEN;
end implementation;
| bsd-3-clause | 4b12f8dfc27586584cf79926239c1c97 | 0.411362 | 5.428571 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/slave.vhd | 10 | 27,202 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
| bsd-3-clause | eaf15d6add83ed7b16df5caf138ffc95 | 0.512242 | 4.117772 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/result_fsm.vhd | 11 | 3,686 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity result_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
sysrst : in std_logic;
rstdone : out std_logic;
rnw : in std_logic;
datain : in std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1)
);
end result_fsm;
architecture behavioral of result_fsm is
-- Declare signals for the results register
signal results : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
result_controller : process (clk,rst,sysrst,start,results,datain,rnw) is
begin
if( rising_edge(clk) ) then
data <= (others => '0');
finish <= '0';
if( rst = '1' or sysrst = '1' ) then
results <= (others => '0');
else
results <= results;
if( start = '1' ) then
if( rnw = '1' ) then
results <= datain;
else
data <= results;
end if;
finish <= '1';
end if;
end if;
end if;
end process result_controller;
end behavioral;
| bsd-3-clause | 7ff8d0e9e76582554bc4b9a33ae36975 | 0.574064 | 4.561881 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_two_v1_00_a/hdl/vhdl/user_logic_hwtul.vhd | 2 | 31,493 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Quicksort
-- Thread implements the quicksort algorithm
-- Passed in argument is a pointer to following struct
-- struct sortData {
-- int * startData; //pointer to start of array
-- int * endData; //pointer to end of array
-- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first
-- There is not return argument, the HWT just sorts the data.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic;
Ttimer : out std_logic_vector( 0 to 31)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
signal new_request : std_logic; --when there is a new request to HWTI
signal timer : std_logic_vector(0 to 31);
type timer_state_machine is ( idle,counting);
signal timer_cs : timer_state_machine :=idle;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
READ_SORTDATA_1,
READ_SORTDATA_2,
READ_SORTDATA_3,
READ_SORTDATA_4,
READ_SORTDATA_5,
READ_SORTDATA_6,
READ_SORTDATA_7,
READ_SORTDATA_8,
COPY_DATA_1,
COPY_DATA_2,
COPY_DATA_3,
COPY_DATA_4,
COPY_DATA_5,
COPY_DATA_6,
COPY_DATA_7,
RECOPY_DATA_1,
RECOPY_DATA_2,
RECOPY_DATA_3,
RECOPY_DATA_4,
FREE_1,
FREE_2,
CALL_QSORT_1,
CALL_QSORT_2,
CALL_QSORT_3,
READ_ARRAY_1,
READ_ARRAY_2,
READ_ARRAY_3,
READ_ARRAY_4,
READ_ARRAY_5,
READ_ARRAY_6,
EXIT_THREAD_1,
EXIT_THREAD_2,
QUICKSORT_1,
QUICKSORT_2,
QUICKSORT_3,
QUICKSORT_4,
QUICKSORT_5,
QUICKSORT_6,
QUICKSORT_7,
QUICKSORT_8,
QUICKSORT_9,
QUICKSORT_A,
QUICKSORT_B,
QUICKSORT_DO,
QUICKSORT_WHILE_LEFT_0,
QUICKSORT_WHILE_LEFT_1,
QUICKSORT_WHILE_LEFT_2,
QUICKSORT_WHILE_LEFT_3,
QUICKSORT_BREAK,
QUICKSORT_WHILE_RIGHT_1,
QUICKSORT_WHILE_RIGHT_2,
QUICKSORT_WHILE_RIGHT_3,
QUICKSORT_SWAP_1,
QUICKSORT_SWAP_2,
QUICKSORT_SWAP_3,
QUICKSORT_SWAP_4,
QUICKSORT_SWAP_5,
QUICKSORT_WHILE,
QUICKSORT_CALL_QS_0,
QUICKSORT_CALL_QS_1,
QUICKSORT_CALL_QS_2,
QUICKSORT_CALL_QS_3,
QUICKSORT_CALL_QS_4,
QUICKSORT_CALL_QS_5,
QUICKSORT_CALL_QS_6,
QUICKSORT_CALL_QS_7,
QUICKSORT_CALL_QS_8,
QUICKSORT_CALL_QS_9,
QUICKSORT_CALL_QS_A,
QUICKSORT_RETURN,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_READ_SORTDATA_5 : std_logic_vector(0 to 15) := x"0007";
constant U_COPY_DATA_3 : std_logic_vector(0 to 15) := x"0053";
constant U_READ_ARRAY_1 : std_logic_vector(0 to 15) := x"0031";
constant U_EXIT_THREAD_1 : std_logic_vector(0 to 15) := x"0021";
constant U_FREE_1 : std_logic_vector(0 to 15) := x"0041";
constant U_QUICKSORT_1 : std_logic_vector(0 to 15) := x"0101";
constant U_QUICKSORT_CALL_QS_6 : std_logic_vector(0 to 15) := x"0171";
constant U_QUICKSORT_RETURN : std_logic_vector(0 to 15) := x"0181";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
-- constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
-- constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
-- constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
-- constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
-- constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
-- constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal startPtr, startPtr_next : std_logic_vector(0 to 31);
signal endPtr, endPtr_next : std_logic_vector(0 to 31);
signal leftPtr, leftPtr_next : std_logic_vector(0 to 31);
signal rightPtr, rightPtr_next : std_logic_vector(0 to 31);
signal left, left_next : std_logic_vector(0 to 31);
signal right, right_next : std_logic_vector(0 to 31);
signal pivot, pivot_next : std_logic_vector(0 to 31);
signal cache, cache_next : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
Ttimer <= timer;
timer_process: process(clock)
begin
if (clock'event and (clock = '1')) then
case timer_cs is
when idle=>
timer <= (others =>'0');
if current_state= FUNCTION_START then
timer_cs <= counting;
end if;
when counting =>
timer <= timer + x"00000001";
if (current_state= FUNCTION_RESET or current_state=EXIT_THREAD_1) then
timer_cs <= idle;
end if;
when others =>
timer <= (others =>'0');
timer_cs <= idle;
end case;
end if;
end process timer_process;
wr <= '0' when ( current_state= WAIT_STATE ) else new_request ;
rd <= exist;
HWTUL_STATE_PROCESS : process (clock,exist) is
begin
if (clock'event and (clock = '1')) then
startPtr <= startPtr_next;
endPtr <= endPtr_next;
leftPtr <= leftPtr_next;
rightPtr <= rightPtr_next;
left <= left_next;
right <= right_next;
pivot <= pivot_next;
cache <= cache_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (exist = '1') then
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_READ_SORTDATA_5 =>
current_state <= READ_SORTDATA_5;
when U_COPY_DATA_3 =>
current_state <= COPY_DATA_3;
when U_READ_ARRAY_1 =>
current_state <= READ_ARRAY_1;
when U_FREE_1 =>
current_state <= FREE_1;
when U_EXIT_THREAD_1 =>
current_state <= EXIT_THREAD_1;
when U_QUICKSORT_1 =>
current_state <= QUICKSORT_1;
when U_QUICKSORT_CALL_QS_6 =>
current_state <= QUICKSORT_CALL_QS_6;
when U_QUICKSORT_RETURN =>
current_state <= QUICKSORT_RETURN;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
elsif ( new_request = '0') then
current_state <= next_state;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
new_request <= '1';
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
startPtr_next <= startPtr;
endPtr_next <= endPtr;
leftPtr_next <= leftPtr;
rightPtr_next <= rightPtr;
left_next <= left;
right_next <= right;
pivot_next <= pivot;
cache_next <= cache;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
startPtr_next <= Z32;
endPtr_next <= Z32;
leftPtr_next <= Z32;
rightPtr_next <= Z32;
left_next <= Z32;
right_next <= Z32;
pivot_next <= Z32;
cache_next <= '1';
new_request <= '0';
when FUNCTION_START => -- 0002
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_SORTDATA_1;
next_state <= WAIT_STATE;
when READ_SORTDATA_1 => -- 0003
-- The passed in argument is address of struct sortdata
-- For the time being, store value in startPtr
startPtr_next <= toUser_value;
-- Read the endPtr address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value + 4;
return_state_next <= READ_SORTDATA_2;
next_state <= WAIT_STATE;
when READ_SORTDATA_2 => -- 0004
endPtr_next <= toUser_value;
-- Read the cache option
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= startPtr + 8;
return_state_next <= READ_SORTDATA_3;
next_state <= WAIT_STATE;
when READ_SORTDATA_3 => -- 0005
cache_next <= toUser_value(31);
-- Now read the address of startPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= startPtr;
return_state_next <= READ_SORTDATA_4;
next_state <= WAIT_STATE;
when READ_SORTDATA_4 => -- 0006
startPtr_next <= toUser_value;
leftPtr_next <= toUser_value;
rightPtr_next <= endPtr;
-- Declare four local variables to hold start, end, left, right pointers
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= x"00000004";
if ( cache = '1' ) then
-- copy the global data locally
return_state_next <= COPY_DATA_1;
next_state <= WAIT_STATE;
else
-- work on data where it is
return_state_next <= READ_SORTDATA_5;
next_state <= WAIT_STATE;
end if;
when READ_SORTDATA_5 => -- 0007
-- Save the start pointer
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= startPtr;
return_state_next <= READ_SORTDATA_6;
next_state <= WAIT_STATE;
when READ_SORTDATA_6 => -- 0008
-- Save the end pointer
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000001";
thrd2intrfc_value <= endPtr;
return_state_next <= READ_SORTDATA_7;
next_state <= WAIT_STATE;
when READ_SORTDATA_7 => -- 0009
-- Save the left pointer
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000002";
thrd2intrfc_value <= leftPtr;
return_state_next <= READ_SORTDATA_8;
next_state <= WAIT_STATE;
when READ_SORTDATA_8 => -- 000A
-- Save the right pointer
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000003";
thrd2intrfc_value <= rightPtr;
-- Sort the data!
return_state_next <= CALL_QSORT_1;
next_state <= WAIT_STATE;
when CALL_QSORT_1 => -- 0011
-- Push the second argument, endPtr;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= rightPtr;
return_state_next <= CALL_QSORT_2;
next_state <= WAIT_STATE;
when CALL_QSORT_2 => -- 0012
-- Push the first argument, startPtr;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= leftPtr;
return_state_next <= CALL_QSORT_3;
next_state <= WAIT_STATE;
when CALL_QSORT_3 => -- 0013
-- Call quicksort
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= U_QUICKSORT_1;
-- thrd2intrfc_value <= Z32(0 to 15) & U_READ_ARRAY_1;
thrd2intrfc_value <= Z32(0 to 15) & U_EXIT_THREAD_1;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when EXIT_THREAD_1 => -- 0021
-- Push a null argument onto stack, as required by hthread_exit;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= timer;
return_state_next <= EXIT_THREAD_2;
next_state <= WAIT_STATE;
when EXIT_THREAD_2 => -- 0022
-- Call exit thread
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when ERROR_STATE => -- 7999
next_state <= ERROR_STATE;
new_request <= '0';
-----------------------------------------------------------------------
-- Quicksort function
-- argument 1 - start pointer
-- argument 2 - end pointer
-----------------------------------------------------------------------
when QUICKSORT_1 => -- 0101
-- Read the first argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
return_state_next <= QUICKSORT_2;
next_state <= WAIT_STATE;
when QUICKSORT_2 => -- 0102
startPtr_next <= toUser_value;
-- Read the second argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= x"00000001";
return_state_next <= QUICKSORT_3;
next_state <= WAIT_STATE;
when QUICKSORT_3 => -- 0103
endPtr_next <= toUser_value;
next_state <= QUICKSORT_4;
new_request <= '0';
when QUICKSORT_4 => -- 0104
-- Declare 5 variables
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= x"00000002";
return_state_next <= QUICKSORT_5;
next_state <= WAIT_STATE;
when QUICKSORT_5 => -- 0105
-- Copy the start and end pointers
leftPtr_next <= startPtr;
rightPtr_next <= endPtr;
next_state <= QUICKSORT_6;
new_request <= '0';
when QUICKSORT_6 => -- 0106
-- check to see if left and right pointers are equal
if ( leftPtr >= rightPtr ) then
-- Nothing to sort, return
next_state <= QUICKSORT_RETURN;
else
next_state <= QUICKSORT_7;
end if;
new_request <= '0';
when QUICKSORT_7 => -- 0107
-- Read the value of the leftPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= leftPtr;
return_state_next <= QUICKSORT_8;
next_state <= WAIT_STATE;
when QUICKSORT_8 => -- 0108
left_next <= toUser_value;
-- Read the value of the rightPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= rightPtr;
return_state_next <= QUICKSORT_9;
next_state <= WAIT_STATE;
when QUICKSORT_9 => -- 0109
right_next <= toUser_value;
next_state <= QUICKSORT_A;
new_request <= '0';
when QUICKSORT_A => -- 010A
-- determine the pivot value by first taking sum of left and right
pivot_next <= left + right;
next_state <= QUICKSORT_B;
new_request <= '0';
when QUICKSORT_B => -- 010B
-- next divide the sum of left and right by two (or shift)
pivot_next <= '0' & pivot(0 to 30);
next_state <= QUICKSORT_DO;
new_request <= '0';
when QUICKSORT_DO => -- 0111
-- This is a placeholder for my own sanity
next_state <= QUICKSORT_WHILE_LEFT_0;
new_request <= '0';
when QUICKSORT_WHILE_LEFT_0 => -- 0121
-- check to see if leftPtr moved past rightPtr
if ( leftPtr < rightPtr ) then
next_state <= QUICKSORT_WHILE_LEFT_1;
else
leftPtr_next <= rightPtr;
next_state <= QUICKSORT_BREAK;
end if;
new_request <= '0';
when QUICKSORT_WHILE_LEFT_1 => -- 0121
-- check to see if left < pivot
if ( left <= pivot ) then
-- left does not have to be swapped, increment leftPtr
leftPtr_next <= leftPtr + 4;
next_state <= QUICKSORT_WHILE_LEFT_2;
else
-- left needs to be swapped, end the while loop
next_state <= QUICKSORT_BREAK;
end if;
new_request <= '0';
when QUICKSORT_WHILE_LEFT_2 => -- 0122
-- read value of leftPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= leftPtr;
return_state_next <= QUICKSORT_WHILE_LEFT_3;
next_state <= WAIT_STATE;
when QUICKSORT_WHILE_LEFT_3 => -- 0123
left_next <= toUser_value;
next_state <= QUICKSORT_WHILE_LEFT_0;
new_request <= '0';
when QUICKSORT_BREAK => -- 0131
-- Check that we did not move past right ptr
if ( leftPtr >= rightPtr ) then
-- we are done swapping
next_state <= QUICKSORT_CALL_QS_0;
else
next_state <= QUICKSORT_WHILE_RIGHT_1;
end if;
new_request <= '0';
when QUICKSORT_WHILE_RIGHT_1 => -- 0141
-- check to see if right < pivot
if ( right > pivot ) then
-- right does not have to be swapped, decrement rightPtr
rightPtr_next <= rightPtr - 4;
next_state <= QUICKSORT_WHILE_RIGHT_2;
else
-- right needs to be swapped, end the while loop
next_state <= QUICKSORT_SWAP_1;
end if;
new_request <= '0';
when QUICKSORT_WHILE_RIGHT_2 => -- 0142
-- read value of rightPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= rightPtr;
return_state_next <= QUICKSORT_WHILE_RIGHT_3;
next_state <= WAIT_STATE;
when QUICKSORT_WHILE_RIGHT_3 => -- 0143
right_next <= toUser_value;
next_state <= QUICKSORT_BREAK;
new_request <= '0';
when QUICKSORT_SWAP_1 => -- 0151
-- write the value of rightPtr with left
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= rightPtr;
thrd2intrfc_value <= left;
return_state_next <= QUICKSORT_SWAP_2;
next_state <= WAIT_STATE;
when QUICKSORT_SWAP_2 => -- 0152
-- write the value of leftPtr with right
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= leftPtr;
thrd2intrfc_value <= right;
return_state_next <= QUICKSORT_SWAP_3;
next_state <= WAIT_STATE;
when QUICKSORT_SWAP_3 => -- 0153
-- increment/decrement pointers
leftPtr_next <= leftPtr + 4;
rightPtr_next <= rightPtr - 4;
next_state <= QUICKSORT_SWAP_4;
new_request <= '0';
when QUICKSORT_SWAP_4 => -- 0154
-- read new value of left
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= leftPtr;
return_state_next <= QUICKSORT_SWAP_5;
next_state <= WAIT_STATE;
when QUICKSORT_SWAP_5 => -- 0155
left_next <= toUser_value;
-- read new value of right
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= rightPtr;
return_state_next <= QUICKSORT_WHILE;
next_state <= WAIT_STATE;
when QUICKSORT_WHILE => -- 0161
right_next <= toUser_value;
-- check to make sure leftPtr < rightPtr
if ( leftPtr < rightPtr ) then
next_state <= QUICKSORT_DO;
else
next_state <= QUICKSORT_CALL_QS_0;
end if;
new_request <= '0';
when QUICKSORT_CALL_QS_0 => -- 0170
-- Check to see if leftPtr == rightPtr
if ( leftPtr = rightPtr ) then
-- Check to see if right > pivot
if ( right >= pivot ) then
leftPtr_next <= rightPtr - 4;
else
rightPtr_next <= rightPtr + 4;
end if;
else
if ( right > pivot ) then
leftPtr_next <= rightPtr - 4;
else
leftPtr_next <= rightPtr;
rightPtr_next <= leftPtr;
end if;
end if;
next_state <= QUICKSORT_CALL_QS_1;
new_request <= '0';
when QUICKSORT_CALL_QS_1 => -- 0171
-- Before calling quicksort need to save rightPtr and endPtr
-- Save the rightPtr
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000000";
thrd2intrfc_value <= rightPtr;
return_state_next <= QUICKSORT_CALL_QS_2;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_2 => -- 0172
-- Save the endPtr
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000001";
thrd2intrfc_value <= endPtr;
return_state_next <= QUICKSORT_CALL_QS_3;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_3 => -- 0173
-- Push the leftPtr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= leftPtr;
return_state_next <= QUICKSORT_CALL_QS_4;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_4 => -- 0174
-- Push the startPtr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= startPtr;
return_state_next <= QUICKSORT_CALL_QS_5;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_5 => -- 0175
-- Call quicksort
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= U_QUICKSORT_1;
thrd2intrfc_value <= Z32(0 to 15) & U_QUICKSORT_CALL_QS_6;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_6 => -- 0176
-- read the value of endPtr
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= x"00000001";
return_state_next <= QUICKSORT_CALL_QS_7;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_7 => -- 0177
endPtr_next <= toUser_value;
-- read the value of rightPtr
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= x"00000000";
return_state_next <= QUICKSORT_CALL_QS_8;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_8 => -- 0178
rightPtr_next <= toUser_value;
-- Push the rightPtr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= endPtr;
return_state_next <= QUICKSORT_CALL_QS_9;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_9 => -- 0179
-- push the endPtr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= rightPtr;
return_state_next <= QUICKSORT_CALL_QS_A;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_A => -- 017A
-- Call quicksort
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= U_QUICKSORT_1;
thrd2intrfc_value <= Z32(0 to 15) & U_QUICKSORT_RETURN;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when QUICKSORT_RETURN => -- 0181
-- Return
thrd2intrfc_opcode <= OPCODE_RETURN;
thrd2intrfc_value <= Z32;
return_state_next <= ERROR_STATE;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when others =>
next_state <= ERROR_STATE;
new_request <= '0';
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | f4658e44ba26816ccdcc2b33fd7372a9 | 0.531928 | 4.142181 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_v20.vhd | 3 | 30,900 | -------------------------------------------------------------------------------
-- $Id: opb_v20.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_v20.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_v20.vhd
-- Version: v1.10c
-- Description: IBM OPB (On-chip Peripheral Bus) implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- opb_v20.vhd
-- -- opb_arbiter.vhd
--
--VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Gmm_SP2
-- Upgraded the IP with opb_ipif_v3_01_a
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Im_SP1
--
-- Modified the files below for the processes MASTER_LOOP and MASTERLOOP to
-- remove the latch it was creating:
-- 1) priority_register_logic.vhd
-- 2) arbitration_logic.vhd
-- These modules are present in the opb_arbiter_v1_02_e.
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- BLT 2002-01-08 Added WDT Reset
-- BLT 2002-05-02 Added instantiation of opb_arbiter
-- ALS 2003-01-07 Instantiated opb_arbiter_v1_02_d to optimize
-- opb_timeout (registered it)
-- bsbrao 2004-09-27 Upgraded the arbiter IP with opb_ipif_v3_01_a
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.or_gate;
use opb_v20_v1_10_d.opb_arbiter;
library Unisim;
use Unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_USE_LUT_OR -- Use LUT-based OR instead of MUXCY-based OR
-- C_EXT_RESET_HIGH -- External reset is active high
-- C_BASEADDR -- OPB Arbiter base address
-- C_HIGHADDR -- OPB Arbiter high address
-- C_NUM_MASTERS -- number of OPB masters
-- C_NUM_SLAVES -- number of OPB slaves (external to opb_v20)
-- Do not include the slave interface of the
-- opb_arbiter (if present) in this total.
-- C_OPB_DWIDTH -- width of OPB data bus
-- C_OPB_AWIDTH -- width of OPB address bus
-- C_DYNAM_PRIORITY -- dynamic or fixed priority
-- C_REG_GRANTS -- registered or combinational grant outputs
-- C_PARK -- bus parking
-- C_PROC_INTRFCE -- OPB slave interface
-- C_DEV_BLK_ID -- device block id
-- C_DEV_MIR_ENABLE -- IPIF mirror capability enable
--
-- Definition of Ports:
-- See OPB specification V2.0
--
-- input SYS_Rst -- System reset
-- input Debug_SYS_Rst -- Reset from JTAG UART for reseting from debugger
-- input WDT_Rst -- Reset from Watchdog Timer
-- input OPB_Clk -- OPB Clock
-- output OPB_Rst -- Reset out to OPB bus
--
-- -- Master outputs
-- input M_ABus -- master address
-- input M_BE -- master byte enables
-- input M_beXfer -- master byte enable transfer
-- input M_busLock -- master buslock
-- input M_DBus -- master databus
-- input M_DBusEn -- master databus enable
-- input M_DBusEn32_63 -- master databus enable for data bits 32:63
-- input M_dwXfer -- master double word transfer
-- input M_fwXfer -- master fullword transfer
-- input M_hwXfer -- master halfword transfer
-- input M_request -- master request
-- input M_RNW -- master read/not write
-- input M_select -- master select
-- input M_seqAddr -- master sequential address
-- -- Slave outputs
-- input Sl_beAck -- slave byte enable acknowledge
-- input Sl_DBus -- slave databus
-- input Sl_DBusEn -- slave databus enable
-- input Sl_DBusEn32_63 -- slave databus enable for data bits 32:63
-- input Sl_errAck -- slave error acknowledge
-- input Sl_dwAck -- slave doubleword acknowledge
-- input Sl_fwAck -- slave fullword acknowledge
-- input Sl_hwAck -- slave halfword acknowledge
-- input Sl_retry -- slave retry
-- input Sl_toutSup -- slave timeout suppress
-- input Sl_xferAck -- slave transfer acknowledge
--
-- -- OPB outputs
-- output OPB_MRequest -- OPB request
-- output OPB_ABus -- OPB address
-- output OPB_BE -- OPB byte enables
-- output OPB_beXfer -- OPB byte enable transfer
-- output OPB_beAck -- OPB
-- output OPB_busLock -- OPB buslock
-- output OPB_rdDBus -- OPB read databus
-- output OPB_wrDBus -- OPB write databus
-- output OPB_DBus -- OPB databus
-- output OPB_errAck -- OPB error acknowledge
-- output OPB_dwAck -- OPB doubleword acknowledge
-- output OPB_dwXfer -- OPB doubleword transfer
-- output OPB_fwAck -- OPB fullword acknowledge
-- output OPB_fwXfer -- OPB fullword transfer
-- output OPB_hwAck -- OPB halfword acknowledge
-- output OPB_hwXfer -- OPB halfword transfer
-- output OPB_MGrant -- OPB master grant
-- output OPB_pendReq -- OPB pending request
-- output OPB_retry -- OPB retry
-- output OPB_RNW -- OPB read/not write
-- output OPB_select -- OPB select
-- output OPB_seqAddr -- OPB sequential address
-- output OPB_timeout -- OPB timeout
-- output OPB_toutSup -- OPB timeout suppress
-- output OPB_xferAck -- OPB transfer acknowledge
--
-- OPB V2.0 Specification exceptions:
--
-- 1. DMA_SlnAck and Sln_dmaReq are not used.
-- 2. Mn_UABus and OPB_UABus are not used since the address bus width is
-- a parameter.
-- 3. M_DBusEn, M_DBusEn32_64, Sl_DBusEn, and Sl_DBusEn32_63 have no function
-- since we require all masters and slaves to drive zero if they are
-- inactive. All AND'ing with select, etc., is done in the master or slave
-- so that the AND is not required in the bus implementation.
-- 4. The OPB_DBus has been split into two intermediate buses, OPB_wrDBus and
-- OPB_rdDBus, for more efficient implementation in FPGA. The OPB_DBus is
-- the OR of these two intermediate buses.
-- 5. OPB_xferAck and OPB_retry MUST be asserted within 15 clock cycles
-- cycles (by the rising edge of the 16th clock) and OPB_toutSup must be
-- asserted by the rising edge of the 14th clock so that OPB_timeout
-- can be registered and FPGA timing is improved
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_v20 is
generic (
-- Bus interconnect generics
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 8;
C_NUM_SLAVES : integer := 4;
C_USE_LUT_OR : integer := 0;
C_EXT_RESET_HIGH : integer := 1;
-- Arbiter generics
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port (
-- Clock and reset
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
-- Master outputs
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1)
:= (others => '0');
M_BE : in std_logic_vector(0 to
(C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1)
:= (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
-- Slave outputs
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*
C_NUM_SLAVES-1)
:= (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
-- OPB outputs
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); -- extra
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); -- extra
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end entity opb_v20;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of opb_v20 is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Integer_to_Boolean (x: integer) return boolean is
begin
if x=0 then return false;
else return true;
end if;
end function Integer_to_Boolean;
-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
constant C_USE_LUT_OR_B : boolean := Integer_to_Boolean(C_USE_LUT_OR);
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
signal arb_timeout : std_logic := '0';
signal arb_mgrant : std_logic_vector(0 to C_NUM_MASTERS-1);
signal arb_dbus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal arb_errack : std_logic;
signal arb_retry : std_logic;
signal arb_toutsup : std_logic;
signal arb_xferack : std_logic;
signal opb_DBus_inputs : std_logic_vector(0 to 2*C_OPB_DWIDTH-1);
signal iOPB_wrDBus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iOPB_rdDBus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iOPB_beXfer : std_logic_vector(0 to 0);
signal iOPB_beAck : std_logic_vector(0 to 0);
signal iOPB_busLock : std_logic_vector(0 to 0);
signal iOPB_errAck : std_logic_vector(0 to 0);
signal iOPB_dwAck : std_logic_vector(0 to 0);
signal iOPB_dwXfer : std_logic_vector(0 to 0);
signal iOPB_fwAck : std_logic_vector(0 to 0);
signal iOPB_fwXfer : std_logic_vector(0 to 0);
signal iOPB_hwAck : std_logic_vector(0 to 0);
signal iOPB_hwXfer : std_logic_vector(0 to 0);
signal iOPB_retry : std_logic_vector(0 to 0);
signal iOPB_RNW : std_logic_vector(0 to 0);
signal iOPB_select : std_logic_vector(0 to 0);
signal iOPB_seqAddr : std_logic_vector(0 to 0);
signal iOPB_toutSup : std_logic_vector(0 to 0);
signal iOPB_xferAck : std_logic_vector(0 to 0);
signal iOPB_Rst : std_logic;
signal iOPB_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal iOPB_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal srl_time_out : std_logic;
signal sys_rst_i : std_logic;
-----------------------------------------------------------------------------
-- Attribute declarations
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin -- architecture imp
--------------------------------------------------------------------------------
-- Power On Reset to OPB
--------------------------------------------------------------------------------
SYS_RST_PROC: process (SYS_Rst,WDT_Rst,Debug_SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input or WDT_Rst or Debug_SYS_Rst;
end process SYS_RST_PROC;
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => OPB_Clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
POR_FF_I: FDS
port map (
Q => iOPB_Rst,
D => srl_time_out,
C => OPB_Clk,
S => sys_rst_i);
OPB_MRequest <= M_request; -- pass the Master request through
OPB_ABus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,C_OPB_AWIDTH,C_USE_LUT_OR_B)
port map (M_ABus,iOPB_ABus);
OPB_BE_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,(C_OPB_DWIDTH+7)/8,
C_USE_LUT_OR_B)
port map (M_BE,iOPB_BE);
OPB_beXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_beXfer,iOPB_beXfer);
OPB_busLock_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_busLock,iOPB_busLock);
-- The following two signals are not part of the V2.0 spec but are
-- intermediate buses that are OR'ed to form OPB_DBus. They can be
-- used in an implementation to optimize the master and slave OR
-- functions by breaking up the OPB_DBus OR gate.
OPB_wrDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (M_DBus,iOPB_wrDBus);
opb_DBus_inputs <= iOPB_wrDBus & iOPB_rdDBus;
OPB_rdDBus <= iOPB_rdDBus;
OPB_wrDBus <= iOPB_wrDBus;
OPB_DBus_I: entity opb_v20_v1_10_d.or_gate generic map (2,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (opb_DBus_inputs,OPB_DBus);
OPB_dwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_dwXfer,iOPB_dwXfer);
OPB_fwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_fwXfer,iOPB_fwXfer);
OPB_hwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_hwXfer,iOPB_hwXfer);
OPB_MGrant <= arb_mgrant;
-- OPB_pendReq is generated by OR'ing all master requests except
-- a master's own request. It indicates to a master that one or
-- more of the other masters attached to the bus is requesting
-- access.
MORE_THAN_ONE_MASTER_GEN: if C_NUM_MASTERS > 1 generate
OPB_pendReq_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
OR_ALL_BUT_SELF_PROCESS: process (M_request) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
or_gate_input(j) <= M_request(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
or_gate_input(j-1) <= M_request(j);
end loop;
end process OR_ALL_BUT_SELF_PROCESS;
OPB_pendReq_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,C_USE_LUT_OR_B)
port map (or_gate_input,OPB_pendReq(i to i));
end generate OPB_pendReq_GEN;
end generate MORE_THAN_ONE_MASTER_GEN;
ONLY_ONE_MASTER_GEN: if C_NUM_MASTERS = 1 generate
OPB_pendReq(0) <= '0';
end generate ONLY_ONE_MASTER_GEN;
OPB_RNW_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_RNW,iOPB_RNW);
OPB_select_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_select,iOPB_select);
OPB_seqAddr_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_seqAddr,iOPB_seqAddr);
OPB_hwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_hwAck,iOPB_hwAck);
OPB_fwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_fwAck,iOPB_fwAck);
OPB_dwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_dwAck,iOPB_dwAck);
OPB_beAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_beAck,iOPB_beAck);
OPB_timeout <= Arb_timeout; -- pass the Timeout through
--------------------------------------------------------------------------------
-- The following signals must be generated conditionally based on the
-- state of C_PROC_INTRFCE
--------------------------------------------------------------------------------
ARBITER_HAS_PROC_INTF: if C_PROC_INTRFCE /= 0 generate
signal sl_plus_arb_dbus : std_logic_vector(0 to ((C_NUM_SLAVES+1)*C_OPB_DWIDTH)-1);
signal sl_plus_arb_errack : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_retry : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_toutsup : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_xferack : std_logic_vector(0 to C_NUM_SLAVES);
begin
sl_plus_arb_dbus <= Sl_DBus & arb_dbus;
sl_plus_arb_errack <= Sl_errAck & arb_errack;
sl_plus_arb_retry <= Sl_retry & arb_retry;
sl_plus_arb_toutsup <= Sl_toutSup & arb_toutsup;
sl_plus_arb_xferack <= Sl_xferAck & arb_xferack;
OPB_toutSup_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_toutsup,iOPB_toutSup);
OPB_xferAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_xferack,iOPB_xferAck);
OPB_retry_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_retry,iOPB_retry);
OPB_errAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_errack,iOPB_errAck);
OPB_rdDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (sl_plus_arb_dbus,iOPB_rdDBus);
end generate ARBITER_HAS_PROC_INTF;
ARBITER_HAS_NO_PROC_INTF: if C_PROC_INTRFCE = 0 generate
begin
OPB_toutSup_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_toutSup,iOPB_toutSup);
OPB_xferAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_xferAck,iOPB_xferAck);
OPB_retry_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_retry,iOPB_retry);
OPB_errAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_errAck,iOPB_errAck);
OPB_rdDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (Sl_DBus,iOPB_rdDBus);
end generate ARBITER_HAS_NO_PROC_INTF;
OPB_beXfer <= iOPB_beXfer(0);
OPB_beAck <= iOPB_beAck(0);
OPB_busLock <= iOPB_busLock(0);
OPB_errAck <= iOPB_errAck(0);
OPB_dwAck <= iOPB_dwAck(0);
OPB_dwXfer <= iOPB_dwXfer(0);
OPB_fwAck <= iOPB_fwAck(0);
OPB_fwXfer <= iOPB_fwXfer(0);
OPB_hwAck <= iOPB_hwAck(0);
OPB_hwXfer <= iOPB_hwXfer(0);
OPB_retry <= iOPB_retry(0);
OPB_RNW <= iOPB_RNW(0);
OPB_select <= iOPB_select(0);
OPB_seqAddr <= iOPB_seqAddr(0);
OPB_toutSup <= iOPB_toutSup(0);
OPB_xferAck <= iOPB_xferAck(0);
OPB_Rst <= iOPB_Rst;
OPB_ABus <= iOPB_ABus;
OPB_BE <= iOPB_BE;
OPB_ARBITER_I : entity opb_v20_v1_10_d.opb_arbiter
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_NUM_MASTERS => C_NUM_MASTERS,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_REG_GRANTS => C_REG_GRANTS,
C_PARK => C_PARK,
C_PROC_INTRFCE => C_PROC_INTRFCE,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE)
port map (
ARB_DBus => arb_dbus,
ARB_ErrAck => arb_errack,
ARB_Retry => arb_retry,
ARB_ToutSup => arb_toutsup,
ARB_XferAck => arb_xferack,
OPB_Clk => OPB_clk,
M_request => M_request,
OPB_Abus => iOPB_ABus,
OPB_BE => iOPB_BE,
OPB_buslock => iOPB_busLock(0),
OPB_Dbus => iOPB_wrDBus,
OPB_MGrant => arb_mgrant,
OPB_retry => iOPB_retry(0),
OPB_RNW => iOPB_rnw(0),
OPB_select => iOPB_select(0),
OPB_seqAddr => iOPB_seqaddr(0),
OPB_timeout => arb_timeout,
OPB_toutSup => iOPB_toutsup(0),
OPB_xferAck => iOPB_xferack(0),
OPB_Rst => iOPB_Rst);
end architecture imp;
| bsd-3-clause | 92e2ff2ce17f6c4c42194fc58d82de5e | 0.496214 | 3.796535 | false | false | false | false |
QuickJack/logi-hard | hdl/control/rgb_32_32_matrix_ctrl.vhd | 2 | 13,650 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:27:28 07/10/2014
-- Design Name:
-- Module Name: rgb_32_32_matrix_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.logi_utils_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb_32_32_matrix_ctrl is
generic(
clk_div : positive := 10;
-- TODO: nb_panels is untested, still need to be validated
nb_panels : positive := 4 ;
bits_per_color : INTEGER RANGE 1 TO 4 := 4 ;
expose_step_cycle: positive := 1910
);
port(
clk, reset : in std_logic ;
pixel_addr : in std_logic_vector((nbit(32*32*nb_panels))-1 downto 0);
pixel_value_out : out std_logic_vector((bits_per_color*3)-1 downto 0);
pixel_value_in : in std_logic_vector((bits_per_color*3)-1 downto 0);
write_pixel : in std_logic ;
SCLK_OUT : out std_logic ;
BLANK_OUT : out std_logic ;
LATCH_OUT : out std_logic ;
A_OUT : out std_logic_vector(3 downto 0);
R_out : out std_logic_vector(1 downto 0);
G_out : out std_logic_vector(1 downto 0);
B_out : out std_logic_vector(1 downto 0)
);
end rgb_32_32_matrix_ctrl;
architecture Behavioral of rgb_32_32_matrix_ctrl is
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
type ctrl_state is (EXPOSE, BLANK, LATCH, UNBLANK, READ, SHIFT1, SHIFT2);
constant LINE_SIZE : positive := 32*nb_panels ;
constant RAM_SIZE : positive := LINE_SIZE*32 ;
constant BOTTOM_ADDRESS_OFFSET : positive := LINE_SIZE * 16 ;
signal cur_state, next_state : ctrl_state ;
signal next_pixel_div, bin_code_delay, exposure_time : std_logic_vector(15 downto 0);
signal end_count : std_logic ;
signal col_count : std_logic_vector(nbit(LINE_SIZE)-1 downto 0);
signal line_count : std_logic_vector(3 downto 0);
signal clk_count, count_load_val : std_logic_vector(15 downto 0) ;
signal rd_bit, exp_bit : std_logic_vector(1 downto 0);
signal pixel_read_addr, line_base_addr : std_logic_vector(nbit(RAM_SIZE/2)-1 downto 0);
signal line_count_enable, col_count_enable, rd_bit_count_enable : std_logic ;
signal line_count_reset, col_count_reset : std_logic ;
signal pixel_data_line0, pixel_data_line16 : std_logic_vector((bits_per_color*3)-1 downto 0);
signal pixel_data_line16_extended, pixel_data_line0_extended : std_logic_vector(15 downto 0) ;
signal end_of_col, end_of_bits : std_logic ;
signal shift_count : std_logic_vector(3 downto 0);
signal end_of_exposure, load_exposure, load_count : std_logic ;
signal SCLK_Q, LATCH_Q, BLANK_Q : std_logic ;
signal R1_Q, G1_Q, B1_Q, R0_Q, G0_Q, B0_Q : std_logic ;
signal A_OUT_Q : std_logic_vector(3 downto 0);
signal pixel_write_addr_line0, pixel_write_addr_line16 : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0);
signal pixel_write_addr : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0);
signal pixel_value_out_0, pixel_value_out_1 : std_logic_vector((bits_per_color*3)-1 downto 0);
signal write_mem0, write_mem1 : std_logic ;
begin
-- ram buffer instanciation
pixel_write_addr <= pixel_addr ;
pixel_write_addr_line0 <= pixel_write_addr ;
--when pixel_write_addr < ((32*nb_panels)*16) else
--(others => '0');
pixel_write_addr_line16 <= pixel_write_addr - BOTTOM_ADDRESS_OFFSET ;
--when pixel_write_addr >= (32*nb_panels)*16 else
--(others => '0'); -- only for simulation purpose ...
write_mem0 <= write_pixel when pixel_write_addr < BOTTOM_ADDRESS_OFFSET else
'0' ;
pixel_value_out <= pixel_value_out_0 when pixel_addr < BOTTOM_ADDRESS_OFFSET else
pixel_value_out_1 ;
frame_buffer0 : dpram_NxN
generic map(SIZE => RAM_SIZE/2, NBIT => bits_per_color*3, ADDR_WIDTH => nbit(RAM_SIZE/2))
port map(
clk => clk,
we => write_mem0,
di => pixel_value_in,
a => pixel_write_addr_line0(nbit(RAM_SIZE/2)-1 downto 0) ,
dpra => pixel_read_addr,
spo => pixel_value_out_0,
dpo => pixel_data_line0
);
pixel_data_line0_extended((bits_per_color*3)-1 downto 0) <= pixel_data_line0 ;
pixel_data_line0_extended(15 downto (bits_per_color*3)) <= (others => '0') ;
write_mem1 <= write_pixel when pixel_write_addr >= BOTTOM_ADDRESS_OFFSET else
'0' ;
frame_buffer1 : dpram_NxN
generic map(SIZE => RAM_SIZE/2, NBIT => bits_per_color*3, ADDR_WIDTH => nbit(RAM_SIZE/2))
port map(
clk => clk,
we => write_mem1,
di => pixel_value_in,
a => pixel_write_addr_line16(nbit(RAM_SIZE/2)-1 downto 0) ,
dpra => pixel_read_addr,
spo => pixel_value_out_1,
dpo => pixel_data_line16
);
pixel_data_line16_extended((bits_per_color*3)-1 downto 0) <= pixel_data_line16 ;
pixel_data_line16_extended(15 downto (bits_per_color*3)) <= (others => '0') ;
-- ram buffer read address decoding
pixel_read_addr <= line_base_addr + std_logic_vector(resize(unsigned(col_count), pixel_read_addr'LENGTH)) ;
-- state machine code
-- state machine latch state process
process(clk, reset)
begin
if reset = '1' then
cur_state <= EXPOSE ;
elsif rising_edge(clk) then
cur_state <= next_state ;
end if;
end process;
-- state machine, state evolution process
process(cur_state, end_count, col_count, end_of_col, end_of_exposure)
begin
next_state <= cur_state ;
case cur_state is
when EXPOSE =>
if end_of_exposure = '1' then
next_state <= BLANK ;
end if ;
when BLANK =>
if end_count = '1' then
next_state <= LATCH ;
end if ;
when LATCH =>
if end_count = '1' then
next_state <= UNBLANK ;
end if ;
when UNBLANK =>
if end_count = '1' then
next_state <= SHIFT1 ;
end if ;
when SHIFT1 =>
if end_count = '1' then
next_state <= SHIFT2 ;
end if ;
when SHIFT2 =>
if end_of_col = '1' and end_count = '1' then
next_state <= EXPOSE ;
elsif end_count = '1' then
next_state <= SHIFT1 ;
end if ;
when others =>
next_state <= EXPOSE ;
end case ;
end process;
-- internal signals management
-- clk_count is used to generate the time interval between states
-- it is also used to generate the output clock frequency
process(clk, reset)
begin
if reset = '1' then
clk_count <= (others => '0');
elsif rising_edge(clk) then
if load_count = '1' then
clk_count <= count_load_val ;
else
clk_count <= clk_count - 1 ;
end if ;
end if;
end process;
-- helper signal to simplify equations
end_count <= '1' when clk_count = 0 else
'0' ;
load_count <= '1' when cur_state = EXPOSE else
end_count;
-- value to in interval counter, value to load is computed for next state
with cur_state select
count_load_val <= std_logic_vector(to_unsigned((clk_div*8)-1, 16) ) when EXPOSE,
std_logic_vector(to_unsigned((clk_div*8)-1, 16) ) when BLANK,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when LATCH,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when UNBLANK,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when SHIFT1,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when SHIFT2,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when others;
-- counter for exposure time
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
exposure_time <= bin_code_delay;
elsif load_exposure = '1' then
exposure_time <= bin_code_delay ;
elsif exposure_time > 0 then
exposure_time <= exposure_time - 1 ;
end if ;
end if;
end process;
end_of_exposure <= '1' when exposure_time = 0 else
'0' ;
load_exposure <= '1' when cur_state = LATCH else
'0' ;
-- column counter, is incremented on each falling edge of sclk
process(clk, reset)
begin
if reset = '1' then
col_count <= (others => '0') ;
elsif rising_edge(clk) then
if col_count_reset = '1' then
col_count <= (others => '0') ;
elsif col_count_enable = '1' and col_count < (LINE_SIZE-1) then
col_count <= col_count + 1 ;
end if ;
end if;
end process;
-- helper signal to simplify equations
end_of_col <= '1' when col_count = (LINE_SIZE-1) else
'0' ;
-- the column count is reseted on end of blank
with cur_state select
col_count_reset <= '0' when SHIFT1,
'0' when SHIFT2,
end_count when UNBLANK,
'0' when others;
-- column are counted when shifintg the pixel data
with cur_state select
col_count_enable <= end_count when SHIFT2,
'0' when others ;
-- line counter, specify the line to read from memory
process(clk, reset)
begin
if reset = '1' then
line_count <= (others => '0') ;
line_base_addr <= (others => '0') ;
elsif rising_edge(clk) then
if line_count_reset = '1' then
line_count <= (others => '0') ;
line_base_addr <= (others => '0') ;
elsif line_count_enable = '1' then
line_count <= line_count + 1 ;
line_base_addr <= line_base_addr + LINE_SIZE ;
end if ;
end if;
end process;
-- increment line counter after blanking
with cur_state select
line_count_enable <= (end_count and end_of_bits) when LATCH,
'0' when others ;
line_count_reset <= '1' when line_count_enable = '1' and line_count = 15 else
'0' ;
-- rd_bit specify the bit to read from the color code
-- exp bit specify the bit being exposed on the matrix
process(clk, reset)
begin
if reset = '1' then
rd_bit <= (others => '0') ;
--exp_bit <= (others => '0') ;
elsif rising_edge(clk) then
if end_of_bits = '1' and rd_bit_count_enable = '1' then
rd_bit <= (others => '0') ;
--exp_bit <= rd_bit ;
elsif rd_bit_count_enable = '1' then
rd_bit <= rd_bit + 1 ;
--exp_bit <= rd_bit ;
end if ;
end if;
end process;
with cur_state select
rd_bit_count_enable <= (end_count) when LATCH,
'0' when others ;
-- helper signals to simplify equations
end_of_bits <= '1' when rd_bit = bits_per_color-1 else
'0' ;
-- The binary coded modulation delay is doubled for each exposed color bit
with conv_integer(rd_bit) select
bin_code_delay <= std_logic_vector(to_unsigned(expose_step_cycle, 16)) when 3,
std_logic_vector(to_unsigned(expose_step_cycle*2, 16)) when 2,
std_logic_vector(to_unsigned(expose_step_cycle*4, 16)) when 1,
std_logic_vector(to_unsigned(expose_step_cycle*8, 16)) when others ;
-- output management
-- the output are combinatorial but latched to avoid glitches
with cur_state select
SCLK_q <= '0' when SHIFT1,
'1' when SHIFT2,
'0' when others ;
with cur_state select
BLANK_q <= '1' when BLANK,
'1' when LATCH,
'0' when others ;
with cur_state select
LATCH_q <= '1' when LATCH,
'0' when others ;
with conv_integer(rd_bit) select
R0_q <= pixel_data_line0_extended(8) when 3,
pixel_data_line0_extended(9) when 2,
pixel_data_line0_extended(10) when 1,
pixel_data_line0_extended(11) when others;
with conv_integer(rd_bit) select
G0_q <= pixel_data_line0_extended(4) when 3,
pixel_data_line0_extended(5) when 2,
pixel_data_line0_extended(6) when 1,
pixel_data_line0_extended(7) when others;
with conv_integer(rd_bit) select
B0_q <= pixel_data_line0_extended(0) when 3,
pixel_data_line0_extended(1) when 2,
pixel_data_line0_extended(2) when 1,
pixel_data_line0_extended(3) when others;
with conv_integer(rd_bit) select
R1_q <= pixel_data_line16_extended(8) when 3,
pixel_data_line16_extended(9) when 2,
pixel_data_line16_extended(10) when 1,
pixel_data_line16_extended(11) when others;
with conv_integer(rd_bit) select
G1_q <= pixel_data_line16_extended(4) when 3,
pixel_data_line16_extended(5) when 2,
pixel_data_line16_extended(6) when 1,
pixel_data_line16_extended(7) when others;
with conv_integer(rd_bit) select
B1_q <= pixel_data_line16_extended(0) when 3,
pixel_data_line16_extended(1) when 2,
pixel_data_line16_extended(2) when 1,
pixel_data_line16_extended(3) when others;
-- the address to be output to the matrix is a delayed version of the
-- line being read from memory. We expose one line, while we are loading the values
-- for the next
process(clk, reset)
begin
if reset = '1' then
A_OUT_Q <= (others => '0');
elsif rising_edge(clk) then
if cur_state = BLANK and end_count = '1' then
A_OUT_Q <= line_count ;
end if ;
end if;
end process;
-- all output are latched to prevent glitches
process(clk, reset)
begin
if rising_edge(clk) then
SCLK_OUT <= SCLK_q ;
LATCH_OUT <= LATCH_q ;
BLANK_OUT <= BLANK_q ;
R_OUT(0) <= R0_q ;
R_OUT(1) <= R1_q ;
G_OUT(0) <= G0_q ;
G_OUT(1) <= G1_q ;
B_OUT(0) <= B0_q ;
B_OUT(1) <= B1_q ;
A_OUT <= A_OUT_Q ;
end if;
end process;
end Behavioral;
| lgpl-3.0 | 63bb0f08a342fa0a18f18e64a4024963 | 0.637949 | 2.962883 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_ipif.vhd | 2 | 12,913 | -- $Id: opb_ipif.vhd,v 1.2 2004/05/05 23:12:12 gburch Exp $
-------------------------------------------------------------------------------
-- opb_ipif.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ipif.vhd
--
-- Description: Simple slave OPB IPIF, OPB to IPIC.
--
--
-------------------------------------------------------------------------------
-- Structure: opb_ipif
-- opb_ipif
-- -- opb_bam
-- -- reset_mir
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Gm_SP2
--
-- Fixed problem with double clock wrce to interrupt control which caused
-- an interrupt to be generated when a user cleared an already pending
-- interrupt.
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
--
-- FLO 05/19/03
-- ^^^^^^
-- Initial version.
-- ~~~~~~
-- GAB 05/05/04
-- ^^^^^^
-- Added change log.
-- Fixed interrupt control double clock wrce
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.INTEGER_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.calc_num_ce;
use ipif_common_v1_00_c.ipif_pkg.calc_start_ce_index;
use ipif_common_v1_00_c.ipif_pkg.DEPENDENT_PROPS_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.get_min_dwidth;
use ipif_common_v1_00_c.ipif_pkg.IPIF_INTR;
use ipif_common_v1_00_c.ipif_pkg.IPIF_RST;
use ipif_common_v1_00_c.ipif_pkg.USER_00;
library opb_ipif_v3_00_a;
use opb_ipif_v3_00_a.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_ipif is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => IPIF_INTR, 1 => IPIF_RST, 2 => USER_00 );
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( x"0000_0000_6000_0000", x"0000_0000_6000_003F", x"0000_0000_6000_0040", x"0000_0000_6000_0043", x"0000_0000_6000_0100", x"0000_0000_6000_01FF" );
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := ( 32, 32, 32 );
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 16, 1, 8 );
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := ( 0 => (others => 0) ,1 => (others => 0) ,2 => (others => 0) );
C_PIPELINE_MODEL : integer := 7;
C_DEV_BLK_ID : INTEGER := 1;
C_DEV_MIR_ENABLE : INTEGER := 0;
C_AWIDTH : INTEGER := 32;
C_DWIDTH : INTEGER := 32;
C_FAMILY : string := "virtexe";
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
C_INCLUDE_DEV_ISC : INTEGER := 1;
C_INCLUDE_DEV_IID : integer := 0;
C_DEV_BURST_ENABLE : INTEGER := 0
);
port
(
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
OPB_xferAck : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_DWIDTH*calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
IP2Bus_Ack : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Error : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Retry : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_ToutSup : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Intr : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
Device_Intr : out std_logic
);
end entity opb_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of opb_ipif is
component opb_bam is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => IPIF_INTR, 1 => IPIF_RST, 2 => USER_00 );
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( x"0000_0000_6000_0000", x"0000_0000_6000_003F", x"0000_0000_6000_0040", x"0000_0000_6000_0043", x"0000_0000_6000_0100", x"0000_0000_6000_01FF" );
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := ( 32, 32, 32 );
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 16, 1, 8 );
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := ( 0 => (others => 0) ,1 => (others => 0) ,2 => (others => 0) );
C_PIPELINE_MODEL : integer := 7;
C_DEV_BLK_ID : INTEGER := 1;
C_DEV_MIR_ENABLE : INTEGER := 0;
C_AWIDTH : INTEGER := 32;
C_DWIDTH : INTEGER := 32;
C_FAMILY : string := "virtexe";
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
C_INCLUDE_DEV_ISC : INTEGER := 1;
C_INCLUDE_DEV_IID : integer := 0;
C_DEV_BURST_ENABLE : INTEGER := 0
);
port
(
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
OPB_xferAck : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_DWIDTH*calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
IP2Bus_Ack : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Error : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Retry : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_ToutSup : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Intr : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
Device_Intr : out std_logic
);
end component opb_bam;
begin ------------------------------------------------------------------------
OPB_BAM_I : opb_bam
generic map
(
C_ARD_ID_ARRAY => C_ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => C_ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => C_ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => C_PIPELINE_MODEL,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_ISC => C_INCLUDE_DEV_ISC,
C_INCLUDE_DEV_IID => C_INCLUDE_DEV_IID,
C_DEV_BURST_ENABLE => C_DEV_BURST_ENABLE
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_xferAck => OPB_xferAck,
Sln_DBus => Sln_DBus,
Sln_xferAck => Sln_xferAck,
Sln_errAck => Sln_errAck,
Sln_retry => Sln_retry,
Sln_toutSup => Sln_toutSup,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_CE => Bus2IP_CE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_Burst => Bus2IP_Burst,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_Ack => IP2Bus_Ack,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Retry => IP2Bus_Retry,
IP2Bus_ToutSup => IP2Bus_ToutSup,
IP2Bus_PostedWrInh => IP2Bus_PostedWrInh,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => Bus2IP_Clk,
IP2Bus_Clk => IP2Bus_Clk,
Reset => Reset,
Bus2IP_Reset => Bus2IP_Reset,
IP2Bus_Intr => IP2Bus_Intr,
Device_Intr => Device_Intr
);
end architecture imp;
| bsd-3-clause | 4467ff939b0706b923da49eefffa0c5a | 0.44885 | 3.526215 | false | false | false | false |
pdaxrom/p601zero | cpu11.vhd | 1 | 158,088 | --===========================================================================--
--
-- S Y N T H E Z I A B L E cpu11 - HC11 compatible CPU core
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : cpu11.vhd
--
-- Entity name : cpu11
--
-- Purpose : HC11 instruction set compatible CPU core
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Uses : Nothing
--
-- Author : John Kent - [email protected]
--
-------------------------------------------------------------------------------
-- Revision list
--
-- Version 0.1 - 13 November 2002 - John Kent
-- revamped 6801 CPU into 68HC11 CPU.
-- Added Y index register
-- Added Y indexing prebyte
-- Added CMPD with prebyte
-- Added bit operators
-- Updated stack operations
--
-- Version 0.3 - 15 December 2002 - John Kent
-- implemented FDIV
-- implemented IDIV
--
-- Version 1.0 - 7 September 2003 - John Kent
-- Released to Open Cores
-- Basic 6800 instructions working
-- but not Divide and bit operations.
--
-- Version 1.1 - 4 April 2004
-- Removed Test_alu and Test_cc signals
-- Moved Dual operand execution into fetch state
-- Fixed Indexed bit operators
--
-- Added by sashz (11 Jul 2017):
-- 13 Jan 2004 1.1 John Kent
-- As Reported by Michael Hasenfratz CLR did not clear the carry bit.
-- this is because the state sequencer enumerated the ALU with "alu_ld8"
-- rather than "alu_clr". I've also moved the "alu_clr" to the "alu_clc"
-- decode which clears the carry. It should not be necessary, but is a
-- more obvious way of doing things.
--
-- Added by sashz (15 Jul 2017):
-- Fixed mistyped prefix for page4 indexed state
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu11 is
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic;
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
xirq: in std_logic;
irq_ext3: in std_logic;
irq_ext2: in std_logic;
irq_ext1: in std_logic;
irq_ext0: in std_logic
);
end;
architecture CPU_ARCH of cpu11 is
constant SBIT : integer := 7;
constant XBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
type state_type is (reset_state, fetch_state, decode_state,
extended_state, indexed_state, read8_state, read16_state, immediate16_state,
write8_state, write16_state,
execute_state, halt_state, spin_state,
exchange_state,
mul_state, mulea_state, muld_state, mul0_state,
idiv_state,
div1_state, div2_state, div3_state, div4_state, div5_state,
jmp_state, jsr_state, jsr1_state,
branch_state, bsr_state, bsr1_state,
bitmask_state, brset_state, brclr_state,
rts_hi_state, rts_lo_state,
int_pcl_state, int_pch_state,
int_ixl_state, int_ixh_state,
int_iyl_state, int_iyh_state,
int_cc_state, int_acca_state, int_accb_state,
int_wai_state, int_maski_state, int_maskx_state,
rti_state, rti_cc_state, rti_acca_state, rti_accb_state,
rti_ixl_state, rti_ixh_state,
rti_iyl_state, rti_iyh_state,
rti_pcl_state, rti_pch_state,
pula_state, psha_state, pulb_state, pshb_state,
pulxy_lo_state, pulxy_hi_state, pshxy_lo_state, pshxy_hi_state,
vect_lo_state, vect_hi_state );
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad );
type dout_type is ( acca_dout, accb_dout, cc_dout,
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
md_lo_dout, md_hi_dout, pc_lo_dout, pc_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type pre_type is (reset_pre, fetch_pre, latch_pre );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
type sp_type is (reset_sp, latch_sp, load_sp );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea, add_ix_ea, add_iy_ea );
type iv_type is (reset_iv, latch_iv, swi_iv, xirq_iv, irq_iv, ext3_iv, ext2_iv, ext1_iv, ext0_iv );
type count_type is (reset_count, latch_count, inc_count );
type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, iy_left, pc_left, sp_left, ea_left );
type right_type is (md_right, zero_right, one_right, accb_right, pre_right, ea_right, sexea_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_inc16, alu_dec16,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8, alu_rol16,
alu_asr8, alu_asl8, alu_lsr8,
alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv,
alu_sex, alu_clx, alu_tpa, alu_tap,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa,
alu_bset, alu_bclr );
signal op_code: std_logic_vector(7 downto 0);
signal pre_byte: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal yreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(2 downto 0);
signal ea_bit: std_logic;
signal count: std_logic_vector(4 downto 0);
signal state: state_type;
signal next_state: state_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal pre_ctrl: pre_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal iy_ctrl: iy_type;
signal cc_ctrl: cc_type;
signal sp_ctrl: sp_type;
signal iv_ctrl: iv_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
signal count_ctrl: count_type;
begin
--------------------------------
--
-- Accumulator A
--
--------------------------------
acca_reg : process( clk, acca_ctrl, out_alu, acca, data_in )
begin
if clk'event and clk = '0' then
case acca_ctrl is
when reset_acca =>
acca <= "00000000";
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others =>
-- when latch_acca =>
acca <= acca;
end case;
end if;
end process;
--------------------------------
--
-- Accumulator B
--
--------------------------------
accb_reg : process( clk, accb_ctrl, out_alu, accb, data_in )
begin
if clk'event and clk = '0' then
case accb_ctrl is
when reset_accb =>
accb <= "00000000";
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others =>
-- when latch_accb =>
accb <= accb;
end case;
end if;
end process;
----------------------------------
--
-- Condition Codes
--
----------------------------------
cc_reg: process( clk, cc_ctrl, cc_out, cc, data_in )
begin
if clk'event and clk = '0' then
case cc_ctrl is
when reset_cc =>
cc <= "11000000";
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
-- when latch_cc =>
cc <= cc;
end case;
end if;
end process;
--------------------------------
--
-- X Index register
--
--------------------------------
ix_reg : process( clk, ix_ctrl, out_alu, xreg, data_in )
begin
if clk'event and clk = '0' then
case ix_ctrl is
when reset_ix =>
xreg <= "0000000000000000";
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
-- when latch_ix =>
xreg <= xreg;
end case;
end if;
end process;
--------------------------------
--
-- Y Index register
--
--------------------------------
iy_reg : process( clk, iy_ctrl, out_alu, yreg, data_in )
begin
if clk'event and clk = '0' then
case iy_ctrl is
when reset_iy =>
yreg <= "0000000000000000";
when load_iy =>
yreg <= out_alu(15 downto 0);
when pull_hi_iy =>
yreg(15 downto 8) <= data_in;
when pull_lo_iy =>
yreg(7 downto 0) <= data_in;
when others =>
-- when latch_iy =>
yreg <= yreg;
end case;
end if;
end process;
--------------------------------
--
-- stack pointer
--
--------------------------------
sp_reg : process( clk, sp_ctrl, out_alu )
begin
if clk'event and clk = '0' then
case sp_ctrl is
when reset_sp =>
sp <= "0000000000000000";
when load_sp =>
sp <= out_alu(15 downto 0);
when others =>
-- when latch_sp =>
sp <= sp;
end case;
end if;
end process;
----------------------------------
--
-- Program Counter Control
--
----------------------------------
pc_reg: process( clk, pc_ctrl, pc, out_alu, data_in )
begin
if clk'event and clk = '0' then
case pc_ctrl is
when reset_pc =>
pc <= "0000000000000000";
when incr_pc =>
pc <= pc + "0000000000000001";
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when others =>
-- when latch_pc =>
pc <= pc;
end case;
end if;
end process;
----------------------------------
--
-- Effective Address Control
--
----------------------------------
ea_reg: process( clk, ea_ctrl, ea, out_alu, data_in, xreg, yreg )
begin
if clk'event and clk = '0' then
case ea_ctrl is
when reset_ea =>
ea <= "0000000000000000";
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= "00000000";
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when add_ix_ea =>
ea <= ea + xreg;
when add_iy_ea =>
ea <= ea + yreg;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
-- when latch_ea =>
ea <= ea;
end case;
end if;
end process;
--------------------------------
--
-- Memory Data
--
--------------------------------
md_reg : process( clk, md_ctrl, out_alu, data_in, md )
begin
if clk'event and clk = '0' then
case md_ctrl is
when reset_md =>
md <= "0000000000000000";
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md =>
md(15 downto 8) <= "00000000";
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
-- when latch_md =>
md <= md;
end case;
end if;
end process;
----------------------------------
--
-- interrupt vector
--
----------------------------------
iv_reg: process( clk, iv_ctrl )
begin
if clk'event and clk = '0' then
case iv_ctrl is
when reset_iv =>
iv <= "111";
when xirq_iv =>
iv <= "110";
when swi_iv =>
iv <= "101";
when irq_iv =>
iv <= "100";
when ext3_iv =>
iv <= "011";
when ext2_iv =>
iv <= "010";
when ext1_iv =>
iv <= "001";
when ext0_iv =>
iv <= "000";
when others =>
iv <= iv;
end case;
end if;
end process;
----------------------------------
--
-- op code register
--
----------------------------------
op_reg: process( clk, data_in, op_ctrl, op_code )
begin
if clk'event and clk = '0' then
case op_ctrl is
when reset_op =>
op_code <= "00000001"; -- nop
when fetch_op =>
op_code <= data_in;
when others =>
-- when latch_op =>
op_code <= op_code;
end case;
end if;
end process;
----------------------------------
--
-- pre byte register
--
----------------------------------
pre_reg: process( clk, pre_ctrl, data_in, pre_byte )
begin
if clk'event and clk = '0' then
case pre_ctrl is
when reset_pre =>
pre_byte <= "00000000";
when fetch_pre =>
pre_byte <= data_in;
when others =>
-- when latch_op =>
pre_byte <= pre_byte;
end case;
end if;
end process;
----------------------------------
--
-- counter
--
----------------------------------
count_reg: process( clk, count_ctrl, count )
begin
if clk'event and clk = '0' then
case count_ctrl is
when reset_count =>
count <= "00000";
when inc_count =>
count <= count + "00001";
when others =>
-- when latch_count =>
count <= count;
end case;
end if;
end process;
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv )
begin
case addr_ctrl is
when idle_ad =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
when fetch_ad =>
address <= pc;
vma <= '1';
rw <= '1';
when read_ad =>
address <= ea;
vma <= '1';
rw <= '1';
when write_ad =>
address <= ea;
vma <= '1';
rw <= '0';
when push_ad =>
address <= sp;
vma <= '1';
rw <= '0';
when pull_ad =>
address <= sp;
vma <= '1';
rw <= '1';
when int_hi_ad =>
address <= "111111111111" & iv & "0";
vma <= '1';
rw <= '1';
when int_lo_ad =>
address <= "111111111111" & iv & "1";
vma <= '1';
rw <= '1';
when others =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
end case;
end process;
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, yreg, pc, cc )
begin
case dout_ctrl is
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when cc_dout => -- condition codes
data_out <= cc;
when ix_lo_dout => -- X index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- X index reg
data_out <= xreg(15 downto 8);
when iy_lo_dout => -- Y index reg
data_out <= yreg(7 downto 0);
when iy_hi_dout => -- Y index reg
data_out <= yreg(15 downto 8);
when md_lo_dout => -- memory data (ALU)
data_out <= md(7 downto 0);
when md_hi_dout => -- memory data (ALU)
data_out <= md(15 downto 8);
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
when others =>
data_out <= "00000000";
end case;
end process;
----------------------------------
--
-- ea bit mutiplexer (used by multiply)
--
----------------------------------
ea_bit_mux: process( count, ea )
begin
case count(3 downto 0) is
when "0000" =>
ea_bit <= ea(0);
when "0001" =>
ea_bit <= ea(1);
when "0010" =>
ea_bit <= ea(2);
when "0011" =>
ea_bit <= ea(3);
when "0100" =>
ea_bit <= ea(4);
when "0101" =>
ea_bit <= ea(5);
when "0110" =>
ea_bit <= ea(6);
when "0111" =>
ea_bit <= ea(7);
when "1000" =>
ea_bit <= ea(8);
when "1001" =>
ea_bit <= ea(9);
when "1010" =>
ea_bit <= ea(10);
when "1011" =>
ea_bit <= ea(11);
when "1100" =>
ea_bit <= ea(12);
when "1101" =>
ea_bit <= ea(13);
when "1110" =>
ea_bit <= ea(14);
when "1111" =>
ea_bit <= ea(15);
when others =>
null;
end case;
end process;
----------------------------------
--
-- Left Mux
--
----------------------------------
left_mux: process( left_ctrl, acca, accb, xreg, yreg, sp, pc, ea, md )
begin
case left_ctrl is
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when iy_left =>
left <= yreg;
when sp_left =>
left <= sp;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
right_mux: process( right_ctrl, data_in, md, accb, pre_byte, ea )
begin
case right_ctrl is
when zero_right =>
right <= "0000000000000000";
when one_right =>
right <= "0000000000000001";
when accb_right =>
right <= "00000000" & accb; -- for abx / aby instructions
when pre_right =>
right <= "00000000" & pre_byte; -- prebyte register doubles as bit mask
when ea_right =>
right <= ea;
when sexea_right =>
if ea(7) = '0' then
right <= "00000000" & ea(7 downto 0);
else
right <= "11111111" & ea(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
alu_logic: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 | alu_rol16 =>
carry_in := cc(CBIT);
when others =>
carry_in := '0';
end case;
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
if (cc(CBIT) = '0') then
if( cc(HBIT) = '1' ) then
if valid_hi then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
else
if valid_lo then
if valid_hi then
daa_reg := "00000000";
else
daa_reg := "01100000";
end if;
else
if( left(7 downto 4) <= 8 ) then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
end if;
end if;
else
if ( cc(HBIT) = '1' )then
daa_reg := "01100110";
else
if valid_lo then
daa_reg := "01100000";
else
daa_reg := "01100110";
end if;
end if;
end if;
case alu_ctrl is
when alu_add8 | alu_adc | alu_inc |
alu_add16 | alu_inc16 =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_sbc | alu_dec |
alu_sub16 | alu_dec16 =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_bclr =>
out_alu <= left and (not right); -- bclr
when alu_ora | alu_bset =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 | alu_rol16 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/rol16/asl8/lsl16
when alu_lsr16 | alu_lsr8 =>
out_alu <= carry_in & left(15 downto 1); -- lsr
when alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror
when alu_asr8 =>
out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_tpa =>
out_alu <= "00000000" & cc;
when others =>
out_alu <= left; -- nop
end case;
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 | alu_rol16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_sec =>
cc_out(CBIT) <= '1';
when alu_clc =>
cc_out(CBIT) <= '0';
when alu_tap =>
cc_out(CBIT) <= left(CBIT);
when others => -- carry is not affected by cpx
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 |
alu_bset | alu_bclr =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_inc16 | alu_dec16 |
alu_ld16 | alu_st16 =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_tap =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 |
alu_bset | alu_bclr =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 =>
cc_out(NBIT) <= out_alu(15);
when alu_tap =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_sei =>
cc_out(IBIT) <= '1'; -- set interrupt mask
when alu_cli =>
cc_out(IBIT) <= '0'; -- clear interrupt mask
when alu_tap =>
cc_out(IBIT) <= left(IBIT);
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_tap =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
when alu_asr8 =>
cc_out(VBIT) <= left(0) xor left(7);
when alu_lsr8 | alu_lsr16 =>
cc_out(VBIT) <= left(0);
when alu_ror8 =>
cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
when alu_tap =>
cc_out(VBIT) <= left(VBIT);
when alu_and | alu_ora | alu_eor | alu_com |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 |
alu_bset | alu_bclr |
alu_clv =>
cc_out(VBIT) <= '0';
when alu_sev =>
cc_out(VBIT) <= '1';
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
case alu_ctrl is
when alu_sex =>
cc_out(XBIT) <= '1'; -- set interrupt mask
when alu_clx =>
cc_out(XBIT) <= '0'; -- clear interrupt mask
when alu_tap =>
cc_out(XBIT) <= cc(XBIT) and left(XBIT);
when others =>
cc_out(XBIT) <= cc(XBIT) and left(XBIT);
end case;
case alu_ctrl is
when alu_tap =>
cc_out(SBIT) <= left(SBIT);
when others =>
cc_out(SBIT) <= cc(SBIT);
end case;
end process;
------------------------------------
--
-- state sequencer
--
------------------------------------
state_logic: process( state, op_code, pre_byte, cc, ea, md, irq, xirq,
irq_ext3, irq_ext2, irq_ext1, irq_ext0, ea_bit, count )
begin
case state is
when reset_state => -- released from reset
-- reset the registers
op_ctrl <= reset_op;
pre_ctrl <= reset_pre;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
ix_ctrl <= reset_ix;
iy_ctrl <= reset_iy;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
iv_ctrl <= reset_iv;
sp_ctrl <= reset_sp;
count_ctrl <= reset_count;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= reset_cc;
-- idle the bus
dout_ctrl <= md_lo_dout;
addr_ctrl <= idle_ad;
next_state <= vect_hi_state;
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- default the registers
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
dout_ctrl <= pc_hi_dout;
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- default the registers
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
--
-- Here to fetch an instruction
-- PC points to opcode
-- Should service interrupt requests at this point
-- either from the timer
-- or from the external input.
--
when fetch_state =>
case op_code(7 downto 4) is
when "0000" | -- inherent operators
"0001" | -- bit operators come here
"0010" | -- branch conditional
"0011" | -- stack operators
"0100" | -- acca single operand
"0101" | -- accb single operand
"0110" | -- indexed single op
"0111" => -- extended single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
when "1000" | -- acca immediate
"1001" | -- acca direct
"1010" | -- acca indexed
"1011" => -- acca extended
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0011" => -- subd / cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
if (pre_byte = "00011010") or (pre_byte = "11001101") then
-- CPD
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
else
-- SUBD
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end if;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1100" => -- cpx / cpy
if (pre_byte = "00011000") or (pre_byte = "00011010") then
-- cpy
left_ctrl <= iy_left;
else
-- cpx
left_ctrl <= ix_left;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1101" => -- bsr / jsr
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1110" => -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
when "1111" => -- sts / xgdx / xgdy
if op_code(7 downto 4) = "1000" then
--
-- exchange registers
-- at this point md holds accd
-- accd holds either X or Y
-- now transfer md to X or Y
--
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
else
-- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
end if;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
end case;
when "1100" | -- accb immediate
"1101" | -- accb direct
"1110" | -- accb indexed
"1111" => -- accb extended
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when "1110" => -- ldx / ldy
if ((pre_byte = "00011000") or (pre_byte = "00011010")) then
-- LDY
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
-- LDX
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
when "1111" => -- stx / sty
if ((pre_byte = "00011000") or (pre_byte = "00011010")) then
-- STY
left_ctrl <= iy_left;
else
-- STX
left_ctrl <= ix_left;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
end case;
ea_ctrl <= reset_ea;
md_ctrl <= latch_md;
count_ctrl <= reset_count;
-- fetch the op code
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
iv_ctrl <= latch_iv;
-- service non maskable interrupts
if (xirq = '1') and (cc(XBIT) = '0') then
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
-- service maskable interrupts
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
else
-- Advance the PC to fetch next instruction byte
pc_ctrl <= incr_pc;
next_state <= decode_state;
end if;
end if;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode_state =>
-- fetch first byte of address or immediate data
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
pre_ctrl <= latch_pre;
case op_code(7 downto 4) is
when "0000" =>
md_ctrl <= reset_md;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
op_ctrl <= latch_op;
case op_code(3 downto 0) is
when "0000" => -- test -- spin PC
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= reset_ea;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
next_state <= spin_state;
when "0001" => -- nop
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= reset_ea;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
next_state <= fetch_state;
when "0010" => -- idiv
-- transfer IX to ea
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
next_state <= idiv_state;
when "0011" => -- fdiv
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= reset_ix;
iy_ctrl <= latch_iy;
next_state <= div1_state;
when "0100" => -- lsrd
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "0101" => -- lsld
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsl16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "0110" => -- tap
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tap;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "0111" => -- tpa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tpa;
cc_ctrl <= latch_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1000" => -- inx / iny
if pre_byte = "00011000" then
-- iny
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
-- inx
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
ea_ctrl <= reset_ea;
right_ctrl <= one_right;
alu_ctrl <= alu_inc16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
next_state <= fetch_state;
when "1001" => -- dex / dey
if pre_byte = "00011000" then
-- dey
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
-- dex
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
ea_ctrl <= reset_ea;
right_ctrl <= one_right;
alu_ctrl <= alu_dec16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
next_state <= fetch_state;
when "1010" => -- clv
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clv;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1011" => -- sev
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sev;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1100" => -- clc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1101" => -- sec
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sec;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1110" => -- cli
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_cli;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1111" => -- sei
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
end case;
-- acca / accb inherent instructions
when "0001" =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
case op_code(3 downto 0) is
when "0000" => -- sba
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "0001" => -- cba
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "0010" => -- brset direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= read8_state;
when "0011" => -- brclr direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= read8_state;
when "0100" => -- bset direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= read8_state;
when "0101" => -- bclr direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= read8_state;
when "0110" => -- tab
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "0111" => -- tba
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1000" => -- indexed y prebyte
op_ctrl <= fetch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= decode_state;
when "1001" => -- daa
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1010" => -- prebyte - CPD / CPY / LDY / STY ff,X
op_ctrl <= fetch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= decode_state;
when "1011" => -- aba
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1100" => -- bset indexed
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when "1101" => -- bclr indexed
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when "1110" => -- brset indexed
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when "1111" => -- brclr indexed
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when others =>
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
when "0010" => -- branch conditional
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0000" => -- bra
next_state <= branch_state;
when "0001" => -- brn
next_state <= fetch_state;
when "0010" => -- bhi
if (cc(CBIT) or cc(ZBIT)) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0011" => -- bls
if (cc(CBIT) or cc(ZBIT)) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0100" => -- bcc/bhs
if cc(CBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0101" => -- bcs/blo
if cc(CBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0110" => -- bne
if cc(ZBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0111" => -- beq
if cc(ZBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1000" => -- bvc
if cc(VBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1001" => -- bvs
if cc(VBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1010" => -- bpl
if cc(NBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1011" => -- bmi
if cc(NBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1100" => -- bge
if (cc(NBIT) xor cc(VBIT)) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1101" => -- blt
if (cc(NBIT) xor cc(VBIT)) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1110" => -- bgt
if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1111" => -- ble
if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when others =>
next_state <= fetch_state;
end case;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0000" => -- tsx / tsy
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
if pre_byte = "00011000" then
-- tsy
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
-- tsx
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
next_state <= fetch_state;
when "0001" => -- ins
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0010" => -- pula
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= pula_state;
when "0011" => -- pulb
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= pulb_state;
when "0100" => -- des
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0101" => -- txs / tys
if pre_byte = "00011000" then
-- tys
left_ctrl <= iy_left;
else
-- txs
left_ctrl <= ix_left;
end if;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0110" => -- psha
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= psha_state;
when "0111" => -- pshb
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= pshb_state;
when "1000" => -- pulxy
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= pulxy_hi_state;
when "1001" => -- rts
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= rts_hi_state;
when "1010" => -- abx / aby
if pre_byte = "00011000" then
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
when "1011" => -- rti
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= rti_cc_state;
when "1100" => -- pshxy
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= pshxy_lo_state;
when "1101" => -- mul
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= mul_state;
when "1110" => -- wai
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= int_pcl_state;
when "1111" => -- swi
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= int_pcl_state;
when others =>
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = Acc A dest = Acc A
-- Do not advance PC
--
when "0100" => -- acca single op
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- single operand acc b
-- Do not advance PC
--
when "0101" =>
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
when "1000" => -- acca immediate
ea_ctrl <= fetch_first_ea; -- for BSR
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
cc_ctrl <= latch_cc;
case op_code(3 downto 0) is
when "0011" | -- subd #
"1100" | -- cpx / cpy #
"1110" => -- lds #
-- increment the pc
md_ctrl <= fetch_first_md;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
next_state <= immediate16_state;
when "1101" => -- bsr
-- increment the pc
md_ctrl <= fetch_first_md;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
next_state <= bsr_state;
when "1111" => -- egdx /egdy
-- idle pc
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
pc_ctrl <= latch_pc;
md_ctrl <= load_md;
next_state <= exchange_state;
when others =>
md_ctrl <= fetch_first_md;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
ea_ctrl <= fetch_first_ea;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0111" => -- staa direct
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1111" => -- sts direct
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1101" => -- jsr direct
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= jsr_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= read8_state;
end case;
when "1010" => -- acca indexed
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when "1011" => -- acca extended
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
when "1100" => -- accb immediate
ea_ctrl <= latch_ea;
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldx # / ldy #
op_ctrl <= latch_op;
next_state <= immediate16_state;
when "1101" => -- indexed Y pre-byte $CD
op_ctrl <= fetch_op;
next_state <= decode_state;
when others =>
op_ctrl <= latch_op;
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0111" => -- stab direct
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std direct
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx / sty direct
if( pre_byte = "00011000" ) or (pre_byte = "00011010" ) then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= read8_state;
end case;
when "1110" => -- accb indexed
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when "1111" => -- accb extended
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
when others =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- idle the pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
when immediate16_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
pre_ctrl <= latch_pre;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
ea_ctrl <= latch_ea;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
--
-- ea holds 8 bit index offet
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
-- idle bus.
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- add 8 bit ea to ix or iy
if(( pre_byte = "00011000") or (pre_byte = "11001101")) then
ea_ctrl <= add_iy_ea;
else
ea_ctrl <= add_ix_ea;
end if;
case op_code(7 downto 4) is
when "0001" => -- BSET, BCLR, BRSET, BRCLR
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
case op_code(3 downto 0) is
when "1100" | -- BSET
"1101" | -- BCLR
"1110" | -- BRSET
"1111" => -- BRCLR
next_state <= read8_state;
when others =>
next_state <= fetch_state;
end case;
when "0110" => -- single op indexed
case op_code(3 downto 0) is
when "1011" => -- undefined
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jmp_state;
when "1111" => -- clr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
-- alu_ctrl <= alu_st8;
alu_ctrl <= alu_clr; -- 13 Jan 2004 /sashz
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1010" => -- acca indexed
case op_code(3 downto 0) is
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- jsr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jsr_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1110" => -- accb indexed
case op_code(3 downto 0) is
when "0111" => -- stab direct
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std direct
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx / sty direct
if( pre_byte = "00011000" ) or (pre_byte = "00011010" ) then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
--
-- ea holds 8 bit index offet
-- calculate the effective memory address
-- using the alu
--
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- work out the next state
case op_code(7 downto 4) is
when "0111" => -- single op extended
case op_code(3 downto 0) is
when "1011" => -- undefined
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jmp_state;
when "1111" => -- clr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
-- alu_ctrl <= alu_ld8;
alu_ctrl <= alu_clr; -- 13 Jan 2004 /sashz
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1011" => -- acca extended
case op_code(3 downto 0) is
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- jsr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jsr_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1111" => -- accb extended
case op_code(3 downto 0) is
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx / sty
if(( pre_byte = "00011000" ) or ( pre_byte = "00011010" )) then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when others =>
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte (direct page)
-- can enter here from extended addressing
-- read memory location
-- note that reads may be 8 or 16 bits
--
when read8_state => -- read data
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
when "0001" => -- bset / bclr / brset / brclr
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
pc_ctrl <= load_pc;
next_state <= bitmask_state;
when "0110" | "0111" => -- single operand
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
pc_ctrl <= latch_pc;
next_state <= execute_state;
when "1001" | "1010" | "1011" => -- acca
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0011" | -- subd / cpd
"1110" | -- lds
"1100" => -- cpx / cpy
-- increment the effective address in case of 16 bit load
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= read16_state;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= fetch_state;
end case;
when "1101" | "1110" | "1111" => -- accb
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldx / ldy
-- increment the effective address in case of 16 bit load
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= read16_state;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= fetch_state;
end case;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
when read16_state => -- read second data byte from ea
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- idle the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
--
-- exchange registers
-- at this point md holds accd
-- transfer X or Y to accd
--
when exchange_state => -- md holds accd
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- transfer x or y to accd
if pre_byte = "00011000" then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle the address bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
when bitmask_state => -- fetch bit mask from next op
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
-- addvance the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- read the bit mask into the pre byte register
pre_ctrl <= fetch_pre;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
case op_code is
when "00010010" | "00011110" => -- brset
next_state <= brset_state;
when "00010011" | "00011111" => -- brclr
next_state <= brclr_state;
when "00010100" | "00011100" => -- bset
next_state <= execute_state;
when "00010101" | "00011101" => -- bclr
next_state <= execute_state;
when others =>
next_state <= fetch_state;
end case;
when brclr_state => -- fetch the branch offset
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- advance the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch the branch offset
addr_ctrl <= fetch_ad;
ea_ctrl <= fetch_first_ea;
dout_ctrl <= md_lo_dout;
if (pre_byte and md(7 downto 0) ) = "00000000" then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when brset_state => -- fetch the branch offset
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- advance the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch the branch offset
addr_ctrl <= fetch_ad;
ea_ctrl <= fetch_first_ea;
dout_ctrl <= md_lo_dout;
if (pre_byte and md(7 downto 0) ) = "00000000" then
next_state <= fetch_state;
else
next_state <= branch_state;
end if;
when jmp_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
when jsr_state => -- JSR
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= jsr1_state;
when jsr1_state => -- JSR
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= jmp_state;
when branch_state => -- Bcc
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- calculate signed branch
left_ctrl <= pc_left;
right_ctrl <= sexea_right; -- right must be sign extended effective address
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
when bsr_state => -- BSR
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= bsr1_state;
when bsr1_state => -- BSR
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= branch_state;
when rts_hi_state => -- RTS
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_hi_dout;
next_state <= rts_lo_state;
when rts_lo_state => -- RTS1
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
when mul_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mulea_state;
when mulea_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
md_ctrl <= latch_md;
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= muld_state;
when muld_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= latch_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul0_state;
when mul0_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= inc_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- if ea bit(count) set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea_bit = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if count = "0111" then
next_state <= fetch_state;
else
next_state <= mul0_state;
end if;
--
-- Integer division
-- ACCD = numerator
-- EA = denominator
-- IX = quotient
--
-- For integer divide, re-arrange registers
-- IX = ACCD = dividend low word
-- ACCD = 0 = dividend
--
when idiv_state =>
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- transfer ACCD to IX
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix; --- quotient / dividend
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= div1_state;
--
-- Common integer divide
-- ACCD = Dividend high word
-- IX = Dividend low word / Quotient
-- EA = Divisor
-- MD = Temp for subtraction
--
-- Test for divide
-- MD = ACCD - EA
--
when div1_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- subtract denominator from numerator
left_ctrl <= accd_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
md_ctrl <= load_md; -- md = temporary result
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= div2_state;
--
-- shift carry into quotient
-- IX = IX << 1 + Carry
-- next state dependant on carry from previous state
--
when div2_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= inc_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= load_md;
-- rotate carry into quotient
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if cc(CBIT) = '1' then
next_state <= div3_state;
else
next_state <= div4_state;
end if;
--
-- hear if Carry Set from subtract
-- ACCD = ACCD << 1 + Carry
--
when div3_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- shift numerator left
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if count = "10000" then
next_state <= div5_state;
else
next_state <= div1_state;
end if;
--
-- hear if Carry Clear from subtract
-- ACCD = MD << 1 + Carry
--
when div4_state =>
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- numerator = Subtraction rotated left
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if count = "10000" then
next_state <= div5_state;
else
next_state <= div1_state;
end if;
--
-- invert quotient in IX
-- IX = COM( IX )
--
when div5_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- complement quotient
left_ctrl <= ix_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
--
-- Spin the Program counter
--
when spin_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- complement quotient
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
cc_ctrl <= latch_cc;
-- idle bus
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
next_state <= spin_state;
--
-- Execute cycle is performed by
-- single operand indexed and extended instructions
-- and bit operators.
--
when execute_state => -- execute
-- default
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
count_ctrl <= reset_count;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
when "0001" => -- bit operators come here
case op_code(3 downto 0) is
when "0100" | "1100" => -- bset
-- OR bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_bset;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0101" | "1101" => -- bclr
-- AND bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_bclr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
-- idle ALU
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when "0110" | -- indexed single op
"0111" => -- extended single op
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1011" => -- undefined
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
--
-- 16 bit Write state
-- write high byte of ALU output.
-- EA hold address of memory to write to
-- Advance the effective address in ALU
--
when write16_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- write the ALU hi byte to ea
addr_ctrl <= write_ad;
dout_ctrl <= md_hi_dout;
next_state <= write8_state;
--
-- 8 bit write
-- Write low 8 bits of ALU output
--
when write8_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
when psha_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= push_ad;
dout_ctrl <= acca_dout;
next_state <= fetch_state;
when pula_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pull_ad;
dout_ctrl <= acca_dout;
next_state <= fetch_state;
when pshb_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= push_ad;
dout_ctrl <= accb_dout;
next_state <= fetch_state;
when pulb_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pull_ad;
dout_ctrl <= accb_dout;
next_state <= fetch_state;
when pshxy_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= push_ad;
if pre_byte = "00011000" then
dout_ctrl <= iy_lo_dout;
else
dout_ctrl <= ix_lo_dout;
end if;
next_state <= pshxy_hi_state;
when pshxy_hi_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix / iy hi
addr_ctrl <= push_ad;
if pre_byte = "00011000" then
dout_ctrl <= iy_hi_dout;
else
dout_ctrl <= ix_hi_dout;
end if;
next_state <= fetch_state;
when pulxy_hi_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- pull ix hi
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= pull_hi_iy;
dout_ctrl <= iy_hi_dout;
else
ix_ctrl <= pull_hi_ix;
iy_ctrl <= latch_iy;
dout_ctrl <= ix_hi_dout;
end if;
addr_ctrl <= pull_ad;
next_state <= pulxy_lo_state;
when pulxy_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read ix low
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= pull_lo_iy;
dout_ctrl <= iy_lo_dout;
else
ix_ctrl <= pull_lo_ix;
iy_ctrl <= latch_iy;
dout_ctrl <= ix_lo_dout;
end if;
addr_ctrl <= pull_ad;
next_state <= fetch_state;
--
-- return from interrupt
-- enter here from bogus interrupts
--
when rti_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- idle address bus
cc_ctrl <= latch_cc;
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
next_state <= rti_cc_state;
when rti_cc_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pull_ad;
dout_ctrl <= cc_dout;
next_state <= rti_accb_state;
when rti_accb_state =>
-- default registers
acca_ctrl <= latch_acca;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pull_ad;
dout_ctrl <= accb_dout;
next_state <= rti_acca_state;
when rti_acca_state =>
-- default registers
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pull_ad;
dout_ctrl <= acca_dout;
next_state <= rti_ixh_state;
when rti_ixh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_hi_dout;
next_state <= rti_ixl_state;
when rti_ixl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_lo_dout;
next_state <= rti_iyh_state;
when rti_iyh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pull_ad;
dout_ctrl <= iy_hi_dout;
next_state <= rti_iyl_state;
when rti_iyl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pull_ad;
dout_ctrl <= iy_lo_dout;
next_state <= rti_pch_state;
when rti_pch_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_hi_dout;
next_state <= rti_pcl_state;
when rti_pcl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
--
-- here on interrupt
-- iv register hold interrupt type
--
when int_pcl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
when int_pch_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= int_iyl_state;
when int_iyl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write iy low
addr_ctrl <= push_ad;
dout_ctrl <= iy_lo_dout;
next_state <= int_iyh_state;
when int_iyh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write iy hi
addr_ctrl <= push_ad;
dout_ctrl <= iy_hi_dout;
next_state <= int_ixl_state;
when int_ixl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= push_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
when int_ixh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= push_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_acca_state;
when int_acca_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= push_ad;
dout_ctrl <= acca_dout;
next_state <= int_accb_state;
when int_accb_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= push_ad;
dout_ctrl <= accb_dout;
next_state <= int_cc_state;
when int_cc_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write cc
addr_ctrl <= push_ad;
dout_ctrl <= cc_dout;
--
-- XIRQ is level sensitive
--
if (xirq = '1') and (cc(XBIT) = '0') then
iv_ctrl <= xirq_iv;
next_state <= int_maskx_state;
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_maski_state;
elsif (irq_ext3 = '1') and (cc(IBIT) = '0') then
iv_ctrl <= ext3_iv;
next_state <= int_maski_state;
elsif (irq_ext2 = '1') and (cc(IBIT) = '0') then
iv_ctrl <= ext2_iv;
next_state <= int_maski_state;
elsif (irq_ext1 = '1') and (cc(IBIT) = '0') then
iv_ctrl <= ext1_iv;
next_state <= int_maski_state;
elsif (irq_ext0 = '1') and (cc(IBIT) = '0') then
iv_ctrl <= ext0_iv;
next_state <= int_maski_state;
else
case op_code is
when "00111110" => -- WAI (wait for interrupt)
iv_ctrl <= latch_iv;
next_state <= int_wai_state;
when "00111111" => -- SWI (Software interrupt)
iv_ctrl <= swi_iv;
next_state <= vect_hi_state;
when others => -- bogus interrupt (return)
iv_ctrl <= latch_iv;
next_state <= rti_state;
end case;
end if;
end if;
when int_wai_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
count_ctrl <= reset_count;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- enable interrupts
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_cli;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
--
-- XIRQ is level sensitive
--
if (xirq = '1') and (cc(XBIT) = '0') then
iv_ctrl <= xirq_iv;
next_state <= int_maskx_state;
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_maski_state;
elsif (irq_ext3 = '1') and (cc(IBIT) = '0') then
iv_ctrl <= ext3_iv;
next_state <= int_maski_state;
elsif (irq_ext2 = '1') and (cc(IBIT) = '0') then
iv_ctrl <= ext2_iv;
next_state <= int_maski_state;
elsif (irq_ext1 = '1') and (cc(IBIT) = '0') then
iv_ctrl <= ext1_iv;
next_state <= int_maski_state;
elsif (irq_ext0 = '1') and (cc(IBIT) = '0') then
iv_ctrl <= ext0_iv;
next_state <= int_maski_state;
else
iv_ctrl <= latch_iv;
next_state <= int_wai_state;
end if;
end if;
when int_maskx_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- Mask IRQ
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sex;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= vect_hi_state;
when int_maski_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- Mask IRQ
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= vect_hi_state;
when others => -- halt on undefine states
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- do nothing in ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= halt_state;
end case;
end process;
--------------------------------
--
-- state machine
--
--------------------------------
change_state: process( clk, rst, state )
begin
if rst = '1' then
state <= reset_state;
elsif clk'event and clk = '0' then
state <= next_state;
end if;
end process;
-- output
end;
| gpl-3.0 | 51f3218b1893feff2a078933cdb18c7e | 0.434094 | 3.618237 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/addr_load_and_incr.vhd | 3 | 5,835 | -------------------------------------------------------------------------------
-- $Id: addr_load_and_incr.vhd,v 1.1 2003/03/15 01:05:24 ostlerf Exp $
-------------------------------------------------------------------------------
-- addr_load_and_incr - entity and architecture
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: addr_load_and_incr.vhd
--
-- Description: Module to load an address, increment present address and
-- synchronously reset using Virtex primitives.
--
-- This module instantiates Virtex primitives to realize a module requiring
-- minimal FPGA resources that synchronously loads Bus_input data on
-- Bus_output when Incr_N_Load is low. and synchronously increments
-- Bus_output when Incr_N_Load is high. Both operations are gated by
-- FDRE_CE which is the register clock enable. A synchronous reset is
-- performed via FDRE_Reset which takes precidence over FDRE_CE and
-- the D-input. One LUT is required per bus-bit.
--
-- Note that this module was designed because I was not successful in
-- inferring FDRE FFs with synplicity's 6.2 release.
--
-------------------------------------------------------------------------------
--
-- addr_load_and_incr.vhd
-- unisim
--
-------------------------------------------------------------------------------
-- Author: MLL
-- History:
-- MLL 09/27/01 -- First version
--
-- <initials> <date>
-- ^^^^^^
--
-------------------------------------------------------------------------------
library unisim;
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity addr_load_and_incr is
generic (
C_BUS_WIDTH : integer
);
port(
--Bus ports
Bus_Clk : in STD_LOGIC;
FDRE_CE : in STD_LOGIC;
FDRE_Reset : in STD_LOGIC;
Incr_N_Load : in STD_LOGIC;
Bus_input : in STD_LOGIC_VECTOR (0 to C_BUS_WIDTH-1);
Bus_output : out STD_LOGIC_VECTOR (0 to C_BUS_WIDTH-1)
);
end addr_load_and_incr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of addr_load_and_incr is
constant RESET_ACTIVE: std_logic := '1';
--signals
signal Bus_cry : STD_LOGIC_VECTOR (0 to C_BUS_WIDTH-1);
signal Bus_qxu : STD_LOGIC_VECTOR (0 to C_BUS_WIDTH-1);
signal Bus_s : STD_LOGIC_VECTOR (0 to C_BUS_WIDTH-1);
signal Bus_c : STD_LOGIC_VECTOR (0 to C_BUS_WIDTH-1);
component LUT4
generic(
INIT : bit_vector(15 downto 0)
);
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component XORCY
port(
O : out STD_ULOGIC;
LI : in STD_ULOGIC;
CI : in STD_ULOGIC);
end component;
component MUXCY_L
port(
LO : out STD_ULOGIC;
DI : in STD_ULOGIC;
CI : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
component FDRE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC;
R : in STD_ULOGIC);
end component;
begin
Bus_output <= Bus_c;
Load_and_increment_vector_Generate: for j in 0 to C_BUS_WIDTH-2 generate
begin
I_LUT4_add_incr: LUT4
generic map(
INIT => X"1BE4"
)
port map(
O => Bus_qxu(j),
I0 => Incr_N_Load,
I1 => Bus_input(j),
I2 => Bus_c(j),
I3 => '0'
);
I_XORCY_add_incr: XORCY
port map(
O => Bus_s(j),
LI => Bus_qxu(j),
CI => Bus_cry(j+1)
);
I_FDRE_add_incr: FDRE
port map(
Q => Bus_c(j),
C => Bus_Clk,
CE => FDRE_CE,
D => Bus_s(j),
R => FDRE_Reset
);
I_MUXCY_L_add_incr: MUXCY_L
port map(
LO => Bus_cry(j),
DI => '0',
CI => Bus_cry(j+1),
S =>Bus_qxu(j)
);
end generate Load_and_increment_vector_Generate;
I_LUT4_add_incr: LUT4
generic map(
INIT => X"1BE4"
)
port map(
O => Bus_qxu(C_BUS_WIDTH-1),
I0 => Incr_N_Load,
I1 => Bus_input(C_BUS_WIDTH-1),
I2 => Bus_c(C_BUS_WIDTH-1),
I3 => '0'
);
I_XORCY_add_incr: XORCY
port map(
O => Bus_s(C_BUS_WIDTH-1),
LI => Bus_qxu(C_BUS_WIDTH-1),
CI => Incr_N_Load
);
I_FDRE_add_incr: FDRE
port map(
Q => Bus_c(C_BUS_WIDTH-1),
C => Bus_Clk,
CE => FDRE_CE,
D => Bus_s(C_BUS_WIDTH-1),
R => FDRE_Reset
);
I_MUXCY_L_add_incr: MUXCY_L
port map(
LO => Bus_cry(C_BUS_WIDTH-1),
DI => '0',
CI => Incr_N_Load,
S =>Bus_qxu(C_BUS_WIDTH-1)
);
end implementation;
| bsd-3-clause | cdb603462f7ec9b3fdb2b376aa8825f6 | 0.409083 | 3.98838 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/dynshreg_i_f.vhd | 2 | 20,729 | -------------------------------------------------------------------------------
-- $Id: dynshreg_i_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: FLO
--
-- History:
-- FLO 01/03/07 First Version. Derived from dynshreg_f.
--
-- ~~~~~~
-- FLO 12/20/07
-- ^^^^^^
-- -Now using clog2 instead of log2.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_i_f is
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
--
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
function srl_init_string(i, j : natural;
w : natural;
d : positive;
bpsrl : positive;
v : bit_vector
) return bit_vector is
variable base : natural := j*bpsrl*w + i;
variable r : bit_vector(bpsrl-1 downto 0) := (others => '0');
begin
for k in 0 to min(bpsrl, d-j*bpsrl)-1 loop
r(k) := v(base+k*w);
end loop;
return r;
end srl_init_string;
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
generic map (
INIT => srl_init_string(i, j,
C_DWIDTH,
C_DEPTH,
BPSRL,
FULL_INIT_VAL)
)
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
generic map (
INIT => srl_init_string(i, j,
C_DWIDTH,
C_DEPTH,
BPSRL,
FULL_INIT_VAL)
)
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v3_00_a.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
| bsd-3-clause | a2b0075103e283416145b30155323452 | 0.478219 | 4.483885 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_lock_1.vhd | 2 | 16,347 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_lock_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_lock( mutex );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- if( _mutex_owner( mutex->num ) == hthread_self() )
when STATE_4 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg1_next <= intrfc2thrd_value;
-- Call the Synch Manager to find out the owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg1_next <= intrfc2thrd_value;
-- Call hthread_self();
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_SELF;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
if ( intrfc2thrd_value = reg1 ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= STATE_8;
-- hthread_mutex_unlock( mutex );
when STATE_8 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- Call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
when STATE_10 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | ecc7afe47bb7ed80066b453a85bf4321 | 0.544565 | 3.792807 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/or_bits.vhd | 2 | 10,959 | -------------------------------------------------------------------------------
-- $Id: or_bits.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Or_bits
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_bits.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
-- C_START_BIT -- starting bit location of bits to OR
-- C_BUS_SIZE -- total size of the bus
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- input Sig -- another signal not in the bus to be ORd with the
-- -- bus section
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_bits is
generic (
C_NUM_BITS : integer := 8;
C_START_BIT : integer := 0;
C_BUS_SIZE : integer := 8);
port (
In_bus : in std_logic_vector(0 to C_BUS_SIZE-1);
Sig : in std_logic;
Or_out : out std_logic
);
end or_bits;
architecture implementation of or_bits is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less (including Sig), a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 4 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= Sig or In_bus(C_START_BIT);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(C_START_BIT + i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more (including Sig), then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 4 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(C_START_BIT to C_START_BIT+C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
--CI => '0' , --[in]
CI => Sig , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| bsd-3-clause | a7b6ae47ef90213ec6c3416b07d8b97a | 0.404234 | 4.988166 | false | false | false | false |
xdsopl/vhdl | asynchronous_quadrature_decoder_testbench.vhd | 1 | 2,217 | -- asynchronous_quadrature_decoder_testbench - testbench for asynchronous quadrature decoder
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity asynchronous_quadrature_decoder_testbench is
end asynchronous_quadrature_decoder_testbench;
architecture behavioral of asynchronous_quadrature_decoder_testbench is
signal a, b : std_logic := '0';
signal rotary : std_logic_vector (1 downto 0);
signal direction : std_logic;
signal pulse : std_logic;
procedure noise(variable n : inout std_logic_vector(15 downto 0)) is
begin
-- Thanks Maxim on smspower for (reverse engineered?) specs.
-- Generator polynomial for noise channel of SN76489
-- used on the SMS is not irrereducible: X^16 + X^13 + 1
n := (n(0) xor n(3)) & n(15 downto 1);
end procedure;
procedure switch(
signal s : out std_logic;
constant v : std_logic;
variable n : inout std_logic_vector(15 downto 0)) is
begin
s <= v;
wait for 10 us;
for i in 1 to 19 loop
s <= n(0);
noise(n);
wait for 10 us;
end loop;
s <= v;
wait for 800 us;
end procedure;
begin
rotary <= b & a;
asynchronous_quadrature_decoder_inst : entity work.asynchronous_quadrature_decoder
port map (rotary, direction, pulse);
stimulus : process
variable n : std_logic_vector(15 downto 0) := (15 => '1', others => '0');
begin
-- start position
a <= '0';
b <= '0';
wait for 2 ms;
for j in 0 to 2 loop
for i in 0 to j loop
-- one step left
switch(a, '1', n);
switch(b, '1', n);
switch(a, '0', n);
switch(b, '0', n);
wait for 1 ms;
end loop;
for i in 0 to j loop
-- one step right
switch(b, '1', n);
switch(a, '1', n);
switch(b, '0', n);
switch(a, '0', n);
wait for 1 ms;
end loop;
end loop;
wait;
end process;
end behavioral;
| cc0-1.0 | 17edd40e847117640f25bc8848f762ec | 0.673884 | 3.203757 | false | true | false | false |
a4a881d4/zcpsm | src/zcpsm/queue/Rx_queue.vhd | 1 | 3,573 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Rx_queue is
generic(
HEAD_AWIDTH : natural := 5;
FIFO_AWIDTH : natural := 2;
RAM_TYPE : string := "DIS_RAM"
);
port(
clk : in std_logic;
reset : in std_logic;
-- Rx Input
head_wren : in std_logic;
head_waddr : in std_logic_vector(HEAD_AWIDTH - 1 downto 0);
head_wdata : in std_logic_vector(7 downto 0);
head_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end entity;
architecture arch_Rx_queue of Rx_queue is
component fifo_block
generic(
DWIDTH : INTEGER; -- 8
BLOCK_AWIDTH : INTEGER; -- 5
FIFO_AWIDTH : INTEGER; -- 2
RAM_TYPE : STRING);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
wr_block : in std_logic;
wr_clk : in std_logic;
wren : in std_logic;
waddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
wdata : in std_logic_vector((DWIDTH-1) downto 0);
rd_block : in std_logic;
rd_clk : in std_logic;
raddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
rdata : out std_logic_vector((DWIDTH-1) downto 0);
full : out std_logic;
empty : out std_logic);
end component;
component fifo2zcpsm
generic(
BLOCK_AWIDTH : INTEGER;
DWIDTH : INTEGER);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
fifo_rd_block : out std_logic;
fifo_raddr : out std_logic_vector((BLOCK_AWIDTH-1) downto 0);
fifo_rdata : in std_logic_vector((DWIDTH-1) downto 0);
fifo_full : in std_logic;
fifo_empty : in std_logic);
end component;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_raddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal fifo_rdata : std_logic_vector(7 downto 0);
signal fifo_rd_block : std_logic;
begin
u_queue : fifo_block
generic map(
DWIDTH => 8,
BLOCK_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => RAM_TYPE
)
port map(
clk => clk,
reset => reset,
clr => '0',
wr_block => head_wr_block,
wr_clk => clk,
wren => head_wren,
waddr => head_waddr,
wdata => head_wdata,
rd_block => fifo_rd_block,
rd_clk => zcpsm_clk,
raddr => fifo_raddr,
rdata => fifo_rdata,
empty => fifo_empty,
full => fifo_full
);
u_zcpsm_intf : fifo2zcpsm
generic map(
BLOCK_AWIDTH => HEAD_AWIDTH,
-- BLOCK_AWIDTH => 6,
DWIDTH => 8
)
port map(
clk => clk,
reset => reset,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => zcpsm_ce,
zcpsm_port_id => zcpsm_port_id,
zcpsm_write_strobe => zcpsm_write_strobe,
zcpsm_out_port => zcpsm_out_port,
zcpsm_read_strobe => zcpsm_read_strobe,
zcpsm_in_port => zcpsm_in_port,
fifo_rd_block => fifo_rd_block,
fifo_raddr => fifo_raddr,
fifo_rdata => fifo_rdata,
fifo_full => fifo_full,
fifo_empty => fifo_empty
);
end arch_Rx_queue;
| gpl-2.0 | a4d8357102e18f2a4a1b17d69492df35 | 0.610132 | 2.688488 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_locmon.vhd | 1 | 9,070 | --------------------------------------------------------------------------------
-- Title : Location Monitor
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_locmon.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 08/04/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The WBB2VME core supports two independent Location Monitors. Each can be used
-- to monitor the VMEbus in order to notify the CPU about write/read accesses to
-- a predefined VME address, even if the WBB2VME master or slave is not used for
-- this transaction. If a hit is found, the notification is done by interrupt
-- (signaled via locmon_irq to WBB).
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- vme_ctrl
-- vme_locmon
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_locmon.vhd,v $
-- Revision 1.2 2012/11/12 08:13:08 MMiehling
-- bugfix locmon: registered addresses before evaluation in order to get stable results
--
-- Revision 1.1 2012/03/29 10:14:38 MMiehling
-- Initial Revision
--
-- Revision 1.5 2005/02/04 13:44:07 mmiehling
-- added combinations of addr3+4; changed locmon_en timing
--
-- Revision 1.4 2004/11/02 11:29:20 mmiehling
-- improved timing and area
--
-- Revision 1.3 2003/12/01 10:03:06 MMiehling
-- adopted to changed vme_adr timing
--
-- Revision 1.2 2003/06/13 10:06:12 MMiehling
-- added address bits 3+4
--
-- Revision 1.1 2003/04/22 11:07:25 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_locmon IS
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
en_vme_adr_in : IN std_logic; -- samples adress and am after asn goes low
ma_en_vme_data_out_reg : IN std_logic; -- enable of vme_adr_out
sl_writen_reg : IN std_logic; -- vme write/read
vme_adr_locmon : IN std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring (registered with en_vme_adr_in)
vam_reg : IN std_logic_vector(5 DOWNTO 0); -- vme registered vam_in
clr_locmon : IN std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
loc_sel : OUT std_logic_vector(1 DOWNTO 0); -- these bits are loaded with combinations of address bits [4:3] if locmon hit address
loc_am_0 : IN std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_am_1 : IN std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_irq_0 : OUT std_logic; -- loc-monitor #0 - irq
loc_irq_1 : OUT std_logic; -- loc-monitor #1 - irq
loc_rw_0 : IN std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_rw_1 : IN std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_adr_0 : IN std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
loc_adr_1 : IN std_logic_vector(31 DOWNTO 0) -- location monitor #1 adress
);
END vme_locmon;
ARCHITECTURE vme_locmon_arch OF vme_locmon IS
SIGNAL sl_writen_req_q : std_logic;
SIGNAL locmon_en : std_logic;
SIGNAL locmon_en_q : std_logic;
SIGNAL adr_0_equal : std_logic_vector(2 DOWNTO 0);
SIGNAL adr_1_equal : std_logic_vector(2 DOWNTO 0);
SIGNAL vam_0_equal : std_logic;
SIGNAL vam_1_equal : std_logic;
SIGNAL loc_hit_am_0 : std_logic_vector(2 DOWNTO 0);
SIGNAL loc_hit_am_1 : std_logic_vector(2 DOWNTO 0);
SIGNAL en_vme_adr_in_q : std_logic;
SIGNAL en_vme_adr_in_flag : std_logic;
SIGNAL vme_adr_locmon_q : std_logic_vector(31 DOWNTO 2);
SIGNAL vam_reg_q : std_logic_vector(5 DOWNTO 4);
BEGIN
en_vme_adr_in_flag <= '1' WHEN en_vme_adr_in = '1' AND en_vme_adr_in_q = '0' ELSE '0';
loc_sel <= vme_adr_locmon_q(4 DOWNTO 3);
-- locmon_0
adr_0_equal(0) <= '1' WHEN vme_adr_locmon_q(15 DOWNTO 10) = loc_adr_0(15 DOWNTO 10) ELSE '0';
adr_0_equal(1) <= '1' WHEN vme_adr_locmon_q(23 DOWNTO 16) = loc_adr_0(23 DOWNTO 16) ELSE '0';
adr_0_equal(2) <= '1' WHEN vme_adr_locmon_q(31 DOWNTO 24) = loc_adr_0(31 DOWNTO 24) ELSE '0';
vam_0_equal <= '1' WHEN vam_reg_q = loc_am_0 ELSE '0';
-- A32
loc_hit_am_0(0) <= '1' WHEN loc_am_0 = "00" AND adr_0_equal(2 DOWNTO 0) = "111" AND vam_0_equal = '1' AND
((loc_rw_0(0) = '1' AND sl_writen_req_q = '1') OR (loc_rw_0(1) = '1' AND sl_writen_req_q = '0')) ELSE '0';
-- A16
loc_hit_am_0(1) <= '1' WHEN loc_am_0 = "10" AND adr_0_equal(0) = '1' AND vam_0_equal = '1' AND
((loc_rw_0(0) = '1' AND sl_writen_req_q = '1') OR (loc_rw_0(1) = '1' AND sl_writen_req_q = '0')) ELSE '0';
-- A24
loc_hit_am_0(2) <= '1' WHEN loc_am_0 = "11" AND adr_0_equal(1 DOWNTO 0) = "11" AND vam_0_equal = '1' AND
((loc_rw_0(0) = '1' AND sl_writen_req_q = '1') OR (loc_rw_0(1) = '1' AND sl_writen_req_q = '0')) ELSE '0';
-- locmon_1
adr_1_equal(0) <= '1' WHEN vme_adr_locmon_q(15 DOWNTO 10) = loc_adr_1(15 DOWNTO 10) ELSE '0';
adr_1_equal(1) <= '1' WHEN vme_adr_locmon_q(23 DOWNTO 16) = loc_adr_1(23 DOWNTO 16) ELSE '0';
adr_1_equal(2) <= '1' WHEN vme_adr_locmon_q(31 DOWNTO 24) = loc_adr_1(31 DOWNTO 24) ELSE '0';
vam_1_equal <= '1' WHEN vam_reg_q = loc_am_1 ELSE '0';
-- A32
loc_hit_am_1(0) <= '1' WHEN loc_am_1 = "00" AND adr_1_equal(2 DOWNTO 0) = "111" AND vam_1_equal = '1' AND
((loc_rw_1(0) = '1' AND sl_writen_req_q = '1') OR (loc_rw_1(1) = '1' AND sl_writen_req_q = '0')) ELSE '0';
-- A16
loc_hit_am_1(1) <= '1' WHEN loc_am_1 = "10" AND adr_1_equal(0) = '1' AND vam_1_equal = '1' AND
((loc_rw_1(0) = '1' AND sl_writen_req_q = '1') OR (loc_rw_1(1) = '1' AND sl_writen_req_q = '0')) ELSE '0';
-- A24
loc_hit_am_1(2) <= '1' WHEN loc_am_1 = "11" AND adr_1_equal(1 DOWNTO 0) = "11" AND vam_1_equal = '1' AND
((loc_rw_1(0) = '1' AND sl_writen_req_q = '1') OR (loc_rw_1(1) = '1' AND sl_writen_req_q = '0')) ELSE '0';
loc : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
loc_irq_0 <= '0';
loc_irq_1 <= '0';
sl_writen_req_q <= '0';
en_vme_adr_in_q <= '0';
locmon_en_q <= '0';
locmon_en <= '0';
vme_adr_locmon_q <= (OTHERS => '0');
vam_reg_q <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
en_vme_adr_in_q <= en_vme_adr_in;
locmon_en <= en_vme_adr_in_flag;
locmon_en_q <= locmon_en;
IF locmon_en = '1' THEN -- sample inputs for locmon at start of operation
sl_writen_req_q <= sl_writen_reg;
vme_adr_locmon_q <= vme_adr_locmon;
vam_reg_q <= vam_reg(5 DOWNTO 4);
END IF;
IF clr_locmon(0) = '1' THEN
loc_irq_0 <= '0';
ELSIF (loc_hit_am_0(0) = '1' OR loc_hit_am_0(1) = '1' OR loc_hit_am_0(2) = '1') AND locmon_en_q = '1' THEN
loc_irq_0 <= '1';
ELSE
loc_irq_0 <= '0';
END IF;
IF clr_locmon(1) = '1' THEN
loc_irq_1 <= '0';
ELSIF (loc_hit_am_0(0) = '1' OR loc_hit_am_1(1) = '1' OR loc_hit_am_1(2) = '1') AND locmon_en_q = '1' THEN
loc_irq_1 <= '1';
ELSE
loc_irq_1 <= '0';
END IF;
END IF;
END PROCESS loc;
END vme_locmon_arch;
| gpl-3.0 | b4cb9bd63ee7fd25e060c82e761671a7 | 0.514994 | 3.182456 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/ipif_mirror128.vhd | 2 | 17,014 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic mirrors data from the master with
-- the smaller bus width to the correct byte lanes of the
-- larger IPIF devices. The BE signals are also mirrored.
--
-- For reads, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 10-10-2008 -- First version
-- ^^^^^^
-- First version of IPIF mirror logic.
-- ~~~~~~
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of IPIF Slave
-- C_SMALLEST : integer := width of smallest Master (not access size)
-- that will access the IPIF Slave
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of Master accessing slave
-- Size indication (Decode_size)
-- 00 - 32-Bit Master
-- 01 - 64-Bit Master
-- 10 - 128-Bit Master
-- 11 - 256-Bit Master (Not Support)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_mirror128 is
generic (
C_DWIDTH : integer := 32; -- 64, 128 (Slave Dwidth)
C_SMALLEST : integer := 32; -- 32, 64, 128 (Smallest Master)
C_AWIDTH : integer := 32
);
port (
Wr_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Wr_Size : in std_logic_vector(0 to 1);
Rd_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Rd_Size : in std_logic_vector(0 to 1);
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_mirror128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_mirror128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
GEN_SAME: if C_DWIDTH <= C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
-------------------------------------------------------------------------------
-- Write Data Mirroring
-------------------------------------------------------------------------------
---------------------
-- 64 Bit Support --
---------------------
GEN_WR_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-3); --a29
case addr_bits is
when '0' =>
case Wr_Size is
when "00" => -- 32-Bit Master
BE_Out(4 to 7) <= (others => '0');
when others => null;
end case;
when '1' =>
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31);
BE_Out(4 to 7) <= BE_In(0 to 3);
BE_Out(0 to 3) <= (others => '0');
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_WR_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "00" => --0
case Wr_Size is
when "00" => -- 32-Bit Master
BE_Out(4 to 15) <= (others => '0');
when "01" => -- 64-Bit Master
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when "01" => --4
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31);
BE_Out(4 to 7) <= BE_In(0 to 3);
BE_Out(0 to 3) <= (others => '0');
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when "10" => --8
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(64 to 95) <= Wr_Data_In(0 to 31);
BE_Out(8 to 11) <= BE_In(0 to 3);
BE_Out(0 to 7) <= (others => '0');
BE_Out(12 to 15) <= (others => '0');
when "01" => -- 64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when "11" => --C
case Wr_Size is
when "00" => --32-Bit Master
Wr_Data_Out(96 to 127) <= Wr_Data_In(0 to 31);
BE_Out(12 to 15) <= BE_In(0 to 3);
BE_Out(0 to 11) <= (others => '0');
when "01" => --64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_128_32;
GEN_WR_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-4);
case addr_bits is
when '0' =>
case Wr_Size is
when "01" => -- 64-Bit Master
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when '1' => --8
case Wr_Size is
when "01" => -- 64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_128_64;
-------------------------------------------------------------------------------
-- Read Data Steering
-------------------------------------------------------------------------------
---------------------
-- 64 Bit Support --
---------------------
GEN_RD_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_RD_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63);
when others => null;
end case;
when "10" => --8
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(64 to 95);
when "01" => -- 64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when "11" => --C
case Rd_Size is
when "00" => --32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(96 to 127);
when "01" => --64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_128_32;
GEN_RD_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
case Rd_Size is
when "01" => -- 64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_128_64;
end architecture IMP;
| bsd-3-clause | 96c3be8266a6bc9987607a2a43802333 | 0.421535 | 4.362564 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/addsub.vhd | 2 | 10,864 | -------------------------------------------------------------------------------
-- $Id: addsub.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Either add an ArgA or subtract an ArgS from an ArgD.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: addsub.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description:
-- Either add an ArgA or subtract an ArgS from an ArgD. The
-- output, Result, can be optionally combinatorial or registered.
--
-- When C_REGISTERED is false, Result will take on one of
-- two values:
--
-- ArgD - ArgS, when Sub is asserted, or
-- ArgD + ArgA, when Sub is not asserted.
--
-- Cry_BrwN will be '1' if ArgD + ArgA produces a carry
-- and it will be '0' if ArgD - ArgS produces a borrow.
--
-- The signals Clk, Rst and CE are meaningful and used only
-- if C_REGISTERED is true. These may be "tied off" to any
-- std_logic value in combinatorial instantiations (e.g.
-- connected to '0').
--
-- This table details the operation in registered mode:
--
-- Clk Rst CE Sub <Cry_BrwN, Result>
-- --- --- -- --- ------------------
-- _
-- _| 1 x x 0
--
-- _
-- _| 0 1 0 ArgD + ArgA
--
-- _
-- _| 0 1 1 ArgD - ArgS
--
-- _
-- _| 0 0 x No change
--
-- _
-- not _| x x x No change
--
-------------------------------------------------------------------------------
-- Structure:
--
-- addsub.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/14/2003 -- First version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity addsub is
generic (
C_WIDTH : natural := 8;
C_REGISTERED : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic; -- Reset Result and Cry_BrwN to zero
CE : in std_logic;
ArgD : in std_logic_vector(0 to C_WIDTH-1);
ArgA : in std_logic_vector(0 to C_WIDTH-1);
ArgS : in std_logic_vector(0 to C_WIDTH-1);
Sub : in std_logic;
Cry_BrwN : out std_logic;
Result : out std_logic_vector(0 to C_WIDTH-1)
);
end addsub;
library unisim;
use unisim.VCOMPONENTS.FDRE;
use unisim.VCOMPONENTS.MUXCY;
use unisim.VCOMPONENTS.XORCY;
library ieee;
use ieee.numeric_std.all;
architecture imp of addsub is
signal lutout,
xorcy_out : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
begin
cry(C_WIDTH) <= Sub;
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
begin
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
lutout(j) <= ArgD(j) xor ArgA(j) when Sub = '0' else
ArgD(j) xnor ArgS(j);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => ArgD(j),
CI => cry(j+1),
S => lutout(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lutout(j),
CI => cry(j+1),
O => xorcy_out(j)
);
------------------------------------------------------------------------
-- Result, combinatorial or registered.
------------------------------------------------------------------------
COM_GEN : if not C_REGISTERED generate
Result(j) <= xorcy_out(j);
end generate;
-- else
REG_GEN : if C_REGISTERED generate
FDRE_I1: FDRE
port map (
Q => Result(j),
C => Clk,
CE => CE,
D => xorcy_out(j),
R => Rst
);
end generate;
end generate;
----------------------------------------------------------------------------
-- Cry_BrwN, combinatorial or registered.
----------------------------------------------------------------------------
COM_GEN : if not C_REGISTERED generate
Cry_BrwN <= cry(0);
end generate;
-- else
REG_GEN : if C_REGISTERED generate
FDRE_I1: FDRE
port map (
Q => Cry_BrwN,
C => Clk,
CE => CE,
D => cry(0),
R => Rst
);
end generate;
end imp;
| bsd-3-clause | 577f1820ca4e95641c1b4a8e23c02728 | 0.371686 | 5.36229 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/xps_bram_if_cntlr_v1_00_b/hdl/vhdl/xbic_addr_be_support.vhd | 2 | 11,646 | -------------------------------------------------------------------------------
-- $Id: xbic_addr_be_support.vhd,v 1.2.2.1 2008/12/16 22:23:17 dougt Exp $
-------------------------------------------------------------------------------
-- xbic_addr_be_support.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2007, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: xbic_addr_be_support.vhd
--
-- Description:
-- This VHDL file implements the logic to combine the used portion of the
-- PLB_UABus with the PLB_ABus to form the actual internal address bus.
-- The module also implements the BE Mux that is required when the Slave
-- Native Data Width is less than the PLB data Bus width
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- xps_bram_if_cntlr.vhd
-- |
-- |- xbic_slave_attach_sngl
-- | |
-- | |- xbic_addr_decode
-- | |- xbic_addr_be_support
-- | |- xbic_data_steer_mirror
-- |
-- |- xbic_slave_attach_burst
-- |
-- |- xbic_addr_decode
-- |- xbic_addr_be_support
-- |- xbic_data_steer_mirror
-- |- xbic_addr_cntr
-- | |
-- | |- xbic_be_reset_gen.vhd
-- |
-- |- xbic_dbeat_control
-- |- xbic_data_steer_mirror
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.2.2.1 $
-- Date: $2/12/2007$
--
-- History:
-- DET 2/12/2007 Initial Version
--
-- DET 9/9/2008 v1_00_b for EDK 11.x release
-- ~~~~~~
-- - Updated Disclaimer in header section.
-- ^^^^^^
--
-- DET 12/16/2008 v1_01_b
-- ~~~~~~
-- - Updated eula/header to latest version.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim; -- Required for Xilinx primitives
use unisim.all;
-------------------------------------------------------------------------------
entity xbic_addr_be_support is
generic (
C_SPLB_DWIDTH : Integer := 32;
C_SPLB_AWIDTH : Integer := 32;
C_SPLB_NATIVE_DWIDTH : Integer := 32
);
port (
-- Inputs from PLB
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_Msize : In std_logic_vector(0 to 1);
-- Outputs to Internal logic
Internal_ABus : out std_logic_vector(0 to C_SPLB_AWIDTH-1);
Internal_BE : out std_logic_vector(0 to (C_SPLB_NATIVE_DWIDTH/8)-1)
);
end entity xbic_addr_be_support;
architecture implementation of xbic_addr_be_support is
-- Constants
Constant UPPER_ADDR_SIZE : integer := C_SPLB_AWIDTH-32;
-- Signals
signal sig_combined_abus : std_logic_vector(0 to C_SPLB_AWIDTH-1);
begin --(architecture implementation)
Internal_ABus <= sig_combined_abus;
------------------------------------------------------------
-- If Generate
--
-- Label: ADDRESS_EQ_32
--
-- If Generate Description:
-- This IfGen hooks up the PLB_ABus when the
-- total number of address bits used is equal to 32.
-- In this case, the PLB_UABus is ignored.
------------------------------------------------------------
ADDRESS_EQ_32 : if (C_SPLB_AWIDTH = 32) generate
begin
sig_combined_abus <= PLB_ABus;
end generate ADDRESS_EQ_32;
------------------------------------------------------------
-- If Generate
--
-- Label: ADDRESS_GT_32
--
-- If Generate Description:
-- This IfGen combines the used portion of the PLB_UABus
-- with the PLB_ABus when the total number of address bits
-- used is greater than 32 but less than 64.
--
------------------------------------------------------------
ADDRESS_GT_32 : if (C_SPLB_AWIDTH > 32 and
C_SPLB_AWIDTH < 64) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_ADDR
--
-- Process Description:
-- Combine the Upper and Lower address bus values into the
-- address bus used internally.
--
-------------------------------------------------------------
ASSIGN_ADDR : process (PLB_UABus,
PLB_ABus)
begin
-- Rip the used upper PLB addr bus bits and merge
-- into the most significant address bits
sig_combined_abus(0 to UPPER_ADDR_SIZE-1) <=
PLB_UABus((32-UPPER_ADDR_SIZE) to 31);
-- Assign least significant addr bus bits
sig_combined_abus(C_SPLB_AWIDTH-32 to
C_SPLB_AWIDTH-1)
<= PLB_ABus;
end process ASSIGN_ADDR;
end generate ADDRESS_GT_32;
------------------------------------------------------------
-- If Generate
--
-- Label: ADDRESS_EQ_64
--
-- If Generate Description:
-- This IfGen merges the PLB_UABus and the PLB_ABus when
-- the total number of address bits used is equal to 64.
--
------------------------------------------------------------
ADDRESS_EQ_64 : if (C_SPLB_AWIDTH = 64) generate
begin
sig_combined_abus(0 to 31) <= PLB_UABus ;
sig_combined_abus(32 to 63) <= PLB_ABus ;
end generate ADDRESS_EQ_64;
------------------------------------------------------------
-- If Generate
--
-- Label: PLB_EQ_SLAVE
--
-- If Generate Description:
-- Connects the PLB Be to the internal BE bus. No muxing
-- required when the PLB and the Slave are the same data width.
--
------------------------------------------------------------
PLB_EQ_SLAVE : if (C_SPLB_DWIDTH = C_SPLB_NATIVE_DWIDTH) generate
begin
Internal_BE <= PLB_BE;
end generate PLB_EQ_SLAVE;
------------------------------------------------------------
-- If Generate
--
-- Label: PLB64_SLAVE32
--
-- If Generate Description:
-- Muxes the PLB BE to the internal BE bus when the PLB
-- data Width is 64 bits and the Slave data width is 32 bits.
--
------------------------------------------------------------
PLB64_SLAVE32 : if (C_SPLB_DWIDTH = 64 and
C_SPLB_NATIVE_DWIDTH = 32) generate
begin
Internal_BE <= PLB_BE(4 to 7)
When PLB_ABus(29) = '1'
Else PLB_BE(0 to 3);
end generate PLB64_SLAVE32;
------------------------------------------------------------
-- If Generate
--
-- Label: PLB128_SLAVE32
--
-- If Generate Description:
-- Muxes the PLB BE to the internal BE bus when the PLB
-- data Width is 128 bits and the Slave data width is 32 bits.
--
------------------------------------------------------------
PLB128_SLAVE32 : if (C_SPLB_DWIDTH = 128 and
C_SPLB_NATIVE_DWIDTH = 32) generate
begin
Internal_BE <= PLB_BE(12 to 15)
When PLB_ABus(28 to 29) = "11"
Else PLB_BE(8 to 11)
When PLB_ABus(28 to 29) = "10"
Else PLB_BE(4 to 7)
When PLB_ABus(28 to 29) = "01"
Else PLB_BE(0 to 3);
end generate PLB128_SLAVE32;
------------------------------------------------------------
-- If Generate
--
-- Label: PLB128_SLAVE64
--
-- If Generate Description:
-- Muxes the PLB BE to the internal BE bus when the PLB
-- data Width is 128 bits and the Slave data width is 64 bits.
--
------------------------------------------------------------
PLB128_SLAVE64 : if (C_SPLB_DWIDTH = 128 and
C_SPLB_NATIVE_DWIDTH = 64) generate
begin
Internal_BE <= PLB_BE(8 to 15)
When PLB_ABus(28) = '1'
Else PLB_BE(0 to 7);
end generate PLB128_SLAVE64;
end implementation;
| bsd-3-clause | e1da69ce9411acf0c8b29502e0373ab4 | 0.472093 | 4.621429 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ipif_control_rd.vhd | 3 | 35,921 | -------------------------------------------------------------------------------
-- $Id: ipif_control_rd.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
--ipif_control_rd.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_control_rd.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Read Packet FIFO IPIF Local Bus Interface control
-- block.
--
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs. Separate lines with blank lines if necessary to
-- improve readability.
--
-- ipif_control_rd.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe March 19,2001 -- V1.00a
--
-- Doug Thorpe June 08-12,2001 -- V1.00b
-- - Corrected an error condition where the FIFO2Bus_Error was getting set
-- at the end of a legitimate burst read operation. If the RdFIFO goes
-- empty after the initiation of the read (at least one FIFO2Bus_RdAck
-- has been issued), an 'Empty' condition causes only an inhibit of the
-- FIFO2Bus_RdAck signal.
-- - Fixed the implimentation of the MIR inclusion/occlusion through the
-- use of if--generate clauses.
--
-- DET June 25, 2001 V1.00c
-- - Removed redundant logic assignments flagged by
-- Synplicity
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
-- DET Aug 20, 2001 Version v1.01a
-- - Platform Generator Compliancy modifications
--
-- DET Sept 17, 2001
-- - Size optimization changes
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
entity ipif_control_rd is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for disable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_INTFC_TYPE : integer range 0 to 31 := 1;
-- IPIF block protocol Type
C_VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning of top level design
C_VERSION_MINOR : integer range 0 to 99 := 2;
-- Minor Version of top level design
C_VERSION_REV : integer range 0 to 26 := 0;
-- Revision letter of top level design
C_FIFO_WIDTH : Integer := 32;
-- Width of FIFO data in bits
C_DP_ADDRESS_WIDTH : Integer := 9;
-- Indicates address width of RdFIFO memory
-- (= log2(fifo_depth)
C_SUPPORT_BURST : Boolean := true;
-- Indicates read burst support for the IPIF bus
C_IPIF_DBUS_WIDTH : Integer := 32
-- Width of the IPIF data bus in bits
);
port (
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_Clk : In std_logic; -- Master timing clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(C_IPIF_DBUS_WIDTH-4 to
C_IPIF_DBUS_WIDTH-1);
-- Inputs from the FIFO Interface Logic
Fifo_rd_data : In std_logic_vector(0 to C_FIFO_WIDTH-1);
BRAMFifo_RdAck : In std_logic;
SRLFifo_RdAck : In std_logic;
Occupancy : In std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
AlmostEmpty : In std_logic;
Empty : In std_logic;
Deadlock : In std_logic;
-- Outputs to the FIFO
Fifo_rst : Out std_logic;
BRAMFifo_RdReq : Out std_logic;
SRLFifo_RdReq : Out std_logic;
Fifo_burst_rd_xfer : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock : Out std_logic;
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end ipif_control_rd ;
-------------------------------------------------------------------------------
architecture implementation of ipif_control_rd is
-- COMPONENTS
-- No components
--TYPES
-- no types
-- CONSTANTS
-- Module Software Reset screen value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- This requires a Hex 'A' to be written
-- to ativate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
signal bus_data_out : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal sw_reset_error : std_logic;
signal reg_occupancy : std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Signal reg_almostempty : std_logic;
Signal reg_empty : std_logic;
Signal reg_deadlock : std_logic;
Signal reg_rdce2 : std_logic;
Signal reg_wrce1 : std_logic;
Signal reg_rdreq : std_logic;
Signal read_ack : std_logic;
Signal reg_read_ack : std_logic;
Signal write_ack : std_logic;
Signal rd_access_error : std_logic;
Signal wr_access_error : std_logic;
Signal burst_rd_xfer : std_logic;
Signal read_req : std_logic;
Signal reg_read_req : std_logic;
Signal write_req : std_logic;
Signal fifo_rd_req : std_logic;
Signal fifo_errack_inhibit : std_logic;
Signal rd_vect : std_logic_vector(0 to 3);
Signal sig_srl_rdack : std_logic;
Signal sig_bram_rdack : std_logic;
Signal sig_rst_match : std_logic;
Signal sig_rst_vect : std_logic_vector(0 to 1);
Signal sig_fifo_rd_data : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-------------------------------------------------------------------------------
---------- start architecture logic -------------------------------------------
begin
-- General access detection (used to terminate reply signal to the Bus)
read_req <= (Bus2FIFO_RdCE1 or Bus2FIFO_RdCE2 or Bus2FIFO_RdCE3);
write_req <= (Bus2FIFO_WrCE1 or Bus2FIFO_WrCE2 or Bus2FIFO_WrCE3);
-- I/O assignments
FIFO2Bus_DBus <= bus_data_out;
FIFO2Bus_ToutSup <= LOGIC_LOW; -- output signal not currently used so
-- drive low .
FIFO2Bus_Retry <= LOGIC_LOW; -- output signal not currently used so
-- drive low.
FIFO2Bus_WrAck <= write_ack and write_req; -- connect the write
-- acknowledge (drive only
-- if a request is present)
FIFO2Bus_RdAck <= read_ack and read_req; -- connect the read
-- acknowledge (drive only if
-- a request is present)
FIFO2Bus_Error <= (sw_reset_error or
rd_access_error or
wr_access_error) and
(read_req or write_req);
FIFO2IRPT_DeadLock <= Deadlock;
BRAMFifo_RdReq <= Bus_RdReq and Bus2FIFO_RdCE3; -- Read Request to BRAM
-- based FIFO.
SRLFifo_RdReq <= reg_rdreq and Bus2FIFO_RdCE3; -- Read Request to SRL
-- based FIFO
Fifo_burst_rd_xfer <= burst_rd_xfer; -- Burst detect signal to FIFO read
-- controller
sig_srl_rdack <= SRLFifo_RdAck;
sig_bram_rdack <= BRAMFifo_RdAck;
------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The FIFO data bus width is smaller than the IPIF data bus width so connect
-- the smaller FIFO data to LSB position of data bus to IPIF interface and
-- set the remaining data bus bits to zeroes.
-------------------------------------------------------------------------------
BUS_BIGGER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH > C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
sig_fifo_rd_data <= (others => '0'); --default bus state
for j in 0 to C_FIFO_WIDTH-1 loop
sig_fifo_rd_data(C_IPIF_DBUS_WIDTH-C_FIFO_WIDTH+j)
<= fifo_rd_data(j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_BIGGER_THAN_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is equal to the IPIF data bus width so connect
-- the FIFO data to IPIF data interface.
-------------------------------------------------------------------------------
BUS_EQUAL_TO_FIFO : if (C_IPIF_DBUS_WIDTH = C_FIFO_WIDTH) generate
sig_fifo_rd_data <= fifo_rd_data;
end generate BUS_EQUAL_TO_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is bigger than the IPIF data bus width !!BAD!!!
-- Connect the LSBits of the FIFO data to the IPIF data bus interface,
-- Don't use (truncate) the MSBits of the FIFO data spilling over the IPIF
-- data bus width.
-------------------------------------------------------------------------------
BUS_SMALLER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH < C_FIFO_WIDTH) generate
CONNECT_DBUS : process (fifo_rd_data)
Begin
for j in C_IPIF_DBUS_WIDTH-1 downto 0 loop
sig_fifo_rd_data(j) <= fifo_rd_data(C_FIFO_WIDTH-
C_IPIF_DBUS_WIDTH+j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_SMALLER_THAN_FIFO;
------------------------------------------------------------------------------
-- Register the input chip enables
------------------------------------------------------------------------------
REGISTER_CHIP_ENABLES : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_rdce2 <= '0';
reg_wrce1 <= '0';
reg_rdreq <= '0';
reg_read_req <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
reg_rdce2 <= Bus2FIFO_RdCE2;
reg_wrce1 <= Bus2FIFO_WrCE1;
reg_rdreq <= Bus_RdReq;
reg_read_req <= read_req;
Else
null;
End if;
End process; -- REGISTER_CHIP_ENABLES
INCLUDE_BURST : if (C_SUPPORT_BURST = true) generate
--burst_rd_xfer <= reg_rdreq and Bus_RdReq;
-------------------------------------------------------------------------
-- This process detects the completion of at least one valid FIFO data
-- read cycle during a burst read.
-------------------------------------------------------------------------
GEN_ERRACK_INHIB : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
fifo_errack_inhibit <= '0';
burst_rd_xfer <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1' ) Then
burst_rd_xfer <= reg_rdreq and Bus_RdReq;
If (Bus2FIFO_RdCE3 = '1' and sig_bram_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and sig_srl_rdack = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_RdCE3 = '0') Then
fifo_errack_inhibit <= '0';
else
null;
End if;
else
null;
End if;
End process; -- GEN_ERRACK_INHIB
end generate INCLUDE_BURST;
OMIT_BURST : if (C_SUPPORT_BURST = false) generate
burst_rd_xfer <= '0';
fifo_errack_inhibit <= '0';
end generate OMIT_BURST;
-------------------------------------------------------------------------------
-- Assemble and latch the FIFO status register fields
-------------------------------------------------------------------------------
GET_STATUS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_occupancy <= (others => '0');
reg_deadlock <= '0';
reg_almostempty <= '0';
reg_empty <= '1';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
If (reg_rdce2 = '1') Then -- hold last value registered during
-- read operation.
null;
else -- register new status every clock
reg_occupancy <= Occupancy ;
reg_deadlock <= Deadlock ;
reg_almostempty <= AlmostEmpty ;
reg_empty <= Empty ;
End if;
else
null; -- do nothing
End if;
End process; -- GET_STATUS
sig_rst_match <= Bus_DBus(C_IPIF_DBUS_WIDTH-4)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-3))
and Bus_DBus(C_IPIF_DBUS_WIDTH-2)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-1));
sig_rst_vect <= sig_rst_match & Bus2FIFO_WrCE1;
------------------------------------------------------------------------------
-- Generate the S/W reset as a result of an IPIF Bus write to register
-- port 1 and data on the DBus inputs matching the Reset match value.
------------------------------------------------------------------------------
GENERATE_SOFTWARE_RESET : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
Fifo_rst <= '1';
sw_reset_error <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
Case sig_rst_vect Is
When "11" =>
Fifo_rst <= '1';
sw_reset_error <= '0';
When "01" =>
Fifo_rst <= '0';
sw_reset_error <= '1';
When others =>
Fifo_rst <= '0';
sw_reset_error <= '0';
End case;
Else
null;
End if;
End process; -- GENERATE_SOFTWARE_RESET
-- Synthesis for MIR inclusion ------------------------------------------------
Include_MIR :if (C_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
Signal mir_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics and Constants
-- Conversion to std_logic_vector is required
----------------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MAJOR, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MINOR, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_VERSION_REV, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_BLOCK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_INTFC_TYPE, 8);
BUS_LEQ_32 : if (C_IPIF_DBUS_WIDTH <= 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
for j in 0 to C_IPIF_DBUS_WIDTH-1 loop
mir_bus(j) <= mir_value((32-C_IPIF_DBUS_WIDTH)+j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_LEQ_32;
BUS_GT_32 : if (C_IPIF_DBUS_WIDTH > 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
mir_bus <= (others => '0'); -- default bus values
for j in 0 to 31 loop
mir_bus((C_IPIF_DBUS_WIDTH-32)+j) <= mir_value(j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_GT_32;
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0';
-- Occupancy is not scaled in this case.
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '1'; -- occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, mir_bus, status_bus,
sig_fifo_rd_data, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1001" => -- Read MIR port
bus_data_out <= mir_bus;
When "1010" => -- Read Status port
bus_data_out <= status_bus;
When "1100" => -- Read FIFO data port
bus_data_out <= sig_fifo_rd_data;
When others => -- default to zeroes
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Include_MIR;
-------------------------------------------------------------------------------
-- Synthesis for MIR occlusion
-------------------------------------------------------------------------------
Occlude_MIR : if (C_MIR_ENABLE = False) generate
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled in this case.
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostempty ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the occupancy value down.
-- Note status_bus bit 3 is not set, signaling a complete occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the occupancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled occupancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostempty, reg_empty,
reg_occupancy)
Begin
status_bus(4 to C_IPIF_DBUS_WIDTH-1) <= (others => '0');
-- set default bus values
status_bus(3) <= '1' ;
-- Indicate occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostempty;
status_bus(0) <= reg_empty ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_occupancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, sig_fifo_rd_data,
status_bus, rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1010" =>
bus_data_out <= status_bus;
When "1100" =>
bus_data_out <= sig_fifo_rd_data;
When others =>
bus_data_out <= (others => '0');
End case;
End process ; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE1 = '1') Then -- attempting to read MIR but it
-- is not included
rd_access_error <= '1';
Elsif (Bus2FIFO_RdCE3 = '1' and Empty = '1' and
fifo_errack_inhibit = '0') Then -- attempting to read the
-- rdfifo with an empty
rd_access_error <= '1'; -- condition is an error,
-- but only on the
-- initiation of the read
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Occlude_MIR;
-------------------------------------------------------------------------------
-- Generate the Read Acknowledge to the Bus
-------------------------------------------------------------------------------
GEN_READ_ACK : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
reg_read_ack <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE1 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE2 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE3 = '1') Then
reg_read_ack <= sig_bram_rdack;
else
reg_read_ack <= '0';
End if;
Else
null;
End if;
End process; -- GEN_READ_ACK
read_ack <= reg_read_ack
or rd_access_error
or sig_srl_rdack;
write_ack <= reg_wrce1 or wr_access_error;
-------------------------------------------------------------------------------
-- Generate the Write Error Acknowledge Reply to the Bus when
-- an attempted write access by the IPIF Local Bus is invalid
-------------------------------------------------------------------------------
--GEN_WR_ERROR : process (Bus2FIFO_WrCE2, Bus2FIFO_WrCE3)
GEN_WR_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
wr_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_WrCE2 = '1') Then -- attempting to write to the status
-- register.
wr_access_error <= '1';
ElsIf (Bus2FIFO_WrCE3 = '1') Then -- attempting a write to the FIFO
-- Read data port.
wr_access_error <= '1';
Else
wr_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_WR_ERROR
end implementation;
| bsd-3-clause | 20bfb00046837a03a04a8cb529e86792 | 0.409036 | 4.801631 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_slave.vhd | 1 | 34,588 | --------------------------------------------------------------------------------
-- Title : VME Slave
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_slave.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 11/02/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The WBB2VME core supports 5 independent VME slave windows. These windows are
-- disabled per default and can be enabled via register bits SLENx.
-- If a slave window is enabled, the base address must be set to an appropriate
-- value. The window defined by base address and size must be unique on the
-- VMEbus in order to prevent VMEbus signals driven by more than one slave!
-- Three slave windows (SLV16, SLV24 and SLV32) are capable to access the local
-- SRAM (VME slave base address = 0x0 of local SRAM). The local SRAM can be
-- accessed from CPU, DMA, Mailbox and VME slave, which must be well organized
-- in order to prevent data mismatch!
-- Two slave windows (SLV24_PCI and SLV32_PCI) are capable to access the PCI
-- address space at an offset address defined in register PCI_OFFSET. The
-- offset will be added to the VME address during each access to the PCI space.
-- The address modifiers for these VME slave windows cannot be configured, but
-- all common types are supported:
-- Hex 543210 Function
-- 0x3F HHHHHH A24 supervisory block transfer (BLT)
-- 0x3E HHHHHL A24 supervisory program transfer
-- 0x3D HHHHLH A24 supervisory data transfer
-- 0x3C HHHHLL A24 supervisory 64-bit block transfer (MBLT)
-- 0x3B HHHLHH A24 non privileged block transfer (BLT)
-- 0x3A HHHLHL A24 non privileged program transfer
-- 0x39 HHHLLH A24 non privileged data transfer
-- 0x38 HHHLLL A24 non privileged 64-bit block transfer (MBLT)
-- 0x2D HLHHLH A16 supervisory transfer
-- 0x29 HLHLLH A16 non-privileged transfer
-- 0x0F LLHHHH A32 supervisory block transfer (BLT)
-- 0x0E LLHHHL A32 supervisory program transfer
-- 0x0D LLHHLH A32 supervisory data transfer
-- 0x0C LLHHLL A32 supervisory 64-bit block transfer (MBLT)
-- 0x0B LLHLHH A32 non privileged block transfer (BLT)
-- 0x0A LLHLHL A32 non privileged program transfer
-- 0x09 LLHLLH A32 non privileged data transfer
-- 0x08 LLHLLL A32 non privileged 64-bit block transfer (MBLT)
--------------------------------------------------------------------------------
-- Hierarchy:
--
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.5 $
--
-- $Log: vme_slave.vhd,v $
-- Revision 1.5 2015/04/07 14:30:11 AGeissler
-- R1: MAIN_PR002233
-- M1.1: Added signal sl_acc_valid, which shows that the sl_acc is
-- stable and can be used
-- M1.2: Added signal asn_in_sl_reg, which is the synchronized asn
-- PIN signal with one register
-- M1.3: Wait until sl_acc is stable, before switching to sl_vme_req
-- R2: Clearness
-- M2: Removed unused comments and signals
--
-- Revision 1.4 2015/03/30 15:23:01 AGeissler
-- R1: If there is a write request from the master to one of a VME slave card and than another write
-- access to a different VME slave card is directly followed, the previous VME slave card acknowledge the write
-- access again even if it is not selected. This cause a VME bus error on the VME master. (MAIN_PR002233)
-- M1: The ld_loc_adr signal shall be generated directly from the conditional signals and not stored in a register,
-- that a new incomming address by the VME bus when address strob is active is stored and evaluated before
-- a new access to the old address is performed.
--
-- Revision 1.3 2012/09/25 11:21:41 MMiehling
-- removed unused signals
--
-- Revision 1.2 2012/08/27 12:57:09 MMiehling
-- general rework of d64 access handling
--
-- Revision 1.1 2012/03/29 10:14:32 MMiehling
-- Initial Revision
--
-- Revision 1.8 2004/07/27 17:15:44 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.7 2004/06/17 13:02:31 MMiehling
-- removed clr_hit and sl_acc_reg
--
-- Revision 1.6 2003/12/17 15:51:52 MMiehling
-- improved performance
--
-- Revision 1.5 2003/12/01 10:04:00 MMiehling
-- added d64
--
-- Revision 1.4 2003/06/24 13:47:15 MMiehling
-- added loc_keep
--
-- Revision 1.3 2003/06/13 10:06:44 MMiehling
-- improved timing
--
-- Revision 1.2 2003/04/22 11:03:06 MMiehling
-- improved request - acknowledge
--
-- Revision 1.1 2003/04/01 13:04:47 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vme_pkg.ALL;
ENTITY vme_slave IS
PORT (
clk : IN std_logic; -- this Unit works at 66 MHz
rst : IN std_logic;
-------------------------------------------------------------------------------
-- PINS (VMEbus, inputs asynchronous !):
asn_in : IN std_logic; -- vme adress strobe input
dsan_in : IN std_logic; -- vme data strobe A input
dsbn_in : IN std_logic; -- vme data strobe B input
dtackn_out : OUT std_logic; -- vme data acknowledge output
sl_writen_reg : IN std_logic; -- vme read/write
-------------------------------------------------------------------------------
-- vme-mstr
mstr_busy : IN std_logic; -- if set, vme-master is busy
-- vme_au
sl_acc : IN std_logic_vector(4 DOWNTO 0); -- A16 hit, A24 hit, A32 hit, D32 blt, D64 blt
sl_acc_valid : IN std_logic; -- sl_acc has been calculated and is valid
my_iack : IN std_logic;
wbm_we_o : IN std_logic; -- mensb master read/write
reg_acc : IN std_logic; -- reg access is requested by vmebus
en_vme_adr_in : OUT std_logic; -- samples adress and am after asn goes low
asn_in_sl_reg : OUT std_logic; -- registered asn signal
-- sys_arbiter
slave_req : OUT std_logic; -- request signal for slave access
slave_active : IN std_logic; -- acknowledge/active signal for slave access
sl_write_flag : OUT std_logic; -- write flag for register access from vme side
sl_second_word : OUT std_logic; -- differs between address and data phase in d64 accesses
-- vme_du
sl_en_vme_data_in_reg : OUT std_logic; -- enable vme input reg
sl_en_vme_data_in_reg_high : OUT std_logic; -- slave enable of vme data high in registers
sl_oe_vd : OUT std_logic; -- output enable for vme data
sl_oe_va : OUT std_logic; -- output enable for vme adress
reg_en_vme_data_out_reg : OUT std_logic; -- enable vme output reg
sl_io_ctrl : OUT io_ctrl_type;
ld_loc_adr_m_cnt : OUT std_logic; -- load address counter
sl_inc_loc_adr_m_cnt : OUT std_logic; -- increment address counter
clr_intreq : OUT std_logic; -- clear interrupt request (intr(3) <= '0'
-- mensb_master
loc_keep : OUT std_logic; -- if '1', csn remains active (keeps bus)
mensb_mstr_req : OUT std_logic; -- mensb master request
mensb_mstr_ack : IN std_logic -- mensb master acknowledge
);
END vme_slave;
ARCHITECTURE vme_slave_arch OF vme_slave IS
TYPE sl_states IS (sl_idle, sl_vme_req, sl_vme_req2, sl_vme_ack, sl_wait_1, sl_wait_ondata, sl_wait_on_dsn, sl_got_dsn);
SIGNAL sl_state : sl_states;
TYPE req_states IS(idle, req);
SIGNAL req_state, req_nxtstate : req_states;
SIGNAL dsan_in_reg : std_logic;
SIGNAL dsbn_in_reg : std_logic;
SIGNAL asn_in_reg : std_logic;
SIGNAL request : std_logic;
SIGNAL acknowledge : std_logic;
SIGNAL sl_end : std_logic;
SIGNAL dtackn_out_reg : std_logic;
SIGNAL ld_loc_adr : std_logic;
SIGNAL slave_req_int : std_logic;
SIGNAL slave_active_reg : std_logic;
SIGNAL first_cycle : std_logic;
SIGNAL asn_in_reg2 : std_logic;
SIGNAL mstr_busy_q : std_logic;
BEGIN
asn_in_sl_reg <= asn_in_reg;
slave_req <= slave_req_int;
ld_loc_adr_m_cnt <= ld_loc_adr;
sl_second_word <= NOT first_cycle;
reg_en_vme_data_out_reg <= '1' WHEN slave_active = '1' AND (reg_acc = '1' OR my_iack = '1') ELSE '0';
loc_keep <= '1' WHEN asn_in_reg = '1' AND asn_in_reg2 = '0' ELSE '0';
sl_inc_loc_adr_m_cnt <= '1' WHEN (mensb_mstr_ack = '1' AND wbm_we_o = '1') ELSE -- write access
'1' WHEN (sl_end = '1' AND wbm_we_o = '0' AND NOT sl_acc(0) = '1') ELSE -- read access
'0';
en_vme_adr_in <= '1' WHEN asn_in_reg = '0' AND asn_in_reg2 = '1' ELSE '0'; -- detect falling edge
req_sta : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
req_state <= idle;
slave_active_reg <= '0';
mstr_busy_q <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
req_state <= req_nxtstate;
slave_active_reg <= slave_active;
mstr_busy_q <= mstr_busy;
END IF;
END PROCESS req_sta;
req_fsm : PROCESS (req_state, request, reg_acc, my_iack, slave_active_reg, mensb_mstr_ack)
BEGIN
CASE req_state IS
WHEN idle =>
IF my_iack = '0' AND reg_acc = '0' AND request = '1' THEN
req_nxtstate <= req;
mensb_mstr_req <= '1';
acknowledge <= '0';
slave_req_int <= '0';
ELSIF (my_iack = '1' OR reg_acc = '1') AND request = '1' THEN
req_nxtstate <= req;
mensb_mstr_req <= '0';
acknowledge <= '0';
slave_req_int <= '1';
ELSE
req_nxtstate <= idle;
mensb_mstr_req <= '0';
acknowledge <= '1';
slave_req_int <= '0';
END IF;
WHEN req =>
IF my_iack = '0' AND reg_acc = '0' THEN
IF mensb_mstr_ack = '1' THEN
req_nxtstate <= idle;
mensb_mstr_req <= '1'; -- keep for this cycle
acknowledge <= '1';
slave_req_int <= '0';
ELSE
req_nxtstate <= req;
mensb_mstr_req <= '1'; -- wait for acknowledge
acknowledge <= '0';
slave_req_int <= '0';
END IF;
ELSE
IF slave_active_reg = '1' THEN
req_nxtstate <= idle;
mensb_mstr_req <= '0';
acknowledge <= '1'; -- keep for this cycle
slave_req_int <= '1';
ELSE
req_nxtstate <= req;
mensb_mstr_req <= '0';
acknowledge <= '0';
slave_req_int <= '1'; -- wait for acknowledge
END IF;
END IF;
WHEN OTHERS =>
req_nxtstate <= idle;
mensb_mstr_req <= '0';
acknowledge <= '1';
slave_req_int <= '0';
END CASE;
END PROCESS req_fsm;
reg : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
asn_in_reg <= '1';
asn_in_reg2 <= '1';
dsan_in_reg <= '1';
dsbn_in_reg <= '1';
clr_intreq <= '0';
dtackn_out <= '1';
sl_write_flag <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF reg_acc = '1' AND slave_active_reg = '0' AND slave_active = '1' AND wbm_we_o = '1' THEN
sl_write_flag <= '1';
ELSE
sl_write_flag <= '0';
END IF;
dtackn_out <= dtackn_out_reg;
asn_in_reg <= asn_in;
asn_in_reg2 <= asn_in_reg;
dsan_in_reg <= dsan_in;
dsbn_in_reg <= dsbn_in;
IF my_iack = '1' AND sl_end = '1' THEN
clr_intreq <= '1';
ELSE
clr_intreq <= '0';
END IF;
END IF;
END PROCESS reg;
ld_loc_adr <= '1' WHEN asn_in_reg = '0' AND (dsan_in_reg = '0' OR dsbn_in_reg = '0') AND acknowledge = '1' AND
mstr_busy = '0' AND mstr_busy_q = '0' AND sl_state = sl_idle AND sl_acc_valid = '1' AND
(sl_acc(4) = '1' OR sl_acc(3) = '1' OR sl_acc(2) = '1' OR my_iack = '1') ELSE '0';
sl_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sl_state <= sl_idle;
dtackn_out_reg <= '1';
request <= '0';
sl_en_vme_data_in_reg<= '0';
sl_oe_va <= '0';
sl_oe_vd <= '0';
sl_end <= '0';
first_cycle <= '0';
sl_en_vme_data_in_reg_high <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '1';
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE sl_state IS
WHEN sl_idle =>
IF ld_loc_adr = '1' THEN
sl_state <= sl_vme_req; -- if vme bus requests a transmission
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
first_cycle <= '1'; -- indicates adress cycle for d64 bursts
IF sl_writen_reg = '1' THEN -- read
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
ELSE -- write
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '0';
END IF;
ELSE
sl_state <= sl_idle; -- actions on vme bus are not for this slave
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '1';
first_cycle <= '0';
END IF;
dtackn_out_reg <= '1';
request <= '0';
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
sl_oe_vd <= '0';
sl_oe_va <= '0';
sl_end <= '0';
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
WHEN sl_vme_req =>
IF request = '0' AND acknowledge = '0' THEN -- wait until prior access is finished
sl_state <= sl_vme_req;
IF wbm_we_o = '0' AND sl_acc(0) = '0' THEN -- no d64
request <= '1'; -- set master request for read actions
ELSIF wbm_we_o = '0' AND sl_acc(0) = '1' AND first_cycle = '0' THEN
request <= '1'; -- set master request for read actions
ELSE
request <= '0';
END IF;
ELSIF wbm_we_o = '1' THEN -- if write access, then go on
sl_state <= sl_vme_ack;
request <= '0';
ELSIF wbm_we_o = '0' AND acknowledge = '1' AND request = '1' AND sl_acc(0) = '1' THEN -- read: requested data is available => go on
sl_state <= sl_vme_req2;
request <= '1'; -- req for second d32
ELSIF wbm_we_o = '0' AND acknowledge = '1' AND request = '1' THEN -- read: requested data is available => go on
sl_state <= sl_vme_ack;
request <= '0';
ELSIF wbm_we_o = '0' AND sl_acc(0) = '1' AND first_cycle = '1' THEN
sl_state <= sl_vme_ack; -- first d64 read cycle is only adress => no req
request <= '0';
ELSE -- wbm_we_o = '0' AND acknowledge = '1' AND request = '0' THEN -- if read access, then request internal data
sl_state <= sl_vme_req;
IF wbm_we_o = '0' THEN
request <= '1'; -- set master request for read actions
ELSE
request <= '0';
END IF;
END IF;
dtackn_out_reg <= '1';
sl_en_vme_data_in_reg <= '1';
sl_en_vme_data_in_reg_high <= '0';
IF wbm_we_o = '0' THEN
sl_oe_vd <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
ELSE
sl_oe_vd <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '0';
END IF;
sl_end <= '0';
first_cycle <= first_cycle;
IF wbm_we_o = '0' AND first_cycle = '0' AND sl_acc(0) = '1' THEN -- d64 read
sl_oe_va <= '1';
sl_io_ctrl.a_dir <= '1';
sl_io_ctrl.a_oe_n <= '0';
ELSE -- d64 write or non-d64
sl_oe_va <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
END IF;
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
WHEN sl_vme_req2 => -- wait on second d32 for d64 read access
IF acknowledge = '1' THEN
sl_state <= sl_vme_ack;
request <= '0';
ELSE
sl_state <= sl_vme_req2;
request <= '1';
END IF;
dtackn_out_reg <= '1';
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
sl_oe_vd <= '1';
sl_oe_va <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
sl_io_ctrl.a_dir <= '1';
sl_io_ctrl.a_oe_n <= '0';
sl_end <= '0';
first_cycle <= first_cycle;
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
WHEN sl_vme_ack =>
sl_state <= sl_wait_1;
dtackn_out_reg <= '1';
IF wbm_we_o = '0' THEN
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
sl_oe_vd <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
ELSE
IF sl_acc(0) = '1' THEN -- if sl_blt64
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '1'; -- if d64 then latch high d32
ELSE
sl_en_vme_data_in_reg <= '1'; -- if d32 then latch low d32
sl_en_vme_data_in_reg_high <= '0';
END IF;
sl_oe_vd <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '0';
END IF;
request <= '0';
sl_end <= '0';
first_cycle <= first_cycle;
IF wbm_we_o = '0' AND first_cycle = '0' AND sl_acc(0) = '1' THEN -- d64 read
sl_oe_va <= '1';
sl_io_ctrl.a_dir <= '1';
sl_io_ctrl.a_oe_n <= '0';
ELSE -- d64 write or non-d64
sl_oe_va <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
END IF;
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
WHEN sl_wait_1 =>
IF wbm_we_o = '0' THEN
sl_state <= sl_wait_ondata; -- if read access, another wait state is required
dtackn_out_reg <= '1';
request <= '0';
sl_oe_vd <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
ELSE
IF sl_acc(0) = '1' AND first_cycle = '1' THEN
request <= '0'; -- no request when adress cycle of d64 burst
ELSE
request <= '1'; -- master request for write action now, because data on mensb is valid
END IF;
sl_state <= sl_wait_on_dsn;
dtackn_out_reg <= '0';
sl_oe_vd <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '0';
END IF;
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
sl_end <= '0';
first_cycle <= first_cycle;
IF wbm_we_o = '0' AND first_cycle = '0' AND sl_acc(0) = '1' THEN -- d64 read
sl_oe_va <= '1';
sl_io_ctrl.a_dir <= '1';
sl_io_ctrl.a_oe_n <= '0';
ELSE -- d64 write or non-d64
sl_oe_va <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
END IF;
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
WHEN sl_wait_ondata =>
IF acknowledge = '1' THEN
sl_state <= sl_wait_on_dsn;
ELSE
sl_state <= sl_wait_ondata;
END IF;
dtackn_out_reg <= '1';
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
request <= '0';
sl_oe_vd <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
sl_end <= '0';
first_cycle <= first_cycle;
IF wbm_we_o = '0' AND first_cycle = '0' AND sl_acc(0) = '1' THEN -- d64 read
sl_oe_va <= '1';
sl_io_ctrl.a_dir <= '1';
sl_io_ctrl.a_oe_n <= '0';
ELSE -- d64 write or non-d64
sl_oe_va <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
END IF;
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
WHEN sl_wait_on_dsn =>
IF dsan_in_reg = '1' AND dsbn_in_reg = '1' THEN
sl_state <= sl_got_dsn;
ELSE
sl_state <= sl_wait_on_dsn;
END IF;
IF wbm_we_o = '0' THEN
sl_oe_vd <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
ELSE
sl_oe_vd <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '0';
END IF;
dtackn_out_reg <= '0';
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
request <= '0';
sl_end <= '0';
first_cycle <= first_cycle;
IF wbm_we_o = '0' AND first_cycle = '0' AND sl_acc(0) = '1' THEN -- d64 read
sl_oe_va <= '1';
sl_io_ctrl.a_dir <= '1';
sl_io_ctrl.a_oe_n <= '0';
ELSE -- d64 write or non-d64
sl_oe_va <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
END IF;
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
WHEN sl_got_dsn =>
IF sl_acc(1) = '1' AND asn_in_reg = '0' THEN -- d32 burst access
sl_oe_va <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '1';
IF wbm_we_o = '0' THEN
sl_oe_vd <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
ELSE
sl_oe_vd <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '0';
END IF;
IF (dsan_in_reg = '0' OR dsbn_in_reg = '0') THEN -- wait on new dsn for next burst transmission
sl_state <= sl_vme_req;
sl_end <= '1'; -- used for incrementing adress
ELSE
sl_state <= sl_got_dsn;
sl_end <= '0';
END IF;
request <= '0';
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
ELSIF sl_acc(0) = '1' AND asn_in_reg = '0' THEN -- d64 burst access
IF (dsan_in_reg = '0' OR dsbn_in_reg = '0') AND acknowledge = '1' THEN -- wait on new dsn for next burst transmission
sl_state <= sl_vme_req;
sl_en_vme_data_in_reg <= '1'; -- latch next low d32
sl_en_vme_data_in_reg_high <= '0';
IF first_cycle = '1' THEN
sl_end <= '0'; -- no increment, because first d64 is address cycle
ELSE
sl_end <= '1'; -- used for incrementing adress
END IF;
IF wbm_we_o = '0' THEN
sl_oe_vd <= '1';
sl_oe_va <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
sl_io_ctrl.a_dir <= '1';
sl_io_ctrl.a_oe_n <= '0'; -- activate address lines for d64 read
ELSE
sl_oe_vd <= '0';
sl_oe_va <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0'; -- activate address lines for d64 write
END IF;
ELSE
sl_state <= sl_got_dsn;
sl_end <= '0';
IF wbm_we_o = '0' THEN
sl_oe_vd <= '1';
sl_oe_va <= '1';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '0';
sl_io_ctrl.a_dir <= '1';
sl_io_ctrl.a_oe_n <= '0'; -- activate address lines for d64 read
ELSE
sl_oe_vd <= '0';
sl_oe_va <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0'; -- activate address lines for d64 write
END IF;
END IF;
request <= '0';
ELSE
sl_state <= sl_idle;
sl_end <= '1';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
sl_oe_vd <= '0';
sl_oe_va <= '0';
sl_io_ctrl.d_dir <= '0';
sl_io_ctrl.d_oe_n <= '1';
request <= '0';
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
END IF;
dtackn_out_reg <= '1';
first_cycle <= '0';
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
WHEN OTHERS =>
sl_state <= sl_idle;
dtackn_out_reg <= '1';
request <= '0';
sl_en_vme_data_in_reg <= '0';
sl_en_vme_data_in_reg_high <= '0';
sl_oe_vd <= '0';
sl_oe_va <= '0';
sl_io_ctrl.a_dir <= '0';
sl_io_ctrl.a_oe_n <= '0';
sl_io_ctrl.d_dir <= '1';
sl_io_ctrl.d_oe_n <= '1';
sl_end <= '0';
first_cycle <= first_cycle;
sl_io_ctrl.am_dir <= '0';
sl_io_ctrl.am_oe_n <= '0';
END CASE;
END IF;
END PROCESS sl_fsm;
END vme_slave_arch;
| gpl-3.0 | a47d34c9263aaa073c306f7234192371 | 0.375072 | 4.061054 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/ip_16z091_01_top.vhd | 1 | 130,069 | --------------------------------------------------------------------------------
-- Title : top level module for 16z091-01 design
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : ip_16z091_01_top
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 23.02.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a
-- Synthesis : Quartus II 10.0
--------------------------------------------------------------------------------
-- Description :
-- Toplevel module that combines the 16z091-01 IP core with the Altera hard
-- makro PCIe IP core
--------------------------------------------------------------------------------
-- Hierarchy :
-- * ip_16z091_01_top_core
-- ip_16z091_01
-- Hard_IP
-- z091_01_wb_adr_dec
-- pcie_msi
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.fpga_pkg_2.all;
entity ip_16z091_01_top is
generic(
SIMULATION : std_logic := '0'; -- =1 simulation,=0 synthesis
FPGA_FAMILY : family_type := NONE;
IRQ_WIDTH : integer range 32 downto 1 := 1;
-- only use one of the following 3:
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
NR_OF_BARS_USED : natural range 6 downto 1 := 5;
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
BAR_MASK_0 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_1 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_2 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_3 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_4 : std_logic_vector(31 downto 0) := x"FF000001";
BAR_MASK_5 : std_logic_vector(31 downto 0) := x"FF000001";
ROM_MASK : std_logic_vector(31 downto 0) := x"FFFF0000";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000010000"; -- 16DW = 64Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
GP_DEBUG_PORT_WIDTH : positive := 1
);
port(
-- Hard IP ports:
clk_50 : in std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
clk_125 : in std_logic; -- 125 MHz clock for fixed_clk, CycloneIV only
ref_clk : in std_logic; -- 100 MHz reference clock
clk_500 : in std_logic; -- 500 Hz clock
ext_rst_n : in std_logic; -- for CycloneV this MUST be connected to
-- nPERSTL0 for top left HardIP
-- nPERSTL1 for bottom left Hard IP <- use this one first (recommended by Altera)
rx_0 : in std_logic;
rx_1 : in std_logic;
rx_2 : in std_logic;
rx_3 : in std_logic;
tx_0 : out std_logic;
tx_1 : out std_logic;
tx_2 : out std_logic;
tx_3 : out std_logic;
-- Wishbone ports:
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
irq_req_i : in std_logic_vector(IRQ_WIDTH -1 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
gp_debug_port : out std_logic_vector(GP_DEBUG_PORT_WIDTH -1 downto 0); -- general purpose debug port
link_train_active : out std_logic
);
end entity ip_16z091_01_top;
-- ****************************************************************************
-- +----------------------------------------------------------------------------
-- | Architecture for Cyclone IV
-- +----------------------------------------------------------------------------
architecture ip_16z091_01_top_arch of ip_16z091_01_top is
constant MAX_ADDR_VAL : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- := 2^32 - 1
function conv_std_to_string(
in_bit : std_logic
) return string is
begin
if(in_bit = '0') then
return "false";
else
return "true";
end if;
end function conv_std_to_string;
function calc_mask_size(
in_BAR_mask : std_logic_vector;
BAR_No : integer range 5 downto 0
) return integer is
variable in_val : std_logic_vector(31 downto 0) := (others => '0');
variable int_temp : integer := 0;
variable addr_line : integer range 32 downto 1 := 1;
begin
if(BAR_No > NR_OF_BARS_USED - 1) then
return 0;
else
---------------------------------------------------------
-- memory thus unmask I/O, type and prefetch bit values
---------------------------------------------------------
if(in_BAR_mask(0) = '0') then
in_val := in_BAR_mask(31 downto 4) & "0000";
-----------------------------------------
-- I/O thus unmask I/O and reserved bit
-----------------------------------------
else
in_val := in_BAR_mask(31 downto 2) & "00";
end if;
in_val := MAX_ADDR_VAL - in_val;
int_temp := conv_integer(unsigned(in_val));
while int_temp >= 2 loop
addr_line := addr_line + 1;
int_temp := int_temp / 2;
end loop;
return addr_line;
end if;
end function calc_mask_size;
constant IO_SPACE_0 : string := conv_std_to_string(BAR_MASK_0(0));
constant PREFETCH_0 : string := conv_std_to_string(BAR_MASK_0(3));
constant SIZE_MASK_0 : integer := calc_mask_size(BAR_MASK_0, 0);
constant IO_SPACE_1 : string := conv_std_to_string(BAR_MASK_1(0));
constant PREFETCH_1 : string := conv_std_to_string(BAR_MASK_1(3));
constant SIZE_MASK_1 : integer := calc_mask_size(BAR_MASK_1, 1);
constant IO_SPACE_2 : string := conv_std_to_string(BAR_MASK_2(0));
constant PREFETCH_2 : string := conv_std_to_string(BAR_MASK_2(3));
constant SIZE_MASK_2 : integer := calc_mask_size(BAR_MASK_2, 2);
constant IO_SPACE_3 : string := conv_std_to_string(BAR_MASK_3(0));
constant PREFETCH_3 : string := conv_std_to_string(BAR_MASK_3(3));
constant SIZE_MASK_3 : integer := calc_mask_size(BAR_MASK_3, 3);
constant IO_SPACE_4 : string := conv_std_to_string(BAR_MASK_4(0));
constant PREFETCH_4 : string := conv_std_to_string(BAR_MASK_4(3));
constant SIZE_MASK_4 : integer := calc_mask_size(BAR_MASK_4, 4);
constant IO_SPACE_5 : string := conv_std_to_string(BAR_MASK_5(0));
constant PREFETCH_5 : string := conv_std_to_string(BAR_MASK_5(3));
constant SIZE_MASK_5 : integer := calc_mask_size(BAR_MASK_5, 5);
--TODO_ITEM FIX THIS!
--constant SIZE_MASK_ROM : integer := calc_mask_size(ROM_MASK, 6);
constant SIZE_MASK_ROM : integer := calc_mask_size(ROM_MASK, 5);
constant SUPPORTED_DEVICES : supported_family_types := (CYCLONE4, ARRIA2_GX);
-- internal signals -----------------------------------------------------------
signal rst_int : std_logic;
signal core_clk_int : std_logic;
signal crst_int : std_logic;
signal srst_int : std_logic;
signal npor_int : std_logic;
signal rx_st_data0_int : std_logic_vector(63 downto 0);
signal rx_st_err0_int : std_logic;
signal rx_st_valid0_int : std_logic;
signal rx_st_sop0_int : std_logic;
signal rx_st_eop0_int : std_logic;
signal rx_st_be0_int : std_logic_vector(7 downto 0);
signal rx_st_bardec0_int : std_logic_vector(7 downto 0);
signal tx_st_ready0_int : std_logic;
signal tx_fifo_full0_int : std_logic;
signal tx_fifo_empty0_int : std_logic;
signal tx_fifo_rdptr0_int : std_logic_vector(3 downto 0);
signal tx_fifo_wrptr0_int : std_logic_vector(3 downto 0);
signal pme_to_sr_int : std_logic;
signal tl_cfg_add_int : std_logic_vector(3 downto 0);
signal tl_cfg_ctl_int : std_logic_vector(31 downto 0);
signal tl_cfg_ctl_wr_int : std_logic;
signal tl_cfg_sts_int : std_logic_vector(52 downto 0);
signal tl_cfg_sts_wr_int : std_logic;
signal app_int_ack_int : std_logic;
signal app_msi_ack_int : std_logic;
signal rx_st_mask0_int : std_logic;
signal rx_st_ready0_int : std_logic;
signal tx_st_err0_int : std_logic;
signal tx_st_valid0_int : std_logic;
signal tx_st_sop0_int : std_logic;
signal tx_st_eop0_int : std_logic;
signal tx_st_data0_int : std_logic_vector(63 downto 0);
signal pme_to_cr_int : std_logic;
signal app_int_sts_int : std_logic;
signal app_msi_req_int : std_logic;
signal app_msi_tc_int : std_logic_vector(2 downto 0);
signal app_msi_num_int : std_logic_vector(4 downto 0);
signal pex_msi_num_int : std_logic_vector(4 downto 0);
signal derr_cor_ext_rcv_int : std_logic_vector(1 downto 0) := "00";
signal derr_cor_ext_rpl_int : std_logic;
signal derr_rpl_int : std_logic;
signal r2c_err0_int : std_logic;
signal cpl_err_int : std_logic_vector(6 downto 0);
signal cpl_pending_int : std_logic;
--signal int_bar_hit : std_logic_vector(6 downto 0);
--signal wbm_adr_int : std_logic_vector(31 downto 0);
signal reconfig_fromgxb_int : std_logic_vector (4 downto 0);
signal reconfig_togxb_int : std_logic_vector (3 downto 0);
SIGNAL reconf_busy : std_logic;
signal pll_powerdown_int : std_logic;
signal l2_exit : std_logic;
signal hotrst_exit : std_logic;
signal dlup_exit : std_logic;
signal rst_cwh : std_logic;
signal rst_cwh_cnt : std_logic_vector (1 downto 0);
--signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
--signal wbm_cyc_o_int_d : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0); --mwawrik: delayed cycle causes problems
signal test_in_int : std_logic_vector(39 downto 0);
signal pipe_mode_int : std_logic;
-- signals to connect pcie_msi
signal int_wb_int : std_logic;
signal int_wb_pwr_enable : std_logic;
signal int_wb_int_num : std_logic_vector(4 downto 0);
signal int_wb_int_ack : std_logic;
signal int_wb_int_num_allowed : std_logic_vector(5 downto 0);
signal int_ltssm : std_logic_vector(4 downto 0);
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component ip_16z091_01
generic(
FPGA_FAMILY : family_type := NONE;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
READY_LATENCY : natural := 2;
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001";
WBM_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011";
WBM_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
WBS_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100";
WBS_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000";
RX_FIFO_DEPTH : natural := 1024;
RX_LPM_WIDTHU : natural := 10;
TX_HEADER_FIFO_DEPTH : natural := 32;
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024;
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
wb_rst : in std_logic;
-- IP Core
core_clk : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
--wb_bar_dec : out std_logic_vector(6 downto 0);
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
wb_int : in std_logic;
wb_pwr_enable : in std_logic;
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end component;
component hard_ip_x1
port (
-- inputs:
signal app_int_sts : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal app_msi_req : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC;
signal crst : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal lmi_wren : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pclk_in : IN STD_LOGIC;
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pm_event : IN STD_LOGIC;
signal pme_to_cr : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal rx_st_ready0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
-- outputs:
signal app_clk : OUT STD_LOGIC;
signal app_int_ack : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal core_clk_out : OUT STD_LOGIC;
signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
signal derr_cor_ext_rpl : OUT STD_LOGIC;
signal derr_rpl : OUT STD_LOGIC;
signal dlup_exit : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal l2_exit : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal lmi_ack : OUT STD_LOGIC;
signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal r2c_err0 : OUT STD_LOGIC;
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal rx_st_err0 : OUT STD_LOGIC;
signal rx_st_sop0 : OUT STD_LOGIC;
signal rx_st_valid0 : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_out0 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC
);
end component;
COMPONENT Hard_IP_x4 is
port (
-- inputs:
signal app_int_sts : IN STD_LOGIC;
signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal app_msi_req : IN STD_LOGIC;
signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal busy_altgxb_reconfig : IN STD_LOGIC;
signal cal_blk_clk : IN STD_LOGIC;
signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
signal cpl_pending : IN STD_LOGIC;
signal crst : IN STD_LOGIC;
signal fixedclk_serdes : IN STD_LOGIC;
signal gxb_powerdown : IN STD_LOGIC;
signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
signal lmi_rden : IN STD_LOGIC;
signal lmi_wren : IN STD_LOGIC;
signal npor : IN STD_LOGIC;
signal pclk_in : IN STD_LOGIC;
signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
signal phystatus_ext : IN STD_LOGIC;
signal pipe_mode : IN STD_LOGIC;
signal pld_clk : IN STD_LOGIC;
signal pll_powerdown : IN STD_LOGIC;
signal pm_auxpwr : IN STD_LOGIC;
signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
signal pm_event : IN STD_LOGIC;
signal pme_to_cr : IN STD_LOGIC;
signal reconfig_clk : IN STD_LOGIC;
signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
signal refclk : IN STD_LOGIC;
signal rx_in0 : IN STD_LOGIC;
signal rx_in1 : IN STD_LOGIC;
signal rx_in2 : IN STD_LOGIC;
signal rx_in3 : IN STD_LOGIC;
signal rx_st_mask0 : IN STD_LOGIC;
signal rx_st_ready0 : IN STD_LOGIC;
signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata1_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata2_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdata3_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rxdatak0_ext : IN STD_LOGIC;
signal rxdatak1_ext : IN STD_LOGIC;
signal rxdatak2_ext : IN STD_LOGIC;
signal rxdatak3_ext : IN STD_LOGIC;
signal rxelecidle0_ext : IN STD_LOGIC;
signal rxelecidle1_ext : IN STD_LOGIC;
signal rxelecidle2_ext : IN STD_LOGIC;
signal rxelecidle3_ext : IN STD_LOGIC;
signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus1_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus2_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxstatus3_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal rxvalid0_ext : IN STD_LOGIC;
signal rxvalid1_ext : IN STD_LOGIC;
signal rxvalid2_ext : IN STD_LOGIC;
signal rxvalid3_ext : IN STD_LOGIC;
signal srst : IN STD_LOGIC;
signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal tx_st_eop0 : IN STD_LOGIC;
signal tx_st_err0 : IN STD_LOGIC;
signal tx_st_sop0 : IN STD_LOGIC;
signal tx_st_valid0 : IN STD_LOGIC;
-- outputs:
signal app_int_ack : OUT STD_LOGIC;
signal app_msi_ack : OUT STD_LOGIC;
signal clk250_out : OUT STD_LOGIC;
signal clk500_out : OUT STD_LOGIC;
signal core_clk_out : OUT STD_LOGIC;
signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
signal derr_cor_ext_rpl : OUT STD_LOGIC;
signal derr_rpl : OUT STD_LOGIC;
signal dlup_exit : OUT STD_LOGIC;
signal hotrst_exit : OUT STD_LOGIC;
signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal l2_exit : OUT STD_LOGIC;
signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal lmi_ack : OUT STD_LOGIC;
signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal pme_to_sr : OUT STD_LOGIC;
signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal r2c_err0 : OUT STD_LOGIC;
signal rate_ext : OUT STD_LOGIC;
signal rc_pll_locked : OUT STD_LOGIC;
signal rc_rx_digitalreset : OUT STD_LOGIC;
signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
signal reset_status : OUT STD_LOGIC;
signal rx_fifo_empty0 : OUT STD_LOGIC;
signal rx_fifo_full0 : OUT STD_LOGIC;
signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal rx_st_eop0 : OUT STD_LOGIC;
signal rx_st_err0 : OUT STD_LOGIC;
signal rx_st_sop0 : OUT STD_LOGIC;
signal rx_st_valid0 : OUT STD_LOGIC;
signal rxpolarity0_ext : OUT STD_LOGIC;
signal rxpolarity1_ext : OUT STD_LOGIC;
signal rxpolarity2_ext : OUT STD_LOGIC;
signal rxpolarity3_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
signal tl_cfg_sts_wr : OUT STD_LOGIC;
signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
signal tx_fifo_empty0 : OUT STD_LOGIC;
signal tx_fifo_full0 : OUT STD_LOGIC;
signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tx_out0 : OUT STD_LOGIC;
signal tx_out1 : OUT STD_LOGIC;
signal tx_out2 : OUT STD_LOGIC;
signal tx_out3 : OUT STD_LOGIC;
signal tx_st_ready0 : OUT STD_LOGIC;
signal txcompl0_ext : OUT STD_LOGIC;
signal txcompl1_ext : OUT STD_LOGIC;
signal txcompl2_ext : OUT STD_LOGIC;
signal txcompl3_ext : OUT STD_LOGIC;
signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata1_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata2_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdata3_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal txdatak0_ext : OUT STD_LOGIC;
signal txdatak1_ext : OUT STD_LOGIC;
signal txdatak2_ext : OUT STD_LOGIC;
signal txdatak3_ext : OUT STD_LOGIC;
signal txdetectrx_ext : OUT STD_LOGIC;
signal txelecidle0_ext : OUT STD_LOGIC;
signal txelecidle1_ext : OUT STD_LOGIC;
signal txelecidle2_ext : OUT STD_LOGIC;
signal txelecidle3_ext : OUT STD_LOGIC
);
end COMPONENT Hard_IP_x4;
--component z091_01_wb_adr_dec
-- generic(
-- NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
-- );
-- port (
-- pci_cyc_i : in std_logic_vector(6 downto 0);
-- wbm_adr_o_q : in std_logic_vector(31 downto 2);
--
-- wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
-- );
--end component;
component alt_reconf
port(
reconfig_clk : in std_logic;
reconfig_fromgxb : in std_logic_vector (4 downto 0);
busy : out std_logic;
reconfig_togxb : out std_logic_vector (3 downto 0)
);
end component;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
component pcie_msi
generic (
WIDTH : integer range 32 downto 1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
irq_req_i : in std_logic_vector(WIDTH -1 downto 0);
wb_int_o : out std_logic;
wb_pwr_enable_o : out std_logic;
wb_int_num_o : OUT std_logic_vector(4 downto 0);
wb_int_ack_i : in std_logic;
wb_int_num_allowed_i : in std_logic_vector(5 downto 0)
);
end component;
-------------------------------------------------------------------------------
begin
-- coverage off
assert not no_valid_device(supported_devices => SUPPORTED_DEVICES, device => FPGA_FAMILY) report "16z091-01: no valid FPGA device selected" severity failure;
-- coverage on
gp_debug_port <= (others => '0');
--wbm_cyc_o <= wbm_cyc_o_int;
npor_int <= ext_rst_n and '1';
pll_powerdown_int <= not npor_int;
----------------------------------
-- assign debug port if ltssm is
-- in link training mode
----------------------------------
link_train_active <= '0' when int_ltssm = "01111" else
'1';
-------------------------------------------------
-- work around for Altera receiver detect issue
-------------------------------------------------
pipe_mode_int <= '0'; -- use serial mode
test_in_int(39 downto 4) <= (others => '0');
test_in_int(3) <= not pipe_mode_int;
test_in_int(2 downto 1) <= (others => '0');
--------------------------------------------
-- speed up initialization for simulation:
--------------------------------------------
test_in_int(0) <= SIMULATION;
-- instanciate components
ip_16z091_01_comp : ip_16z091_01
generic map(
FPGA_FAMILY => FPGA_FAMILY,
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
READY_LATENCY => 2,
FIFO_MAX_USEDW => conv_std_logic_vector((2**RX_LPM_WIDTHU - 8),10),
WBM_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 5),10),
WBM_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
WBS_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 4),10),
WBS_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
PCIE_REQUEST_LENGTH => PCIE_REQUEST_LENGTH,
RX_FIFO_DEPTH => 2**RX_LPM_WIDTHU,
RX_LPM_WIDTHU => RX_LPM_WIDTHU,
TX_HEADER_FIFO_DEPTH => 2**TX_HEADER_LPM_WIDTHU,
TX_HEADER_LPM_WIDTHU => TX_HEADER_LPM_WIDTHU,
TX_DATA_FIFO_DEPTH => 2**TX_DATA_LPM_WIDTHU,
TX_DATA_LPM_WIDTHU => TX_DATA_LPM_WIDTHU
)
port map(
clk => core_clk_int,
rst => rst_int,
clk_500 => clk_500,
wb_clk => wb_clk,
wb_rst => wb_rst,
-- IP Core
core_clk => core_clk_int,
rx_st_data0 => rx_st_data0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_valid0 => rx_st_valid0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_bardec0 => rx_st_bardec0_int,
tx_st_ready0 => tx_st_ready0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
pme_to_sr => pme_to_sr_int,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_valid0 => tx_st_valid0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_data0 => tx_st_data0_int,
pme_to_cr => pme_to_cr_int,
app_int_sts => app_int_sts_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
app_msi_num => app_msi_num_int,
pex_msi_num => pex_msi_num_int,
derr_cor_ext_rcv => derr_cor_ext_rcv_int,
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
r2c_err0 => r2c_err0_int,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
-- Wishbone master
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
--wbm_cyc => OPEN,
wbm_cyc_o => wbm_cyc_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
--wb_bar_dec => int_bar_hit,
-- Wishbone slave
wbs_cyc => wbs_cyc,
wbs_stb => wbs_stb,
wbs_we => wbs_we,
wbs_sel => wbs_sel,
wbs_adr => wbs_adr,
wbs_dat_i => wbs_dat_i,
wbs_cti => wbs_cti,
wbs_tga => wbs_tga,
wbs_ack => wbs_ack,
wbs_err => wbs_err,
wbs_dat_o => wbs_dat_o,
-- interrupt
wb_int => int_wb_int,
wb_pwr_enable => int_wb_pwr_enable,
wb_int_num => int_wb_int_num,
wb_int_ack => int_wb_int_ack,
wb_int_num_allowed => int_wb_int_num_allowed,
-- error
error_timeout => error_timeout,
error_cor_ext_rcv => error_cor_ext_rcv,
error_cor_ext_rpl => error_cor_ext_rpl,
error_rpl => error_rpl,
error_r2c0 => error_r2c0,
error_msi_num => error_msi_num,
-- debug port
rx_debug_out => open
);
gen_x4: if USE_LANES = "100" generate
Hard_IP_x4_comp : entity work.Hard_IP_x4
port map(
-- inputs:
app_int_sts => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
busy_altgxb_reconfig => reconf_busy,
cal_blk_clk => clk_50,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
crst => crst_int,
fixedclk_serdes => clk_125,
gxb_powerdown => '0',
hpg_ctrler => (others => '0'),
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
npor => npor_int,
pclk_in => core_clk_int,
pex_msi_num => pex_msi_num_int,
phystatus_ext => '0',
pipe_mode => pipe_mode_int,
pld_clk => core_clk_int,
pll_powerdown => '0',
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_clk => clk_50,
reconfig_togxb => reconfig_togxb_int,
refclk => ref_clk,
rx_in0 => rx_0,
rx_in1 => rx_1,
rx_in2 => rx_2,
rx_in3 => rx_3,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
rxdata0_ext => (others => '0'),
rxdata1_ext => (others => '0'),
rxdata2_ext => (others => '0'),
rxdata3_ext => (others => '0'),
rxdatak0_ext => '0',
rxdatak1_ext => '0',
rxdatak2_ext => '0',
rxdatak3_ext => '0',
rxelecidle0_ext => '0',
rxelecidle1_ext => '0',
rxelecidle2_ext => '0',
rxelecidle3_ext => '0',
rxstatus0_ext => (others => '0'),
rxstatus1_ext => (others => '0'),
rxstatus2_ext => (others => '0'),
rxstatus3_ext => (others => '0'),
rxvalid0_ext => '0',
rxvalid1_ext => '0',
rxvalid2_ext => '0',
rxvalid3_ext => '0',
srst => srst_int,
test_in => (others => '0'),
tx_st_data0 => tx_st_data0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_valid0 => tx_st_valid0_int,
-- outputs:
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
clk250_out => open,
clk500_out => open,
core_clk_out => core_clk_int,
derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
dlup_exit => dlup_exit,
hotrst_exit => hotrst_exit,
ko_cpl_spc_vc0 => open,
l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
ltssm => int_ltssm,
pme_to_sr => pme_to_sr_int,
powerdown_ext => open,
r2c_err0 => r2c_err0_int,
rate_ext => open,
rc_pll_locked => open,
reconfig_fromgxb => reconfig_fromgxb_int,
reset_status => open,
rx_fifo_empty0 => open,
rx_fifo_full0 => open,
rx_st_bardec0 => rx_st_bardec0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_data0 => rx_st_data0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_valid0 => rx_st_valid0_int,
rxpolarity0_ext => open,
rxpolarity1_ext => open,
rxpolarity2_ext => open,
rxpolarity3_ext => open,
suc_spd_neg => open,
test_out => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred0 => open,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
tx_out0 => tx_0,
tx_out1 => tx_1,
tx_out2 => tx_2,
tx_out3 => tx_3,
tx_st_ready0 => tx_st_ready0_int,
txcompl0_ext => open,
txcompl1_ext => open,
txcompl2_ext => open,
txcompl3_ext => open,
txdata0_ext => open,
txdata1_ext => open,
txdata2_ext => open,
txdata3_ext => open,
txdatak0_ext => open,
txdatak1_ext => open,
txdatak2_ext => open,
txdatak3_ext => open,
txdetectrx_ext => open,
txelecidle0_ext => open,
txelecidle1_ext => open,
txelecidle2_ext => open,
txelecidle3_ext => open
);
end generate gen_x4;
-- gen_x2: if USE_LANES = "010" generate
-- Hard_IP_x2_comp : entity work.Hard_IP_x2
-- generic map(
-- VENDOR_ID => VENDOR_ID,
-- DEVICE_ID => DEVICE_ID,
-- REVISION_ID => REVISION_ID,
-- CLASS_CODE => CLASS_CODE,
-- SUBSYSTEM_VENDOR_ID => SUBSYSTEM_VENDOR_ID,
-- SUBSYSTEM_DEVICE_ID => SUBSYSTEM_DEVICE_ID,
--
-- IO_SPACE_BAR_0 => IO_SPACE_0, -- IO_SPACE_BAR_0,
-- PREFETCH_BAR_0 => PREFETCH_0, -- PREFETCH_BAR_0,
-- SIZE_MASK_BAR_0 => SIZE_MASK_0, -- SIZE_MASK_BAR_0,
--
-- IO_SPACE_BAR_1 => IO_SPACE_1, -- IO_SPACE_BAR_1,
-- PREFETCH_BAR_1 => PREFETCH_1, -- PREFETCH_BAR_1,
-- SIZE_MASK_BAR_1 => SIZE_MASK_1, -- SIZE_MASK_BAR_1,
--
-- IO_SPACE_BAR_2 => IO_SPACE_2, -- IO_SPACE_BAR_2,
-- PREFETCH_BAR_2 => PREFETCH_2, -- PREFETCH_BAR_2,
-- SIZE_MASK_BAR_2 => SIZE_MASK_2, -- SIZE_MASK_BAR_2,
--
-- IO_SPACE_BAR_3 => IO_SPACE_3, -- IO_SPACE_BAR_3,
-- PREFETCH_BAR_3 => PREFETCH_3, -- PREFETCH_BAR_3,
-- SIZE_MASK_BAR_3 => SIZE_MASK_3, -- SIZE_MASK_BAR_3,
--
-- IO_SPACE_BAR_4 => IO_SPACE_4, -- IO_SPACE_BAR_4,
-- PREFETCH_BAR_4 => PREFETCH_4, -- PREFETCH_BAR_4,
-- SIZE_MASK_BAR_4 => SIZE_MASK_4, -- SIZE_MASK_BAR_4,
--
-- IO_SPACE_BAR_5 => IO_SPACE_5, -- IO_SPACE_BAR_5,
-- PREFETCH_BAR_5 => PREFETCH_5, -- PREFETCH_BAR_5,
-- SIZE_MASK_BAR_5 => SIZE_MASK_5 -- SIZE_MASK_BAR_5
-- )
-- port map(
-- -- inputs:
-- app_int_sts => app_int_sts_int,
-- app_msi_num => app_msi_num_int,
-- app_msi_req => app_msi_req_int,
-- app_msi_tc => app_msi_tc_int,
-- cal_blk_clk => clk_50,
-- cpl_err => cpl_err_int,
-- cpl_pending => cpl_pending_int,
-- crst => crst_int,
-- gxb_powerdown => '0',
-- hpg_ctrler => (others => '0'),
-- lmi_addr => (others => '0'),
-- lmi_din => (others => '0'),
-- lmi_rden => '0',
-- lmi_wren => '0',
-- npor => '1', --ext_rst_n, --'0',
-- pclk_in => core_clk_int,
-- pex_msi_num => pex_msi_num_int,
-- phystatus_ext => '0',
-- pipe_mode => '0',
-- pld_clk => core_clk_int,
-- pll_powerdown => '0',
-- pm_auxpwr => '0',
-- pm_data => (others => '0'),
-- pm_event => '0',
-- pme_to_cr => pme_to_cr_int,
-- reconfig_clk => clk_50,
-- reconfig_togxb => reconfig_togxb_int,
-- refclk => ref_clk,
-- rx_in0 => rx_0,
-- rx_in1 => rx_1,
-- rx_st_mask0 => rx_st_mask0_int,
-- rx_st_ready0 => rx_st_ready0_int,
-- rxdata0_ext => (others => '0'),
-- rxdata1_ext => (others => '0'),
-- rxdatak0_ext => '0',
-- rxdatak1_ext => '0',
-- rxelecidle0_ext => '0',
-- rxelecidle1_ext => '0',
-- rxstatus0_ext => (others => '0'),
-- rxstatus1_ext => (others => '0'),
-- rxvalid0_ext => '0',
-- rxvalid1_ext => '0',
-- srst => srst_int,
-- test_in => (others => '0'),
-- tx_st_data0 => tx_st_data0_int,
-- tx_st_eop0 => tx_st_eop0_int,
-- tx_st_err0 => tx_st_err0_int,
-- tx_st_sop0 => tx_st_sop0_int,
-- tx_st_valid0 => tx_st_valid0_int,
--
-- -- outputs:
-- app_int_ack => app_int_ack_int,
-- app_msi_ack => app_msi_ack_int,
-- clk250_out => open,
-- clk500_out => open,
-- core_clk_out => core_clk_int,
-- derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
-- derr_cor_ext_rpl => derr_cor_ext_rpl_int,
-- derr_rpl => derr_rpl_int,
-- dlup_exit => open,
-- hotrst_exit => open,
-- ko_cpl_spc_vc0 => open,
-- l2_exit => open,
-- lane_act => open,
-- lmi_ack => open,
-- lmi_dout => open,
-- ltssm => open,
-- pme_to_sr => pme_to_sr_int,
-- powerdown_ext => open,
-- r2c_err0 => r2c_err0_int,
-- rate_ext => open,
-- rc_pll_locked => open,
-- reconfig_fromgxb => reconfig_fromgxb_int,
-- reset_status => open,
-- rx_fifo_empty0 => open,
-- rx_fifo_full0 => open,
-- rx_st_bardec0 => rx_st_bardec0_int,
-- rx_st_be0 => rx_st_be0_int,
-- rx_st_data0 => rx_st_data0_int,
-- rx_st_eop0 => rx_st_eop0_int,
-- rx_st_err0 => rx_st_err0_int,
-- rx_st_sop0 => rx_st_sop0_int,
-- rx_st_valid0 => rx_st_valid0_int,
-- rxpolarity0_ext => open,
-- rxpolarity1_ext => open,
-- suc_spd_neg => open,
-- test_out => open,
-- tl_cfg_add => tl_cfg_add_int,
-- tl_cfg_ctl => tl_cfg_ctl_int,
-- tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
-- tl_cfg_sts => tl_cfg_sts_int,
-- tl_cfg_sts_wr => tl_cfg_sts_wr_int,
-- tx_cred0 => open,
-- tx_fifo_empty0 => tx_fifo_empty0_int,
-- tx_fifo_full0 => tx_fifo_full0_int,
-- tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
-- tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
-- tx_out0 => tx_0,
-- tx_out1 => tx_1,
-- tx_st_ready0 => tx_st_ready0_int,
-- txcompl0_ext => open,
-- txcompl1_ext => open,
-- txdata0_ext => open,
-- txdata1_ext => open,
-- txdatak0_ext => open,
-- txdatak1_ext => open,
-- txdetectrx_ext => open,
-- txelecidle0_ext => open,
-- txelecidle1_ext => open
-- );
-- tx_2 <= '1';
-- tx_3 <= '1';
-- end generate gen_x2;
gen_x1: if USE_LANES = "001" generate
Hard_IP_x1_comp : Hard_IP_x1
port map(
app_int_sts => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
busy_altgxb_reconfig => reconf_busy,
cal_blk_clk => clk_50,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
crst => crst_int,
fixedclk_serdes => clk_125,
gxb_powerdown => '0',
hpg_ctrler => (others => '0'),
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
npor => npor_int,
pclk_in => core_clk_int,
pex_msi_num => pex_msi_num_int,
phystatus_ext => '0',
pipe_mode => pipe_mode_int,
pld_clk => core_clk_int,
pll_powerdown => pll_powerdown_int,
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_clk => clk_50,
reconfig_togxb => reconfig_togxb_int,
refclk => ref_clk,
rx_in0 => rx_0,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
rxdata0_ext => (others => '0'),
rxdatak0_ext => '0',
rxelecidle0_ext => '0',
rxstatus0_ext => (others => '0'),
rxvalid0_ext => '0',
srst => srst_int,
test_in => test_in_int,
tx_st_data0 => tx_st_data0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_valid0 => tx_st_valid0_int,
-- outputs:
app_clk => open,
app_int_ack => app_int_ack_int,
app_msi_ack => app_msi_ack_int,
clk250_out => open,
clk500_out => open,
core_clk_out => core_clk_int,
derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
dlup_exit => dlup_exit,
hotrst_exit => hotrst_exit,
ko_cpl_spc_vc0 => open,
l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
ltssm => int_ltssm,
pme_to_sr => pme_to_sr_int,
powerdown_ext => open,
r2c_err0 => r2c_err0_int,
rate_ext => open,
rc_pll_locked => open,
rc_rx_digitalreset => open,
reconfig_fromgxb => reconfig_fromgxb_int,
reset_status => open,
rx_fifo_empty0 => open,
rx_fifo_full0 => open,
rx_st_bardec0 => rx_st_bardec0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_data0 => rx_st_data0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_valid0 => rx_st_valid0_int,
rxpolarity0_ext => open,
suc_spd_neg => open,
test_out => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred0 => open,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
tx_out0 => tx_0,
tx_st_ready0 => tx_st_ready0_int,
txcompl0_ext => open,
txdata0_ext => open,
txdatak0_ext => open,
txdetectrx_ext => open,
txelecidle0_ext => open
);
tx_1 <= '1';
tx_2 <= '1';
tx_3 <= '1';
end generate gen_x1;
--z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
-- generic map(
-- NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
-- )
-- port map(
-- pci_cyc_i => int_bar_hit,
-- wbm_adr_o_q => wbm_adr_int(31 downto 2),
--
-- wbm_cyc_o => wbm_cyc_o_int
-- );
--mwawrik: this process is responsible for the problem, that the cycle is longer active than acknowledge
--cyc_o : process(wb_rst, wb_clk)
--begin
-- if wb_rst = '1' then
-- wbm_cyc_o_int_d <= (others => '0');
-- elsif wb_clk'event and wb_clk = '1' then
-- if wbm_ack = '1' then
-- wbm_cyc_o_int_d <= (others=>'0');
-- else
-- wbm_cyc_o_int_d <= wbm_cyc_o_int;
-- end if;
-- end if;
--end process cyc_o;
------------------------------------------------------------------------------
alt_reconf_comp : alt_reconf
port map(
reconfig_clk => clk_50,
reconfig_fromgxb => reconfig_fromgxb_int,
busy => reconf_busy,
reconfig_togxb => reconfig_togxb_int
);
gen_srst_crst_for_cold_warm_hot: process(rst_int,core_clk_int)
begin
if(rst_int = '1') then -- deactivate rst_cwh during ext_rst
rst_cwh <= '0';
rst_cwh_cnt <= (others => '0');
elsif(core_clk_int'event and core_clk_int = '1') then
if(l2_exit = '0' or hotrst_exit = '0' or dlup_exit = '0') then -- start reset
rst_cwh_cnt <= (others => '1');
elsif(rst_cwh_cnt > 0) then -- count condition
rst_cwh_cnt <= rst_cwh_cnt - 1;
else -- stop condition
rst_cwh_cnt <= (others => '0');
end if;
if(rst_cwh_cnt = 0) then -- reset if cnt > 0
rst_cwh <= '0';
else
rst_cwh <= '1';
end if;
end if;
end process;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
pcie_msi_i0 : pcie_msi
generic map(
WIDTH => IRQ_WIDTH
)
port map(
clk_i => wb_clk,
rst_i => wb_rst,
irq_req_i => irq_req_i,
wb_int_o => int_wb_int,
wb_pwr_enable_o => int_wb_pwr_enable,
wb_int_num_o => int_wb_int_num,
wb_int_ack_i => int_wb_int_ack,
wb_int_num_allowed_i => int_wb_int_num_allowed
);
-------------------------------------------------------------------------------
-- port assignement
--wbm_adr <= wbm_adr_int;
-- reset and clock logic
rst_int <= not ext_rst_n;
crst_int <= rst_int or rst_cwh;
srst_int <= rst_int or rst_cwh;
-------------------------------------------------------------------------------
end architecture ip_16z091_01_top_arch;
-- +----------------------------------------------------------------------------
-- | Architecture for Cyclone V
-- +----------------------------------------------------------------------------
architecture ip_16z091_01_top_cycv_arch of ip_16z091_01_top is
constant MAX_ADDR_VAL : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- := 2^32 - 1
constant MAX_RECONF_IF : positive range 5 downto 1 := 5;
----------------------------------------------
-- Altera changed string values for CycloneV
-- thus added Enabled/Disabled
----------------------------------------------
function conv_std_to_string(
in_bit : std_logic
) return string is
begin
if(in_bit = '0') then
return "Disabled";
else
return "Enabled";
end if;
end function conv_std_to_string;
function calc_mask_size(
in_BAR_mask : std_logic_vector;
BAR_No : integer range 5 downto 0
) return integer is
variable in_val : std_logic_vector(31 downto 0) := (others => '0');
variable int_temp : integer := 0;
variable addr_line : integer range 32 downto 1 := 1;
begin
if(BAR_No > NR_OF_BARS_USED - 1) then
return 0;
else
---------------------------------------------------------
-- memory thus unmask I/O, type and prefetch bit values
---------------------------------------------------------
if(in_BAR_mask(0) = '0') then
in_val := in_BAR_mask(31 downto 4) & "0000";
-----------------------------------------
-- I/O thus unmask I/O and reserved bit
-----------------------------------------
else
in_val := in_BAR_mask(31 downto 2) & "00";
end if;
in_val := MAX_ADDR_VAL - in_val;
int_temp := conv_integer(unsigned(in_val));
while int_temp >= 2 loop
addr_line := addr_line + 1;
int_temp := int_temp / 2;
end loop;
return addr_line;
end if;
end function calc_mask_size;
constant IO_SPACE_0 : string := conv_std_to_string(BAR_MASK_0(0));
constant PREFETCH_0 : string := conv_std_to_string(BAR_MASK_0(3));
constant SIZE_MASK_0 : integer := calc_mask_size(BAR_MASK_0, 0);
constant IO_SPACE_1 : string := conv_std_to_string(BAR_MASK_1(0));
constant PREFETCH_1 : string := conv_std_to_string(BAR_MASK_1(3));
constant SIZE_MASK_1 : integer := calc_mask_size(BAR_MASK_1, 1);
constant IO_SPACE_2 : string := conv_std_to_string(BAR_MASK_2(0));
constant PREFETCH_2 : string := conv_std_to_string(BAR_MASK_2(3));
constant SIZE_MASK_2 : integer := calc_mask_size(BAR_MASK_2, 2);
constant IO_SPACE_3 : string := conv_std_to_string(BAR_MASK_3(0));
constant PREFETCH_3 : string := conv_std_to_string(BAR_MASK_3(3));
constant SIZE_MASK_3 : integer := calc_mask_size(BAR_MASK_3, 3);
constant IO_SPACE_4 : string := conv_std_to_string(BAR_MASK_4(0));
constant PREFETCH_4 : string := conv_std_to_string(BAR_MASK_4(3));
constant SIZE_MASK_4 : integer := calc_mask_size(BAR_MASK_4, 4);
constant IO_SPACE_5 : string := conv_std_to_string(BAR_MASK_5(0));
constant PREFETCH_5 : string := conv_std_to_string(BAR_MASK_5(3));
constant SIZE_MASK_5 : integer := calc_mask_size(BAR_MASK_5, 5);
--TODO_ITEM FIX THIS!
--constant SIZE_MASK_ROM : integer := calc_mask_size(ROM_MASK, 6);
constant SIZE_MASK_ROM : integer := calc_mask_size(ROM_MASK, 5);
constant SUPPORTED_DEVICES : supported_family_type := (CYCLONE5);
-- internal signals -----------------------------------------------------------
signal rst_int : std_logic;
--signal rst_int_n : std_logic;
signal core_clk_int : std_logic;
signal npor_int : std_logic;
signal not_npor_int : std_logic;
--signal pld_clk_inuse_int : std_logic;
signal rst_cnt : std_logic_vector(4 downto 0);
signal reset_status_int : std_logic;
signal rx_st_data0_int : std_logic_vector(63 downto 0);
signal rx_st_err0_int : std_logic;
signal rx_st_valid0_int : std_logic;
signal rx_st_sop0_int : std_logic;
signal rx_st_eop0_int : std_logic;
signal rx_st_be0_int : std_logic_vector(7 downto 0);
signal rx_st_bardec0_int : std_logic_vector(7 downto 0);
signal tx_st_ready0_int : std_logic;
signal tx_fifo_full0_int : std_logic := '0';
signal tx_fifo_empty0_int : std_logic;
signal tx_fifo_rdptr0_int : std_logic_vector(3 downto 0) := (others => '0');
signal tx_fifo_wrptr0_int : std_logic_vector(3 downto 0) := (others => '0');
signal pme_to_sr_int : std_logic;
signal tl_cfg_add_int : std_logic_vector(3 downto 0);
signal tl_cfg_ctl_int : std_logic_vector(31 downto 0);
signal tl_cfg_ctl_wr_int : std_logic;
signal tl_cfg_sts_int : std_logic_vector(52 downto 0);
signal tl_cfg_sts_wr_int : std_logic;
signal app_int_ack_int : std_logic;
signal app_msi_ack_int : std_logic;
signal rx_st_mask0_int : std_logic;
signal rx_st_ready0_int : std_logic;
signal tx_st_err0_int : std_logic;
signal tx_st_valid0_int : std_logic;
signal tx_st_sop0_int : std_logic;
signal tx_st_eop0_int : std_logic;
signal tx_st_data0_int : std_logic_vector(63 downto 0);
signal pme_to_cr_int : std_logic;
signal app_int_sts_int : std_logic;
signal app_msi_req_int : std_logic;
signal app_msi_tc_int : std_logic_vector(2 downto 0);
signal app_msi_num_int : std_logic_vector(4 downto 0);
signal pex_msi_num_int : std_logic_vector(4 downto 0);
signal derr_cor_ext_rcv_int : std_logic_vector(1 downto 0) := "00";
signal derr_cor_ext_rpl_int : std_logic;
signal derr_rpl_int : std_logic;
signal r2c_err0_int : std_logic;
signal cpl_err_int : std_logic_vector(6 downto 0);
signal cpl_pending_int : std_logic;
signal l2_exit : std_logic;
signal hotrst_exit : std_logic;
signal dlup_exit : std_logic;
signal int_ltssm : std_logic_vector(4 downto 0);
signal serdes_pll_locked_int : std_logic;
signal test_in_int : std_logic_vector(31 downto 0);
-- signals to connect pcie_msi
signal int_wb_int : std_logic;
signal int_wb_pwr_enable : std_logic;
signal int_wb_int_num : std_logic_vector(4 downto 0);
signal int_wb_int_ack : std_logic;
signal int_wb_int_num_allowed : std_logic_vector(5 downto 0);
signal reconfig_to_xcvr_int : std_logic_vector(MAX_RECONF_IF*70-1 downto 0);
signal reconfig_from_xcvr_int : std_logic_vector(MAX_RECONF_IF*46-1 downto 0);
signal reconfig_busy_int : std_logic;
-- signals for app_int_ack emulation
-- app_int_ack is missing for CycloneV in Quartus 14.0.2
--TODO ITEM change if signal will be added in future versions
signal irq_app_int_ack : std_logic;
signal irq_int_sts_q : std_logic;
signal irq_int_sts_qq : std_logic;
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component ip_16z091_01
generic(
FPGA_FAMILY : family_type := NONE;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
READY_LATENCY : natural := 2;
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001";
WBM_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011";
WBM_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
WBS_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100";
WBS_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000";
RX_FIFO_DEPTH : natural := 1024;
RX_LPM_WIDTHU : natural := 10;
TX_HEADER_FIFO_DEPTH : natural := 32;
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024;
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
wb_rst : in std_logic;
-- IP Core
core_clk : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
wb_int : in std_logic;
wb_pwr_enable : in std_logic;
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end component;
component PCIeHardIPCycV
port (
npor : in std_logic := '0'; -- npor.npor
pin_perst : in std_logic := '0'; -- .pin_perst
test_in : in std_logic_vector(31 downto 0) := (others => '0'); -- hip_ctrl.test_in
simu_mode_pipe : in std_logic := '0'; -- .simu_mode_pipe
pld_clk : in std_logic := '0'; -- pld_clk.clk
coreclkout : out std_logic; -- coreclkout_hip.clk
refclk : in std_logic := '0'; -- refclk.clk
rx_in0 : in std_logic := '0'; -- hip_serial.rx_in0
rx_in1 : in std_logic := '0';
rx_in2 : in std_logic := '0';
rx_in3 : in std_logic := '0';
tx_out0 : out std_logic; -- .tx_out0
tx_out1 : out std_logic;
tx_out2 : out std_logic;
tx_out3 : out std_logic;
rx_st_valid : out std_logic; -- rx_st.valid
rx_st_sop : out std_logic; -- .startofpacket
rx_st_eop : out std_logic; -- .endofpacket
rx_st_ready : in std_logic := '0'; -- .ready
rx_st_err : out std_logic; -- .error
rx_st_data : out std_logic_vector(63 downto 0); -- .data
rx_st_bar : out std_logic_vector(7 downto 0); -- rx_bar_be.rx_st_bar
rx_st_be : out std_logic_vector(7 downto 0); -- .rx_st_be
rx_st_mask : in std_logic := '0'; -- .rx_st_mask
tx_st_valid : in std_logic := '0'; -- tx_st.valid
tx_st_sop : in std_logic := '0'; -- .startofpacket
tx_st_eop : in std_logic := '0'; -- .endofpacket
tx_st_ready : out std_logic; -- .ready
tx_st_err : in std_logic := '0'; -- .error
tx_st_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
tx_fifo_empty : out std_logic; -- tx_fifo.fifo_empty
tx_cred_datafccp : out std_logic_vector(11 downto 0); -- tx_cred.tx_cred_datafccp
tx_cred_datafcnp : out std_logic_vector(11 downto 0); -- .tx_cred_datafcnp
tx_cred_datafcp : out std_logic_vector(11 downto 0); -- .tx_cred_datafcp
tx_cred_fchipcons : out std_logic_vector(5 downto 0); -- .tx_cred_fchipcons
tx_cred_fcinfinite : out std_logic_vector(5 downto 0); -- .tx_cred_fcinfinite
tx_cred_hdrfccp : out std_logic_vector(7 downto 0); -- .tx_cred_hdrfccp
tx_cred_hdrfcnp : out std_logic_vector(7 downto 0); -- .tx_cred_hdrfcnp
tx_cred_hdrfcp : out std_logic_vector(7 downto 0); -- .tx_cred_hdrfcp
sim_pipe_pclk_in : in std_logic := '0'; -- hip_pipe.sim_pipe_pclk_in
sim_pipe_rate : out std_logic_vector(1 downto 0); -- .sim_pipe_rate
sim_ltssmstate : out std_logic_vector(4 downto 0); -- .sim_ltssmstate
eidleinfersel0 : out std_logic_vector(2 downto 0); -- .eidleinfersel0
eidleinfersel1 : out std_logic_vector(2 downto 0);
eidleinfersel2 : out std_logic_vector(2 downto 0);
eidleinfersel3 : out std_logic_vector(2 downto 0);
powerdown0 : out std_logic_vector(1 downto 0); -- .powerdown0
powerdown1 : out std_logic_vector(1 downto 0);
powerdown2 : out std_logic_vector(1 downto 0);
powerdown3 : out std_logic_vector(1 downto 0);
rxpolarity0 : out std_logic; -- .rxpolarity0
rxpolarity1 : out std_logic;
rxpolarity2 : out std_logic;
rxpolarity3 : out std_logic;
txcompl0 : out std_logic; -- .txcompl0
txcompl1 : out std_logic;
txcompl2 : out std_logic;
txcompl3 : out std_logic;
txdata0 : out std_logic_vector(7 downto 0); -- .txdata0
txdata1 : out std_logic_vector(7 downto 0);
txdata2 : out std_logic_vector(7 downto 0);
txdata3 : out std_logic_vector(7 downto 0);
txdatak0 : out std_logic; -- .txdatak0
txdatak1 : out std_logic;
txdatak2 : out std_logic;
txdatak3 : out std_logic;
txdetectrx0 : out std_logic; -- .txdetectrx0
txdetectrx1 : out std_logic;
txdetectrx2 : out std_logic;
txdetectrx3 : out std_logic;
txelecidle0 : out std_logic; -- .txelecidle0
txelecidle1 : out std_logic;
txelecidle2 : out std_logic;
txelecidle3 : out std_logic;
txswing0 : out std_logic; -- .txswing0
txswing1 : out std_logic;
txswing2 : out std_logic;
txswing3 : out std_logic;
txmargin0 : out std_logic_vector(2 downto 0); -- .txmargin0
txmargin1 : out std_logic_vector(2 downto 0);
txmargin2 : out std_logic_vector(2 downto 0);
txmargin3 : out std_logic_vector(2 downto 0);
txdeemph0 : out std_logic; -- .txdeemph0
txdeemph1 : out std_logic;
txdeemph2 : out std_logic;
txdeemph3 : out std_logic;
phystatus0 : in std_logic := '0'; -- .phystatus0
phystatus1 : in std_logic := '0';
phystatus2 : in std_logic := '0';
phystatus3 : in std_logic := '0';
rxdata0 : in std_logic_vector(7 downto 0) := (others => '0'); -- .rxdata0
rxdata1 : in std_logic_vector(7 downto 0) := (others => '0');
rxdata2 : in std_logic_vector(7 downto 0) := (others => '0');
rxdata3 : in std_logic_vector(7 downto 0) := (others => '0');
rxdatak0 : in std_logic := '0'; -- .rxdatak0
rxdatak1 : in std_logic := '0';
rxdatak2 : in std_logic := '0';
rxdatak3 : in std_logic := '0';
rxelecidle0 : in std_logic := '0'; -- .rxelecidle0
rxelecidle1 : in std_logic := '0';
rxelecidle2 : in std_logic := '0';
rxelecidle3 : in std_logic := '0';
rxstatus0 : in std_logic_vector(2 downto 0) := (others => '0'); -- .rxstatus0
rxstatus1 : in std_logic_vector(2 downto 0) := (others => '0');
rxstatus2 : in std_logic_vector(2 downto 0) := (others => '0');
rxstatus3 : in std_logic_vector(2 downto 0) := (others => '0');
rxvalid0 : in std_logic := '0'; -- .rxvalid0
rxvalid1 : in std_logic := '0';
rxvalid2 : in std_logic := '0';
rxvalid3 : in std_logic := '0';
reset_status : out std_logic; -- hip_rst.reset_status
serdes_pll_locked : out std_logic; -- .serdes_pll_locked
pld_clk_inuse : out std_logic; -- .pld_clk_inuse
pld_core_ready : in std_logic := '0'; -- .pld_core_ready
testin_zero : out std_logic; -- .testin_zero
lmi_addr : in std_logic_vector(11 downto 0) := (others => '0'); -- lmi.lmi_addr
lmi_din : in std_logic_vector(31 downto 0) := (others => '0'); -- .lmi_din
lmi_rden : in std_logic := '0'; -- .lmi_rden
lmi_wren : in std_logic := '0'; -- .lmi_wren
lmi_ack : out std_logic; -- .lmi_ack
lmi_dout : out std_logic_vector(31 downto 0); -- .lmi_dout
pm_auxpwr : in std_logic := '0'; -- power_mngt.pm_auxpwr
pm_data : in std_logic_vector(9 downto 0) := (others => '0'); -- .pm_data
pme_to_cr : in std_logic := '0'; -- .pme_to_cr
pm_event : in std_logic := '0'; -- .pm_event
pme_to_sr : out std_logic; -- .pme_to_sr
reconfig_to_xcvr : in std_logic_vector(349 downto 0) := (others => '0'); -- reconfig_to_xcvr.reconfig_to_xcvr
reconfig_from_xcvr : out std_logic_vector(229 downto 0); -- reconfig_from_xcvr.reconfig_from_xcvr
app_msi_num : in std_logic_vector(4 downto 0) := (others => '0'); -- int_msi.app_msi_num
app_msi_req : in std_logic := '0'; -- .app_msi_req
app_msi_tc : in std_logic_vector(2 downto 0) := (others => '0'); -- .app_msi_tc
app_msi_ack : out std_logic; -- .app_msi_ack
app_int_sts_vec : in std_logic := '0'; -- .app_int_sts
tl_hpg_ctrl_er : in std_logic_vector(4 downto 0) := (others => '0'); -- config_tl.hpg_ctrler
tl_cfg_ctl : out std_logic_vector(31 downto 0); -- .tl_cfg_ctl
cpl_err : in std_logic_vector(6 downto 0) := (others => '0'); -- .cpl_err
tl_cfg_add : out std_logic_vector(3 downto 0); -- .tl_cfg_add
tl_cfg_ctl_wr : out std_logic; -- .tl_cfg_ctl_wr
tl_cfg_sts_wr : out std_logic; -- .tl_cfg_sts_wr
tl_cfg_sts : out std_logic_vector(52 downto 0); -- .tl_cfg_sts
cpl_pending : in std_logic_vector(0 downto 0) := (others => '0'); -- .cpl_pending
derr_cor_ext_rcv0 : out std_logic; -- hip_status.derr_cor_ext_rcv
derr_cor_ext_rpl : out std_logic; -- .derr_cor_ext_rpl
derr_rpl : out std_logic; -- .derr_rpl
dlup_exit : out std_logic; -- .dlup_exit
dl_ltssm : out std_logic_vector(4 downto 0); -- .ltssmstate
ev128ns : out std_logic; -- .ev128ns
ev1us : out std_logic; -- .ev1us
hotrst_exit : out std_logic; -- .hotrst_exit
int_status : out std_logic_vector(3 downto 0); -- .int_status
l2_exit : out std_logic; -- .l2_exit
lane_act : out std_logic_vector(3 downto 0); -- .lane_act
ko_cpl_spc_header : out std_logic_vector(7 downto 0); -- .ko_cpl_spc_header
ko_cpl_spc_data : out std_logic_vector(11 downto 0); -- .ko_cpl_spc_data
dl_current_speed : out std_logic_vector(1 downto 0) -- hip_currentspeed.currentspeed
);
end component;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
component pcie_msi
generic (
WIDTH : integer range 32 downto 1
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
irq_req_i : in std_logic_vector(WIDTH -1 downto 0);
wb_int_o : out std_logic;
wb_pwr_enable_o : out std_logic;
wb_int_num_o : OUT std_logic_vector(4 downto 0);
wb_int_ack_i : in std_logic;
wb_int_num_allowed_i : in std_logic_vector(5 downto 0)
);
end component;
-------------------------------------------
-- Transceiver reconfiguration controller
-------------------------------------------
component CycVTransReconf
port(
reconfig_busy : out std_logic;
mgmt_clk_clk : in std_logic := '0';
mgmt_rst_reset : in std_logic := '0';
reconfig_mgmt_address : in std_logic_vector(6 downto 0) := (others => '0');
reconfig_mgmt_read : in std_logic := '0';
reconfig_mgmt_readdata : out std_logic_vector(31 downto 0);
reconfig_mgmt_waitrequest : out std_logic;
reconfig_mgmt_write : in std_logic := '0';
reconfig_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0');
reconfig_to_xcvr : out std_logic_vector(349 downto 0);
reconfig_from_xcvr : in std_logic_vector(229 downto 0) := (others => '0')
);
end component;
-------------------------------------------------------------------------------
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
-- coverage off
assert not no_valid_device(supported_device => SUPPORTED_DEVICES, device => FPGA_FAMILY) report "16z091-01: no valid FPGA device selected" severity failure;
--assert (USE_LANES = "001") report "16z91-01: no valid USE_LANES setting" severity failure;
assert (USE_LANES = "001" or USE_LANES = "100") report "16z91-01: no valid USE_LANES setting" severity failure;
-- coverage on
gp_debug_port <= (others => '0');
npor_int <= ext_rst_n and '1';
not_npor_int <= not npor_int;
----------------------------------
-- assign debug port if ltssm is
-- in link training mode
----------------------------------
link_train_active <= '0' when int_ltssm = "01111" else
'1';
------------------------------------------------------
-- Definition of signal test_in changed for CycloneV
-- set values as recommended in user guide page 4-51
-- -> seems to be incorrect, all 0 seems to be ok
------------------------------------------------------
--test_in_int(31 downto 12) <= (others => '1'); -- reserved
--test_in_int(11 downto 8) <= x"0"; -- set to "0011" to route PIPE interface signals to test_out
--test_in_int(7) <= '0'; -- reserved
--test_in_int(6) <= '0'; -- force entry to compliance mode
--test_in_int(5) <= '0'; -- compliance test mode
--test_in_int(4 downto 1) <= "0100"; -- reserved
test_in_int(31 downto 1) <= (others => '0');
test_in_int(0) <= SIMULATION; -- =1 for simulation to accelerate initialization
--test_in_int(31 downto 0) <= x"00000201"; --sets values as used in Altera test bench
-----------------------------------------------------
-- new HardIP ready signal for CycloneV
-- reset 16z091-01 as long as pld_clk_inuse=0
-- release rst_int 32x pld_clk after reset_status=0
-----------------------------------------------------
rst_int <= '1' when rst_cnt /= "00000" else '0';
--rst_int_n <= not rst_int;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
--------------------------------------------------------------------
-- release rst_int 32x pld_clk after reset_status=0
-- assert rst_int for min. 32x pld_clk if hotrst_exit or dlup_exit
-- or l2_exit are deasserted for 1 pld_clk cycle
--------------------------------------------------------------------
rst_seq : process(ext_rst_n, reset_status_int, core_clk_int)
begin
if ext_rst_n = '0' then
rst_cnt <= (others => '1');
elsif core_clk_int'event and core_clk_int = '1' then
if reset_status_int = '1' then
rst_cnt <= (others => '1');
elsif dlup_exit = '0' or hotrst_exit = '0' or l2_exit = '0' then
rst_cnt <= (others => '1');
elsif rst_cnt > "00000" then
rst_cnt <= rst_cnt - 1;
end if;
end if;
end process rst_seq;
------------------------------------------------------------------------
-- emulate app_int_ack behavior because signal is missing for CycloneV
------------------------------------------------------------------------
int_ack_c5 : process(rst_int, core_clk_int)
begin
if rst_int = '1' then
irq_app_int_ack <= '0';
irq_int_sts_q <= '0';
irq_int_sts_qq <= '0';
elsif core_clk_int'event and core_clk_int = '1' then
irq_int_sts_q <= app_int_sts_int;
irq_int_sts_qq <= irq_int_sts_q;
if irq_int_sts_q = '1' and irq_int_sts_qq = '0' then
----------------------------
-- acknowledge Assert_INTA
----------------------------
irq_app_int_ack <= '1';
elsif irq_int_sts_q = '0' and irq_int_sts_qq = '1' then
------------------------------
-- acknowledge Deassert_INTA
------------------------------
irq_app_int_ack <= '1';
else
irq_app_int_ack <= '0';
end if;
end if;
end process int_ack_c5;
-- +----------------------------------------------------------------------------
-- | component instantiations
-- +----------------------------------------------------------------------------
ip_16z091_01_comp : ip_16z091_01
generic map(
FPGA_FAMILY => FPGA_FAMILY,
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
READY_LATENCY => 2,
FIFO_MAX_USEDW => conv_std_logic_vector((2**RX_LPM_WIDTHU - 8),10),
WBM_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 5),10),
WBM_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
WBS_SUSPEND_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 4),10),
WBS_RESUME_FIFO_ACCESS => conv_std_logic_vector((2**TX_DATA_LPM_WIDTHU - 9),10),
PCIE_REQUEST_LENGTH => PCIE_REQUEST_LENGTH,
RX_FIFO_DEPTH => 2**RX_LPM_WIDTHU,
RX_LPM_WIDTHU => RX_LPM_WIDTHU,
TX_HEADER_FIFO_DEPTH => 2**TX_HEADER_LPM_WIDTHU,
TX_HEADER_LPM_WIDTHU => TX_HEADER_LPM_WIDTHU,
TX_DATA_FIFO_DEPTH => 2**TX_DATA_LPM_WIDTHU,
TX_DATA_LPM_WIDTHU => TX_DATA_LPM_WIDTHU
)
port map(
clk => core_clk_int,
rst => rst_int,
clk_500 => clk_500,
wb_clk => wb_clk,
wb_rst => wb_rst,
-- IP Core
core_clk => core_clk_int,
rx_st_data0 => rx_st_data0_int,
rx_st_err0 => rx_st_err0_int,
rx_st_valid0 => rx_st_valid0_int,
rx_st_sop0 => rx_st_sop0_int,
rx_st_eop0 => rx_st_eop0_int,
rx_st_be0 => rx_st_be0_int,
rx_st_bardec0 => rx_st_bardec0_int,
tx_st_ready0 => tx_st_ready0_int,
tx_fifo_full0 => tx_fifo_full0_int,
tx_fifo_empty0 => tx_fifo_empty0_int,
tx_fifo_rdptr0 => tx_fifo_rdptr0_int,
tx_fifo_wrptr0 => tx_fifo_wrptr0_int,
pme_to_sr => pme_to_sr_int,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
--TODO ITEM change next line when app_int_ack is added to CycloneV again by Altera
app_int_ack => irq_app_int_ack, --app_int_ack_int,
app_msi_ack => app_msi_ack_int,
rx_st_mask0 => rx_st_mask0_int,
rx_st_ready0 => rx_st_ready0_int,
tx_st_err0 => tx_st_err0_int,
tx_st_valid0 => tx_st_valid0_int,
tx_st_sop0 => tx_st_sop0_int,
tx_st_eop0 => tx_st_eop0_int,
tx_st_data0 => tx_st_data0_int,
pme_to_cr => pme_to_cr_int,
app_int_sts => app_int_sts_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
app_msi_num => app_msi_num_int,
pex_msi_num => pex_msi_num_int,
derr_cor_ext_rcv => derr_cor_ext_rcv_int,
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
r2c_err0 => r2c_err0_int,
cpl_err => cpl_err_int,
cpl_pending => cpl_pending_int,
-- Wishbone master
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
wbm_cyc_o => wbm_cyc_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
-- Wishbone slave
wbs_cyc => wbs_cyc,
wbs_stb => wbs_stb,
wbs_we => wbs_we,
wbs_sel => wbs_sel,
wbs_adr => wbs_adr,
wbs_dat_i => wbs_dat_i,
wbs_cti => wbs_cti,
wbs_tga => wbs_tga,
wbs_ack => wbs_ack,
wbs_err => wbs_err,
wbs_dat_o => wbs_dat_o,
-- interrupt
wb_int => int_wb_int,
wb_pwr_enable => int_wb_pwr_enable,
wb_int_num => int_wb_int_num,
wb_int_ack => int_wb_int_ack,
wb_int_num_allowed => int_wb_int_num_allowed,
-- error
error_timeout => error_timeout,
error_cor_ext_rcv => error_cor_ext_rcv,
error_cor_ext_rpl => error_cor_ext_rpl,
error_rpl => error_rpl,
error_r2c0 => error_r2c0,
error_msi_num => error_msi_num,
-- debug port
rx_debug_out => open
);
gen_cycv_x1: if USE_LANES = "001" generate
PCIeHardIP_CycV_x1_comp : PCIeHardIPCycV
port map(
-- inputs:
app_int_sts_vec => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
cpl_err => cpl_err_int,
cpl_pending(0) => cpl_pending_int,
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
npor => npor_int,
phystatus0 => '0', -- if asserted LTSSM is stuck at x"00"
phystatus1 => '0', -- if asserted LTSSM is stuck at x"00"
-- pin_perst must be connected to nPERST of correct location in device
-- nPERSTL0 for top left
-- nPERSTL1 for bottom left <-- use this one first (recommended by Altera)
pin_perst => ext_rst_n, --'0',
pld_clk => core_clk_int,
pld_core_ready => serdes_pll_locked_int,
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_to_xcvr => reconfig_to_xcvr_int(2*70-1 downto 0), -- 2 reconfig interfaces
refclk => ref_clk,
rx_in0 => rx_0,
rx_in1 => '0',
rx_in2 => '0',
rx_in3 => '0',
rx_st_mask => rx_st_mask0_int,
rx_st_ready => rx_st_ready0_int,
rxdata0 => (others => '0'),
rxdata1 => (others => '0'),
rxdata2 => (others => '0'),
rxdata3 => (others => '0'),
rxdatak0 => '0',
rxdatak1 => '0',
rxdatak2 => '0',
rxdatak3 => '0',
rxelecidle0 => '0',
rxelecidle1 => '0',
rxelecidle2 => '0',
rxelecidle3 => '0',
rxstatus0 => (others => '0'),
rxstatus1 => (others => '0'),
rxstatus2 => (others => '0'),
rxstatus3 => (others => '0'),
rxvalid0 => '0',
rxvalid1 => '0',
rxvalid2 => '0',
rxvalid3 => '0',
sim_pipe_pclk_in => core_clk_int, -- simulation only
simu_mode_pipe => SIMULATION, -- indicate simulation mode
test_in => test_in_int(31 downto 0),
tl_hpg_ctrl_er => (others => '0'), -- hardwire to 0 for endpoints
tx_st_data => tx_st_data0_int,
tx_st_eop => tx_st_eop0_int,
tx_st_err => tx_st_err0_int,
tx_st_sop => tx_st_sop0_int,
tx_st_valid => tx_st_valid0_int,
-- outputs:
app_msi_ack => app_msi_ack_int,
coreclkout => core_clk_int,
derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
dl_current_speed => open, -- indicate current speed of PCIe link
dl_ltssm => int_ltssm,
dlup_exit => dlup_exit,
eidleinfersel0 => open, -- electrical idle entry inference mechanism
eidleinfersel1 => open, -- electrical idle entry inference mechanism
eidleinfersel2 => open, -- electrical idle entry inference mechanism
eidleinfersel3 => open, -- electrical idle entry inference mechanism
ev128ns => open, -- asserted every 128ns
ev1us => open, -- asserted every 1us
hotrst_exit => hotrst_exit,
int_status => open, -- defined as root port signal which shows legacy irq,
-- int_status[0] = A, int_status[3] = D
ko_cpl_spc_data => open,
ko_cpl_spc_header => open,
l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
pld_clk_inuse => open, --pld_clk_inuse_int,
pme_to_sr => pme_to_sr_int,
powerdown0 => open,
powerdown1 => open,
powerdown2 => open,
powerdown3 => open,
reconfig_from_xcvr => reconfig_from_xcvr_int(2*46-1 downto 0), -- 2 reconfig interfaces
reset_status => reset_status_int,
rx_st_bar => rx_st_bardec0_int,
rx_st_be => rx_st_be0_int,
rx_st_data => rx_st_data0_int,
rx_st_eop => rx_st_eop0_int,
rx_st_err => rx_st_err0_int,
rx_st_sop => rx_st_sop0_int,
rx_st_valid => rx_st_valid0_int,
rxpolarity0 => open,
rxpolarity1 => open,
rxpolarity2 => open,
rxpolarity3 => open,
serdes_pll_locked => serdes_pll_locked_int,
sim_ltssmstate => open, --alt_bfm_sim_ltssm, -- show LTSSM state
sim_pipe_rate => open, --alt_bfm_sim_pipe_rate, -- show Gen1,2,3
testin_zero => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred_datafccp => open,
tx_cred_datafcnp => open,
tx_cred_datafcp => open,
tx_cred_fchipcons => open,
tx_cred_fcinfinite => open,
tx_cred_hdrfccp => open,
tx_cred_hdrfcnp => open,
tx_cred_hdrfcp => open,
tx_fifo_empty => tx_fifo_empty0_int,
tx_out0 => tx_0,
tx_out1 => open,
tx_out2 => open,
tx_out3 => open,
tx_st_ready => tx_st_ready0_int,
txcompl0 => open,
txcompl1 => open,
txcompl2 => open,
txcompl3 => open,
txdata0 => open,
txdata1 => open,
txdata2 => open,
txdata3 => open,
txdatak0 => open,
txdatak1 => open,
txdatak2 => open,
txdatak3 => open,
txdeemph0 => open,
txdeemph1 => open,
txdeemph2 => open,
txdeemph3 => open,
txdetectrx0 => open,
txdetectrx1 => open,
txdetectrx2 => open,
txdetectrx3 => open,
txelecidle0 => open,
txelecidle1 => open,
txelecidle2 => open,
txelecidle3 => open,
txmargin0 => open, -- simulation only
txmargin1 => open, -- simulation only
txmargin2 => open, -- simulation only
txmargin3 => open, -- simulation only
txswing0 => open, -- =1: V_OD full swing, =0 half swing
txswing1 => open, -- =1: V_OD full swing, =0 half swing
txswing2 => open, -- =1: V_OD full swing, =0 half swing
txswing3 => open -- =1: V_OD full swing, =0 half swing
);
------------------------------------------------------
-- set default values for signals which are not used
------------------------------------------------------
derr_cor_ext_rcv_int(1) <= '0';
--reconfig_from_xcvr_int(229 downto 92) <= (others => '0');
reconfig_from_xcvr_int(MAX_RECONF_IF*46-1 downto 2*46) <= (others => '0');
tx_fifo_full0_int <= '0';
tx_fifo_rdptr0_int <= (others => '0');
tx_fifo_wrptr0_int <= (others => '0');
pex_msi_num_int <= (others => '0');
r2c_err0_int <= '0';
----------------------------------------
-- set default values for unused ports
----------------------------------------
tx_1 <= '1';
tx_2 <= '1';
tx_3 <= '1';
--------------------------------
-- manage CycloneV transceiver
--------------------------------
cycv_trans_reconf_i0 : CycVTransReconf
port map(
-- inputs
mgmt_clk_clk => ref_clk, -- CycloneV: 75-100MHz
mgmt_rst_reset => not_npor_int, -- high active
reconfig_mgmt_address => (others => '0'),
reconfig_mgmt_read => '0',
reconfig_mgmt_write => '0',
reconfig_mgmt_writedata => (others => '0'),
reconfig_from_xcvr => reconfig_from_xcvr_int(2*46-1 downto 0),
-- outputs
reconfig_busy => reconfig_busy_int,
reconfig_mgmt_readdata => open,
reconfig_mgmt_waitrequest => open,
reconfig_to_xcvr => reconfig_to_xcvr_int(2*70-1 downto 0)
);
end generate gen_cycv_x1;
gen_cycv_x2: if USE_LANES = "010" generate
PCIeHardIP_CycV_x1_comp : PCIeHardIPCycV
port map(
-- inputs:
app_int_sts_vec => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
cpl_err => cpl_err_int,
cpl_pending(0) => cpl_pending_int,
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
npor => npor_int,
phystatus0 => '0', -- if asserted LTSSM is stuck at x"00"
phystatus1 => '0', -- if asserted LTSSM is stuck at x"00"
phystatus2 => '0', -- if asserted LTSSM is stuck at x"00"
phystatus3 => '0', -- if asserted LTSSM is stuck at x"00"
-- pin_perst must be connected to nPERST of correct location in device
-- nPERSTL0 for top left
-- nPERSTL1 for bottom left <-- use this one first (recommended by Altera)
pin_perst => ext_rst_n, --'0',
pld_clk => core_clk_int,
pld_core_ready => serdes_pll_locked_int,
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_to_xcvr => reconfig_to_xcvr_int(3*70-1 downto 0),
refclk => ref_clk,
rx_in0 => rx_0,
rx_in1 => rx_1,
rx_in2 => '0',
rx_in3 => '0',
rx_st_mask => rx_st_mask0_int,
rx_st_ready => rx_st_ready0_int,
rxdata0 => (others => '0'),
rxdata1 => (others => '0'),
rxdata2 => (others => '0'),
rxdata3 => (others => '0'),
rxdatak0 => '0',
rxdatak1 => '0',
rxdatak2 => '0',
rxdatak3 => '0',
rxelecidle0 => '0',
rxelecidle1 => '0',
rxelecidle2 => '0',
rxelecidle3 => '0',
rxstatus0 => (others => '0'),
rxstatus1 => (others => '0'),
rxstatus2 => (others => '0'),
rxstatus3 => (others => '0'),
rxvalid0 => '0',
rxvalid1 => '0',
rxvalid2 => '0',
rxvalid3 => '0',
sim_pipe_pclk_in => core_clk_int, -- simulation only
simu_mode_pipe => SIMULATION, -- indicate simulation mode
test_in => test_in_int(31 downto 0),
tl_hpg_ctrl_er => (others => '0'), -- hardwire to 0 for endpoints
tx_st_data => tx_st_data0_int,
tx_st_eop => tx_st_eop0_int,
tx_st_err => tx_st_err0_int,
tx_st_sop => tx_st_sop0_int,
tx_st_valid => tx_st_valid0_int,
-- outputs:
app_msi_ack => app_msi_ack_int,
coreclkout => core_clk_int,
derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
dl_current_speed => open, -- indicate current speed of PCIe link
dl_ltssm => int_ltssm,
dlup_exit => dlup_exit,
eidleinfersel0 => open, -- electrical idle entry inference mechanism
eidleinfersel1 => open, -- electrical idle entry inference mechanism
eidleinfersel2 => open, -- electrical idle entry inference mechanism
eidleinfersel3 => open, -- electrical idle entry inference mechanism
ev128ns => open, -- asserted every 128ns
ev1us => open, -- asserted every 1us
hotrst_exit => hotrst_exit,
int_status => open, -- defined as root port signal which shows legacy irq,
-- int_status[0] = A, int_status[3] = D
ko_cpl_spc_data => open,
ko_cpl_spc_header => open,
l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
pld_clk_inuse => open, --pld_clk_inuse_int,
pme_to_sr => pme_to_sr_int,
powerdown0 => open,
powerdown1 => open,
powerdown2 => open,
powerdown3 => open,
reconfig_from_xcvr => reconfig_from_xcvr_int(3*46-1 downto 0),
reset_status => reset_status_int,
rx_st_bar => rx_st_bardec0_int,
rx_st_be => rx_st_be0_int,
rx_st_data => rx_st_data0_int,
rx_st_eop => rx_st_eop0_int,
rx_st_err => rx_st_err0_int,
rx_st_sop => rx_st_sop0_int,
rx_st_valid => rx_st_valid0_int,
rxpolarity0 => open,
rxpolarity1 => open,
rxpolarity2 => open,
rxpolarity3 => open,
serdes_pll_locked => serdes_pll_locked_int,
sim_ltssmstate => open, --alt_bfm_sim_ltssm, -- show LTSSM state
sim_pipe_rate => open, --alt_bfm_sim_pipe_rate, -- show Gen1,2,3
testin_zero => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred_datafccp => open,
tx_cred_datafcnp => open,
tx_cred_datafcp => open,
tx_cred_fchipcons => open,
tx_cred_fcinfinite => open,
tx_cred_hdrfccp => open,
tx_cred_hdrfcnp => open,
tx_cred_hdrfcp => open,
tx_fifo_empty => tx_fifo_empty0_int,
tx_out0 => tx_0,
tx_out1 => tx_1,
tx_out2 => open,
tx_out3 => open,
tx_st_ready => tx_st_ready0_int,
txcompl0 => open,
txcompl1 => open,
txcompl2 => open,
txcompl3 => open,
txdata0 => open,
txdata1 => open,
txdata2 => open,
txdata3 => open,
txdatak0 => open,
txdatak1 => open,
txdatak2 => open,
txdatak3 => open,
txdeemph0 => open,
txdeemph1 => open,
txdeemph2 => open,
txdeemph3 => open,
txdetectrx0 => open,
txdetectrx1 => open,
txdetectrx2 => open,
txdetectrx3 => open,
txelecidle0 => open,
txelecidle1 => open,
txelecidle2 => open,
txelecidle3 => open,
txmargin0 => open, -- simulation only
txmargin1 => open, -- simulation only
txmargin2 => open, -- simulation only
txmargin3 => open, -- simulation only
txswing0 => open, -- =1: V_OD full swing, =0 half swing
txswing1 => open, -- =1: V_OD full swing, =0 half swing
txswing2 => open, -- =1: V_OD full swing, =0 half swing
txswing3 => open -- =1: V_OD full swing, =0 half swing
);
------------------------------------------------------
-- set default values for signals which are not used
------------------------------------------------------
derr_cor_ext_rcv_int(1) <= '0';
reconfig_from_xcvr_int(MAX_RECONF_IF*46-1 downto 3*46) <= (others => '0');
tx_fifo_full0_int <= '0';
tx_fifo_rdptr0_int <= (others => '0');
tx_fifo_wrptr0_int <= (others => '0');
pex_msi_num_int <= (others => '0');
r2c_err0_int <= '0';
----------------------------------------
-- set default values for unused ports
----------------------------------------
tx_2 <= '1';
tx_3 <= '1';
--------------------------------
-- manage CycloneV transceiver
--------------------------------
cycv_trans_reconf_i0 : CycVTransReconf
port map(
-- inputs
mgmt_clk_clk => ref_clk, -- CycloneV: 75-100MHz
mgmt_rst_reset => not_npor_int, -- high active
reconfig_mgmt_address => (others => '0'),
reconfig_mgmt_read => '0',
reconfig_mgmt_write => '0',
reconfig_mgmt_writedata => (others => '0'),
reconfig_from_xcvr => reconfig_from_xcvr_int(3*46-1 downto 0),
-- outputs
reconfig_busy => reconfig_busy_int,
reconfig_mgmt_readdata => open,
reconfig_mgmt_waitrequest => open,
reconfig_to_xcvr => reconfig_to_xcvr_int(3*70-1 downto 0)
);
end generate gen_cycv_x2;
gen_cycv_x4: if USE_LANES = "100" generate
PCIeHardIP_CycV_x1_comp : PCIeHardIPCycV
port map(
-- inputs:
app_int_sts_vec => app_int_sts_int,
app_msi_num => app_msi_num_int,
app_msi_req => app_msi_req_int,
app_msi_tc => app_msi_tc_int,
cpl_err => cpl_err_int,
cpl_pending(0) => cpl_pending_int,
lmi_addr => (others => '0'),
lmi_din => (others => '0'),
lmi_rden => '0',
lmi_wren => '0',
npor => npor_int,
phystatus0 => '0', -- if asserted LTSSM is stuck at x"00"
phystatus1 => '0', -- if asserted LTSSM is stuck at x"00"
-- pin_perst must be connected to nPERST of correct location in device
-- nPERSTL0 for top left
-- nPERSTL1 for bottom left <-- use this one first (recommended by Altera)
pin_perst => ext_rst_n, --'0',
pld_clk => core_clk_int,
pld_core_ready => serdes_pll_locked_int,
pm_auxpwr => '0',
pm_data => (others => '0'),
pm_event => '0',
pme_to_cr => pme_to_cr_int,
reconfig_to_xcvr => reconfig_to_xcvr_int(3*70-1 downto 0),
refclk => ref_clk,
rx_in0 => rx_0,
rx_in1 => rx_1,
rx_in2 => rx_2,
rx_in3 => rx_3,
rx_st_mask => rx_st_mask0_int,
rx_st_ready => rx_st_ready0_int,
rxdata0 => (others => '0'),
rxdata1 => (others => '0'),
rxdata2 => (others => '0'),
rxdata3 => (others => '0'),
rxdatak0 => '0',
rxdatak1 => '0',
rxdatak2 => '0',
rxdatak3 => '0',
rxelecidle0 => '0',
rxelecidle1 => '0',
rxelecidle2 => '0',
rxelecidle3 => '0',
rxstatus0 => (others => '0'),
rxstatus1 => (others => '0'),
rxstatus2 => (others => '0'),
rxstatus3 => (others => '0'),
rxvalid0 => '0',
rxvalid1 => '0',
rxvalid2 => '0',
rxvalid3 => '0',
sim_pipe_pclk_in => core_clk_int, -- simulation only
simu_mode_pipe => SIMULATION, -- indicate simulation mode
test_in => test_in_int(31 downto 0),
tl_hpg_ctrl_er => (others => '0'), -- hardwire to 0 for endpoints
tx_st_data => tx_st_data0_int,
tx_st_eop => tx_st_eop0_int,
tx_st_err => tx_st_err0_int,
tx_st_sop => tx_st_sop0_int,
tx_st_valid => tx_st_valid0_int,
-- outputs:
app_msi_ack => app_msi_ack_int,
coreclkout => core_clk_int,
derr_cor_ext_rcv0 => derr_cor_ext_rcv_int(0),
derr_cor_ext_rpl => derr_cor_ext_rpl_int,
derr_rpl => derr_rpl_int,
dl_current_speed => open, -- indicate current speed of PCIe link
dl_ltssm => int_ltssm,
dlup_exit => dlup_exit,
eidleinfersel0 => open, -- electrical idle entry inference mechanism
eidleinfersel1 => open, -- electrical idle entry inference mechanism
eidleinfersel2 => open, -- electrical idle entry inference mechanism
eidleinfersel3 => open, -- electrical idle entry inference mechanism
ev128ns => open, -- asserted every 128ns
ev1us => open, -- asserted every 1us
hotrst_exit => hotrst_exit,
int_status => open, -- defined as root port signal which shows legacy irq,
-- int_status[0] = A, int_status[3] = D
ko_cpl_spc_data => open,
ko_cpl_spc_header => open,
l2_exit => l2_exit,
lane_act => open,
lmi_ack => open,
lmi_dout => open,
pld_clk_inuse => open, --pld_clk_inuse_int,
pme_to_sr => pme_to_sr_int,
powerdown0 => open,
powerdown1 => open,
powerdown2 => open,
powerdown3 => open,
reconfig_from_xcvr => reconfig_from_xcvr_int(3*46-1 downto 0),
reset_status => reset_status_int,
rx_st_bar => rx_st_bardec0_int,
rx_st_be => rx_st_be0_int,
rx_st_data => rx_st_data0_int,
rx_st_eop => rx_st_eop0_int,
rx_st_err => rx_st_err0_int,
rx_st_sop => rx_st_sop0_int,
rx_st_valid => rx_st_valid0_int,
rxpolarity0 => open,
rxpolarity1 => open,
rxpolarity2 => open,
rxpolarity3 => open,
serdes_pll_locked => serdes_pll_locked_int,
sim_ltssmstate => open, --alt_bfm_sim_ltssm, -- show LTSSM state
sim_pipe_rate => open, --alt_bfm_sim_pipe_rate, -- show Gen1,2,3
testin_zero => open,
tl_cfg_add => tl_cfg_add_int,
tl_cfg_ctl => tl_cfg_ctl_int,
tl_cfg_ctl_wr => tl_cfg_ctl_wr_int,
tl_cfg_sts => tl_cfg_sts_int,
tl_cfg_sts_wr => tl_cfg_sts_wr_int,
tx_cred_datafccp => open,
tx_cred_datafcnp => open,
tx_cred_datafcp => open,
tx_cred_fchipcons => open,
tx_cred_fcinfinite => open,
tx_cred_hdrfccp => open,
tx_cred_hdrfcnp => open,
tx_cred_hdrfcp => open,
tx_fifo_empty => tx_fifo_empty0_int,
tx_out0 => tx_0,
tx_out1 => tx_1,
tx_out2 => tx_2,
tx_out3 => tx_3,
tx_st_ready => tx_st_ready0_int,
txcompl0 => open,
txcompl1 => open,
txcompl2 => open,
txcompl3 => open,
txdata0 => open,
txdata1 => open,
txdata2 => open,
txdata3 => open,
txdatak0 => open,
txdatak1 => open,
txdatak2 => open,
txdatak3 => open,
txdeemph0 => open,
txdeemph1 => open,
txdeemph2 => open,
txdeemph3 => open,
txdetectrx0 => open,
txdetectrx1 => open,
txdetectrx2 => open,
txdetectrx3 => open,
txelecidle0 => open,
txelecidle1 => open,
txelecidle2 => open,
txelecidle3 => open,
txmargin0 => open, -- simulation only
txmargin1 => open, -- simulation only
txmargin2 => open, -- simulation only
txmargin3 => open, -- simulation only
txswing0 => open, -- =1: V_OD full swing, =0 half swing
txswing1 => open, -- =1: V_OD full swing, =0 half swing
txswing2 => open, -- =1: V_OD full swing, =0 half swing
txswing3 => open -- =1: V_OD full swing, =0 half swing
);
------------------------------------------------------
-- set default values for signals which are not used
------------------------------------------------------
derr_cor_ext_rcv_int(1) <= '0';
reconfig_from_xcvr_int(MAX_RECONF_IF*46-1 downto 3*46) <= (others => '0');
tx_fifo_full0_int <= '0';
tx_fifo_rdptr0_int <= (others => '0');
tx_fifo_wrptr0_int <= (others => '0');
pex_msi_num_int <= (others => '0');
r2c_err0_int <= '0';
--------------------------------
-- manage CycloneV transceiver
--------------------------------
cycv_trans_reconf_i0 : CycVTransReconf
port map(
-- inputs
mgmt_clk_clk => ref_clk, -- CycloneV: 75-100MHz
mgmt_rst_reset => not_npor_int, -- high active
reconfig_mgmt_address => (others => '0'),
reconfig_mgmt_read => '0',
reconfig_mgmt_write => '0',
reconfig_mgmt_writedata => (others => '0'),
reconfig_from_xcvr => reconfig_from_xcvr_int(3*46-1 downto 0),
-- outputs
reconfig_busy => reconfig_busy_int,
reconfig_mgmt_readdata => open,
reconfig_mgmt_waitrequest => open,
reconfig_to_xcvr => reconfig_to_xcvr_int(3*70-1 downto 0)
);
end generate gen_cycv_x4;
---------------------------------------
-- module to convert irq_req_i vector
-- to 16z091-01 irq behavior
---------------------------------------
pcie_msi_i0 : pcie_msi
generic map(
WIDTH => IRQ_WIDTH
)
port map(
clk_i => wb_clk,
rst_i => wb_rst,
irq_req_i => irq_req_i,
wb_int_o => int_wb_int,
wb_pwr_enable_o => int_wb_pwr_enable,
wb_int_num_o => int_wb_int_num,
wb_int_ack_i => int_wb_int_ack,
wb_int_num_allowed_i => int_wb_int_num_allowed
);
-------------------------------------------------------------------------------
end architecture ip_16z091_01_top_cycv_arch;
| gpl-3.0 | bed87d637938a529e9feb8593f404c74 | 0.434815 | 3.780636 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_signal_2.vhd | 2 | 22,015 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_signal_2.c
-- NUM_THREADS = 3
-- reg1 = i
-- reg2 = * mutex
-- reg3 = * cond
-- reg4 = * start_num
-- reg5 = * havelock_num
-- reg6 = * function
-- reg7 = * attr
-- reg8 = thread[i]
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of cond
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg4_next <= intrfc2thrd_value;
-- Read the address of havelock_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 12;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg5_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 16;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg6_next <= intrfc2thrd_value;
-- Read the address of attr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 20;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_7 =>
reg7_next <= intrfc2thrd_value;
-- set i=0
reg1_next <= Z32;
next_state <= STATE_8;
when STATE_8 =>
case reg1 is
when x"00000000" => next_state <= STATE_9;
when x"00000001" => next_state <= STATE_9;
when x"00000002" => next_state <= STATE_9;
when others => next_state <= STATE_14;
end case;
-- hthread_create( &data->thread[i], data->attr, data->function, (void *) data );
when STATE_9 =>
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- push &data->thread[i]
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000018" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
reg1_next <= reg1 + x"00000001";
-- while( *(data->start_num) != THREAD_NUM ) hthread_yield();
when STATE_14 =>
-- Read the value of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
case intrfc2thrd_value is
when x"00000003" => next_state <= STATE_17;
when others => next_state <= STATE_16;
end case;
when STATE_16 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->mutex );
when STATE_17 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
-- hthread_cond_signal( data->cond );
when STATE_19 =>
-- push data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call hthread_cond_signal
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->mutex );
when STATE_21 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- while( *(data->havelock_num) == 0 ) hthread_yield();
when STATE_23 =>
-- Read the value of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_24 =>
case intrfc2thrd_value is
when x"00000000" => next_state <= STATE_25;
when others => next_state <= STATE_26;
end case;
when STATE_25 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- retVal = *( data->havelock_num )
when STATE_26 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_27;
when STATE_27 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | e2178c6ff15454a1cf6c11d1b19a3445 | 0.552351 | 3.635838 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_trylock_1.vhd | 2 | 16,356 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_trylock_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_lock( mutex );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_trylock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_TRYLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- if( _mutex_owner( mutex->num ) != hthread_self() )
when STATE_4 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg1_next <= intrfc2thrd_value;
-- Call the Synch Manager to find out the owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg1_next <= intrfc2thrd_value;
-- Call hthread_self();
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_SELF;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
if ( intrfc2thrd_value = reg1 ) then
retVal_next <= x"00000001";
else
retVal_next <= Z32;
end if;
next_state <= STATE_8;
-- hthread_mutex_unlock( mutex );
when STATE_8 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- Call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
when STATE_10 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 4a3212c2178710aaed22ba0e107890cb | 0.544815 | 3.794896 | false | false | false | false |
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