repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Paebbels/PicoBlaze-Library | vhdl/Wrapper/pb_UART_Wrapper.vhdl | 1 | 10,211 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze UART Wrapper
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.uart.all;
use PoC.xil.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
use L_PicoBlaze.pb_comp.all;
entity pb_UART_Wrapper is
generic (
DEBUG : BOOLEAN := TRUE;
ENABLE_CHIPSCOPE : BOOLEAN := TRUE;
CLOCK_FREQ : FREQ := 100 MHz;
BAUDRATE : BAUD := 115200 Bd;
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
USE_POC_UART : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
ICON_ControlBus : inout T_XIL_CHIPSCOPE_CONTROL;
-- UART physical interface
UART_TX : out STD_LOGIC;
UART_RX : in STD_LOGIC
);
end entity;
architecture rtl of pb_UART_Wrapper is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
signal Adapter_TX_put : STD_LOGIC;
signal Adapter_TX_Data : T_SLV_8;
signal UART_TX_Empty_n : STD_LOGIC;
signal UART_TX_HalfFull : STD_LOGIC;
signal UART_TX_Full : STD_LOGIC;
signal UART_RX_Data : T_SLV_8;
signal Adapter_RX_got : STD_LOGIC;
signal UART_RX_Empty_n : STD_LOGIC;
signal UART_RX_HalfFull : STD_LOGIC;
signal UART_RX_Full : STD_LOGIC;
signal UART_TX_i : STD_LOGIC;
BEGIN
assert FALSE report "pb_UART_Wrapper: BAUDRATE=: " & to_string(BAUDRATE, 3) severity NOTE;
assert io_UART_IsTypicalBaudRate(BAUDRATE) report "The given baudrate is not known to be a typical baudrate!" severity WARNING;
UART : entity L_PicoBlaze.pb_UART_Device
generic map (
DEVICE_INSTANCE => DEVICE_INSTANCE
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
Address => Address,
WriteStrobe => WriteStrobe,
WriteStrobe_K => WriteStrobe_K,
ReadStrobe => ReadStrobe,
DataIn => DataIn,
DataOut => DataOut,
Interrupt => Interrupt,
Interrupt_Ack => Interrupt_Ack,
Message => Message,
UART_TX_put => Adapter_TX_put,
UART_TX_Data => Adapter_TX_Data,
UART_TX_Empty_n => UART_TX_Empty_n,
UART_TX_HalfFull => UART_TX_HalfFull,
UART_TX_Full => UART_TX_Full,
UART_RX_got => Adapter_RX_got,
UART_RX_Data => UART_RX_Data,
UART_RX_Empty_n => UART_RX_Empty_n,
UART_RX_HalfFull => UART_RX_HalfFull,
UART_RX_Full => UART_RX_Full
);
genXilinx : if (USE_POC_UART = FALSE) generate
constant UART_OVERSAMPLING_RATE : POSITIVE := 16;
constant TIME_UNIT_INTERVAL : TIME := 1 sec / (to_real(BAUDRATE, 1 Bd) * real(UART_OVERSAMPLING_RATE));
constant BAUDRATE_COUNTER_MAX : POSITIVE := TimingToCycles(TIME_UNIT_INTERVAL, CLOCK_FREQ);
constant BAUDRATE_COUNTER_BITS : POSITIVE := log2ceilnz(BAUDRATE_COUNTER_MAX + 1);
signal BaudRate_Counter_us : UNSIGNED(BAUDRATE_COUNTER_BITS + 1 downto 0) := (others => '0');
signal BaudRate_Counter_eq : STD_LOGIC;
signal ClockEnable : STD_LOGIC;
begin
assert FALSE report " TIME_UNIT_INTERVAL: " & to_string(TIME_UNIT_INTERVAL, 3) severity NOTE;
assert FALSE report " BAUDRATE_COUNTER_MAX: " & INTEGER'image(BAUDRATE_COUNTER_MAX) severity NOTE;
BaudRate_Counter_us <= upcounter_next(cnt => BaudRate_Counter_us, rst => BaudRate_Counter_eq) when rising_edge(Clock);
BaudRate_Counter_eq <= upcounter_equal(cnt => BaudRate_Counter_us, value => (BAUDRATE_COUNTER_MAX - 1));
ClockEnable <= BaudRate_Counter_eq;
gen00 : if (DEVICE = DEVICE_VIRTEX5) generate
TX : uart_tx6_unconstrained
port map (
clk => Clock,
buffer_reset => Reset,
en_16_x_baud => ClockEnable,
data_in => Adapter_TX_Data,
buffer_write => Adapter_TX_put,
buffer_data_present => UART_TX_Empty_n,
buffer_half_full => UART_TX_HalfFull,
buffer_full => UART_TX_Full,
serial_out => UART_TX_i
);
end generate;
gen01 : if (DEVICE /= DEVICE_VIRTEX5) generate
TX : uart_tx6
port map (
clk => Clock,
buffer_reset => Reset,
en_16_x_baud => ClockEnable,
data_in => Adapter_TX_Data,
buffer_write => Adapter_TX_put,
buffer_data_present => UART_TX_Empty_n,
buffer_half_full => UART_TX_HalfFull,
buffer_full => UART_TX_Full,
serial_out => UART_TX_i
);
end generate;
gen10 : if (DEVICE = DEVICE_VIRTEX5) generate
RX : uart_rx6_unconstrained
port map (
clk => Clock,
buffer_reset => Reset,
en_16_x_baud => ClockEnable,
data_out => UART_RX_Data,
buffer_read => Adapter_RX_got,
buffer_data_present => UART_RX_Empty_n,
buffer_half_full => UART_RX_HalfFull,
buffer_full => UART_RX_Full,
serial_in => UART_RX
);
end generate;
gen11 : if (DEVICE /= DEVICE_VIRTEX5) generate
RX : uart_rx6
port map (
clk => Clock,
buffer_reset => Reset,
en_16_x_baud => ClockEnable,
data_out => UART_RX_Data,
buffer_read => Adapter_RX_got,
buffer_data_present => UART_RX_Empty_n,
buffer_half_full => UART_RX_HalfFull,
buffer_full => UART_RX_Full,
serial_in => UART_RX
);
end generate;
end generate;
genPoC : if (USE_POC_UART = TRUE) generate
constant FIFO_DEPTH : POSITIVE := 32;
constant FILLSTATE_BITS : POSITIVE := log2ceil(FIFO_DEPTH);
signal UART_TX_EmptyState : STD_LOGIC_VECTOR(FILLSTATE_BITS - 1 downto 0);
signal UART_RX_FullState : STD_LOGIC_VECTOR(FILLSTATE_BITS - 1 downto 0);
begin
UART : entity PoC.uart_fifo
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE,
FLOWCONTROL => UART_FLOWCONTROL_NONE,
TX_MIN_DEPTH => FIFO_DEPTH,
TX_ESTATE_BITS => FILLSTATE_BITS,
RX_MIN_DEPTH => FIFO_DEPTH,
RX_FSTATE_BITS => FILLSTATE_BITS
)
port map (
Clock => Clock,
Reset => Reset,
-- FIFO interface
TX_put => Adapter_TX_put,
TX_Data => Adapter_TX_Data,
TX_Full => UART_TX_Full,
TX_EmptyState => UART_TX_EmptyState,
RX_Valid => UART_RX_Empty_n,
RX_Data => UART_RX_Data,
RX_got => Adapter_RX_got,
RX_FullState => UART_RX_FullState,
RX_Overflow => open,
-- External Pins
UART_TX => UART_TX_i,
UART_RX => UART_RX
);
UART_TX_Empty_n <= to_sl(unsigned(UART_TX_EmptyState) < 31);
UART_TX_HalfFull <= to_sl(unsigned(UART_TX_EmptyState) <= 7);
UART_RX_HalfFull <= to_sl(unsigned(UART_RX_FullState) >= 8);
UART_RX_Full <= to_sl(unsigned(UART_RX_FullState) >= 16);
end generate;
-- assign outputs
UART_TX <= UART_TX_i;
genDebug : if (ENABLE_CHIPSCOPE = TRUE) generate
signal Trigger0 : STD_LOGIC_VECTOR(29 downto 0);
signal Trigger0_d : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');
begin
Trigger0(0) <= Reset;
Trigger0(1) <= '0';
Trigger0(2) <= Adapter_RX_got;
Trigger0(10 downto 3) <= UART_RX_Data;
Trigger0(11) <= UART_RX_Empty_n;
Trigger0(12) <= UART_RX_HalfFull;
Trigger0(13) <= UART_RX_Full;
Trigger0(14) <= Adapter_TX_put;
Trigger0(22 downto 15) <= Adapter_TX_Data;
Trigger0(23) <= UART_TX_Empty_n;
Trigger0(24) <= UART_TX_HalfFull;
Trigger0(25) <= UART_TX_Full;
Trigger0(26) <= UART_TX_i;
Trigger0(27) <= UART_RX;
Trigger0(28) <= Address(0);
Trigger0(29) <= ReadStrobe;
Trigger0_d <= Trigger0 when rising_edge(Clock);
CSP_UART : entity L_PicoBlaze.CSP_UART_ILA
port map (
CONTROL => ICON_ControlBus,
CLK => Clock,
TRIG0 => Trigger0_d,
TRIG_OUT => open
);
end generate;
end;
| apache-2.0 | 04fbe304e584c28c45529fc2dba4fa5d | 0.544805 | 3.093305 | false | false | false | false |
minosys-jp/FPGA | Zybo/vgagraph/vgagraph/src/vgagraph_fifo/synth/vgagraph_fifo.vhd | 1 | 38,941 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY vgagraph_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END vgagraph_fifo;
ARCHITECTURE vgagraph_fifo_arch OF vgagraph_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF vgagraph_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF vgagraph_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF vgagraph_fifo_arch : ARCHITECTURE IS "vgagraph_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF vgagraph_fifo_arch: ARCHITECTURE IS "vgagraph_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=16,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_" &
"MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_T" &
"HRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=2048,C_RD_FREQ=1,C_RD_PNTR_WIDTH=11,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTE" &
"RFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_W" &
"IDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_T" &
"YPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C" &
"_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=" &
"10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=" &
"1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_AS" &
"SERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 32,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 16,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "1kx36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1021,
C_PROG_FULL_THRESH_NEGATE_VAL => 1020,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 2048,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 11,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END vgagraph_fifo_arch;
| bsd-2-clause | ec8f19710332e199f51a955c1c4be22e | 0.627796 | 2.911912 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32i/alu.vhd | 2 | 1,735 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logic
);
end alu;
architecture arch_alu of alu is
signal r, shift: std_logic_vector(31 downto 0);
signal shift_op2: std_logic_vector(4 downto 0);
signal addsub: std_logic_vector(32 downto 0);
signal less, left, logical: std_logic;
begin
process(op1, op2, alu_op, addsub, less, shift_op2, shift)
begin
case alu_op is
when "0000" => r <= op1 and op2;
when "0001" => r <= op1 or op2;
when "0010" => r <= op1 xor op2;
when "0100" | "0101" => r <= addsub(31 downto 0);
when "0110" => r <= op2;
when "0111" | "1000" => r <= x"0000000" & "000" & less;
when others => r <= shift;
end case;
end process;
addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2);
less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31);
less_than <= less;
zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or
r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or
r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or
r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0));
shift_op2 <= op2(4 downto 0);
left <= '1' when alu_op(0) = '1' else '0';
logical <= '1' when alu_op(2) = '0' else '0';
barrel_shifter: entity work.bshift
port map( left => left,
logical => logical,
shift => shift_op2,
input => op1,
output => shift
);
result <= r;
end arch_alu;
| gpl-2.0 | 4d4dd51d0595a84c902d122b49fe5ecf | 0.594236 | 2.335128 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/serport_xontx_tb.vhd | 1 | 4,378 | -- $Id: serport_xontx_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx_tb - sim
-- Description: serial port: xon/xoff logic tx path (SIM only!)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-03 724 1.0 Initial version (copied from serport_xontx)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib_tb.all;
entity serport_xontx_tb is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx_tb;
architecture sim of serport_xontx_tb is
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
end sim;
| gpl-3.0 | cb91d4f3ba09ee2b9ae8e0e4703c8ddd | 0.463682 | 3.850484 | false | false | false | false |
wfjm/w11 | rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd | 1 | 24,390 | -- $Id: fx2_3fifoctl_ic.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fx2_3fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 controller (3 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-30 888 14.7 131013 xc6slx16-2 207 207 48 125 s 6.9/5.8
-- 2012-01-15 453 13.3 O76x xc3s1200e-4 157 265 96 243 s 7.7/7.4
-- 2012-01-15 453 13.3 O76x xc3s1200e-4 156 259 96 238 s 7.9/7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-04-30 888 1.2 BUGFIX: resolve rx fifo threshold deadlock
-- add fsm_* monitor lines
-- 2013-01-04 469 1.1 BUGFIX: redo rx logic, now properly pipelined
-- 2012-01-09 453 1.0 Initial version (derived from 2fifo_ic)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_3fifoctl_ic is -- EZ-USB FX2 controller(3 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit 1 data in
TXENA : in slbit; -- transmit 1 data enable
TXBUSY : out slbit; -- transmit 1 data busy
TXAFULL : out slbit; -- transmit 1 almost full flag
TX2DATA : in slv8; -- transmit 2 data in
TX2ENA : in slbit; -- transmit 2 data enable
TX2BUSY : out slbit; -- transmit 2 data busy
TX2AFULL : out slbit; -- transmit 2 almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_3fifoctl_ic;
architecture syn of fx2_3fifoctl_ic is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_tx2fifo: slv2 := c_fifo_ep8;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe wait
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp, -- s_txdisp: write, dispatch
s_tx2prep0, -- s_tx2prep0: switch to tx2-fifo
s_tx2prep1, -- s_tx2prep1: fifo addr setup
s_tx2prep2, -- s_tx2prep2: wait for flags
s_tx2disp -- s_tx2disp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend 1 time out counter
pe2tocnt : slv(PETOWIDTH-1 downto 0); -- pktend 2 time out counter
pepend : slbit; -- pktend 1 pending
pe2pend : slbit; -- pktend 2 pending
rxpipe1 : slbit; -- read pipe 1: iob capture stage
rxpipe2 : slbit; -- read pipe 2: fifo write stage
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep8_sel : slbit; -- ep8 (tx2) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
moni_ep8_pf : slbit; -- ep8 (tx2) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
petocnt_init, -- pe2tocnt
'0','0', -- pepend,pe2pend
'0','0', -- rxpipe1, rxpipe2
ccnt_init, -- ccnt
'0','0','0', -- moni_ep(4|6|8)_sel
'0','0','0' -- moni_ep(4|6|8)_pf
);
constant rxfifo_thres : natural := 3; -- required free space in rx fifo to
-- start rx pipeline
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal FX2_DATA_DO : slv8 := (others=>'0');
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TX2FIFO_DO : slv8 := (others=>'0');
signal TX2FIFO_VAL : slbit := '0';
signal TX2FIFO_HOLD : slbit := '0';
signal TX2SIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TX2SIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
signal TX2BUSY_L : slbit := '0';
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1 and
TX2AFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL|TX2AFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => FX2_DATA_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
TX2FIFO : fifo_2c_dram -- output 2 fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TX2DATA,
ENA => TX2ENA,
BUSY => TX2BUSY_L,
DO => TX2FIFO_DO,
VAL => TX2FIFO_VAL,
HOLD => TX2FIFO_HOLD,
SIZEW => TX2SIZE_USR,
SIZER => TX2SIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, FX2_FLAG_N, TXFIFO_VAL, TX2FIFO_VAL,
TXFIFO_DO, TX2FIFO_DO, RXSIZE_FX2, TXBUSY_L, TX2BUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable itx2fifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable idata_do : slv8 := (others=>'0');
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable sltx2ok : slbit := '0';
variable pipeok : slbit := '0';
variable rxfifook : slbit := '0';
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
itx2fifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
idata_do := TXFIFO_DO;
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
sltx2ok := FX2_FLAG_N(c_flag_tx2_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
rxfifook := '0';
if unsigned(RXSIZE_FX2)>rxfifo_thres then -- enough space in rx fifo ?
rxfifook := '1';
end if;
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
n.rxpipe1 := '0';
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and rxfifook='1' then -- rx data and space in fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
elsif sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')then
ififo_ce := '1';
ififo := c_tx2fifo;
n.state := s_tx2prep1;
end if;
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_txprep0; -- otherwise switch to tx flow
end if;
-- if chunk done and tx2 or pe2 pending and possible
elsif cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
then
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_tx2prep0;
end if;
-- if more rx to do and possible
elsif slrxok='1' and rxfifook='1' then
islrd := '1';
cc_cnt := '1';
n.rxpipe1 := '1';
if pipeok='1' then
n.state := s_rxdisp; -- 1 cycle read
--n.state := s_rxprep2; -- 2 cycle read
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_idle; -- to idle
end if;
end if;
when s_rxpipe => -- s_rxpipe: read, pipe wait
isloe := '1';
n.state := s_rxprep2;
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and tx2 or pe2 pending and possible
if cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
then
n.state := s_tx2prep0;
-- if chunk done and rx pending and possible
elsif cc_done='1' and slrxok='1' and rxfifook='1' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_do := TXFIFO_DO;
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when s_tx2prep0 => -- s_tx2prep0: switch to tx2-fifo
ififo_ce := '1';
ififo := c_tx2fifo;
n.state := s_tx2prep1;
when s_tx2prep1 => -- s_tx2prep1: fifo addr setup
cc_clr := '1';
n.state := s_tx2prep2;
when s_tx2prep2 => -- s_tx2prep2: wait for flags
n.state := s_tx2disp;
when s_tx2disp => -- s_tx2disp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and rxfifook='1' then
n.state := s_rxprep0;
-- if chunk done and tx or pe pending and possible
elsif cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')
then
n.state := s_txprep0;
-- if pktend 2 to do and possible
elsif sltx2ok = '1' and r.pe2pend = '1' then
ipktend := '1';
n.pe2pend := '0';
n.state := s_idle;
-- if more tx2 to do and possible
elsif sltx2ok = '1' and TX2FIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pe2pend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itx2fifo_hold := '0';
idata_do := TX2FIFO_DO;
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_tx2disp; -- stream
else
n.state := s_tx2prep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
-- rx pipe handling
idata_cei := r.rxpipe1;
n.rxpipe2 := r.rxpipe1;
irxfifo_ena := r.rxpipe2;
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every ifclk cycle
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
if TX2FIFO_VAL = '1' then
n.pe2tocnt := (others=>'1');
else
if unsigned(r.pe2tocnt) /= 0 then
n.pe2tocnt := slv(unsigned(r.pe2tocnt) - 1);
if unsigned(r.pe2tocnt) = 1 then
n.pe2pend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
n.moni_ep8_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_tx2disp then
n.moni_ep8_sel := '1';
n.moni_ep8_pf := not FX2_FLAG_N(c_flag_prog);
end if;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
FX2_DATA_DO <= idata_do;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
TX2FIFO_HOLD <= itx2fifo_hold;
end process proc_next;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.fifo_ep8 <= R_REGS.moni_ep8_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.flag_ep8_full <= not FX2_FLAG_N(c_flag_tx2_ff);
R_MONI_C.flag_ep8_almost <= R_REGS.moni_ep8_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
case R_REGS.state is
when s_idle => R_MONI_C.fsm_idle <= '1';
when s_rxprep0 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxprep1 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxprep2 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxdisp => R_MONI_C.fsm_disp <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxpipe => R_MONI_C.fsm_pipe <= '1'; R_MONI_C.fsm_rx <= '1';
when s_txprep0 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txprep1 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txprep2 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txdisp => R_MONI_C.fsm_disp <= '1'; R_MONI_C.fsm_tx <= '1';
when s_tx2prep0 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx2 <= '1';
when s_tx2prep1 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx2 <= '1';
when s_tx2prep2 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx2 <= '1';
when s_tx2disp => R_MONI_C.fsm_disp <= '1'; R_MONI_C.fsm_tx2 <= '1';
when others => null;
end case;
R_MONI_S <= R_MONI_C;
end if;
end if;
end process proc_moni;
proc_almost: process (RXSIZE_USR, TXSIZE_USR, TX2SIZE_USR)
begin
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
if unsigned(TX2SIZE_USR) <= TX2AFULL_THRES then
TX2AFULL <= '1';
else
TX2AFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
TX2BUSY <= TX2BUSY_L;
MONI <= R_MONI_S;
end syn;
| gpl-3.0 | eb74e0d25cff4bb6f3cc5df967550f8d | 0.492169 | 3.251566 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/gray2bin_gen.vhd | 1 | 1,384 | -- $Id: gray2bin_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gray2bin_gen - syn
-- Description: Gray code to binary converter
--
-- Dependencies: -
-- Test bench: tb/tb_gray_cnt_n
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end entity gray2bin_gen;
architecture syn of gray2bin_gen is
begin
proc_comb: process (DI)
variable ido : slv(DWIDTH-1 downto 0);
begin
ido := (others=>'0');
ido(DWIDTH-1) := DI(DWIDTH-1);
for i in DWIDTH-2 downto 0 loop
ido(i) := ido(i+1) xor DI(i);
end loop;
DO <= ido;
end process proc_comb;
end syn;
| gpl-3.0 | 370986af61316dd3cfc1f1745bef94f7 | 0.544798 | 3.434243 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/tb/tb_sramif2migui_core.vhd | 1 | 17,065 | -- $Id: tb_sramif2migui_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_sramif2migui_core - sim
-- Description: Test bench for sramif2migui_core and migui_core_gsim
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- migui_core_gsim
-- sramif2migui_core
-- migui_core_gsim
-- migui2bram
--
-- To test: sramif2migui_core
--
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-25 1093 1.0 Initial version
-- 2018-11-10 1067 0.1 First draft (derived fr tb_nx_cram_memctl.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.miglib.all;
use work.sys_conf.all;
entity tb_sramif2migui_core is
end tb_sramif2migui_core;
architecture sim of tb_sramif2migui_core is
constant clkmui_mul : positive := 6;
constant clkmui_div : positive := 12;
constant c_caco_wait : positive := 50; -- UI_CLK cycles till CALIB_COMP = 1
constant mwidth : positive := 2**sys_conf_bawidth; -- mask width (8 or 16)
constant dwidth : positive := 8*mwidth; -- data width (64 or 128)
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv20 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal SYS_CLK : slbit := '0';
signal SYS_RST : slbit := '0';
signal UI_CLK : slbit := '0';
signal UI_CLK_SYNC_RST : slbit := '0';
signal INIT_CALIB_COMPLETE : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_EN : slbit := '0';
signal APP_CMD : slv3:= (others=>'0');
signal APP_ADDR : slv(sys_conf_mawidth-1 downto 0):= (others=>'0');
signal APP_WDF_RDY : slbit := '0';
signal APP_WDF_WREN : slbit := '0';
signal APP_WDF_DATA : slv(dwidth-1 downto 0):= (others=>'0');
signal APP_WDF_MASK : slv(mwidth-1 downto 0):= (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RD_DATA : slv(dwidth-1 downto 0):= (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv20 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv20 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv20 := (others=>'0');
signal R_NRDRHIT : integer := 0;
signal R_NWRRHIT : integer := 0;
signal R_NWRFLUSH : integer := 0;
signal R_NMIGCBUSY : integer := 0;
signal R_NMIGWBUSY : integer := 0;
signal R_NMIGCACOW : integer := 0;
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal UI_CLK_CYCLE : integer := 0;
constant clock_period : Delay_length := 12.5 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 3 ns;
constant c2out_time : Delay_length := 5 ns;
constant sysclock_period : Delay_length := 5.833 ns;
constant sysclock_offset : Delay_length := 200 ns;
begin
USRCLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
SYSCLKGEN : simclk
generic map (
PERIOD => sysclock_period,
OFFSET => sysclock_offset)
port map (
CLK => SYS_CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UICLKCNT : simclkcnt port map (CLK => UI_CLK, CLK_CYCLE => UI_CLK_CYCLE);
SR2MU : sramif2migui_core
generic map (
BAWIDTH => sys_conf_bawidth,
MAWIDTH => sys_conf_mawidth)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
MONI => MONI,
UI_CLK => UI_CLK,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END
);
BTYP_MSIM : if sys_conf_btyp = c_btyp_msim generate
I0 : migui_core_gsim
generic map (
BAWIDTH => sys_conf_bawidth,
MAWIDTH => sys_conf_mawidth,
SAWIDTH => sys_conf_sawidth,
CLKMUI_MUL => clkmui_mul,
CLKMUI_DIV => clkmui_div)
port map (
SYS_CLK => SYS_CLK,
SYS_RST => SYS_RST,
UI_CLK => UI_CLK,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_REF_REQ => '0',
APP_ZQ_REQ => '0',
APP_REF_ACK => open,
APP_ZQ_ACK => open
);
end generate BTYP_MSIM;
BTYP_BRAM : if sys_conf_btyp = c_btyp_bram generate
I0 : migui2bram
generic map (
BAWIDTH => sys_conf_bawidth,
MAWIDTH => sys_conf_mawidth,
RAWIDTH => sys_conf_rawidth,
RDELAY => sys_conf_rdelay,
CLKMUI_MUL => clkmui_mul,
CLKMUI_DIV => clkmui_div,
CLKMSYS_PERIOD => 6.000)
port map (
SYS_CLK => SYS_CLK,
SYS_RST => SYS_RST,
UI_CLK => UI_CLK,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END
);
end generate BTYP_BRAM;
proc_stim: process
file fstim : text open read_mode is "tb_sramif2migui_core_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv20 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
variable nwreq : natural := 0;
variable nrdrhit : integer := 0;
variable nwrrhit : integer := 0;
variable nwrflush : integer := 0;
variable nmigcbusy : integer := 0;
variable nmigwbusy : integer := 0;
variable nmigcacow : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wreq " => -- .wreq
read_ea(iline, nwreq);
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nb="));
write(oline, nbusy, right, 2);
write(oline, string'(" mo="));
write(oline, R_NRDRHIT-nrdrhit, right, 2);
write(oline, R_NWRRHIT-nwrrhit, right, 2);
write(oline, R_NWRFLUSH-nwrflush, right, 2);
write(oline, R_NMIGCBUSY-nmigcbusy, right, 2);
write(oline, R_NMIGWBUSY-nmigwbusy, right, 2);
write(oline, string'(" "));
write(oline, R_NMIGCACOW-nmigcacow, right, 1);
writeline(output, oline);
nrdrhit := R_NRDRHIT;
nwrrhit := R_NWRRHIT;
nwrflush := R_NWRFLUSH;
nmigcbusy := R_NMIGCBUSY;
nmigwbusy := R_NMIGWBUSY;
nmigcacow := R_NMIGCACOW;
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
wait for clock_period;
REQ <= '0';
if nwreq > 0 then wait for nwreq*clock_period; end if;
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 6, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nb="));
write(oline, nbusy, right, 2);
write(oline, string'(" mo="));
write(oline, R_NRDRHIT-nrdrhit, right, 2);
write(oline, R_NWRRHIT-nwrrhit, right, 2);
write(oline, R_NWRFLUSH-nwrflush, right, 2);
write(oline, R_NMIGCBUSY-nmigcbusy, right, 2);
write(oline, R_NMIGWBUSY-nmigwbusy, right, 2);
write(oline, string'(" "));
write(oline, R_NMIGCACOW-nmigcacow, right, 1);
writeline(output, oline);
nrdrhit := R_NRDRHIT;
nwrrhit := R_NWRRHIT;
nwrflush := R_NWRFLUSH;
nmigcbusy := R_NMIGCBUSY;
nmigwbusy := R_NMIGWBUSY;
nmigcacow := R_NMIGCACOW;
wait for clock_period;
REQ <= '0';
if nwreq > 0 then wait for nwreq*clock_period; end if;
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": stat moni-cnt= ");
write(oline, R_NRDRHIT, right, 5);
write(oline, string'(","));
write(oline, R_NWRRHIT, right, 5);
write(oline, string'(","));
write(oline, R_NWRFLUSH, right, 5);
write(oline, string'(","));
write(oline, R_NMIGCBUSY, right, 5);
write(oline, string'(","));
write(oline, R_NMIGWBUSY, right, 5);
write(oline, string'(","));
write(oline, R_NMIGCACOW, right, 5);
writeline(output, oline);
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
-- performance counter
if MONI.rdrhit = '1' then
R_NRDRHIT <= R_NRDRHIT + 1;
end if;
if MONI.wrrhit = '1' then
R_NWRRHIT <= R_NWRRHIT + 1;
end if;
if MONI.wrflush = '1' then
R_NWRFLUSH <= R_NWRFLUSH + 1;
end if;
if MONI.migcbusy = '1' then
R_NMIGCBUSY <= R_NMIGCBUSY + 1;
end if;
if MONI.migwbusy = '1' then
R_NMIGWBUSY <= R_NMIGWBUSY + 1;
end if;
if MONI.migcacow = '1' then
R_NMIGCACOW <= R_NMIGCACOW + 1;
end if;
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(UI_CLK);
if R_MEMON = '1' then
if APP_EN = '1' then
writetimestamp(oline, UI_CLK_CYCLE, ": mreq ");
write(oline, APP_CMD, right, 3);
write(oline, string'(","));
write(oline, APP_RDY, right);
write(oline, string'(","));
write(oline, APP_WDF_RDY, right);
writegen(oline,
APP_ADDR(sys_conf_sawidth-sys_conf_bawidth-1 downto 0),
right, 7, 16);
write(oline, APP_WDF_WREN, right, 2);
write(oline, APP_WDF_END, right, 2);
if APP_WDF_WREN = '1' then
writegen(oline, APP_WDF_MASK, right, (mwidth/4)+1, 16);
writegen(oline, APP_WDF_DATA, right, (dwidth/4)+1, 16);
end if;
writeline(output, oline);
end if;
if APP_RD_DATA_VALID = '1' then
writetimestamp(oline, UI_CLK_CYCLE, ": mres ");
write(oline, APP_RD_DATA_END, right);
writegen(oline, APP_RD_DATA, right, (dwidth/4)+1, 16);
writeline(output, oline);
end if;
end if;
end loop;
end process proc_memon;
end sim;
| gpl-3.0 | ece2ad465042520a81ccd94a450a9374 | 0.499561 | 3.573074 | false | false | false | false |
jasonpeng/cg3207-proj | ALU/Divider_Test.vhd | 1 | 2,881 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05:29:39 11/13/2013
-- Design Name:
-- Module Name: C:/Users/Jason/Documents/GitHub/cg3207-proj/ALU/Divider_Test.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: divider
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Divider_Test IS
END Divider_Test;
ARCHITECTURE behavior OF Divider_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT divider
PORT(
enable : IN std_logic;
Control_a : IN std_logic_vector(2 downto 0);
dividend_i : IN std_logic_vector(31 downto 0);
divisor_i : IN std_logic_vector(31 downto 0);
quotient_o : OUT std_logic_vector(31 downto 0);
remainder_o : OUT std_logic_vector(31 downto 0);
done_b : OUT std_logic;
debug_b : OUT std_logic_vector(27 downto 0)
);
END COMPONENT;
--Inputs
signal enable : std_logic := '0';
signal Control_a : std_logic_vector(2 downto 0) := (others => '0');
signal dividend_i : std_logic_vector(31 downto 0) := (others => '0');
signal divisor_i : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal quotient_o : std_logic_vector(31 downto 0);
signal remainder_o : std_logic_vector(31 downto 0);
signal done_b : std_logic;
signal debug_b : std_logic_vector(27 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: divider PORT MAP (
enable => enable,
Control_a => Control_a,
dividend_i => dividend_i,
divisor_i => divisor_i,
quotient_o => quotient_o,
remainder_o => remainder_o,
done_b => done_b,
debug_b => debug_b
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
enable <= '1';
Control_a <= "010";
dividend_i <= X"00000007";
divisor_i <= X"00000004";
wait for 100 ns;
dividend_i <= X"00000009";
-- insert stimulus here
wait;
end process;
END;
| gpl-2.0 | b7eec3ad71976de5aa06ad9297f94b35 | 0.59285 | 3.795784 | false | true | false | false |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_BitBangingIO_Device.vhdl | 1 | 6,106 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: BitBanging I/O Device for PicoBlaze
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_BitBangingIO_Device is
generic (
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
BITS : POSITIVE := 8;
INITIAL_VALUE : STD_LOGIC_VECTOR
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
-- BBIO interface
BBIO_Out : OUT STD_LOGIC_VECTOR(BITS - 1 downto 0);
BBIO_In : IN STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of pb_BitBangingIO_Device is
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
constant REQUIRED_REG_BYTES : POSITIVE := div_ceil(BITS, 8);
constant BIT_SET_CLR : NATURAL := log2ceil(REQUIRED_REG_BYTES);
constant BIT_OUT_IN : NATURAL := log2ceil(REQUIRED_REG_BYTES);
constant REG_WO_SET_BIT_VALUE : STD_LOGIC := '0';
constant REG_WO_CLEAR_BIT_VALUE : STD_LOGIC := '1';
constant REG_RO_OUTPUT_BIT_VALUE : STD_LOGIC := '0';
constant REG_RO_INPUT_BIT_VALUE : STD_LOGIC := '1';
constant INITIAL_VALUE_I : STD_LOGIC_VECTOR((REQUIRED_REG_BYTES * 8) - 1 downto 0) := resize(INITIAL_VALUE, REQUIRED_REG_BYTES * 8);
signal Reg_DataOut : T_SLVV_8(REQUIRED_REG_BYTES - 1 downto 0) := to_slvv_8(INITIAL_VALUE_I);
signal Reg_DataIn : T_SLVV_8(REQUIRED_REG_BYTES - 1 downto 0) := to_slvv_8(INITIAL_VALUE_I);
begin
assert (BITS <= 16)
report "BitBangingIO size is not supported. Supported sizes up to 16 bits. BITS=" & INTEGER'image(BITS)
severity failure;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
variable index : NATURAL;
begin
if rising_edge(Clock) then
index := to_index(AdrDec_WriteAddress(BIT_SET_CLR - 1 downto 0));
if (Reset = '1') then
Reg_DataOut <= to_slvv_8(INITIAL_VALUE_I);
else
if (AdrDec_we = '1') then
case AdrDec_WriteAddress(BIT_SET_CLR) is
when REG_WO_SET_BIT_VALUE => Reg_DataOut(index) <= Reg_DataOut(index) or AdrDec_Data;
when REG_WO_CLEAR_BIT_VALUE => Reg_DataOut(index) <= Reg_DataOut(index) and not AdrDec_Data;
when others => null;
end case;
end if;
Reg_DataIn <= to_slvv_8(resize(BBIO_In, (Reg_DataIn'length * 8)));
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_DataOut, Reg_DataIn)
variable index : NATURAL;
begin
index := to_index(AdrDec_ReadAddress(BIT_OUT_IN - 1 downto 0));
case AdrDec_ReadAddress(BIT_OUT_IN) is
when REG_RO_OUTPUT_BIT_VALUE => DataOut <= Reg_DataOut(index);
when REG_RO_INPUT_BIT_VALUE => DataOut <= Reg_DataIn(index);
when others => DataOut <= (others => 'X');
end case;
end process;
Interrupt <= '0';
Message <= x"00";
BBIO_Out <= resize(to_slv(Reg_DataOut), BBIO_Out'length);
end;
| apache-2.0 | e73db1a6ff303d936baa03b0b7307dfd | 0.545365 | 3.268737 | false | false | false | false |
wfjm/w11 | rtl/bplib/s3board/tb/s3board_fusp_dummy.vhd | 1 | 2,807 | -- $Id: s3board_fusp_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s3board_fusp_dummy - syn
-- Description: s3board minimal target (base+fusp; serport loopback)
--
-- Dependencies: -
-- To test: tb_s3board_fusp
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.0.3 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.2 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.0.1 rename s3board_usp_dummy->s3board_fusp_dummy
-- 2010-05-01 286 1.0 Initial version (derived from s3board_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.s3boardlib.all;
entity s3board_fusp_dummy is -- S3BOARD dummy (base+fusp; loopback)
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end s3board_fusp_dummy;
architecture syn of s3board_fusp_dummy is
begin
O_TXD <= I_RXD;
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
| gpl-3.0 | b35be53e799f71990701f05c1ce32483 | 0.509441 | 3.1646 | false | false | false | false |
jasonpeng/cg3207-proj | ALU/Divider.vhd | 1 | 3,498 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:11:02 10/11/2013
-- Design Name:
-- Module Name: Divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity divider is
port (
Control_a: in std_logic_vector(2 downto 0);
dividend_i : in std_logic_vector(31 downto 0);
divisor_i : in std_logic_vector(31 downto 0);
quotient_o : out std_logic_vector(31 downto 0);
remainder_o : out std_logic_vector(31 downto 0);
done_b : out std_logic;
debug_b : out std_logic_vector(27 downto 0) );
end divider;
architecture rtl of divider is
signal counter: integer range 0 to 33;
signal start : std_logic;
begin
process(Control_a, dividend_i, divisor_i, counter)
variable divident:std_logic_vector(31 downto 0);
variable divisor: std_logic_vector(31 downto 0);
variable tmp_rem: std_logic_vector(31 downto 0);
variable tmp_quo: std_logic_vector (31 downto 0);
variable rem_sign: std_logic;
variable quo_sign: std_logic;
variable divisor_check:std_logic;
constant MAX_COUNT : integer := 33;
constant TRI_STATE : std_logic_vector(31 downto 0) := (others => 'Z');
begin
if(start = '0') then
start <= '1';
counter <= MAX_COUNT;
done_b <= '0';
debug_b <= (others => '0');
quotient_o <= TRI_STATE;
remainder_o <= TRI_STATE;
elsif(counter = MAX_COUNT) then --initialize
tmp_rem := X"00000000";
tmp_quo := X"00000000";
rem_sign := '0';
quo_sign := '0';
divident := dividend_i;
divisor := divisor_i;
if (divisor=X"00000000") then
divisor_check := '0';
else
divisor_check := '1';
end if;
if(control_a = "010") then
rem_sign := divident(31);
quo_sign := divident(31) xor divisor(31);
if(divident(31) = '1') then
divident := std_logic_vector(unsigned(not divident) + 1);
end if;
if(divisor(31) = '1') then
divisor := std_logic_vector(unsigned(not divisor) + 1);
end if;
end if;
start <= '1';
counter <= counter - 1;
done_b <= '0';
debug_b <= (others => '0');
quotient_o <= TRI_STATE;
remainder_o <= TRI_STATE;
elsif (counter = 0) then
if(divisor_check='1') then
if(rem_sign = '1') then
remainder_o <= std_logic_vector(unsigned(not tmp_rem) + 1);
else
remainder_o <= tmp_rem;
end if;
if(quo_sign = '1') then
quotient_o <= std_logic_vector(unsigned(not tmp_quo) + 1);
else
quotient_o <= tmp_quo;
end if;
debug_b <= X"0000000";
else
quotient_o <= X"00000000";
remainder_o<= X"00000000";
debug_b <= X"FFFFFFF";
end if;
start <= '0';
done_b<= '1';
counter <= 0;
else
tmp_rem(31 downto 1):= tmp_rem(30 downto 0);
tmp_rem(0) := divident(31);
tmp_quo(31 downto 1):= tmp_quo(30 downto 0);
if(tmp_rem >= divisor) then
tmp_rem := std_logic_vector(unsigned(tmp_rem) - unsigned(divisor));
tmp_quo(0):= '1';
debug_b <= X"0000010";
else
tmp_quo(0):='0';
debug_b <= X"0000000";
end if;
divident(31 downto 1) := divident(30 downto 0);
start <= '1';
counter <= counter - 1;
done_b <= '0';
quotient_o <= TRI_STATE;
remainder_o <= TRI_STATE;
end if;
end process;
end rtl;
| gpl-2.0 | e9d9039fd75e0dabbb15355b07825a97 | 0.582047 | 2.939496 | false | false | false | false |
sjohann81/hf-risc | riscv/sim/hf-riscv_basic_standard_soc_tb.vhd | 1 | 7,805 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 15;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(15 downto 0);
signal gpiob_in, gpiob_out, gpiob_ddr: std_logic_vector(15 downto 0);
signal gpio_sig, gpio_sig2, gpio_sig3: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
wait for 3 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
end process;
process
begin
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
end process;
gpioa_in <= x"00" & "0000" & gpio_sig & "000";
gpiob_in <= "10000" & gpio_sig3 & "00" & "00000" & gpio_sig2 & "00";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(30 downto 24));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | fbb90e8bac9c9ea367af36f97bed39ec | 0.594234 | 2.705373 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32im_nodiv/control.vhd | 1 | 15,378 | -- control signals for HF-RISCV
--
-- alu_op: alu_src1: mem_write: jump:
-- 0000 -> and 0 -> r[rs1] 00 -> no mem write 00 -> no jump
-- 0001 -> or 1 -> pc_last2 01 -> sb 01 -> don't care
-- 0010 -> xor 10 -> sh 10 -> jal
-- 0011 -> don't care alu_src2: 11 -> sw 11 -> jalr
-- 0100 -> add 000 -> imm_u
-- 0101 -> sub 001 -> imm_i mem_read: branch:
-- 0110 -> lui, jal, jalr 010 -> imm_s 00 -> no mem read 000 -> no branch
-- 0111 -> slt 011 -> pc 01 -> lb 001 -> beq
-- 1000 -> sltu 100 -> rs2 10 -> lh 010 -> bne
-- 1001 -> sll 101 -> r[rs2] 11 -> lw 011 -> blt
-- 1010 -> srl 110 -> don't care 100 -> bge
-- 1011 -> sra 111 -> don't care 101 -> bltu
-- 1100 -> mul 110 -> bgeu
-- 1101 -> mulh reg_write: sig_read: 111 -> system
-- 1110 -> mulhsu 0 -> no write 0 -> unsigned
-- 1111 -> mulhu 1 -> write register 1 -> signed
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port ( opcode: in std_logic_vector(6 downto 0);
funct3: in std_logic_vector(2 downto 0);
funct7: in std_logic_vector(6 downto 0);
reg_write: out std_logic;
alu_src1: out std_logic;
alu_src2: out std_logic_vector(2 downto 0);
alu_op: out std_logic_vector(3 downto 0);
jump: out std_logic_vector(1 downto 0);
branch: out std_logic_vector(2 downto 0);
mem_write: out std_logic_vector(1 downto 0);
mem_read: out std_logic_vector(1 downto 0);
sig_read: out std_logic
);
end control;
architecture arch_control of control is
begin
process(opcode, funct3, funct7)
begin
case opcode is -- load immediate / jumps
when "0110111" => -- LUI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0110";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0010111" => -- AUIPC
reg_write <= '1';
alu_src1 <= '1';
alu_src2 <= "000";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1101111" => -- JAL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "011";
alu_op <= "0110";
jump <= "10";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1100111" => -- JALR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "011";
alu_op <= "0110";
jump <= "11";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1100011" => -- branches
case funct3 is
when "000" => -- BEQ
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "001";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "001" => -- BNE
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "010";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "100" => -- BLT
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "011";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" => -- BGE
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "100";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "110" => -- BLTU
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "101";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- BGEU
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "110";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0000011" => -- loads
case funct3 is
when "000" => -- LB
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "01";
sig_read <= '1';
when "001" => -- LH
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "10";
sig_read <= '1';
when "010" => -- LW
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "11";
sig_read <= '1';
when "100" => -- LBU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "01";
sig_read <= '0';
when "101" => -- LHU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "10";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0100011" => -- stores
case funct3 is
when "000" => -- SB
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "01";
mem_read <= "00";
sig_read <= '0';
when "001" => -- SH
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "10";
mem_read <= "00";
sig_read <= '0';
when "010" => -- SW
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "11";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0010011" => -- imm computation
case funct3 is
when "000" => -- ADDI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "010" => -- SLTI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0111";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "011" => -- SLTIU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "1000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "100" => -- XORI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "110" => -- ORI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- ANDI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "001" => -- SLLI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" =>
case funct7 is
when "0000000" => -- SRLI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SRAI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1011";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0110011" => -- computation
case funct3 is
when "000" =>
case funct7 is
when "0000000" => -- ADD
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SUB
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0000001" => -- MUL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "001" =>
case funct7 is
when "0000001" => -- MULH
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1101";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others => -- SLL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "010" =>
case funct7 is
when "0000001" => -- MULHSU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1110";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others => -- SLT
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "011" =>
case funct7 is
when "0000001" => -- MULHU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1111";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others => -- SLTU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "100" => -- XOR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" =>
case funct7 is
when "0000000" => -- SRL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SRA
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1011";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "110" => -- OR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- AND
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "1110011" => -- SYSTEM
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "111";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
end process;
end arch_control;
| gpl-2.0 | 2c64ac2b653f8ec83e4784b1fe1edb5a | 0.385811 | 2.837793 | false | false | false | false |
sjohann81/hf-risc | mips/sim/hf-risc_tb_xtea.vhd | 1 | 10,290 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
signal ext_periph, ext_periph_dly, ready: std_logic;
signal key: std_logic_vector(127 downto 0);
signal input, output: std_logic_vector(63 downto 0);
signal data_read_xtea, data_read_xtea_s: std_logic_vector(31 downto 0);
signal control: std_logic_vector(1 downto 0);
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
wait for 100 us;
gpio_sig <= not gpio_sig;
end process;
gpioa_in <= "0000" & gpio_sig & "000";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
stall_sig <= '0'; --stall;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
data_read <= data_read_xtea when ext_periph = '1' or ext_periph_dly = '1' else data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
data_read_xtea <= data_read_xtea_s;
ext_periph <= '1' when address(31 downto 24) = x"fa" else '0';
process(clock_in, reset)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
ext_periph_dly <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
ext_periph_dly <= ext_periph;
end if;
end process;
process (clock_in, reset, address, key, input, output)
begin
if reset = '1' then
data_read_xtea_s <= (others => '0');
elsif clock_in'event and clock_in = '1' then
if (ext_periph = '1') then -- XTEA is at 0xfa000000
case address(7 downto 4) is
when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
data_read_xtea_s <= x"000000" & "00000" & ready & control;
when "0001" => -- key[0] 0xfa000010
data_read_xtea_s <= key(127 downto 96);
when "0010" => -- key[1] 0xfa000020
data_read_xtea_s <= key(95 downto 64);
when "0011" => -- key[2] 0xfa000030
data_read_xtea_s <= key(63 downto 32);
when "0100" => -- key[3] 0xfa000040
data_read_xtea_s <= key(31 downto 0);
when "0101" => -- input[0] 0xfa000050
data_read_xtea_s <= input(63 downto 32);
when "0110" => -- input[1] 0xfa000060
data_read_xtea_s <= input(31 downto 0);
when "0111" => -- output[0] 0xfa000070
data_read_xtea_s <= output(63 downto 32);
when "1000" => -- output[1] 0xfa000080
data_read_xtea_s <= output(31 downto 0);
when others =>
data_read_xtea_s <= (others => '0');
end case;
end if;
end if;
end process;
process (clock_in, reset, address, control, key, input, output)
begin
if reset = '1' then
key <= (others => '0');
input <= (others => '0');
control <= "00";
elsif clock_in'event and clock_in = '1' then
if (ext_periph = '1' and data_we /= "0000") then -- XTEA is at 0xfa000000
case address(7 downto 4) is
when "0000" => -- control 0xfa000000 (bit2 - ready (R), bit1 - encrypt (RW), bit0 - start (RW)
control <= data_write_periph(1 downto 0);
when "0001" => -- key[0] 0xfa000010
key(127 downto 96) <= data_write_periph;
when "0010" => -- key[1] 0xfa000020
key(95 downto 64) <= data_write_periph;
when "0011" => -- key[2] 0xfa000030
key(63 downto 32) <= data_write_periph;
when "0100" => -- key[3] 0xfa000040
key(31 downto 0) <= data_write_periph;
when "0101" => -- input[0] 0xfa000050
input(63 downto 32) <= data_write_periph;
when "0110" => -- input[1] 0xfa000060
input(31 downto 0) <= data_write_periph;
when others =>
end case;
end if;
end if;
end process;
-- XTEA core
crypto_core: entity work.xtea
port map( clock => clock_in,
reset => reset,
start => control(0),
encrypt => control(1),
key => key,
input => input,
output => output,
ready => ready
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"50000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | 340351ccd749792cf021e6b3c3b1ee3d | 0.586783 | 2.746197 | false | false | false | false |
wfjm/w11 | rtl/bplib/artys7/tb/artys7_dram_dummy.vhd | 1 | 3,215 | -- $Id: artys7_dram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: artys7_dram_dummy - syn
-- Description: artys7target (base; serport loopback, dram project)
--
-- Dependencies: -
-- To test: tb_artys7_dram
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-12 1105 1.0 Initial version (cloned from artys7)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity artys7_dram_dummy is -- ARTY S7 dummy (base+dram)
-- implements artys7_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- artys7 switches
I_BTN : in slv4; -- artys7 buttons
O_LED : out slv4; -- artys7 leds
O_RGBLED0 : out slv3; -- artys7 rgb-led 0
O_RGBLED1 : out slv3; -- artys7 rgb-led 1
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end artys7_dram_dummy;
architecture syn of artys7_dram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0
O_RGBLED1 <= (others=>'0');
DDR3_DQ <= (others=>'Z');
DDR3_DQS_P <= (others=>'Z');
DDR3_DQS_N <= (others=>'Z');
DDR3_ADDR <= (others=>'0');
DDR3_BA <= (others=>'0');
DDR3_RAS_N <= '1';
DDR3_CAS_N <= '1';
DDR3_WE_N <= '1';
DDR3_RESET_N <= '1';
DDR3_CK_P <= (others=>'0');
DDR3_CK_N <= (others=>'1');
DDR3_CKE <= (others=>'0');
DDR3_CS_N <= (others=>'1');
DDR3_DM <= (others=>'0');
DDR3_ODT <= (others=>'0');
end syn;
| gpl-3.0 | 6b8b49f1ce63c8e335a49a50085173d8 | 0.479316 | 3.267276 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32im_nodiv/datapath.vhd | 1 | 12,476 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity datapath is
port ( clock: in std_logic;
reset: in std_logic;
stall: in std_logic;
irq_vector: in std_logic_vector(31 downto 0);
irq: in std_logic;
irq_ack: out std_logic;
exception: out std_logic;
address: out std_logic_vector(31 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
data_w: out std_logic_vector(3 downto 0);
data_b: out std_logic;
data_h: out std_logic;
data_access: out std_logic
);
end datapath;
architecture arch_datapath of datapath is
-- datapath signals
signal inst_in_s, data_in_s, pc, pc_last, pc_last2, pc_plus4, pc_next, result, branch, ext32b, ext32h, alu_src1, alu_src2: std_logic_vector(31 downto 0);
signal ext32: std_logic_vector(31 downto 12);
signal opcode, funct7: std_logic_vector(6 downto 0);
signal funct3: std_logic_vector(2 downto 0);
signal read_reg1, read_reg2, write_reg, rs1, rs2, rd: std_logic_vector(4 downto 0);
signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);
signal imm_u: std_logic_vector(31 downto 12);
signal wreg, zero, less_than, branch_taken, jump_taken, mwait, alu_wait, stall_sig, stall_reg, alu_wait2, alu_wait3: std_logic;
signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
-- control signals
signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;
signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);
signal alu_src2_ctl, branch_ctl: std_logic_vector(2 downto 0);
signal alu_op_ctl: std_logic_vector(3 downto 0);
signal rs1_r, rs2_r, rd_r: std_logic_vector(4 downto 0);
signal imm_i_r, imm_s_r, imm_sb_r, imm_uj_r: std_logic_vector(31 downto 0);
signal imm_u_r: std_logic_vector(31 downto 12);
signal reg_write_ctl_r, alu_src1_ctl_r, sig_read_ctl_r, reg_to_mem_r, mem_to_reg_r, mem_to_reg_r_dly: std_logic;
signal jump_ctl_r, mem_write_ctl_r, mem_read_ctl_r: std_logic_vector(1 downto 0);
signal alu_src2_ctl_r, branch_ctl_r: std_logic_vector(2 downto 0);
signal alu_op_ctl_r: std_logic_vector(3 downto 0);
begin
--
-- FETCH STAGE
--
-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
-- program counter logic
process(clock, reset, reg_to_mem_r, mem_to_reg_r, mwait, stall_sig, stall_reg)
begin
if reset = '1' then
pc <= (others => '0');
pc_last <= (others => '0');
pc_last2 <= (others => '0');
elsif clock'event and clock = '1' then
if stall_sig = '0' then
if mwait = '0' then
if stall_reg = '0' then
pc <= pc_next;
else
pc <= pc_last;
end if;
pc_last <= pc;
pc_last2 <= pc_last;
else
if (reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1') and bds = '0' then
pc <= pc_last;
end if;
end if;
end if;
end if;
end process;
pc_plus4 <= pc + 4;
pc_next <= irq_vector when (irq = '1' and irq_ack_s = '1') or except = '1' else
branch when branch_taken = '1' or jump_taken = '1' else
pc_plus4;
-- interrupt acknowledge logic
irq_ack_s <= '1' when irq = '1' and
bds = '0' and branch_taken = '0' and jump_taken = '0' and
reg_to_mem_r = '0' and mem_to_reg_r = '0' else '0';
irq_ack <= irq_ack_s_dly;
exception <= '1' when except = '1' else '0';
stall_sig <= stall or alu_wait;
process(clock, reset, irq, irq_ack_s, mem_to_reg_r, mwait, stall_sig)
begin
if reset = '1' then
irq_ack_s_dly <= '0';
bds <= '0';
mem_to_reg_r_dly <= '0';
data_access_s_dly <= '0';
stall_reg <= '0';
alu_wait2 <= '0';
alu_wait3 <= '0';
elsif clock'event and clock = '1' then
stall_reg <= stall_sig;
alu_wait2 <= alu_wait;
alu_wait3 <= alu_wait2;
if stall_sig = '0' then
mem_to_reg_r_dly <= mem_to_reg_r;
data_access_s_dly <= data_access_s;
if mwait = '0' then
irq_ack_s_dly <= irq_ack_s;
if branch_taken = '1' or jump_taken = '1' then
bds <= '1';
else
bds <= '0';
end if;
end if;
end if;
end if;
end process;
--
-- DECODE STAGE
--
-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and branches
-- pipeline bubble insertion on loads/stores, exceptions, branches and interrupts
inst_in_s <= x"00000000" when reg_to_mem_r = '1' or mem_to_reg_r = '1' or except = '1' or stall_reg = '1' or alu_wait3 = '1' or
branch_taken = '1' or jump_taken = '1' or bds = '1' or irq_ack_s = '1' else
data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);
-- instruction decode
opcode <= inst_in_s(6 downto 0);
funct3 <= inst_in_s(14 downto 12);
funct7 <= inst_in_s(31 downto 25);
rd <= inst_in_s(11 downto 7);
rs1 <= inst_in_s(19 downto 15);
rs2 <= inst_in_s(24 downto 20);
imm_i <= ext32(31 downto 12) & inst_in_s(31 downto 20);
imm_s <= ext32(31 downto 12) & inst_in_s(31 downto 25) & inst_in_s(11 downto 7);
imm_sb <= ext32(31 downto 13) & inst_in_s(31) & inst_in_s(7) & inst_in_s(30 downto 25) & inst_in_s(11 downto 8) & '0';
imm_u <= inst_in_s(31 downto 12);
imm_uj <= ext32(31 downto 21) & inst_in_s(31) & inst_in_s(19 downto 12) & inst_in_s(20) & inst_in_s(30 downto 21) & '0';
ext32 <= (others => '1') when inst_in_s(31) = '1' else (others => '0');
-- control unit
control_unit: entity work.control
port map( opcode => opcode,
funct3 => funct3,
funct7 => funct7,
reg_write => reg_write_ctl,
alu_src1 => alu_src1_ctl,
alu_src2 => alu_src2_ctl,
alu_op => alu_op_ctl,
jump => jump_ctl,
branch => branch_ctl,
mem_write => mem_write_ctl,
mem_read => mem_read_ctl,
sig_read => sig_read_ctl
);
reg_to_mem <= '1' when mem_write_ctl /= "00" else '0';
mem_to_reg <= '1' when mem_read_ctl /= "00" else '0';
process(clock, reset, irq_ack_s, bds, mwait, stall_sig, alu_wait)
begin
if reset = '1' then
rd_r <= (others => '0');
rs1_r <= (others => '0');
rs2_r <= (others => '0');
imm_i_r <= (others => '0');
imm_s_r <= (others => '0');
imm_sb_r <= (others => '0');
imm_u_r <= (others => '0');
imm_uj_r <= (others => '0');
reg_write_ctl_r <= '0';
alu_src1_ctl_r <= '0';
alu_src2_ctl_r <= (others => '0');
alu_op_ctl_r <= (others => '0');
jump_ctl_r <= (others => '0');
branch_ctl_r <= (others => '0');
mem_write_ctl_r <= (others => '0');
mem_read_ctl_r <= (others => '0');
sig_read_ctl_r <= '0';
reg_to_mem_r <= '0';
mem_to_reg_r <= '0';
elsif clock'event and clock = '1' then
if stall_sig = '0' then
if mwait = '0' then
rd_r <= rd;
rs1_r <= rs1;
rs2_r <= rs2;
imm_i_r <= imm_i;
imm_s_r <= imm_s;
imm_sb_r <= imm_sb;
imm_u_r <= imm_u;
imm_uj_r <= imm_uj;
reg_write_ctl_r <= reg_write_ctl;
alu_src1_ctl_r <= alu_src1_ctl;
alu_src2_ctl_r <= alu_src2_ctl;
alu_op_ctl_r <= alu_op_ctl;
jump_ctl_r <= jump_ctl;
branch_ctl_r <= branch_ctl;
mem_write_ctl_r <= mem_write_ctl;
mem_read_ctl_r <= mem_read_ctl;
sig_read_ctl_r <= sig_read_ctl;
reg_to_mem_r <= reg_to_mem;
mem_to_reg_r <= mem_to_reg;
end if;
end if;
end if;
end process;
--
-- EXECUTE STAGE
--
-- 3rd stage (a) register file access (read)
-- the register file
register_bank: entity work.reg_bank
port map( clock => clock,
read_reg1 => read_reg1,
read_reg2 => read_reg2,
write_reg => write_reg,
wreg => wreg,
write_data => write_data,
read_data1 => read_data1,
read_data2 => read_data2
);
-- register file read/write selection and write enable
read_reg1 <= rs1_r;
read_reg2 <= rs2_r;
write_reg <= rd_r;
wreg <= ((reg_write_ctl_r or mem_to_reg_r_dly) and not mwait and not stall_reg) or alu_wait;
-- 3rd stage (b) ALU operation
alu: entity work.alu
port map( clock => clock,
reset => reset,
op1 => alu_src1,
op2 => alu_src2,
alu_op => alu_op_ctl_r,
result => result,
zero => zero,
less_than => less_than,
alu_wait => alu_wait
);
alu_src1 <= read_data1 when alu_src1_ctl_r = '0' else pc_last2;
alu_src2 <= imm_u_r & x"000" when alu_src2_ctl_r = "000" else
imm_i_r when alu_src2_ctl_r = "001" else
imm_s_r when alu_src2_ctl_r = "010" else
pc when alu_src2_ctl_r = "011" else
x"000000" & "000" & rs2_r when alu_src2_ctl_r = "100" else
read_data2;
branch_src1 <= read_data1 when jump_ctl_r = "11" else pc_last2;
branch_src2 <= imm_uj_r when jump_ctl_r = "10" else
imm_i_r when jump_ctl_r = "11" else imm_sb_r;
branch <= branch_src1 + branch_src2;
branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or -- BEQ
(zero = '0' and branch_ctl_r = "010") or -- BNE
(less_than = '1' and branch_ctl_r = "011") or -- BLT
(less_than = '0' and branch_ctl_r = "100") or -- BGE
(less_than = '1' and branch_ctl_r = "101") or -- BLTU
(less_than = '0' and branch_ctl_r = "110") -- BGEU
else '0';
except <= '1' when branch_ctl_r = "111" else '0';
jump_taken <= '1' when jump_ctl_r /= "00" else '0';
address <= result when data_access_s = '1' and mwait = '1' else pc;
data_b <= '1' when mem_read_ctl_r = "01" or mem_write_ctl_r = "01" else '0';
data_h <= '1' when mem_read_ctl_r = "10" or mem_write_ctl_r = "10" else '0';
data_access_s <= '1' when reg_to_mem_r = '1' or mem_to_reg_r = '1' else '0';
mwait <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
data_access <= mwait;
-- 3rd stage (c) data memory / write back operation, register file access (write)
-- memory access, store operations
process(mem_write_ctl_r, result, read_data2)
begin
case mem_write_ctl_r is
when "11" => -- store word
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);
data_w <= "1111";
when "01" => -- store byte
data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);
case result(1 downto 0) is
when "11" => data_w <= "0001";
when "10" => data_w <= "0010";
when "01" => data_w <= "0100";
when others => data_w <= "1000";
end case;
when "10" => -- store half word
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(7 downto 0) & read_data2(15 downto 8);
case result(1) is
when '1' => data_w <= "0011";
when others => data_w <= "1100";
end case;
when others => -- WTF??
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);
data_w <= "0000";
end case;
end process;
-- memory access, load operations
process(mem_read_ctl_r, result, data_in)
begin
case mem_read_ctl_r is
when "01" => -- load byte
case result(1 downto 0) is
when "11" => data_in_s <= x"000000" & data_in(7 downto 0);
when "10" => data_in_s <= x"000000" & data_in(15 downto 8);
when "01" => data_in_s <= x"000000" & data_in(23 downto 16);
when others => data_in_s <= x"000000" & data_in(31 downto 24);
end case;
when "10" => -- load half word
case result(1) is
when '1' => data_in_s <= x"0000" & data_in(7 downto 0) & data_in(15 downto 8);
when others => data_in_s <= x"0000" & data_in(23 downto 16) & data_in(31 downto 24);
end case;
when others => -- load word
data_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);
end case;
end process;
-- write back
ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or sig_read_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);
ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or sig_read_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);
write_data <= data_in_s when mem_read_ctl_r = "11" else
ext32b when mem_read_ctl_r = "01" else
ext32h when mem_read_ctl_r = "10" else
pc_last when jump_taken = '1' else result;
end arch_datapath;
| gpl-2.0 | a81b2627132010af57a5492723c40fa0 | 0.583039 | 2.536804 | false | false | false | false |
marcoep/LogicAnalyzerNano | LogicAnalyzer.vhd | 1 | 6,202 | -------------------------------------------------------------------------------
-- Title : Logic Analyzer, actual module
-- Project :
-------------------------------------------------------------------------------
-- File : LogicAnalyzer.vhd
-- Author : <Marco@JUDI>
-- Company :
-- Created : 2014-11-27
-- Last update: 2014-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Logic Analyzer Top Level design, with right Input Names etc.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-11-27 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity LogicAnalyzer is
port (
Clk_CI : in std_logic;
Reset_RBI : in std_logic;
BusDI_DI : in std_logic;
BusDO_DI : in std_logic;
BusCS_DI : in std_logic;
BusClk_SI : in std_logic;
Led_SO : out std_logic;
Btn_SI : in std_logic
);
end entity LogicAnalyzer;
architecture Behavioral of LogicAnalyzer is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component StorageRAM is
port (
aclr : in std_logic := '0';
address : in std_logic_vector (12 downto 0);
clock : in std_logic := '1';
data : in std_logic_vector (2 downto 0);
wren : in std_logic;
q : out std_logic_vector (2 downto 0));
end component StorageRAM;
-----------------------------------------------------------------------------
-- Type Declarations
-----------------------------------------------------------------------------
type FsmState_t is (INIT, WAITCLK, SAVE, WAITCLKRESET, RAMFULL);
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
-- Data in Bus and its FFed signals
signal Bus_D, BusF_D, BusFF_D : std_logic_vector(2 downto 0);
-- Bus Clock signal
signal BusClkF_S, BusClkFF_S : std_logic;
-- Counter Data Signals
signal AddrCnt_DP, AddrCnt_DN : unsigned(12 downto 0);
-- Control Signals
signal CntrEna_S, CntrEnded_S, BusClkOne_S, BusClkZero_S, RamWE_S : std_logic;
signal State_SP, State_SN : FsmState_t;
-----------------------------------------------------------------------------
--
--
-- Actual Implementation
--
--
-----------------------------------------------------------------------------
begin -- architecture Behavioral
BusClkZero_S <= not(BusClk_SI or BusClkF_S or BusClkFF_S);
BusClkOne_S <= (BusClk_SI and BusClkF_S and BusClkFF_S);
Bus_D <= (BusDI_DI & BusDO_DI & BusCS_DI);
StorageRAM_1 : entity work.StorageRAM
port map (
aclr => Reset_RBI,
address => std_logic_vector(AddrCnt_DP),
clock => Clk_CI,
data => BusFF_D,
wren => RamWE_S,
q => open);
AddrCnt_DN <= AddrCnt_DP +1;
AddressCounter : process (Clk_CI, Reset_RBI) is
begin -- process AddressCounter
if Reset_RBI = '0' then -- asynchronous reset (active low)
AddrCnt_DP <= (others => '0');
elsif Clk_CI'event and Clk_CI = '1' then -- rising clock edge
if CntrEna_S = '1' then
AddrCnt_DP <= AddrCnt_DN;
end if;
end if;
end process AddressCounter;
BusAndClockFF : process (Clk_CI, Reset_RBI) is
begin -- process Bus and Clock Flipflops
if Reset_RBI = '0' then -- asynchronous reset (active low)
BusF_D <= (others => '0');
BusFF_D <= (others => '0');
BusClkF_S <= '0';
BusClkFF_S <= '0';
elsif Clk_CI'event and Clk_CI = '1' then -- rising clock edge
BusF_D <= Bus_D;
BusFF_D <= BusF_D;
BusClkF_S <= BusClk_SI;
BusClkFF_S <= BusClkF_S;
end if;
end process BusAndClockFF;
-----------------------------------------------------------------------------
-- FSM
-----------------------------------------------------------------------------
FSMNextState : process (AddrCnt_DP, Btn_SI, BusClkOne_S, BusClkZero_S,
BusFF_D(0), State_SP) is
begin -- process FSMNextState
RamWE_S <= '0';
CntrEna_S <= '0';
Led_SO <= '0';
State_SN <= State_SP;
case State_SP is
-------------------------------------------------------------------------
when INIT =>
if BusFF_D(0) = '1' then
State_SN <= WAITCLK;
end if;
-----------------------------------------------------------------------
when WAITCLK =>
if BusClkOne_S = '1' then
State_SN <= SAVE;
end if;
if AddrCnt_DP = "1111111111111" or Btn_SI = '1' then
State_SN <= RAMFULL;
end if;
-------------------------------------------------------------------------
when RAMFULL =>
Led_SO <= '1';
-------------------------------------------------------------------------
when SAVE =>
RamWE_S <= '1';
CntrEna_S <= '1';
State_SN <= WAITCLKRESET;
-------------------------------------------------------------------------
when WAITCLKRESET =>
if BusClkZero_S = '1' then
State_SN <= WAITCLK;
end if;
-------------------------------------------------------------------------
when others =>
State_SN <= INIT;
end case;
end process FSMNextState;
FSMProgress : process (Clk_CI, Reset_RBI) is
begin -- process FSMProgress
if Reset_RBI = '0' then -- asynchronous reset (active low)
State_SP <= INIT;
elsif Clk_CI'event and Clk_CI = '1' then -- rising clock edge
State_SP <= State_SN;
end if;
end process FSMProgress;
end architecture Behavioral;
| mit | b9c4333c47c49090e178c9ffb6a7f5d8 | 0.412448 | 4.494203 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/genlib.vhd | 1 | 6,452 | -- $Id: genlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: genlib
-- Description: some general purpose components
--
-- Dependencies: -
-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 757 1.1 move cdc_pulse to cdclib
-- 2016-03-25 751 1.0.10 add gray_cnt_6
-- 2012-12-29 466 1.0.9 add led_pulse_stretch
-- 2011-11-09 421 1.0.8 add cdc_pulse
-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
-- 2010-04-02 273 1.0.6 add timer
-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
-- 2007-12-25 105 1.0.3 RESET:='0' defaults
-- 2007-06-17 58 1.0.2 added debounce_gen
-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package genlib is
component clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end component;
component cnt_array_dram is -- counter array, dram based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : out slv(AWIDTH-1 downto 0); -- counter address
DATA : out slv(DWIDTH-1 downto 0); -- counter data
ACT : out slbit -- active (not reseting)
);
end component;
component cnt_array_regs is -- counter array, register based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : in slv(AWIDTH-1 downto 0); -- address
DATA : out slv(DWIDTH-1 downto 0) -- counter data
);
end component;
component debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end component;
component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end component;
component gray_cnt_6 is -- 6 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end component;
component gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end component;
component timer is -- retriggerable timer
generic (
TWIDTH : positive := 4; -- timer counter width
RETRIG : boolean := true); -- re-triggerable true/false
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
START : in slbit; -- start timer
STOP : in slbit := '0'; -- stop timer
DONE : out slbit; -- mark last delay cycle
BUSY : out slbit -- timer running
);
end component;
component led_pulse_stretch is -- pulse stretcher for leds
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- pulse time unit clock enable
RESET : in slbit := '0'; -- reset
DIN : in slbit; -- data in
POUT : out slbit -- pulse out
);
end component;
end package genlib;
| gpl-3.0 | 3f49e2fae487ce98fc6d3ef2b54114c3 | 0.50248 | 3.960712 | false | false | false | false |
wfjm/w11 | rtl/bplib/nxcramlib/nx_cram_dummy.vhd | 1 | 1,972 | -- $Id: nx_cram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nx_cram_dummy - syn
-- Description: nexys2/3: CRAM protection dummy
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 renamed from n2_cram_dummy
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port
-- 2010-05-28 295 1.0.1 use _ADV_N
-- 2010-05-21 292 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nx_cram_dummy is -- CRAM protection dummy
port (
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end nx_cram_dummy;
architecture syn of nx_cram_dummy is
begin
O_MEM_CE_N <= '1'; -- disable cram chip
O_MEM_BE_N <= "11";
O_MEM_WE_N <= '1';
O_MEM_OE_N <= '1';
O_MEM_ADV_N <= '1';
O_MEM_CLK <= '0';
O_MEM_CRE <= '0';
O_MEM_ADDR <= (others=>'0');
IO_MEM_DATA <= (others=>'0');
end syn;
| gpl-3.0 | 8d8f3e9d230d520c5c981705a733badd | 0.507606 | 3.095761 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/usr_access_unisim.vhd | 1 | 1,576 | -- $Id: usr_access_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: usr_access_unisim - syn
-- Description: Wrapper for USR_ACCESS* entities
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity usr_access_unisim is -- wrapper for USR_ACCESS family
port (
DATA : out slv32 -- usr_access register value
);
end usr_access_unisim;
architecture syn of usr_access_unisim is
signal DATA_RAW : slv32 := (others=>'0');
begin
UA : USR_ACCESSE2
port map (
CFGCLK => open,
DATA => DATA_RAW,
DATAVALID => open
);
-- the USR_ACCESSE2 simulation model unfortunately returns always 'UUUU'
-- no way to configure it for reasonable simulation behavior
-- there this sanitiser
proc_data: process (DATA_RAW)
variable idata : slv32 := (others=>'0');
begin
idata := to_x01(DATA_RAW);
if is_x(idata) then
idata := (others=>'0');
end if;
DATA <= idata;
end process proc_data;
end syn;
| gpl-3.0 | a3db2fe1c21f69d50a7251e1cdfa2116 | 0.568528 | 3.725768 | false | false | false | false |
nanomolina/vhdl_examples | aludec/test_aludec.vhd | 2 | 1,606 | library ieee;
use ieee.std_logic_1164.all;
entity test_aludec is
end entity;
architecture arq_test_aludec of test_aludec is
component aludec
port (funct: in std_logic_vector(5 downto 0);
aluop: in std_logic_vector(1 downto 0);
alucontrol: out std_logic_vector(2 downto 0));
end component;
signal funct_1: std_logic_vector(5 downto 0);
signal aluop_1: std_logic_vector(1 downto 0);
signal alucontrol_1: std_logic_vector(2 downto 0);
begin
prueba: aludec port map (funct_1, aluop_1, alucontrol_1);
process
begin
aluop_1 <= "00";
wait for 5 ns;
aluop_1 <= "01";
wait for 5 ns;
aluop_1 <= "10";
wait for 5 ns;
aluop_1 <= "11";
wait for 5 ns;
aluop_1 <= "11";
wait for 5 ns;
aluop_1 <= "10";
wait for 5 ns;
aluop_1 <= "01";
wait for 5 ns;
aluop_1 <= "11";
wait for 5 ns;
aluop_1 <= "10";
wait for 5 ns;
end process;
process
begin
funct_1 <= "000000";
wait for 5 ns;
funct_1 <= "010101";
wait for 5 ns;
funct_1 <= "100000";
wait for 5 ns;
funct_1 <= "100100";
wait for 5 ns;
funct_1 <= "100101";
wait for 5 ns;
funct_1 <= "101010";
wait for 5 ns;
funct_1 <= "100010";
wait for 5 ns;
funct_1 <= "100101";
wait for 5 ns;
funct_1 <= "100000";
wait for 5 ns;
funct_1 <= "100010";
wait for 5 ns;
end process;
end architecture;
| gpl-3.0 | 0c878b8e6d49f0c74c4c1ac9bcea53c3 | 0.50934 | 3.560976 | false | false | false | false |
jsyk/spnsyn-demo | t/tslink00/results/tslink_ct.vhd | 1 | 14,240 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
package comp_tslink_ct is
component tslink_ct is
port (
clk : in std_ulogic;
rst : in std_ulogic;
LinkIn : in std_ulogic;
IValid : in std_ulogic;
QAck : in std_ulogic;
IData : in std_logic_vector(7 downto 0);
IAck : out std_ulogic;
ShiftEnable : out std_ulogic;
LinkOut : out std_ulogic;
QValid : out std_ulogic
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
entity tslink_ct is
port (
clk : in std_ulogic;
rst : in std_ulogic;
LinkIn : in std_ulogic;
IValid : in std_ulogic;
QAck : in std_ulogic;
IData : in std_logic_vector(7 downto 0);
IAck : out std_ulogic;
ShiftEnable : out std_ulogic;
LinkOut : out std_ulogic;
QValid : out std_ulogic
);
end entity;
architecture rtl of tslink_ct is
-- Undefined attributes (assuming inputs):
signal S_QAck : std_ulogic;
signal S_IData : std_logic_vector(7 downto 0);
signal S_IValid : std_ulogic;
signal S_LinkIn : std_ulogic;
-- Defined attributes:
signal FS10 : std_ulogic;
signal FP11 : std_ulogic;
signal FP21 : std_ulogic;
signal FP111 : std_ulogic;
signal FP151 : std_ulogic;
signal FP161 : std_ulogic;
signal FS40 : std_ulogic;
signal FP171 : std_ulogic;
signal FP281 : std_ulogic;
signal FS2_cnd0 : std_ulogic;
signal FS2_cnd1 : std_ulogic;
signal FS22 : std_ulogic;
signal FS3_cnd0 : std_ulogic;
signal FS3_cnd1 : std_ulogic;
signal FT9F2 : std_ulogic;
signal FP2S_C01 : std_ulogic;
signal FP2S_C11 : std_ulogic;
signal FP2S_C21 : std_ulogic;
signal FP2S_C31 : std_ulogic;
signal FP2S_C41 : std_ulogic;
signal FP2S_C51 : std_ulogic;
signal FP2S_C61 : std_ulogic;
signal FP2S_C71 : std_ulogic;
signal FP2S_C81 : std_ulogic;
signal FS2P_C01 : std_ulogic;
signal FS2P_C11 : std_ulogic;
signal FS2P_C21 : std_ulogic;
signal FS2P_C31 : std_ulogic;
signal FS2P_C41 : std_ulogic;
signal FS2P_C51 : std_ulogic;
signal FS2P_C61 : std_ulogic;
signal FS2P_C71 : std_ulogic;
signal FS2P_C81 : std_ulogic;
signal N_ow_IAck_0 : std_ulogic;
signal N_ow_ShiftEnable_1 : std_ulogic;
signal N_ow_LinkOut_2 : std_ulogic;
signal N_ow_QValid_3 : std_ulogic;
signal N_FS10_4 : std_ulogic;
signal N_FS10_SSW_5 : std_ulogic;
signal N_FS10_SSR_6 : std_ulogic;
signal N_FP21_7 : std_ulogic;
signal N_FP21_SSW_8 : std_ulogic;
signal N_FP21_SSR_9 : std_ulogic;
signal N_FP151_10 : std_ulogic;
signal N_FP151_SSW_11 : std_ulogic;
signal N_FP151_SSR_12 : std_ulogic;
signal N_FS40_13 : std_ulogic;
signal N_FS40_SSW_14 : std_ulogic;
signal N_FS40_SSR_15 : std_ulogic;
signal N_FP171_16 : std_ulogic;
signal N_FP171_SSW_17 : std_ulogic;
signal N_FP171_SSR_18 : std_ulogic;
signal N_FP281_19 : std_ulogic;
signal N_FP281_SSW_20 : std_ulogic;
signal N_FP281_SSR_21 : std_ulogic;
signal N_FP281_SSW_22 : std_ulogic;
signal N_FP281_SSR_23 : std_ulogic;
signal N_FS22_24 : std_ulogic;
signal N_FS22_SSR_26 : std_ulogic;
signal N_FS3_cnd0_27 : std_ulogic;
signal N_FS3_cnd0_SSW_28 : std_ulogic;
signal N_FS3_cnd0_SSR_29 : std_ulogic;
signal N_FS3_cnd1_30 : std_ulogic;
signal N_FS3_cnd1_SSW_31 : std_ulogic;
signal N_FS3_cnd1_SSR_32 : std_ulogic;
signal N_FT9F2_33 : std_ulogic;
signal N_FT9F2_SSW_34 : std_ulogic;
signal N_FT9F2_SSR_35 : std_ulogic;
signal N_FS2P_C81_36 : std_ulogic;
signal N_FS2P_C81_SSW_37 : std_ulogic;
signal N_FS2P_C81_SSR_38 : std_ulogic;
signal PP1st0 : std_ulogic;
signal PP2st0 : std_ulogic;
signal PP11st0 : std_ulogic;
signal PP12st0 : std_ulogic;
signal PP14st0 : std_ulogic;
signal PP15st0 : std_ulogic;
signal PP16st0 : std_ulogic;
signal PP17st0 : std_ulogic;
signal PP28st0 : std_ulogic;
signal PP29st0 : std_ulogic;
signal PP2S_C0st0 : std_ulogic;
signal PP2S_C1st0 : std_ulogic;
signal PP2S_C2st0 : std_ulogic;
signal PP2S_C3st0 : std_ulogic;
signal PP2S_C4st0 : std_ulogic;
signal PP2S_C5st0 : std_ulogic;
signal PP2S_C6st0 : std_ulogic;
signal PP2S_C7st0 : std_ulogic;
signal PP2S_C8st0 : std_ulogic;
signal PP2S_C9st0 : std_ulogic;
signal PS2P_C0st0 : std_ulogic;
signal PS2P_C1st0 : std_ulogic;
signal PS2P_C2st0 : std_ulogic;
signal PS2P_C3st0 : std_ulogic;
signal PS2P_C4st0 : std_ulogic;
signal PS2P_C5st0 : std_ulogic;
signal PS2P_C6st0 : std_ulogic;
signal PS2P_C7st0 : std_ulogic;
signal PS2P_C8st0 : std_ulogic;
begin
-- I/O assignments:
S_LinkIn <= LinkIn;
S_IValid <= IValid;
S_QAck <= QAck;
S_IData <= IData;
IAck <= N_ow_IAck_0;
ShiftEnable <= N_ow_ShiftEnable_1;
LinkOut <= N_ow_LinkOut_2;
QValid <= N_ow_QValid_3;
-- code-gen (blackbox) instances (0)
-- FS10 : std_ulogic
FS10 <= (N_FS10_4 and N_FS10_SSW_5);
-- FP11 : std_ulogic
FP11 <= (PP1st0 and not PP2st0 and S_LinkIn);
-- FP21 : std_ulogic
FP21 <= (N_FP21_7 and N_FP21_SSW_8);
-- FP111 : std_ulogic
FP111 <= (PP11st0 and not PP12st0 and not S_IValid);
-- FP151 : std_ulogic
FP151 <= (N_FP151_10 and N_FP151_SSW_11);
-- FP161 : std_ulogic
FP161 <= (PP16st0 and not PP29st0 and not S_QAck);
-- FS40 : std_ulogic
FS40 <= (N_FS40_13 and N_FS40_SSW_14);
-- FP171 : std_ulogic
FP171 <= (N_FP171_16 and N_FP171_SSW_17);
-- FP281 : std_ulogic
FP281 <= (N_FP281_19 and N_FP281_SSW_20 and N_FP281_SSW_22);
-- FS2_cnd0 : std_ulogic
FS2_cnd0 <= not S_LinkIn;
-- FS2_cnd1 : std_ulogic
FS2_cnd1 <= S_LinkIn;
-- FS22 : std_ulogic
FS22 <= (N_FS22_24 and N_FP281_SSW_22);
-- FS3_cnd0 : std_ulogic
FS3_cnd0 <= (N_FS3_cnd0_27 and N_FS3_cnd0_SSW_28);
-- FS3_cnd1 : std_ulogic
FS3_cnd1 <= (N_FS3_cnd1_30 and N_FS3_cnd1_SSW_31);
-- FT9F2 : std_ulogic
FT9F2 <= (N_FT9F2_33 and N_FT9F2_SSW_34);
-- FP2S_C01 : std_ulogic
FP2S_C01 <= (PP2S_C0st0 and not PP2S_C1st0);
-- FP2S_C11 : std_ulogic
FP2S_C11 <= (PP2S_C1st0 and not PP2S_C2st0);
-- FP2S_C21 : std_ulogic
FP2S_C21 <= (PP2S_C2st0 and not PP2S_C3st0);
-- FP2S_C31 : std_ulogic
FP2S_C31 <= (PP2S_C3st0 and not PP2S_C4st0);
-- FP2S_C41 : std_ulogic
FP2S_C41 <= (PP2S_C4st0 and not PP2S_C5st0);
-- FP2S_C51 : std_ulogic
FP2S_C51 <= (PP2S_C5st0 and not PP2S_C6st0);
-- FP2S_C61 : std_ulogic
FP2S_C61 <= (PP2S_C6st0 and not PP2S_C7st0);
-- FP2S_C71 : std_ulogic
FP2S_C71 <= (PP2S_C7st0 and not PP2S_C8st0);
-- FP2S_C81 : std_ulogic
FP2S_C81 <= (PP2S_C8st0 and not PP2S_C9st0);
-- FS2P_C01 : std_ulogic
FS2P_C01 <= (PS2P_C0st0 and not PS2P_C1st0);
-- FS2P_C11 : std_ulogic
FS2P_C11 <= (PS2P_C1st0 and not PS2P_C2st0);
-- FS2P_C21 : std_ulogic
FS2P_C21 <= (PS2P_C2st0 and not PS2P_C3st0);
-- FS2P_C31 : std_ulogic
FS2P_C31 <= (PS2P_C3st0 and not PS2P_C4st0);
-- FS2P_C41 : std_ulogic
FS2P_C41 <= (PS2P_C4st0 and not PS2P_C5st0);
-- FS2P_C51 : std_ulogic
FS2P_C51 <= (PS2P_C5st0 and not PS2P_C6st0);
-- FS2P_C61 : std_ulogic
FS2P_C61 <= (PS2P_C6st0 and not PS2P_C7st0);
-- FS2P_C71 : std_ulogic
FS2P_C71 <= (PS2P_C7st0 and not PS2P_C8st0);
-- FS2P_C81 : std_ulogic
FS2P_C81 <= (N_FS2P_C81_36 and N_FS2P_C81_SSW_37);
-- N_ow_IAck_0 : std_ulogic
N_ow_IAck_0 <= FP281;
-- N_ow_ShiftEnable_1 : std_ulogic
N_ow_ShiftEnable_1 <= (FS2P_C01 or FS2P_C11 or FS2P_C21 or FS2P_C31 or FS2P_C41 or FS2P_C51 or FS2P_C61 or FS2P_C71);
-- N_ow_LinkOut_2 : std_ulogic
N_ow_LinkOut_2 <= (FP2S_C01 or FS3_cnd1 or FS3_cnd0 or (FP2S_C11 and S_IData(0)) or (FP2S_C21 and S_IData(1)) or (FP2S_C31 and S_IData(2)) or (FP2S_C41 and S_IData(3)) or (FP2S_C51 and S_IData(4)) or (FP2S_C61 and S_IData(5)) or (FP2S_C71 and S_IData(6)) or (FP2S_C81 and S_IData(7)));
-- N_ow_QValid_3 : std_ulogic
N_ow_QValid_3 <= PP14st0;
-- N_FS10_4 : std_ulogic
N_FS10_4 <= not PP1st0;
-- N_FS10_SSW_5 : std_ulogic
N_FS10_SSW_5 <= (N_FP281_SSR_21 or N_FS2P_C81_SSR_38);
-- N_FS10_SSR_6 : std_ulogic
N_FS10_SSR_6 <= N_FS10_4;
-- N_FP21_7 : std_ulogic
N_FP21_7 <= PP2st0;
-- N_FP21_SSW_8 : std_ulogic
N_FP21_SSW_8 <= (N_FP281_SSR_23 or N_FS22_SSR_26);
-- N_FP21_SSR_9 : std_ulogic
N_FP21_SSR_9 <= N_FP21_7;
-- N_FP151_10 : std_ulogic
N_FP151_10 <= (PP15st0 and not PP16st0 and S_QAck);
-- N_FP151_SSW_11 : std_ulogic
N_FP151_SSW_11 <= (N_FS40_SSR_15 and not N_FT9F2_SSR_35);
-- N_FP151_SSR_12 : std_ulogic
N_FP151_SSR_12 <= N_FP151_10;
-- N_FS40_13 : std_ulogic
N_FS40_13 <= not PP17st0;
-- N_FS40_SSW_14 : std_ulogic
N_FS40_SSW_14 <= (N_FT9F2_SSR_35 or N_FP151_SSR_12);
-- N_FS40_SSR_15 : std_ulogic
N_FS40_SSR_15 <= N_FS40_13;
-- N_FP171_16 : std_ulogic
N_FP171_16 <= PP17st0;
-- N_FP171_SSW_17 : std_ulogic
N_FP171_SSW_17 <= (N_FS3_cnd0_SSR_29 or N_FS3_cnd1_SSR_32);
-- N_FP171_SSR_18 : std_ulogic
N_FP171_SSR_18 <= N_FP171_16;
-- N_FP281_19 : std_ulogic
N_FP281_19 <= (PP28st0 and not PP11st0 and FS2_cnd0);
-- N_FP281_SSW_20 : std_ulogic
N_FP281_SSW_20 <= N_FS10_SSR_6;
-- N_FP281_SSR_21 : std_ulogic
N_FP281_SSR_21 <= (N_FP281_19 and N_FP281_SSW_22);
-- N_FP281_SSW_22 : std_ulogic
N_FP281_SSW_22 <= N_FP21_SSR_9;
-- N_FP281_SSR_23 : std_ulogic
N_FP281_SSR_23 <= (N_FP281_19 and N_FP281_SSW_20);
-- N_FS22_24 : std_ulogic
N_FS22_24 <= (FS2_cnd1 and not PS2P_C0st0);
-- N_FS22_SSR_26 : std_ulogic
N_FS22_SSR_26 <= N_FS22_24;
-- N_FS3_cnd0_27 : std_ulogic
N_FS3_cnd0_27 <= (PP14st0 and not PP15st0);
-- N_FS3_cnd0_SSW_28 : std_ulogic
N_FS3_cnd0_SSW_28 <= N_FP171_SSR_18;
-- N_FS3_cnd0_SSR_29 : std_ulogic
N_FS3_cnd0_SSR_29 <= N_FS3_cnd0_27;
-- N_FS3_cnd1_30 : std_ulogic
N_FS3_cnd1_30 <= (S_IValid and not PP2S_C0st0 and PP12st0);
-- N_FS3_cnd1_SSW_31 : std_ulogic
N_FS3_cnd1_SSW_31 <= (N_FP171_SSR_18 and not N_FS3_cnd0_SSR_29);
-- N_FS3_cnd1_SSR_32 : std_ulogic
N_FS3_cnd1_SSR_32 <= N_FS3_cnd1_30;
-- N_FT9F2_33 : std_ulogic
N_FT9F2_33 <= (not PP28st0 and PP2S_C9st0);
-- N_FT9F2_SSW_34 : std_ulogic
N_FT9F2_SSW_34 <= N_FS40_SSR_15;
-- N_FT9F2_SSR_35 : std_ulogic
N_FT9F2_SSR_35 <= N_FT9F2_33;
-- N_FS2P_C81_36 : std_ulogic
N_FS2P_C81_36 <= (PS2P_C8st0 and not PP14st0 and PP29st0);
-- N_FS2P_C81_SSW_37 : std_ulogic
N_FS2P_C81_SSW_37 <= (N_FS10_SSR_6 and not N_FP281_SSR_21);
-- N_FS2P_C81_SSR_38 : std_ulogic
N_FS2P_C81_SSR_38 <= N_FS2P_C81_36;
all_ffs: process (clk) is
begin
if rising_edge(clk) then
if to_bool(rst) then
PP1st0 <= '1';
PP2st0 <= '0';
PP11st0 <= '0';
PP12st0 <= '1';
PP14st0 <= '0';
PP15st0 <= '0';
PP16st0 <= '0';
PP17st0 <= '1';
PP28st0 <= '0';
PP29st0 <= '1';
PP2S_C0st0 <= '0';
PP2S_C1st0 <= '0';
PP2S_C2st0 <= '0';
PP2S_C3st0 <= '0';
PP2S_C4st0 <= '0';
PP2S_C5st0 <= '0';
PP2S_C6st0 <= '0';
PP2S_C7st0 <= '0';
PP2S_C8st0 <= '0';
PP2S_C9st0 <= '0';
PS2P_C0st0 <= '0';
PS2P_C1st0 <= '0';
PS2P_C2st0 <= '0';
PS2P_C3st0 <= '0';
PS2P_C4st0 <= '0';
PS2P_C5st0 <= '0';
PS2P_C6st0 <= '0';
PS2P_C7st0 <= '0';
PS2P_C8st0 <= '0';
else
if to_bool((FS2P_C81 or not PS2P_C8st0)) then
PS2P_C8st0 <= FS2P_C71;
end if;
if to_bool((FS2P_C71 or not PS2P_C7st0)) then
PS2P_C7st0 <= FS2P_C61;
end if;
if to_bool((FS2P_C61 or not PS2P_C6st0)) then
PS2P_C6st0 <= FS2P_C51;
end if;
if to_bool((FS2P_C51 or not PS2P_C5st0)) then
PS2P_C5st0 <= FS2P_C41;
end if;
if to_bool((FS2P_C41 or not PS2P_C4st0)) then
PS2P_C4st0 <= FS2P_C31;
end if;
if to_bool((FS2P_C31 or not PS2P_C3st0)) then
PS2P_C3st0 <= FS2P_C21;
end if;
if to_bool((FS2P_C21 or not PS2P_C2st0)) then
PS2P_C2st0 <= FS2P_C11;
end if;
if to_bool((FS2P_C11 or not PS2P_C1st0)) then
PS2P_C1st0 <= FS2P_C01;
end if;
if to_bool((FS2P_C01 or not PS2P_C0st0)) then
PS2P_C0st0 <= FS22;
end if;
if to_bool((FT9F2 or not PP2S_C9st0)) then
PP2S_C9st0 <= FP2S_C81;
end if;
if to_bool((FP2S_C81 or not PP2S_C8st0)) then
PP2S_C8st0 <= FP2S_C71;
end if;
if to_bool((FP2S_C71 or not PP2S_C7st0)) then
PP2S_C7st0 <= FP2S_C61;
end if;
if to_bool((FP2S_C61 or not PP2S_C6st0)) then
PP2S_C6st0 <= FP2S_C51;
end if;
if to_bool((FP2S_C51 or not PP2S_C5st0)) then
PP2S_C5st0 <= FP2S_C41;
end if;
if to_bool((FP2S_C41 or not PP2S_C4st0)) then
PP2S_C4st0 <= FP2S_C31;
end if;
if to_bool((FP2S_C31 or not PP2S_C3st0)) then
PP2S_C3st0 <= FP2S_C21;
end if;
if to_bool((FP2S_C21 or not PP2S_C2st0)) then
PP2S_C2st0 <= FP2S_C11;
end if;
if to_bool((FP2S_C11 or not PP2S_C1st0)) then
PP2S_C1st0 <= FP2S_C01;
end if;
if to_bool((FP2S_C01 or not PP2S_C0st0)) then
PP2S_C0st0 <= FS3_cnd1;
end if;
if to_bool((FS2P_C81 or not PP29st0)) then
PP29st0 <= FP161;
end if;
if to_bool((FP281 or not PP28st0)) then
PP28st0 <= FT9F2;
end if;
if to_bool((FP171 or not PP17st0)) then
PP17st0 <= FS40;
end if;
if to_bool((FP161 or not PP16st0)) then
PP16st0 <= FP151;
end if;
if to_bool((FP151 or not PP15st0)) then
PP15st0 <= FS3_cnd0;
end if;
if to_bool((FS3_cnd0 or not PP14st0)) then
PP14st0 <= FS2P_C81;
end if;
if to_bool((FS3_cnd1 or not PP12st0)) then
PP12st0 <= FP111;
end if;
if to_bool((FP111 or not PP11st0)) then
PP11st0 <= FP281;
end if;
if to_bool((FP21 or not PP2st0)) then
PP2st0 <= FP11;
end if;
if to_bool((FP11 or not PP1st0)) then
PP1st0 <= FS10;
end if;
end if;
end if;
end process;
end architecture rtl;
| gpl-2.0 | 04ba8c299407c02eef1f67cfd3cc1e19 | 0.600281 | 2.280224 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys2/tb/nexys2_fusp_cuff_dummy.vhd | 1 | 3,857 | -- $Id: nexys2_fusp_cuff_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys2_fusp_cuff_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.0 Initial version (derived nexys2_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_fusp_cuff_dummy is -- NEXYS 2 dummy (+fusp+cuff; loopback)
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end nexys2_fusp_cuff_dummy;
architecture syn of nexys2_fusp_cuff_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet
O_FX2_SLWR_N <= '1';
O_FX2_SLOE_N <= '1';
O_FX2_PKTEND_N <= '1';
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
| gpl-3.0 | 6e1453ed253619a03d3215bd5bc234d8 | 0.490277 | 3.182343 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_dz11.vhd | 1 | 31,769 | -- $Id: ibdr_dz11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dz11 - syn
-- Description: ibus dev(rem): DZ11
--
-- Dependencies: fifo_simple_dram
-- ib_rlim_slv
-- Test bench: xxdp: zdzaj0
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-05-19 1150 1.0 Initial version
-- 2019-05-01 1144 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dz11 is -- ibus dev(rem): DZ11
-- fixed address: 160100
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#160100#,16));
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dz11;
architecture syn of ibdr_dz11 is
-- loc view register naming, offsets and bit definitions
constant ibaddr_csr : slv2 := "00"; -- csr address offset
constant ibaddr_rbuf_lpr : slv2 := "01"; -- rbuf/lpr address offset
constant ibaddr_tcr : slv2 := "10"; -- tcr address offset
constant ibaddr_msr_tdr : slv2 := "11"; -- msr/tdr address offset
constant csr_ibf_trdy : integer := 15;
constant csr_ibf_tie : integer := 14;
constant csr_ibf_sa : integer := 13;
constant csr_ibf_sae : integer := 12;
subtype csr_ibf_tline is integer range 10 downto 8;
constant csr_ibf_rdone : integer := 7;
constant csr_ibf_rie : integer := 6;
constant csr_ibf_mse : integer := 5;
constant csr_ibf_clr : integer := 4;
constant csr_ibf_maint : integer := 3;
constant rbuf_ibf_val : integer := 15;
constant rbuf_ibf_ferr : integer := 13;
subtype rbuf_ibf_line is integer range 10 downto 8;
subtype rbuf_ibf_data is integer range 7 downto 0;
constant lpr_ibf_rxon : integer := 12;
subtype lpr_ibf_line is integer range 2 downto 0;
subtype tcr_ibf_dtr is integer range 15 downto 8;
subtype tcr_ibf_lena is integer range 7 downto 0;
subtype msr_ibf_co is integer range 15 downto 8;
subtype msr_ibf_ring is integer range 7 downto 0;
subtype tdr_ibf_brk is integer range 15 downto 8;
subtype tdr_ibf_tbuf is integer range 7 downto 0;
-- rem view register naming, offsets and bit definitions
constant ibaddr_cntl : slv2 := "00"; -- cntl address offset
constant ibaddr_stat : slv2 := "01"; -- stat address offset
constant ibaddr_fuse : slv2 := "10"; -- fuse address offset
constant ibaddr_fdat : slv2 := "11"; -- fdat address offset
-- rem-r view
subtype cntl_ibf_awdth is integer range 10 downto 8;
subtype cntl_ibf_ssel is integer range 4 downto 3; -- also wr
constant cntl_ibf_sam: integer := 7; -- also wr
constant cntl_ibf_mse : integer := 2;
constant cntl_ibf_maint : integer := 1;
-- rem-w view
subtype cntl_ibf_data is integer range 15 downto 8;
subtype cntl_ibf_rrlim is integer range 14 downto 12;
subtype cntl_ibf_trlim is integer range 10 downto 8;
constant cntl_ibf_rclr : integer := 6;
constant cntl_ibf_tclr : integer := 5;
-- cntl_ibf_ssel is integer range 4 downto 3;
subtype cntl_ibf_func is integer range 2 downto 0;
constant func_noop : slv3 := "000"; -- func: noop
constant func_sco : slv3 := "001"; -- func: set CO
constant func_sring : slv3 := "010"; -- func: set RING
constant func_srlim : slv3 := "011"; -- func: set RLIM
constant ssel_dtle : slv2 := "00"; -- ssel: get DTR and LENA
constant ssel_brrx : slv2 := "01"; -- ssel: get BRK and RXON
constant ssel_cori : slv2 := "10"; -- ssel: get CO and RING
constant ssel_rlcn : slv2 := "11"; -- ssel: get RLIM and CNTL
constant cal_dtr : slv3 := "000"; -- cal: DTR
constant cal_brk : slv3 := "001"; -- cal: BRK
constant cal_rxon : slv3 := "010"; -- cal: RXON
constant cal_csr : slv3 := "011"; -- cal: CSR
subtype sdlle_ibf_dtr is integer range 15 downto 8;
subtype sdlle_ibf_lena is integer range 7 downto 0;
subtype sbrrx_ibf_brk is integer range 15 downto 8;
subtype sbrrx_ibf_rxon is integer range 7 downto 0;
subtype scori_ibf_co is integer range 15 downto 8;
subtype scori_ibf_ring is integer range 7 downto 0;
subtype srlcn_ibf_rrlim is integer range 14 downto 12;
subtype srlcn_ibf_trlim is integer range 10 downto 8;
constant srlcn_ibf_rir : integer := 7;
constant srlcn_ibf_tir : integer := 6;
constant srlcn_ibf_mse : integer := 5;
constant srlcn_ibf_maint: integer := 3;
subtype fuse_ibf_rsize is integer range AWIDTH-1+8 downto 8;
subtype fuse_ibf_tsize is integer range AWIDTH-1 downto 0;
constant fdat_ibf_val : integer := 15;
constant fdat_ibf_last : integer := 14;
constant fdat_ibf_ferr : integer := 13;
constant fdat_ibf_cal : integer := 11;
subtype fdat_ibf_line is integer range 10 downto 8;
subtype fdat_ibf_data is integer range 7 downto 0;
constant fbuf_ibf_cal : integer := 12;
constant fbuf_ibf_ferr : integer := 11;
subtype fbuf_ibf_line is integer range 10 downto 8;
subtype fbuf_ibf_data is integer range 7 downto 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
ssel : slv2; -- rcsr: status select
rrlim : slv3; -- rcsr: receiver rate limit
trlim : slv3; -- rcsr: transmitter rate limit
dtr : slv8; -- line state: dtr
lena : slv8; -- line state: lena
brk : slv8; -- line state: brk
rxon : slv8; -- line state: rxon
co : slv8; -- line state: co
ring : slv8; -- line state: ring
trdy : slbit; -- csr: transmitter ready
tie : slbit; -- csr: transmitter ie
sa : slbit; -- csr: silo alarm
sae : slbit; -- csr: silo alarm enable
tline : slv3; -- csr: transmit line
rdone : slbit; -- csr: receiver done
rie : slbit; -- csr: receiver ie
mse : slbit; -- csr: master scan enable
clr : slbit; -- csr: clear
maint : slbit; -- csr: maintenance mode
sam : slbit; -- sae monitor
lcnt : slv3; -- line counter
scnt : slv5; -- silo counter
qdtr : slbit; -- queue DTR alert
qbrk : slbit; -- queue BRK alert
qrxon : slbit; -- queue RXON alert
qcsr : slbit; -- queue CSR alert
qclr : slbit; -- queue CLR alert
rintreq : slbit; -- rx interrupt request
tintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"00","000","000", -- ssel,rrlim,trlim
(others=>'0'), -- dtr
(others=>'0'), -- lena
(others=>'0'), -- brk
(others=>'0'), -- rxon
(others=>'0'), -- co
(others=>'0'), -- ring
'0','0','0','0', -- trdy,tie,sa,sae
"000", -- tline
'0','0','0','0','0', -- rdone,rie,mse,clr,maint
'0', -- sam
(others=>'0'), -- lcnt
(others=>'0'), -- scnt
'0','0','0','0','0', -- qdtr,qbrk,qrxon,qcsr,qclr
'0','0' -- rintreq,tintreq
);
constant c_fuse1 : slv(AWIDTH-1 downto 0) := slv(to_unsigned(1,AWIDTH));
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal RBUF_CE : slbit := '0';
signal RBUF_WE : slbit := '0';
signal RBUF_DI : slv12 := (others=>'0');
signal RBUF_DO : slv12 := (others=>'0');
signal RBUF_RESET : slbit := '0';
signal RBUF_EMPTY : slbit := '0';
signal RBUF_FULL : slbit := '0';
signal RBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal TBUF_CE : slbit := '0';
signal TBUF_WE : slbit := '0';
signal TBUF_DI : slv13 := (others=>'0');
signal TBUF_DO : slv13 := (others=>'0');
signal TBUF_RESET : slbit := '0';
signal TBUF_EMPTY : slbit := '0';
signal TBUF_FULL : slbit := '0';
signal TBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RRLIM_START : slbit := '0';
signal RRLIM_BUSY : slbit := '0';
signal TRLIM_START : slbit := '0';
signal TRLIM_BUSY : slbit := '0';
pure function toint (val : slv3) return integer is
begin
return to_integer(unsigned(val));
end function toint;
begin
assert AWIDTH>=5 and AWIDTH<=7
report "assert(AWIDTH>=5 and AWIDTH<=7): unsupported AWIDTH"
severity failure;
RBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 12) -- FER+LINE(3)+BUF(8)
port map (
CLK => CLK,
RESET => RBUF_RESET,
CE => RBUF_CE,
WE => RBUF_WE,
DI => RBUF_DI,
DO => RBUF_DO,
EMPTY => RBUF_EMPTY,
FULL => RBUF_FULL,
SIZE => RBUF_FUSE
);
TBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 13) -- CAL+FER+LINE(3)+BUF(8)
port map (
CLK => CLK,
RESET => TBUF_RESET,
CE => TBUF_CE,
WE => TBUF_WE,
DI => TBUF_DI,
DO => TBUF_DO,
EMPTY => TBUF_EMPTY,
FULL => TBUF_FULL,
SIZE => TBUF_FUSE
);
RRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rrlim,
START => RRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RRLIM_BUSY
);
TRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.trlim,
START => TRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => TRLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET='1' or R_REGS.clr='1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.ssel <= N_REGS.ssel; -- keep SSEL field
R_REGS.rrlim <= N_REGS.rrlim; -- keep RRLIM field
R_REGS.trlim <= N_REGS.trlim; -- keep TRLIM field
R_REGS.qclr <= N_REGS.qclr; -- keep clr cal request
R_REGS.dtr <= N_REGS.dtr; -- keep DTR (model cntl)
R_REGS.co <= N_REGS.co; -- keep CO (model cntl)
R_REGS.ring <= N_REGS.ring; -- keep RING (model cntl)
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX, RESET,
RBUF_DO, RBUF_EMPTY, RBUF_FULL, RBUF_FUSE, RRLIM_BUSY,
TBUF_DO, TBUF_EMPTY, TBUF_FULL, TBUF_FUSE, TRLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable iback : slbit := '0';
variable ibrd : slbit := '0';
variable ibwr : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable irbufdi : slv12 := (others=>'0');
variable irbufce : slbit := '0';
variable irbufwe : slbit := '0';
variable irbufrst : slbit := '0';
variable irrlimsta : slbit := '0';
variable itbufdi : slv13 := (others=>'0');
variable itbufce : slbit := '0';
variable itbufwe : slbit := '0';
variable itbufrst : slbit := '0';
variable itrlimsta : slbit := '0';
variable ixbuffull : slbit := '0';
variable iscntclr : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
iback := r.ibsel and ibreq;
ibrd := IB_MREQ.re;
ibwr := IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
irbufdi := (others=>'0');
irbufce := '0';
irbufwe := '0';
irbufrst := RESET and not r.mse;
irrlimsta := '0';
itbufdi := (others=>'0');
itbufce := '0';
itbufwe := '0';
itbufrst := RESET;
itrlimsta := '0';
iscntclr := not r.mse;
-- setup for rbuf writes
if r.maint = '0' then -- not in maint mode (rem fifo write)
irbufdi(fbuf_ibf_ferr) := IB_MREQ.din(fdat_ibf_ferr);
irbufdi(fbuf_ibf_line) := IB_MREQ.din(fdat_ibf_line);
irbufdi(fbuf_ibf_data) := IB_MREQ.din(fdat_ibf_data);
else -- in maint mode (loc tbuf write)
irbufdi(fbuf_ibf_ferr) := '0'; -- brk ignored on maint mode
irbufdi(fbuf_ibf_line) := r.tline;
irbufdi(fbuf_ibf_data) := IB_MREQ.din(tdr_ibf_tbuf);
end if;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then -- ibus selected ---------------------
-- setup for tbuf writes generated from ibus accesses
itbufdi(fbuf_ibf_ferr) := r.brk(toint(r.tline));
itbufdi(fbuf_ibf_line) := r.tline;
itbufdi(fbuf_ibf_data) := IB_MREQ.din(tdr_ibf_tbuf);
if IB_MREQ.racc = '1' then -- rri view: rem side access -------
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL -- control --------------
idout(cntl_ibf_awdth) := slv(to_unsigned(AWIDTH,3));
idout(cntl_ibf_sam) := r.sam;
idout(cntl_ibf_ssel) := r.ssel;
idout(cntl_ibf_mse) := r.mse;
idout(cntl_ibf_maint) := r.maint;
if ibwr = '1' then
if IB_MREQ.din(cntl_ibf_sam) = '1' then
n.sam := '0';
end if;
if IB_MREQ.din(cntl_ibf_rclr) = '1' then
irbufrst := '1';
end if;
if IB_MREQ.din(cntl_ibf_tclr) = '1' then
itbufrst := '1';
end if;
n.ssel := IB_MREQ.din(cntl_ibf_ssel);
case IB_MREQ.din(cntl_ibf_func) is -- handle cntl.func ------
when func_sco => -- func: set CO ------
n.co := IB_MREQ.din(cntl_ibf_data);
when func_sring => -- func: set RING ----
n.ring := IB_MREQ.din(cntl_ibf_data);
when func_srlim => -- func: set RLIM ----
n.rrlim := IB_MREQ.din(cntl_ibf_rrlim);
n.trlim := IB_MREQ.din(cntl_ibf_trlim);
when others => null;
end case;
end if;
when ibaddr_stat => -- STAT -- status ---------------
case r.ssel is
when ssel_dtle => -- ssel: get DTR and LENA
idout(sdlle_ibf_dtr) := r.dtr;
idout(sdlle_ibf_lena) := r.lena;
when ssel_brrx => -- ssel: get BRK and RXON
idout(sbrrx_ibf_brk) := r.brk;
idout(sbrrx_ibf_rxon) := r.rxon;
when ssel_cori => -- ssel: get CO and RING
idout(scori_ibf_co) := r.co;
idout(scori_ibf_ring) := r.ring;
when ssel_rlcn => -- ssel: get CNTL and RLIM
idout(srlcn_ibf_rrlim) := r.rrlim;
idout(srlcn_ibf_trlim) := r.trlim;
idout(srlcn_ibf_rir) := r.rintreq;
idout(srlcn_ibf_tir) := r.tintreq;
idout(srlcn_ibf_mse) := r.mse;
idout(srlcn_ibf_maint) := r.maint;
when others => null;
end case;
if ibrd = '1' then -- advance ssel on read
n.ssel := slv(unsigned(r.ssel) + 1);
end if;
if ibwr = '1' then -- stat is read-only
iback := '0';
end if;
when ibaddr_fuse => -- FUSE -- fifo usage -----------
idout(fuse_ibf_rsize) := RBUF_FUSE;
idout(fuse_ibf_tsize) := TBUF_FUSE;
when ibaddr_fdat => -- FDAT -- fifo read/write ------
idout(fdat_ibf_val) := not TBUF_EMPTY;
if TBUF_FUSE = c_fuse1 then
idout(fdat_ibf_last) := '1';
end if;
idout(fdat_ibf_ferr) := TBUF_DO(fbuf_ibf_ferr);
idout(fdat_ibf_cal) := TBUF_DO(fbuf_ibf_cal);
idout(fdat_ibf_line) := TBUF_DO(fbuf_ibf_line);
idout(fdat_ibf_data) := TBUF_DO(fbuf_ibf_data);
if ibrd = '1' then -- fifo read
if TBUF_EMPTY = '0' then -- fifo not empty
itbufce := '1'; -- read from fifo
itbufwe := '0';
else -- read from empty fifo
iback := '0'; -- signal nak
end if;
end if;
if ibwr = '1' then -- fifo write
if RBUF_FULL = '0' then -- fifo not full
if r.mse='1' and r.maint='0' then -- running and not in maint
if r.rxon(toint(IB_MREQ.din(fdat_ibf_line))) = '1' then
irbufce := '1'; -- write to fifo
irbufwe := '1'; -- with default irbufdi
else
-- usually the backend is woken up to send more data by an
-- attn send when the last RBUF value is read. When all
-- data is dropped that never happens. So send an attn
-- when a value is dropped and the RBUF is empty.
if RBUF_EMPTY = '0' then -- for drop on empty fifo
ilam := '1'; -- ask for more data
end if;
end if;
end if;
else -- write to full fifo
iback := '0'; -- signal nak
end if;
end if;
when others => null;
end case; -- IB_MREQ.addr
else -- cpu view: loc side access -------
case IB_MREQ.addr(2 downto 1) is
when ibaddr_csr => -- CSR -- control/status -------
idout(csr_ibf_trdy) := r.trdy;
idout(csr_ibf_tie) := r.tie;
idout(csr_ibf_sa) := r.sa;
idout(csr_ibf_sae) := r.sae;
idout(csr_ibf_tline) := r.tline;
idout(csr_ibf_rdone) := r.rdone;
idout(csr_ibf_rie) := r.rie;
idout(csr_ibf_mse) := r.mse;
idout(csr_ibf_clr) := r.clr;
idout(csr_ibf_maint) := r.maint;
if ibw1 = '1' then
n.tie := IB_MREQ.din(csr_ibf_tie);
if IB_MREQ.din(csr_ibf_tie) = '1' then
if r.tie='0' and r.trdy='1' then -- tie 0->1 and trdy
n.rintreq := '1'; -- request interrupt
end if;
else
n.tintreq := '0';
end if;
n.sae := IB_MREQ.din(csr_ibf_sae);
if IB_MREQ.din(csr_ibf_sae) = '1' then
n.sam := '1';
end if;
end if;
if ibw0 = '1' then
n.rie := IB_MREQ.din(csr_ibf_rie);
if IB_MREQ.din(csr_ibf_rie) = '1' then
if r.rie='0' and -- rie 0->1
((r.sae='0' and r.rdone='1') or -- and no silo and rdone
(r.sae='1' and r.sa='1')) -- or silo and alarm
then
n.rintreq := '1';
end if;
else
n.rintreq := '0';
end if;
n.mse := IB_MREQ.din(csr_ibf_mse);
if IB_MREQ.din(csr_ibf_mse) = '0' then -- mse clear
n.rdone := '0';
n.trdy := '0';
end if;
if r.mse /= IB_MREQ.din(csr_ibf_mse) then -- mse change
n.qcsr := '1';
end if;
if IB_MREQ.din(csr_ibf_clr) = '1' then -- clr set ?
n.clr := '1'; -- request clr
n.qclr := '1'; -- queue clr cal
end if;
n.maint := IB_MREQ.din(csr_ibf_maint);
if r.maint /= IB_MREQ.din(csr_ibf_maint) then -- maint change
n.qcsr := '1';
end if;
end if;
when ibaddr_rbuf_lpr => -- RBUF/LPR ---------------------
idout(rbuf_ibf_val) := r.rdone;
idout(rbuf_ibf_ferr) := RBUF_DO(fbuf_ibf_ferr);
idout(rbuf_ibf_line) := RBUF_DO(fbuf_ibf_line);
idout(rbuf_ibf_data) := RBUF_DO(fbuf_ibf_data);
if ibrd = '1' then -- RBUF read
if r.rdone = '1' then
irbufce := '1'; -- read next value from fifo
irbufwe := '0';
if RBUF_FUSE=c_fuse1 and r.maint='0' then -- last val ?
ilam := '1'; -- rri lam
end if;
n.rdone := '0'; -- clear rdone
n.sa := '0'; -- clear silo alarm
n.rintreq := '0'; -- clear interrupt
iscntclr := '1'; -- clear silo count
end if;
end if;
if ibwr = '1' then -- LPR write
n.rxon(toint(IB_MREQ.din(lpr_ibf_line))) :=
IB_MREQ.din(lpr_ibf_rxon);
if r.rxon(toint(IB_MREQ.din(lpr_ibf_line))) /=
IB_MREQ.din(lpr_ibf_rxon) then -- if changed
n.qrxon := '1'; -- queue rxon cal
end if;
end if;
when ibaddr_tcr => -- TCR -- transmit control ---
idout(tcr_ibf_dtr) := r.dtr;
idout(tcr_ibf_lena) := r.lena;
if ibw1 = '1' then -- DTR written
n.dtr := IB_MREQ.din(tcr_ibf_dtr);
if r.dtr /= IB_MREQ.din(tcr_ibf_dtr) then -- if changed
n.qdtr := '1'; -- queue dtr cal
end if;
end if;
if ibw0 = '1' then -- LENA written
n.lena := IB_MREQ.din(tcr_ibf_lena);
-- check if ready and active line is disabled
if r.trdy = '1' and
IB_MREQ.din(tcr_ibf_lena)(toint(r.tline)) = '0' then
n.trdy := '0'; -- clear ready
n.tintreq := '0'; -- clear interrupt
end if;
end if;
when ibaddr_msr_tdr => -- MSR/TDR ----------------------
idout(msr_ibf_co) := r.co;
idout(msr_ibf_ring) := r.ring;
if ibw1 = '1' then -- BRK written
n.brk := IB_MREQ.din(tdr_ibf_brk);
if r.brk /= IB_MREQ.din(tdr_ibf_brk) then -- if changed
n.qbrk := '1'; -- queue brk cal
end if;
end if;
if ibw0 = '1' then -- TBUF written
if r.trdy = '1' then -- ignore buf write when rdy=0
n.trdy := '0'; -- clear ready
n.tintreq := '0'; -- clear interrupt
if r.maint = '0' then -- not in maint mode
if TBUF_FULL = '0' then -- fifo not full
itbufce := '1'; -- write to fifo
itbufwe := '1'; -- with default itbufdi
end if;
else -- in maint mode
if RBUF_FULL = '0' then -- fifo not full
if r.rxon(toint(r.tline)) = '1' then -- line enabled ?
irbufce := '1'; -- write to fifo
irbufwe := '1'; -- with default irbufdi
end if;
end if;
end if;
end if;
end if;
when others => null;
end case; -- IB_MREQ.addr
end if; -- IB_MREQ.racc
-- silo counter logic
if iscntclr = '1' then
n.scnt := (others=>'0');
elsif irbufwe = '1' then
if r.scnt(4) = '0' then
n.scnt := slv(unsigned(r.scnt) + 1);
end if;
end if;
else -- ibus not selected -----------------
-- handle rx done, timer and interrupt
if r.sae = '0' then -- silo alarm disabled
if RBUF_EMPTY='0' and RRLIM_BUSY='0' then -- not empty and not busy ?
if r.rdone = '0' then -- rdone not set ?
n.rdone := '1'; -- set rdone
irrlimsta := '1'; -- start timer
if r.rie = '1' then -- rx irupt enabled ?
n.rintreq := '1'; -- request rx irupt
end if;
end if;
end if;
else -- silo alarm enabled
if RBUF_EMPTY = '0' then -- not empty ?
if r.rdone = '0' then -- rdone not set ?
n.rdone := '1'; -- set rdone
if r.scnt(4)='1' and RRLIM_BUSY='0' then -- silo16 and not busy ?
if r.sa = '0' then -- sa not set ?
n.sa := '1'; -- set sa
irrlimsta := '1'; -- start timer
if r.rie = '1' then -- rx irupt enabled ?
n.rintreq := '1'; -- request rx irupt
end if;
end if;
end if;
end if;
end if;
end if; -- else r.sae='0'
-- handle tx ready, tline, timer and interrupt
if r.maint = '0' then
ixbuffull := TBUF_FULL;
else
ixbuffull := RBUF_FULL;
end if;
if ixbuffull='0' and TRLIM_BUSY='0' then -- not full and not busy ?
if (r.qdtr or r.qbrk or r.qrxon or r.qcsr) = '0' then -- no cal queued
if r.mse = '1' and r.trdy = '0' then -- searching ?
if r.lena(toint(r.lcnt)) = '1' then -- line found
n.tline := r.lcnt; -- remember line
n.trdy := '1'; -- set ready
itrlimsta := '1'; -- start timer
if r.tie='1' then
n.tintreq := '1'; -- request interrupt
end if;
end if;
-- incrementing lcnt here ensures that the start point for the next
-- search (n.lcnt) is the line one past the current winner (r.lcnt).
n.lcnt := slv(unsigned(r.lcnt) + 1); -- go for next line
end if;
end if;
end if;
-- handle queue change alerts
if TBUF_FULL = '0' then -- fifo space available ?
itbufdi(fbuf_ibf_cal) := '1';
if r.qdtr = '1' then -- cal DTR pending
n.qdtr := '0';
itbufdi(fbuf_ibf_line) := cal_dtr;
itbufdi(fbuf_ibf_data) := r.dtr;
itbufce := '1';
itbufwe := '1';
elsif r.qbrk = '1' then -- cal BRK pending
n.qbrk := '0';
itbufdi(fbuf_ibf_line) := cal_brk;
itbufdi(fbuf_ibf_data) := r.brk;
itbufce := '1';
itbufwe := '1';
elsif r.qrxon = '1' then -- cal RXON pending
n.qrxon := '0';
itbufdi(fbuf_ibf_line) := cal_rxon;
itbufdi(fbuf_ibf_data) := r.rxon;
itbufce := '1';
itbufwe := '1';
elsif r.qcsr='1' or r.qclr='1' then -- cal CSR pending
n.qcsr := '0';
n.qclr := '0';
itbufdi(fbuf_ibf_line) := cal_csr;
itbufdi(fbuf_ibf_data) := (others=>'0');
itbufdi(csr_ibf_mse) := r.mse;
itbufdi(csr_ibf_clr) := r.qclr;
itbufdi(csr_ibf_maint) := r.maint;
itbufce := '1';
itbufwe := '1';
end if;
end if;
end if; -- else r.ibsel='1'
if itbufce='1' and itbufwe='1' then -- write to tx fifo
if TBUF_EMPTY='1' then -- first write to empty tx fifo
ilam := '1'; -- request attention
end if;
end if;
-- other state changes
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.tintreq := '0';
end if;
N_REGS <= n;
RBUF_RESET <= irbufrst;
RBUF_CE <= irbufce;
RBUF_WE <= irbufwe;
RBUF_DI <= irbufdi;
RRLIM_START <= irrlimsta;
TBUF_RESET <= itbufrst;
TBUF_CE <= itbufce;
TBUF_WE <= itbufwe;
TBUF_DI <= itbufdi;
TRLIM_START <= itrlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.tintreq;
end process proc_next;
end syn;
| gpl-3.0 | fc51943c2c21cefc45c8ca4a21f23ab3 | 0.452328 | 3.808319 | false | false | false | false |
nsensfel/tabellion | data/test/CNE_00100/valid.vhd | 1 | 1,068 | library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0: in std_logic; -- $SOL:0:0$
ip1: in std_logic; -- $SOL:1:0$
ip2: in std_logic;
ip3: in std_logic;
op0: out std_logic;
op1: out std_logic;
op2: out std_logic;
op3: out std_logic
);
end;
architecture RTL of valid is
signal s0: std_logic; -- $SOL:2:0$
signal s1: std_logic; -- $SOL:3:0$
signal s2: std_logic;
signal s3: std_logic;
begin
op0 <= ip1 when (ip0 = '0') else ip2;
process (s1, ip1, s2)
begin
if (ip1 = '0')
then
op0 <= '0';
else
op0 <= s2;
end if;
if (ip1 = '0')
then
op1 <= s1;
else
op1 <= '1';
end if;
end process;
s3 <= s1 when (s0 = '0') else s2;
process (s1, ip1, s2)
begin
if (s1 = '0')
then
op0 <= '0';
else
op0 <= s2;
end if;
if (s1 = '0')
then
op1 <= ip1;
else
op1 <= '1';
end if;
end process;
end architecture;
| apache-2.0 | 05fd1c93c0c7f40aa5c3a78754c8bc54 | 0.464419 | 2.817942 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_vmbox.vhd | 1 | 25,563 | -- $Id: pdp11_vmbox.vhd 1320 2022-11-22 18:52:59Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_vmbox - syn
-- Description: pdp11: virtual memory
--
-- Dependencies: pdp11_mmu
-- pdp11_ubmap
-- ibus/ib_sres_or_4
-- ibus/ib_sres_or_2
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-11-21 1320 1.6.9 rename some rsv->ser; remove obsolete trap_done;
-- 2022-11-18 1317 1.6.8 BUGFIX: correct red/yellow zone boundary
-- 2019-06-22 1170 1.6.7 support membe for em cacc access
-- 2016-05-22 767 1.6.6 don't init N_REGS (vivado fix for fsm inference)
-- 2015-07-03 697 1.6.5 much wider DM_STAT_VM
-- 2015-04-04 662 1.6.4 atowidth now 6 (was 5) to support ibdr_rprm reset
-- 2011-11-18 427 1.6.3 now numeric_std clean
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
-- 2010-10-17 333 1.6 implement ibus V2 interface
-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
-- from CP_ADDR; now all ibr handling via vmbox
-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
-- 2008-03-02 121 1.3.1 remove snoopers
-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
-- 2008-01-05 110 1.1.3 update snooper.
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
-- all status into regs_type. add intbus HOLD support.
-- 2007-12-30 108 1.1.1 use ubf_byte[01]
-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
-- 2nd port was unused, connected ADDR caused slow net
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
CRESET : in slbit; -- cpu reset
BRESET : in slbit; -- bus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end pdp11_vmbox;
architecture syn of pdp11_vmbox is
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
constant atowidth : natural := 6; -- size of access timeout counter
-- ! rbus tout must be > ibus tout !
-- ! ensure all BTOWIDTH > atowidth !
type state_type is (
s_idle, -- s_idle: wait for vm_cntl request
s_mem_w, -- s_mem_w: check mmu, wait for memory
s_ib_w, -- s_ib_w: wait for ibus
s_ib_wend, -- s_ib_wend: ibus write completion
s_ib_rend, -- s_ib_rend: ibus read completion
s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
s_fail, -- s_fail: vmbox fatal error catcher
s_errrsv, -- s_errrsv: red stack violation
s_errib -- s_errib: ibus error handler
);
type regs_type is record -- state registers
state : state_type; -- state
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
kstack : slbit; -- access through kernel stack
ysv : slbit; -- yellow stack violation detected
vaok : slbit; -- virtual address valid (from MMU)
trap_mmu : slbit; -- mmu trap requested
mdin : slv16; -- data input (memory order)
paddr : slv22; -- physical address register
paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
atocnt : slv(atowidth-1 downto 0); -- access timeout counter
ibre : slbit; -- ibus re signal
ibwe : slbit; -- ibus we signal
ibbe : slv2; -- ibus be0,be1 signals
ibrmw : slbit; -- ibus rmw signal
ibcacc : slbit; -- ibus cacc signal
ibracc : slbit; -- ibus racc signal
ibdout : slv16; -- ibus dout register
end record regs_type;
constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
s_idle, -- state
'0','0','0','0', -- wacc,macc,cacc,bytop
'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
(others=>'0'), -- mdin
(others=>'0'), -- paddr
(others=>'0'), -- paddr_iopage
atocnt_init, -- atocnt
'0','0',"00", -- ibre,ibwe,ibbe
'0','0','0', -- ibrmw,ibcacc,ibracc
(others=>'0') -- ibdout
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
signal MMU_STAT : mmu_stat_type := mmu_stat_init;
signal PADDRH : slv16 := (others=>'0');
signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
signal UBMAP_MREQ : slbit := '0';
signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
signal VM_STAT_L : vm_stat_type := vm_stat_init; -- vm status (local)
signal VM_DOUT_L : slv16 := (others=>'0'); -- vm data out (local)
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
signal EM_MREQ_L : em_mreq_type := em_mreq_init; -- ext mem: request (local)
begin
MMU : pdp11_mmu
port map (
CLK => CLK,
CRESET => CRESET,
BRESET => BRESET,
CNTL => MMU_CNTL,
VADDR => VM_ADDR,
MONI => MMU_MONI,
STAT => MMU_STAT,
PADDRH => PADDRH,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_MMU
);
UBMAP : pdp11_ubmap
port map (
CLK => CLK,
MREQ => UBMAP_MREQ,
ADDR_UB => CP_ADDR.addr(17 downto 1),
ADDR_PM => UBMAP_ADDR_PM,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_UBMAP
);
SRES_OR_INT : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_CPU,
IB_SRES_2 => IB_SRES_SLIM,
IB_SRES_3 => IB_SRES_MMU,
IB_SRES_4 => IB_SRES_UBMAP,
IB_SRES_OR => IB_SRES_INT
);
SRES_OR_ALL : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_INT,
IB_SRES_2 => IB_SRES_EXT,
IB_SRES_OR => IB_SRES
);
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_slim)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SLIM
);
proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_SLIM = '1' then
idout(ibf_byte1) := R_SLIM;
end if;
IB_SRES_SLIM.dout <= idout;
IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SLIM.busy <= '0';
end process proc_ibres;
proc_slim: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_SLIM <= (others=>'0');
elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_SLIM <= IB_MREQ.din(ibf_byte1);
end if;
end if;
end if;
end process proc_slim;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
IB_SRES, UBMAP_ADDR_PM,
EM_SRES, MMU_STAT, PADDRH)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ivm_stat : vm_stat_type := vm_stat_init;
variable ivm_dout : slv16 := (others=>'0');
variable iem_mreq : em_mreq_type := em_mreq_init;
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
variable ipaddr : slv22 := (others=>'0');
variable ipaddr_iopage : slv9 := (others=>'0');
variable iib_aval : slbit := '0';
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
variable iubmap_mreq : slbit := '0';
variable paddr_mmu : slbit := '0';
variable paddr_sel : slv2 := "00";
constant c_paddr_sel_vmaddr : slv2 := "00";
constant c_paddr_sel_rpaddr : slv2 := "01";
constant c_paddr_sel_cacc : slv2 := "10";
constant c_paddr_sel_ubmap : slv2 := "11";
begin
r := R_REGS;
n := R_REGS;
n.state := s_fail;
ivm_stat := vm_stat_init;
ivm_dout := EM_SRES.dout;
immu_cntl := mmu_cntl_init;
iib_aval := '0';
iem_mreq := em_mreq_init;
iem_mreq.din := VM_DIN;
if VM_CNTL.cacc = '1' then -- if cacc access
iem_mreq.be := CP_ADDR.be; -- use membe setup
elsif VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if VM_ADDR(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
iubmap_mreq :='0';
paddr_mmu := '1'; -- ipaddr selector, used in s_idle
-- and overwritten in s_idle_mw_mem
paddr_sel := "00";
if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
paddr_mmu := '0';
paddr_sel := c_paddr_sel_vmaddr;
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
paddr_sel := c_paddr_sel_ubmap;
else
paddr_sel := c_paddr_sel_cacc;
end if;
end if;
end if;
-- the iopage base is determined based on mmu regs and request type
-- r.paddr_iopage is updated during s_idle. This way the iopage base
-- address is determined in parallel to paddr and latched at end of s_idle.
-- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_22bit = '0' then
ipaddr_iopage := "000000111"; -- 16 bit cacc
end if;
else
if MMU_STAT.ena_mmu = '0' then
ipaddr_iopage := "000000111"; -- 16 bit mode
else
if MMU_STAT.ena_22bit = '0' then
ipaddr_iopage := "000011111"; -- 18 bit mode
end if;
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
is_stackyellow := '0';
is_stackred := '0';
if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
if unsigned(VM_ADDR(15 downto 8)) = unsigned(R_SLIM) and
unsigned(VM_ADDR(7 downto 5)) = 7 then
is_stackyellow := '1';
else
is_stackred := '1';
end if;
end if;
if VM_ADDR(15 downto 1) = "111111111111111" then -- PSW protection
is_stackred := '1';
end if;
immu_cntl.wacc := VM_CNTL.wacc;
immu_cntl.macc := VM_CNTL.macc;
immu_cntl.cacc := VM_CNTL.cacc;
immu_cntl.dspace := VM_CNTL.dspace;
immu_cntl.mode := VM_CNTL.mode;
case r.state is
when s_idle => -- s_idle: wait for vm_cntl request --
n.state := s_idle;
iubmap_mreq := '1'; -- activate ubmap always in s_idle
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.cacc := VM_CNTL.cacc;
n.bytop := VM_CNTL.bytop;
n.kstack := VM_CNTL.kstack;
n.ysv := '0';
n.vaok := MMU_STAT.vaok;
n.trap_mmu := MMU_STAT.trap;
n.mdin := iem_mreq.din;
-- n.paddr assignment handled separately in 'if state=s_idle' at the
-- end.
immu_cntl.req := '1';
if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
n.state := s_fail;
elsif VM_CNTL.kstack='1' and VM_CNTL.vecser='0' and
is_stackred='1' then
n.state := s_errrsv;
else
iem_mreq.req := '1';
iem_mreq.we := VM_CNTL.wacc;
if VM_CNTL.kstack='1' and VM_CNTL.vecser='0' then
n.ysv := is_stackyellow;
end if;
n.state := s_mem_w;
end if;
end if;
when s_mem_w => -- s_mem_w: check mmu, wait for memory
if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
ivm_stat.err := '1';
ivm_stat.err_odd := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
elsif r.vaok = '0' then -- MMU abort ?
ivm_stat.err := '1';
ivm_stat.err_mmu := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if r.paddr(21 downto 13) = r.paddr_iopage then
-- I/O page decoded
iem_mreq.cancel := '1'; -- cancel pending mem request
iib_aval := '1'; -- declare ibus addr valid
n.ibre := not r.wacc;
n.ibwe := r.wacc;
n.ibcacc := r.cacc;
n.ibracc := r.cacc and CP_ADDR.racc;
n.ibbe := "11";
if r.cacc = '1' then -- console access ?
n.ibbe := CP_ADDR.be;
else -- cpu access ?
if r.bytop = '1' then
if r.paddr(0) = '0' then
n.ibbe(1) := '0';
else
n.ibbe(0) := '0';
end if;
end if;
end if;
n.ibrmw := r.macc;
n.state := s_ib_w;
else
if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
ivm_stat.err := '1';
ivm_stat.err_nxm := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
iem_mreq.cancel := '1'; -- cancel pending mem request
n.state := s_idle;
else
if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
ivm_stat.ack := '1';
ivm_stat.trap_ysv := r.ysv;
ivm_stat.trap_mmu := r.trap_mmu;
if r.macc='1' and r.wacc='0' then
n.state := s_idle_mw_mem;
else
n.state := s_idle;
end if;
else
n.state := s_mem_w; -- keep waiting
end if;
end if;
end if;
end if;
when s_ib_w => -- s_ib_w: wait for ibus -------------
ato_go := '1'; -- activate timeout counter
iib_aval := '1'; -- declare ibus addr valid
n.ibre := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
n.ibrmw := '0';
n.ibbe := "00";
n.ibcacc := '0';
n.ibracc := '0';
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
if r.wacc = '1' then
n.state := s_ib_wend;
else
if r.macc = '1' then -- if first part of rmw
n.ibrmw := r.macc; -- keep rmw
n.ibbe := r.ibbe; -- keep be's
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
end if;
n.ibdout := IB_SRES.dout;
n.state := s_ib_rend;
end if;
elsif IB_SRES.busy='1' and ato_end='0' then
n.ibre := r.ibre; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibrmw := r.ibrmw;
n.ibbe := r.ibbe;
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
n.state := s_ib_w;
else
n.state := s_errib;
end if;
when s_ib_wend => -- s_ib_wend: ibus write completion --
ivm_stat.ack := '1';
n.state := s_idle;
when s_ib_rend => -- s_ib_rend: ibus read completion ---
ivm_stat.ack := '1';
ivm_dout := r.ibdout;
if r.macc='1' then -- first part of read-mod-write
iib_aval := '1'; -- keep ibus addr valid
n.state := s_idle_mw_ib;
else
n.state := s_idle;
end if;
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
n.state := s_idle_mw_ib;
iib_aval := '1'; -- keep ibus addr valid
if r.ibbe = "10" then
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
n.ibwe := '1'; -- Note: all other ibus drivers
-- already set in 1st part
n.state := s_ib_w;
end if;
end if;
when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
n.state := s_idle_mw_mem;
paddr_mmu := '0';
paddr_sel := c_paddr_sel_rpaddr;
if VM_CNTL.bytop = '0' then -- if word access
iem_mreq.be := "11"; -- both be's
else
if r.paddr(0) = '0' then -- if low byte
iem_mreq.be := "01";
else -- if high byte
iem_mreq.be := "10";
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
end if;
if VM_CNTL.req = '1' then
n.wacc := VM_CNTL.wacc;
n.macc := VM_CNTL.macc;
n.bytop := VM_CNTL.bytop;
n.mdin := iem_mreq.din;
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
iem_mreq.req := '1';
iem_mreq.we := '1';
n.state := s_mem_mw_w;
end if;
end if;
when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
if EM_SRES.ack_w = '1' then
ivm_stat.ack := '1';
n.state := s_idle;
else
n.state := s_mem_mw_w; -- keep waiting
end if;
when s_fail => -- s_fail: vmbox fatal error catcher
ivm_stat.fail := '1';
n.state := s_idle;
when s_errrsv => -- s_errrsv: red stack violation -----
ivm_stat.err := '1';
ivm_stat.err_rsv := '1';
n.state := s_idle;
when s_errib => -- s_errib: ibus error handler -------
ivm_stat.err := '1';
ivm_stat.err_iobto := '1';
ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
n.state := s_idle;
when others => null;
end case;
if r.bytop='1' and r.paddr(0)='1' then
ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
end if;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
ipaddr := (others=>'0');
if paddr_mmu = '1' then
ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
ipaddr(21 downto 6) := PADDRH;
if MMU_STAT.ena_22bit = '0' then
ipaddr(21 downto 18) := (others=>'0');
end if;
else
case paddr_sel is
when c_paddr_sel_vmaddr =>
ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
when c_paddr_sel_rpaddr =>
ipaddr := r.paddr;
when c_paddr_sel_cacc =>
ipaddr := CP_ADDR.addr & '0';
if CP_ADDR.ena_22bit = '0' then
ipaddr(21 downto 16) := (others=>'0');
end if;
when c_paddr_sel_ubmap =>
ipaddr := UBMAP_ADDR_PM & '0';
when others => null;
end case;
end if;
if r.state = s_idle then
n.paddr := ipaddr;
n.paddr_iopage := ipaddr_iopage;
end if;
iem_mreq.addr := ipaddr(21 downto 1);
N_REGS <= n;
UBMAP_MREQ <= iubmap_mreq;
IB_MREQ.aval <= iib_aval;
IB_MREQ.re <= r.ibre;
IB_MREQ.we <= r.ibwe;
IB_MREQ.be0 <= r.ibbe(0);
IB_MREQ.be1 <= r.ibbe(1);
IB_MREQ.rmw <= r.ibrmw;
IB_MREQ.cacc <= r.ibcacc;
IB_MREQ.racc <= r.ibracc;
IB_MREQ.addr <= r.paddr(12 downto 1);
IB_MREQ.din <= r.mdin;
VM_STAT_L <= ivm_stat;
VM_DOUT_L <= ivm_dout;
MMU_CNTL <= immu_cntl;
EM_MREQ_L <= iem_mreq;
end process proc_next;
VM_STAT <= VM_STAT_L;
VM_DOUT <= VM_DOUT_L;
IB_MREQ_M <= IB_MREQ; -- external drive master port
EM_MREQ <= EM_MREQ_L;
DM_STAT_VM.vmcntl <= VM_CNTL;
DM_STAT_VM.vmaddr <= VM_ADDR;
DM_STAT_VM.vmdin <= VM_DIN;
DM_STAT_VM.vmstat <= VM_STAT_L;
DM_STAT_VM.vmdout <= VM_DOUT_L;
DM_STAT_VM.ibmreq <= IB_MREQ;
DM_STAT_VM.ibsres <= IB_SRES;
DM_STAT_VM.emmreq <= EM_MREQ_L;
DM_STAT_VM.emsres <= EM_SRES;
end syn;
| gpl-3.0 | d8b43b8fef09fceff574bf6376718852 | 0.482807 | 3.433118 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibd_kw11p.vhd | 1 | 11,991 | -- $Id: ibd_kw11p.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_kw11p - syn
-- Description: ibus dev(loc): KW11-P (programmable line clock)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2-2018.2; ghdl 0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2018-09-09 1043 14.7 131013 xc6slx16-2 61 110 0 42 s 6.2
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-24 1138 1.1 add csr.ir; add rem controllable options for
-- RATE=11: sysclk, 1 Mhz, extevt, none
-- 2018-09-09 1043 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_kw11p is -- ibus dev(loc): KW11-P (line clock)
-- fixed address: 172540
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
EXTEVT : in slbit; -- external event for RATE="11"
CPUSUSP : in slbit; -- cpu suspended
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibd_kw11p;
architecture syn of ibd_kw11p is
constant ibaddr_kw11p : slv16 := slv(to_unsigned(8#172540#,16));
constant ibaddr_csr : slv2 := "00"; -- csr address offset
constant ibaddr_csb : slv2 := "01"; -- csb address offset
constant ibaddr_ctr : slv2 := "10"; -- ctr address offset
constant csr_ibf_err : integer := 15;
constant csr_ibf_ir : integer := 10;
subtype csr_ibf_erate is integer range 9 downto 8;
constant csr_ibf_done : integer := 7;
constant csr_ibf_ie : integer := 6;
constant csr_ibf_fix : integer := 5;
constant csr_ibf_updn : integer := 4;
constant csr_ibf_mode : integer := 3;
subtype csr_ibf_rate is integer range 2 downto 1;
constant csr_ibf_run : integer := 0;
constant rate_100k : slv2 := "00";
constant rate_10k : slv2 := "01";
constant rate_line : slv2 := "10";
constant rate_ext : slv2 := "11";
constant erate_sclk : slv2 := "00";
constant erate_usec : slv2 := "01";
constant erate_ext : slv2 := "10";
constant erate_noop : slv2 := "11";
constant dwidth : natural := 4; -- decade divider
constant ddivide : natural := 10;
constant lwidth : natural := 5; -- msec -> 50 Hz divider
constant ldivide : natural := 20;
constant ctrzero : slv16 := (others=>'0');
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
erate : slv2; -- ext rate mode
err : slbit; -- re-interrupt error
done : slbit; -- counter wrap occured
ie : slbit; -- interrupt enable
updn : slbit; -- 0=count-down; 1=count-up
mode : slbit; -- 0=single; 1=repeated interrupt
rate : slv2; -- 00=100kHz;01=10kHz;10=line;11=event
run : slbit; -- enable counter
csb : slv16; -- interval count
ctr : slv16; -- clock counter
intreq : slbit; -- interrupt request
lcnt : slv(lwidth-1 downto 0); -- line clock divider
d1cnt : slv(dwidth-1 downto 0); -- usec -> 100 kHz divider
d2cnt : slv(dwidth-1 downto 0); -- 100->10 kHz divider
evt100k : slbit; -- evt flag: 100 kHz
evt10k : slbit; -- evt flag: 10 kHz
evtline : slbit; -- evt flag: line clock
evtext : slbit; -- evt flag: external event
evtfix : slbit; -- evt flag: csr FIX
evtload : slbit; -- evt flag: load from csb
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"00", -- erate
'0','0','0','0','0', -- err,done,ie,updn,mode
"00",'0', -- rate,run
(others=>'0'), -- csb
(others=>'0'), -- ctr
'0', -- intreq
(others=>'0'), -- lcnt
(others=>'0'), -- d1cnt
(others=>'0'), -- d2cnt
'0','0','0','0', -- evt100k,evt10k,evtline,evyevt
'0','0' -- evtfix,evtload
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.erate <= N_REGS.erate; -- keep ERATE field
R_REGS.lcnt <= N_REGS.lcnt; -- don't clear clock dividers
R_REGS.d1cnt <= N_REGS.d1cnt; -- "
R_REGS.d2cnt <= N_REGS.d2cnt; -- "
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, CE_USEC, CE_MSEC,
EXTEVT, CPUSUSP, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibwr : slbit := '0';
variable ievt : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibwr := IB_MREQ.we;
ievt := '0';
n.evtext := '0';
case r.erate is
when erate_sclk => n.evtext := '1';
when erate_usec => n.evtext := CE_USEC;
when erate_ext => n.evtext := EXTEVT;
when erate_noop => n.evtext := '0';
when others => null;
end case;
n.evt100k := '0'; -- one shot
n.evt10k := '0'; -- one shot
n.evtline := '0'; -- one shot
n.evtfix := '0'; -- one shot
n.evtload := '0'; -- one shot
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_kw11p(12 downto 3) and -- is in 17254*
IB_MREQ.addr(2 downto 1) /= "11" then -- is not *****6
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel='1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_csr => -- CSR -- control and status ---------
idout(csr_ibf_err) := r.err;
idout(csr_ibf_done) := r.done;
idout(csr_ibf_ie) := r.ie;
idout(csr_ibf_updn) := r.updn;
idout(csr_ibf_mode) := r.mode;
idout(csr_ibf_rate) := r.rate;
idout(csr_ibf_run) := r.run;
if ibrd='1' then
n.err := '0'; -- err is read and clear
n.done := '0'; -- done is read and clear
end if;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibwr = '1' then
n.evtfix := IB_MREQ.din(csr_ibf_fix);
n.ie := IB_MREQ.din(csr_ibf_ie);
n.updn := IB_MREQ.din(csr_ibf_updn);
n.mode := IB_MREQ.din(csr_ibf_mode);
n.rate := IB_MREQ.din(csr_ibf_rate);
n.run := IB_MREQ.din(csr_ibf_run);
if IB_MREQ.din(csr_ibf_ie)='0' then
n.intreq := '0';
end if;
end if;
else -- rri ---------------------
idout(csr_ibf_ir) := r.intreq;
idout(csr_ibf_erate) := r.erate;
if ibwr = '1' then
n.erate := IB_MREQ.din(csr_ibf_erate);
end if;
end if;
when ibaddr_csb => -- CSB -- count set buffer -----------
idout := (others=>'0'); -- csb is not readable, return zero !
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibwr = '1' then
n.csb := IB_MREQ.din;
n.evtload := '1';
end if;
end if;
when ibaddr_ctr => -- CTR -- counter --------------------
idout := r.ctr;
when others => null;
end case;
end if;
-- other state changes
-- clock dividers
if CPUSUSP='0' then -- advance if not suspended
if CE_MSEC='1' then -- on msec
n.lcnt := slv(unsigned(r.lcnt) + 1);
if unsigned(r.lcnt) = ldivide-1 then
n.lcnt := (others=>'0');
n.evtline := '1';
end if;
end if;
if CE_USEC='1' then -- on usec
n.d1cnt := slv(unsigned(r.d1cnt) + 1);
if unsigned(r.d1cnt) = ddivide-1 then
n.d1cnt := (others=>'0');
n.evt100k := '1';
n.d2cnt := slv(unsigned(r.d2cnt) + 1);
if unsigned(r.d2cnt) = ddivide-1 then
n.d2cnt := (others=>'0');
n.evt10k := '1';
end if;
end if;
end if;
end if;
-- counter logic
-- select source
if r.run='1' then
case r.rate is
when rate_100k => ievt := r.evt100k;
when rate_10k => ievt := r.evt10k;
when rate_line => ievt := r.evtline;
when rate_ext => ievt := r.evtext;
when others => null;
end case;
else
ievt := r.evtfix;
end if;
-- load or action
if r.evtload='1' then -- load
n.ctr := r.csb;
else -- action
if ievt='1' then -- count event ?
if r.updn='0' then -- count-down
n.ctr := slv(unsigned(r.ctr) - 1);
else -- count-up
n.ctr := slv(unsigned(r.ctr) + 1);
end if;
if n.ctr=ctrzero then -- zero reached ?
n.done := '1'; -- set done
if r.done='1' then -- already done
n.err := '1'; -- set error
end if;
if r.ie = '1' then -- interrupt enabled ?
n.intreq := '1';
end if;
if r.mode='1' then -- mode: repeat
n.ctr := r.csb;
else -- mode: single shot
n.csb := ctrzero;
n.run := '0';
end if;
end if;
end if; -- if ievt='1'
end if; -- if r.evtload='1'
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
EI_REQ <= r.intreq;
end process proc_next;
end syn;
| gpl-3.0 | 1266595f3d8ac22cc50d592ad8ea0c91 | 0.443666 | 3.726227 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4/tb/sys_conf1_sim.vhd | 1 | 2,204 | -- $Id: sys_conf1_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop1_n4 (for test bench)
--
-- Dependencies: -
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-27 753 1.1 clock now from cmt and configurable
-- 2015-02-21 649 1.0 Initial version (cloned from sys_tst_serloop1_n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to
-- 240 cycles (2 usec). This affects mainly the autobauder. A break will be
-- detected after 128 msec periods, this in simulation after 256 usec or
-- 30720 cycles. This is compatible with bitrates of 115200 baud or higher
-- (115200 <-> 8.68 usec <-> 1040 cycles)
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkdiv_msecdiv : integer := 2; -- shortened !!
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure serport ------------------------------------------------------
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 | 42f76f4ca584296e306ae4fbc0da7b51 | 0.566243 | 4.073937 | false | true | false | false |
wfjm/w11 | rtl/ibus/ibdr_minisys.vhd | 1 | 7,113 | -- $Id: ibdr_minisys.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_minisys - syn
-- Description: ibus(rem) devices for minimal system:SDR+KW+DL+RK
--
-- Dependencies: ib_rlim_gen
-- ibdr_sdreg
-- ibd_kw11l
-- ibdr_dl11
-- ibdr_rk11
-- ib_sres_or_4
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 128 469 16 265 s 7.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 122 472 16 269 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-23 1136 1.1.5 add CLK port to ib_intmap
-- 2019-04-14 1131 1.1.4 ib_rlim_gen has CPUSUSP port; RLIM_CEV now slv8
-- 2019-04-07 1129 1.1.3 ibdr_dl11: use RLIM_CEV, drop CE_USEC
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
-- to _dl11
-- 2009-05-31 221 1.0.6 add RESET to kw11l;
-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC
-- 2008-08-22 161 1.0.4 use iblib, ibdlib
-- 2008-05-09 144 1.0.3 use EI_ACK with _kw11l, _dl11
-- 2008-04-18 136 1.0.2 add RESET port, use for ibdr_sdreg
-- 2008-01-20 113 1.0.1 RRI_LAM now vector
-- 2008-01-20 112 1.0 Initial version
------------------------------------------------------------------------------
--
-- mini system setup
--
-- ibbase vec pri slot attn device name
--
-- 177546 100 6 4 - KW11-L
-- 177400 220 5 3 4 RK11
-- 177560 060 4 2 1 DL11-RX 1st
-- 064 4 1 ^ DL11-TX 1st
-- 177570 - - - - sdreg
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end ibdr_minisys;
architecture syn of ibdr_minisys is
constant conf_intmap : intmap_array_type :=
(intmap_init, -- line 15
intmap_init, -- line 14
intmap_init, -- line 13
intmap_init, -- line 12
intmap_init, -- line 11
intmap_init, -- line 10
intmap_init, -- line 9
intmap_init, -- line 8
intmap_init, -- line 7
intmap_init, -- line 6
intmap_init, -- line 5
(8#100#,6), -- line 4 KW11-L
(8#220#,5), -- line 3 RK11
(8#060#,4), -- line 2 DL11-RX
(8#064#,4), -- line 1 DL11-TX
intmap_init -- line 0
);
signal RB_LAM_DL11 : slbit := '0';
signal RB_LAM_RK11 : slbit := '0';
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
signal IB_SRES_DL11 : ib_sres_type := ib_sres_init;
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
signal EI_REQ : slv16_1 := (others=>'0');
signal EI_ACK : slv16_1 := (others=>'0');
signal EI_REQ_KW11L : slbit := '0';
signal EI_REQ_DL11RX : slbit := '0';
signal EI_REQ_DL11TX : slbit := '0';
signal EI_REQ_RK11 : slbit := '0';
signal EI_ACK_KW11L : slbit := '0';
signal EI_ACK_DL11RX : slbit := '0';
signal EI_ACK_DL11TX : slbit := '0';
signal EI_ACK_RK11 : slbit := '0';
signal RLIM_CEV : slv8 := (others=>'0');
begin
RLIM : ib_rlim_gen
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => '0',
CPUSUSP => '0',
RLIM_CEV => RLIM_CEV
);
SDREG : ibdr_sdreg
port map (
CLK => CLK,
RESET => RESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SDREG,
DISPREG => DISPREG
);
KW11L : ibd_kw11l
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
BRESET => BRESET,
CPUSUSP => '0',
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_KW11L,
EI_REQ => EI_REQ_KW11L,
EI_ACK => EI_ACK_KW11L
);
DL11 : ibdr_dl11
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RLIM_CEV => RLIM_CEV,
RB_LAM => RB_LAM_DL11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11,
EI_REQ_RX => EI_REQ_DL11RX,
EI_REQ_TX => EI_REQ_DL11TX,
EI_ACK_RX => EI_ACK_DL11RX,
EI_ACK_TX => EI_ACK_DL11TX
);
RK11 : ibdr_rk11
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RB_LAM => RB_LAM_RK11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RK11,
EI_REQ => EI_REQ_RK11,
EI_ACK => EI_ACK_RK11
);
SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_SDREG,
IB_SRES_2 => IB_SRES_KW11L,
IB_SRES_3 => IB_SRES_DL11,
IB_SRES_4 => IB_SRES_RK11,
IB_SRES_OR => IB_SRES
);
INTMAP : ib_intmap
generic map (
INTMAP => conf_intmap)
port map (
CLK => CLK,
EI_REQ => EI_REQ,
EI_ACKM => EI_ACKM,
EI_ACK => EI_ACK,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT
);
EI_REQ(4) <= EI_REQ_KW11L;
EI_REQ(3) <= EI_REQ_RK11;
EI_REQ(2) <= EI_REQ_DL11RX;
EI_REQ(1) <= EI_REQ_DL11TX;
EI_ACK_KW11L <= EI_ACK(4);
EI_ACK_RK11 <= EI_ACK(3);
EI_ACK_DL11RX <= EI_ACK(2);
EI_ACK_DL11TX <= EI_ACK(1);
RB_LAM(1) <= RB_LAM_DL11;
RB_LAM(2) <= '0'; -- for 2nd DL11
RB_LAM(3) <= '0'; -- for DZ11
RB_LAM(4) <= RB_LAM_RK11;
RB_LAM(15 downto 5) <= (others=>'0');
end syn;
| gpl-3.0 | 022cca1b2634147d06a3f1805dd988ea | 0.477295 | 3.059355 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/spi_master_slave/spi_master_slave_tb.vhd | 1 | 1,749 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
entity tb is
end tb;
architecture tb of tb is
signal clock, reset, we, valid, spi_ssn, spi_clk_i, spi_clk_o, spi_mosi, spi_miso: std_logic := '0';
signal input, output: std_logic_vector(7 downto 0);
signal clk_div: std_logic_vector(2 downto 0);
begin
reset <= '0', '1' after 5 ns, '0' after 500 ns;
process --25Mhz system clock
begin
clock <= not clock;
wait for 20 ns;
clock <= not clock;
wait for 20 ns;
end process;
spi_ssn <= '1', '0' after 5600 ns, '1' after 10000 ns;
we <= '0', '1' after 1002 ns, '0' after 4600 ns;
spi_miso <= '0', '1' after 2460 ns, '0' after 3000 ns, '1' after 6050 ns, '1' after 6250 ns, '1' after 6450 ns, '1' after 6650 ns, '0' after 6850 ns, '0' after 7050 ns, '0' after 7250 ns, '0' after 7450 ns, '1' after 7650 ns, '1' after 7850 ns, '0' after 8050 ns, '0' after 8250 ns, '0' after 8450 ns, '0' after 8650 ns, '1' after 8850 ns, '1' after 9050 ns;
spi_clk_i <= '0', '1' after 6100 ns, '0' after 6300 ns, '1' after 6500 ns, '0' after 6700 ns, '1' after 6900 ns, '0' after 7100 ns, '1' after 7300 ns, '0' after 7500 ns, '1' after 7700 ns, '0' after 7900 ns, '1' after 8100 ns, '0' after 8300 ns, '1' after 8500 ns, '0' after 8700 ns, '1' after 8900 ns, '0' after 9100 ns;
input <= x"a1";
clk_div <= "001";
spi_core: entity work.spi_master_slave
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clock,
rst_i => reset,
data_i => input,
data_o => output,
data_valid_o => valid,
wren_i => we,
clk_div_i => clk_div,
spi_ssn_i => spi_ssn,
spi_clk_i => spi_clk_i,
spi_clk_o => spi_clk_o,
spi_do_o => spi_mosi,
spi_di_i => spi_miso
);
end tb;
| gpl-2.0 | 13eda38d2185d10e59bb04aaf24fe40c | 0.61578 | 2.425798 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/uart/uart.vhd | 1 | 3,743 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity uart is
port( clk : in std_logic;
reset : in std_logic;
divisor : in std_logic_vector(11 downto 0);
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic
);
end;
architecture logic of uart is
signal delay_write_reg : std_logic_vector(11 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(11 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(8 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(7 downto 0);
signal uart_read2 : std_logic;
begin
uart_proc:
process(clk, reset, enable_read, enable_write, data_in, data_write_reg, bits_write_reg,
delay_write_reg, data_read_reg, bits_read_reg, delay_read_reg, data_save_reg,
read_value_reg, uart_read2, busy_write_sig, uart_read)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= x"00" & '1';
bits_write_reg <= "0000";
delay_write_reg <= (others => '0');
read_value_reg <= (others => '1');
data_read_reg <= (others => '0');
bits_read_reg <= "0000";
delay_read_reg <= (others => '0');
data_save_reg <= (others => '0');
elsif clk'event and clk = '1' then
-- UART write
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= (others => '0'); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
if delay_write_reg /= divisor then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= (others => '0'); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
-- average uart_read signal
if uart_read = '1' then
if read_value_reg /= x"ff" then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= x"00" then
read_value_reg <= read_value_reg - 1;
end if;
end if;
-- UART read
if delay_read_reg = x"0000" then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & divisor(11 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= divisor; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
if bits_read_reg = "0000" and delay_read_reg = divisor then
data_save_reg <= '1' & data_read_reg;
elsif enable_read = '1' then
data_save_reg(8) <= '0'; --data_available
end if;
end if;
if bits_write_reg /= "0000" then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
uart_write <= data_write_reg(0);
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process;
end;
| gpl-2.0 | 30baeabbdf1a25579835bc8c7888765e | 0.615549 | 2.724163 | false | false | false | false |
sjohann81/hf-risc | riscv/sim/hf-riscv_assoc_tb.vhd | 1 | 10,725 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(15 downto 0);
signal gpiob_in, gpiob_out, gpiob_ddr: std_logic_vector(15 downto 0);
signal gpio_sig, gpio_sig2, gpio_sig3: std_logic := '0';
signal data_read_spi: std_logic_vector(31 downto 0);
signal data_mode: std_logic_vector(2 downto 0);
signal burst, wr, rd, we, stall_dly, stall_dly2, stall_spi, spi_sel, spi_cs, spi_cs2, spi_clk, spi_mosi, spi_miso, hold_n, spi_cs_n_s: std_logic := '0';
signal sync_mac_out, sync_mac_in: std_logic_vector(31 downto 0) := x"12345678";
signal sync_mac_en, sync_mac_rst: std_logic;
signal async_mac_out, async_mac_in: std_logic_vector(31 downto 0) := x"87654321";
signal async_mac_en, async_mac_rst: std_logic;
signal de_pause: std_logic_vector(1 downto 0);
signal de_config: std_logic_vector(4 downto 0);
signal de_cde_sel, de_mde_sel_l, de_mde_sel_b: std_logic_vector(3 downto 0);
signal de_cde_ctrl: std_logic_vector(15 downto 0);
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
wait for 100 us;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
end process;
process
begin
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
end process;
gpioa_in <= x"00" & "0000" & gpio_sig & "000";
gpiob_in <= "10000" & gpio_sig3 & "00" & "00000" & gpio_sig2 & "00";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
spi_sel <= '1' when address(31 downto 28) = "0011" else '0';
rd <= '1' when (spi_sel = '1' and data_we = "0000" and stall_dly2 = '0') else '0';
wr <= '1' when (spi_sel = '1' and data_we /= "0000" and stall_dly2 = '0') else '0';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_spi when spi_sel = '1' or stall_dly2 = '1' else
data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
hold_n <= '1';
burst <= '0';
stall_sig <= stall_spi;
-- external SPI SRAM/EEPROM, 0x30000000 (26,25 - spi select, 24 - short address mode, 23 - EEPROM write enable latch)
spi_cs <= spi_cs_n_s when spi_sel = '1' and address(25) = '0' else '1';
-- external SPI SRAM/EEPROM, 0x32000000
spi_cs2 <= spi_cs_n_s when spi_sel = '1' and address(25) = '1' else '1';
we <= address(24) and address(23);
process(clock_in, reset, stall_spi)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
stall_dly <= '0';
stall_dly2 <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
stall_dly <= stall_spi;
stall_dly2 <= stall_dly;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => data_mode,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr,
sync_mac_i => sync_mac_out,
sync_mac_o => sync_mac_in,
sync_mac_en_o => sync_mac_en,
sync_mac_rst_o => sync_mac_rst,
async_mac_i => async_mac_out,
async_mac_o => async_mac_in,
async_mac_en_o => async_mac_en,
async_mac_rst_o => async_mac_rst,
de_pause_o => de_pause,
de_config_o => de_config,
de_cde_sel_o => de_cde_sel,
de_mde_sel_l_o => de_mde_sel_l,
de_mde_sel_b_o => de_mde_sel_b,
de_cde_ctrl_o => de_cde_ctrl
);
sram_ctrl_core: entity work.spi_sram_ctrl
port map( clk_i => clock_in,
rst_i => reset,
addr_i => address(23 downto 0),
data_i => data_write,
data_o => data_read_spi,
burst_i => burst,
bmode_i => data_mode(2),
hmode_i => data_mode(1),
wr_i => wr,
rd_i => rd,
saddr_i => address(24),
wren_i => we,
data_ack_o => open,
cpu_stall_o => stall_spi,
spi_cs_n_o => spi_cs_n_s,
spi_clk_o => spi_clk,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso
);
spi_sram: entity work.M23LC1024
port map( SI_SIO0 => spi_mosi,
SO_SIO1 => spi_miso,
SCK => spi_clk,
CS_N => spi_cs,
SIO2 => open,
HOLD_N_SIO3 => hold_n,
RESET => reset
);
spi_eeprom: entity work.M25LC256
port map( SI => spi_mosi,
SO => spi_miso,
SCK => spi_clk,
CS_N => spi_cs2,
WP_N => hold_n,
HOLD_N => hold_n,
RESET => reset
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(30 downto 24));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"70000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | e776f65e4470256d9c616635a8140f59 | 0.593846 | 2.626745 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd | 1 | 15,127 | -- $Id: sys_w11a_br_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_br_n4d - syn
-- Description: w11a test design for nexys4d (bram only)
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_4line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- w11a/pdp11_bram_memctl
-- vlib/rlink/ioleds_sp1c
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_sys_w11a_br_n4d
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1 3099 5842 267 132.0 1957
-- 2019-05-19 1150 2017.2 xc7a100t-1 3097 6562 273 132.0 2110 +dz11
-- 2019-02-02 1108 2018.3 xc7a100t-1 2837 6083 170 131.5 1957
-- 2019-02-02 1108 2017.2 xc7a100t-1 2825 5843 170 131.5 1824 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a100t-1 2602 5490 138 131.5 1754 +KW11P
-- 2017-05-25 898 2016.4 xc7a100t-1 2541 5500 138 131.5 1750 +DEUNA
-- 2017-01-07 842 2016.4 xc7a100t-1 2491 5335 138 131.5 1728
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.2 use s7_cmt_1ce1ce
-- 2018-10-13 1055 1.1 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-01-04 838 1.0 Initial version (derived from sys_w11a_br_n4)
------------------------------------------------------------------------------
--
-- w11a test design for nexys4d
-- w11a + rlink + serport
--
-- Usage of Nexys 4DDR Switches, Buttons, LEDs
--
-- SWI(15:5): no function (only connected to sn_humanio_rbus)
-- (5): select DSP(7:4) display
-- 0 abclkdiv & abclkdiv_f
-- 1 PC
-- (4): select DSP(3:0) display
-- 0 DISPREG
-- 1 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2): unused-reserved (USB port select)
-- (1): 1 enable XON
-- (0): unused-reserved (serial port select)
--
-- LEDs if SWI(3) = 1
-- (15:0) DR emulation; shows R0 during wait like 11/45+70
--
-- LEDs if SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5)
-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4)
-- DP(3:0) shows IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_br_n4d is -- top level
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_w11a_br_n4d;
architecture syn of sys_w11a_br_n4d is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"08"; -- nexys4d
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_4line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
BRAM_CTL: pdp11_bram_memctl -- memory controller -----------------
generic map (
MAWIDTH => sys_conf_memctl_mawidth,
NBLOCK => sys_conf_memctl_nblock)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => DSP_DP(3 downto 0)
);
DSP_DP(7 downto 4) <= "0010";
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 3)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
-- setup unused outputs in nexys4d
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 9fabdda14476bf2c08653c6ece439e4e | 0.482779 | 3.245441 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/cmoda7/tb/sys_conf_sim.vhd | 1 | 4,736 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_c7 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.1-2018.3; ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.0.2 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.0.1 add sys_conf_ibd_kw11p
-- 2017-06-24 914 1.0 Initial version (cloned from _n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 10;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 512kB memory blocks => 512*16 = 8192 MMU blocks
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural :=
(512*16) + (256*sys_conf_memctl_nblock) - 1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 8; -- 16kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := false; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | d019385e8f7f7efc357257782840cf87 | 0.592272 | 3.631902 | false | true | false | false |
wfjm/w11 | rtl/ibus/ibdr_rhrp.vhd | 1 | 65,903 | -- $Id: ibdr_rhrp.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rhrp - syn
-- Description: ibus dev(rem): RHRP
--
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-06-20 692 14.7 131013 xc6slx16-2 212 406 8 142 s 8.7
-- 2015-05-14 680 14.7 131013 xc6slx16-2 211 408 8 131 s 8.8
-- 2015-04-06 664 14.7 131013 xc6slx16-2 177 331 8 112 s 8.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2015-06-20 692 1.0.3 BUGFIX: fix func-go when drive/init busy checks
-- 2015-06-05 690 1.0.2 use 'not unit' for lsb of rpsn to avoid SI detect
-- BUGFIX: set rmr only for write to busy unit
-- 2015-05-15 682 1.0.1 correct ibsel range select logic
-- 2015-05-14 680 1.0 Initial version
-- 2015-03-15 658 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_rhrp is -- ibus dev(rem): RH+RP
-- fixed address: 176700
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
BRESET : in slbit; -- ibus reset
ITIMER : in slbit; -- instruction timer
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
-- by default xst uses a binary encoding for the main fsm.
-- that give quite sub-optimal results, so force one-hot
attribute fsm_encoding : string;
attribute fsm_encoding of ibdr_rhrp : entity is "one-hot";
end entity ibdr_rhrp;
architecture syn of ibdr_rhrp is
constant ibaddr_rhrp : slv16 := slv(to_unsigned(8#176700#,16));
-- nam rw mb rp rm storage
constant ibaddr_cs1 : slv5 := "00000"; -- cs1 rw 0 rpcs1 rmcs1 m d,6+r
constant ibaddr_wc : slv5 := "00001"; -- wc rw - rpwc rmwc m 0,7
constant ibaddr_ba : slv5 := "00010"; -- ba rw - rpba rmba m 1,7
constant ibaddr_da : slv5 := "00011"; -- da rw 5 rpda rmda m d,0
constant ibaddr_cs2 : slv5 := "00100"; -- cs2 rw - rpcs2 rmcs2 r cs2*
constant ibaddr_ds : slv5 := "00101"; -- ds r- 1 rpds rmds r ds*
constant ibaddr_er1 : slv5 := "00110"; -- er1 rw 2 rper1 rmer1 r er1*
constant ibaddr_as : slv5 := "00111"; -- as rw 4 rpas rmas r as*
constant ibaddr_la : slv5 := "01000"; -- la r- 7 rpla rmla r sc
constant ibaddr_db : slv5 := "01001"; -- db r? - rpdb rmdb m 2,7
constant ibaddr_mr1 : slv5 := "01010"; -- mr1 rw 3 rpmr1 rmmr1 m d,3
constant ibaddr_dt : slv5 := "01011"; -- dt r- 6 rpdt rmdt r dt*+map
constant ibaddr_sn : slv5 := "01100"; -- sn r- 10 rpsn rmsn <map>
constant ibaddr_of : slv5 := "01101"; -- of rw 11 rpof rmof m d,1
constant ibaddr_dc : slv5 := "01110"; -- dc rw 12 rpdc rmdc m d,2
constant ibaddr_m13 : slv5 := "01111"; -- m13 rw 13 rpcc m =dc!
-- rw 13 rmhr m d,4
constant ibaddr_m14 : slv5 := "10000"; -- m14 rw 14 rper2 =0
-- rw 14 rmmr2 m d,5
constant ibaddr_m15 : slv5 := "10001"; -- m15 rw 15 rper3 =0
-- rw 15 rmer2 =0
constant ibaddr_ec1 : slv5 := "10010"; -- ec1 r- 16 rpec1 rmec1 =0
constant ibaddr_ec2 : slv5 := "10011"; -- ec1 r- 17 rpec2 rmec2 =0
constant ibaddr_bae : slv5 := "10100"; -- bae rw - rpbae rmbae r bae
constant ibaddr_cs3 : slv5 := "10101"; -- cs3 rw - rpcs3 rmcs3 r cs3*
constant omux_cs1 : slv4 := "0000";
constant omux_cs2 : slv4 := "0001";
constant omux_ds : slv4 := "0010";
constant omux_er1 : slv4 := "0011";
constant omux_as : slv4 := "0100";
constant omux_la : slv4 := "0101";
constant omux_dt : slv4 := "0110";
constant omux_sn : slv4 := "0111";
constant omux_bae : slv4 := "1000";
constant omux_cs3 : slv4 := "1001";
constant omux_mem : slv4 := "1010";
constant omux_zero : slv4 := "1111";
constant amapc_da : slv3 := "000";
constant amapc_mr1 : slv3 := "011";
constant amapc_of : slv3 := "001";
constant amapc_dc : slv3 := "010";
constant amapc_hr : slv3 := "100";
constant amapc_mr2 : slv3 := "101";
constant amapc_cs1 : slv3 := "110";
constant amapc_ext : slv3 := "111";
constant amapr_wc : slv2 := "00";
constant amapr_ba : slv2 := "01";
constant amapr_db : slv2 := "10";
subtype amap_f_unit is integer range 4 downto 3; -- unit part
subtype amap_f_reg is integer range 2 downto 0; -- reg part
constant clrmode_breset : slv2 := "00";
constant clrmode_cs2clr : slv2 := "01";
constant clrmode_fdclr : slv2 := "10";
constant clrmode_fpres : slv2 := "11";
constant cs1_ibf_sc : integer := 15; -- special condition
constant cs1_ibf_tre : integer := 14; -- transfer error
constant cs1_ibf_dva : integer := 11; -- drive available
subtype cs1_ibf_bae is integer range 9 downto 8; -- bus addr ext (1:0)
constant cs1_ibf_rdy : integer := 7; -- controller ready
constant cs1_ibf_ie : integer := 6; -- interrupt enable
subtype cs1_ibf_func is integer range 5 downto 1; -- function code
constant cs1_ibf_go : integer := 0; -- interrupt enable
constant func_noop : slv5 := "00000"; -- func: noop
constant func_unl : slv5 := "00001"; -- func: unload
constant func_seek : slv5 := "00010"; -- func: seek
constant func_recal : slv5 := "00011"; -- func: recalibrate
constant func_dclr : slv5 := "00100"; -- func: drive clear
constant func_pore : slv5 := "00101"; -- func: port release
constant func_offs : slv5 := "00110"; -- func: offset
constant func_retc : slv5 := "00111"; -- func: return to center
constant func_pres : slv5 := "01000"; -- func: readin preset
constant func_pack : slv5 := "01001"; -- func: pack acknowledge
constant func_sear : slv5 := "01100"; -- func: search
constant func_xfer : slv5 := "10100"; -- used to check for xfer type funcs
constant func_wcd : slv5 := "10100"; -- func: write check data
constant func_wchd : slv5 := "10101"; -- func: write check header&data
constant func_write : slv5 := "11000"; -- func: write
constant func_whd : slv5 := "11001"; -- func: write header&data
constant func_read : slv5 := "11100"; -- func: read
constant func_rhd : slv5 := "11101"; -- func: read header&data
constant rfunc_wunit : slv5 := "00001"; -- rem func: write runit
constant rfunc_cunit : slv5 := "00010"; -- rem func: copy funit->runit
constant rfunc_done : slv5 := "00011"; -- rem func: done (set rdy)
constant rfunc_widly : slv5 := "00100"; -- rem func: write idly
-- cs1 usage for rem functions
subtype cs1_ibf_runit is integer range 9 downto 8; -- new runit (_wunit)
constant cs1_ibf_rata : integer := 8; -- use ata (_done)
subtype cs1_ibf_ridly is integer range 15 downto 8; -- new idly (_widly)
subtype da_ibf_ta is integer range 12 downto 8; -- track addr
subtype da_ibf_sa is integer range 5 downto 0; -- sector addr
constant cs2_ibf_rwco : integer := 15; -- rem: write check odd word
constant cs2_ibf_wce : integer := 14; -- write check error
constant cs2_ibf_ned : integer := 12; -- non-existent drive
constant cs2_ibf_nem : integer := 11; -- non-existent memory
constant cs2_ibf_pge : integer := 10; -- programming error
constant cs2_ibf_mxf : integer := 9; -- missed transfer
constant cs2_ibf_or : integer := 7; -- output ready
constant cs2_ibf_ir : integer := 6; -- input ready
constant cs2_ibf_clr : integer := 5; -- clear controller
constant cs2_ibf_pat : integer := 4; -- parity test
constant cs2_ibf_bai : integer := 3; -- bus address inhibit
constant cs2_ibf_unit2 : integer := 2; -- unit select msb
subtype cs2_ibf_unit is integer range 1 downto 0; -- unit select
constant ds_ibf_ata : integer := 15; -- attention
constant ds_ibf_erp : integer := 14; -- any errors in er1 or er2
constant ds_ibf_pip : integer := 13; -- positioning in progress
constant ds_ibf_mol : integer := 12; -- medium online (ATTACHED)
constant ds_ibf_wrl : integer := 11; -- write locked
constant ds_ibf_lbt : integer := 10; -- last block transfered
constant ds_ibf_dpr : integer := 8; -- drive present (ENABLED)
constant ds_ibf_dry : integer := 7; -- drive ready
constant ds_ibf_vv : integer := 6; -- volume valid
constant ds_ibf_om : integer := 0; -- offset mode
constant er1_ibf_uns : integer := 14; -- drive unsafe
constant er1_ibf_wle : integer := 11; -- write lock error
constant er1_ibf_iae : integer := 10; -- invalid address error
constant er1_ibf_aoe : integer := 9; -- address overflow error
constant er1_ibf_rmr : integer := 2; -- register modification refused
constant er1_ibf_ilf : integer := 0; -- illegal function
subtype la_ibf_sc is integer range 11 downto 6; -- current sector
constant dt_ibf_rm : integer := 2; -- rm cntl
constant dt_ibf_e1 : integer := 1; -- encoded type bit 1
constant dt_ibf_e0 : integer := 0; -- encoded type bit 0
constant dte_rp04 : slv3 := "000"; -- encoded dt for rp04 rm=0
constant dte_rp06 : slv3 := "001"; -- encoded dt for rp06 rm=0
constant dte_rm03 : slv3 := "100"; -- encoded dt for rm03 rm=1
constant dte_rm80 : slv3 := "101"; -- encoded dt for rm80 rm=1
constant dte_rm05 : slv3 := "110"; -- encoded dt for rm05 rm=1
constant dte_rp07 : slv3 := "111"; -- encoded dt for rp07 rm=1
subtype dc_ibf_ca is integer range 9 downto 0; -- cyclinder addr
subtype bae_ibf_bae is integer range 5 downto 0; -- bus addr ext.
constant cs3_ibf_wco : integer := 12; -- write check odd
constant cs3_ibf_wce : integer := 11; -- write check even
constant cs3_ibf_ie : integer := 6; -- interrupt enable
constant cs3_ibf_rseardone : integer := 3; -- rem: sear done flag
constant cs3_ibf_rpackdone : integer := 2; -- rem: pack done flag
constant cs3_ibf_rporedone : integer := 1; -- rem: pore done flag
constant cs3_ibf_rseekdone : integer := 0; -- rem: seek done flag
-- RP controller type disks
constant rp04_dtyp : slv6 := slv(to_unsigned( 8#20#, 6));
constant rp04_camax : slv10 := slv(to_unsigned( 411-1, 10));
constant rp04_tamax : slv5 := slv(to_unsigned( 19-1, 5));
constant rp04_samax : slv6 := slv(to_unsigned( 22-1, 6));
constant rp06_dtyp : slv6 := slv(to_unsigned( 8#22#, 6));
constant rp06_camax : slv10 := slv(to_unsigned( 815-1, 10));
constant rp06_tamax : slv5 := slv(to_unsigned( 19-1, 5));
constant rp06_samax : slv6 := slv(to_unsigned( 22-1, 6));
-- RM controller type disks (Note: rp07 has a RM stype controller!)
constant rm03_dtyp : slv6 := slv(to_unsigned( 8#24#, 6));
constant rm03_camax : slv10 := slv(to_unsigned( 823-1, 10));
constant rm03_tamax : slv5 := slv(to_unsigned( 5-1, 5));
constant rm03_samax : slv6 := slv(to_unsigned( 32-1, 6));
constant rm80_dtyp : slv6 := slv(to_unsigned( 8#26#, 6));
constant rm80_camax : slv10 := slv(to_unsigned( 559-1, 10));
constant rm80_tamax : slv5 := slv(to_unsigned( 14-1, 5));
constant rm80_samax : slv6 := slv(to_unsigned( 31-1, 6));
constant rm05_dtyp : slv6 := slv(to_unsigned( 8#27#, 6));
constant rm05_camax : slv10 := slv(to_unsigned( 823-1, 10));
constant rm05_tamax : slv5 := slv(to_unsigned( 19-1, 5));
constant rm05_samax : slv6 := slv(to_unsigned( 32-1, 6));
constant rp07_dtyp : slv6 := slv(to_unsigned( 8#42#, 6));
constant rp07_camax : slv10 := slv(to_unsigned( 630-1, 10));
constant rp07_tamax : slv5 := slv(to_unsigned( 32-1, 5));
constant rp07_samax : slv6 := slv(to_unsigned( 50-1, 6));
type state_type is (
s_idle, -- idle: handle ibus
s_wcs1, -- wcs1: write cs1
s_wcs2, -- wcs2: write cs2
s_wcs3, -- wcs3: write cs3
s_wer1, -- wer1: write er1 (rem only)
s_was, -- was: write as
s_wdt, -- wdt: write dt (rem only)
s_wds, -- wdt: write ds (rem only)
s_wbae, -- wbae: write bae
s_wmem, -- wmem: write mem (DA,MR1,OF,DC,MR2)
s_wmembe, -- wmem: write mem with be (WC,BA,DB)
s_whr, -- whr: write hr (holding reg only)
s_funcchk, -- funcchk: check function go
s_funcgo, -- funcgo: handle function go
s_chkdc, -- chkdc: handle dc check
s_chkda, -- chksa: handle da check
s_chkdo, -- chkdo: execute function
s_read, -- read: all register reads
s_setrmr, -- set rmr flag
s_oot_clr0, -- OOT clr0: state 0
s_oot_clr1, -- OOT clr1: state 1
s_oot_clr2 -- OOT clr2: state 2
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
amap : slv5; -- mem mapped address
omux : slv4; -- omux select
dinmsk : slv16; -- mbreq.din masked
dtrm : slv4; -- dt: drive rm controller
dte1 : slv4; -- dt: drive type bit 1
dte0 : slv4; -- dt: drive type bit 0
bae : slv6; -- bae: bus addr extension (in cs1&bae)
cs1sc : slbit; -- cs1: special condition
cs1tre : slbit; -- cs1: transfer error
cs1rdy : slbit; -- cs1: controller ready
cs1ie : slbit; -- cs1: interrupt enable
ffunc : slv5; -- func code (frozen on ext func go)
fxfer : slbit; -- func is xfer
cs2wce : slbit; -- cs2: write check error
cs2ned : slbit; -- cs2: non-existent drive
cs2nem : slbit; -- cs2: non-existent memory
cs2pge : slbit; -- cs2: programming error
cs2mxf : slbit; -- cs2: missed transfer
cs2pat : slbit; -- cs2: parity test
cs2bai : slbit; -- cs2: bus address inhibit
cs2unit2: slbit; -- cs2: unit lsb
cs2unit : slv2; -- unit (ibus view)
funit : slv2; -- unit (frozen on ext func go)
runit : slv2; -- unit (remote view)
eunit : slv2; -- unit (effective)
dsata : slv4; -- ds: attention
dserp : slv4; -- ds: error summary (or of er1+er2)
dspip : slv4; -- ds: positioning in progress
dsmol : slv4; -- ds: medium online (ATTACHED)
dswrl : slv4; -- ds: write locked
dslbt : slv4; -- ds: last block transfered
dsdpr : slv4; -- ds: drive present (ENABLED)
dsvv : slv4; -- ds: volume valid
dsom : slv4; -- ds: offset mode
er1uns : slv4; -- er1: dive unsafe
er1wle : slv4; -- er1: write lock error
er1iae : slv4; -- er1: invalid address error
er1aoe : slv4; -- er1: address overflow error
er1rmr : slv4; -- er1: register modificaton refused
er1ilf : slv4; -- er1: illegal function
cs3wco : slbit; -- cs3: write check odd word
idlyval : slv8; -- int delay value
idlycnt : slv8; -- int delay counter
seekdone: slbit; -- cs3 rem: seek done
poredone: slbit; -- cs3 rem: port rel done
packdone: slbit; -- cs3 rem: pack ack done
seardone: slbit; -- cs3 rem: search done
ned : slbit; -- current drive non-existent
cerm : slbit; -- current eff. drive rm controller
dtyp : slv6; -- current drive type (5:0)
camax : slv10; -- current max cylinder address
tamax : slv5; -- current max track address
samax : slv6; -- current max sector address
uscnt : slv7; -- usec counter
sc : slv6; -- current sector counter
clrmode : slv2; -- clear: mode
clrreg : slv3; -- clear: register counter
ireq : slbit; -- interrupt request flag
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
s_idle, -- state
(others=>'0'), -- amap,
(others=>'0'), -- omux,
(others=>'0'), -- dinmsk,
(others=>'0'), -- dtrm
(others=>'0'), -- dte1
(others=>'0'), -- dte0
(others=>'0'), -- bae,
'0','0','1','0', -- cs1sc,cs1tre,cs1rdy,cs1ie
(others=>'0'), -- ffunc
'0', -- fxfer
'0','0','0','0', -- cs2wce,cs2ned,cs2nem,cs2pge
'0','0','0', -- cs2mxf,cs2pat,cs2bai
'0', -- cs2unit2
(others=>'0'), -- cs2unit
(others=>'0'), -- funit
(others=>'0'), -- runit
(others=>'0'), -- eunit
(others=>'0'), -- dsata
(others=>'0'), -- dserp
(others=>'0'), -- dspip
(others=>'0'), -- dsmol
(others=>'0'), -- dswrl
(others=>'0'), -- dslbt
(others=>'0'), -- dsdpr
(others=>'0'), -- dsvv
(others=>'0'), -- dsom
(others=>'0'), -- er1uns
(others=>'0'), -- er1wle
(others=>'0'), -- er1iae
(others=>'0'), -- er1aoe
(others=>'0'), -- er1rmr
(others=>'0'), -- er1ilf
'0', -- cs3wco
x"0a", -- idlyval (default delay=10)
(others=>'0'), -- idlycnt
'0','0','0','0', -- seekdone,poredone,packdone,seardone
'0','0', -- ned,cerm
(others=>'0'), -- dtyp
(others=>'0'), -- camax
(others=>'0'), -- tamax
(others=>'0'), -- samax
(others=>'0'), -- uscnt
(others=>'0'), -- sc
(others=>'0'), -- clrmode
(others=>'0'), -- clrreg
'0' -- ireq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';
signal MEM_ADDR : slv5 := (others=>'0');
signal MEM_DIN : slv16 := (others=>'0');
signal MEM_DOUT : slv16 := (others=>'0');
-- the following is unfortunately not accepted by xst:
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of R_REGS.state : signal is "one-hot";
begin
MEM_1 : ram_1swar_gen
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_1_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte1),
DO => MEM_DOUT(ibf_byte1));
MEM_0 : ram_1swar_gen
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_0_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte0),
DO => MEM_DOUT(ibf_byte0));
proc_regs: process (CLK)
begin
-- BRESET handled in main fsm, not here !!
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, BRESET, ITIMER, IB_MREQ, MEM_DOUT,
EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
variable iei_req : slbit := '0';
variable imem_we0 : slbit := '0';
variable imem_we1 : slbit := '0';
variable imem_addr : slv5 := (others=>'0');
variable imem_din : slv16 := (others=>'0');
variable ieunit : slv2 := (others=>'0');
variable iomux : slv4 := (others=>'0'); -- omux select
variable iamap : slv5 := (others=>'0'); -- mem mapped address
variable imask : slv16 := (others=>'0'); -- implemented bits mask
variable imbreg : slbit := '0'; -- massbus register
variable inormr : slbit := '0'; -- inhibit rmr protect
variable idte : slv3 := (others=>'0'); -- encoded drive type
variable idtyp : slv6 := (others=>'0'); -- drive type (5:0)
variable icamax : slv10 := (others=>'0'); -- max cylinder address
variable itamax : slv5 := (others=>'0'); -- max track address
variable isamax : slv6 := (others=>'0'); -- max sector address
variable ined : slbit := '0'; -- non-existent drive
variable icerm : slbit := '0'; -- effectiv drive is rm
variable iclrreg : slbit := '0'; -- clr enable
variable iscinc : slbit := '0'; -- increment r.sc enable
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
iei_req := '0';
imem_we0 := '0';
imem_we1 := '0';
imem_addr := r.amap; -- default address (from mapper)
imem_din := r.dinmsk; -- default input (from masker)
ieunit := (others=>'0');
iomux := (others=>'0');
iamap := (others=>'0');
imask := (others=>'1'); -- default: all bits ok
imbreg := '0';
inormr := '0';
idte := (others=>'0');
idtyp := (others=>'0');
icamax := (others=>'0');
itamax := (others=>'0');
isamax := (others=>'0');
ined := '0';
icerm := '0';
iclrreg := '0';
iscinc := '0';
-- ibus address decoder, accept only offsets 0 to ibaddr_cs3
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 6) = ibaddr_rhrp(12 downto 6) and
unsigned(IB_MREQ.addr(5 downto 1)) <= unsigned(ibaddr_cs3) then
n.ibsel := '1';
end if;
-- internal state machine
case r.state is
when s_idle => -- idle: handle ibus -----------------
if r.ibsel='1' then -- selected
-- determine effective unit number
if ibrem = '1' then
ieunit := r.runit;
else
ieunit := r.cs2unit;
end if;
n.eunit := ieunit;
-- determine drive properties (always via iunit) FIXME: correct ??
idte(2) := r.dtrm(to_integer(unsigned(r.cs2unit)));
idte(1) := r.dte1(to_integer(unsigned(r.cs2unit)));
idte(0) := r.dte0(to_integer(unsigned(r.cs2unit)));
case idte is
when dte_rp04 => -- RP04
idtyp := rp04_dtyp;
icamax := rp04_camax;
itamax := rp04_tamax;
isamax := rp04_samax;
when dte_rp06 => -- RP06
idtyp := rp06_dtyp;
icamax := rp06_camax;
itamax := rp06_tamax;
isamax := rp06_samax;
when dte_rm03 => -- RM03
idtyp := rm03_dtyp;
icamax := rm03_camax;
itamax := rm03_tamax;
isamax := rm03_samax;
when dte_rm80 => -- RM80
idtyp := rm80_dtyp;
icamax := rm80_camax;
itamax := rm80_tamax;
isamax := rm80_samax;
when dte_rm05 => -- RM05
idtyp := rm05_dtyp;
icamax := rm05_camax;
itamax := rm05_tamax;
isamax := rm05_samax;
when dte_rp07 => -- RP07
idtyp := rp07_dtyp;
icamax := rp07_camax;
itamax := rp07_tamax;
isamax := rp07_samax;
when others =>
idtyp := (others=>'0');
icamax := (others=>'0');
itamax := (others=>'0');
isamax := (others=>'0');
end case; -- case idte
n.dtyp := idtyp;
n.camax := icamax;
n.tamax := itamax;
n.samax := isamax;
-- consider drive non-existent if not 'DPR' or unit>=4 selected
if r.dsdpr(to_integer(unsigned(r.cs2unit))) = '0' or
r.cs2unit2 = '1' then
ined := '1';
end if;
n.ned := ined;
icerm := r.dtrm(to_integer(unsigned(ieunit)));
n.cerm := icerm;
-- setup mapper
case IB_MREQ.addr(5 downto 1) is
when ibaddr_cs1 => -- RxCS1 control reg 1
-- cs1 not flagged mbreg !! ned handling done explicitely
iamap := ieunit & amapc_cs1;
iomux := omux_cs1;
when ibaddr_wc => -- RxWC word count
iamap := amapr_wc & amapc_ext;
iomux := omux_mem;
when ibaddr_ba => -- RxBA bus address
imask := "1111111111111110"; -- lsb ignored
iamap := amapr_ba & amapc_ext;
iomux := omux_mem;
when ibaddr_da => -- RxDA disk address
imask := "0001111100111111"; -- 000t tttt 00ss ssss
iamap := ieunit & amapc_da;
iomux := omux_mem;
imbreg := '1'; -- mb 5
when ibaddr_cs2 => -- RxCS2 control reg 2
iomux := omux_cs2;
when ibaddr_ds => -- RxDS drive status
iomux := omux_ds;
imbreg := '1'; -- mb 1
when ibaddr_er1 => -- RxER1 error status 1
iomux := omux_er1;
imbreg := '1'; -- mb 2
when ibaddr_as => -- RxAS attention summary
iomux := omux_as;
imbreg := '1'; -- mb 4
inormr := '1'; -- AS writes allowed when RDY=0
when ibaddr_la => -- RxLA look ahead
iomux := omux_la;
imbreg := '1'; -- mb 7
when ibaddr_db => -- RxDB data buffer
iamap := amapr_db & amapc_ext;
iomux := omux_mem;
when ibaddr_mr1 => -- RxMR1 maintenance reg 1
iamap := ieunit & amapc_mr1;
iomux := omux_mem;
imbreg := '1'; -- mb 3
inormr := '1'; -- MR1 writes allowed when RDY=0
when ibaddr_dt => -- RxDT drive type
iomux := omux_dt;
imbreg := '1'; -- mb 6
when ibaddr_sn => -- RxSN serial number
iomux := omux_sn;
imbreg := '1'; -- mb 10
when ibaddr_of => -- RxOF offset reg
imask := "0001110011111111"; -- 000f eh00 d??? ????
iamap := ieunit & amapc_of;
iomux := omux_mem;
imbreg := '1'; -- mb 11
when ibaddr_dc => -- RxDC desired cylinder
imask := "0000001111111111"; -- 0000 00cc cccc cccc
iamap := ieunit & amapc_dc;
iomux := omux_mem;
imbreg := '1'; -- mb 12
when ibaddr_m13 =>
if icerm = '1' then
iamap := ieunit & amapc_hr; -- RMHR holding reg
else
iamap := ieunit & amapc_dc; -- RPDC current cylinder
end if;
iomux := omux_mem;
imbreg := '1'; -- mb 13
when ibaddr_m14 =>
if icerm = '1' then
iamap := ieunit & amapc_mr2; -- RMMR2 maintenance reg 2
iomux := omux_mem;
else
iomux := omux_zero; -- RPER2 error status 2
end if;
imbreg := '1'; -- mb 14
when ibaddr_m15 => -- RxER3 error status 3/2
iomux := omux_zero;
imbreg := '1'; -- mb 15
when ibaddr_ec1 => -- RxEC1 ecc status 1
iomux := omux_zero;
imbreg := '1'; -- mb 16
when ibaddr_ec2 => -- RxEC2 ecc status 2
iomux := omux_zero;
imbreg := '1'; -- mb 17
when ibaddr_bae => -- RxBAE bus addr extension
iomux := omux_bae;
when ibaddr_cs3 => -- RxCS3 control reg 3
iomux := omux_cs3;
when others => null; -- doesn't happen, ibsel only for
-- subrange up to cs3, and all
-- 22 regs are decoded above
end case; -- case IB_MREQ.addr
n.amap := iamap;
n.omux := iomux;
n.dinmsk := imask and IB_MREQ.din;
if IB_MREQ.we = '1' then -- write request
ibhold := '1'; -- assume follow-up state taken
case IB_MREQ.addr(5 downto 1) is
when ibaddr_cs1 => n.state := s_wcs1; -- RxCS1
when ibaddr_wc => n.state := s_wmembe; -- RxWC
when ibaddr_ba => n.state := s_wmembe; -- RxBA
when ibaddr_da => n.state := s_wmem; -- RxDA
when ibaddr_cs2 => n.state := s_wcs2; -- RxCS2
when ibaddr_ds => n.state := s_wds; -- RxDS (read-only)
when ibaddr_er1 => n.state := s_wer1; -- RxER1 (read-only)
when ibaddr_as => n.state := s_was; -- RxAS
when ibaddr_la => n.state := s_whr; -- RxLA (read-only)
when ibaddr_db => n.state := s_wmembe; -- RxDB
when ibaddr_mr1 => n.state := s_wmem; -- RxMR1
when ibaddr_dt => n.state := s_wdt; -- RxDT (read-only)
when ibaddr_sn => n.state := s_whr; -- RxSN (read-only)
when ibaddr_of => n.state := s_wmem; -- RxOF
when ibaddr_dc => n.state := s_wmem; -- RxDC
when ibaddr_m13 => n.state := s_whr; -- RPCC|RMHR (fits both)
when ibaddr_m14 =>
if icerm = '1' then
n.state := s_wmem; -- RMMR2
else
n.state := s_whr; -- RPER2
end if;
when ibaddr_m15 => n.state := s_whr; -- RPER3|RMER2 (fits both)
when ibaddr_ec1 => n.state := s_whr; -- RxEC1
when ibaddr_ec2 => n.state := s_whr; -- RxEC2
when ibaddr_bae => n.state := s_wbae; -- RxBAE
when ibaddr_cs3 => n.state := s_wcs3; -- RxCS3
when others => null; -- doesn't happen, ibsel only for
-- subrange up to cs3, and all
-- 22 regs are decoded above
end case; -- case IB_MREQ.addr
-- some general error catchers
if ibrem = '0' and imbreg='1' then -- local massbus write
-- for cs1: imbreg=0 !!
-- write to non-existent drives
if ined = '1' then
n.cs2ned := '1';
-- write to a busy unit, can be a search/seek or a transfer
elsif inormr='0' and -- rmr protected reg
(r.dspip(to_integer(unsigned(r.cs2unit)))='1' or -- busy pip
(r.cs1rdy='0' and (r.funit = r.cs2unit)) -- busy xfer
) then
n.state := s_setrmr;
end if;
end if;
elsif IB_MREQ.re = '1' then -- read request
if ibrem='0' and imbreg='1' and ined='1' then
n.cs2ned := '1'; -- signal error
else
ibhold := '1';
n.state := s_read;
end if;
end if; -- if IB_MREQ.we .. elsif IB_MREQ.re
-- BRESET and ITIMER can be handled in the 'else' because both can
-- never come during an ibus transaction. Done here to keep logic
-- path in the 'if' short.
else -- if r.ibsel='1'
if BRESET = '1' then
n.eunit := "00";
n.clrmode := clrmode_breset;
n.state := s_oot_clr0; -- OOT state, no hold!
end if;
if unsigned(r.idlycnt) = 0 then -- interrupt delay expired
n.dsata := r.dsata or r.dspip; -- convert pip's to ata's
n.dspip := (others=>'0'); -- and mark them done
else
if ITIMER = '1' then -- not expired and ITIMER
n.idlycnt := slv(unsigned(r.idlycnt) - 1); -- count down
end if;
end if;
end if; -- if r.ibsel='1'
-- s_idle goes up to here !!
when s_wcs1 => -- wcs1: write cs1 -------------------
n.state := s_idle; -- in general return to s_idle
imem_addr := r.amap; -- use mapped address
imem_din := r.dinmsk; -- use masked input
if ibrem = '0' then -- loc write access
if IB_MREQ.be1 = '1' then
if IB_MREQ.din(cs1_ibf_tre) = '1' then -- TRE=1 -> clear errors
n.cs2wce := '0';
n.cs2ned := '0';
n.cs2nem := '0';
n.cs2pge := '0';
n.cs2mxf := '0';
end if;
if r.cs1rdy = '1' then -- only if RDY
n.bae(1 downto 0) := IB_MREQ.din(cs1_ibf_bae); -- update bae
end if;
end if; -- IB_MREQ.be1 = '1'
if IB_MREQ.be0 = '1' then
n.cs1ie := IB_MREQ.din(cs1_ibf_ie);
if IB_MREQ.din(cs1_ibf_ie) = '1' and -- if IE and RDY both 1
IB_MREQ.din(cs1_ibf_rdy) = '1'then
n.ireq := '1'; -- issue software interrupt
end if;
if r.ned = '0' and -- drive on
IB_MREQ.din(cs1_ibf_go) = '1' then -- GO bit set
ibhold := '1';
n.state := s_funcchk;
end if;
-- FIXME_code: that's likely not fully correct, cs1 func bits are
-- stored before all error checks are done...
imem_we0 := IB_MREQ.be0; -- remember func field per unit
if r.ned = '1' then -- loc access and drive off
n.cs2ned := '1'; -- signal error
end if;
end if; -- IB_MREQ.be0 = '1'
else -- rem write access. GO not checked
-- always treated as remote function
case IB_MREQ.din(cs1_ibf_func) is
when rfunc_wunit => -- rfunc: wunit ---------------
n.runit := IB_MREQ.din(cs1_ibf_runit);
when rfunc_cunit => -- rfunc: cunit ---------------
n.runit := r.funit; -- use unit from last ext func go
when rfunc_done => -- rfunc: done ----------------
n.cs1rdy := '1';
if IB_MREQ.din(cs1_ibf_rata) = '0' then
n.ireq := r.cs1ie; -- yes, ireq is set from ie !!
else
n.dsata(to_integer(unsigned(r.funit))) := '1';
end if;
when rfunc_widly => -- rfunc: widly ---------------
n.idlyval := IB_MREQ.din(cs1_ibf_ridly);
when others => null;
end case;
end if;
when s_wcs2 => -- wcs2: write cs2 -------------------
n.state := s_idle; -- in general return to s_idle
if ibrem = '1' then -- rem access
n.cs3wco := IB_MREQ.din(cs2_ibf_rwco); -- cs3.wco rem set via cs2 !!
n.cs2wce := IB_MREQ.din(cs2_ibf_wce);
n.cs2nem := IB_MREQ.din(cs2_ibf_nem);
n.cs2mxf := IB_MREQ.din(cs2_ibf_mxf); -- FIXME: really used ???
else
if IB_MREQ.be0 = '1' then
n.cs2pat := IB_MREQ.din(cs2_ibf_pat);
n.cs2bai := IB_MREQ.din(cs2_ibf_bai);
n.cs2unit2 := IB_MREQ.din(cs2_ibf_unit2);
n.cs2unit := IB_MREQ.din(cs2_ibf_unit);
if IB_MREQ.din(cs2_ibf_clr) = '1' then
n.eunit := "00";
n.clrmode := clrmode_cs2clr;
n.state := s_oot_clr0; -- OOT state, no hold!
end if;
end if;
end if;
when s_wcs3 => -- wcs3: write cs3 -------------------
n.state := s_idle; -- in general return to s_idle
if ibrem = '0' then -- loc access
if IB_MREQ.be0 = '1' then
n.cs1ie := IB_MREQ.din(cs3_ibf_ie);
end if;
end if;
when s_wer1 => -- wer1: write er1 (rem only) --------
n.state := s_idle; -- in general return to s_idle
if ibrem = '1' then -- rem access
if IB_MREQ.din(er1_ibf_uns) = '1' then
n.er1uns(to_integer(unsigned(r.eunit))) := '1';
end if;
if IB_MREQ.din(er1_ibf_wle) = '1' then
n.er1wle(to_integer(unsigned(r.eunit))) := '1';
end if;
if IB_MREQ.din(er1_ibf_iae) = '1' then
n.er1iae(to_integer(unsigned(r.eunit))) := '1';
end if;
if IB_MREQ.din(er1_ibf_aoe) = '1' then
n.er1aoe(to_integer(unsigned(r.eunit))) := '1';
end if;
if IB_MREQ.din(er1_ibf_ilf) = '1' then
n.er1ilf(to_integer(unsigned(r.eunit))) := '1';
end if;
else -- loc access
ibhold := '1';
n.state := s_whr;
end if;
when s_was => -- was: write as ---------------------
n.state := s_idle; -- in general return to s_idle
-- clear the attention bits marked as '1' in data word (loc and rem !!)
n.dsata := r.dsata and not IB_MREQ.din(r.dsata'range);
if ibrem = '0' then -- loc access
ibhold := '1';
n.state := s_whr;
end if;
when s_wdt => -- wdt: write dt ---------------------
n.state := s_idle; -- in general return to s_idle
if ibrem = '1' then -- rem access
n.dtrm(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_rm);
n.dte1(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_e1);
n.dte0(to_integer(unsigned(r.runit))) := IB_MREQ.din(dt_ibf_e0);
n.state := s_idle;
else -- loc access
ibhold := '1';
n.state := s_whr;
end if;
when s_wds => -- wdt: write ds ---------------------
n.state := s_idle; -- in general return to s_idle
if ibrem = '1' then -- rem access
n.dsmol(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_mol);
n.dswrl(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_wrl);
n.dslbt(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_lbt);
n.dsdpr(to_integer(unsigned(r.runit))) := IB_MREQ.din(ds_ibf_dpr);
if IB_MREQ.din(ds_ibf_ata) = '1' then -- set ata on demand
n.dsata(to_integer(unsigned(r.runit))) := '1';
end if;
if IB_MREQ.din(ds_ibf_vv) = '1' then -- clr vv on demand
n.dsvv(to_integer(unsigned(r.runit))) := '0';
end if;
if IB_MREQ.din(ds_ibf_erp) = '1' then -- clr er1 on demand
n.er1uns(to_integer(unsigned(r.eunit))) := '0'; -- clr all er1
n.er1wle(to_integer(unsigned(r.eunit))) := '0'; -- "
n.er1iae(to_integer(unsigned(r.eunit))) := '0'; -- "
n.er1aoe(to_integer(unsigned(r.eunit))) := '0'; -- "
n.er1rmr(to_integer(unsigned(r.eunit))) := '0'; -- "
n.er1ilf(to_integer(unsigned(r.eunit))) := '0'; -- "
end if;
n.state := s_idle;
else -- loc access
ibhold := '1'; -- read-only reg, thus noop
n.state := s_whr;
end if;
when s_wbae => -- wbae: write bae -------------------
n.state := s_idle; -- in general return to s_idle
if IB_MREQ.be0 = '1' then
n.bae := IB_MREQ.din(bae_ibf_bae);
end if;
when s_wmem => -- wmem: write mem (DA,MR1,OF,DC,MR2)-
-- this state only handles massbus registers
n.state := s_idle; -- in general return to s_idle
imem_addr := r.amap; -- use mapped address
imem_din := r.dinmsk; -- use masked input
if ibrem = '0' then -- loc access
imem_we0 := '1'; -- write memory
imem_we1 := '1';
ibhold := '1';
n.state := s_whr;
else -- rem access
imem_we0 := '1'; -- write memory
imem_we1 := '1';
end if;
when s_wmembe => -- wmem: write mem with be (WC,BA,DB)-
-- this state only handles controller registers --> no ned checking
n.state := s_idle; -- in general return to s_idle
imem_we0 := IB_MREQ.be0;
imem_we1 := IB_MREQ.be1;
imem_addr := r.amap;
imem_din := r.dinmsk;
when s_whr => -- whr: write hr ---------------------
n.state := s_idle; -- in general return to s_idle
imem_addr := r.cs2unit & amapc_hr; -- mem address of holding reg
imem_din := not IB_MREQ.din;
if ibrem = '0' then -- loc access
imem_we0 := '1'; -- keep state
imem_we1 := '1';
end if;
when s_funcchk => -- funcchk: check function go --------
n.state := s_idle; -- in general return to s_idle
if r.cs1rdy = '0' and
unsigned(IB_MREQ.din(cs1_ibf_func)) >= unsigned(func_xfer) then
n.cs2pge := '1'; -- issue program error
elsif IB_MREQ.din(cs1_ibf_func) = func_dclr then
n.eunit := r.cs2unit; -- for follow-up states
n.clrmode := clrmode_fdclr;
n.state := s_oot_clr0; -- OOT state, no hold!
elsif r.dserp(to_integer(unsigned(r.cs2unit))) = '1' then
n.er1ilf(to_integer(unsigned(r.cs2unit))) := '1';
else
ibhold := '1';
n.state := s_funcgo;
end if;
when s_funcgo => -- funcgo: handle function go --------
n.state := s_idle; -- in general return to s_idle
n.dsata(to_integer(unsigned(r.cs2unit))) := '0';
case IB_MREQ.din(cs1_ibf_func) is
when func_noop => -- func: noop --------------
null; -- nothing done...
when func_pore => -- func: port release-------
n.poredone := '1'; -- take note in done flag
when func_unl => -- func: unload ------------
-- only for RP, simply clears MOL
if r.dtrm(to_integer(unsigned(r.cs2unit))) = '0' then
n.dsmol(to_integer(unsigned(r.cs2unit))) := '0';
n.dswrl(to_integer(unsigned(r.cs2unit))) := '0';
n.dsvv(to_integer(unsigned(r.cs2unit))) := '0';
n.dsom(to_integer(unsigned(r.cs2unit))) := '0';
else
n.er1ilf(to_integer(unsigned(r.cs2unit))) := '1';
end if;
n.dsata(to_integer(unsigned(r.cs2unit))) := '1';
-- when func_dclr => now handled in funcchk !!
when func_offs | -- func: offset ------------
func_retc => -- func: return to center --
-- currently always immediate completion, so ata set here
n.dsata(to_integer(unsigned(r.cs2unit))) := '1';
if r.dsmol(to_integer(unsigned(r.cs2unit))) = '0' then
n.er1uns(to_integer(unsigned(r.cs2unit))) := '1';
else
if IB_MREQ.din(cs1_ibf_func) = func_offs then
n.dsom(to_integer(unsigned(r.cs2unit))) := '1';
else
n.dsom(to_integer(unsigned(r.cs2unit))) := '0';
end if;
end if;
when func_pres => -- func: readin preset -----
n.dsvv(to_integer(unsigned(r.cs2unit))) := '1';
n.eunit := r.cs2unit; -- for follow-up states
n.clrmode := clrmode_fpres;
n.state := s_oot_clr0; -- OOT state, no hold!
when func_pack => -- func: pack acknowledge --
n.dsvv(to_integer(unsigned(r.cs2unit))) := '1';
n.packdone := '1'; -- take note in done flag
-- seek like and data transfer functions
when func_seek | -- func: seek --------------
func_recal | -- func: recalibrate -------
func_sear | -- func: search ------------
func_wcd | -- func: write check data --
func_wchd | -- func: write check h&d ---
func_write | -- func: write ------------
func_whd | -- func: write header&data -
func_read | -- func: read --------------
func_rhd => -- func: read header&data --
if IB_MREQ.din(cs1_ibf_func) = func_seek then
n.seekdone := '1'; -- take note in done flag
end if;
if IB_MREQ.din(cs1_ibf_func) = func_sear then
n.seardone := '1'; -- take note in done flag
end if;
-- check for transfer functions
n.fxfer := '0';
if unsigned(IB_MREQ.din(cs1_ibf_func)) >= unsigned(func_wcd) then
n.fxfer := '1';
-- in case of write, check for write lock
if IB_MREQ.din(cs1_ibf_func) = func_write or
IB_MREQ.din(cs1_ibf_func) = func_whd then
if r.dswrl(to_integer(unsigned(r.cs2unit))) = '1' then
n.er1wle(to_integer(unsigned(r.cs2unit))) := '1';
end if;
end if;
end if;
if r.dsmol(to_integer(unsigned(r.cs2unit))) = '0' then
n.er1uns(to_integer(unsigned(r.cs2unit))) := '1';
n.dsata(to_integer(unsigned(r.cs2unit))) := '1';
else
ibhold := '1';
n.state := s_chkdc;
end if;
-- illegal function codes
when others =>
n.er1ilf(to_integer(unsigned(r.cs2unit))) := '1';
n.dsata(to_integer(unsigned(r.cs2unit))) := '1';
end case; -- IB_MREQ.din(cs1_ibf_func)
when s_chkdc => -- chkdc: handle dc check ------------
imem_addr := r.cs2unit & amapc_dc; -- mem address of dc reg
if unsigned(MEM_DOUT(dc_ibf_ca)) > unsigned(r.camax) then
n.er1iae(to_integer(unsigned(r.cs2unit))) := '1';
end if;
ibhold := '1';
n.state := s_chkda;
when s_chkda => -- chkda: handle da check ------------
imem_addr := r.cs2unit & amapc_da; -- mem address of da reg
if unsigned(MEM_DOUT(da_ibf_sa)) > unsigned(r.samax) or
unsigned(MEM_DOUT(da_ibf_ta)) > unsigned(r.tamax) then
n.er1iae(to_integer(unsigned(r.cs2unit))) := '1';
end if;
ibhold := '1';
n.state := s_chkdo;
when s_chkdo => -- chkdo: execute function -----------
if r.er1iae(to_integer(unsigned(r.cs2unit))) = '1' or
r.er1wle(to_integer(unsigned(r.cs2unit))) = '1' then
n.dsata(to_integer(unsigned(r.cs2unit))) := '1'; -- ata and done
else
if r.fxfer = '0' then -- must be seek like function
n.dspip(to_integer(unsigned(r.cs2unit))) := '1'; -- pip
n.idlycnt := r.idlyval; -- start delay
else -- must be transfer function
n.ffunc := IB_MREQ.din(cs1_ibf_func); -- latch func
n.funit := r.cs2unit; -- latch unit
n.cs1rdy := '0'; -- controller busy
n.cs2wce := '0'; -- clear errors
n.cs2ned := '0';
n.cs2nem := '0';
n.cs2pge := '0';
n.cs2mxf := '0';
ilam := '1'; -- issue lam
end if;
end if;
n.state := s_idle;
when s_read => -- read: all register reads ----------
n.state := s_idle; -- in general return to s_idle
imem_addr := r.amap;
case r.omux is
when omux_cs1 => -- omux: cs1 reg ---------------
idout(cs1_ibf_sc) := r.cs1sc;
idout(cs1_ibf_tre) := r.cs1tre;
idout(cs1_ibf_dva) := '1';
idout(cs1_ibf_bae) := r.bae(1 downto 0);
idout(cs1_ibf_rdy) := r.cs1rdy;
idout(cs1_ibf_ie) := r.cs1ie;
if ibrem = '0' then -- loc access
idout(cs1_ibf_func) := MEM_DOUT(cs1_ibf_func); --func per unit
if r.ned = '1' then -- drive off
n.cs2ned := '1'; -- signal error
end if;
else -- rem access
idout(cs1_ibf_func) := r.ffunc;
end if;
when omux_cs2 => -- omux: cs2 reg ---------------
idout(cs2_ibf_wce) := r.cs2wce;
idout(cs2_ibf_ned) := r.cs2ned;
idout(cs2_ibf_nem) := r.cs2nem;
idout(cs2_ibf_pge) := r.cs2pge;
idout(cs2_ibf_mxf) := r.cs2mxf;
idout(cs2_ibf_or) := '1';
idout(cs2_ibf_ir) := '1';
idout(cs2_ibf_pat) := r.cs2pat;
idout(cs2_ibf_bai) := r.cs2bai;
idout(cs2_ibf_unit2) := r.cs2unit2;
if ibrem = '0' then -- loc access
idout(cs2_ibf_unit) := r.cs2unit;
else -- rem access
idout(cs2_ibf_unit) := r.funit;
end if;
when omux_ds => -- omux: ds reg ---------------
idout(ds_ibf_ata) := r.dsata(to_integer(unsigned(r.eunit)));
idout(ds_ibf_erp) := r.dserp(to_integer(unsigned(r.eunit)));
idout(ds_ibf_pip) := r.dspip(to_integer(unsigned(r.eunit)));
idout(ds_ibf_mol) := r.dsmol(to_integer(unsigned(r.eunit)));
idout(ds_ibf_wrl) := r.dswrl(to_integer(unsigned(r.eunit)));
idout(ds_ibf_lbt) := r.dslbt(to_integer(unsigned(r.eunit)));
idout(ds_ibf_dpr) := r.dsdpr(to_integer(unsigned(r.eunit)));
-- ds.dry is 0 if mol=0 or if transfer or seek is active on unit
-- the logic below checks for the complement ...
if r.dsmol(to_integer(unsigned(r.eunit))) = '1' then
if (r.cs1rdy = '1' or r.funit /= r.eunit) and
r.dspip(to_integer(unsigned(r.eunit))) = '0' then
idout(ds_ibf_dry) := '1';
end if;
end if;
idout(ds_ibf_vv) := r.dsvv (to_integer(unsigned(r.eunit)));
idout(ds_ibf_om) := r.dsom (to_integer(unsigned(r.eunit)));
when omux_er1 => -- omux: er1 reg ---------------
idout(er1_ibf_uns) := r.er1uns(to_integer(unsigned(r.eunit)));
idout(er1_ibf_wle) := r.er1wle(to_integer(unsigned(r.eunit)));
idout(er1_ibf_iae) := r.er1iae(to_integer(unsigned(r.eunit)));
idout(er1_ibf_aoe) := r.er1aoe(to_integer(unsigned(r.eunit)));
idout(er1_ibf_rmr) := r.er1rmr(to_integer(unsigned(r.eunit)));
idout(er1_ibf_ilf) := r.er1ilf(to_integer(unsigned(r.eunit)));
when omux_as => -- omux: as reg ---------------
idout(r.dsata'range) := r.dsata;
when omux_la => -- omux: la reg ---------------
idout(la_ibf_sc) := r.sc;
when omux_dt => -- omux: dt reg ---------------
if ibrem = '0' then -- loc access
idout(13) := '1'; -- set bit 020000 (movable head)
idout(r.dtyp'range) := r.dtyp;
else -- rem access (read back rem side)
idout(dt_ibf_rm) := r.dtrm(to_integer(unsigned(r.runit)));
idout(dt_ibf_e1) := r.dte1(to_integer(unsigned(r.runit)));
idout(dt_ibf_e0) := r.dte0(to_integer(unsigned(r.runit)));
end if;
when omux_sn => -- omux: sn reg ---------------
-- the serial number is encoded as 4 digit BCD
-- digit 3: always 1
-- digit 2: 1 if RM type; 0 if RP type
-- digit 1: 0-3 based on encoded drive type
-- digit 0: 0-3 taken as complement of unit
-- Note: the 3lsb are the *complement* of the unit number because
-- 211bsd driver code contains a hack to detect SI and CDC
-- drives. For those drives the drive type is encode in the
-- sn register, and one convention is that the 3 lsb of sn
-- equal the unit numnber. To prevent that the SI/CDC hacks
-- are actived the 3lsb are set as complement of the unit !
idout(12) := '1';
idout(8) := r.dtrm(to_integer(unsigned(r.eunit)));
idout(5) := r.dte1(to_integer(unsigned(r.eunit)));
idout(4) := r.dte0(to_integer(unsigned(r.eunit)));
idout(2) := '1';
idout(1) := not r.eunit(1);
idout(0) := not r.eunit(0);
when omux_bae => -- omux: bae reg ---------------
idout(bae_ibf_bae) := r.bae;
when omux_cs3 => -- omux: cs3 reg ---------------
idout(cs3_ibf_wco) := r.cs2wce and r.cs3wco;
idout(cs3_ibf_wce) := r.cs2wce and not r.cs3wco;
idout(cs3_ibf_ie) := r.cs1ie;
if ibrem = '1' then -- rem access
idout(cs3_ibf_rseardone) := r.seardone;
idout(cs3_ibf_rpackdone) := r.packdone;
idout(cs3_ibf_rporedone) := r.poredone;
idout(cs3_ibf_rseekdone) := r.seekdone;
if IB_MREQ.re = '1' then -- if read, do read & clear
n.seardone := '0';
n.packdone := '0';
n.poredone := '0';
n.seekdone := '0';
end if;
end if;
when omux_mem => -- omux: mem output ------------
idout := MEM_DOUT;
when omux_zero => -- omux: zero ------------------
idout := (others=>'0');
when others => null; -- nxr caught before in mapper !
end case; -- case r.omux
when s_setrmr => -- set rmr flag ----------------------
n.er1rmr(to_integer(unsigned(r.cs2unit))) := '1';
n.state := s_idle;
when s_oot_clr0 => -- OOT clr0: state 0 -----------------
if r.clrmode=clrmode_breset or r.clrmode=clrmode_cs2clr then
n.cs1rdy := '1'; -- clear cs1
n.cs1ie := '0';
n.cs2wce := '0'; -- clear cs2
n.cs2ned := '0';
n.cs2nem := '0';
n.cs2pge := '0';
n.cs2mxf := '0';
n.cs2pat := '0';
n.cs2bai := '0';
n.cs2unit2 := '0';
n.cs2unit := (others=>'0');
n.bae := (others=>'0'); -- clear bae
n.ireq := '0'; -- clear iff
end if;
if r.clrmode=clrmode_breset or r.clrmode=clrmode_fdclr then
n.er1uns(to_integer(unsigned(r.eunit))) := '0'; -- clr all er1
n.er1wle(to_integer(unsigned(r.eunit))) := '0'; -- "
n.er1iae(to_integer(unsigned(r.eunit))) := '0'; -- "
n.er1aoe(to_integer(unsigned(r.eunit))) := '0'; -- "
n.er1rmr(to_integer(unsigned(r.eunit))) := '0'; -- "
n.er1ilf(to_integer(unsigned(r.eunit))) := '0'; -- "
end if;
n.cerm := r.dtrm(to_integer(unsigned(ieunit)));
n.clrreg := "000";
ibhold := r.ibsel; -- delay pending request
n.state := s_oot_clr1;
when s_oot_clr1 => -- OOT clr1: state 1 ----------------
imem_addr := r.eunit & r.clrreg;
imem_din := (others=>'0');
iclrreg := '0';
case r.clrmode is
when clrmode_breset => -- BRESET -------------------------
iclrreg := '1'; -- simply clear all (cntl+drives)
when clrmode_cs2clr => -- CS2.CLR (controller clr) -------
case r.clrreg is
when amapc_ext => iclrreg := '1';
when amapc_mr1 => iclrreg := r.cerm;
when others => null;
end case;
when clrmode_fdclr => -- func=DCLR (drive clr) ----------
case r.clrreg is
when amapc_mr1 => iclrreg := r.cerm;
when others => null;
end case;
when clrmode_fpres => -- func=PRESET --------------------
case r.clrreg is
when amapc_da => iclrreg := '1';
when amapc_of => iclrreg := '1';
when amapc_dc => iclrreg := '1';
when others => null;
end case;
when others => null;
end case;
if iclrreg = '1' then
imem_we0 := IB_MREQ.be0;
imem_we1 := IB_MREQ.be1;
end if;
n.clrreg := slv(unsigned(r.clrreg) + 1);
ibhold := r.ibsel; -- delay pending request
if r.clrreg = "111" then -- if last register done
n.state := s_oot_clr2; -- proceed with clr2
end if;
when s_oot_clr2 => -- OOT clr2: state 2 ----------------
n.eunit := slv(unsigned(r.eunit) + 1);
ibhold := r.ibsel; -- delay pending request, so that
-- s_idle can finally process it
if (r.clrmode=clrmode_breset or r.clrmode=clrmode_cs2clr) and
r.eunit /= "11" then
n.state := s_oot_clr0;
else
n.state := s_idle;
end if;
when others => null; -- <> ------------------------------
end case; -- case r.state
-- update cs1tre and cs1sc
n.cs1tre := r.cs2wce or r.cs2ned or r.cs2nem or r.cs2pge or r.cs2mxf;
n.cs1sc := n.cs1tre or r.dsata(0) or r.dsata(1) or r.dsata(2) or r.dsata(3);
-- update dserp
n.dserp := r.er1uns or -- or all er1
r.er1wle or -- "
r.er1iae or -- "
r.er1aoe or -- "
r.er1rmr or -- "
r.er1ilf; -- "
-- handle current sector counter (for RxLA emulation)
-- advance every 128 usec, so generate a pulse every 128 usec
if CE_USEC = '1' then
n.uscnt := slv(unsigned(r.uscnt) + 1);
if unsigned(r.uscnt) = 0 then
iscinc := '1';
end if;
end if;
-- if current sector larger or equal highest sector wrap to zero
-- note: iscinc is also '1' when unit changes, this ensures that
-- the sector counter is always in range when read to ibus.
if iscinc = '1' then
if unsigned(r.sc) >= unsigned(r.samax) then
n.sc := (others=>'0');
else
n.sc := slv(unsigned(r.sc) + 1);
end if;
end if;
-- the RH70 interrupt logic is very unusual
-- 1. done interrupts (rdy 0->1) are edge sensitive (via r.ireq)
-- 2. done interrupts are not canceled when IE is cleared
-- 3. attention interrupts are level sensitive (via r.cs1sc)
-- 4. IE is disabled on interrupt acknowledge
iei_req := r.ireq or (r.cs1sc and r.cs1ie and r.cs1rdy);
if EI_ACK = '1' then -- interrupt executed
n.ireq := '0'; -- cancel request
n.cs1ie := '0'; -- disable interrupts
end if;
N_REGS <= n;
MEM_0_WE <= imem_we0;
MEM_1_WE <= imem_we1;
MEM_ADDR <= imem_addr;
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
end syn;
| gpl-3.0 | 2e24c9a23a184bb2cb17502ed51bec25 | 0.450374 | 3.645077 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd | 1 | 3,711 | -- $Id: tb_tst_serloop_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop_s3 - sim
-- Description: Test bench for sys_tst_serloop_s3
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop_s3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop_s3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-06 420 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop_s3 is
end tb_tst_serloop_s3;
architecture sim of tb_tst_serloop_s3 is
signal CLK50 : slbit := '0';
signal CLKS : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
UUT : entity work.sys_tst_serloop_s3
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKS,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | 2cb6188a1a4bf8aae2fae94545b5e31b | 0.50741 | 3.026917 | false | false | false | false |
jsyk/spnsyn-demo | t/myutils.vhd | 1 | 6,121 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
package myutils is
subtype dfu_opcode_t is std_logic_vector(4 downto 0);
subtype dfu_veclen_t is std_logic_vector(9 downto 0);
subtype raw_dfu_config_t is std_logic_vector(14 downto 0);
type dfu_config_t is record
opcode : dfu_opcode_t; --! DFU command operation code
veclen : dfu_veclen_t; --! vector length
end record;
type dfu_ctrlreg_t is record
cfg : dfu_config_t;
idx : dfu_veclen_t;
p_idx : dfu_veclen_t;
end record;
constant ZERO_dfu_config_t : dfu_config_t := (
opcode => (others => '0'),
veclen => (others => '0')
);
constant ZERO_dfu_ctrlreg_t : dfu_ctrlreg_t := (
cfg => ZERO_dfu_config_t,
idx => (others => '0'), p_idx => (others => '0')
);
constant UNDEF_dfu_ctrlreg_t : dfu_ctrlreg_t := ZERO_dfu_ctrlreg_t;
--
-- counter
function minus(D: std_logic_vector; P: std_ulogic) return std_logic_vector;
function minus(D: std_logic_vector) return std_logic_vector;
function is_nonzero(D: std_logic_vector(7 downto 0)) return std_ulogic;
-- folder
function concat(D1: std_logic_vector; D2: std_logic_vector; P: std_ulogic) return std_logic_vector;
function take_first(D1: std_logic_vector; D2: std_logic_vector; P: std_ulogic) return std_logic_vector;
function adder_stage(DI: std_logic_vector; P: std_ulogic) return std_logic_vector;
function nop1(DI: std_logic_vector; P: std_ulogic) return std_logic_vector;
function nop2(DI: std_logic_vector; P: std_ulogic) return std_logic_vector;
function extend_inp_null(DI: std_logic_vector(31 downto 0); P: std_ulogic) return std_logic_vector;
function give_neutral(ctc: dfu_ctrlreg_t) return std_logic_vector;
function extend_inp_ctr(DA: std_logic_vector(31 downto 0); ctr: dfu_ctrlreg_t; P: std_ulogic) return std_logic_vector;
function init_ctr(DI: raw_dfu_config_t; P: std_ulogic) return dfu_ctrlreg_t;
function update_ctr(DI: dfu_ctrlreg_t; P: std_ulogic) return dfu_ctrlreg_t;
function is_reduction(DI: dfu_ctrlreg_t) return std_ulogic;
function is_continuing(DI: dfu_ctrlreg_t) return std_ulogic;
end;
package body myutils is
function minus(D: std_logic_vector; P: std_ulogic) return std_logic_vector is
constant len : integer := D'length;
variable res : std_logic_vector(len downto 0); -- wider
begin
res := std_logic_vector( to_signed(to_integer(signed(D)) - 1, len+1) );
return res(len-1 downto 0);
end function minus;
function minus(D: std_logic_vector) return std_logic_vector is
constant len : integer := D'length;
variable res : std_logic_vector(len downto 0); -- wider
begin
res := std_logic_vector( to_signed(to_integer(signed(D)) - 1, len+1) );
return res(len-1 downto 0);
end function minus;
function is_nonzero(D: std_logic_vector(7 downto 0)) return std_ulogic is
begin
if D /= zero_std_logic_vector(7, 0) then
return '1';
else
return '0';
end if;
end function is_nonzero;
function concat(D1: std_logic_vector; D2: std_logic_vector; P: std_ulogic) return std_logic_vector is
variable D : std_logic_vector((D1'length + D2'length - 1) downto 0);
begin
D := D1 & D2;
return D;
end function concat;
function take_first(D1: std_logic_vector; D2: std_logic_vector; P: std_ulogic) return std_logic_vector is
begin
return D1;
end function;
function adder_stage(DI: std_logic_vector; P: std_ulogic) return std_logic_vector is
variable DO : std_logic_vector((DI'length/2 -1) downto 0);
variable a, b : integer;
begin
a := to_integer(signed(DI(DI'length-1 downto DI'length/2)));
b := to_integer(signed(DI(DI'length/2-1 downto 0)));
DO := std_logic_vector(to_signed(a + b, DI'length/2));
return DO;
end function adder_stage;
function nop1(DI: std_logic_vector; P: std_ulogic) return std_logic_vector is
begin
return DI;
end function;
function nop2(DI: std_logic_vector; P: std_ulogic) return std_logic_vector is
begin
return DI;
end function;
function extend_inp_null(DI: std_logic_vector(31 downto 0); P: std_ulogic) return std_logic_vector is
variable v : std_logic_vector(41 downto 0);
begin
v := (others => '0');
v(31 downto 0) := DI;
return v;
end function;
function give_neutral(ctc: dfu_ctrlreg_t) return std_logic_vector is
variable v : std_logic_vector(41 downto 0);
begin
-- ctc.cfg.opcode(4 downto 0)
-- RIMmS neutral
-- "00000" add -> 0
-- "00001" sub -> 0
-- "10000" sum -> 0
-- "10011" min -> +inf
-- "10101" max -> -inf
-- "11011" idxmin -> +inf
-- "11101" idxmax -> -inf
v := (others => '0');
if ctc.cfg.opcode(2 downto 1) = "01" then
-- +inf
-- v(31 downto 0) := x"7FFFffff";
v(31 downto 0) := x"7FFF0000";
elsif ctc.cfg.opcode(2 downto 1) = "10" then
-- -inf
-- v(31 downto 0) := x"80000000";
v(31 downto 0) := x"8000ffff";
end if;
-- TODO
--v(31 downto 0) := DI;
return v;
end function;
function extend_inp_ctr(DA: std_logic_vector(31 downto 0); ctr: dfu_ctrlreg_t; P: std_ulogic) return std_logic_vector is
variable v : std_logic_vector(41 downto 0);
begin
v := (others => '0');
v(31 downto 0) := DA;
v(41 downto 32) := ctr.p_idx;
return v;
end function;
function init_ctr(DI: raw_dfu_config_t; P: std_ulogic) return dfu_ctrlreg_t is
variable v : dfu_ctrlreg_t;
begin
v := ZERO_dfu_ctrlreg_t;
v.cfg.opcode := DI(14 downto 10);
v.cfg.veclen := DI(9 downto 0);
return v;
end function;
function update_ctr(DI: dfu_ctrlreg_t; P: std_ulogic) return dfu_ctrlreg_t is
variable v : dfu_ctrlreg_t;
begin
v := DI;
v.p_idx := v.idx;
v.idx := std_logic_vector(to_unsigned( to_integer(unsigned(v.idx)) + 1, dfu_veclen_t'length));
return v;
end function;
function is_reduction(DI: dfu_ctrlreg_t) return std_ulogic is
begin
return DI.cfg.opcode(4);
end function;
function is_continuing(DI: dfu_ctrlreg_t) return std_ulogic is
begin
if DI.cfg.veclen /= DI.idx then
return '1';
else
return '0';
end if;
end function;
end;
| gpl-2.0 | 66ea2cdc670b8364e7ab494e8906cee2 | 0.66035 | 2.93714 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | controller.vhd | 1 | 2,037 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY controller IS
PORT (
opcode : IN std_logic_vector(5 downto 0);
ulaOp : out std_logic_vector(1 downto 0);
RegDst, ulaFonte, escMem, lerMem, DvC, memParaReg, escReg: out std_logic
);
END controller;
ARCHITECTURE rtl OF controller IS
BEGIN
process(opcode)
begin
CASE opcode IS
WHEN "000000" => -- R type
RegDst <= '1';
ulaFonte <= '0';
memParaReg <= '0';
lerMem <= '0';
escMem <= '0';
escReg <= '1';
DvC <= '0';
ulaOp <= "10";
WHEN "100011" => -- lw / I type
RegDst <= '0';
ulaFonte <= '1';
memParaReg <= '1';
lerMem <= '1';
escMem <= '0';
escReg <= '1';
DvC <= '0';
ulaOp <= "00";
WHEN "101011" => -- sw / I type
RegDst <= '-';
ulaFonte <= '1';
memParaReg <= '-';
lerMem <= '0';
escMem <= '1';
escReg <= '0';
DvC <= '0';
ulaOp <= "00";
WHEN "000100" => -- beq / I type
RegDst <= '-';
ulaFonte <= '0';
memParaReg <= '-';
lerMem <= '0';
escMem <= '0';
escReg <= '0';
DvC <= '1';
ulaOp <= "01";
WHEN "001000" => -- addi / I type
RegDst <= '0';
ulaFonte <= '1';
memParaReg <= '0';
lerMem <= '0';
escMem <= '0';
escReg <= '1';
DvC <= '0';
ulaOp <= "00";
WHEN "001101" => -- ori / I type
RegDst <= '0';
ulaFonte <= '1';
memParaReg <= '0';
lerMem <= '0';
escMem <= '0';
escReg <= '1';
DvC <= '0';
ulaOp <= "00";
WHEN "000010" => -- j / J type
RegDst <= '-';
ulaFonte <= '-';
memParaReg <= '-';
lerMem <= '0';
escMem <= '0';
escReg <= '0';
DvC <= '0';
ulaOp <= "00";
WHEN OTHERS =>
RegDst <= '0';
ulaFonte <= '0';
memParaReg <= '0';
lerMem <= '0';
escMem <= '0';
escReg <= '0';
DvC <= '0';
ulaOp <= "00";
END CASE;
end process;
END rtl;
| mit | 1e04a5a4f18462d75f5876f5b5a2cc67 | 0.44919 | 3.013314 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tbcore/tbcore_rlink.vhd | 1 | 9,457 | -- $Id: tbcore_rlink.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbcore_rlink - sim
-- Description: Core for a rlink_cext based test bench
--
-- Dependencies: simlib/simclkcnt
-- rlink_cext_iface
--
-- To test: generic, any rlink_cext based target
--
-- Target Devices: generic
-- Tool versions: ghdl 0.26-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-25 1074 3.3 wait 40 cycles after CONF_DONE
-- 2016-09-17 807 3.2.2 conf: .sinit -> .sdata; finite length SB_VAL pulse
-- 2016-09-02 805 3.2.1 conf: add .wait and CONF_DONE; drop CLK_STOP
-- 2016-02-07 729 3.2 use rlink_cext_iface (allow VHPI and DPI backend)
-- 2015-11-01 712 3.1.3 proc_stim: drive SB_CNTL from start to avoid 'U'
-- 2013-01-04 469 3.1.2 use 1ns wait for .sinit to allow simbus debugging
-- 2011-12-25 445 3.1.1 add SB_ init drivers to avoid SB_VAL='U' at start
-- 2011-12-23 444 3.1 redo clock handling, remove simclk, CLK now input
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 rename rritb_core->tbcore_rlink; use rbv3 naming
-- 2010-06-05 301 1.1.2 rename .rpmon -> .rbmon
-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
use work.rlinklib.all;
entity tbcore_rlink is -- core of rlink_cext based test bench
port (
CLK : in slbit; -- control interface clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end tbcore_rlink;
architecture sim of tbcore_rlink is
signal CLK_CYCLE : integer := 0;
signal CEXT_CYCLE : slv32 := (others=>'0');
signal CEXT_RXDATA : slv32 := (others=>'0');
signal CEXT_RXVAL : slbit := '0';
signal CEXT_RXHOLD : slbit := '1';
signal CONF_DONE : slbit := '0';
begin
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
CEXT_IFACE : entity work.rlink_cext_iface
port map (
CLK => CLK,
CLK_CYCLE => CEXT_CYCLE,
RX_DATA => CEXT_RXDATA,
RX_VAL => CEXT_RXVAL,
RX_HOLD => CEXT_RXHOLD,
TX_DATA => TX_DATA,
TX_ENA => TX_ENA
);
CEXT_CYCLE <= slv(to_signed(CLK_CYCLE,32));
proc_conf: process
file fconf : text open read_mode is "rlink_cext_conf";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable ien : slbit := '0';
variable ibit : integer := 0;
variable twait : Delay_length := 0 ns;
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
CONF_DONE <= '0';
SB_SIMSTOP <= 'L';
SB_CNTL <= (others=>'L');
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
file_loop: while not endfile(fconf) loop
readline (fconf, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
wait for 1 ns;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
wait for 1 ns;
if ien = '1' then
SB_CNTL(sbcntl_sbf_rlmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rlmon) <= 'L';
end if;
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
wait for 1 ns;
if ien = '1' then
SB_CNTL(sbcntl_sbf_rbmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rbmon) <= 'L';
end if;
when ".sdata" => -- .sdata
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
wait for 1 ns;
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= 'H';
wait for 1 ns;
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
when ".wait " => -- .wait
read_ea(iline, twait);
wait for twait;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
CONF_DONE <= '1';
wait; -- halt process here
end process proc_conf;
proc_stim: process
variable irxint : integer := 0;
variable irxslv : slv24 := (others=>'0');
variable ibit : integer := 0;
variable oline : line;
variable r_sb_cntl : slv16 := (others=>'Z');
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
-- setup init values for all output ports
RX_DATA <= (others=>'0');
RX_VAL <= '0';
SB_VAL <= 'Z';
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
SB_CNTL <= (others=>'Z');
CEXT_RXHOLD <= '1';
-- wait for CONF_DONE, plus addional 40 clock cycles (conf+design run up)
while CONF_DONE = '0' loop
wait until rising_edge(CLK);
end loop;
for i in 0 to 39 loop
wait until rising_edge(CLK);
end loop; -- i
writetimestamp(oline, CLK_CYCLE, ": START");
writeline(output, oline);
stim_loop: loop
wait until falling_edge(CLK);
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
RX_VAL <= '0';
CEXT_RXHOLD <= RX_HOLD;
if RX_HOLD = '0' then
irxint := to_integer(signed(CEXT_RXDATA));
if CEXT_RXVAL = '1' then
if irxint <= 16#ff# then -- normal data byte
RX_DATA <= slv(to_unsigned(irxint, 8));
RX_VAL <= '1';
elsif irxint >= 16#1000000# then -- out-of-band message
irxslv := slv(to_unsigned(irxint mod 16#1000000#, 24));
iaddr := irxslv(23 downto 16);
idata := irxslv(15 downto 0);
writetimestamp(oline, CLK_CYCLE, ": OOB-MSG");
write(oline, irxslv(23 downto 16), right, 9);
write(oline, irxslv(15 downto 8), right, 9);
write(oline, irxslv( 7 downto 0), right, 9);
write(oline, string'(" : "));
writeoct(oline, iaddr, right, 3);
writeoct(oline, idata, right, 7);
writeline(output, oline);
if unsigned(iaddr) = 0 then
ibit := to_integer(unsigned(idata(15 downto 8)));
r_sb_cntl(ibit) := idata(0);
else
SB_ADDR <= iaddr;
SB_DATA <= idata;
-- In principle a delta cycle long pulse is enough to make the
-- simbus transfer. A 500 ps long pulse is generated to ensure
-- that SB_VAL is visible in a viewer. That works up to 1 GHz
SB_VAL <= '1';
wait for 500 ps;
SB_VAL <= 'Z';
wait for 0 ps;
end if;
end if;
elsif irxint = -1 then -- end-of-file seen
exit stim_loop;
else
report "rlink_cext_getbyte error: " & integer'image(-irxint)
severity failure;
end if; -- CEXT_RXVAL = '1'
end if; -- RX_HOLD = '0'
SB_CNTL <= r_sb_cntl;
end loop;
-- wait for 50 clock cycles (design run down)
for i in 0 to 49 loop
wait until rising_edge(CLK);
end loop; -- i
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
SB_SIMSTOP <= '1'; -- signal simulation stop
wait for 100 ns; -- monitor grace time
report "Simulation Finished" severity failure; -- end simulation
end process proc_stim;
end sim;
| gpl-3.0 | 0d31d50f084258b3eaf38139ec53e6a5 | 0.512636 | 3.684067 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys3/tb/nexys3_fusp_dummy.vhd | 1 | 3,287 | -- $Id: nexys3_fusp_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1 use nxcramlib
-- 2011-11-25 432 1.0 Initial version (derived from nexys2_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_dummy is -- NEXYS 3 dummy (base+fusp; loopback)
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys3_fusp_dummy;
architecture syn of nexys3_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
| gpl-3.0 | bf722ddff4c53bfc18558404725c133f | 0.487375 | 3.273904 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/tb/tb_fifo_simple_dram.vhd | 1 | 7,065 | -- $Id: tb_fifo_simple_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_fifo_simple_dram - sim
-- Description: Test bench for fifo_simple_dram
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_fifo_simple_dram [UUT]
--
-- To test: fifo_simple_dram
--
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2017.2 ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_fifo_simple_dram is
end tb_fifo_simple_dram;
architecture sim of tb_fifo_simple_dram is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE : slbit := '0';
signal WE : slbit := '0';
signal DI : slv16 := (others=>'0');
signal DO : slv16 := (others=>'0');
signal EMPTY : slbit := '0';
signal FULL : slbit := '0';
signal SIZE : slv4 := (others=>'0');
signal N_EMPTY : slbit := '1';
signal N_FULL : slbit := '0';
signal N_SIZE : slv4 := (others=>'0');
signal R_EMPTY : slbit := '1';
signal R_FULL : slbit := '0';
signal R_SIZE : slv4 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_fifo_simple_dram
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
WE => WE,
DI => DI,
DO => DO,
EMPTY => EMPTY,
FULL => FULL,
SIZE => SIZE
);
proc_stim: process
file fstim : text open read_mode is "tb_fifo_simple_dram_stim";
variable iline : line;
variable oline : line;
variable dname : string(1 to 6) := (others=>' ');
variable ok : boolean;
variable nwait : integer := 0; --
variable idi : slv16 := (others=>'0');
variable ido : slv16 := (others=>'0');
variable isize : slv4 := (others=>'0');
begin
wait for clock_offset;
wait until rising_edge(CLK);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".wait " => -- .wait ncyc
read_ea(iline, nwait);
for i in 1 to nwait loop
wait until rising_edge(CLK);
end loop; -- i
when "reset " => -- reset
writetimestamp(oline, CLK_CYCLE, ": reset");
writeline(output, oline);
RESET <= '1';
isize := "0000";
N_EMPTY <= '1';
N_FULL <= '0';
N_SIZE <= isize;
wait until rising_edge(CLK);
RESET <= '0';
wait for 0 ns;
when "write " => -- write di
readgen_ea(iline, idi, 16);
writetimestamp(oline, CLK_CYCLE, ": write");
write(oline, idi, right, 18);
writeline(output, oline);
CE <= '1';
WE <= '1';
DI <= idi;
isize := slv(unsigned(isize) + 1);
N_SIZE <= isize;
N_EMPTY <= '0';
if isize = "1111" then
N_FULL <= '1';
end if;
wait until rising_edge(CLK);
CE <= '0';
WE <= '0';
wait for 0 ns;
when "read " => -- read do
readgen_ea(iline, ido, 16);
CE <= '1';
WE <= '0';
isize := slv(unsigned(isize) - 1);
N_SIZE <= isize;
N_FULL <= '0';
if isize = "0000" then
N_EMPTY <= '1';
end if;
wait for c2out_time; -- check same cycle read response
writetimestamp(oline, CLK_CYCLE, ": read ");
write(oline, DO, right, 18);
if DO = ido then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, ido, right, 18);
end if;
writeline(output, oline);
wait until rising_edge(CLK);
CE <= '0';
wait for 0 ns;
when others => -- bad directive
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
end loop; -- file_loop:
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 20*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable iempty_1 : slbit := '1';
begin
loop
wait until rising_edge(CLK); -- at rising clock
R_EMPTY <= N_EMPTY; -- latch expected values
R_FULL <= N_FULL;
R_SIZE <= N_SIZE;
wait for c2out_time; -- after clock2output time check
if EMPTY='0' or iempty_1 ='0' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, DO, right, 18);
write(oline, EMPTY, right, 3);
write(oline, FULL, right, 2);
write(oline, SIZE, right, 6);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(SIZE)), right, 2);
write(oline, string'(")"));
if EMPTY /= R_EMPTY then
write(oline, string'(" FAIL EMPTY exp="));
write(oline, R_EMPTY);
end if;
if FULL /= R_FULL then
write(oline, string'(" FAIL FULL exp="));
write(oline, R_FULL);
end if;
if SIZE /= R_SIZE then
write(oline, string'(" FAIL SIZE exp="));
write(oline, R_SIZE);
end if;
writeline(output, oline);
end if;
iempty_1 := EMPTY;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | 5d4a1e09fe9796efe6b163ba54083212 | 0.484218 | 3.960202 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/xtea/xtea.vhd | 1 | 5,115 | --XTEA encryption algorithm v0.3
--Sergio Johann Filho, 2016
--
--based on reference code (below) released into the public domain by David Wheeler and Roger Needham
--the code takes 64 bits of data in v[0] and v[1] and 128 bits of key in key[0] - key[3]
--recommended number of rounds is 32 (2 Feistel-network rounds are performed on each iteration).
--
--
--void encipher(uint32_t num_rounds, uint32_t v[2], uint32_t const key[4]){
-- uint32_t i;
-- uint32_t v0 = v[0], v1 = v[1], sum = 0, delta = 0x9E3779B9;
--
-- for (i = 0; i < num_rounds; i++){
-- v0 += (((v1 << 4) ^ (v1 >> 5)) + v1) ^ (sum + key[sum & 3]);
-- sum += delta;
-- v1 += (((v0 << 4) ^ (v0 >> 5)) + v0) ^ (sum + key[(sum>>11) & 3]);
-- }
-- v[0] = v0; v[1] = v1;
--}
--
--void decipher(uint32_t num_rounds, uint32_t v[2], uint32_t const key[4]){
-- uint32_t i;
-- uint32_t v0 = v[0], v1 = v[1], delta = 0x9E3779B9, sum = delta * num_rounds;
--
-- for (i = 0; i < num_rounds; i++){
-- v1 -= (((v0 << 4) ^ (v0 >> 5)) + v0) ^ (sum + key[(sum>>11) & 3]);
-- sum -= delta;
-- v0 -= (((v1 << 4) ^ (v1 >> 5)) + v1) ^ (sum + key[sum & 3]);
-- }
-- v[0] = v0; v[1] = v1;
--}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity xtea is
generic (
ROUNDS: integer := 32
);
port ( clock: in std_logic;
reset: in std_logic;
start: in std_logic;
encrypt: in std_logic;
key: in std_logic_vector(127 downto 0);
input: in std_logic_vector(63 downto 0);
output: out std_logic_vector(63 downto 0);
ready: out std_logic
);
end xtea;
architecture xtea_arch of xtea is
type states is (idle, enc_step1, enc_step2, enc_step3, dec_step1, dec_step2, dec_step3, key_sel1, key_sel2, done);
signal state: states;
signal v0, v1, sum, delta, key_sel: std_logic_vector(31 downto 0);
signal counter: std_logic_vector(7 downto 0);
begin
delta <= x"9e3779b9";
process(clock, reset)
begin
if reset = '1' then
v0 <= (others => '0');
v1 <= (others => '0');
sum <= (others => '0');
key_sel <= (others => '0');
counter <= (others => '0');
output <= (others => '0');
ready <= '0';
elsif clock'event and clock = '1' then
case state is
when idle =>
ready <= '0';
counter <= (others => '0');
when key_sel1 =>
case sum(1 downto 0) is
when "00" =>
key_sel <= key(127 downto 96);
when "01" =>
key_sel <= key(95 downto 64);
when "10" =>
key_sel <= key(63 downto 32);
when "11" =>
key_sel <= key(31 downto 0);
when others => null;
end case;
when key_sel2 =>
case sum(12 downto 11) is
when "00" =>
key_sel <= key(127 downto 96);
when "01" =>
key_sel <= key(95 downto 64);
when "10" =>
key_sel <= key(63 downto 32);
when "11" =>
key_sel <= key(31 downto 0);
when others => null;
end case;
when enc_step1 =>
v1 <= input(31 downto 0);
v0 <= input(63 downto 32);
sum <= (others => '0');
when enc_step2 =>
v0 <= v0 + ((((v1(27 downto 0) & "0000") xor ("00000" & v1(31 downto 5))) + v1) xor (sum + key_sel));
sum <= sum + delta;
when enc_step3 =>
v1 <= v1 + ((((v0(27 downto 0) & "0000") xor ("00000" & v0(31 downto 5))) + v0) xor (sum + key_sel));
counter <= counter + 1;
when dec_step1 =>
v1 <= input(31 downto 0);
v0 <= input(63 downto 32);
sum <= x"c6ef3720";
when dec_step2 =>
v1 <= v1 - ((((v0(27 downto 0) & "0000") xor ("00000" & v0(31 downto 5))) + v0) xor (sum + key_sel));
sum <= sum - delta;
when dec_step3 =>
v0 <= v0 - ((((v1(27 downto 0) & "0000") xor ("00000" & v1(31 downto 5))) + v1) xor (sum + key_sel));
counter <= counter + 1;
when done =>
output(63 downto 32) <= v0;
output(31 downto 0) <= v1;
ready <= '1';
when others => null;
end case;
end if;
end process;
process(clock, reset, state, counter, start, encrypt)
begin
if reset = '1' then
state <= idle;
elsif clock'event and clock = '1' then
case state is
when idle =>
if (start = '1') then
if (encrypt = '1') then
state <= enc_step1;
else
state <= dec_step1;
end if;
else
state <= idle;
end if;
when key_sel1 =>
if (encrypt = '1') then
state <= enc_step2;
else
state <= dec_step3;
end if;
when key_sel2 =>
if (encrypt = '1') then
state <= enc_step3;
else
state <= dec_step2;
end if;
when enc_step1 => state <= key_sel1;
when enc_step2 => state <= key_sel2;
when enc_step3 =>
if (counter < ROUNDS-1) then
state <= key_sel1;
else
state <= done;
end if;
when dec_step1 => state <= key_sel2;
when dec_step2 => state <= key_sel1;
when dec_step3 =>
if (counter < ROUNDS-1) then
state <= key_sel2;
else
state <= done;
end if;
when done =>
if (start = '1') then
state <= done;
else
state <= idle;
end if;
when others => null;
end case;
end if;
end process;
end xtea_arch;
| gpl-2.0 | cf184e8fb5d36fcff4d5cee6d4cf1feb | 0.536657 | 2.647516 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop2_n4.vhd | 1 | 3,773 | -- $Id: tb_tst_serloop2_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n4 - sim
-- Description: Test bench for sys_tst_serloop2_n4
--
-- Dependencies: simlib/simclk
-- xlib/sfs_gsim_core
-- sys_tst_serloop2_n4 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n4
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.1.1 use sfs_gsim_core
-- 2016-09-03 805 1.1 remove CLK_STOP logic (simstop via report)
-- 2016-04-09 760 1.0 Initial version (cloned from tb_tst_serloop1_n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
use work.sys_conf.all;
entity tb_tst_serloop2_n4 is
end tb_tst_serloop2_n4;
architecture sim of tb_tst_serloop2_n4 is
signal CLK100 : slbit := '0';
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
GEN_CLKSYS : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide)
port map (
CLKIN => CLK100,
CLKFX => CLKH,
LOCKED => open
);
GEN_CLKSER : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLK100,
CLKFX => CLKS,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n4
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => '1',
O_LED => open,
O_RGBLED0 => open,
O_RGBLED1 => open,
O_ANO_N => open,
O_SEG_N => open
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => RTS_N,
P0_CTS_N => CTS_N,
P1_RXD => open, -- port 1 unused for n4 !
P1_TXD => '0',
P1_RTS_N => '0',
P1_CTS_N => open,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
RTS_N <= O_RTS_N after delay_time;
I_CTS_N <= CTS_N after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | 15f29877595970fb80cf40fcd82a31e7 | 0.511529 | 3.170588 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/sfs_gsim_core.vhd | 1 | 3,066 | -- $Id: sfs_gsim_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sfs_gsim_core - sim
-- Description: simple frequency synthesis (SIM only!)
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2015.4-2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0 Initial version (derived from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity sfs_gsim_core is -- frequency synthesis for simulation
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1); -- output divide
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end sfs_gsim_core;
architecture sim of sfs_gsim_core is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : Delay_length := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : Delay_length := 0 ns;
variable t_period : Delay_length := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "sfs_gsim_core: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := VCO_DIVIDE * OUT_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to VCO_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= VCO_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
end sim;
| gpl-3.0 | 1f9a7c710f276e5d533d230d49d07444 | 0.526419 | 3.910714 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/iob_reg_o.vhd | 1 | 1,417 | -- $Id: iob_reg_o.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, output only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_o is -- registered IOB, output
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end iob_reg_o;
architecture syn of iob_reg_o is
begin
IOB : iob_reg_o_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DO(0) => DO,
PAD(0) => PAD
);
end syn;
| gpl-3.0 | 5a0fbf552230a314e0bc86fc2e4cc763 | 0.475653 | 3.524876 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd | 1 | 1,757 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 | 54dcf5f97d467cf0238151a2a9a6648d | 0.62436 | 3.535211 | false | false | false | false |
nsensfel/tabellion | data/test/CNE_00100/invalid.vhd | 1 | 1,589 | library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0: in std_logic;
ip1: in std_logic;
ip2: in std_logic;
ip3: in std_logic;
op0: out std_logic;
op1: out std_logic;
op2: out std_logic;
op3: out std_logic
);
end;
architecture RTL of valid is
signal s0: std_logic;
signal s1: std_logic;
signal s2: std_logic;
signal s3: std_logic;
begin
op0 <= ip1 when (ip0 = '0') else ip2;
op0 <= ip1 when (ip0 = '1') else ip2;
process (s1, ip1, s2)
begin
if (ip1 = '0')
then
op0 <= '0';
else
op0 <= s2;
end if;
if (ip1 = '0')
then
op1 <= s1;
else
op1 <= '1';
end if;
end process;
process (s1, ip1, s2)
begin
if (ip1 = '1')
then
op0 <= '0';
else
op0 <= s2;
end if;
if (ip1 = '0')
then
op1 <= s1;
else
op1 <= '1';
end if;
end process;
s3 <= s1 when (s0 = '0') else s2;
s3 <= s1 when (s0 = '1') else s2;
process (s1, ip1, s2)
begin
if (s1 = '0')
then
op0 <= '0';
else
op0 <= s2;
end if;
if (s1 = '0')
then
op1 <= ip1;
else
op1 <= '1';
end if;
end process;
process (s1, ip1, s2)
begin
if (s1 = '1')
then
op0 <= '0';
else
op0 <= s2;
end if;
if (s1 = '0')
then
op1 <= ip1;
else
op1 <= '1';
end if;
end process;
end architecture;
| apache-2.0 | 211477f9ffc990fdcf86dbc1f161072d | 0.42983 | 2.926335 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | memData.vhd | 1 | 7,118 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: memData.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY memData IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END memData;
ARCHITECTURE SYN OF memdata IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "memData.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 10,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "memData.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "memData.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL memData.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memData.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memData.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memData.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memData_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| mit | beaf419a00dde71ab6262ad870cc6055 | 0.655662 | 3.489216 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01600_bad.vhd | 1 | 3,858 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01600_bad.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of package element: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity CNE_01600_good is
port (
i_Clock : in std_logic; -- Global clock signal
i_Reset_n : in std_logic; -- Global reset signal
i_Raz : in std_logic; -- Reset counting and load length
i_Enable : in std_logic; -- Enable the counter
i_Length : in std_logic_vector(Width downto 0); -- How much the module should count (Value expected - 1)
o_Done : out std_logic -- Counter output
);
end CNE_01600_good;
architecture Behavioral of CNE_01600_good is
signal Count : signed(Width downto 0); -- Counting signal
signal Length : signed(Width downto 0); -- How much the module should count
signal Done : std_logic; -- Counter output
begin
P_Count:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
Count <= (others => '0');
Length <= (others => '0');
Done <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Raz='1') then
-- Reset the counting
Length <= signed(i_Length);
Count <= (others => '0');
elsif (i_Enable='1' and Done='0') then
-- Counter activated and not finished
Count <= Count + 1;
end if;
if (Count>=Length) then -- Compared elements are of the same type and dimension
-- Counter finished
Done <= '1';
else
Done <= '0';
end if;
end if;
end process;
o_Done <= Done;
end Behavioral; | gpl-3.0 | 35d02dfa19c4d74c0792bcb04e20c263 | 0.479264 | 4.704878 | false | false | false | false |
rad-/VHDL-Pong | KeyboardController.vhd | 1 | 2,419 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity KeyboardController is
Port ( Clock : in STD_LOGIC;
KeyboardClock : in STD_LOGIC;
KeyboardData : in STD_LOGIC;
LeftPaddleDirection : inout integer;
RightPaddleDirection : inout integer
);
end KeyboardController;
architecture Behavioral of KeyboardController is
signal bitCount : integer range 0 to 100 := 0;
signal scancodeReady : STD_LOGIC := '0';
signal scancode : STD_LOGIC_VECTOR(7 downto 0);
signal breakReceived : STD_LOGIC := '0';
constant keyboardA : STD_LOGIC_VECTOR(7 downto 0) := "00011100";
constant keyboardZ : STD_LOGIC_VECTOR(7 downto 0) := "00011010";
constant keyboardK : STD_LOGIC_VECTOR(7 downto 0) := "01000010";
constant keyboardM : STD_LOGIC_VECTOR(7 downto 0) := "00111010";
begin
keyboard_scan_ready_enable : process(KeyboardClock)
begin
if falling_edge(KeyboardClock) then
if bitCount = 0 and KeyboardData = '0' then --keyboard wants to send data
scancodeReady <= '0';
bitCount <= bitCount + 1;
elsif bitCount > 0 and bitCount < 9 then -- shift one bit into the scancode from the left
scancode <= KeyboardData & scancode(7 downto 1);
bitCount <= bitCount + 1;
elsif bitCount = 9 then -- parity bit
bitCount <= bitCount + 1;
elsif bitCount = 10 then -- end of message
scancodeReady <= '1';
bitCount <= 0;
end if;
end if;
end process keyboard_scan_ready_enable;
scan_keyboard : process(scancodeReady, scancode)
begin
if scancodeReady'event and scancodeReady = '1' then
-- breakcode breaks the current scancode
if breakReceived = '1' then
breakReceived <= '0';
if scancode = keyboardA or scancode = keyboardY then
LeftPaddleDirection <= 0;
elsif scancode = keyboardK or scancode = keyboardM then
RightPaddleDirection <= 0;
end if;
elsif breakReceived = '0' then
-- scancode processing
if scancode = "11110000" then
-- mark break for next scancode
breakReceived <= '1';
end if;
if scancode = keyboardA then
LeftPaddleDirection <= -1;
elsif scancode = keyboardY then
LeftPaddleDirection <= 1;
elsif scancode = keyboardK then
RightPaddleDirection <= -1;
elsif scancode = keyboardM then
RightPaddleDirection <= 1;
end if;
end if;
end if;
end process scan_keyboard;
end Behavioral;
| mit | fe7f056551fd0598edf99c0a4b547a8c | 0.689128 | 3.670713 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/gray_cnt_5.vhd | 1 | 4,216 | -- $Id: gray_cnt_5.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_5 - syn
-- Description: 5 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-07 840 1.1 disable fsm recognition in vivado
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 9 5 302MHz/ 3.31ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end entity gray_cnt_5;
architecture syn of gray_cnt_5 is
signal R_DATA : slv5 := (others=>'0');
signal N_DATA : slv5 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm
-- is inferred, using 'Johnson' encoding. DATA will be deduced
-- in a combinatorial logic, and will thus have very likely some
-- glitches at the clock transitions, rendering the whole Gray
-- coding useless.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
-- Note: vivado started with -fsm_extraction one_hot didn't fsm recognize
-- this code up to 2016.2. With 2016.3 and later it is converted into a
-- 31 state one-hot fsm, unless explicitely suppressed
attribute fsm_encoding : string;
attribute fsm_encoding of R_DATA : signal is "none";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
N_DATA <= (others=>'0');
case R_DATA is
when "00000" => N_DATA <= "00001"; -- 0
when "00001" => N_DATA <= "00011"; -- 1
when "00011" => N_DATA <= "00010"; -- 2
when "00010" => N_DATA <= "00110"; -- 3
when "00110" => N_DATA <= "00111"; -- 4
when "00111" => N_DATA <= "00101"; -- 5
when "00101" => N_DATA <= "00100"; -- 6
when "00100" => N_DATA <= "01100"; -- 7
when "01100" => N_DATA <= "01101"; -- 8
when "01101" => N_DATA <= "01111"; -- 9
when "01111" => N_DATA <= "01110"; -- 10
when "01110" => N_DATA <= "01010"; -- 11
when "01010" => N_DATA <= "01011"; -- 12
when "01011" => N_DATA <= "01001"; -- 13
when "01001" => N_DATA <= "01000"; -- 14
when "01000" => N_DATA <= "11000"; -- 15
when "11000" => N_DATA <= "11001"; -- 16
when "11001" => N_DATA <= "11011"; -- 17
when "11011" => N_DATA <= "11010"; -- 18
when "11010" => N_DATA <= "11110"; -- 19
when "11110" => N_DATA <= "11111"; -- 20
when "11111" => N_DATA <= "11101"; -- 21
when "11101" => N_DATA <= "11100"; -- 22
when "11100" => N_DATA <= "10100"; -- 23
when "10100" => N_DATA <= "10101"; -- 24
when "10101" => N_DATA <= "10111"; -- 25
when "10111" => N_DATA <= "10110"; -- 26
when "10110" => N_DATA <= "10010"; -- 27
when "10010" => N_DATA <= "10011"; -- 28
when "10011" => N_DATA <= "10001"; -- 29
when "10001" => N_DATA <= "10000"; -- 30
when "10000" => N_DATA <= "00000"; -- 31
when others => null;
end case;
end process proc_next;
DATA <= R_DATA;
end syn;
| gpl-3.0 | 0ef87c1449b5ee38dd420c0adfade51f | 0.509013 | 3.351351 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01700_good.vhd | 1 | 2,993 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01700_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of rising edge detection signal: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01700_good is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Signal on which detect edges
o_D_re : out std_logic -- Rising edge of i_D
);
end CNE_01700_good;
architecture Behavioral of CNE_01700_good is
signal D_r1 : std_logic; -- i_D registered 1 time
signal D_r2 : std_logic; -- i_D registered 2 times
begin
-- Rising edge detection process
P_detection: process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D_r1 <= '0';
D_r2 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
D_r2 <= D_r1;
end if;
end process;
o_D_re <= D_r1 and not D_r2;
end Behavioral;
--CODE | gpl-3.0 | cca68223223a155b489328651f969391 | 0.487137 | 4.369343 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/bp_rs232_2line_iob.vhd | 1 | 1,848 | -- $Id: bp_rs232_2line_iob.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2line_iob - syn
-- Description: iob's for 2 line rs232 (RXD,TXD only)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 Moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_int)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit -- pad-o: transmit data (board view)
);
end bp_rs232_2line_iob;
architecture syn of bp_rs232_2line_iob is
begin
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
end syn;
| gpl-3.0 | 75ea86858237cc666d9091f3ed07d016 | 0.484848 | 3.434944 | false | false | false | false |
sjohann81/hf-risc | riscv/sim/ram.vhd | 2 | 1,715 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity bram is
generic(memory_file : string := "code.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 16; -- address width
bank: integer := 0); -- memory bank (0,1,2,3)
port(
clk : in std_logic; --clock
addr : in std_logic_vector(address_width - 1 downto 2); --address bus
cs_n : in std_logic; --chip select
we_n : in std_logic; --write enable
data_i: in std_logic_vector(data_width - 1 downto 0); --write data bus
data_o: out std_logic_vector(data_width - 1 downto 0) --read data bus
);
end bram;
architecture memory of bram is
type ram is array(2 ** address_width -1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal ram1 : ram := (others => (others => '0'));
begin
process(clk)
variable data : std_logic_vector(data_width*4 -1 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is "code.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
readline(load_file, hex_file_line);
hread(hex_file_line, data);
ram1(conv_integer(index)) <= data(((bank+1)*data_width)-1 downto bank*data_width);
index := index + 1;
end loop;
end if;
if (clk'event and clk = '1') then
if(cs_n = '0') then
if(we_n = '0') then
ram1(conv_integer(addr(address_width -1 downto 2))) <= data_i;
else
data_o <= ram1(conv_integer(addr(address_width -1 downto 2)));
end if;
end if;
end if;
end process;
end memory;
| gpl-2.0 | 6eda3e611b64de289cbf8bcd37bb5708 | 0.644315 | 2.816092 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/ieee_proposed/float_pkg_c.vhd | 3 | 259,105 | ------------------------------------------------------------------------------
-- "float_pkg" package contains functions for floating point math.
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.float_pkg.all;
-- Last Modified: $Date: 2006/05/09 19:21:24 $
-- RCS ID: $Id: float_pkg_c.vhd,v 1.1 2006/05/09 19:21:24 sandeepd Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee, ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.fixed_pkg.all;
-- synthesis translate_off
use std.textio.all;
-- synthesis translate_on
package float_pkg is
--%%% Uncomment the Generics
-- new work.fixed_generic_pkg
-- generic map (
-- float_exponent_width => 8; -- float32'high
-- float_fraction_width => 23; -- -float32'low
-- float_round_style => round_nearest; -- round nearest algorithm
-- float_denormalize => true; -- Use IEEE extended floating
-- float_check_error => true; -- Turn on NAN and overflow processing
-- float_guard_bits => 3; -- number of guard bits
-- no_warning => false -- show warnings
-- );
--%%% REMOVE THE REST OF THIS FILE.
constant float_exponent_width : NATURAL := 8; -- float32'high
constant float_fraction_width : NATURAL := 23; -- -float32'low
constant float_round_style : round_type := round_nearest; -- round nearest algorithm
constant float_denormalize : BOOLEAN := true; -- Use IEEE extended floating
-- point (Denormalized numbers)
constant float_check_error : BOOLEAN := true; -- Turn on NAN and overflow processing
constant float_guard_bits : NATURAL := 3; -- number of guard bits
constant NO_WARNING : BOOLEAN := false;
-- Author David Bishop ([email protected])
constant CopyRightNotice : STRING :=
"Copyright 2005 by IEEE. All rights reserved.";
-- Note that the size of the vector is not defined here, but in
-- the package which calls this one.
type float is array (INTEGER range <>) of STD_LOGIC; -- main type
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
subtype float32 is float (8 downto -23); -- IEEE 754 single precision
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
subtype float64 is float (11 downto -52); -- IEEE 754 double precision
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
subtype float128 is float (15 downto -112); -- IEEE 854 & C extended precision
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handel approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- differed constant
-- Returns the class which X falls into
function Class (
x : float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : float) return float;
function "-" (arg : float) return float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : float) return float;
function "-" (l, r : float) return float;
function "*" (l, r : float) return float;
function "/" (l, r : float) return float;
function "rem" (l, r : float) return float;
function "mod" (l, r : float) return float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function subtract (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function multiply (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function divide (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function remainder (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function modulo (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
-- reciprocal
function reciprocal (
arg : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function dividebyp2 (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
-- Multiply accumumlate result = l*r + c
function mac (
l, r, c : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function Is_Negative (arg : float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
-- These functions are intentionally not implemented in this package,
-- use the "fphdl_pkg" to get this funcitonality.
function eq ( -- equal =
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : float) return BOOLEAN;
function "/=" (l, r : float) return BOOLEAN;
function ">=" (l, r : float) return BOOLEAN;
function "<=" (l, r : float) return BOOLEAN;
function ">" (l, r : float) return BOOLEAN;
function "<" (l, r : float) return BOOLEAN;
--%%% Uncomment the following (new syntax)
-- function "?=" (l, r : float) return STD_ULOGIC;
-- function "?\=" (l, r : float) return STD_ULOGIC;
-- function "?>" (l, r : float) return STD_ULOGIC;
-- function "?>=" (l, r : float) return STD_ULOGIC;
-- function "?<" (l, r : float) return STD_ULOGIC;
-- function "?<=" (l, r : float) return STD_ULOGIC;
--%%% remove the following (old syntax)
function \?=\ (l, r : float) return STD_ULOGIC;
function \?/=\ (l, r : float) return STD_ULOGIC;
function \?>\ (l, r : float) return STD_ULOGIC;
function \?>=\ (l, r : float) return STD_ULOGIC;
function \?<\ (l, r : float) return STD_ULOGIC;
function \?<=\ (l, r : float) return STD_ULOGIC;
function std_match (l, r : float) return BOOLEAN;
function find_lsb (arg : float; y : STD_ULOGIC) return INTEGER;
function find_msb (arg : float; y : STD_ULOGIC) return INTEGER;
function maximum (l, r : float) return float;
function minimum (l, r : float) return float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function resize (
arg : float; -- Floating point input
size_res : float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function to_float32 (
arg : float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function to_float64 (
arg : float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
function to_float128 (
arg : float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : float) return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [float return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [float return STD_LOGIC_VECTOR];
-- Converts an fp into an SULV
function to_sulv (arg : float) return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [float return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [float return STD_ULOGIC_VECTOR];
-- std_logic_vector to float
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return float;
-- signed to float
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return float;
-- unsigned fixed point to float
function to_float (
arg : ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extentions
return float;
-- signed fixed point to float
function to_float (
arg : sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : float;
constant round_style : round_type := float_round_style) -- rounding option
return float;
-- real to float
function to_float (
arg : REAL;
size_res : float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : float;
constant round_style : round_type := float_round_style) -- rounding option
return float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : float;
constant round_style : round_type := float_round_style) -- rounding option
return float;
-- slv to float
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : float)
return float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : float)
return float;
-- unsigned fixed point to float
function to_float (
arg : ufixed; -- unsigned fixed point input
size_res : float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extentions
return float;
-- signed fixed point to float
function to_float (
arg : sfixed;
size_res : float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return float;
-- float to unsigned
function to_unsigned (
arg : float; -- floating point input
constant size : NATURAL; -- length of output
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return UNSIGNED;
-- float to signed
function to_signed (
arg : float; -- floating point input
constant size : NATURAL; -- length of output
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant round_style : BOOLEAN := fixed_round_style; -- rounding
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return ufixed;
-- float to signed fixed point
function to_sfixed (
arg : float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant round_style : BOOLEAN := fixed_round_style; -- rounding
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : float; -- floating point input
size_res : UNSIGNED;
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return UNSIGNED;
-- float to signed
function to_signed (
arg : float; -- floating point input
size_res : SIGNED;
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : float; -- fp input
size_res : ufixed;
constant round_style : BOOLEAN := fixed_round_style; -- rounding
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return ufixed;
-- float to signed fixed point
function to_sfixed (
arg : float; -- fp input
size_res : sfixed;
constant round_style : BOOLEAN := fixed_round_style; -- rounding
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return sfixed;
-- float to real
function to_real (
arg : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return INTEGER;
-- Maps metalogical values
function to_01 (
arg : float; -- floating point input
XMAP : STD_LOGIC := '0')
return float;
function Is_X (arg : float) return BOOLEAN;
function to_X01 (arg : float) return float;
function to_X01Z (arg : float) return float;
function to_UX01 (arg : float) return float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponend is biased by -1
procedure break_number (
arg : in float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- a number between 1.0 and 2.0
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponend is assumed to be biased by -1
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return float;
-- Exponend is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return float;
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return float;
-- Exponend is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return float;
-- overloaded versions
function "+" (l : float; r : REAL) return float;
function "+" (l : REAL; r : float) return float;
function "+" (l : float; r : INTEGER) return float;
function "+" (l : INTEGER; r : float) return float;
function "-" (l : float; r : REAL) return float;
function "-" (l : REAL; r : float) return float;
function "-" (l : float; r : INTEGER) return float;
function "-" (l : INTEGER; r : float) return float;
function "*" (l : float; r : REAL) return float;
function "*" (l : REAL; r : float) return float;
function "*" (l : float; r : INTEGER) return float;
function "*" (l : INTEGER; r : float) return float;
function "/" (l : float; r : REAL) return float;
function "/" (l : REAL; r : float) return float;
function "/" (l : float; r : INTEGER) return float;
function "/" (l : INTEGER; r : float) return float;
function "rem" (l : float; r : REAL) return float;
function "rem" (l : REAL; r : float) return float;
function "rem" (l : float; r : INTEGER) return float;
function "rem" (l : INTEGER; r : float) return float;
function "mod" (l : float; r : REAL) return float;
function "mod" (l : REAL; r : float) return float;
function "mod" (l : float; r : INTEGER) return float;
function "mod" (l : INTEGER; r : float) return float;
function "=" (l : float; r : REAL) return BOOLEAN;
function "/=" (l : float; r : REAL) return BOOLEAN;
function ">=" (l : float; r : REAL) return BOOLEAN;
function "<=" (l : float; r : REAL) return BOOLEAN;
function ">" (l : float; r : REAL) return BOOLEAN;
function "<" (l : float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : float) return BOOLEAN;
function "/=" (l : REAL; r : float) return BOOLEAN;
function ">=" (l : REAL; r : float) return BOOLEAN;
function "<=" (l : REAL; r : float) return BOOLEAN;
function ">" (l : REAL; r : float) return BOOLEAN;
function "<" (l : REAL; r : float) return BOOLEAN;
function "=" (l : float; r : INTEGER) return BOOLEAN;
function "/=" (l : float; r : INTEGER) return BOOLEAN;
function ">=" (l : float; r : INTEGER) return BOOLEAN;
function "<=" (l : float; r : INTEGER) return BOOLEAN;
function ">" (l : float; r : INTEGER) return BOOLEAN;
function "<" (l : float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : float) return BOOLEAN;
function "/=" (l : INTEGER; r : float) return BOOLEAN;
function ">=" (l : INTEGER; r : float) return BOOLEAN;
function "<=" (l : INTEGER; r : float) return BOOLEAN;
function ">" (l : INTEGER; r : float) return BOOLEAN;
function "<" (l : INTEGER; r : float) return BOOLEAN;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : float) return float;
function "and" (L, R : float) return float;
function "or" (L, R : float) return float;
function "nand" (L, R : float) return float;
function "nor" (L, R : float) return float;
function "xor" (L, R : float) return float;
function "xnor" (L, R : float) return float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : float) return float;
function "and" (L : float; R : STD_ULOGIC) return float;
function "or" (L : STD_ULOGIC; R : float) return float;
function "or" (L : float; R : STD_ULOGIC) return float;
function "nand" (L : STD_ULOGIC; R : float) return float;
function "nand" (L : float; R : STD_ULOGIC) return float;
function "nor" (L : STD_ULOGIC; R : float) return float;
function "nor" (L : float; R : STD_ULOGIC) return float;
function "xor" (L : STD_ULOGIC; R : float) return float;
function "xor" (L : float; R : STD_ULOGIC) return float;
function "xnor" (L : STD_ULOGIC; R : float) return float;
function "xnor" (L : float; R : STD_ULOGIC) return float;
-- Reduction operators, same as numeric_std functions
-- %%% remove 6 functions (old syntax)
function and_reduce (arg : float) return STD_ULOGIC;
function nand_reduce (arg : float) return STD_ULOGIC;
function or_reduce (arg : float) return STD_ULOGIC;
function nor_reduce (arg : float) return STD_ULOGIC;
function xor_reduce (arg : float) return STD_ULOGIC;
function xnor_reduce (arg : float) return STD_ULOGIC;
-- %%% Uncomment the following 6 functions (new syntax)
-- function "and" (arg : float) RETURN std_ulogic;
-- function "nand" (arg : float) RETURN std_ulogic;
-- function "or" (arg : float) RETURN std_ulogic;
-- function "nor" (arg : float) RETURN std_ulogic;
-- function "xor" (arg : float) RETURN std_ulogic;
-- function "xnor" (arg : float) RETURN std_ulogic;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-- Note: "find_msb" and "find_lsb" not implemented, use "logb".
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : float) return float;
-- Returns y * 2**n for intergral values of N without computing 2**n
function Scalb (
y : float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
-- Returns y * 2**n for intergral values of N without computing 2**n
function Scalb (
y : float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float;
-- returns the unbiased exponent of x
function Logb (x : float) return INTEGER;
function Logb (x : float) return SIGNED;
-- returns the next represtable neighbor of x in the direction toward y
function Nextafter (
x, y : float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : float) return BOOLEAN;
function Finite (x : float) return BOOLEAN;
function Isnan (x : float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float;
-- size_res versions
function zerofp (
size_res : float) -- variable is only use for sizing
return float;
function nanfp (
size_res : float) -- variable is only use for sizing
return float;
function qnanfp (
size_res : float) -- variable is only use for sizing
return float;
function pos_inffp (
size_res : float) -- variable is only use for sizing
return float;
function neg_inffp (
size_res : float) -- variable is only use for sizing
return float;
function neg_zerofp (
size_res : float) -- variable is only use for sizing
return float;
-- synthesis translate_off
-- rtl_synthesis off
-- impure functions
-- writes S:EEEE:FFFFFFFF
procedure write (
L : inout LINE; -- access type (pointer)
VALUE : in float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ(L : inout LINE; VALUE : out float);
procedure READ(L : inout LINE; VALUE : out float; GOOD : out BOOLEAN);
alias bread is READ [LINE, float, BOOLEAN];
alias bread is READ [LINE, float];
alias bwrite is WRITE [LINE, float, SIDE, WIDTH];
procedure owrite (
L : inout LINE; -- access type (pointer)
VALUE : in float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no seperaters used
procedure OREAD(L : inout LINE; VALUE : out float);
procedure OREAD(L : inout LINE; VALUE : out float; GOOD : out BOOLEAN);
-- Hex write with padding, no seperators
procedure hwrite (
L : inout LINE; -- access type (pointer)
VALUE : in float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no seperaters used
procedure HREAD(L : inout LINE; VALUE : out float);
procedure HREAD(L : inout LINE; VALUE : out float; GOOD : out BOOLEAN);
-- returns "S:EEEE:FFFFFFFF"
function to_string (
value : float;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
-- Returns a HEX string, with padding
function to_hstring (
value : float;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
-- Returns and octal string, with padding
function to_ostring (
value : float;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL return float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return float;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return float;
function from_string (
bstring : STRING; -- binary string
size_res : float) -- used for sizing only
return float;
alias from_bstring is from_string [STRING, float return float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : float) -- used for sizing only
return float;
function from_hstring (
hstring : STRING; -- hex string
size_res : float) -- used for sizing only
return float;
-- synthesis translate_on
-- rtl_synthesis on
function to_StdLogicVector (arg : float) return std_logic_vector ;
function to_Std_Logic_Vector (arg : float) return std_logic_vector;
function to_StdULogicVector (arg : float) return std_ulogic_vector ;
function to_Std_ULogic_Vector (arg : float) return std_ulogic_vector;
end package float_pkg;
library ieee;
use ieee.math_real.all;
use ieee.std_logic_textio.all; -- %%% for testing only
package body float_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- differed constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : float (0 downto 1) := (others => '0');
constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-- %%% These functions can be removed in the final release.
-- %%% Replace and_reducex with "and" (and all similar _reducex functions)
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1'; -- Change for version 1.3
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reducex (BUS_int (BUS_int'left downto Half));
Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reducex;
function and_reducex (arg : UNSIGNED)
return STD_LOGIC is
begin
return and_reducex (STD_LOGIC_VECTOR (arg));
end function and_reducex;
-- purpose: OR all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function or_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reducex (BUS_int (BUS_int'left downto Half));
Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reducex;
function or_reducex (arg : UNSIGNED)
return STD_LOGIC is
begin
return or_reducex (STD_LOGIC_VECTOR (arg));
end function or_reducex;
function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reducex (BUS_int (BUS_int'left downto Half));
Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reducex;
-- purpose: To find the largest of 2 numbers
-- %%% Will be implicit in VHDL-200X
function maximum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
-- purpose: Find the first "1" is a vector, starting from the MSB
-- %%% This is a copy of the proposed "find_msb" from 1076.3
function find_msb (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop : for i in xarg'range loop
if xarg(i) = y then
return i;
end if;
end loop;
return -1;
end function find_msb;
-- %%% End remove
-- Special version of "minimum" to do some boundary checking
function minx (l, r : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report "FLOAT_GENERIC_PKG: Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
if L > R then return R;
else return L;
end if;
end function minx;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- purpose: Test the boundary conditions of a Real number
-- function test_boundary (
-- arg : REAL; -- Input, converted to real
-- constant fraction_width : NATURAL; -- length of FP output fraction
-- constant exponent_width : NATURAL; -- length of FP exponent
-- constant denormalize : BOOLEAN := true) -- Use IEEE extended FP
-- return boundary_type is
-- constant expon_base : SIGNED (exponent_width-1 downto 0) :=
-- gen_expon_base(exponent_width); -- exponent offset
-- constant exp_min : SIGNED (12 downto 0) :=
-- -(resize(expon_base, 13)) +1; -- Minimum normal exponent
-- constant exp_ext_min : SIGNED (12 downto 0) :=
-- exp_min - fraction_width; -- Minimum for denormal exponent
-- begin -- function test_boundary
-- -- Check to see if the exponent is big enough
-- -- Note that the argument is always an absolute value at this point.
-- if arg = 0.0 then
-- return zero;
-- elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
-- return normal;
-- else
-- if arg < 2.0 ** to_integer(exp_min) then
-- if denormalize then
-- if arg < 2.0 ** to_integer(exp_ext_min) then
-- return zero;
-- else
-- return denormal;
-- end if;
-- else
-- if arg < 2.0 ** to_integer(exp_min-1) then
-- return zero;
-- else
-- return normal; -- Can still represent this number
-- end if;
-- end if;
-- elsif exponent_width < 11 then
-- if arg >= 2.0 ** (to_integer(expon_base)+1) then
-- return infinity;
-- else
-- return normal;
-- end if;
-- else
-- return normal;
-- end if;
-- end if;
-- end function test_boundary;
-- Some synthesis tools don't like this function, so do it this way
-- (ignoring denormal and infinite numbers)
function test_boundary (
arg : REAL; -- Input, converted to real
constant fraction_width : NATURAL; -- length of FP output fraction
constant exponent_width : NATURAL; -- length of FP exponent
constant denormalize : BOOLEAN := true) -- Use IEEE extended FP
return boundary_type is
begin -- function test_boundary
if arg = 0.0 then
return zero;
else
return normal;
end if;
end function test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or_reducex (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or_reducex (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and_reducex(fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- Integer version of the "log2" command
-- Synthisable, used by to_float(integer) function
function log2(A : NATURAL) return NATURAL is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if (2**I > A) then return(I-1);
end if;
end loop;
return(30);
end function log2;
-- purpose: Look for the boundaries of the integer input
-- Synthisable
function fp_input_type (
arg : INTEGER; -- integer input
constant fraction_width : NATURAL; -- length of FP output fraction
constant exponent_width : NATURAL) -- length of FP output exponent
return boundary_type is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable maxint : INTEGER;
begin -- function fp_input_type
if arg = 0 then
return zero;
elsif exponent_width > 5 then -- largest possible integer = 2**31
return normal;
else
maxint := 2 ** (to_integer(expon_base)+1);
-- worry about infinity
if arg >= maxint then
return infinity;
else
return normal;
end if;
end if;
end function fp_input_type;
procedure break_number ( -- internal version
arg : in float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report "FLOAT_GENERIC_PKG.BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -minx(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or or_reducex (remainder (1 downto 0)));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a string, this funciton is here because
-- or_reducex (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : natural)
return std_ulogic is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_slv (
arg : float) -- fp vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR(arg'length - 1 downto 0);
variable slv : t;
begin -- function to_std_logic_vector
if arg'length < 1 then
return NSLV;
end if;
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(31) := arg (31-23)
-- end loop floop;
return slv;
end function to_slv;
-- Converts an fp into an SULV
function to_sulv (arg : float) return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return float is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
begin -- function normalize
result (exponent_width) := sign; -- sign bit
round := false;
shiftr := find_msb (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or_reducex(fract) = '0') then -- Zero
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length);
shiftr := to_integer (expon + expon_base); -- new shift
sfract := fract sll shiftr; -- shift
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp;
end if;
rexpon := UNSIGNED ((rexp(exponent_width-1 downto 0))-1);
rexpon(exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := float(rexpon);
result (-1 downto -fraction_width) := float(rfract);
else -- return zero
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
elsif (exp > expon_base-1) then -- infinity
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign; -- redo sign bit for neg inf.
else -- normal number
sfract := fract srl shiftr; -- shift
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => sticky,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon(exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := float(rexpon);
result (-1 downto -fraction_width) := float(rfract);
end if;
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return float is
variable result : float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
for i in arguns'high downto maximum (arguns'high-fract'length+1, 0) loop
arguns (i) := fract (fract'high + (i-arguns'high));
end loop;
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return float is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
for i in arguns'high downto maximum (arguns'high-fract'length+1, 0) loop
arguns (i) := fract (fract'high + (i-arguns'high));
end loop;
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
-- Synthisable
function Class (
x : float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate is
constant fraction_width : INTEGER := -minx(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : float (exponent_width downto -fraction_width);
begin -- class
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report "FLOAT_GENERIC_PKG.CLASS: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
and_reducex (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1' then -- Exponent is all "1".
if or_reducex (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or_reducex (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or_reducex (to_slv (arg(-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Class;
procedure break_number (
arg : in float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED;
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -minx(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fptyp : valid_fpstate;
variable exp : SIGNED (expon'range);
begin
fptyp := Class (arg, check_error);
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
sign := to_x01(arg(arg'high));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := to_01(SIGNED(arg(exponent_width-1 downto 0)), 'X');
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report "FLOAT_GENERIC_PKG.BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a meta state goes in, a meta state comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
procedure break_number (
arg : in float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- 1 downto -fraction_width
expon : out SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -minx(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fptyp : valid_fpstate;
variable exp : SIGNED (expon'range);
begin
fptyp := Class (arg, check_error);
for i in -1 downto -fraction_width loop
fract(i) := arg(i);
end loop;
sign := to_x01(arg(arg'high));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (0) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (0) := '0';
else
exp := -expon_base - 1;
fract (0) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (0) := '1';
exp := to_01(SIGNED(arg(exponent_width-1 downto 0)), 'X');
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report "FLOAT_GENERIC_PKG.BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a meta state goes in, a meta state comes out.
exp := (others => '1');
fract (0) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- Arithmetic functions
-- Synthisable
function "abs" (
arg : float) -- floating point input
return float is
variable result : float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
-- Synthisable
function "-" (
arg : float) -- floating point input
return float is
variable result : float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Synthisable
function add (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED(fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable shiftx : SIGNED(exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := class (lresize, false); -- errors already checked
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := class (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or_reducex (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or_reducex (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or_reducex (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or_reducex (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Calls "add".
-- Synthisable
function subtract (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
variable negr : float (r'range); -- negative version of r
begin
negr := -r; -- r := -r
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
function multiply (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED(fraction_width downto 0); -- fractions
variable rfract : UNSIGNED((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED(fraction_width+1+multguard downto 0); -- result fraction
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := class (lresize, false); -- errors already checked
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := class (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or_reducex(rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- add the exponents
rexpon := (exponl(exponl'high)&exponl) + (exponr(exponr'high)&exponr) +1;
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED is
-- This is a special divider for the floating point routies.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL := -minx(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsiged divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED(exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED(fraction_width downto 0);
variable fractg : UNSIGNED(fraction_width+divguard downto 0);
variable sfract : UNSIGNED(fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := class(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report "FLOAT_GENERIC_PKG.RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- execpt for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- Synthisable
function divide (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
-- variable fractl : unsigned((2*(fraction_width+1)+divguard+2) downto 0); -- left
variable fractl : UNSIGNED((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED(fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED(fractl'range); -- result fraction
variable sfract : UNSIGNED(fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report "FLOAT_GENERIC_PKG.DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := class (lresize, false); -- errors already checked
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := class (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_msb(urfract, '1');
fractr := shift_left (fractr, shifty);
rexpon := rexpon + shifty;
end if;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report "FLOAT_GENERIC_PKG.DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult(exponent_width) := l(exponent_width) xor r(exponent_width);
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := class (lresize, false); -- errors already checked
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := class (rresize, false); -- errors already checked
fp_sign := l(l'high) xor r(r'high); -- sign
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or_reducex (urfract (fraction_width-1 downto 0)) = '0')
report "FLOAT_GENERIC_PKG.DIVIDEBYP2: "
& "Divideby2 called with a none power of two denominator"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumumlate result = l*r + c
function mac (
l, r, c : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL :=
-minx (minx(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED(fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract, ufract : UNSIGNED(fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED(exponent_width-1 downto 0); -- exponents
variable shiftx : SIGNED(exponent_width downto 0); -- shift fractions
variable rexpon, rexpon2 : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : float (exponent_width downto -fraction_width);
variable cresize : float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
cfptype := class (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := class (lresize, false); -- errors already checked
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := class (rresize, false); -- errors already checked
cresize := resize (arg => c,
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := class (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := (exponl(exponl'high)&exponl) + (exponr(exponr'high)&exponr) +1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := exponc(exponent_width-1) & exponc;
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or_reducex (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := exponc(exponent_width-1) & exponc;
leftright := false;
sticky := or_reducex (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := exponc(exponent_width-1) & exponc;
sticky := or_reducex (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reducex (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reducex (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
function remainder (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED(fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED(fractr'range); -- result fraction
variable sfract : UNSIGNED(fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := class (lresize, false); -- errors already checked
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := class (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
function modulo (
l, r : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL := - minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : float (exponent_width downto -fraction_width);
variable remres : float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (is_negative (l)) then
remres := - remres;
end if;
if (is_negative (l) = is_negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
function Is_Negative (arg : float) return BOOLEAN is
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
-- Synthisable
function eq ( -- equal =
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
-- Synthisable
function lt ( -- less than <
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := to_01(UNSIGNED(lresize(exponent_width-1 downto 0)), 'X');
expr := to_01(UNSIGNED(rresize(exponent_width-1 downto 0)), 'X');
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
-- Synthisable
function gt ( -- greater than >
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := to_01(UNSIGNED(lresize(exponent_width-1 downto 0)), 'X');
expr := to_01(UNSIGNED(rresize(exponent_width-1 downto 0)), 'X');
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := class (l, check_error);
rfptype := class (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greather than or equal to >=
l, r : float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
--%%% Uncomment the following function
-- function "?=" (L, R: float) return std_ulogic is
function \?=\ (L, R : float) return STD_ULOGIC is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
return \?=\ (ufixed(lresize), ufixed(rresize));
--%%% return (to_slv(lresize) ?= to_slv(rresize));
end if;
end function \?=\;
--%%% end function "?=";
function \?/=\ (L, R : float) return STD_ULOGIC is
constant fraction_width : NATURAL := -minx(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
return \?/=\ (ufixed(lresize), ufixed(rresize));
--%%% return (to_slv(lresize) ?/= to_slv(rresize));
end if;
end function \?/=\;
--%%% end function "?/=";
-- %%% function "?>" (L, R : float) return std_ulogic is
function \?>\ (L, R : float) return std_ulogic is
constant fraction_width : NATURAL := -minx(l'low, r'low);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
elsif (find_msb (l, '-') /= l'low-1)
or (find_msb (r, '-') /= r'low-1) then
report "float_generic_pkg.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% end function "?>";
-- %%% function "?>=" (L, R : float) return std_ulogic is
function \?>=\ (L, R : float) return std_ulogic is
constant fraction_width : NATURAL := -minx(l'low, r'low);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
elsif (find_msb (l, '-') /= l'low-1)
or (find_msb (r, '-') /= r'low-1) then
report "float_generic_pkg.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% end function "?>=";
-- %%% function "?<" (L, R : float) return std_ulogic is
function \?<\ (L, R : float) return std_ulogic is
constant fraction_width : NATURAL := -minx(l'low, r'low);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
elsif (find_msb (l, '-') /= l'low-1)
or (find_msb (r, '-') /= r'low-1) then
report "float_generic_pkg.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% end function "?<";
-- %%% function "?<=" (L, R : float) return std_ulogic is
function \?<=\ (L, R : float) return std_ulogic is
constant fraction_width : NATURAL := -minx(l'low, r'low);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
elsif (find_msb (l, '-') /= l'low-1)
or (find_msb (r, '-') /= r'low-1) then
report "float_generic_pkg.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% end function "?<=";
function std_match (L, R : float) return BOOLEAN is
begin
return std_match(to_slv(L), to_slv(R));
end function std_match;
function find_lsb (arg : float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
-- These override the defaults for the compare operators.
function "=" (l, r : float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : float)
return float is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
L, R : float)
return float is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
-- Synthesizable
function resize (
arg : float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable round : BOOLEAN;
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
variable passguard : NATURAL;
begin
fptype := class(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := signed(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : float; -- Floating point input
size_res : float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- Not Synthisable (unless the input is a constant)
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
variable result : float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable exp_real : REAL; -- real version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := 0.0 - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
validfp := test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
-- exp_real := log (arg_real)/ log (2.0);
exp_real := log2 (arg_real);
exp := INTEGER (floor(exp_real)); -- positive fraction.
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when round_zero =>
null; -- don't round
end case;
if (round) then
if and_reducex(fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := float(expon);
result (-1 downto -fraction_width) := float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
-- Synthisable
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return float is
variable result : float (exponent_width downto -fraction_width);
variable arg_int : INTEGER; -- Real version of argument
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
constant frac_base : INTEGER := 30; -- Base to multiply fraction by
variable fract_shift : UNSIGNED (frac_base downto 0);
-- unshifted fract
variable validfp : boundary_type; -- used to check integer
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
validfp := fp_input_type (arg => arg_int,
exponent_width => exponent_width,
fraction_width => fraction_width);
if validfp = zero then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif validfp = infinity then
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
exp := to_signed (log2(arg_int), exp'length); -- positive fraction.
-- Compute Fraction
fract_shift := to_unsigned (arg_int, frac_base+1);
fract_shift := shift_left (fract_shift, (frac_base-to_integer(exp)));
-- pull out the fraction
fract := (others => '0'); -- zero out fraction first.
fract (fract'high downto maximum(0, fract'high-(frac_base-1))) :=
fract_shift (frac_base-1 downto maximum(0, frac_base-1-fract'high));
-- Round
if frac_base-1-fract'high > 0 then
round := check_round (
fract_in => fract (0),
sign => result (exponent_width),
remainder => fract_shift (frac_base-2-fract'high
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := fract;
end if;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := float(expon);
result (-1 downto -fraction_width) := float(rfract);
end if;
return result;
end function to_float;
-- to_float (unsigned)
-- Synthesizable
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return float is
variable result : float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable arg_int : UNSIGNED(xarg'range); -- Real version of argument
variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
begin
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (xarg)));
if (or_reducex (arg_int) = 'X') then
result := (others => 'X');
elsif (arg_int = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
result (exponent_width) := '0'; -- positive sign
-- Compute Exponent
argb2 := to_unsigned(find_msb(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => result (exponent_width),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := float(expon);
result (-1 downto -fraction_width) := float(rfract);
end if;
end if;
return result;
end function to_float;
-- to_float (signed)
-- Synthesizable
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return float is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : float (exponent_width downto -fraction_width);
variable argabs : SIGNED (xarg'range);
variable arg_int : UNSIGNED(xarg'range); -- unsigned version of argument
variable sign : STD_ULOGIC; -- sign of the signed number
begin
sign := to_x01 (xarg(xarg'high));
argabs := abs (xarg);
arg_int := UNSIGNED (argabs);
result := to_float (
arg => arg_int,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style);
if sign = '1' then
result (exponent_width) := '1';
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return float is
variable fpvar : float (exponent_width downto -fraction_width);
alias argslv : STD_LOGIC_VECTOR (fpvar'length-1 downto 0) is arg;
begin
fpvar := float(argslv);
-- floop : for i in fpvar'range loop
-- fpvar(i) := to_X01 (argslv(i-fpvar'low)); -- fpvar(8) := arg (8+23)
-- end loop floop;
return fpvar;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return float is
begin
return to_float (arg => to_stdlogicvector(arg),
exponent_width => exponent_width,
fraction_width => fraction_width);
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extentions
return float is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : ufixed (integer_width downto in_fraction_width);
variable result : float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- Real version of argument
variable exp, exptmp : SIGNED (exponent_width downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0); -- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin -- function to_float
xresult := to_01(arg, 'X');
arg_int := UNSIGNED(to_slv(xresult));
if (or_reducex (arg_int) = 'X') then
result := (others => 'X');
elsif (arg_int = 0) then
result := (others => '0'); -- return zero
else
result := (others => '0'); -- positive sign
-- Compute Exponent
exp := to_signed(find_msb(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
-- denormal number
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => '0',
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => '0',
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := float(expon);
result (-1 downto -fraction_width) := float(fract);
end if;
return result;
end function to_float;
function to_float (
arg : sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return float is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width - 1
downto 0); -- signed version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (or_reducex (UNSIGNED(argx)) = 'X') then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
argx := -argx; -- Make it positive.
else
result (exponent_width) := '0';
end if;
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx(arg_int'range))));
-- Compute Exponent
exp := to_signed(find_msb(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := float(expon);
result (-1 downto -fraction_width) := float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : float;
constant round_style : round_type := float_round_style) -- rounding option
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : float;
constant round_style : round_type := float_round_style) -- rounding option
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : float;
constant round_style : round_type := float_round_style) -- rounding
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : float)
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : float)
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => to_stdlogicvector(arg),
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : ufixed; -- unsigned fixed point input
size_res : float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extentions
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : sfixed;
size_res : float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return float is
variable result : float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- fp_to_integer - Floating point to integer
-- Note, to do an "int" function, call this routine with the
-- round_style set to "round_zero".
-- Synthesizable
function to_integer (
arg : float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return INTEGER is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (30 downto 0); -- Fraction
variable result : INTEGER;
variable sign : STD_ULOGIC; -- true if negative
begin
validfp := class (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
-- Add the sign bit back in.
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if and_reducex(frac) = '1' then -- return most negative number
result := INTEGER'low;
else
result := -to_integer(frac);
end if;
else
result := to_integer(frac);
end if;
end case classcase;
return result;
end function to_integer;
-- fp_to_unsigned - floating point to unsigned number
-- Synthesizable
function to_unsigned (
arg : float; -- floating point input
constant size : NATURAL; -- length of output
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return UNSIGNED is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := class (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- fp_to_signed - floating point to signed number
-- Synthesizable
function to_signed (
arg : float; -- floating point input
constant size : NATURAL; -- length of output
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return SIGNED is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable result : SIGNED (size-1 downto 0);
begin
validfp := class (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant round_style : BOOLEAN := fixed_round_style; -- rounding
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return ufixed is
constant fraction_width : INTEGER := -minx(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : ufixed (left_index downto right_index-3);
variable result : ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := class (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (arg => STD_LOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant round_style : BOOLEAN := fixed_round_style; -- rounding
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return sfixed is
constant fraction_width : INTEGER := -minx(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : sfixed (left_index downto right_index-3);
variable result : sfixed (left_index downto right_index) := (others => '0'); -- result
begin -- function to_ufixed
validfp := class (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : float; -- floating point input
size_res : UNSIGNED;
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return UNSIGNED is
variable result : UNSIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_unsigned (arg => arg,
size => size_res'length,
check_error => check_error,
round_style => round_style);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : float; -- floating point input
size_res : SIGNED;
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant round_style : round_type := float_round_style) -- rounding option
return SIGNED is
variable result : SIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_signed (arg => arg,
size => size_res'length,
check_error => check_error,
round_style => round_style);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : float; -- fp input
size_res : ufixed;
constant round_style : BOOLEAN := fixed_round_style; -- rounding
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : float; -- fp input
size_res : sfixed;
constant round_style : BOOLEAN := fixed_round_style; -- rounding
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- Floating point to Real number conversion
-- Not Synthesizable
function to_real (
arg : float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL is
constant fraction_width : INTEGER := -minx(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := class (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : float; -- floating point input
XMAP : STD_LOGIC := '0')
return float is
variable BAD_ELEMENT : BOOLEAN := false;
variable RESULT : float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert NO_WARNING
report "FLOAT_GENERIC_PKG.TO_01: null detected, returning NAFP"
severity warning;
return NAFP;
end if;
for I in RESULT'range loop
case arg(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
RESULT := (others => XMAP);
end if;
return RESULT;
end function to_01;
function Is_X
(arg : float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : float) return float is
begin
if (arg'length < 1) then
assert NO_WARNING
report "FLOAT_GENERIC_PKG.TO_X01: null detected, returning NAFP"
severity warning;
return NAFP;
else
return to_float (to_X01(to_slv(arg)), arg'high, -arg'low);
end if;
end function to_X01;
function to_X01Z (arg : float) return float is
begin
if (arg'length < 1) then
assert NO_WARNING
report "FLOAT_GENERIC_PKG.TO_X01Z: null detected, returning NAFP"
severity warning;
return NAFP;
else
return to_float (to_X01Z(to_slv(arg)), arg'high, -arg'low);
end if;
end function to_X01Z;
function to_UX01 (arg : float) return float is
begin
if (arg'length < 1) then
assert NO_WARNING
report "FLOAT_GENERIC_PKG.TO_UX01: null detected, returning NAFP"
severity warning;
return NAFP;
else
return to_float (to_UX01(to_slv(arg)), arg'high, -arg'low);
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : float) return float is
begin
return add (l, r);
end function "+";
function "-" (l, r : float) return float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : float) return float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : float) return float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : float) return float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : float) return float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : float; r : REAL) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return add (l_float, r);
end function "+";
function "+" (l : float; r : INTEGER) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return add (l_float, r);
end function "+";
function "-" (l : float; r : REAL) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return subtract (l_float, r);
end function "-";
function "-" (l : float; r : INTEGER) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return subtract (l_float, r);
end function "-";
function "*" (l : float; r : REAL) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return multiply (l_float, r);
end function "*";
function "*" (l : float; r : INTEGER) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return multiply (l_float, r);
end function "*";
function "/" (l : float; r : REAL) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return divide (l_float, r);
end function "/";
function "/" (l : float; r : INTEGER) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return divide (l_float, r);
end function "/";
function "rem" (l : float; r : REAL) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return remainder (l_float, r);
end function "rem";
function "rem" (l : float; r : INTEGER) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return remainder (l_float, r);
end function "rem";
function "mod" (l : float; r : REAL) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return modulo (l_float, r);
end function "mod";
function "mod" (l : float; r : INTEGER) return float is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : float) return float is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return modulo (l_float, r);
end function "mod";
function "=" (l : float; r : REAL) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return eq (l, r_float);
end function "=";
function "/=" (l : float; r : REAL) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return ne (l, r_float);
end function "/=";
function ">=" (l : float; r : REAL) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return ge (l, r_float);
end function ">=";
function "<=" (l : float; r : REAL) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return le (l, r_float);
end function "<=";
function ">" (l : float; r : REAL) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return gt (l, r_float);
end function ">";
function "<" (l : float; r : REAL) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return lt (l_float, r);
end function "<";
function "=" (l : float; r : INTEGER) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return eq (l, r_float);
end function "=";
function "/=" (l : float; r : INTEGER) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return ne (l, r_float);
end function "/=";
function ">=" (l : float; r : INTEGER) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return ge (l, r_float);
end function ">=";
function "<=" (l : float; r : INTEGER) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return le (l, r_float);
end function "<=";
function ">" (l : float; r : INTEGER) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return gt (l, r_float);
end function ">";
function "<" (l : float; r : INTEGER) return BOOLEAN is
variable r_float : float (l'range);
begin
r_float := to_float (r, l); -- use size_res function
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : float) return BOOLEAN is
variable l_float : float (r'range);
begin
l_float := to_float(l, r);
return lt (l_float, r);
end function "<";
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : float) return float is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
variable resfp : float (L'range); -- back to float
begin
RESULT := not to_slv(L);
resfp := float (RESULT);
return resfp;
end function "not";
function "and" (L, R : float) return float is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
variable resfp : float (L'range); -- back to float
begin
RESULT := to_slv(L) and to_slv(R);
resfp := float (RESULT);
return resfp;
end function "and";
function "or" (L, R : float) return float is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
variable resfp : float (L'range); -- back to float
begin
RESULT := to_slv(L) or to_slv(R);
resfp := float (RESULT);
return resfp;
end function "or";
function "nand" (L, R : float) return float is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
variable resfp : float (L'range); -- back to float
begin
RESULT := to_slv(L) nand to_slv(R);
resfp := float (RESULT);
return resfp;
end function "nand";
function "nor" (L, R : float) return float is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
variable resfp : float (L'range); -- back to float
begin
RESULT := to_slv(L) nor to_slv(R);
resfp := float (RESULT);
return resfp;
end function "nor";
function "xor" (L, R : float) return float is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
variable resfp : float (L'range); -- back to float
begin
RESULT := to_slv(L) xor to_slv(R);
resfp := float (RESULT);
return resfp;
end function "xor";
function "xnor" (L, R : float) return float is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
variable resfp : float (L'range); -- back to float
begin
RESULT := to_slv(L) xnor to_slv(R);
resfp := float (RESULT);
return resfp;
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : float) return float is
variable result : float (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : float; R : STD_ULOGIC) return float is
variable result : float (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : float) return float is
variable result : float (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : float; R : STD_ULOGIC) return float is
variable result : float (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : float) return float is
variable result : float (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : float; R : STD_ULOGIC) return float is
variable result : float (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : float) return float is
variable result : float (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : float; R : STD_ULOGIC) return float is
variable result : float (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : float) return float is
variable result : float (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : float; R : STD_ULOGIC) return float is
variable result : float (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : float) return float is
variable result : float (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : float; R : STD_ULOGIC) return float is
variable result : float (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
-- %%% remove 6 functions (old syntax)
function and_reduce(arg : float) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : float) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : float) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : float) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : float) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : float) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
-- %%% Uncomment the following 6 functions (new syntax)
-- function "and" ( arg : float ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";
-- function "nand" ( arg : float ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : float ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : float ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : float ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : float ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : float) -- floating point input
return float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
constant fraction_width : NATURAL := -minx(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
constant expon_base : SIGNED (exponent_width-1 downto 0)
:= gen_expon_base(exponent_width); -- exponent offset
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := class(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return float is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : float) -- floating point input
return INTEGER is
constant fraction_width : NATURAL := -minx (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := class(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_msb (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : float) -- floating point input
return SIGNED is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return float is
constant fraction_width : NATURAL := -minx(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := class (x, check_error);
validfpy := class (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and_reducex (fract) = '1' then -- fraction is all "1".
if and_reducex (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report "FLOAT_GENERIC_PKG.FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and_reducex (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or_reducex (fract) = '0' then -- fraction is all "0".
if or_reducex (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or_reducex (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or class (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and_reducex (fract) = '1' then -- fraction is all "1".
if and_reducex (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report "FLOAT_GENERIC_PKG.FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and_reducex (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or_reducex (fract) = '0' then -- fraction is all "0".
if or_reducex (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or_reducex (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := float(fract);
result (exponent_width -1 downto 0) := float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : float) -- floating point input
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := class (x);
rfptype := class (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Class (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Class (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float is
constant result : float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float is
variable result : float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float is
variable result : float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float is
variable result : float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float is
variable result : float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return float is
variable result : float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : float) -- variable is only use for sizing
return float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : float) -- variable is only use for sizing
return float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : float) -- variable is only use for sizing
return float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : float) -- variable is only use for sizing
return float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : float) -- variable is only use for sizing
return float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : float) -- variable is only use for sizing
return float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- rtl_synthesis off
-- synthesis translate_off
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
-- %%% Remove the following lines for inclution in VHDL-200x-ft
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_ostring;
-- %%% end remove lines
procedure write (
L : inout LINE; -- input line
VALUE : in float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
write(L, s, JUSTIFIED, FIELD);
end procedure write;
procedure READ(L : inout LINE; VALUE : out float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
loop -- skip white space
read(l, c, readOk);
exit when ((readOk = false) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
for i in value'high downto value'low loop
value(i) := 'X';
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FLOAT_GENERIC_PKG.READ(float): "
& "Error end of file encountered.";
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= value'low) then
report "FLOAT_GENERIC_PKG.READ(float): "
& "Warning: Value truncated.";
return;
end if;
elsif c = ':' or c = '.' then -- seperator, ignore
if not (i = -1 or i = value'high-1) then
report "FLOAT_GENERIC_PKG.READ(float): "
& "Warning: Seperator point does not match number format: '"
& c & "' ecountered at location " & INTEGER'image(i) & ".";
end if;
elsif (char_to_MVL9plus(c) = error) then
report "FLOAT_GENERIC_PKG.READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal.";
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE; VALUE : out float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
loop -- skip white space
read(l, c, readOk);
exit when ((readOk = false) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
for i in value'high downto value'low loop
value(i) := 'X';
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
good := false;
return;
elsif c = ':' or c = '.' then -- seperator, ignore
good := (i = -1 or i = value'high-1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure owrite (
L : inout LINE; -- access type (pointer)
VALUE : in float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
write (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure OREAD(L : inout LINE; VALUE : out float) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable dummy : CHARACTER; -- to read the "."
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
OREAD (L => L,
VALUE => nybble,
good => igood);
assert (igood)
report "FLOAT_GENERIC_PKG.OREAD: Failed to skip white space " & L.all
severity error;
i := ne-1 - 3; -- Top - 3
slv (ne-1 downto i+1) := nybble;
while (i /= -1) and igood and L.all'length /= 0 loop
if (L.all(1) = '.') or (L.all(1) = ':') then
read (L, dummy);
else
OREAD (L => L,
VALUE => nybble,
good => igood);
assert (igood)
report "FLOAT_GENERIC_PKG.OREAD: Failed to read the string " & L.all
severity error;
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
assert igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(ne-1 downto VALUE'high-VALUE'low+1)) = '0')
report "FLOAT_GENERIC_PKG.OREAD: Vector truncated."
severity error;
value := to_float (slv(VALUE'high-VALUE'low downto 0),
value'high, -value'low);
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable dummy : CHARACTER; -- to read the "."
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
OREAD (L => L,
VALUE => nybble,
good => igood);
i := ne-1 - 3; -- Top - 3
slv (ne-1 downto i+1) := nybble;
while (i /= -1) and igood and L.all'length /= 0 loop
if (L.all(1) = '.') or (L.all(1) = ':') then
read (L, dummy, igood);
else
OREAD (L => L,
VALUE => nybble,
good => igood);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(ne-1 downto VALUE'high-VALUE'low+1)) = '0');
value := to_float (slv(VALUE'high-VALUE'low downto 0),
value'high, -value'low);
end procedure OREAD;
procedure hwrite (
L : inout LINE; -- access type (pointer)
VALUE : in float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
write (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
procedure HREAD(L : inout LINE; VALUE : out float) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable dummy : CHARACTER; -- to read the "."
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
HREAD (L => L,
VALUE => nybble,
good => igood);
assert (igood)
report "FLOAT_GENERIC_PKG.HREAD: Failed to skip white space " & L.all
severity error;
i := ne - 1 - 4; -- Top - 4
slv (ne -1 downto i+1) := nybble;
while (i /= -1) and igood and L.all'length /= 0 loop
if (L.all(1) = '.') or (L.all(1) = ':') then
read (L, dummy);
else
HREAD (L => L,
VALUE => nybble,
good => igood);
assert (igood)
report "FLOAT_GENERIC_PKG.HREAD: Failed to read the string " & L.all
severity error;
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
assert igood and -- We did not get another error
(i = -1) and -- We read everything
(or_reducex(slv(ne-1 downto VALUE'high-VALUE'low+1)) = '0')
report "FLOAT_GENERIC_PKG.HREAD: Vector truncated."
severity error;
value := to_float (slv(VALUE'high-VALUE'low downto 0),
value'high, -value'low);
end procedure HREAD;
procedure HREAD(L : inout LINE; VALUE : out float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable dummy : CHARACTER; -- to read the "."
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
HREAD (L => L,
VALUE => nybble,
good => igood);
i := ne - 1 - 4; -- Top - 4
slv (ne-1 downto i+1) := nybble;
while (i /= -1) and igood and L.all'length /= 0 loop
if (L.all(1) = '.') or (L.all(1) = ':') then
read (L, dummy, igood);
else
HREAD (L => L,
VALUE => nybble,
good => igood);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(ne-1 downto VALUE'high-VALUE'low+1)) = '0');
value := to_float (slv(VALUE'high-VALUE'low downto 0),
value'high, -value'low);
end procedure HREAD;
function to_string (
value : float;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
return justify (s, JUSTIFIED, FIELD);
end function to_string;
function to_hstring (
value : float;
justified : SIDE := right;
field : width := 0
) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv, justified, field);
end function to_hstring;
function to_ostring (
value : float;
justified : SIDE := right;
field : width := 0
) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv, justified, field);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return float is
variable result : float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "FLOAT_GENERIC_PKG.from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return float is
variable result : float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "FLOAT_GENERIC_PKG.from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return float is
variable result : float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "FLOAT_GENERIC_PKG.from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : float) -- used for sizing only
return float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : float) -- used for sizing only
return float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : float) -- used for sizing only
return float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
-- synthesis translate_on
-- rtl_synthesis on
function to_StdLogicVector (arg : float) return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (arg : float) return std_logic_vector is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdULogicVector (arg : float) return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (arg : float) return std_ulogic_vector is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
end package body float_pkg;
| mit | e41533b318acf6a3c4fb79bf89d41dd6 | 0.54447 | 4.250759 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd | 1 | 11,859 | -- $Id: sys_tst_rlink_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n4d - syn
-- Description: rlink tester design for nexys4d
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_4line_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- bplib/bpgen/rgbdrv_master
-- bplib/bpgen/rgbdrv_analog_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_2
-- vlib/rbus/rb_sres_or_6
--
-- Test bench: tb/tb_tst_rlink_n4d
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2022.1; ghdl 0.29-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1 1181 1611 34 3.0 581
-- 2019-02-02 1108 2018.3 xc7a100t-1 1179 1721 36 3.0 597
-- 2019-02-02 1108 2017.2 xc7a100t-1 1179 1802 36 3.0 619
-- 2016-04-02 758 2015.4 xc7a100t-1 1113 1461 36 3.0 528 usracc
-- 2016-03-27 753 2015.4 xc7a100t-1 1124 1461 36 3.0 522 meminf
-- 2016-03-13 743 2015.4 xc7a100t-1 1124 1463 64 4.5 567 +XADC
-- 2016-02-20 734 2015.4 xc7a100t-1 1080 1424 64 4.5 502 +RGB
-- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 4.5 495
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-06-05 772 1.5.3 use CDUWIDTH=7, 120 MHz clock is natural choice
-- 2016-04-02 758 1.5.2 add rbd_usracc_e2 (bitfile+jtag timestamp access)
-- 2016-03-19 748 1.5.1 define rlink SYSID
-- 2016-03-12 741 1.5 add sysmon_rbus
-- 2016-02-20 734 1.4.2 add rgbdrv_analog_rbus for two rgb leds
-- 2015-04-11 666 1.4.1 rearrange XON handling
-- 2015-02-06 643 1.4 factor out memory
-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display
-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio
-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-09-28 535 1.0 Initial version (derived from sys_tst_rlink_n3)
------------------------------------------------------------------------------
-- Usage of Nexys 4DDR Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): -unused-
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(1): timer 1 busy
-- LED(0): timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n4d is -- top level
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_rlink_n4d;
architecture syn of sys_tst_rlink_n4d is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RGBCNTL : slv3 := (others=>'0');
signal DIMCNTL : slv12 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx
constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"08"; -- nexys4d
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good up to 127 MHz
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
HIO : sn_humanio_rbus
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RGBMSTR : rgbdrv_master
generic map (
DWIDTH => DIMCNTL'length)
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL
);
RGB0 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
RB_ADDR => rbaddr_rgb0)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB0,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED0
);
RGB1 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
RB_ADDR => rbaddr_rgb1)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB1,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED1
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_ORRGB : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_RGB0,
RB_SRES_2 => RB_SRES_RGB1,
RB_SRES_OR => RB_SRES_RGB
);
RB_SRES_OR1 : rb_sres_or_6
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_3 => RB_SRES_RGB,
RB_SRES_4 => RB_SRES_SYSMON,
RB_SRES_5 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
DSP_DAT(15 downto 0) <= (others=>'0');
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(15 downto 8) <= SWI(15 downto 8);
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
| gpl-3.0 | 88e296b374ba78848a1b286fbf095ef7 | 0.508643 | 3.116689 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01900_bad.vhd | 1 | 3,030 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01900_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of registered signals: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01900_bad is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Signal on which detect edges
o_D_re : out std_logic -- Rising edge of i_D
);
end CNE_01900_bad;
architecture Behavioral of CNE_01900_bad is
signal D_clocked : std_logic; -- i_D registered 1 time
signal D_clocked2 : std_logic; -- i_D registered 2 times
begin
-- Rising edge detection process
P_detection: process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D_clocked <= '0';
D_clocked2 <= '0';
elsif (rising_edge(i_Clock)) then
D_clocked <= i_D;
D_clocked2 <= D_clocked;
end if;
end process;
o_D_re <= D_clocked and not D_clocked2;
end Behavioral;
--CODE | gpl-3.0 | dd3f2715777e6312de03c8b1626c0fae | 0.493069 | 4.455882 | false | false | false | false |
wfjm/w11 | rtl/vlib/comlib/misc/gen_crc8_tbl_check.vhd | 1 | 3,057 | -- $Id: gen_crc8_tbl_check.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to test crc8 transition table
--
-- Dependencies: -
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 use now 'A6' polynomial of Koopman et al.
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity gen_crc8_tbl_check is
end gen_crc8_tbl_check;
architecture sim of gen_crc8_tbl_check is
begin
process
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174,
242, 191, 104, 37, 139, 198, 17, 92,
169, 228, 51, 126, 208, 157, 74, 7,
91, 22, 193, 140, 34, 111, 184, 245,
31, 82, 133, 200, 102, 43, 252, 177,
237, 160, 119, 58, 148, 217, 14, 67,
182, 251, 44, 97, 207, 130, 85, 24,
68, 9, 222, 147, 61, 112, 167, 234,
62, 115, 164, 233, 71, 10, 221, 144,
204, 129, 86, 27, 181, 248, 47, 98,
151, 218, 13, 64, 238, 163, 116, 57,
101, 40, 255, 178, 28, 81, 134, 203,
33, 108, 187, 246, 88, 21, 194, 143,
211, 158, 73, 4, 170, 231, 48, 125,
136, 197, 18, 95, 241, 188, 107, 38,
122, 55, 224, 173, 3, 78, 153, 212,
124, 49, 230, 171, 5, 72, 159, 210,
142, 195, 20, 89, 247, 186, 109, 32,
213, 152, 79, 2, 172, 225, 54, 123,
39, 106, 189, 240, 94, 19, 196, 137,
99, 46, 249, 180, 26, 87, 128, 205,
145, 220, 11, 70, 232, 165, 114, 63,
202, 135, 80, 29, 179, 254, 41, 100,
56, 117, 162, 239, 65, 12, 219, 150,
66, 15, 216, 149, 59, 118, 161, 236,
176, 253, 42, 103, 201, 132, 83, 30,
235, 166, 113, 60, 146, 223, 8, 69,
25, 84, 131, 206, 96, 45, 250, 183,
93, 16, 199, 138, 36, 105, 190, 243,
175, 226, 53, 120, 214, 155, 76, 1,
244, 185, 110, 35, 141, 192, 23, 90,
6, 75, 156, 209, 127, 50, 229, 168
);
variable crc : integer := 0;
variable oline : line;
begin
loop_i: for i in 0 to 255 loop
write(oline, i, right, 4);
write(oline, string'(": cycle length = "));
crc := i;
loop_n: for n in 1 to 256 loop
crc := crc8_tbl(crc);
if crc = i then
write(oline, n, right, 4);
writeline(output, oline);
exit loop_n;
end if;
end loop; -- n
end loop; -- i
wait;
end process;
end sim;
| gpl-3.0 | 8ceaa4daf3911d4a8237d7a84a5405e0 | 0.489696 | 2.820111 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/tb_serport_autobaud.vhd | 1 | 8,538 | -- $Id: tb_serport_autobaud.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_autobaud - sim
-- Description: Test bench for serport_autobaud
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_serport_autobaud [UUT]
--
-- To test: serport_autobaud
--
-- Target Devices: generic
--
-- Verified (with tb_serport_autobaud_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-21 91 - 0.26 - - c:ok
-- 2007-10-14 89 - 0.26 - - c:ok
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-12 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.2 use new simclk/simclkcnt
-- 2011-10-22 417 1.1.3 now numeric_std clean
-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
-- 2007-10-14 89 1.1 add extra stop bit for CLKDIV=0; drop c2out wait;
-- add moni for autobauder
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serportlib.all;
entity tb_serport_autobaud is
end tb_serport_autobaud;
architecture sim of tb_serport_autobaud is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal RXSD : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKDIV : slv13 := (others=>'0');
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXSD2 : slbit := '0';
signal RXDATA3 : slv8 := (others=>'0');
signal RXVAL3 : slbit := '0';
signal RXERR3 : slbit := '0';
signal RXACT3 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_serport_autobaud
port map (
CLK => CLK,
RESET => RESET,
RXSD => RXSD,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CLKDIV => CLKDIV,
ABACT => ABACT,
ABDONE => ABDONE,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD2 => TXSD2,
RXDATA3 => RXDATA3,
RXVAL3 => RXVAL3,
RXERR3 => RXERR3,
RXACT3 => RXACT3
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_autobaud_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable irate : integer := 16;
variable ival : slbit;
variable itxdata : slv8 := (others=>'0');
begin
RXSD <= '1';
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".break" => -- .break
read_ea(iline, idelta);
write(oline, string'(".break"));
writeline(output, oline);
RXSD <= '0';
wait for idelta*clock_period;
RXSD <= '1';
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
read_ea(iline, irate);
when "send " => -- send
read_ea(iline, ival);
read_ea(iline, itxdata);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
RXSD <= '0'; -- start bit
N_MON_VAL <= ival;
N_MON_DAT <= itxdata;
wait for clock_period;
N_MON_VAL <= '0';
wait for (irate-1)*clock_period;
RXSD <= '1';
for i in itxdata'reverse_range loop -- transmit lsb first
RXSD <= itxdata(i); -- data bit
wait for irate*clock_period;
end loop;
RXSD <= '1'; -- stop bit (plus extra cycle)
wait for (irate+1)*clock_period;
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 25*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable iabact : slbit := '0';
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_DAT_1 <= N_MON_DAT;
if (ABACT xor iabact)='1' then
writetimestamp(oline, CLK_CYCLE, ": auto ABACT =");
write(oline, ABACT, right, 2);
iabact := ABACT;
writeline(output, oline);
end if;
if ABDONE = '1' then
writetimestamp(oline, CLK_CYCLE, ": auto CLKDIV =");
write(oline, to_integer(unsigned(CLKDIV)), right, 3);
writeline(output, oline);
end if;
if RXVAL='1' or (ABACT='0' and RXERR='1' and unsigned(RXDATA)/=0) then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | 7a7e03641c457537762ff01020ed03dc | 0.507262 | 3.70091 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/pb.pkg.vhdl | 1 | 76,851 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and
-- functions associated to the L_PicoBlaze namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_TEXTIO.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
package pb is
constant PB_VERBOSE : BOOLEAN := FALSE; -- POC_VERBOSE;
constant PB_REPORT : BOOLEAN := FALSE;
subtype T_PB_ADDRESS is STD_LOGIC_VECTOR(11 downto 0);
subtype T_PB_INSTRUCTION is STD_LOGIC_VECTOR(17 downto 0);
-- PicoBlaze I/O bus
type T_PB_IOBUS_PB_DEV is record
PortID : T_SLV_8;
Data : T_SLV_8;
WriteStrobe : STD_LOGIC;
WriteStrobe_K : STD_LOGIC;
ReadStrobe : STD_LOGIC;
Interrupt_Ack : STD_LOGIC;
end record;
type T_PB_IOBUS_DEV_PB is record
Data : T_SLV_8;
Interrupt : STD_LOGIC;
Message : T_SLV_8;
end record;
type T_PB_IOBUS_PB_DEV_VECTOR is array(NATURAL range <>) of T_PB_IOBUS_PB_DEV;
type T_PB_IOBUS_DEV_PB_VECTOR is array(NATURAL range <>) of T_PB_IOBUS_DEV_PB;
constant T_PB_IOBUS_PB_DEV_Z : T_PB_IOBUS_PB_DEV := ((others => 'Z'), (others => 'Z'), others => 'Z');
constant T_PB_IOBUS_DEV_PB_Z : T_PB_IOBUS_DEV_PB := ((others => 'Z'), 'Z', (others => 'Z'));
-- private functions (must be declared public to be useable in public constants)
-- ===========================================================================
-- constant C_PB_MAX_LONGNAME_LENGTH : POSITIVE := 64;
constant C_PB_MAX_SHORTNAME_LENGTH : POSITIVE := 32;
-- subtype T_PB_LONGNAME is STRING(1 to C_PB_MAX_LONGNAME_LENGTH);
subtype T_PB_SHORTNAME is STRING(1 to C_PB_MAX_SHORTNAME_LENGTH);
type T_PB_SHORTNAME_VECTOR is array(NATURAL range <>) of T_PB_SHORTNAME;
-- constant C_PB_LONGNAME_EMPTY : T_PB_LONGNAME := (others => C_POC_NUL);
constant C_PB_SHORTNAME_EMPTY : T_PB_SHORTNAME := (others => C_POC_NUL);
-- function pb_LongName(name : string) return T_PB_LONGNAME ;
function pb_ShortName(name : string) return T_PB_SHORTNAME;
-- PicoBlaze device description
constant C_PB_MAX_REGISTER_FIELDS : POSITIVE := 32;
constant C_PB_MAX_REGISTERS : POSITIVE := 32;
constant C_PB_MAX_REGISTER_FIELD_MAPPINGS : POSITIVE := 32;
constant C_PB_MAX_MAPPINGS : POSITIVE := 32;
constant C_PB_MAX_DEVICES : POSITIVE := 32;
constant C_PB_MAX_BUSSES : POSITIVE := 12;
subtype T_PB_REGISTER_FIELD_INDEX is NATURAL range 0 to (C_PB_MAX_REGISTER_FIELDS - 1);
subtype T_PB_REGISTER_INDEX is NATURAL range 0 to (C_PB_MAX_REGISTERS - 1);
subtype T_PB_REGISTER_FIELD_MAPPING_INDEX is NATURAL range 0 to (C_PB_MAX_REGISTER_FIELD_MAPPINGS - 1);
subtype T_PB_PORTNUMBER_MAPPING_INDEX is NATURAL range 0 to (C_PB_MAX_MAPPINGS - 1);
subtype T_PB_DEVICE_INSTANCE_INDEX is NATURAL range 0 to (C_PB_MAX_DEVICES - 1);
subtype T_PB_BUS_INDEX is NATURAL range 0 to (C_PB_MAX_BUSSES - 1);
type T_PB_REGISTER_FIELD_KIND is (PB_REGISTER_FIELD_KIND_READ, PB_REGISTER_FIELD_KIND_WRITE, PB_REGISTER_FIELD_KIND_READWRITE);
type T_PB_REGISTER_FIELD is record
FieldID : T_UINT_8;
-- FieldName : T_PB_LONGNAME;
FieldShort : T_PB_SHORTNAME;
Length : T_UINT_8;
AutoClear : BOOLEAN;
FieldKind : T_PB_REGISTER_FIELD_KIND;
Encoding : STRING(1 to 256);
end record;
constant C_PB_REGISTER_FIELD_EMPTY : T_PB_REGISTER_FIELD := (
FieldID => 0,
-- FieldName => C_PB_LONGNAME_EMPTY,
FieldShort => C_PB_SHORTNAME_EMPTY,
Length => 0,
AutoClear => FALSE,
FieldKind => PB_REGISTER_FIELD_KIND_READ,
Encoding => (others => C_POC_NUL)
);
type T_PB_REGISTER_FIELD_VECTOR is array(NATURAL range <>) of T_PB_REGISTER_FIELD;
type T_PB_REGISTER_FIELD_MAPPING_KIND is (PB_REGISTER_FIELD_MAPPING_KIND_READ, PB_REGISTER_FIELD_MAPPING_KIND_WRITE, PB_REGISTER_FIELD_MAPPING_KIND_WRITEK);
type T_PB_REGISTER_FIELD_GROUP is record
FieldShort : T_PB_SHORTNAME;
Offset : T_UINT_8;
MappingKind : T_PB_REGISTER_FIELD_MAPPING_KIND;
end record;
type T_PB_REGISTER_FIELD_GROUP_VECTOR is array(NATURAL range <>) of T_PB_REGISTER_FIELD_GROUP;
type T_PB_REGISTER_FIELD_MAPPING is record
FieldID : T_UINT_8;
Start : T_UINT_8;
Length : T_UINT_8;
MappingKind : T_PB_REGISTER_FIELD_MAPPING_KIND;
end record;
type T_PB_REGISTER_FIELD_MAPPING_VECTOR is array(NATURAL range <>) of T_PB_REGISTER_FIELD_MAPPING;
constant C_PB_REGISTER_FIELD_MAPPING_EMPTY : T_PB_REGISTER_FIELD_MAPPING := (
FieldID => 255,
Start => 0,
Length => 0,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ
);
type T_PB_REGISTER_KIND is (PB_REGISTER_KIND_READ, PB_REGISTER_KIND_WRITE, PB_REGISTER_KIND_READWRITE, PB_REGISTER_KIND_WRITEK);
type T_PB_REGISTER is record
-- RegisterName : T_PB_LONGNAME;
RegisterShort : T_PB_SHORTNAME;
RegisterNumber : T_UINT_8;
RegisterKind : T_PB_REGISTER_KIND;
FieldMappings : T_PB_REGISTER_FIELD_MAPPING_VECTOR(T_PB_REGISTER_FIELD_MAPPING_INDEX);
FieldMappingCount : T_UINT_8;
end record;
constant C_PB_REGISTER_EMPTY : T_PB_REGISTER := (
-- RegisterName => C_PB_LONGNAME_EMPTY,
RegisterShort => C_PB_SHORTNAME_EMPTY,
RegisterNumber => 255,
RegisterKind => PB_REGISTER_KIND_READ,
FieldMappings => (others => C_PB_REGISTER_FIELD_MAPPING_EMPTY),
FieldMappingCount => 0
);
type T_PB_REGISTER_VECTOR is array(NATURAL range <>) of T_PB_REGISTER;
type T_PB_DEVICE is record
-- DeviceName : T_PB_LONGNAME;
DeviceShort : T_PB_SHORTNAME;
Registers : T_PB_REGISTER_VECTOR(T_PB_REGISTER_INDEX);
RegisterCount : T_UINT_8;
RegisterFields : T_PB_REGISTER_FIELD_VECTOR(T_PB_REGISTER_FIELD_INDEX);
RegisterFieldCount : T_UINT_8;
CreatesInterrupt : BOOLEAN;
end record;
type T_PB_DEVICE_VECTOR is array (NATURAL range <>) of T_PB_DEVICE;
constant C_PB_DEVICE_EMPTY : T_PB_DEVICE := (
-- DeviceName => C_PB_LONGNAME_EMPTY,
DeviceShort => C_PB_SHORTNAME_EMPTY,
Registers => (others => C_PB_REGISTER_EMPTY),
RegisterCount => 0,
RegisterFields => (others => C_PB_REGISTER_FIELD_EMPTY),
RegisterFieldCount => 0,
CreatesInterrupt => FALSE
);
type T_PB_MAPPING_KIND is (PB_MAPPING_KIND_EMPTY, PB_MAPPING_KIND_WRITE, PB_MAPPING_KIND_WRITEK, PB_MAPPING_KIND_READ);
type T_PB_PORTNUMBER_MAPPING is record
PortNumber : T_UINT_8;
RegID : T_PB_REGISTER_INDEX;
RegNumber : T_UINT_8;
MappingKind : T_PB_MAPPING_KIND;
end record;
type T_PB_PORTNUMBER_MAPPING_VECTOR is array(NATURAL range <>) of T_PB_PORTNUMBER_MAPPING;
constant C_PB_PORTNUMBER_MAPPING_EMPTY : T_PB_PORTNUMBER_MAPPING := (
PortNumber => 0,
RegID => 0,
RegNumber => 0,
MappingKind => PB_MAPPING_KIND_EMPTY
);
type T_PB_DEVICE_INSTANCE is record
-- DeviceName : T_PB_LONGNAME;
DeviceShort : T_PB_SHORTNAME;
Device : T_PB_DEVICE;
BusShort : T_PB_SHORTNAME;
MappingCount : T_PB_PORTNUMBER_MAPPING_INDEX;
Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
end record;
type T_PB_DEVICE_DESCRIPTION is record
DeviceShort : T_PB_SHORTNAME;
BusShort : T_PB_SHORTNAME;
ReadMappings : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
ReadMappingCount : T_PB_PORTNUMBER_MAPPING_INDEX;
WriteMappings : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
WriteMappingCount : T_PB_PORTNUMBER_MAPPING_INDEX;
WriteKMappings : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
WriteKMappingCount : T_PB_PORTNUMBER_MAPPING_INDEX;
end record;
type T_PB_DEVICE_INSTANCE_VECTOR is array (NATURAL range <>) of T_PB_DEVICE_INSTANCE;
constant C_PB_DEVICE_INSTANCE_EMPTY : T_PB_DEVICE_INSTANCE := (
-- DeviceName => C_PB_LONGNAME_EMPTY,
DeviceShort => C_PB_SHORTNAME_EMPTY,
Device => C_PB_DEVICE_EMPTY,
BusShort => C_PB_SHORTNAME_EMPTY,
MappingCount => 0,
Mappings => (others => C_PB_PORTNUMBER_MAPPING_EMPTY)
);
function pb_CreateReadonlyField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD;
function pb_CreateWriteonlyField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD;
function pb_CreateRegisterField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD;
function pb_EnumerateRegisterFields(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR) return T_PB_REGISTER_FIELD_VECTOR;
function pb_GetRegisterFieldID(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; NameShort : STRING) return T_UINT_8;
function pb_GetRegisterField(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; NameShort : STRING) return T_PB_REGISTER_FIELD;
function pb_CreateRegisterRO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER;
function pb_CreateRegisterRW(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR;
function pb_CreateRegisterWO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER;
function pb_CreateRegisterKO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER;
function pb_CreateRegisterWK(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR;
function pb_CreateRegisterRWK(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR;
function pb_CreateCombinedRegister(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterFields : T_PB_REGISTER_FIELD_GROUP_VECTOR) return T_PB_REGISTER;
function pb_CreateDevice(DeviceName : STRING; DeviceShort : STRING; Registers : T_PB_REGISTER_VECTOR; RegisterFields : T_PB_REGISTER_FIELD_VECTOR; CreatesInterrupt : BOOLEAN := FALSE) return T_PB_DEVICE;
function pb_CreateDeviceAlias(Device : T_PB_DEVICE; AliasName : STRING) return T_PB_DEVICE;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; InstanceNumber : T_UINT_8; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; NameLong : STRING; NameShort : STRING; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE;
function pb_GetDeviceInstance(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; NameShort : STRING) return T_PB_DEVICE_INSTANCE;
subtype T_PB_BUSID is NATURAL range 0 to 31;
subtype T_PB_DEVICEID is NATURAL range 0 to 127;
type T_PB_BUSID_VECTOR is array (NATURAL range <>) of T_PB_BUSID;
type T_PB_DEVICEID_VECTOR is array (NATURAL range <>) of T_PB_DEVICEID;
type T_PB_BUS is record
-- BusName : T_PB_LONGNAME;
BusShort : T_PB_SHORTNAME;
SuperBusShort : T_PB_SHORTNAME;
SuperBusID : T_PB_BUSID;
SubBusses : T_PB_BUSID_VECTOR(0 to 7);
SubBusCount : NATURAL range 0 to 8;
Devices : T_PB_DEVICEID_VECTOR(0 to 31);
DeviceCount : NATURAL range 0 to 32;
TotalDeviceCount : T_UINT_8;
end record;
type T_PB_BUS_VECTOR is array (NATURAL range <>) of T_PB_BUS;
constant C_PB_BUS_EMPTY : T_PB_BUS := (
-- BusName => C_PB_LONGNAME_EMPTY,
BusShort => C_PB_SHORTNAME_EMPTY,
SuperBusShort => C_PB_SHORTNAME_EMPTY,
SuperBusID => 0,
SubBusses => (others => 0),
SubBusCount => 0,
Devices => (others => 0),
DeviceCount => 0,
TotalDeviceCount => 0
);
function pb_CreateBus(BusName : STRING; BusShort : STRING; SuperBusShort : STRING) return T_PB_BUS;
function pb_ConnectBusses(Busses : T_PB_BUS_VECTOR) return T_PB_BUS_VECTOR;
type T_PB_SYSTEM is record
-- SystemName : T_PB_LONGNAME;
SystemShort : T_PB_SHORTNAME;
DeviceInstanceCount : T_PB_DEVICE_INSTANCE_INDEX;
DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR(T_PB_DEVICE_INSTANCE_INDEX);
BusCount : T_PB_BUS_INDEX;
Busses : T_PB_BUS_VECTOR(T_PB_BUS_INDEX);
end record;
function pb_CreateSystem(SystemName : STRING; SystemShort : STRING; Busses : T_PB_BUS_VECTOR; DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR) return T_PB_SYSTEM;
function pb_GetDeviceInstance(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_INSTANCE;
function pb_GetDeviceDescription(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_DESCRIPTION;
function pb_Resize(RegisterMapping : T_PB_REGISTER_FIELD_MAPPING; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_MAPPING_VECTOR;
function pb_Resize(RegisterField : T_PB_REGISTER_FIELD; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_VECTOR;
function pb_Resize(Reg : T_PB_REGISTER; Size : NATURAL := 0) return T_PB_REGISTER_VECTOR;
function pb_ResizeVec(RegisterMappings : T_PB_REGISTER_FIELD_MAPPING_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_MAPPING_VECTOR;
function pb_ResizeVec(RegisterFields : T_PB_REGISTER_FIELD_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_VECTOR;
function pb_ResizeVec(Registers : T_PB_REGISTER_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_VECTOR;
function pb_ResizeVec(Busses : T_PB_BUS_VECTOR; Size : NATURAL := 0) return T_PB_BUS_VECTOR;
function pb_ResizeVec(Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR; Size : NATURAL := 0) return T_PB_PORTNUMBER_MAPPING_VECTOR;
function pb_ResizeVec(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; Size : NATURAL := 0) return T_PB_DEVICE_INSTANCE_VECTOR;
-- PicoBlaze interrupt functions
function pb_GetInterruptCount(System : T_PB_SYSTEM) return NATURAL;
function pb_GetInterruptPortIndex(System : T_PB_SYSTEM; DeviceShort : STRING) return NATURAL;
function pb_GetInterruptVector(PicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return STD_LOGIC_VECTOR;
function pb_GetInterruptMessages(PicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return T_SLVV_8;
procedure pb_AssignInterruptAck(signal Output : inout T_PB_IOBUS_PB_DEV_VECTOR; Input : STD_LOGIC_VECTOR; System : T_PB_SYSTEM);
-- PicoBlaze AddressDecoder functions
function pb_FilterMappings(DeviceInstance : T_PB_DEVICE_INSTANCE; MappingKind : T_PB_MAPPING_KIND) return T_PB_PORTNUMBER_MAPPING_VECTOR;
-- PicoBlaze bus functions
function pb_GetBusIndex(System : T_PB_SYSTEM; DeviceShort : STRING) return NATURAL;
function pb_GetBusWidth(System : T_PB_SYSTEM; BusShort : STRING) return NATURAL;
function pb_GetSubOrdinateBus(Input : T_PB_IOBUS_PB_DEV_VECTOR; System : T_PB_SYSTEM; BusShort : STRING) return T_PB_IOBUS_PB_DEV_VECTOR;
procedure pb_AssignSubOrdinateBus(signal Output : inout T_PB_IOBUS_DEV_PB_VECTOR; Input : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM; BusShort : STRING);
impure function pb_PrintAddressMapping(System : T_PB_SYSTEM) return BOOLEAN;
impure function pb_PrintBusses(System : T_PB_SYSTEM) return BOOLEAN;
impure function pb_ExportAddressMappingAsAssemblerConstants(System : T_PB_SYSTEM; psmFileName : STRING) return BOOLEAN;
impure function pb_ExportAddressMappingAsAssemblerInterruptVector(System : T_PB_SYSTEM; psmFileName : STRING; TableRows : POSITIVE) return BOOLEAN;
impure function pb_ExportAddressMappingAsChipScopeTokens(System : T_PB_SYSTEM; tokenFileName : STRING) return BOOLEAN;
end package;
package body pb is
-- private functions (must be declared before public functions)
-- ===========================================================================
-- function pb_LongName(name : STRING) return T_PB_LONGNAME is
-- begin
-- return resize(name, C_PB_MAX_LONGNAME_LENGTH);
-- end function;
function pb_ShortName(name : STRING) return T_PB_SHORTNAME is
begin
return resize(name, C_PB_MAX_SHORTNAME_LENGTH);
end function;
-- public functions
-- ===========================================================================
function pb_CreateReadonlyField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD is
variable Result : T_PB_REGISTER_FIELD;
begin
-- Result.FieldName := pb_LongName(NameLong);
Result.FieldShort := pb_ShortName(NameShort);
Result.Length := Length;
Result.FieldKind := PB_REGISTER_FIELD_KIND_READ;
Result.AutoClear := AutoClear;
Result.Encoding := resize(Encoding, Result.Encoding'length);
return Result;
end function;
function pb_CreateWriteonlyField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD is
variable Result : T_PB_REGISTER_FIELD;
begin
-- Result.FieldName := pb_LongName(NameLong);
Result.FieldShort := pb_ShortName(NameShort);
Result.Length := Length;
Result.FieldKind := PB_REGISTER_FIELD_KIND_WRITE;
Result.AutoClear := AutoClear;
Result.Encoding := resize(Encoding, Result.Encoding'length);
return Result;
end function;
function pb_CreateRegisterField(NameLong : STRING; NameShort : STRING; Length : T_UINT_8; Encoding : STRING := ""; AutoClear : BOOLEAN := FALSE) return T_PB_REGISTER_FIELD is
variable Result : T_PB_REGISTER_FIELD;
begin
-- Result.FieldName := pb_LongName(NameLong);
Result.FieldShort := pb_ShortName(NameShort);
Result.Length := Length;
Result.FieldKind := PB_REGISTER_FIELD_KIND_READWRITE;
Result.AutoClear := AutoClear;
Result.Encoding := resize(Encoding, Result.Encoding'length);
return Result;
end function;
function pb_EnumerateRegisterFields(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR) return T_PB_REGISTER_FIELD_VECTOR is
variable Result : T_PB_REGISTER_FIELD_VECTOR(RegisterFieldList'range);
begin
for i in RegisterFieldList'range loop
Result(i) := RegisterFieldList(i);
Result(i).FieldID := i;
end loop;
return Result;
end function;
function pb_GetRegisterFieldID(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; NameShort : STRING) return T_UINT_8 is
begin
for i in RegisterFieldList'range loop
next when (not str_match(RegisterFieldList(i).FieldShort, NameShort));
return i;
end loop;
report "RegisterField '" & str_trim(NameShort) & "' does not exist!" severity FAILURE;
end function;
function pb_GetRegisterField(RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; NameShort : STRING) return T_PB_REGISTER_FIELD is
begin
return RegisterFieldList(pb_GetRegisterFieldID(RegisterFieldList, NameShort));
end function;
function pb_CreateRegisterRO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER;
constant REPORT_PREFIX : STRING := ite((PB_REPORT and not PB_VERBOSE), "pb_CreateRegisterRO: ", " ");
begin
if (RegisterField.FieldKind /= PB_REGISTER_FIELD_KIND_READ) then
report "pb_CreateRegisterRO: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not RO, but should be translated into a READ register." severity FAILURE;
end if;
if (PB_VERBOSE = TRUE) then
report "pb_CreateRegisterRO:" severity NOTE;
report " RegisterFieldList: Count=" & INTEGER'image(RegisterFieldList'length) severity NOTE;
for i in RegisterFields'range loop
report " " & INTEGER'image(i) & ": " & str_trim(RegisterFields(i).FieldShort) severity NOTE;
end loop;
end if;
if (PB_REPORT = TRUE) then
report REPORT_PREFIX & "Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result.RegisterName := pb_LongName(NameShort);
Result.RegisterShort := pb_ShortName(NameShort);
Result.RegisterNumber := RegisterNumber;
Result.RegisterKind := PB_REGISTER_KIND_READ;
Result.FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ));
return Result;
end function;
function pb_CreateRegisterRW(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER_VECTOR(0 to 1);
begin
if (RegisterField.FieldKind /= PB_REGISTER_FIELD_KIND_READWRITE) then
report "pb_CreateRegisterRW: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not RW, but should be translated into a READ and a WRITE register." severity FAILURE;
end if;
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterRW: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result(0).RegisterName := pb_LongName(NameShort);
Result(0).RegisterShort := pb_ShortName(NameShort);
Result(0).RegisterNumber := RegisterNumber;
Result(0).RegisterKind := PB_REGISTER_KIND_READ;
Result(0).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ));
-- Result(1).RegisterName := pb_LongName(NameShort);
Result(1).RegisterShort := pb_ShortName(NameShort);
Result(1).RegisterNumber := RegisterNumber;
Result(1).RegisterKind := PB_REGISTER_KIND_WRITE;
Result(1).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITE));
return Result;
end function;
function pb_CreateRegisterWO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER;
begin
if (RegisterField.FieldKind /= PB_REGISTER_FIELD_KIND_WRITE) then
report "pb_CreateRegisterRO: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not WO, but shall be translated into a WRITE register." severity FAILURE;
end if;
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterWO: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result.RegisterName := pb_LongName(NameShort);
Result.RegisterShort := pb_ShortName(NameShort);
Result.RegisterNumber := RegisterNumber;
Result.RegisterKind := PB_REGISTER_KIND_WRITE;
Result.FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ));
return Result;
end function;
function pb_CreateRegisterKO(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER;
begin
if (RegisterField.FieldKind = PB_REGISTER_FIELD_KIND_READ) then
report "pb_CreateRegisterK: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not WO or RW, but should be translated into a WRITE register." severity FAILURE;
end if;
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterKO: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result.RegisterName := pb_LongName(NameShort);
Result.RegisterShort := pb_ShortName(NameShort);
Result.RegisterNumber := RegisterNumber;
Result.RegisterKind := PB_REGISTER_KIND_WRITEK;
Result.FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITEK));
return Result;
end function;
function pb_CreateRegisterWK(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER_VECTOR(0 to 1);
begin
if (RegisterField.FieldKind = PB_REGISTER_FIELD_KIND_READ) then
report "pb_CreateRegisterRW: Given RegisterField '" & str_trim(RegisterNameShort) & "' is not WO, but should be translated into a WRITE register." severity FAILURE;
end if;
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterWK: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result(0).RegisterName := pb_LongName(NameShort);
Result(0).RegisterShort := pb_ShortName(NameShort);
Result(0).RegisterNumber := RegisterNumber;
Result(0).RegisterKind := PB_REGISTER_KIND_WRITE;
Result(0).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITE));
-- Result(1).RegisterName := pb_LongName(NameShort);
Result(1).RegisterShort := pb_ShortName(NameShort);
Result(1).RegisterNumber := RegisterNumber;
Result(1).RegisterKind := PB_REGISTER_KIND_WRITEK;
Result(1).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITEK));
return Result;
end function;
function pb_CreateRegisterRWK(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterNameShort : STRING; Offset : T_UINT_8 := 0) return T_PB_REGISTER_VECTOR is
constant RegisterFields : T_PB_REGISTER_FIELD_VECTOR := pb_EnumerateRegisterFields(RegisterFieldList);
constant RegisterField : T_PB_REGISTER_FIELD := pb_GetRegisterField(RegisterFields, RegisterNameShort);
variable Result : T_PB_REGISTER_VECTOR(0 to 2);
begin
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "pb_CreateRegisterRWK: Creating register '" & str_trim(NameShort) & "' @RegNum " & INTEGER'image(RegisterNumber) & " from field: '" & str_trim(RegisterField.FieldShort) & "'" severity NOTE;
end if;
-- Result(0).RegisterName := pb_LongName(NameShort);
Result(0).RegisterShort := pb_ShortName(NameShort);
Result(0).RegisterNumber := RegisterNumber;
Result(0).RegisterKind := PB_REGISTER_KIND_READ;
Result(0).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_READ));
-- Result(1).RegisterName := pb_LongName(NameShort);
Result(1).RegisterShort := pb_ShortName(NameShort);
Result(1).RegisterNumber := RegisterNumber;
Result(1).RegisterKind := PB_REGISTER_KIND_WRITE;
Result(1).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITE));
-- Result(2).RegisterName := pb_LongName(NameShort);
Result(2).RegisterShort := pb_ShortName(NameShort);
Result(2).RegisterNumber := RegisterNumber;
Result(2).RegisterKind := PB_REGISTER_KIND_WRITEK;
Result(2).FieldMappings := pb_Resize((
FieldID => RegisterField.FieldID,
Start => Offset,
Length => RegisterField.Length,
MappingKind => PB_REGISTER_FIELD_MAPPING_KIND_WRITEK));
return Result;
end function;
function pb_CreateCombinedRegister(NameShort : STRING; RegisterNumber : T_UINT_8; RegisterFieldList : T_PB_REGISTER_FIELD_VECTOR; RegisterFields : T_PB_REGISTER_FIELD_GROUP_VECTOR) return T_PB_REGISTER is
variable Result : T_PB_REGISTER;
variable RegisterField : T_PB_REGISTER_FIELD;
begin
-- Result.RegisterName := pb_LongName(NameShort);
Result.RegisterShort := pb_ShortName(NameShort);
Result.RegisterNumber := RegisterNumber;
for i in RegisterFields'range loop
RegisterField := pb_GetRegisterField(RegisterFieldList, RegisterFields(i).FieldShort);
Result.FieldMappings(i) := (
FieldID => pb_GetRegisterFieldID(RegisterFieldList, RegisterField.FieldShort),
Start => RegisterFields(i).Offset,
Length => RegisterField.Length,
MappingKind => RegisterFields(i).MappingKind);
Result.FieldMappingCount := RegisterFields'length;
if (Result.RegisterKind = PB_REGISTER_KIND_READ) then
if (RegisterFields(i).MappingKind = PB_REGISTER_FIELD_MAPPING_KIND_WRITE) then
Result.RegisterKind := PB_REGISTER_KIND_READWRITE;
elsif (RegisterFields(i).MappingKind = PB_REGISTER_FIELD_MAPPING_KIND_WRITEK) then
Result.RegisterKind := PB_REGISTER_KIND_READWRITE;
end if;
elsif (Result.RegisterKind = PB_REGISTER_KIND_WRITE) then
if (RegisterFields(i).MappingKind = PB_REGISTER_FIELD_MAPPING_KIND_READ) then
Result.RegisterKind := PB_REGISTER_KIND_READWRITE;
end if;
elsif (Result.RegisterKind = PB_REGISTER_KIND_WRITEK) then
if (RegisterFields(i).MappingKind = PB_REGISTER_FIELD_MAPPING_KIND_READ) then
Result.RegisterKind := PB_REGISTER_KIND_READWRITE;
end if;
end if;
end loop;
return Result;
end function;
-- private function
function pb_CreateMapping(Device : T_PB_DEVICE; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_PORTNUMBER_MAPPING_VECTOR is
variable Result : T_PB_PORTNUMBER_MAPPING_VECTOR(T_PB_PORTNUMBER_MAPPING_INDEX);
variable Reg : T_PB_REGISTER;
variable j : T_UINT_8;
begin
Result := (others => C_PB_PORTNUMBER_MAPPING_EMPTY);
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report "Creating PortNumber mapping for device " & str_trim(Device.DeviceShort) & " with " & INTEGER'image(Device.RegisterCount) & " registers:" severity NOTE;
end if;
j := 0;
for i in 0 to Device.RegisterCount - 1 loop
Reg := Device.Registers(i);
case Reg.RegisterKind is
when PB_REGISTER_KIND_READ =>
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report " Mapping PortNumber " & INTEGER'image(MappingStart + Reg.RegisterNumber) & " to register " & INTEGER'image(Reg.RegisterNumber) & " (" & str_trim(Reg.RegisterShort) & ") as readable" severity NOTE;
end if;
Result(j) := (
PortNumber => MappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_READ
);
j := j + 1;
when PB_REGISTER_KIND_READWRITE =>
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report " Mapping PortNumber " & INTEGER'image(MappingStart + Reg.RegisterNumber) & " to register " & INTEGER'image(Reg.RegisterNumber) & " (" & str_trim(Reg.RegisterShort) & ") as read/writeable" severity NOTE;
end if;
Result(j) := (
PortNumber => MappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_READ
);
Result(j + 1) := (
PortNumber => MappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_WRITE
);
j := j + 2;
when PB_REGISTER_KIND_WRITE =>
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report " Mapping PortNumber " & INTEGER'image(MappingStart + Reg.RegisterNumber) & " to register " & INTEGER'image(Reg.RegisterNumber) & " (" & str_trim(Reg.RegisterShort) & ") as writeable" severity NOTE;
end if;
Result(j) := (
PortNumber => MappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_WRITE
);
j := j + 1;
when PB_REGISTER_KIND_WRITEK =>
if ((PB_VERBOSE or PB_REPORT) = TRUE) then
report " Mapping PortNumber " & INTEGER'image(KMappingStart + Reg.RegisterNumber) & " to register " & INTEGER'image(Reg.RegisterNumber) & " (" & str_trim(Reg.RegisterShort) & ") as K-writeable" severity NOTE;
end if;
Result(j) := (
PortNumber => KMappingStart + Reg.RegisterNumber,
RegID => i,
RegNumber => Reg.RegisterNumber,
MappingKind => PB_MAPPING_KIND_WRITEK
);
j := j + 1;
if (j > C_PB_MAX_MAPPINGS) then
report "pb_CreateMapping: Too many mappings created." severity FAILURE;
end if;
end case;
end loop;
return Result(0 to j - 1);
end function;
function pb_CreateDevice(DeviceName : STRING; DeviceShort : STRING; Registers : T_PB_REGISTER_VECTOR; RegisterFields : T_PB_REGISTER_FIELD_VECTOR; CreatesInterrupt : BOOLEAN := FALSE) return T_PB_DEVICE is
variable Result : T_PB_DEVICE;
begin
-- Result.DeviceName := pb_LongName(DeviceName);
Result.DeviceShort := pb_ShortName(DeviceShort);
Result.Registers := pb_ResizeVec(Registers);
Result.RegisterCount := Registers'length;
Result.RegisterFields := pb_ResizeVec(RegisterFields);
Result.RegisterFieldCount := RegisterFields'length;
Result.CreatesInterrupt := CreatesInterrupt;
return Result;
end function;
function pb_CreateDeviceAlias(Device : T_PB_DEVICE; AliasName : STRING) return T_PB_DEVICE is
variable Result : T_PB_DEVICE;
begin
Result := Device;
Result.DeviceShort := pb_ShortName(AliasName);
return Result;
end function;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE is
constant Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_CreateMapping(Device, MappingStart, KMappingStart);
variable Result : T_PB_DEVICE_INSTANCE;
begin
-- Result.DeviceName := Device.DeviceName;
Result.DeviceShort := Device.DeviceShort;
Result.Device := Device;
Result.BusShort := pb_ShortName(BusShort);
Result.MappingCount := Mappings'length;
Result.Mappings := pb_ResizeVec(Mappings);
return Result;
end function;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; InstanceNumber : T_UINT_8; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE is
constant Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_CreateMapping(Device, MappingStart, KMappingStart);
variable Result : T_PB_DEVICE_INSTANCE;
begin
-- Result.DeviceName := pb_LongName(str_trim(Device.DeviceName) & INTEGER'image(InstanceNumber));
Result.DeviceShort := pb_ShortName(str_trim(Device.DeviceShort) & INTEGER'image(InstanceNumber));
Result.Device := Device;
Result.BusShort := pb_ShortName(BusShort);
Result.MappingCount := Mappings'length;
Result.Mappings := pb_ResizeVec(Mappings);
return Result;
end function;
function pb_CreateDeviceInstance(Device : T_PB_DEVICE; NameLong : STRING; NameShort : STRING; BusShort : STRING; MappingStart : T_UINT_8; KMappingStart : T_UINT_8 := T_UINT_8'high) return T_PB_DEVICE_INSTANCE is
constant Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_CreateMapping(Device, MappingStart, KMappingStart);
variable Result : T_PB_DEVICE_INSTANCE;
begin
-- Result.DeviceName := pb_LongName(NameLong);
Result.DeviceShort := pb_ShortName(NameShort);
Result.Device := Device;
Result.BusShort := pb_ShortName(BusShort);
Result.MappingCount := Mappings'length;
Result.Mappings := pb_ResizeVec(Mappings);
return Result;
end function;
function pb_GetDeviceInstanceID(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; NameShort : STRING) return T_PB_DEVICE_INSTANCE_INDEX is
begin
for i in DeviceInstances'range loop
next when (not str_match(DeviceInstances(i).DeviceShort, NameShort));
return i;
end loop;
report "Device '" & str_trim(NameShort) & "' does not exist!" severity FAILURE;
end function;
function pb_GetDeviceInstanceID(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_INSTANCE_INDEX is
begin
for i in 0 to System.DeviceInstanceCount - 1 loop
next when (not str_match(System.DeviceInstances(i).DeviceShort, NameShort));
return i;
end loop;
report "Device '" & str_trim(NameShort) & "' does not exist!" severity FAILURE;
end function;
function pb_GetDeviceInstance(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; NameShort : STRING) return T_PB_DEVICE_INSTANCE is
begin
return DeviceInstances(pb_GetDeviceInstanceID(DeviceInstances, NameShort));
end function;
function pb_GetDeviceInstance(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_INSTANCE is
begin
return System.DeviceInstances(pb_GetDeviceInstanceID(System, NameShort));
end function;
function pb_GetDeviceDescription(System : T_PB_SYSTEM; NameShort : STRING) return T_PB_DEVICE_DESCRIPTION is
constant DeviceInstance : T_PB_DEVICE_INSTANCE := System.DeviceInstances(pb_GetDeviceInstanceID(System, NameShort));
constant ReadMappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_FilterMappings(DeviceInstance, PB_MAPPING_KIND_READ);
constant WriteMappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_FilterMappings(DeviceInstance, PB_MAPPING_KIND_WRITE);
constant WriteKMappings : T_PB_PORTNUMBER_MAPPING_VECTOR := pb_FilterMappings(DeviceInstance, PB_MAPPING_KIND_WRITEK);
variable Result : T_PB_DEVICE_DESCRIPTION;
begin
Result.DeviceShort := DeviceInstance.DeviceShort;
Result.BusShort := DeviceInstance.BusShort;
Result.ReadMappings := pb_ResizeVec(ReadMappings);
Result.ReadMappingCount := ReadMappings'length;
Result.WriteMappings := pb_ResizeVec(ReadMappings);
Result.WriteMappingCount := WriteMappings'length;
Result.WriteKMappings := pb_ResizeVec(WriteKMappings);
Result.WriteKMappingCount := WriteKMappings'length;
return Result;
end function;
function pb_CreateBus(BusName : STRING; BusShort : STRING; SuperBusShort : STRING) return T_PB_BUS is
variable Result : T_PB_BUS;
begin
-- Result.BusName := pb_LongName(BusName);
Result.BusShort := pb_ShortName(BusShort);
Result.SuperBusShort := pb_ShortName(SuperBusShort);
Result.SuperBusID := 0;
Result.SubBusses := (others => 0);
Result.SubBusCount := 0;
Result.Devices := (others => 0);
Result.DeviceCount := 0;
Result.TotalDeviceCount := 0;
return Result;
end function;
function pb_GetBusID(Busses : T_PB_BUS_VECTOR; BusShort : T_PB_SHORTNAME) return NATURAL is
begin
for i in Busses'range loop
next when (Busses(i).BusShort /= BusShort);
return i;
end loop;
report "Unknown bus name '" & str_trim(BusShort) & "'" severity failure;
end function;
function pb_GetBusID(System : T_PB_SYSTEM; BusShort : T_PB_SHORTNAME) return NATURAL is
begin
return pb_GetBusID(System.Busses(0 to System.BusCount - 1), BusShort);
end function;
function pb_ConnectBusses(Busses : T_PB_BUS_VECTOR) return T_PB_BUS_VECTOR is
variable Result : T_PB_BUS_VECTOR(Busses'range);
variable SuperBusID : T_PB_BUSID;
variable j : T_UINT_8;
begin
for i in Busses'range loop
if (PB_VERBOSE = TRUE) then
report "pb_ConnectBusses: Connecting bus '" & str_trim(Busses(i).BusShort) & "' to '" & str_trim(Busses(i).SuperBusShort) & "'" severity NOTE;
end if;
if (str_length(Busses(i).SuperBusShort) /= 0) then
SuperBusID := pb_GetBusID(Busses, Busses(i).SuperBusShort);
else
SuperBusID := T_PB_BUSID'high;
end if;
-- Result(i).BusName := Busses(i).BusName;
Result(i).BusShort := Busses(i).BusShort;
Result(i).SuperBusShort := Busses(i).SuperBusShort;
Result(i).SuperBusID := SuperBusID;
if (SuperBusID /= T_PB_BUSID'high) then
j := Result(SuperBusID).SubBusCount;
Result(SuperBusID).SubBusses(j) := i;
Result(SuperBusID).SubBusCount := j + 1;
end if;
end loop;
return Result;
end function;
function pb_GetTotalDeviceCount(Busses : T_PB_BUS_VECTOR; BusID : T_PB_BUSID) return T_UINT_8 is
variable Result : T_UINT_8;
begin
Result := 0;
-- report "pb_GetTotalDeviceCount: BusID=" & INTEGER'image(BusID) severity NOTE;
for i in 0 to Busses(BusID).SubBusCount - 1 loop
Result := Result + pb_GetTotalDeviceCount(Busses, Busses(BusID).SubBusses(i));
end loop;
return Result + Busses(BusID).DeviceCount;
end function;
function pb_CreateSystem(SystemName : STRING; SystemShort : STRING; Busses : T_PB_BUS_VECTOR; DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR) return T_PB_SYSTEM is
variable Result : T_PB_SYSTEM;
variable BusID : T_PB_BUSID;
variable j : T_UINT_8;
begin
-- Result.SystemName := pb_LongName(SystemName);
Result.SystemShort := pb_ShortName(SystemShort);
Result.DeviceInstances := pb_ResizeVec(DeviceInstances);
Result.DeviceInstanceCount := DeviceInstances'length;
Result.Busses := pb_ResizeVec(Busses);
Result.BusCount := Busses'length;
-- connect devices to busses
for i in DeviceInstances'range loop
BusID := pb_GetBusID(Busses, DeviceInstances(i).BusShort);
j := Result.Busses(BusID).DeviceCount;
Result.Busses(BusID).Devices(j) := i;
Result.Busses(BusID).DeviceCount := j + 1;
end loop;
-- count devices on a bus
-- TODO: rewrite recursion to local loops
for i in 0 to Result.BusCount - 1 loop
Result.Busses(i).TotalDeviceCount := pb_GetTotalDeviceCount(Result.Busses(0 to Result.BusCount - 1), i);
end loop;
return Result;
end function;
function pb_Resize(RegisterMapping : T_PB_REGISTER_FIELD_MAPPING; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_MAPPING_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_FIELD_MAPPING_INDEX'high);
begin
return RegisterMapping & T_PB_REGISTER_FIELD_MAPPING_VECTOR'(1 to high => C_PB_REGISTER_FIELD_MAPPING_EMPTY);
end function;
function pb_Resize(RegisterField : T_PB_REGISTER_FIELD; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_FIELD_INDEX'high);
begin
return RegisterField & T_PB_REGISTER_FIELD_VECTOR'(1 to high => C_PB_REGISTER_FIELD_EMPTY);
end function;
function pb_Resize(Reg : T_PB_REGISTER; Size : NATURAL := 0) return T_PB_REGISTER_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_INDEX'high);
begin
return Reg & T_PB_REGISTER_VECTOR'(1 to high => C_PB_REGISTER_EMPTY);
end function;
function pb_ResizeVec(RegisterMappings : T_PB_REGISTER_FIELD_MAPPING_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_MAPPING_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_FIELD_MAPPING_INDEX'high);
begin
return RegisterMappings & T_PB_REGISTER_FIELD_MAPPING_VECTOR'(RegisterMappings'length to high => C_PB_REGISTER_FIELD_MAPPING_EMPTY);
end function;
function pb_ResizeVec(RegisterFields : T_PB_REGISTER_FIELD_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_FIELD_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_FIELD_INDEX'high);
begin
return RegisterFields & T_PB_REGISTER_FIELD_VECTOR'(RegisterFields'length to high => C_PB_REGISTER_FIELD_EMPTY);
end function;
function pb_ResizeVec(Registers : T_PB_REGISTER_VECTOR; Size : NATURAL := 0) return T_PB_REGISTER_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_REGISTER_INDEX'high);
begin
return Registers & T_PB_REGISTER_VECTOR'(Registers'length to high => C_PB_REGISTER_EMPTY);
end function;
function pb_ResizeVec(Busses : T_PB_BUS_VECTOR; Size : NATURAL := 0) return T_PB_BUS_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_BUS_INDEX'high);
begin
return Busses & T_PB_BUS_VECTOR'(Busses'length to high => C_PB_BUS_EMPTY);
end function;
function pb_ResizeVec(Mappings : T_PB_PORTNUMBER_MAPPING_VECTOR; Size : NATURAL := 0) return T_PB_PORTNUMBER_MAPPING_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_PORTNUMBER_MAPPING_INDEX'high);
begin
return Mappings & T_PB_PORTNUMBER_MAPPING_VECTOR'(Mappings'length to high => C_PB_PORTNUMBER_MAPPING_EMPTY);
end function;
function pb_ResizeVec(DeviceInstances : T_PB_DEVICE_INSTANCE_VECTOR; Size : NATURAL := 0) return T_PB_DEVICE_INSTANCE_VECTOR is
constant high : T_UINT_8 := ite(Size /= 0, (Size - 1), T_PB_DEVICE_INSTANCE_INDEX'high);
begin
return DeviceInstances & T_PB_DEVICE_INSTANCE_VECTOR'(DeviceInstances'length to high => C_PB_DEVICE_INSTANCE_EMPTY);
end function;
-- PicoBlaze interrupt functions
function pb_GetInterruptCount(System : T_PB_SYSTEM) return NATURAL is
variable Result : NATURAL;
begin
Result := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
if (System.DeviceInstances(i).Device.CreatesInterrupt = TRUE) then
Result := Result + 1;
end if;
end loop;
return Result;
end function;
function pb_GetInterruptPortIndex(System : T_PB_SYSTEM; DeviceShort : STRING) return NATURAL is
variable Result : NATURAL;
begin
Result := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
exit when str_match(System.DeviceInstances(i).DeviceShort, DeviceShort);
Result := Result + 1;
end loop;
return Result;
end function;
function pb_GetInterruptVector(PicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return STD_LOGIC_VECTOR is
variable Result : STD_LOGIC_VECTOR(System.DeviceInstanceCount - 1 downto 0);
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable BusIndex : T_PB_BUSID;
variable InterruptPortID : T_UINT_8;
begin
InterruptPortID := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
BusIndex := pb_GetBusIndex(System, DeviceInstance.DeviceShort);
if (DeviceInstance.Device.CreatesInterrupt = TRUE) then
Result(InterruptPortID) := PicoBlazeBus(BusIndex).Interrupt;
InterruptPortID := InterruptPortID + 1;
end if;
end loop;
return Result(InterruptPortID - 1 downto 0);
end function;
function pb_GetInterruptMessages(PicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return T_SLVV_8 is
variable Result : T_SLVV_8(System.DeviceInstanceCount - 1 downto 0);
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable BusIndex : T_PB_BUSID;
variable InterruptPortID : T_UINT_8;
begin
InterruptPortID := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
BusIndex := pb_GetBusIndex(System, DeviceInstance.DeviceShort);
if (DeviceInstance.Device.CreatesInterrupt = TRUE) then
Result(InterruptPortID) := PicoBlazeBus(BusIndex).Message;
InterruptPortID := InterruptPortID + 1;
end if;
end loop;
return Result(InterruptPortID - 1 downto 0);
end function;
procedure pb_AssignInterruptAck(signal Output : inout T_PB_IOBUS_PB_DEV_VECTOR; Input : STD_LOGIC_VECTOR; System : T_PB_SYSTEM) is
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable BusIndex : T_PB_BUSID;
variable InterruptPortID : NATURAL;
begin
InterruptPortID := 0;
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
BusIndex := pb_GetBusIndex(System, DeviceInstance.DeviceShort);
if (DeviceInstance.Device.CreatesInterrupt = TRUE) then
Output(i).Interrupt_Ack <= Input(InterruptPortID);
InterruptPortID := InterruptPortID + 1;
else
Output(i).Interrupt_Ack <= '0';
end if;
end loop;
end procedure;
-- PicoBlaze AddressDecoder functions
function pb_FilterMappings(DeviceInstance : T_PB_DEVICE_INSTANCE; MappingKind : T_PB_MAPPING_KIND) return T_PB_PORTNUMBER_MAPPING_VECTOR is
variable Result : T_PB_PORTNUMBER_MAPPING_VECTOR(0 to DeviceInstance.MappingCount - 1);
variable ResultCount : NATURAL;
begin
Result := (others => C_PB_PORTNUMBER_MAPPING_EMPTY);
ResultCount := 0;
for i in 0 to DeviceInstance.MappingCount - 1 loop
if (DeviceInstance.Mappings(i).MappingKind = MappingKind) then
Result(ResultCount) := DeviceInstance.Mappings(i);
ResultCount := ResultCount + 1;
end if;
end loop;
return Result(0 to ResultCount - 1);
end function;
-- PicoBlaze bus functions
function pb_GetBusWidth(System : T_PB_SYSTEM; BusShort : STRING) return NATURAL is
constant BUSID : T_PB_BUSID := pb_GetBusID(System, pb_ShortName(BusShort));
begin
return System.Busses(BUSID).TotalDeviceCount;
end function;
function pb_GetBusIndex(System : T_PB_SYSTEM; DeviceShort : STRING) return NATURAL is
constant DeviceInstance : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(System, DeviceShort);
constant DeviceInstanceID : T_PB_DEVICE_INSTANCE_INDEX := pb_GetDeviceInstanceID(System, DeviceShort);
constant BusID : T_PB_BUSID := pb_GetBusID(System, DeviceInstance.BusShort);
constant MyBus : T_PB_BUS := System.Busses(BusID);
variable Result : NATURAL;
begin
-- report "pb_GetBusIndex: DevInstID=" & INTEGER'image(DeviceInstanceID) severity NOTE;
Result := MyBus.TotalDeviceCount - MyBus.DeviceCount;
for i in 0 to MyBus.DeviceCount - 1 loop
-- report "pb_GetBusIndex: Devices(i)=" & INTEGER'image(MyBus.Devices(i)) severity NOTE;
exit when (MyBus.Devices(i) = DeviceInstanceID);
Result := Result + 1;
end loop;
return Result;
end function;
function pb_GetSubBusOffset(System : T_PB_SYSTEM; BusShort : T_PB_SHORTNAME) return NATURAL is
constant BusID : T_PB_BUSID := pb_GetBusID(System, BusShort);
constant SuperBusID : T_PB_BUSID := System.Busses(BusID).SuperBusID;
variable Result : NATURAL;
begin
Result := 0;
for i in 0 to System.Busses(SuperBusID).SubBusCount - 1 loop
if (System.Busses(SuperBusID).SubBusses(i) = BusID) then
return Result;
else
Result := Result + System.Busses(System.Busses(SuperBusID).SubBusses(i)).TotalDeviceCount;
end if;
end loop;
-- report error
end function;
function pb_GetSubOrdinateBus(Input : T_PB_IOBUS_PB_DEV_VECTOR; System : T_PB_SYSTEM; BusShort : STRING) return T_PB_IOBUS_PB_DEV_VECTOR is
constant BusWidth : NATURAL := pb_GetBusWidth(System, BusShort);
constant Offset : NATURAL := pb_GetSubBusOffset(System, pb_ShortName(BusShort));
variable Result : T_PB_IOBUS_PB_DEV_VECTOR(BusWidth - 1 downto 0);
begin
for i in Result'range loop
Result(i) := Input(Offset + i);
end loop;
return Result;
end function;
procedure pb_AssignSubOrdinateBus(signal Output : inout T_PB_IOBUS_DEV_PB_VECTOR; Input : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM; BusShort : STRING) is
constant Offset : NATURAL := pb_GetSubBusOffset(System, pb_ShortName(BusShort));
begin
for i in Input'range loop
Output(Offset + i) <= Input(i);
end loop;
end procedure;
impure function pb_PrintAddressMapping(System : T_PB_SYSTEM) return BOOLEAN is
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable Device : T_PB_DEVICE;
variable Reg : T_PB_REGISTER;
variable Field : T_PB_REGISTER_FIELD_MAPPING;
begin
if (not (PB_VERBOSE or PB_REPORT)) then
return FALSE;
end if;
report "Printing PicoBlaze address mappings..." severity NOTE;
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
Device := DeviceInstance.Device;
report "DeviceInstance " & INTEGER'image(i) & ":" severity NOTE;
report " DeviceInstance: " & str_trim(DeviceInstance.DeviceShort) severity NOTE;
report " Device: " & str_trim(Device.DeviceShort) severity NOTE;
report " Registers: " severity NOTE;
for j in 0 to Device.RegisterCount - 1 loop
Reg := Device.Registers(j);
report " " & INTEGER'image(j) & ": " & str_trim(Reg.RegisterShort) & " Reg#=" & INTEGER'image(Reg.RegisterNumber) & " " &
ite((Reg.RegisterKind = PB_REGISTER_KIND_READ), "RD",
ite((Reg.RegisterKind = PB_REGISTER_KIND_READWRITE), "RW",
ite((Reg.RegisterKind = PB_REGISTER_KIND_WRITE), "WR", "K ")))
severity NOTE;
for k in 0 to Reg.FieldMappingCount - 1 loop
Field := Reg.FieldMappings(k);
report " " & INTEGER'image(k) & ": FieldID=" & INTEGER'image(Field.FieldID) & " (" & str_trim(Device.RegisterFields(Field.FieldID).FieldShort) & ")"
severity NOTE;
end loop;
end loop;
end loop;
return TRUE;
end function;
impure function pb_PrintBusses(System : T_PB_SYSTEM) return BOOLEAN is
variable CurBus : T_PB_BUS;
begin
if (not (PB_VERBOSE or PB_REPORT)) then
return FALSE;
end if;
report "pb_PrintBusses: Count=" & INTEGER'image(System.BusCount) severity NOTE;
for i in 0 to System.BusCount - 1 loop
CurBus := System.Busses(i);
report "BusID " & INTEGER'image(i) & "(" & str_trim(CurBus.BusShort) & ")" severity NOTE;
report " SuperBusID " & INTEGER'image(CurBus.SuperBusID) & "(" & ite((CurBus.SuperBusID /= T_PB_BUSID'high), str_trim(System.Busses(System.Busses(imax(i, T_PB_BUS_INDEX'high)).SuperBusID).BusShort), "----") & ")" severity NOTE;
report " SubBusCount " & INTEGER'image(CurBus.SubBusCount) severity NOTE;
for j in 0 to CurBus.SubBusCount - 1 loop
report " SubBusID " & INTEGER'image(CurBus.SubBusses(j)) & "(" & str_trim(System.Busses(CurBus.SubBusses(j)).BusShort) & ")" severity NOTE;
end loop;
report " DeviceCount " & INTEGER'image(CurBus.DeviceCount) severity NOTE;
for j in 0 to CurBus.DeviceCount - 1 loop
report " DeviceID " & INTEGER'image(CurBus.Devices(j)) & "(" & str_trim(System.DeviceInstances(CurBus.Devices(j)).DeviceShort) & ")" severity NOTE;
end loop;
end loop;
return TRUE;
end function;
impure function pb_ExportAddressMappingAsAssemblerConstants(System : T_PB_SYSTEM; psmFileName : STRING) return BOOLEAN is
file psmFile : TEXT open WRITE_MODE is psmFileName;
variable psmLine : LINE;
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable Mapping : T_PB_PORTNUMBER_MAPPING;
type T_USAGE_TRACKING is record
DeviceInstanceID : T_UINT_8;
MappingID : T_UINT_8;
end record;
type T_ERROR_DETECT is array (NATURAL range <>) of T_USAGE_TRACKING;
variable AddressMapRead : T_ERROR_DETECT(0 to 255);
variable AddressMapWrite : T_ERROR_DETECT(0 to 255);
variable AddressMapWriteK : T_ERROR_DETECT(0 to 15);
variable MappingID : T_UINT_8;
variable DeviceInstanceID : T_UINT_8;
variable RegID : T_UINT_8;
variable Reg : T_PB_REGISTER;
begin
AddressMapRead := (others => (0, 255));
AddressMapWrite := (others => (0, 255));
AddressMapWriteK := (others => (0, 255));
report "Exporting PicoBlaze address mappings as psm-file to '" & psmFileName & "' ..." severity note;
-- psm-file: write file header
write(psmLine, STRING'("; Generate by synthesis for '" & str_trim(System.SystemShort) & "'")); writeline(psmFile, psmLine);
write(psmLine, STRING'(";")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; This file contains the PicoBlaze PortNumber to DeviceRegister mappings.")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; =======================================================================")); writeline(psmFile, psmLine);
-- write per device entires
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
write(psmLine, STRING'(";")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; ") & str_trim(DeviceInstance.DeviceShort)); writeline(psmFile, psmLine);
for j in 0 to DeviceInstance.MappingCount - 1 loop
Mapping := DeviceInstance.Mappings(j);
if (Mapping.MappingKind /= PB_MAPPING_KIND_EMPTY) then
if (PB_VERBOSE = TRUE) then
report " Map PortNumber " & INTEGER'image(Mapping.PortNumber) &
" to device " & INTEGER'image(i) &
" (" & str_trim(DeviceInstance.DeviceShort) &
") register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity NOTE;
end if;
end if;
-- tokenFile content for INPUT address space
if (Mapping.MappingKind = PB_MAPPING_KIND_READ) then
if (AddressMapRead(Mapping.PortNumber).MappingID = 255) then
AddressMapRead(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j); -- save used MappingID for a PortNumber
write(psmLine, "CONSTANT " & resize(
"IPORT_" & str_toUpper(str_trim(DeviceInstance.DeviceShort)) &
"_" & str_toUpper(str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort)) &
", ", 40, ' ') &
ite((Mapping.PortNumber < 10), " ", "") &
ite((Mapping.PortNumber < 100), " ", "") &
INTEGER'image(Mapping.PortNumber) & "'d ; " &
str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & "(");
write(psmLine, STRING'("dummy[3:0]"));
for k in 1 to 1 loop
write(psmLine, STRING'(",dummy[7:4]"));
end loop;
write(psmLine, STRING'(")"));
writeline(psmFile, psmLine);
else
DeviceInstanceID := AddressMapRead(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapRead(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsAssemblerConstants:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
-- tokenFile content for OUTPUT address space
elsif (Mapping.MappingKind = PB_MAPPING_KIND_WRITE) then
if (AddressMapWrite(Mapping.PortNumber).MappingID = 255) then
AddressMapWrite(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j);
write(psmLine, "CONSTANT " & resize(
"OPORT_" & str_toUpper(str_trim(DeviceInstance.DeviceShort)) &
"_" & str_toUpper(str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort)) &
", ", 40, ' ') &
ite((Mapping.PortNumber < 10), " ", "") &
ite((Mapping.PortNumber < 100), " ", "") &
INTEGER'image(Mapping.PortNumber) & "'d ; " &
str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort));
writeline(psmFile, psmLine);
else
DeviceInstanceID := AddressMapWrite(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapWrite(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsAssemblerConstants:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
-- tokenFile content for OUTPUTK address space
elsif (Mapping.MappingKind = PB_MAPPING_KIND_WRITEK) then
if (AddressMapWriteK(Mapping.PortNumber).MappingID = 255) then
AddressMapWriteK(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j);
write(psmLine, "CONSTANT " & resize(
"KPORT_" & str_toUpper(str_trim(DeviceInstance.DeviceShort)) &
"_" & str_toUpper(str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort)) &
", ", 40, ' ') &
ite((Mapping.PortNumber < 10), " ", "") &
ite((Mapping.PortNumber < 100), " ", "") &
INTEGER'image(Mapping.PortNumber) & "'d ; " &
str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort));
writeline(psmFile, psmLine);
else
DeviceInstanceID := AddressMapWriteK(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapWriteK(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsAssemblerConstants:" & LF & "K PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
end if;
end loop;
end loop;
file_close(psmFile);
return true;
end function;
impure function pb_ExportAddressMappingAsAssemblerInterruptVector(System : T_PB_SYSTEM; psmFileName : STRING; TableRows : POSITIVE) return BOOLEAN is
file psmFile : TEXT open WRITE_MODE is psmFileName;
variable psmLine : LINE;
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable j : NATURAL := 0;
begin
report "Exporting PicoBlaze interrupt vector table as psm-file to '" & psmFileName & "' ..." severity note;
-- psm-file: write file header
write(psmLine, STRING'("; Generate by synthesis for '" & str_trim(System.SystemShort) & "'")); writeline(psmFile, psmLine);
write(psmLine, STRING'(";")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; This file contains the PicoBlaze InterruptVector table.")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; =======================================================")); writeline(psmFile, psmLine);
-- write per device entires
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
-- tokenFile content for existing interrupt
if (DeviceInstance.Device.CreatesInterrupt = TRUE) then
write(psmLine, STRING'("JUMP __ISR_") & resize(str_trim(DeviceInstance.DeviceShort), 16, ' ') &
STRING'("; ") & ite((j < 10), STRING'(" "), "") & INTEGER'image(j) &
STRING'(": ") & str_trim(DeviceInstance.DeviceShort));
writeline(psmFile, psmLine);
j := j + 1;
end if;
-- assert not PB_VERBOSE report "pb_ExportAddressMapping: Map PortNumber " & INTEGER'image(Mapping.PortNumber) &
-- " to device " & INTEGER'image(-1) &
-- " (" & str_trim(DeviceInstance.DeviceShort) &
-- ") register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
-- " (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
-- severity NOTE;
end loop;
write(psmLine, STRING'(";")); writeline(psmFile, psmLine);
write(psmLine, STRING'("; catch undefined ISR routines")); writeline(psmFile, psmLine);
for i in j to TableRows - 1 loop
write(psmLine, STRING'("JUMP __ISR_Error ; ") & INTEGER'image(i) & STRING'(": "));
writeline(psmFile, psmLine);
end loop;
file_close(psmFile);
return true;
end function;
impure function pb_ExportAddressMappingAsChipScopeTokens(System : T_PB_SYSTEM; tokenFileName : STRING) return BOOLEAN is
file tokenFile : TEXT open WRITE_MODE is tokenFileName;
variable tokenLine : LINE;
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable Device : T_PB_DEVICE;
variable Mapping : T_PB_PORTNUMBER_MAPPING;
variable PortNumber_slv : T_SLV_8;
type T_USAGE_TRACKING is record
DeviceInstanceID : T_UINT_8;
MappingID : T_UINT_8;
end record;
type T_ERROR_DETECT is array (NATURAL range <>) of T_USAGE_TRACKING;
variable AddressMapRead : T_ERROR_DETECT(0 to 255);
variable AddressMapWrite : T_ERROR_DETECT(0 to 255);
variable AddressMapWriteK : T_ERROR_DETECT(0 to 15);
variable MappingID : T_UINT_8;
variable DeviceInstanceID : T_UINT_8;
variable RegID : T_UINT_8;
variable Reg : T_PB_REGISTER;
begin
AddressMapRead := (others => (0, 255));
AddressMapWrite := (others => (0, 255));
AddressMapWriteK := (others => (0, 255));
report "Exporting PicoBlaze address mappings as token-file to '" & tokenFileName & "'..." severity note;
-- token-file: write file header
write(tokenLine, STRING'("# " & str_trim(System.SystemShort) & " - PortNumbers")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("# ChipScope Token File Version")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("@FILE_VERSION=1.0.0")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("# Default token value")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("@DEFAULT_TOKEN=")); writeline(tokenFile, tokenLine);
-- write per device entires
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("# ") & str_trim(DeviceInstance.DeviceShort)); writeline(tokenFile, tokenLine);
for j in 0 to DeviceInstance.MappingCount - 1 loop
Mapping := DeviceInstance.Mappings(j);
if (PB_VERBOSE = TRUE) then
report " Map PortNumber " & INTEGER'image(Mapping.PortNumber) &
" to device " & INTEGER'image(i) &
" (" & str_trim(DeviceInstance.DeviceShort) &
") register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity NOTE;
end if;
-- tokenFile content for INPUT address space
if (Mapping.MappingKind = PB_MAPPING_KIND_READ) then
if (AddressMapRead(Mapping.PortNumber).MappingID = 255) then
PortNumber_slv := to_slv(Mapping.PortNumber, 8);
AddressMapRead(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j); -- save used MappingID for a PortNumber
write(tokenLine, "RD_" & str_trim(DeviceInstance.DeviceShort) & "_" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & "=2" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
else
DeviceInstanceID := AddressMapRead(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapRead(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsChipScopeTokens:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
-- tokenFile content for OUTPUT address space
elsif (Mapping.MappingKind = PB_MAPPING_KIND_WRITE) then
PortNumber_slv := to_slv(Mapping.PortNumber, 8);
if (AddressMapWrite(Mapping.PortNumber).MappingID = 255) then
AddressMapWrite(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j);
write(tokenLine, "WR_" & str_trim(DeviceInstance.DeviceShort) & "_" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & "=1" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
else
DeviceInstanceID := AddressMapWrite(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapWrite(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsChipScopeTokens:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
-- tokenFile content for OUTPUTK address space
elsif (Mapping.MappingKind = PB_MAPPING_KIND_WRITEK) then
if (AddressMapWriteK(Mapping.PortNumber).MappingID = 255) then
AddressMapWriteK(Mapping.PortNumber) := (DeviceInstanceID => i, MappingID => j);
for k in 0 to 15 loop
PortNumber_slv := to_slv(k, 4) & to_slv(Mapping.PortNumber, 4);
write(tokenLine, STRING'("WK_" & str_trim(DeviceInstance.DeviceShort) & "_" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & "=4" & to_string(PortNumber_slv, 'h', 2)));
writeline(tokenFile, tokenLine);
end loop;
else
DeviceInstanceID := AddressMapWriteK(Mapping.PortNumber).DeviceInstanceID;
MappingID := AddressMapWriteK(Mapping.PortNumber).MappingID;
RegID := System.DeviceInstances(DeviceInstanceID).Mappings(MappingID).RegID;
Reg := System.DeviceInstances(DeviceInstanceID).Device.Registers(RegID);
report "pb_ExportAddressMappingAsChipScopeTokens:" & LF & "PortNumber " & INTEGER'image(Mapping.PortNumber) &
" is already used by " & str_trim(System.DeviceInstances(DeviceInstanceID).DeviceShort) &
" register " & INTEGER'image(Reg.RegisterNumber) &
" (" & str_trim(Reg.RegisterShort) & ")." & LF &
"This overlaps with device " & str_trim(DeviceInstance.DeviceShort) &
" register " & INTEGER'image(DeviceInstance.Device.Registers(Mapping.RegID).RegisterNumber) &
" (" & str_trim(DeviceInstance.Device.Registers(Mapping.RegID).RegisterShort) & ")."
severity FAILURE;
end if;
end if;
end loop;
end loop;
-- write tokens for unused PortNumbers
write(tokenLine, STRING'("#")); writeline(tokenFile, tokenLine);
write(tokenLine, STRING'("# unused PortNumbers")); writeline(tokenFile, tokenLine);
for i in AddressMapWrite'range loop
PortNumber_slv := to_slv(i, 8);
if (AddressMapWrite(i).MappingID = 255) then
write(tokenLine, "WR_ERR" & "=1" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
end if;
end loop;
for i in AddressMapRead'range loop
PortNumber_slv := to_slv(i, 8);
if (AddressMapRead(i).MappingID = 255) then
write(tokenLine, "RD_ERR" & "=2" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
end if;
end loop;
for i in AddressMapWriteK'range loop
if (AddressMapWriteK(i).MappingID = 255) then
for k in 0 to 15 loop
PortNumber_slv := to_slv(k, 4) & to_slv(i, 4);
write(tokenLine, "WK_ERR" & "=4" & to_string(PortNumber_slv, 'h', 2));
writeline(tokenFile, tokenLine);
end loop;
end if;
end loop;
file_close(tokenFile);
return true;
end function;
end package body;
| apache-2.0 | 9b482a8d0b5b51d25f9fbdc5392cb1a2 | 0.684623 | 3.557752 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/rlink_sp1c.vhd | 1 | 6,174 | -- $Id: rlink_sp1c.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c - syn
-- Description: rlink_core8 + serport_1clock combo
--
-- Dependencies: rlink_core8
-- serport/serport_1clock
-- rbus/rbd_rbmon
-- rbus/rb_sres_or_2
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2015-05-02 672 14.7 131013 xc6slx16-2 495 671 56 255 s 8.8 - -
-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
-- 2015-05-02 672 4.2 add rbd_rbmon (optional via generics)
-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL, rearrange XON handling
-- 2014-08-28 588 4.0 use rlink v4 iface, 4 bit STAT
-- 2011-12-09 437 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity rlink_sp1c is -- rlink_core8+serport_1clock combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ESCFILL : in slbit; -- enable fill escaping
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
SER_MONI : out serport_moni_type -- serport: monitor port
);
end entity rlink_sp1c;
architecture syn of rlink_sp1c is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
signal RB_SRES_M : rb_sres_type := rb_sres_init;
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
begin
CORE : rlink_core8 -- rlink master ----------------------
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
SYSID => SYSID,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RLBMON=> ENAPIN_RLBMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
ESCXON => ENAXON,
ESCFILL => ESCFILL,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_M,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock -- serport interface -----------------
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => '0', -- escaping now in rlink_core8
RXDATA => RLB_DI,
RXVAL => RLB_ENA,
RXHOLD => RLB_BUSY,
TXDATA => RLB_DO,
TXENA => RLB_VAL,
TXBUSY => RLB_HOLD,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
begin
I0 : rbd_rbmon
generic map (
RB_ADDR => RBMON_RBADDR,
AWIDTH => RBMON_AWIDTH)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_RBMON,
RB_SRES_SUM => RB_SRES_M
);
end generate RBMON;
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES,
RB_SRES_2 => RB_SRES_RBMON,
RB_SRES_OR => RB_SRES_M
);
RB_MREQ <= RB_MREQ_M; -- setup output signals
end syn;
| gpl-3.0 | d5d3608a771c0822e1ed4c134375ce82 | 0.502592 | 3.550316 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rbd_timer.vhd | 1 | 4,244 | -- $Id: rbd_timer.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_timer - syn
-- Description: rbus dev: usec precision timer
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-29 351 12.1 M53d xc3s1000-4 19 63 - 34 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 0 time r/w/- Timer register
-- w: if > 0 timer is running
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
entity rbd_timer is -- rbus dev: usec precision timer
generic (
RB_ADDR : slv16 := (others=>'0'));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DONE : out slbit; -- 1 cycle pulse when expired
BUSY : out slbit -- timer running
);
end entity rbd_timer;
architecture syn of rbd_timer is
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
timer : slv16; -- timer value
timer_act : slbit; -- timer active flag
timer_end : slbit; -- timer done flag
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- timer
'0','0' -- timer_act,timer_end
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, RB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_dout := (others=>'0');
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr=RB_ADDR then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := RB_MREQ.re or RB_MREQ.we;
if RB_MREQ.we = '1' then
n.timer := RB_MREQ.din;
n.timer_act := '1';
end if;
if RB_MREQ.re = '1' then
irb_dout := r.timer;
end if;
end if;
-- timer logic
-- count down when active and 'on-the-usec'
n.timer_end := '0'; -- ensure end is 1 cycle pulse
if CE_USEC = '1' then -- if at usec
if r.timer_act = '1' then -- if timer active
if unsigned(r.timer) = 0 then -- if timer at end
n.timer_act := '0'; -- mark unactive
n.timer_end := '1'; -- send end marker
else -- else: timer not at end
n.timer := slv(unsigned(r.timer) - 1); -- decrement
end if;
end if;
end if;
N_REGS <= n;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= '0';
RB_SRES.busy <= '0';
DONE <= r.timer_end;
BUSY <= r.timer_act;
end process proc_next;
end syn;
| gpl-3.0 | 492c8e3c62aca550a6eab14d9752b219 | 0.483035 | 3.521992 | false | false | false | false |
sjohann81/hf-risc | mips/platform/spartan3_starterkit/spartan3_SRAM.vhd | 1 | 5,154 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
uart_support : string := "yes"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
int_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic;
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0);
ram_address: out std_logic_vector(31 downto 2);
ram_data: inout std_logic_vector(31 downto 0);
ram_ce1_n: out std_logic;
ram_ub1_n: out std_logic;
ram_lb1_n: out std_logic;
ram_ce2_n: out std_logic;
ram_ub2_n: out std_logic;
ram_lb2_n: out std_logic;
ram_we_n: out std_logic;
ram_oe_n: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, stall_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal data_we, data_w_cpu: std_logic_vector(3 downto 0);
signal we_n_next : std_logic;
signal we_n_reg : std_logic;
signal data_reg : std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock, we_n_next)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
if reset_in = '1' then
we_n_reg <= '1';
elsif rising_edge(clk_in) then
we_n_reg <= we_n_next or not clock;
end if;
if reset_in = '1' then
data_read_ram <= (others => '0');
elsif rising_edge(clock) then
data_read_ram <= ram_data;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
-- HF-RISC core
core: entity work.datapath
port map( clock => clock,
reset => reset,
stall => stall_cpu,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
data_access => data_access_cpu
);
-- peripherals / busmux logic
peripherals_busmux: entity work.busmux
generic map(
uart_support => uart_support
)
port map(
clock => clock,
reset => reset,
stall => stall,
stall_cpu => stall_cpu,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
data_access_cpu => data_access_cpu,
addr_mem => address,
data_read_mem => data_read,
data_write_mem => data_write,
data_we_mem => data_we,
extio_in => extio_in,
extio_out => extio_out,
uart_read => uart_read,
uart_write => uart_write
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external SRAM)
-- very simple SRAM memory controller using both IS61LV25616AL chips.
-- these SRAMs have 16-bit words, so we use both chips and access each using low and
-- high banks. using this arrangement, we have byte addressable 32-bit words.
-- the address bus is controlled directly by the CPU.
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
ram_address <= address(31 downto 2);
ram_we_n <= we_n_reg;
ram_control:
process(clock, ram_enable_n, data_we, data_write)
begin
if ram_enable_n = '0' then --SRAM
ram_ce1_n <= '0';
ram_ce2_n <= '0';
if data_we = "0000" then -- read
ram_data <= (others => 'Z');
ram_ub1_n <= '0';
ram_lb1_n <= '0';
ram_ub2_n <= '0';
ram_lb2_n <= '0';
we_n_next <= '1';
ram_oe_n <= '0';
else -- write
if clock = '1' then
ram_data <= (others => 'Z');
else
ram_data <= data_write;
end if;
ram_ub1_n <= not data_we(3);
ram_lb1_n <= not data_we(2);
ram_ub2_n <= not data_we(1);
ram_lb2_n <= not data_we(0);
we_n_next <= '0';
ram_oe_n <= '1';
end if;
else
ram_data <= (others => 'Z');
ram_ce1_n <= '1';
ram_ub1_n <= '1';
ram_lb1_n <= '1';
ram_ce2_n <= '1';
ram_ub2_n <= '1';
ram_lb2_n <= '1';
we_n_next <= '1';
ram_oe_n <= '1';
end if;
end process;
end top_level;
| gpl-2.0 | 6d716a10693dd04857e1ecccf63541ec | 0.61234 | 2.540168 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01800_bad.vhd | 1 | 2,989 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01800_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of falling edge detection signal: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01800_bad is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Signal on which detect edges
o_D : out std_logic -- Falling edge of i_D
);
end CNE_01800_bad;
architecture Behavioral of CNE_01800_bad is
signal D_r1 : std_logic; -- i_D registered 1 time
signal D_r2 : std_logic; -- i_D registered 2 times
begin
-- Rising edge detection process
P_detection: process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D_r1 <= '0';
D_r2 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
D_r2 <= D_r1;
end if;
end process;
o_D <= not D_r1 and D_r2;
end Behavioral;
--CODE | gpl-3.0 | 6b48a8562012a8fceeca9f0a6f6d7d71 | 0.485447 | 4.376281 | false | false | false | false |
sjohann81/hf-risc | riscv/platform/spartan3e_nexys2/spartan3e_nexys2_basic_soc.vhd | 1 | 4,991 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 15;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (rst_i, clk_i, clock)
begin
if rst_i = '1' then
clock <= '0';
else
if clk_i'event and clk_i = '1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, rst_i)
begin
if (rst_i = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | f99fe54cc3e0d95bf32726b92cda1ff6 | 0.630535 | 2.608991 | false | false | false | false |
wfjm/w11 | rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd | 1 | 2,953 | -- $Id: ioleds_sp1c_fx2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ioleds_sp1c_fx2 - syn
-- Description: io activity leds for rlink+serport_1clk+fx2_ic combo
--
-- Dependencies: genlib/led_pulse_stretch
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity ioleds_sp1c_fx2 is -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end entity ioleds_sp1c_fx2;
architecture syn of ioleds_sp1c_fx2 is
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
signal TXENA_LED : slbit := '0';
signal RXVAL_LED : slbit := '0';
begin
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.rxval,
POUT => RXVAL_LED
);
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.txena,
POUT => TXENA_LED
);
proc_leddiv: process (CLK)
begin
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
end process proc_leddiv;
proc_ledmux : process (ENAFX2, SER_MONI, RLB_MONI, RB_SRES,
TXENA_LED, RXVAL_LED)
begin
if ENAFX2 = '0' then
IOLEDS(3) <= not SER_MONI.txok;
IOLEDS(2) <= SER_MONI.txact;
IOLEDS(1) <= not SER_MONI.rxok;
IOLEDS(0) <= SER_MONI.rxact;
else
IOLEDS(3) <= RB_SRES.busy;
IOLEDS(2) <= RLB_MONI.txbusy;
IOLEDS(1) <= TXENA_LED;
IOLEDS(0) <= RXVAL_LED;
end if;
end process proc_ledmux;
end syn;
| gpl-3.0 | 6cb10d979ace7b533f4df6171814a164 | 0.51981 | 3.371005 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/bp_swibtnled.vhd | 1 | 3,160 | -- $Id: bp_swibtnled.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: bp_swibtnled - syn
-- Description: Generic SWI, BTN and LED handling
--
-- Dependencies: xlib/iob_reg_i_gen
-- xlib/iob_reg_o_gen
-- genlib/debounce_gen
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4-2015.4; ghdl 0.26-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.0 Initial version, extracted from s3_humanio
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end bp_swibtnled;
architecture syn of bp_swibtnled is
signal RI_SWI : slv(SWIDTH-1 downto 0) := (others=>'0');
signal RI_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
begin
IOB_SWI : iob_reg_i_gen
generic map (DWIDTH => SWIDTH)
port map (CLK => CLK, CE => '1', DI => RI_SWI, PAD => I_SWI);
IOB_BTN : iob_reg_i_gen
generic map (DWIDTH => BWIDTH)
port map (CLK => CLK, CE => '1', DI => RI_BTN, PAD => I_BTN);
IOB_LED : iob_reg_o_gen
generic map (DWIDTH => LWIDTH)
port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
DEB: if DEBOUNCE generate
DEB_SWI : debounce_gen
generic map (
CWIDTH => 2,
CEDIV => 3,
DWIDTH => SWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE_INT => CE_MSEC,
DI => RI_SWI,
DO => SWI
);
DEB_BTN : debounce_gen
generic map (
CWIDTH => 2,
CEDIV => 3,
DWIDTH => BWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE_INT => CE_MSEC,
DI => RI_BTN,
DO => BTN
);
end generate DEB;
NODEB: if not DEBOUNCE generate
SWI <= RI_SWI;
BTN <= RI_BTN;
end generate NODEB;
end syn;
| gpl-3.0 | ba8b38e84ed7e111ef52f0e768f60659 | 0.5 | 3.615561 | false | false | false | false |
wfjm/w11 | rtl/vlib/cdclib/cdc_value.vhd | 1 | 2,447 | -- $Id: cdc_value.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cdc_value - syn
-- Description: clock domain crossing for a slowly changing value
--
-- Dependencies: cdc_pulse
-- cdc_vector_s0
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-02 1101 2.0 reinplement using cdc_pulse and cdc_vector_s0
-- 2016-04-08 459 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.cdclib.all;
entity cdc_value is -- cdc for value (slow change)
generic (
DWIDTH : positive := 16); -- data port width
port (
CLKI : in slbit; -- I|input clock
CLKO : in slbit; -- O|output clock
DI : in slv(DWIDTH-1 downto 0); -- I|input data
DO : out slv(DWIDTH-1 downto 0); -- O|output data
UPDT : out slbit -- O|output data updated
);
end entity cdc_value;
architecture syn of cdc_value is
subtype d_range is integer range DWIDTH-1 downto 0;
signal R_DI : slv(d_range) := (others=>'0');
signal R_UPDT : slbit := '0';
signal PULSE_PIN : slbit := '0';
signal PULSE_BUSY : slbit := '0';
signal PULSE_POUT : slbit := '0';
begin
CDC_ENA: cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => true)
port map (
CLKM => CLKI,
RESET => '0',
CLKS => CLKO,
PIN => PULSE_PIN,
BUSY => PULSE_BUSY,
POUT => PULSE_POUT
);
CDC_DOUT : cdc_vector_s0
generic map (
DWIDTH => DWIDTH)
port map (
CLKO => CLKO,
ENA => PULSE_POUT,
DI => R_DI,
DO => DO
);
PULSE_PIN <= not PULSE_BUSY;
proc_clki: process (CLKI)
begin
if rising_edge(CLKI) then
if PULSE_PIN = '1' then
R_DI <= DI;
end if;
end if;
end process proc_clki;
proc_clko: process (CLKO)
begin
if rising_edge(CLKO) then
R_UPDT <= PULSE_POUT;
end if;
end process proc_clko;
UPDT <= R_UPDT;
end syn;
| gpl-3.0 | dba397f1b4ad75a461bd4dafad1b13b7 | 0.520638 | 3.541245 | false | false | false | false |
wfjm/w11 | rtl/ibus/iblib.vhd | 1 | 8,739 | -- $Id: iblib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: iblib
-- Description: Definitions for ibus interface and bus entities
--
-- Dependencies: -
-- Tool versions: ise 8.1-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-23 1136 2.2.4 add CLK port to ib_intmap,ib_intmap24
-- 2019-04-14 1131 2.2.3 ib_rlim_gen: add CPUSUSP port; RLIM_CEV now slv8
-- 2019-03-17 1123 2.2.2 add ib_rlim_gen,ib_rlim_slv
-- 2019-02-10 1111 2.2.1 add ibd_ibtst
-- 2017-01-28 846 2.2 add ib_intmap24
-- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type
-- 2015-04-24 668 2.1 add ibd_ibmon
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon
-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw
-- 2010-06-11 303 1.1 added racc,cacc signals to ib_mreq_type
-- 2009-06-01 221 1.0.1 added dip signal to ib_mreq_type
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package iblib is
type ib_mreq_type is record -- ibus - master request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
rmw : slbit; -- read-modify-write
be0 : slbit; -- byte enable low
be1 : slbit; -- byte enable high
cacc : slbit; -- console access
racc : slbit; -- remote access
addr : slv13_1; -- address bit(12:1)
din : slv16; -- data (input to slave)
end record ib_mreq_type;
constant ib_mreq_init : ib_mreq_type :=
('0','0','0','0', -- aval, re, we, rmw
'0','0','0','0', -- be0, be1, cacc, racc
(others=>'0'), -- addr
(others=>'0')); -- din
type ib_sres_type is record -- ibus - slave response
ack : slbit; -- acknowledge
busy : slbit; -- busy
dout : slv16; -- data (output from slave)
end record ib_sres_type;
constant ib_sres_init : ib_sres_type :=
('0','0', -- ack, busy
(others=>'0')); -- dout
type ib_sres_vector is array (natural range <>) of ib_sres_type;
subtype ibf_byte1 is integer range 15 downto 8;
subtype ibf_byte0 is integer range 7 downto 0;
component ib_sel is -- ibus address select logic
generic (
IB_ADDR : slv16; -- ibus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
IB_MREQ : in ib_mreq_type; -- ibus request
SEL : out slbit -- select state bit
);
end component;
component ib_sres_or_2 is -- ibus result or, 2 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_3 is -- ibus result or, 3 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_4 is -- ibus result or, 4 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_gen is -- ibus result or, generic
generic (
WIDTH : natural := 4); -- number of input ports
port (
IB_SRES_IN : in ib_sres_vector(1 to WIDTH); -- ib_sres input array
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
type intmap_type is record -- interrupt map entry type
vec : natural; -- vector address
pri : natural; -- priority
end record intmap_type;
constant intmap_init : intmap_type := (0,0);
type intmap_array_type is array (15 downto 0) of intmap_type;
constant intmap_array_init : intmap_array_type := (others=>intmap_init);
component ib_intmap is -- external interrupt mapper (15 line)
generic (
INTMAP : intmap_array_type := intmap_array_init);
port (
CLK : in slbit; -- clock
EI_REQ : in slv16_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end component;
type intmap24_array_type is array (23 downto 0) of intmap_type;
constant intmap24_array_init : intmap24_array_type := (others=>intmap_init);
component ib_intmap24 is -- external interrupt mapper (23 line)
generic (
INTMAP : intmap24_array_type := intmap24_array_init);
port (
CLK : in slbit; -- clock
EI_REQ : in slv24_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv24_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end component;
component ibd_ibmon is -- ibus dev: ibus monitor
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16));
AWIDTH : natural := 9);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus: request
IB_SRES : out ib_sres_type; -- ibus: response
IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor)
);
end component;
component ibd_ibtst is -- ibus dev(rem): ibus tester
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#170000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component ib_rlim_gen is -- ibus rate limter - master
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
CPUSUSP : in slbit; -- cpu suspended
RLIM_CEV : out slv8 -- clock enable vector
);
end component;
component ib_rlim_slv is -- ibus rate limter - slave
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
RLIM_CEV : in slv8; -- clock enable vector
SEL : in slv3; -- rlim select
START : in slbit; -- start timer
STOP : in slbit; -- stop timer
DONE : out slbit; -- 1 cycle pulse when expired
BUSY : out slbit -- timer running
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end component;
end package iblib;
| gpl-3.0 | 2bb9df3b31f15dfae37e31fe5b1882de | 0.518709 | 3.687342 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/cmoda7/sys_conf.vhd | 1 | 1,926 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_c7 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.1; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | feb37777a81b35c675c41acb8532510f | 0.623053 | 3.586592 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd | 1 | 11,977 | -- $Id: sys_tst_rlink_cuff_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_n3 - syn
-- Description: rlink tester design for nexys3 with fx2 interface
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2014-12-20 614 14.4 131013 xc6slx16-2 1029 1519 104 566 p 9.2 ic2/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-25 638 1.2.2 retire fx2_2fifoctl_as
-- 2014-12-24 620 1.2.1 relocate hio rbus address
-- 2014-08-15 583 1.2 rb_mreq addr now 16 bit
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_rlink_cuff_n2
-- and sys_tst_fx2loop_n3
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (1) timer 1 busy
-- (0) timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back pressure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_n3 is -- top level
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_n3;
architecture syn of sys_tst_rlink_cuff_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
| gpl-3.0 | 7ea9a84a924daa2ab3b3811c20ab4d33 | 0.491108 | 3.074968 | false | false | false | false |
wfjm/w11 | rtl/vlib/simlib/simbididly.vhd | 1 | 3,782 | -- $Id: simbididly.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: simbididly - sim
-- Description: Bi-directional bus delay for test benches
--
-- Dependencies: -
-- Test bench: tb_simbididly
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.0.1 ensure non-zero DELAY
-- 2016-07-17 789 1.0 Initial version (use separate driver regs now)
-- 2016-07-16 787 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity simbididly is -- test bench bi-directional bus delay
generic (
DELAY : Delay_length; -- transport delay between A and B (>0ns!)
DWIDTH : positive := 16); -- data port width
port (
A : inout slv(DWIDTH-1 downto 0); -- port A
B : inout slv(DWIDTH-1 downto 0) -- port B
);
end entity simbididly;
architecture sim of simbididly is
type state_type is (
s_idle, -- s_idle: both ports high-z
s_a2b, -- s_a2b: A drives, B listens
s_b2a -- s_b2a: B drives, A listens
);
constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_STATE : state_type := s_idle;
signal R_A : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_B : slv(DWIDTH-1 downto 0) := (others=>'Z');
begin
process
variable istate : state_type := s_idle;
begin
-- the delay model can enter into a delta cycle oszillation mode
-- when DELAY is 0 ns. So ensure the delay is non-zero
assert DELAY > 0 ns report "DELAY > 0 ns" severity failure;
while true loop
-- if idle check whether A or B port starts to drive bus
-- Note: both signal R_STATE and variable istate is updated
-- istate is needed to control the driver section below in the
-- same delta cycle based on the most recent state state
istate := R_STATE;
if now > 0 ns then -- to avoid startup problems
if R_STATE = s_idle then
if A /= all_z then
R_STATE <= s_a2b;
istate := s_a2b;
elsif B /= all_z then
R_STATE <= s_b2a;
istate := s_b2a;
end if;
end if;
end if;
case istate is
when s_a2b =>
R_B <= transport A after DELAY;
if A = all_z then R_STATE <= s_idle after DELAY; end if;
when s_b2a =>
R_A <= transport B after DELAY;
if B = all_z then R_STATE <= s_idle after DELAY; end if;
when others => null;
end case;
-- Note: the driver clash check is done by comparing an internal signal
-- with the external signal. If they differ this indicates a clash.
-- Just checking for 'x' gives false alarms when the bus is driven
-- with 'x', which can for example come from a memory model before
-- valid data is available.
if now > 0 ns then -- to avoid startup problems
case istate is
when s_a2b =>
assert B = R_B report "driver clash B port" severity error;
when s_b2a =>
assert A = R_A report "driver clash A port" severity error;
when others => null;
end case;
end if;
wait on A,B;
end loop;
end process;
A <= R_A;
B <= R_B;
end sim;
| gpl-3.0 | ffe11f09f21fafb81381b6f5b8b4557b | 0.543892 | 3.824065 | false | false | false | false |
mossmann/hackrf | firmware/cpld/sgpio_debug/top.vhd | 1 | 5,995 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_SYNC_EN : in std_logic;
HOST_SYNC_CMD : out std_logic;
HOST_SYNC : in std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic;
B2AUX1 : out std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_rx_i : std_logic;
signal codec_clk_tx_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal host_sync_enable : std_logic := '0';
signal host_sync_o : std_logic := '0';
signal host_sync_i : std_logic := '0';
signal host_sync_latched : std_logic := '0';
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal compare_counter : std_logic_vector(7 downto 0);
signal glitch_detected_o : std_logic;
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
HOST_CAPTURE <= host_data_capture_o;
host_sync_enable <= HOST_SYNC_EN;
host_sync_i <= HOST_SYNC;
HOST_SYNC_CMD <= host_sync_o;
B2AUX1 <= glitch_detected_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
------------------------------------------------
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7f" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
codec_clk_rx_i <= CODEC_CLK;
adc_data_i <= DA(7 downto 0);
if (transfer_direction_i = from_adc) then
data_to_host_o <= data_to_host_o + 1;
end if;
end if;
end process;
process(host_clk_i)
begin
if falling_edge(host_clk_i) then
codec_clk_tx_i <= CODEC_CLK;
data_from_host_i <= HOST_DATA;
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
if data_from_host_i /= compare_counter then
glitch_detected_o <= '1';
else
glitch_detected_o <= '0';
end if;
compare_counter <= data_from_host_i + 1;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process (host_data_enable_i, host_sync_i)
begin
host_sync_o <= host_data_enable_i;
if host_data_enable_i = '1' then
if rising_edge(host_sync_i) then
host_sync_latched <= host_sync_i;
end if;
else
host_sync_latched <= '0';
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
else
if codec_clk_rx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 3310bce691e49d1f93a02c95b914c934 | 0.521435 | 3.698334 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_lp11_buf.vhd | 1 | 10,440 | -- $Id: ibdr_lp11_buf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_lp11_buf - syn
-- Description: ibus dev(rem): LP11
--
-- Dependencies: fifo_simple_dram
-- ib_rlim_slv
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2017.2-2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-05-31 1156 1.0.4 size->fuse rename; re-organize rlim handling
-- 2019-04-24 1138 1.0.3 add csr.ir (intreq monitor)
-- 2019-04-20 1134 1.0.2 remove fifo clear on BRESET
-- 2019-04-14 1131 1.0.1 RLIM_CEV now slv8
-- 2019-03-17 1123 1.0 Initial version
-- 2019-03-10 1121 0.1 First draft (derived from ibdr_lp11)
------------------------------------------------------------------------------
--
-- Notes:
-- - the ERR bit is just a status flag
-- - no hardware interlock (DONE forced 0 when ERR=1), like in simh
-- - also no interrupt when ERR goes 1, like in simh
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_lp11_buf is -- ibus dev(rem): LP11 (buffered)
-- fixed address: 177514
generic (
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_lp11_buf;
architecture syn of ibdr_lp11_buf is
constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16));
constant ibaddr_csr : slv1 := "0"; -- csr address offset
constant ibaddr_buf : slv1 := "1"; -- buf address offset
constant csr_ibf_err : integer := 15;
subtype csr_ibf_rlim is integer range 14 downto 12;
subtype csr_ibf_type is integer range 10 downto 8;
constant csr_ibf_done : integer := 7;
constant csr_ibf_ie : integer := 6;
constant csr_ibf_ir : integer := 5;
constant buf_ibf_val : integer := 15;
subtype buf_ibf_fuse is integer range AWIDTH-1+8 downto 8;
subtype buf_ibf_data is integer range 6 downto 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
err : slbit; -- csr: error flag
rlim : slv3; -- csr: rate limit
done : slbit; -- csr: done flag
ie : slbit; -- csr: interrupt enable
intreq : slbit; -- interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- err !! is set !!
"000", -- rlim
'1', -- done !! is set !!
'0', -- ie
'0' -- intreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal PBUF_CE : slbit := '0';
signal PBUF_WE : slbit := '0';
signal PBUF_DO : slv7 := (others=>'0');
signal PBUF_RESET : slbit := '0';
signal PBUF_EMPTY : slbit := '0';
signal PBUF_FULL : slbit := '0';
signal PBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RLIM_START : slbit := '0';
signal RLIM_BUSY : slbit := '0';
begin
assert AWIDTH>=4 and AWIDTH<=7
report "assert(AWIDTH>=4 and AWIDTH<=7): unsupported AWIDTH"
severity failure;
PBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 7)
port map (
CLK => CLK,
RESET => PBUF_RESET,
CE => PBUF_CE,
WE => PBUF_WE,
DI => IB_MREQ.din(buf_ibf_data),
DO => PBUF_DO,
EMPTY => PBUF_EMPTY,
FULL => PBUF_FULL,
SIZE => PBUF_FUSE
);
RLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rlim,
START => RLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.err <= N_REGS.err; -- keep ERR flag
R_REGS.rlim <= N_REGS.rlim; -- keep RLIM flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK, RESET, BRESET,
PBUF_DO, PBUF_EMPTY, PBUF_FULL, PBUF_FUSE, RLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable iback : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable ipbufce : slbit := '0';
variable ipbufwe : slbit := '0';
variable irlimsta : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
iback := r.ibsel and ibreq;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
ipbufce := '0';
ipbufwe := '0';
irlimsta := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then -- ibus selected ---------------------
case IB_MREQ.addr(1 downto 1) is
when ibaddr_csr => -- CSR -- control status -------------
idout(csr_ibf_err) := r.err;
idout(csr_ibf_done) := r.done;
idout(csr_ibf_ie) := r.ie;
if IB_MREQ.racc = '0' then -- cpu
if ibw0 = '1' then
n.ie := IB_MREQ.din(csr_ibf_ie);
if IB_MREQ.din(csr_ibf_ie) = '1' then
if r.done='1' and r.ie='0' then -- ie set while done=1
n.intreq := '1'; -- request interrupt
end if;
else
n.intreq := '0';
end if;
end if;
else -- rri
idout(csr_ibf_rlim) := r.rlim;
idout(csr_ibf_type) := slv(to_unsigned(AWIDTH,3));
idout(csr_ibf_ir) := r.intreq;
if ibw1 = '1' then
n.err := IB_MREQ.din(csr_ibf_err);
n.rlim := IB_MREQ.din(csr_ibf_rlim);
if IB_MREQ.din(csr_ibf_err) = '1' then
n.done := '1';
n.intreq := '0'; -- clear irupt (like simh!)
end if;
end if;
end if;
when ibaddr_buf => -- BUF -- data buffer ----------------
if IB_MREQ.racc = '0' then -- cpu
if ibw0 = '1' then
if r.done = '1' then -- ignore buf write when done=0
n.done := '0'; -- clear done
n.intreq := '0'; -- clear interrupt
if r.err = '0' then -- if online (handle via rbus)
if PBUF_FULL = '0' then -- fifo not full
ipbufce := '1'; -- write to fifo
ipbufwe := '1';
if PBUF_EMPTY = '1' then -- first write to empty fifo
ilam := '1'; -- request attention
end if;
end if; -- PBUF_FULL = '0'
else -- if offline (discard locally)
null;
end if; -- r.err = '0'
end if; -- r.done = '1'
end if; -- ibw0 = '1'
else -- rri
idout(buf_ibf_val) := not PBUF_EMPTY;
idout(buf_ibf_fuse) := PBUF_FUSE;
idout(buf_ibf_data) := PBUF_DO;
if ibrd = '1' then
if PBUF_EMPTY = '0' then -- fifo not empty
ipbufce := '1'; -- read from fifo
ipbufwe := '0';
else -- read from empty fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when others => null;
end case;
else -- ibus not selected -----------------
-- handle done, timer and interrupt
if PBUF_FULL='0' and RLIM_BUSY='0' then -- not full and not busy ?
if r.done = '0' then -- done not set ?
n.done := '1'; -- set done
irlimsta := '1'; -- start timer
if r.err='0' and r.ie='1' then -- err=0 and irupt enabled ?
n.intreq := '1'; -- request interrupt
end if;
end if;
end if;
end if; -- else r.ibsel='1'
-- other state changes
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
PBUF_RESET <= RESET or r.err;
PBUF_CE <= ipbufce;
PBUF_WE <= ipbufwe;
RLIM_START <= irlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ <= r.intreq;
end process proc_next;
end syn;
| gpl-3.0 | e61d25ec81bc87ad9061c3cb1525faa3 | 0.454981 | 3.777135 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/serport_xonrx_tb.vhd | 1 | 3,843 | -- $Id: serport_xonrx_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_xonrx_tb - sim
-- Description: serial port: xon/xoff logic rx path (SIM only!)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-03 724 1.0 Initial version (copied from serport_xonrx)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib_tb.all;
entity serport_xonrx_tb is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end serport_xonrx_tb;
architecture sim of serport_xonrx_tb is
type regs_type is record
txok : slbit; -- tx channel ok state
escseen : slbit; -- escape seen
rxdata : slv8; -- user rxdata
rxval : slbit; -- user rxval
rxovr : slbit; -- user rxovr
end record regs_type;
constant regs_init : regs_type := (
'1', -- txok (startup default is ok !!)
'0', -- escseen
(others=>'0'), -- rxdata
'0','0' -- rxval,rxovr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if ENAXON = '0' then
n.txok := '1';
end if;
if ENAESC = '0' then
n.escseen := '0';
end if;
n.rxovr := '0'; -- ensure single clock pulse
if UART_RXVAL = '1' then
if ENAXON='1' and UART_RXDATA=c_serport_xon then
n.txok := '1';
elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
n.txok := '0';
elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
n.escseen := '1';
else
if r.escseen = '1' then
n.escseen := '0';
end if;
if r.rxval = '0' then
n.rxval := '1';
if r.escseen = '1' then
n.rxdata := not UART_RXDATA;
else
n.rxdata := UART_RXDATA;
end if;
else
n.rxovr := '1';
end if;
end if;
end if;
if r.rxval='1' and RXHOLD='0' then
n.rxval := '0';
end if;
N_REGS <= n;
RXDATA <= r.rxdata;
RXVAL <= r.rxval;
RXOVR <= r.rxovr;
TXOK <= r.txok;
end process proc_next;
end sim;
| gpl-3.0 | c54330bbfee85212e03c56f29378b789 | 0.483476 | 3.862312 | false | false | false | false |
wfjm/w11 | rtl/vlib/comlib/cdata2byte.vhd | 1 | 4,419 | -- $Id: cdata2byte.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cdata2byte - syn
-- Description: 9 bit comma,data to Byte stream converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-10-12 596 2.0 re-write, commas now 2 byte sequences
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
entity cdata2byte is -- 9bit comma,data -> byte stream
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ESCXON : in slbit; -- enable xon/xoff escaping
ESCFILL : in slbit; -- enable fill escaping
DI : in slv9; -- input data; bit 8 = comma flag
ENA : in slbit; -- input data enable
BUSY : out slbit; -- input data busy
DO : out slv8; -- output data
VAL : out slbit; -- output data valid
HOLD : in slbit -- output data hold
);
end cdata2byte;
architecture syn of cdata2byte is
type regs_type is record
data : slv8; -- data
ecode : slv3; -- ecode
dataval : slbit; -- data valid
ecodeval : slbit; -- ecode valid
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- data
(others=>'0'), -- ecode
'0','0' -- dataval,ecodeval
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, DI, ENA, HOLD, ESCXON, ESCFILL)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idata : slv8 := (others=>'0');
variable iecode : slv3 := (others=>'0');
variable iesc : slbit := '0';
variable ibusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
-- data path logic
iesc := '0';
iecode := '0' & DI(1 downto 0);
if DI(8) = '1' then
iesc := '1';
else
case DI(7 downto 0) is
when c_cdata_xon =>
if ESCXON = '1' then
iesc := '1';
iecode := c_cdata_ec_xon;
end if;
when c_cdata_xoff =>
if ESCXON = '1' then
iesc := '1';
iecode := c_cdata_ec_xoff;
end if;
when c_cdata_fill =>
if ESCFILL = '1' then
iesc := '1';
iecode := c_cdata_ec_fill;
end if;
when c_cdata_escape =>
iesc := '1';
iecode := c_cdata_ec_esc;
when others => null;
end case;
end if;
if iesc = '0' then
idata := DI(7 downto 0);
else
idata := c_cdata_escape;
end if;
-- control path logic
ibusy := '1';
if HOLD = '0' then
n.dataval := '0';
if r.ecodeval = '1' then
n.data(c_cdata_edf_pref) := c_cdata_ed_pref;
n.data(c_cdata_edf_eci) := not r.ecode;
n.data(c_cdata_edf_ec ) := r.ecode;
n.dataval := '1';
n.ecodeval := '0';
else
ibusy := '0';
if ENA = '1' then
n.data := idata;
n.dataval := '1';
n.ecode := iecode;
n.ecodeval := iesc;
end if;
end if;
end if;
N_REGS <= n;
DO <= r.data;
VAL <= r.dataval;
BUSY <= ibusy;
end process proc_next;
end syn;
| gpl-3.0 | 4f862a115b0a1b09210dd0b1eccc01c3 | 0.473184 | 3.619165 | false | false | false | false |
wfjm/w11 | rtl/ibus/ib_sres_or_3.vhd | 1 | 2,163 | -- $Id: ib_sres_or_3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_3 - syn
-- Description: ibus: result or, 3 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_3 is -- ibus result or, 3 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_3;
architecture syn of ib_sres_or_3 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack or
IB_SRES_3.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy or
IB_SRES_3.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout or
IB_SRES_3.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => ib_sres_init
);
-- synthesis translate_on
end syn;
| gpl-3.0 | fafa2c427fa826f094224e7f65e9ef50 | 0.503467 | 3.121212 | false | false | false | false |
wfjm/w11 | rtl/bplib/s3board/tb/tb_s3board_core.vhd | 1 | 3,599 | -- $Id: tb_s3board_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board_core - sim
-- Description: Test bench for s3board - core device handling
--
-- Dependencies: simlib/simbididly
-- bplib/issi/is61lv25616al
--
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.1 use simbididly
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board_core is
port (
I_SWI : out slv8; -- s3 switches
I_BTN : out slv4; -- s3 buttons
O_MEM_CE_N : in slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : in slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- sram: write enable (act.low)
O_MEM_OE_N : in slbit; -- sram: output enable (act.low)
O_MEM_ADDR : in slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end tb_s3board_core;
architecture sim of tb_s3board_core is
signal MM_MEM_CE_N : slv2 := (others=>'1');
signal MM_MEM_BE_N : slv4 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADDR : slv18 := (others=>'Z');
signal MM_MEM_DATA : slv32 := (others=>'0');
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 32)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
MEM_L : entity work.is61lv25616al
port map (
CE_N => MM_MEM_CE_N(0),
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => MM_MEM_CE_N(1),
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(3),
LB_N => MM_MEM_BE_N(2),
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA(31 downto 16)
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
| gpl-3.0 | a8ef15735a34116af8fc48a135e4882b | 0.542651 | 2.849565 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/mem_ctl.vhd | 2 | 1,224 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity memory_control is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic;
mem_addr : out std_logic_vector(31 downto 0);
mem_write_data : out std_logic_vector(31 downto 0);
mem_read_data : in std_logic_vector(31 downto 0);
mem_we : out std_logic;
mem_clk : out std_logic
);
end memory_control;
architecture behavioral of memory_control is
signal addr_r, data_r : std_logic_vector(31 downto 0);
begin
--Not much to it, just here so it can be expanded later in need be
mem_clk <= clk;
mem_addr <= addr_r;
mem_write_data <= data_r;
data_out <= mem_read_data;
mem_we <= we;
latch : process (clk, rst) is
begin
if rst = '1' then
addr_r <= (others => '0');
data_r <= (others => '0');
elsif rising_edge(clk) then
addr_r <= address;
data_r <= data_in;
end if;
end process;
end behavioral;
| mit | 21e241a276fff26837208c7cca8236d0 | 0.620915 | 2.992665 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_dmcmon.vhd | 1 | 34,371 | -- $Id: pdp11_dmcmon.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmcmon- syn
-- Description: pdp11: debug&moni: cpu monitor
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- memlib/ram_1swar_1ar_gen
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-08-02 707 14.7 131013 xc6slx16-2 213 233 16 151 s 5.9
--
-- Revision History: -
-- Date Rev Version Comment
-- 2022-10-25 1309 2.0.2 rename _gpr -> _gr
-- 2019-06-02 1159 2.0.1 use rbaddr_ constants
-- 2017-04-22 884 2.0 use DM_STAT_SE.idle; revised interface, add suspend
-- 2015-08-03 709 1.0 Initial version
-- 2015-07-05 697 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/f Control register
-- 05 mwsup r/w/- mem wait suppress
-- 04 imode r/w/- instruction mode
-- 03 wstop r/w/- stop on wrap
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start and latch all options
-- 110 sus suspend (noop if not started)
-- 111 res resume (noop if not started)
-- 001 stat r/-/- Status register
-- 15:13 bsize r/-/- buffer size (AWIDTH-8)
-- 12:09 malcnt r/-/- valid entries in memory access log
-- 08 snum r/-/- snum support
-- 02 wrap r/-/- line address wrapped (cleared on start)
-- 01 susp r/-/- suspended
-- 00 run r/-/- running (can be suspended)
-- 010 addr r/w/- Address register (writable when stopped)
-- *:04 laddr r/w/- line address
-- 03:00 waddr r/w/- word address (0000 to 1000)
-- 011 data r/w/- Data register
-- 100 iaddr r/-/- Last instruction cmon address
-- *:04 laddr r/-/- line address
-- 03:00 r/-/- -always zero-
-- 101 ipc r/-/- Last instruction pc
-- 110 ireg r/-/- Last instruction
-- 111 imal r/-/- Last instruction memory access log
--
-- data format:
-- word 8 15 : vm.vmcntl.req
-- if req = 1
-- 14 : vm.vmcntl.wacc
-- 13 : vm.vmcntl.macc
-- 12 : vm.vmcntl.cacc
-- 11 : vm.vmcntl.bytop
-- 10 : vm.vmcntl.dspace
-- if req = 0
-- 14 : vm.vmcntl.ack
-- 13 : vm.vmcntl.err
-- if ack = 1 and err = 0
-- 12 : vm.vmcntl.trap_ysv
-- 11 : vm.vmcntl.trap_mmu
-- 10 : mwdrop (signals memwait suppress when mwsup=1)
-- if ack = 0 and err = 1
-- 12:10 : vm error code (priority encoded, but only one anyone)
-- 000 err_odd = 1
-- 001 err_mmu = 1
-- 010 err_nxm = 1
-- 011 err_iobto = 1
-- 100 err_rsv = 1
--
-- 09 : se.istart
-- 08 : se.idone
--
-- if imode = 0
-- 07:00 : se.snum
-- if imode = 1
-- 07:00 : cnum
--
-- word 7 15:01 : dp.pc (captured at se.istart)
-- 00 : idecode (is dp.ireg_we delayed by 1 cycle)
-- word 6 15:00 : dp.ireg
-- word 5 15:14 : dp.psw.cmode
-- 13:12 : dp.psw.pmode
-- 11 : dp.psw.rset
-- if imode = 0
-- 10 : dp.dres valid
-- 09 : dp.ddst_we
-- 08 : dp.dsrc_we
-- if imode = 1
-- 10 : -- unused --
-- 09 : -- unused --
-- 08 : se.vfetch
-- always
-- 07:05 : dp.psw.pri
-- 04 : dp.psw.tflag
-- 03:00 : dp.psw.cc
-- word 4 15:00 : dp.dsrc
-- word 3 15:00 : dp.ddst
-- word 2 15:00 : dp.dres (reged)
-- word 1 15:00 : vm.vmaddr (captured at vm.vmcntl.req)
-- word 0 15:00 : vm.vmdin or vm.vmdout (captured at req or ack)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
-- to control the instantiation. ghdl checks even for not instantiated
-- entities the validity of generics, that's why natural needed here ....
entity pdp11_dmcmon is -- debug&moni: cpu monitor
generic (
RB_ADDR : slv16 := rbaddr_dmcmon_off;
AWIDTH : natural := 8;
SNUM : boolean := false);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
);
end pdp11_dmcmon;
architecture syn of pdp11_dmcmon is
constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
constant rbaddr_stat : slv3 := "001"; -- stat address offset
constant rbaddr_addr : slv3 := "010"; -- addr address offset
constant rbaddr_data : slv3 := "011"; -- data address offset
constant rbaddr_iaddr : slv3 := "100"; -- iaddr address offset
constant rbaddr_ipc : slv3 := "101"; -- ipc address offset
constant rbaddr_ireg : slv3 := "110"; -- ireg address offset
constant rbaddr_imal : slv3 := "111"; -- imal address offset
constant cntl_rbf_mwsup : integer := 5;
constant cntl_rbf_imode : integer := 4;
constant cntl_rbf_wstop : integer := 3;
subtype cntl_rbf_func is integer range 2 downto 0;
subtype stat_rbf_bsize is integer range 15 downto 13;
subtype stat_rbf_malcnt is integer range 12 downto 9;
constant stat_rbf_snum : integer := 8;
constant stat_rbf_wrap : integer := 2;
constant stat_rbf_susp : integer := 1;
constant stat_rbf_run : integer := 0;
subtype addr_rbf_laddr is integer range 4+AWIDTH-1 downto 4;
subtype addr_rbf_waddr is integer range 3 downto 0;
subtype bram_mf_port11 is integer range 143 downto 108;
subtype bram_mf_port10 is integer range 107 downto 72;
subtype bram_mf_port01 is integer range 71 downto 36;
subtype bram_mf_port00 is integer range 35 downto 0;
subtype bram_df_word8 is integer range 143 downto 128;
subtype bram_df_word7 is integer range 127 downto 112;
subtype bram_df_word6 is integer range 111 downto 96;
subtype bram_df_word5 is integer range 95 downto 80;
subtype bram_df_word4 is integer range 79 downto 64;
subtype bram_df_word3 is integer range 63 downto 48;
subtype bram_df_word2 is integer range 47 downto 32;
subtype bram_df_word1 is integer range 31 downto 16;
subtype bram_df_word0 is integer range 15 downto 0;
constant dat8_rbf_req : integer := 15;
constant dat8_rbf_wacc : integer := 14; -- if req=1
constant dat8_rbf_macc : integer := 13; -- "
constant dat8_rbf_cacc : integer := 12; -- "
constant dat8_rbf_bytop : integer := 11; -- "
constant dat8_rbf_dspace : integer := 10; -- "
constant dat8_rbf_ack : integer := 14; -- if req=0
constant dat8_rbf_err : integer := 13; -- "
constant dat8_rbf_trap_ysv : integer := 12; -- if req=0 ack=1 err=0
constant dat8_rbf_trap_mmu : integer := 11; -- "
constant dat8_rbf_mwdrop : integer := 10; -- "
subtype dat8_rbf_vmerr is integer range 12 downto 10;-- if req=0 ack=0 err=1
constant dat8_rbf_istart : integer := 9; -- always
constant dat8_rbf_idone : integer := 8; -- "
constant vmerr_odd : slv3 := "001"; -- vm error code: err_odd
constant vmerr_mmu : slv3 := "010"; -- vm error code: err_mmu
constant vmerr_nxm : slv3 := "011"; -- vm error code: err_nxm
constant vmerr_iobto : slv3 := "100"; -- vm error code: err_iobto
constant vmerr_rsv : slv3 := "101"; -- vm error code: err_rsv
subtype dat8_rbf_snum is integer range 7 downto 0;
subtype dat8_rbf_cnum is integer range 7 downto 0;
subtype dat7_rbf_pc is integer range 15 downto 1;
constant dat7_rbf_idecode : integer := 0;
subtype dat5_rbf_cmode is integer range 15 downto 14;
subtype dat5_rbf_pmode is integer range 13 downto 12;
constant dat5_rbf_rset : integer := 11;
constant dat5_rbf_dres_val : integer := 10; -- if imode=0
constant dat5_rbf_ddst_we : integer := 9;
constant dat5_rbf_dsrc_we : integer := 8;
constant dat5_rbf_vfetch : integer := 8; -- if imode=1
subtype dat5_rbf_pri is integer range 7 downto 5;
constant dat5_rbf_tflag : integer := 4;
subtype dat5_rbf_cc is integer range 3 downto 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_sus : slv3 := "110"; -- func: suspend
constant func_res : slv3 := "111"; -- func: resume
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
type regs_type is record
rbsel : slbit; -- rbus select
mwsup : slbit; -- mwsup flag (mem wait suppress)
imode : slbit; -- imode flag
wstop : slbit; -- wstop flag (stop on wrap)
susp : slbit; -- suspended flag
go : slbit; -- go flag (actively running)
active : slbit; -- active flag
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv4; -- word address
cnum : slv8; -- clk counter
mal_waddr : slv4; -- mem acc log: write address
mal_raddr : slv4; -- mem acc log: read address
dp_pc_fet : slv16_1; -- dp.pc_fet (capture on se.istart)
dp_pc_dec : slv16_1; -- dp.pc_dec (capture on dp.ireg_we + 1)
dp_ireg : slv16; -- dp.ireg
dp_ireg_we : slbit; -- dp.ireg_we
dp_ireg_we_1 : slbit; -- dp.ireg_we last cycle
dp_dres : slv16; -- dp.dres
dp_dsrc_we : slbit; -- dp.dsrc_we
dp_ddst_we : slbit; -- dp.ddst_we
dp_dres_val : slbit; -- dp.dres valid
vm_addr : slv16; -- vm.vmaddr
vm_din : slv16; -- vm.vmdin
vm_dout : slv16; -- vm.vmdout
vm_req : slbit; -- vm.vmcntl.req
vm_wacc : slbit; -- vm.vmcntl.wacc
vm_macc : slbit; -- vm.vmcntl.macc
vm_cacc : slbit; -- vm.vmcntl.cacc
vm_bytop : slbit; -- vm.vmcntl.bytop
vm_dspace : slbit; -- vm.vmcntl.dspace
vm_addr_1 : slv16; -- vm.vmaddr last request
vm_dout_1 : slv16; -- vm.vmdout last request
vm_wacc_1 : slbit; -- vm.vmcntl.wacc last request
vm_macc_1 : slbit; -- vm.vmcntl.macc last request
vm_cacc_1 : slbit; -- vm.vmcntl.cacc last request
vm_bytop_1 : slbit; -- vm.vmcntl.bytop last request
vm_dspace_1 : slbit; -- vm.vmcntl.dspace last request
vm_ack : slbit; -- vm.vmstat.ack
vm_err : slbit; -- vm.vmstat.err
vm_err_odd : slbit; -- vm.vmstat.err_odd
vm_err_mmu : slbit; -- vm.vmstat.err_mmu
vm_err_nxm : slbit; -- vm.vmstat.err_nxm
vm_err_iobto : slbit; -- vm.vmstat.err_iobto
vm_err_rsv : slbit; -- vm.vmstat.err_rsv
vm_trap_ysv : slbit; -- vm.vmstat.trap_ysv
vm_trap_mmu : slbit; -- vm.vmstat.trap_mmu
vm_pend : slbit; -- vm req pending
se_idle : slbit; -- se.idle
se_istart : slbit; -- se.istart
se_istart_1 : slbit; -- se.istart last cycle
se_idone : slbit; -- se.idone
se_vfetch : slbit; -- se.vfetch
se_snum : slv8; -- se.snum
mwdrop : slbit; -- mem wait drop flag
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
'0','1','0', -- mwsup,imode,wstop
'0','1','0', -- susp,go,active
'0', -- wrap
laddrzero, -- laddr
"0000", -- waddr
(others=>'0'), -- cnum
(others=>'0'), -- macwaddr
(others=>'0'), -- macraddr
(others=>'0'), -- dp_pc_fet
(others=>'0'), -- dp_pc_dec
(others=>'0'), -- dp_ireq
'0','0', -- dp_ireq_we,dp_ireq_we_1
(others=>'0'), -- dp_dres
'0','0','0', -- dp_dsrc_we,dp_ddst_we,dp_dres_val
(others=>'0'), -- vm_addr
(others=>'0'), -- vm_din
(others=>'0'), -- vm_dout
'0','0','0','0','0','0', -- vm_req,..,vm_dspace
(others=>'0'), -- vm_addr_1
(others=>'0'), -- vm_dout_1
'0','0','0','0','0', -- vm_wacc_1,..,vm_dspace_1
'0','0', -- vm_ack,vm_err
'0','0','0','0','0', -- vm_err_*
'0','0', -- vm_trap_*
'0', -- vm_pend
'0','0','0', -- se_idle,se_istart(_1)
'0','0', -- se_idone,se_vfetch
(others=>'0'), -- se_snum
'0' -- mwdrop
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM_ADDRA : slv(AWIDTH downto 0) := (others=>'0');
signal BRAM_ADDRB : slv(AWIDTH downto 0) := (others=>'0');
signal BRAM_DI : slv(143 downto 0) := (others=>'0');
signal BRAM_DO : slv(143 downto 0) := (others=>'0');
signal MAL_WE : slbit := '0';
signal MAL_DI : slv16 := (others=>'0');
signal MAL_DO : slv16 := (others=>'0');
begin
assert AWIDTH>=8 and AWIDTH<=11
report "assert(AWIDTH>=8 and AWIDTH<=11): unsupported AWIDTH"
severity failure;
BRAM0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH+1,
DWIDTH => 36)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => BRAM_EN,
ENB => BRAM_EN,
WEA => BRAM_WE,
WEB => BRAM_WE,
ADDRA => BRAM_ADDRA,
ADDRB => BRAM_ADDRB,
DIA => BRAM_DI(bram_mf_port00),
DIB => BRAM_DI(bram_mf_port01),
DOA => BRAM_DO(bram_mf_port00),
DOB => BRAM_DO(bram_mf_port01)
);
BRAM1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH+1,
DWIDTH => 36)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => BRAM_EN,
ENB => BRAM_EN,
WEA => BRAM_WE,
WEB => BRAM_WE,
ADDRA => BRAM_ADDRA,
ADDRB => BRAM_ADDRB,
DIA => BRAM_DI(bram_mf_port10),
DIB => BRAM_DI(bram_mf_port11),
DOA => BRAM_DO(bram_mf_port10),
DOB => BRAM_DO(bram_mf_port11)
);
MAL : ram_1swar_1ar_gen
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
WE => MAL_WE,
ADDRA => R_REGS.mal_waddr,
ADDRB => R_REGS.mal_raddr,
DI => MAL_DI,
DOA => open,
DOB => MAL_DO);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE,
DM_STAT_DP, DM_STAT_DP.psw, -- xst needs sub-records
DM_STAT_VM, DM_STAT_VM.vmcntl, DM_STAT_VM.vmstat,
DM_STAT_CO, BRAM_DO, MAL_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_err : slbit := '0'; -- FIXME: needed ??
variable irb_busy : slbit := '0'; -- FIXME: needed ??
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ibramen : slbit := '0'; -- BRAM enable
variable ibramwe : slbit := '0'; -- BRAN we
variable igoeff : slbit := '0';
variable iactive : slbit := '0';
variable itake : slbit := '0';
variable laddr_inc : slbit := '0';
variable idat : slv(143 downto 0) := (others=>'0');
variable idat8 : slv16 := (others=>'0');
variable idat7 : slv16 := (others=>'0');
variable idat5 : slv16 := (others=>'0');
variable ivmerr : slv3 := (others=>'0');
variable imal_we : slbit := '0';
variable imal_re : slbit := '0';
variable imal_di : slv16 := (others=>'0');
variable imal_waddr_clr : slbit := '0';
variable imal_raddr_clr : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_err := '0';
irb_busy := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ibramen := '0';
ibramwe := '0';
igoeff := '0';
iactive := '0';
itake := '0';
laddr_inc := '0';
imal_we := '0';
imal_re := '0';
imal_di := r.vm_addr;
imal_waddr_clr := '0';
imal_raddr_clr := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(12 downto 3)=RB_ADDR(12 downto 3) then
n.rbsel := '1';
ibramen := '1'; -- ensure bram read before rbus read
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
case RB_MREQ.din(cntl_rbf_func) is
when func_sto => -- func: stop ------------
n.go := '0';
n.susp := '0';
when func_sta => -- func: start -----------
n.mwsup := RB_MREQ.din(cntl_rbf_mwsup);
n.imode := RB_MREQ.din(cntl_rbf_imode);
n.wstop := RB_MREQ.din(cntl_rbf_wstop);
n.go := '1';
n.susp := '0';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "0000";
when func_sus => -- func: susp ------------
if r.go = '1' then -- noop unless running
n.go := '0';
n.susp := r.go;
end if;
when func_res => -- func: resu ------------
n.go := r.susp;
n.susp := '0';
when others => null; -- <> --------------------
end case;
end if;
when rbaddr_stat => -- stat ------------------
irb_err := RB_MREQ.we;
when rbaddr_addr => -- addr ------------------
if RB_MREQ.we = '1' then
if r.go = '0' then -- if not active OK
n.laddr := RB_MREQ.din(addr_rbf_laddr);
n.waddr := RB_MREQ.din(addr_rbf_waddr);
else
irb_err := '1'; -- otherwise error
end if;
end if;
when rbaddr_data => -- data ------------------
-- write to data is an error
if RB_MREQ.we='1' then
irb_err := '1'; -- error
end if;
-- read to data always allowed, addr only incremented when not active
if RB_MREQ.re = '1' and r.go = '0' then
if r.waddr(3) = '1' then -- equivalent waddr>=1000
n.waddr := (others=>'0');
laddr_inc := '1';
else
n.waddr := slv(unsigned(r.waddr) + 1);
end if;
end if;
when rbaddr_iaddr => -- iaddr -----------------
irb_err := RB_MREQ.we;
when rbaddr_ipc => -- ipc -------------------
irb_err := RB_MREQ.we;
when rbaddr_ireg => -- ireg ------------------
irb_err := RB_MREQ.we;
when rbaddr_imal => -- imal ------------------
irb_err := RB_MREQ.we;
imal_re := RB_MREQ.re;
when others => null; -- <> --------------------
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
irb_dout(cntl_rbf_mwsup) := r.mwsup;
irb_dout(cntl_rbf_imode) := r.imode;
irb_dout(cntl_rbf_wstop) := r.wstop;
when rbaddr_stat => -- stat ------------------
irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-8,3));
irb_dout(stat_rbf_malcnt) := r.mal_waddr;
if SNUM then
irb_dout(stat_rbf_snum) := '1';
end if;
irb_dout(stat_rbf_wrap) := r.wrap;
irb_dout(stat_rbf_susp) := r.susp; -- started and suspended
irb_dout(stat_rbf_run) := r.go or r.susp; -- started
when rbaddr_addr => -- addr ------------------
irb_dout(addr_rbf_laddr) := r.laddr;
irb_dout(addr_rbf_waddr) := r.waddr;
when rbaddr_data => -- data ------------------
case r.waddr is
when "1000" => irb_dout := BRAM_DO(bram_df_word8);
when "0111" => irb_dout := BRAM_DO(bram_df_word7);
when "0110" => irb_dout := BRAM_DO(bram_df_word6);
when "0101" => irb_dout := BRAM_DO(bram_df_word5);
when "0100" => irb_dout := BRAM_DO(bram_df_word4);
when "0011" => irb_dout := BRAM_DO(bram_df_word3);
when "0010" => irb_dout := BRAM_DO(bram_df_word2);
when "0001" => irb_dout := BRAM_DO(bram_df_word1);
when "0000" => irb_dout := BRAM_DO(bram_df_word0);
when others => irb_dout := (others=>'0');
end case;
when rbaddr_iaddr => -- iaddr -----------------
null; -- FIXME_code: implement
when rbaddr_ipc => -- ipc -------------------
irb_dout(r.dp_pc_dec'range) := r.dp_pc_dec;
n.mal_raddr := (others=>'0');
when rbaddr_ireg => -- ireg ------------------
irb_dout := r.dp_ireg;
when rbaddr_imal => -- imal ------------------
irb_dout := MAL_DO;
when others => null;
end case;
end if;
-- cpu monitor
-- capture CPU state signals which are combinatorial logic
if DM_STAT_SE.istart = '1' then
n.dp_pc_fet := DM_STAT_DP.pc(15 downto 1);
end if;
n.dp_ireg := DM_STAT_DP.ireg;
n.dp_ireg_we := DM_STAT_DP.ireg_we;
n.dp_ireg_we_1 := r.dp_ireg_we;
if r.dp_ireg_we = '1' then -- dp_pc_dec update when dp_ireg changes
n.dp_pc_dec := r.dp_pc_fet;
end if;
n.dp_dsrc_we := DM_STAT_DP.dsrc_we;
n.dp_ddst_we := DM_STAT_DP.ddst_we;
n.dp_dres_val := '0';
if ((DM_STAT_DP.gr_we or DM_STAT_DP.psr_we or -- capture dres only when
DM_STAT_DP.dsrc_we or DM_STAT_DP.ddst_we or -- actually used
DM_STAT_DP.dtmp_we or DM_STAT_DP.cpdout_we or
DM_STAT_VM.vmcntl.req) = '1') then
n.dp_dres := DM_STAT_DP.dres;
n.dp_dres_val := '1';
end if;
n.vm_req := DM_STAT_VM.vmcntl.req;
-- capture vm request data when vm_req asserted, need them in later cycles
-- don't update vmaddr for write part of rmw sequence
-- no valid address vmaddr given, address is kept in vmbox
if DM_STAT_VM.vmcntl.req = '1' then
n.vm_wacc_1 := r.vm_wacc;
n.vm_macc_1 := r.vm_macc;
n.vm_cacc_1 := r.vm_cacc;
n.vm_bytop_1 := r.vm_bytop;
n.vm_dspace_1 := r.vm_dspace;
n.vm_wacc := DM_STAT_VM.vmcntl.wacc;
n.vm_macc := DM_STAT_VM.vmcntl.macc;
n.vm_cacc := DM_STAT_VM.vmcntl.cacc;
n.vm_bytop := DM_STAT_VM.vmcntl.bytop;
n.vm_dspace := DM_STAT_VM.vmcntl.dspace;
if (DM_STAT_VM.vmcntl.macc and DM_STAT_VM.vmcntl.wacc) = '0' then
n.vm_addr_1 := r.vm_addr;
n.vm_addr := DM_STAT_VM.vmaddr;
end if;
n.vm_din := DM_STAT_VM.vmdin;
end if;
n.vm_ack := DM_STAT_VM.vmstat.ack;
n.vm_err := DM_STAT_VM.vmstat.err;
if DM_STAT_VM.vmstat.ack = '1' then
n.vm_dout_1 := r.vm_dout;
n.vm_dout := DM_STAT_VM.vmdout;
n.vm_trap_ysv := DM_STAT_VM.vmstat.trap_ysv;
n.vm_trap_mmu := DM_STAT_VM.vmstat.trap_mmu;
end if;
if DM_STAT_VM.vmstat.err = '1' then
n.vm_err_odd := DM_STAT_VM.vmstat.err_odd;
n.vm_err_mmu := DM_STAT_VM.vmstat.err_mmu;
n.vm_err_nxm := DM_STAT_VM.vmstat.err_nxm;
n.vm_err_iobto := DM_STAT_VM.vmstat.err_iobto;
n.vm_err_rsv := DM_STAT_VM.vmstat.err_rsv;
end if;
n.se_istart_1 := r.se_istart;
n.se_idle := DM_STAT_SE.idle;
n.se_istart := DM_STAT_SE.istart;
n.se_idone := DM_STAT_SE.idone;
n.se_vfetch := DM_STAT_SE.vfetch;
n.se_snum := DM_STAT_SE.snum;
-- active state logic
igoeff := '0';
if r.go = '1' then
if DM_STAT_CO.cpugo='1' and DM_STAT_CO.cpususp='0' then
igoeff := '1';
end if;
if DM_STAT_CO.cpustep = '1' then
igoeff := '1';
end if;
end if;
iactive := r.active;
if r.se_idle = '1' then -- in idle state
if igoeff = '0' then -- if goeff=0 stop running
n.active := '0';
end if;
else -- in non-idle state
if igoeff = '1' then -- if goerr=1 start running
iactive := '1';
n.active := '1';
end if;
end if;
if r.vm_req = '1' then
n.mwdrop := '0';
n.vm_pend := '1';
elsif (r.vm_ack or r.vm_err) = '1' then
n.vm_pend := '0';
end if;
itake := '0';
if r.imode = '0' then -- imode=0
itake := '1'; -- take all
if r.mwsup = '1' then -- if mem wait suppress
if (r.vm_pend and not (r.vm_ack or r.vm_err)) = '1' then
itake := '0';
n.mwdrop := '1';
end if;
end if;
else -- imode=1
itake := r.se_idone or r.se_vfetch or r.vm_err;
end if;
if iactive='1' and itake='1' then -- active and enabled
ibramen := '1';
ibramwe := '1';
laddr_inc := '1';
end if;
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + 1);
if r.go='1' and r.laddr=laddrlast then
n.wrap := '1';
if r.wstop = '1' then
n.go := '0';
end if;
end if;
end if;
-- last but not least: the clock cycle counter
n.cnum := slv(unsigned(r.cnum) + 1);
-- now build memory data word
idat := (others=>'0');
-- encode vm errors
ivmerr := (others=>'0');
if r.vm_err_odd = '1' then
ivmerr := vmerr_odd;
elsif r.vm_err_mmu = '1' then
ivmerr := vmerr_mmu;
elsif r.vm_err_nxm = '1' then
ivmerr := vmerr_nxm;
elsif r.vm_err_iobto = '1' then
ivmerr := vmerr_iobto;
elsif r.vm_err_rsv = '1' then
ivmerr := vmerr_rsv;
end if;
-- Note for imode=1
-- Write vm request data unless there is an error.
-- If in current or last cycle a ifetch (istart=1) was done use
-- attributes of previous request. If last cycle was an ifetch
-- and vm_ack set use also previous data. That ensures that the
-- values of current instruction are shown, and not of pre-fetch
-- build word8
idat8 := (others=>'0');
if r.vm_req = '1' or (r.imode='1' and r.vm_err='0') then
idat8(dat8_rbf_req) := '1';
if r.imode = '1' and (r.se_istart='1' or r.se_istart_1='1') then
idat8(dat8_rbf_wacc) := R_REGS.vm_wacc_1;
idat8(dat8_rbf_macc) := R_REGS.vm_macc_1;
idat8(dat8_rbf_cacc) := R_REGS.vm_cacc_1;
idat8(dat8_rbf_bytop) := R_REGS.vm_bytop_1;
idat8(dat8_rbf_dspace) := R_REGS.vm_dspace_1;
else
idat8(dat8_rbf_wacc) := R_REGS.vm_wacc;
idat8(dat8_rbf_macc) := R_REGS.vm_macc;
idat8(dat8_rbf_cacc) := R_REGS.vm_cacc;
idat8(dat8_rbf_bytop) := R_REGS.vm_bytop;
idat8(dat8_rbf_dspace) := R_REGS.vm_dspace;
end if;
else
idat8(dat8_rbf_ack) := R_REGS.vm_ack;
idat8(dat8_rbf_err) := R_REGS.vm_err;
if r.vm_ack = '1' then
idat8(dat8_rbf_trap_ysv) := R_REGS.vm_trap_ysv;
idat8(dat8_rbf_trap_mmu) := R_REGS.vm_trap_mmu;
idat8(dat8_rbf_mwdrop) := R_REGS.mwdrop;
elsif r.vm_err = '1' then
idat8(dat8_rbf_vmerr) := ivmerr;
end if;
end if;
idat8(dat8_rbf_istart) := R_REGS.se_istart;
idat8(dat8_rbf_idone) := R_REGS.se_idone;
if r.imode = '0' then
idat8(dat8_rbf_snum) := R_REGS.se_snum;
else
idat8(dat8_rbf_cnum) := R_REGS.cnum;
end if;
idat(bram_df_word8) := idat8;
-- build word7
idat7 := (others=>'0');
idat7(dat7_rbf_pc) := R_REGS.dp_pc_dec;
idat7(dat7_rbf_idecode):= R_REGS.dp_ireg_we_1;
idat(bram_df_word7) := idat7;
-- build word6
idat(bram_df_word6) := R_REGS.dp_ireg;
-- build word5
idat5 := (others=>'0');
idat5(dat5_rbf_cmode) := DM_STAT_DP.psw.cmode;
idat5(dat5_rbf_pmode) := DM_STAT_DP.psw.pmode;
idat5(dat5_rbf_rset) := DM_STAT_DP.psw.rset;
if r.imode = '0' then
idat5(dat5_rbf_dres_val) := R_REGS.dp_dres_val;
idat5(dat5_rbf_ddst_we) := R_REGS.dp_ddst_we;
idat5(dat5_rbf_dsrc_we) := R_REGS.dp_dsrc_we;
else
idat5(dat5_rbf_vfetch) := R_REGS.se_vfetch;
end if;
idat5(dat5_rbf_pri) := DM_STAT_DP.psw.pri;
idat5(dat5_rbf_tflag) := DM_STAT_DP.psw.tflag;
idat5(dat5_rbf_cc) := DM_STAT_DP.psw.cc;
idat(bram_df_word5) := idat5;
-- build word4 to word2
idat(bram_df_word4) := DM_STAT_DP.dsrc;
idat(bram_df_word3) := DM_STAT_DP.ddst;
idat(bram_df_word2) := R_REGS.dp_dres;
-- build word1
if r.imode = '1' and (r.se_istart='1' or r.se_istart_1='1') then
idat(bram_df_word1) := R_REGS.vm_addr_1;
else
idat(bram_df_word1) := R_REGS.vm_addr;
end if;
-- build word0
if r.vm_wacc = '1' then
idat(bram_df_word0) := R_REGS.vm_din;
else
if r.imode = '1' and r.se_istart_1 = '1' and r.vm_ack = '1' then
idat(bram_df_word0) := R_REGS.vm_dout_1;
else
idat(bram_df_word0) := R_REGS.vm_dout;
end if;
end if;
-- finally memory access log buffer logic
if r.vm_cacc = '0' then
if r.vm_req = '1' then
imal_we := '1';
imal_di := r.vm_addr;
elsif r.vm_ack='1' then
imal_we := '1';
if r.vm_wacc='1' then
imal_di := r.vm_din;
else
imal_di := r.vm_dout;
end if;
if r.vm_bytop = '1' then -- for byte read/write data
imal_di(15 downto 8) := (others=>'0'); -- zero msb (is undefined)
end if;
end if;
end if;
imal_waddr_clr := r.dp_ireg_we; -- FIXME: very preliminary !!!
if imal_waddr_clr = '1' then
n.mal_waddr := (others=>'0');
elsif imal_we = '1' then
n.mal_waddr := slv(unsigned(r.mal_waddr) + 1);
end if;
if imal_raddr_clr = '1' then
n.mal_raddr := (others=>'0');
elsif imal_re = '1' then
n.mal_raddr := slv(unsigned(r.mal_raddr) + 1);
end if;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_ADDRA <= '0' & R_REGS.laddr;
BRAM_ADDRB <= '1' & R_REGS.laddr;
BRAM_DI <= idat;
MAL_WE <= imal_we;
MAL_DI <= imal_di;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 | 63e760c70a54d342f4625bfdb3057ea9 | 0.478165 | 3.311591 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | memInst.vhd | 1 | 7,118 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: memInst.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY memInst IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END memInst;
ARCHITECTURE SYN OF meminst IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "memInst.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 10,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "memInst.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "memInst.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL memInst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memInst.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memInst.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memInst.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL memInst_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| mit | 78d9854c78d380178cb0f51dcc535174 | 0.655662 | 3.487506 | false | false | false | false |
wfjm/w11 | rtl/bplib/cmoda7/tb/sys_conf_sim.vhd | 1 | 1,705 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_cmoda7_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.4; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 9; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 60; -- vco 720 MHz
constant sys_conf_clkser_outdivide : positive := 6; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 7ff927c6c120d66e588a0a65e1d11adc | 0.616422 | 3.62766 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd | 1 | 7,826 | -- $Id: tb_nexys3_fusp.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/s6_cmt_sfs
-- rlink/tbcore/tbcore_rlink
-- tb_nexys3_core
-- serport/tb/serport_master_tb
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys3_fusp is
end tb_nexys3_fusp;
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back pressure for data flow to tb
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys3_fusp_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | a57175866d7e481dc466f50c6e54a821 | 0.522872 | 3.077468 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vhd | 1 | 7,766 | -- $Id: sys_tst_rlink_c7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_c7 - syn
-- Description: rlink tester design for CmodA7 board
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- bplib/bpgen/rgbdrv_master
-- bplib/bpgen/rgbdrv_analog_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
-- vlib/xlib/iob_reg_o_gen
--
-- Test bench: tb/tb_tst_rlink_c7
--
-- Target Devices: generic
-- Tool versions: viv 2016.4-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1 913 1402 34 3.0 494
-- 2019-02-02 1108 2018.3 xc7a35t-1 913 1494 36 3.0 496
-- 2019-02-02 1108 2017.2 xc7a35t-1 914 1581 36 3.0 510
-- 2017-06-05 907 2016.4 xc7a35t-1 913 1556 36 3.0 513
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version (derived from sys_tst_rlink_arty)
------------------------------------------------------------------------------
-- Usage of CmodA7 Buttons, LEDs, RGBLEDs:
--
-- LED(1): SER_MONI.txact (shows tx activity)
-- LED(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_c7 is -- top level
-- implements cmoda7_aif
port (
I_CLK12 : in slbit; -- 12 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3 -- c7 rgb-led 0
);
end sys_tst_rlink_c7;
architecture syn of sys_tst_rlink_c7 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal LED : slv2 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RGBCNTL : slv3 := (others=>'0');
signal DIMCNTL : slv12 := (others=>'0');
constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"09"; -- cmoda7
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 83.3,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK12,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RGBMSTR : rgbdrv_master
generic map (
DWIDTH => DIMCNTL'length)
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL
);
RGB0 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
ACTLOW => '1', -- CmodA7 has active low RGBLED
RB_ADDR => rbaddr_rgb0)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB0,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED0_N
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR1 : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_RGB0,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
IOB_LED : iob_reg_o_gen
generic map (DWIDTH => O_LED'length)
port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
LED(1) <= SER_MONI.txact;
LED(0) <= SER_MONI.rxact;
end syn;
| gpl-3.0 | 69e5a097c43929956c6c4fc1b2c28b52 | 0.501803 | 3.282333 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32im_nodiv/alu.vhd | 1 | 2,659 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( clock: in std_logic;
reset: in std_logic;
op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logic;
alu_wait: out std_logic
);
end alu;
architecture arch_alu of alu is
signal r, shift, mul_lo, mul_hi: std_logic_vector(31 downto 0);
signal shift_op2: std_logic_vector(4 downto 0);
signal addsub: std_logic_vector(32 downto 0);
signal less, left, logical, mul_trg, mul_sig0, mul_sig1, mul_rdy, mul_rdy2, mul_hold: std_logic;
begin
process(op1, op2, alu_op, addsub, less, shift_op2, shift, mul_lo, mul_hi)
begin
case alu_op is
when "0000" => r <= op1 and op2;
when "0001" => r <= op1 or op2;
when "0010" => r <= op1 xor op2;
when "0100" | "0101" => r <= addsub(31 downto 0);
when "0110" => r <= op2;
when "0111" | "1000" => r <= x"0000000" & "000" & less;
when "1001" | "1010" | "1011" => r <= shift;
when "1100" => r <= mul_lo;
when others => r <= mul_hi;
end case;
end process;
result <= r;
addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2);
less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31);
less_than <= less;
zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or
r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or
r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or
r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0));
shift_op2 <= op2(4 downto 0);
left <= '1' when alu_op(1) = '0' else '0';
logical <= '1' when alu_op(1 downto 0) /= "11" else '0';
barrel_shifter: entity work.bshift
port map( left => left,
logical => logical,
shift => shift_op2,
input => op1,
output => shift
);
mul_trg <= '1' when alu_op >= "1100" and mul_rdy = '1' and mul_rdy2 = '1' else '0';
mul_sig0 <= '1' when alu_op(1) = '0' else '0';
mul_sig1 <= '1' when alu_op(1 downto 0) = "10" else '0';
alu_wait <= mul_trg or mul_hold or not mul_rdy;
process(clock, reset)
begin
if reset = '1' then
mul_hold <= '0';
mul_rdy2 <= '0';
elsif clock'event and clock = '1' then
mul_hold <= mul_trg;
mul_rdy2 <= mul_rdy;
end if;
end process;
multiplier: entity work.mul
port map( clock => clock,
reset => reset,
trg => mul_trg,
sig0 => mul_sig0,
sig1 => mul_sig1,
i0 => op1,
i1 => op2,
o0 => mul_lo,
o1 => mul_hi,
rdy => mul_rdy
);
end arch_alu;
| gpl-2.0 | 3e512541e9a548bdf6d93261a035c988 | 0.583302 | 2.324301 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4d/tb/nexys4d_dummy.vhd | 1 | 2,162 | -- $Id: nexys4d_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys4d_dummy - syn
-- Description: nexys4d minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys4d
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version (derived from nexys4_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nexys4d_dummy is -- NEXYS 4DDR dummy (base; loopback)
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end nexys4d_dummy;
architecture syn of nexys4d_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
| gpl-3.0 | 123cde60c1d5eee436d4e350b1df75b6 | 0.486124 | 3.475884 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.vhd | 1 | 6,825 | -- $Id: sys_tst_serloop_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop_s3 - syn
-- Description: Tester serial link for s3board
--
-- Dependencies: vlib/xlib/dcm_sfs
-- genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- s3board/s3_sram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-16 426 13.1 O40d xc3s1000-4 424 602 64 476 t 13.6
-- 2011-11-13 425 13.1 O40d xc3s1000-4 421 586 64 466 t 13.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.2 rename serport stat->moni port
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-12 423 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop_s3 is -- top level
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop_s3;
architecture syn of sys_tst_serloop_s3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 60 sim: 12
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
| gpl-3.0 | 021029f0572491f8f9e1508155a6ffd0 | 0.478974 | 3.233065 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/fifo_1c_dram_raw.vhd | 1 | 4,152 | -- $Id: fifo_1c_dram_raw.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_1c_dram_raw - syn
-- Description: FIFO, single clock domain, distributed RAM based, 'raw'
-- interface exposing dram signals.
--
-- Dependencies: ram_1swar_1ar_gen
--
-- Test bench: tb/tb_fifo_1c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-03 47 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
WE : in slbit; -- write enable
RE : in slbit; -- read enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
EMPTY : out slbit; -- empty flag
FULL : out slbit -- full flag
);
end fifo_1c_dram_raw;
architecture syn of fifo_1c_dram_raw is
type regs_type is record
waddr : slv(AWIDTH-1 downto 0); -- write address
raddr : slv(AWIDTH-1 downto 0); -- read address
empty : slbit; -- empty flag
full : slbit; -- full flag
end record regs_type;
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RAM_WE : slbit := '0';
begin
RAM : ram_1swar_1ar_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
WE => RAM_WE,
ADDRA => R_REGS.waddr,
ADDRB => R_REGS.raddr,
DI => DI,
DOA => open,
DOB => DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, WE, RE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
variable we_val : slbit := '0';
variable re_val : slbit := '0';
variable iram_we : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
re_val := RE and not r.empty;
we_val := WE and ((not r.full) or RE);
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
iram_we := '0';
if RESET = '1' then
n := regs_init;
else
if we_val = '1' then
n.waddr := slv(unsigned(r.waddr) + 1);
iram_we := '1';
if re_val = '0' then
n.empty := '0';
if unsigned(isize) = memsize-1 then
n.full := '1';
end if;
end if;
end if;
if re_val = '1' then
n.raddr := slv(unsigned(r.raddr) + 1);
if we_val = '0' then
n.full := '0';
if unsigned(isize) = 1 then
n.empty := '1';
end if;
end if;
end if;
end if;
N_REGS <= n;
RAM_WE <= iram_we;
SIZE <= isize;
EMPTY <= r.empty;
FULL <= r.full;
end process proc_next;
end syn;
| gpl-3.0 | 2292b7a32f7daefe114072c3384ede94 | 0.506744 | 3.477387 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01300_bad.vhd | 1 | 3,292 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01300_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of constant name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01300_good is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end CNE_01300_good;
architecture Behavioral of CNE_01300_good is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
constant Length : unsigned(3 downto 0) := "1001"; -- Counter period
begin
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count>=Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable='1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral; | gpl-3.0 | 542eeb0600a12d196baee354891be1a0 | 0.496962 | 4.656294 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/rlink_sp2c.vhd | 1 | 5,918 | -- $Id: rlink_sp2c.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp2c - syn
-- Description: rlink_core8 + serport_2clock2 combo
--
-- Dependencies: rlink_core8
-- serport/serport_2clock2
-- rbus/rbd_rbmon
-- rbus/rb_sres_or_2
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2016-03-28 755 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity rlink_sp2c is -- rlink_core8+serport_2clock2 combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- U|clock (user design)
CE_USEC : in slbit; -- U|1 usec clock enable
CE_MSEC : in slbit; -- U|1 msec clock enable
CE_INT : in slbit := '0'; -- U|rri ato time unit clock enable
RESET : in slbit; -- U|reset
CLKS : in slbit; -- S|clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ESCFILL : in slbit; -- U|enable fill escaping
RXSD : in slbit; -- S|receive serial data (board view)
TXSD : out slbit; -- S|transmit serial data (board view)
CTS_N : in slbit := '0'; -- S|clear to send (act.low, board view)
RTS_N : out slbit; -- S|request to send (act.low, brd view)
RB_MREQ : out rb_mreq_type; -- U|rbus: request
RB_SRES : in rb_sres_type; -- U|rbus: response
RB_LAM : in slv16; -- U|rbus: look at me
RB_STAT : in slv4; -- U|rbus: status flags
RL_MONI : out rl_moni_type; -- U|rlink_core: monitor port
SER_MONI : out serport_moni_type -- U|serport: monitor port
);
end entity rlink_sp2c;
architecture syn of rlink_sp2c is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
signal RB_SRES_M : rb_sres_type := rb_sres_init;
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
begin
CORE : rlink_core8 -- rlink master ----------------------
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
SYSID => SYSID,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RLBMON=> ENAPIN_RLBMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
ESCXON => ENAXON,
ESCFILL => ESCFILL,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_M,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_2clock2 -- serport interface -----------------
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => ENAXON,
ENAESC => '0', -- escaping now in rlink_core8
RXDATA => RLB_DI,
RXVAL => RLB_ENA,
RXHOLD => RLB_BUSY,
TXDATA => RLB_DO,
TXENA => RLB_VAL,
TXBUSY => RLB_HOLD,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
begin
I0 : rbd_rbmon
generic map (
RB_ADDR => RBMON_RBADDR,
AWIDTH => RBMON_AWIDTH)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_RBMON,
RB_SRES_SUM => RB_SRES_M
);
end generate RBMON;
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES,
RB_SRES_2 => RB_SRES_RBMON,
RB_SRES_OR => RB_SRES_M
);
RB_MREQ <= RB_MREQ_M; -- setup output signals
end syn;
| gpl-3.0 | 7e8980ea32624d4fb1eba5e8af153ec6 | 0.497465 | 3.599757 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_uart_rx.vhd | 1 | 11,141 | -- $Id: serport_uart_rx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
-- The uart expects CLKDIV+1 wide input bit symbols.
-- This implementation counts the number of 1's in the first CLKDIV clock
-- cycles, and checks in the last cycle of the symbol time whether the
-- number of 1's was > CLKDIV/2. This supresses short glitches nicely,
-- especially for larger clock dividers.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rx - syn
-- Description: serial port UART - receiver
--
-- Dependencies: -
-- Test bench: tb/tb_serport_uart_rxtx
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 2.0.4 don't init N_REGS (vivado fix for fsm inference)
-- 2011-10-22 417 2.0.3 now numeric_std clean
-- 2009-07-12 233 2.0.2 remove snoopers
-- 2008-03-02 121 2.0.1 comment out snoopers
-- 2007-10-21 91 2.0 re-designed and -implemented with state machine.
-- allow CLKDIV=0 with 1 stop bit; allow max. CLKDIV
-- (all 1's); aborts bad start bit after 1/2 cell;
-- accepts stop bit after 1/2 cell, permits tx clock
-- be ~3 percent faster than rx clock.
-- for 3s1000ft256: 50 -> 58 slices for CDWIDTH=13
-- 2007-10-14 89 1.1 almost full rewrite, handles now CLKDIV=0 properly
-- for 3s1000ft256: 43 -> 50 slices for CDWIDTH=13
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_rx is -- serial port uart: receive part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end serport_uart_rx;
architecture syn of serport_uart_rx is
type state_type is (
s_idle, -- s_idle: idle
s_colb0, -- s_colb0: collect b0 (start bit)
s_endb0, -- s_endb0: finish b0 (start bit)
s_colbx, -- s_colbx: collect bx
s_endbx, -- s_endbx: finish bx
s_colb9, -- s_colb9: collect bx (stop bit)
s_endb9 -- s_endb9: finish bx (stop bit)
);
type regs_type is record
state : state_type; -- state
ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv(CDWIDTH downto 0); -- data '1' counter
bcnt : slv4; -- bit counter
sreg : slv8; -- input shift register
end record regs_type;
constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
ccntzero, -- ccnt
dcntzero, -- dcnt
(others=>'0'), -- bcnt
(others=>'0') -- sreg
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CLKDIV, RXSD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable dbit : slbit := '0';
variable ld_ccnt : slbit := '0';
variable tc_ccnt : slbit := '0';
variable tc_bcnt : slbit := '0';
variable ld_dcnt : slbit := '0';
variable ld_bcnt : slbit := '0';
variable ce_bcnt : slbit := '0';
variable iact : slbit := '0';
variable ival : slbit := '0';
variable ierr : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
dbit := '0';
ld_ccnt := '0';
tc_ccnt := '0';
tc_bcnt := '0';
ld_dcnt := '0';
ld_bcnt := '0';
ce_bcnt := '0';
iact := '1';
ival := '0';
ierr := '0';
if unsigned(r.ccnt) = 0 then
tc_ccnt := '1';
end if;
if unsigned(r.bcnt) = 9 then
tc_bcnt := '1';
end if;
if unsigned(r.dcnt) > unsigned("00" & CLKDIV(CDWIDTH-1 downto 1)) then
dbit := '1';
end if;
case r.state is
when s_idle => -- s_idle: idle ----------------------
iact := '0';
ld_dcnt := '1'; -- always keep dcnt in reset
if RXSD = '0' then -- if start bit seen
if tc_ccnt = '1' then
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- start next bit
ce_bcnt := '1';
else
n.state := s_colb0; -- collect b0
end if;
else -- otherwise
ld_ccnt := '1'; -- keep all counters in reset
ld_bcnt := '1';
end if;
when s_colb0 => -- s_colb0: collect b0 (start bit) ---
if tc_ccnt = '1' then -- last cycle of b0 ?
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- "
ce_bcnt := '1';
else -- continue in b0 ?
if dbit='1' and RXSD='1' then -- too many 1's ?
n.state := s_idle; -- abort to idle
ld_dcnt := '1'; -- put counters in reset
ld_ccnt := '1';
ld_bcnt := '1';
end if;
end if;
when s_endb0 => -- s_endb0: finish b0 (start bit) ---
ld_dcnt := '1'; -- start next bit
if dbit = '1' then -- was it a 1 ?
n.state := s_idle; -- abort to idle
ld_ccnt := '1'; -- put counters in reset
ld_bcnt := '1';
else
if tc_ccnt = '1' then -- last cycle of bx ?
n.state := s_endbx; -- finish bx
ld_ccnt := '1';
ce_bcnt := '1';
else -- continue in b0 ?
n.state := s_colbx; -- collect bx
end if;
end if;
when s_colbx => -- s_colbx: collect bx ---------------
if tc_ccnt = '1' then -- last cycle of bx ?
n.state := s_endbx; -- finish bx
ld_ccnt := '1';
ce_bcnt := '1';
end if;
when s_endbx => -- s_endbx: finish bx ---------------
ld_dcnt := '1'; -- start next bit
n.sreg := dbit & r.sreg(7 downto 1);
if tc_ccnt = '1' then -- last cycle of bx ?
if tc_bcnt = '1' then
n.state := s_endb9; -- finish b9
ld_bcnt := '1'; -- and wrap bcnt
else
n.state := s_endbx; -- finish bx
ce_bcnt := '1';
end if;
ld_ccnt := '1';
else -- continue in bx ?
if tc_bcnt = '1' then
n.state := s_colb9; -- collect b9
else
n.state := s_colbx; -- collect bx
end if;
end if;
when s_colb9 => -- s_colb9: collect bx (stop bit) ----
if tc_ccnt = '1' then -- last cycle of b9 ?
n.state := s_endb9; -- finish b9
ld_ccnt := '1'; -- "
ld_bcnt := '1'; -- and wrap bcnt
else -- continue in b9 ?
if dbit='1' and RXSD='1' then -- already enough 1's ?
n.state := s_idle; -- finish to idle
ld_dcnt := '1'; -- put counters in reset
ld_ccnt := '1';
ld_bcnt := '1';
ival := '1';
end if;
end if;
when s_endb9 => -- s_endb9: finish bx (stop bit) ----
ld_dcnt := '1'; -- start next bit
if dbit = '1' then -- was it a valid stop bit ?
ival := '1';
else
ierr := '1';
end if;
if RXSD = '1' then -- line in idle state ?
n.state := s_idle; -- finish to idle state
ld_ccnt := '1'; -- and put counters in reset
ld_bcnt := '1'; -- "
else
if tc_ccnt = '1' then -- last cycle of b9 ?
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- "
ce_bcnt := '1';
else -- continue in b0 ?
n.state := s_colb0; -- collect bx
end if;
end if;
when others => null; -- -----------------------------------
end case;
if RESET = '1' then -- RESET seen
ld_ccnt := '1'; -- keep all counters in reset
ld_dcnt := '1';
ld_bcnt := '1';
n.state := s_idle;
end if;
if ld_ccnt = '1' then -- implement ccnt
n.ccnt := CLKDIV;
else
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
if ld_dcnt = '1' then -- implement dcnt
n.dcnt(CDWIDTH downto 1) := (others=>'0');
n.dcnt(0) := RXSD;
else
if RXSD = '1' then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
end if;
if ld_bcnt = '1' then -- implement bcnt
n.bcnt := (others=>'0');
else
if ce_bcnt = '1' then
n.bcnt := slv(unsigned(r.bcnt) + 1);
end if;
end if;
N_REGS <= n;
RXDATA <= r.sreg;
RXACT <= iact;
RXVAL <= ival;
RXERR <= ierr;
end process proc_next;
end syn;
| gpl-3.0 | 41718b615c03d1401b5e70d958ff8c90 | 0.433624 | 3.91737 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_bustimer.vhd | 1 | 18,405 | --------------------------------------------------------------------------------
-- Title : VME Bustimer
-- Project : A15
--------------------------------------------------------------------------------
-- File : vme_bustimer.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 10/02/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module handles the resets and the vme bus access time-out counting.
--
--------------------------------------------------------------------------------
-- Hierarchy:
-- wbb2vme
-- vme_ctrl
-- vme_bustimer
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: vme_bustimer.vhd,v $
-- Revision 1.3 2014/04/17 07:35:29 MMiehling
-- added signal prevent_sysrst
--
-- Revision 1.2 2012/08/27 12:57:22 MMiehling
-- changed minimum vme reset time to 1 ms
-- general rework of reset handling
--
-- Revision 1.1 2012/03/29 10:14:50 MMiehling
-- Initial Revision
--
-- Revision 1.13 2006/06/02 15:48:55 MMiehling
-- removed sysfailn_int from fsm to reduce logic (now active when startup_rstn active)
--
-- Revision 1.12 2006/05/18 14:29:03 MMiehling
-- arbitration failures when pci2vme is in slot1 => bugfix in deglitcher
-- corrected time-out counter description
-- changed reset release behaviour
--
-- Revision 1.11 2005/02/04 13:44:12 mmiehling
-- added generic simulation
--
-- Revision 1.10 2004/11/02 11:29:53 mmiehling
-- added registered rstn
--
-- Revision 1.9 2004/07/27 17:15:37 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.8 2004/06/17 13:02:26 MMiehling
-- removed clr_hit and sl_acc_reg
--
-- Revision 1.7 2003/12/17 15:51:43 MMiehling
-- sysfailn must be 1 or 0 because external driver makes z
--
-- Revision 1.6 2003/12/01 10:03:51 MMiehling
-- v2p_rst_intn is open collector now
--
-- Revision 1.5 2003/07/14 08:38:06 MMiehling
-- added sysfailn_int; changed rst_counter
--
-- Revision 1.4 2003/06/24 13:47:06 MMiehling
-- changed vme and cpu reset
--
-- Revision 1.3 2003/06/13 10:06:33 MMiehling
-- changed rst_fsm and slot1 detection
--
-- Revision 1.2 2003/04/22 11:02:58 MMiehling
-- reset does not work
--
-- Revision 1.1 2003/04/01 13:04:41 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY vme_bustimer IS
PORT (
clk : IN std_logic; -- global clock
rst : IN std_logic; -- global reset
startup_rst : IN std_logic; -- powerup reset
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
set_sysc : OUT std_logic; -- if set sysc-bit will be set
sysc_bit : IN std_logic; -- 1=slot1 0=slotx
clr_sysr : OUT std_logic; -- if set sysr-bit will be cleared
sysr_bit : IN std_logic; -- 1=system reset
-- connected with Slave Unit
dsain : IN std_logic; -- data strobe a in
dsbin : IN std_logic; -- data strobe b in
bgouten : OUT std_logic; -- enables SGL and bg3out signal
-- bus grant daisy chain is driven through requester in Access VME:
-----------------------------------------------------------------------
-- PINs:
sysfailn : OUT std_logic; -- indicates when A15 is not ready or in reset
sysrstn_in : IN std_logic;
sysrstn_out : OUT std_logic;
v2p_rst : OUT std_logic; -- Reset between VMEbus and Host CPU
bg3n_in : IN std_logic; -- bus grant signal in (if not connected => slot01)
slot01n : OUT std_logic; -- enables V_SYSCLK (16 MHz)
berrn_out : OUT std_logic -- bus error
);
--
END vme_bustimer;
ARCHITECTURE bustimer_arc OF vme_bustimer IS
CONSTANT CONST_10US : std_logic_vector(9 DOWNTO 0):= "1010011011"; -- =667 @ 66MHz => 10,005 us
CONSTANT CONST_200MS : std_logic_vector(14 DOWNTO 0):= "100111000010111"; -- = 19991 @ 10,005us =>
-- counter value for vme rstn => 250ms
SIGNAL btresn : std_logic; -- bus timer reset
SIGNAL cnt : std_logic_vector(12 DOWNTO 0); -- approximately 60 us
SIGNAL sysrstn_out_int : std_logic;
SIGNAL v2p_rst_int : std_logic;
TYPE rst_states IS (IDLE, WAIT_ON_RST, RST_VME, RST_VME2, WAIT_ON_VME, RST_CPU, WAIT_ON_CPU, STARTUP_END);
SIGNAL rst_state : rst_states;
SIGNAL pre_cnt : std_logic_vector(9 DOWNTO 0);
SIGNAL pre_cnt_end : std_logic;
SIGNAL rst_pre_cnt : std_logic;
SIGNAL rst_main_cnt : std_logic;
SIGNAL main_cnt : std_logic_vector(14 DOWNTO 0);
SIGNAL main_cnt_max_sig : std_logic_vector(14 DOWNTO 0);
SIGNAL main_cnt_end : std_logic;
SIGNAL sysrstn_q : std_logic;
SIGNAL sysrstn_qq : std_logic;
SIGNAL sysrstn_qqq : std_logic;
SIGNAL degl_sysrstn : std_logic;
SIGNAL rst_q : std_logic;
SIGNAL rst_qq : std_logic;
SIGNAL rst_qqq : std_logic;
SIGNAL degl_rst : std_logic;
SIGNAL dsain_q : std_logic;
SIGNAL dsbin_q : std_logic;
SIGNAL bg3n_in_q : std_logic;
SIGNAL bg3n_in_qq : std_logic;
SIGNAL pre_cnt_max_sig : std_logic_vector(9 DOWNTO 0);
SIGNAL set_sysc_int : std_logic;
BEGIN
slot01n <= NOT sysc_bit;
sysrstn_out <= sysrstn_out_int;
set_sysc <= set_sysc_int;
sysfailn <= '0' WHEN startup_rst = '1' ELSE '1';
v2p_rst <= v2p_rst_int;
-------------------------------------------------------------------------------
-- Bus Timer. Works only when sysc_bit is set. Generates a bus error after 62 us
-- During normal operation, reset is triggered each
-- time both VMEbus Datastrobes are high.
-------------------------------------------------------------------------------
btresn <= '1' WHEN (dsain_q = '1' AND dsbin_q = '1') ELSE '0';
degl : PROCESS(clk, startup_rst)
BEGIN
IF startup_rst = '1' THEN
sysrstn_q <= '1';
sysrstn_qq <= '1';
sysrstn_qqq <= '1';
degl_sysrstn <= '1';
rst_q <= '0';
rst_qq <= '0';
rst_qqq <= '0';
degl_rst <= '0';
bg3n_in_q <= '1';
bg3n_in_qq <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
bg3n_in_q <= bg3n_in;
bg3n_in_qq <= bg3n_in_q;
sysrstn_q <= sysrstn_in;
sysrstn_qq <= sysrstn_q;
sysrstn_qqq <= sysrstn_qq;
IF sysrstn_q = '0' AND sysrstn_qq = '0' AND sysrstn_qqq = '0' THEN
degl_sysrstn <= '0';
ELSIF sysrstn_q = '1' AND sysrstn_qq = '1' AND sysrstn_qqq = '1' THEN
degl_sysrstn <= '1';
ELSE
degl_sysrstn <= degl_sysrstn;
END IF;
rst_q <= rst;
rst_qq <= rst_q;
rst_qqq <= rst_qq;
IF rst_q = '1' AND rst_qq = '1' AND rst_qqq = '1' THEN
degl_rst <= '1';
ELSIF rst_q = '0' AND rst_qq = '0' AND rst_qqq = '0' THEN
degl_rst <= '0';
END IF;
END IF;
END PROCESS degl;
bustim : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
cnt <= (OTHERS => '0');
berrn_out <= '1';
dsain_q <= '1';
dsbin_q <= '1';
ELSIF clk'event AND clk = '1' THEN
dsain_q <= dsain;
dsbin_q <= dsbin;
IF (btresn = '1') THEN
cnt <= (OTHERS => '0');
ELSIF (dsain_q = '0' OR dsbin_q = '0') AND sysc_bit = '1' THEN -- counter starts with DSA or DSB signal
cnt <= cnt + 1;
END IF;
IF cnt(12) = '1' THEN
berrn_out <= '0';
ELSIF btresn = '1' THEN
berrn_out <= '1';
END IF;
END IF;
END PROCESS bustim;
pre_cnt_max_sig <= CONST_10US;
main_cnt_max_sig <= CONST_200MS;
rst_cnt : PROCESS(clk, startup_rst)
BEGIN
IF startup_rst = '1' THEN
main_cnt <= (OTHERS => '0');
pre_cnt <= (OTHERS => '0');
main_cnt_end <= '0';
pre_cnt_end <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
-- pre counter for counting up to 10 us
IF rst_pre_cnt = '1' THEN
pre_cnt <= (OTHERS => '0');
pre_cnt_end <= '0';
ELSIF pre_cnt = pre_cnt_max_sig THEN
pre_cnt <= (OTHERS => '0');
pre_cnt_end <= '1';
ELSE
pre_cnt <= pre_cnt + 1;
pre_cnt_end <= '0';
END IF;
-- main counter with base of 10 us counts up to 200 ms reset time
IF rst_main_cnt = '1' THEN
main_cnt <= (OTHERS => '0');
main_cnt_end <= '0';
ELSIF main_cnt = main_cnt_max_sig AND pre_cnt_end = '1' THEN
main_cnt <= (OTHERS => '0');
main_cnt_end <= '1';
ELSIF pre_cnt_end = '1' THEN
main_cnt <= main_cnt + 1;
main_cnt_end <= '0';
END IF;
END IF;
END PROCESS rst_cnt;
rst_fsm : PROCESS (clk, startup_rst)
BEGIN
IF startup_rst = '1' THEN
set_sysc_int <= '0';
bgouten <= '0';
sysrstn_out_int <= '0';
v2p_rst_int <= '0';
clr_sysr <= '0';
rst_state <= IDLE;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF set_sysc_int = '1' AND sysc_bit = '1' THEN -- if status reg has stored slot 1 location => clear request to set bit
set_sysc_int <= '0';
ELSIF bg3n_in_qq = '0' AND main_cnt_end = '1' AND rst_state = IDLE THEN -- slot 1 was detected => keep in mind until stored in status reg
set_sysc_int <= '1';
END IF;
CASE rst_state IS
-- wait until powerup reset time has elapsed (16383 * system_clock_period = 250 us @ 66MHz)
WHEN IDLE =>
bgouten <= '0';
sysrstn_out_int <= '0'; -- activate reset to vme-bus
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '0';
IF main_cnt_end = '1' THEN
rst_state <= STARTUP_END;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= IDLE;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- release vme reset and wait for deactivation of vme- and cpu-reset (minimum 16383 * system_clock_period = 250 us @ 66MHz)
WHEN STARTUP_END =>
bgouten <= '0';
sysrstn_out_int <= '1'; -- no reset to vme-bus
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '0';
IF main_cnt_end = '1' AND degl_rst = '0' AND degl_sysrstn = '1' THEN -- wait until cpu and vme does not deliver active reset
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= STARTUP_END;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- normal operation: wait until either cpu-reset or vme-reset is active
WHEN WAIT_ON_RST =>
bgouten <= '1';
sysrstn_out_int <= '1'; -- no reset to vme-bus
clr_sysr <= '0';
v2p_rst_int <= '0'; -- no reset to cpu
IF (degl_rst = '1' OR sysr_bit = '1') AND sysc_bit = '1' THEN -- in slot 1 and cpu or bit has active reset
rst_state <= RST_VME;
rst_pre_cnt <= '0';
rst_main_cnt <= '1';
ELSIF degl_sysrstn = '0' THEN -- not in slot 1 and vme-bus has active reset
rst_state <= RST_CPU;
rst_pre_cnt <= '1'; -- clear counter in order to set cpu 10 us to reset
rst_main_cnt <= '0';
ELSE
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- set cpu reset active
WHEN RST_CPU =>
bgouten <= '1';
sysrstn_out_int <= '1'; -- no reset to vme-bus
v2p_rst_int <= '1'; -- active reset to cpu
clr_sysr <= '0';
IF pre_cnt_end = '1' THEN -- after 10 us, release cpu reset
rst_state <= WAIT_ON_CPU;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= RST_CPU;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- wait until vme-reset has got deactivated
WHEN WAIT_ON_CPU =>
bgouten <= '1';
sysrstn_out_int <= '1'; -- no reset to vme-bus
v2p_rst_int <= not degl_sysrstn;
clr_sysr <= '0';
IF degl_sysrstn = '1' AND degl_rst = '0' THEN -- wait until vme-bus and cpu reset is inactive
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= WAIT_ON_CPU;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- activate vme reset for (16383 * system_clock_period = 250 us @ 66MHz)
WHEN RST_VME =>
bgouten <= '1';
IF prevent_sysrst = '1' THEN
sysrstn_out_int <= '1'; -- no reset
ELSE
sysrstn_out_int <= '0'; -- active reset to vme-bus
END IF;
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '1';
IF main_cnt_end = '1' THEN -- keep vme-bus reset active for counter time
rst_state <= RST_VME2;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= RST_VME;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- extend active vme reset time for (16383 * system_clock_period = 250 us @ 66MHz) till cpu reset has got deactivated
WHEN RST_VME2 =>
bgouten <= '1';
IF prevent_sysrst = '1' THEN
sysrstn_out_int <= '1'; -- no reset
ELSE
sysrstn_out_int <= '0'; -- active reset to vme-bus
END IF;
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '1';
IF main_cnt_end = '1' AND degl_rst = '0' THEN -- wait until cpu-reset is inactive
rst_state <= WAIT_ON_VME;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= RST_VME2;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- wait until vme reset has got deactivated
WHEN WAIT_ON_VME =>
bgouten <= '1';
sysrstn_out_int <= '1'; -- no reset to vme-bus
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '0';
IF degl_sysrstn = '1' THEN -- wait until vme-bus reset is inactive
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= WAIT_ON_VME;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
WHEN OTHERS =>
bgouten <= '0';
sysrstn_out_int <= '1';
v2p_rst_int <= '0';
clr_sysr <= '0';
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END CASE;
END IF;
END PROCESS rst_fsm;
END bustimer_arc;
| gpl-3.0 | 75f4c1eaac301e3635bbd394791528eb | 0.453735 | 3.858491 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwti_v1_00_a/hdl/vhdl/memory.vhd | 3 | 10,450 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AWIDTH -- User logic address bus width
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user logic
-- Bus2IP_Burst -- Bus to IP burst-mode qualifier
-- Bus2IP_RdCE -- Bus to IP read chip enable for user logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user logic
-- Bus2IP_RdReq -- Bus to IP read request
-- Bus2IP_WrReq -- Bus to IP write request
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- Bus2IP_MstError -- Bus to IP master error
-- Bus2IP_MstLastAck -- Bus to IP master last acknowledge
-- Bus2IP_MstRdAck -- Bus to IP master read acknowledge
-- Bus2IP_MstWrAck -- Bus to IP master write acknowledge
-- Bus2IP_MstRetry -- Bus to IP master retry
-- Bus2IP_MstTimeOut -- Bus to IP mster timeout
-- IP2Bus_Addr -- IP to Bus address for the master transaction
-- IP2Bus_MstBE -- IP to Bus byte-enables qualifiers
-- IP2Bus_MstBurst -- IP to Bus burst qualifier
-- IP2Bus_MstBusLock -- IP to Bus bus-lock qualifier
-- IP2Bus_MstNum -- IP to Bus burst size indicator
-- IP2Bus_MstRdReq -- IP to Bus master read request
-- IP2Bus_MstWrReq -- IP to Bus master write request
-- IP2IP_Addr -- IP to IP local device address for the master transaction
------------------------------------------------------------------------------
entity memory is
generic
(
MEM_ADDR : std_logic_vector := x"00000000";
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 64;
C_NUM_CE : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(0 to C_AWIDTH-1);
length : in std_logic_vector(0 to 23);
ack : out std_logic;
last : out std_logic;
--Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
--Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
--Bus2IP_Burst : in std_logic;
--Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_CE-1);
--Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_CE-1);
--Bus2IP_RdReq : in std_logic;
--Bus2IP_WrReq : in std_logic;
--IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
--IP2Bus_Retry : out std_logic;
--IP2Bus_Error : out std_logic;
--IP2Bus_ToutSup : out std_logic;
--IP2Bus_RdAck : out std_logic;
--IP2Bus_WrAck : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1)
);
end entity memory;
architecture behavioral of memory is
type state is
(
IDLE,
SINGLE,
BURST,
LASTMEM,
CHECK
);
signal go : std_logic;
signal mbrst_cv : std_logic;
signal mbrst_nv : std_logic;
signal rd_cv : std_logic;
signal rd_nv : std_logic;
signal wr_cv : std_logic;
signal wr_nv : std_logic;
signal mem_cs : state;
signal mem_ns : state;
signal count_cv : std_logic_vector(0 to 23);
signal count_nv : std_logic_vector(0 to 23);
signal baddr_cv : std_logic_vector(0 to 31);
signal baddr_nv : std_logic_vector(0 to 31);
signal be_cv : std_logic_vector(0 to 7);
signal be_nv : std_logic_vector(0 to 7);
signal burst_cv : std_logic_vector(0 to 4);
signal burst_nv : std_logic_vector(0 to 4);
begin
IP2Bus_Addr <= baddr_cv;
IP2Bus_MstBurst <= mbrst_nv;
IP2Bus_MstBE <= be_cv;
IP2Bus_MstBusLock <= '0';
IP2Bus_MstNum <= burst_nv;
IP2IP_Addr <= MEM_ADDR;
ack <= Bus2IP_MstRdAck or Bus2IP_MstWrAck;
go <= rd or wr;
update : process(clk,rst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWrReq <= '0';
mbrst_cv <= '0';
rd_cv <= '0';
wr_cv <= '0';
be_cv <= (others => '0');
mem_cs <= IDLE;
count_cv <= (others => '0');
baddr_cv <= (others => '0');
burst_cv <= (others => '0');
else
IP2Bus_MstRdReq <= rd_nv;
IP2Bus_MstWrReq <= wr_nv;
mbrst_cv <= mbrst_nv;
be_cv <= be_nv;
rd_cv <= rd_nv;
wr_cv <= wr_nv;
mem_cs <= mem_ns;
count_cv <= count_nv;
baddr_cv <= baddr_nv;
burst_cv <= burst_nv;
end if;
end if;
end process update;
controller : process(mem_cs,count_cv,baddr_cv,burst_cv,go,length,addr,
Bus2IP_MstLastAck,rd_cv,wr_cv,rd,wr,be_cv) is
begin
mbrst_nv <= '0';
last <= '0';
rd_nv <= rd_cv;
wr_nv <= wr_cv;
be_nv <= be_cv;
mem_ns <= mem_cs;
count_nv <= count_cv;
baddr_nv <= baddr_cv;
burst_nv <= burst_cv;
case mem_cs is
when IDLE =>
rd_nv <= rd;
wr_nv <= wr;
if( go = '1' ) then
count_nv <= length;
baddr_nv <= addr;
mem_ns <= CHECK;
if( length(23) = '1' ) then
case addr(29 to 31) is
when "000" => be_nv <= x"80";
when "001" => be_nv <= x"40";
when "010" => be_nv <= x"20";
when "011" => be_nv <= x"10";
when "100" => be_nv <= x"08";
when "101" => be_nv <= x"04";
when "110" => be_nv <= x"02";
when others => be_nv <= x"01";
end case;
elsif( length(22) = '1' ) then
case addr(29 to 30) is
when "00" => be_nv <= x"C0";
when "01" => be_nv <= x"30";
when "10" => be_nv <= x"0C";
when others => be_nv <= x"03";
end case;
elsif( length(21) = '1') then
case addr(29) is
when '0' => be_nv <= x"F0";
when others => be_nv <= x"0F";
end case;
else
be_nv <= x"FF";
end if;
end if;
when SINGLE =>
if ( Bus2IP_MstLastAck = '1' ) then
rd_nv <= '0';
wr_nv <= '0';
mem_ns <= IDLE;
last <= '1';
else
burst_nv <= "00001";
end if;
when BURST =>
mbrst_nv <= '1';
if ( Bus2IP_MstLastAck = '1' ) then
mem_ns <= CHECK;
count_nv <= count_cv - 128;
baddr_nv <= baddr_cv + 128;
else
burst_nv <= "10000";
end if;
when LASTMEM =>
mbrst_nv <= '1';
if ( Bus2IP_MstLastAck = '1' ) then
count_nv <= (others => '0');
last <= '1';
rd_nv <= '0';
wr_nv <= '0';
mem_ns <= IDLE;
else
burst_nv <= count_cv(16 to 20);
end if;
when CHECK =>
if ( count_cv = 0 ) then
mem_ns <= IDLE;
rd_nv <= '0';
wr_nv <= '0';
last <= '1';
elsif ( count_cv <= 8 ) then
burst_nv <= "00001";
mem_ns <= SINGLE;
elsif ( count_cv <= 128 ) then
mbrst_nv <= '1';
burst_nv <= count_cv(16 to 20);
mem_ns <= LASTMEM;
else
mbrst_nv <= '1';
burst_nv <= "10000";
mem_ns <= BURST;
end if;
when others =>
mem_ns <= IDLE;
end case;
end process controller;
end behavioral;
| bsd-3-clause | 22e6b8af97c2aad3ea0e2ef11e03a9ae | 0.425933 | 3.837679 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/counter.vhd | 3 | 9,004 | -------------------------------------------------------------------------------
-- Counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter.vhd
--
-- Description: Implements a parameterizable N-bit counter
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- 1 - LUT per bit plus 3 LUTS for extra features
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter.vhd
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- KC 2002-01-23 First Version
-- LCW 2004-10-08 Updated for NCSim
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity Counter is
generic(
C_NUM_BITS : Integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity Counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of Counter is
signal alu_cy : std_logic_vector(C_NUM_BITS downto 0);
signal iCount_Out : std_logic_vector(C_NUM_BITS - 1 downto 0);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(0) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for I in 0 to (C_NUM_BITS - 1) generate
begin
Counter_Bit_I : entity opb_v20_v1_10_d.counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(I), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(I), -- [out]
Carry_Out => alu_cy(I+1) -- [out]
);
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(C_NUM_BITS) xor Count_Down;
CARRY_OUT_I: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture imp;
| bsd-3-clause | 3f79cb2f2f356eaf8d70bb2f5122952f | 0.403376 | 5.145143 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_init_4.vhd | 2 | 15,108 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_init_4.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- retVal = hthread_mutex_init( mutex, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 6f383b09601871597764bebd06a895df | 0.537861 | 3.848192 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/mutex_init_1.vhd | 2 | 22,505 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
--signal reg5, reg5_next : std_logic_vector(0 to 31);
--signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
--reg5 <= reg5_next;
--reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
--reg5_next <= reg5;
--reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: mutex_init_stress_1
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * completedMutex
-- reg4 = * mutex
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of completedMutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
next_state <= STATE_6;
-- while( *(data->numberOfTestsCompleted) < *(data->numberOfTestsToComplete) )
when STATE_6 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Do the comparision between completed and toBeCompleted
if ( intrfc2thrd_value < reg1 ) then
next_state <= STATE_8;
else
next_state <= FUNCTION_EXIT;
end if;
-- mutex = (hthread_mutex_t *) malloc( sizeof( hthread_mutex_t ) );
when STATE_8 =>
-- push 8B, the size of a hthread_mutex_t
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000008";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- call malloc
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_MALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
-- if ( mutex == NULL ) thread_exit_WITHERROR( NULL );
when STATE_10 =>
reg4_next <= intrfc2thrd_value;
case intrfc2thrd_value is
when x"00000000" =>
-- push null and call exit
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when others =>
next_state <= STATE_12;
end case;
when STATE_11 =>
-- Call exit with error
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT_ERROR;
thrd2intrfc_value <= Z32;
-- hthread_mutex_init( mutex, NULL );
when STATE_12 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
-- call MUTEX_INIT
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_15;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( mutex );
when STATE_15 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_27;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( mutex );
when STATE_27 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_28;
when STATE_28 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_17;
next_state <= WAIT_STATE;
-- hthread_mutex_destroy( mutex );
when STATE_17 =>
-- push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_mutex_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
-- free( mutex );
when STATE_19 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call free
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->completedMutex );
when STATE_21 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- *( data->numberOfTestsCompleted) += 1;
when STATE_23 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_24 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_25;
-- hthread_mutex_unlock( data->completedMutex );
when STATE_25 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_26;
when STATE_26 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 5a087d410c6afcb7feac3baa872abd69 | 0.558942 | 3.686927 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/peripherals/wishbone_gps.vhd | 2 | 9,318 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:06:21 03/22/2014
-- Design Name:
-- Module Name: wishbone_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
use work.logi_primitive_pack.all ;
entity wishbone_gps is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
baudrate : positive := 115_200
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
rx_in : in std_logic
);
end wishbone_gps;
architecture Behavioral of wishbone_gps is
component async_serial is
generic(CLK_FREQ : positive := 100_000_000; BAUDRATE : positive := 115_200; NMEA_HEADER : string := "$GPRMC") ;
port( clk, reset : in std_logic ;
rx : in std_logic ;
tx : out std_logic ;
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_ready : out std_logic ;
data_send : in std_logic ;
available : out std_logic
);
end component;
component nmea_frame_extractor is
generic(nmea_header : string := "$GPRMC");
port(
clk, reset : in std_logic ;
nmea_byte_in : in std_logic_vector(7 downto 0);
new_byte_in : in std_logic ;
nmea_byte_out : out std_logic_vector(7 downto 0);
new_byte_out : out std_logic;
frame_size : out std_logic_vector(7 downto 0);
end_of_frame : out std_logic;
frame_error : out std_logic
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- uart signals
signal rx_register : std_logic_vector(7 downto 0);
signal ctrl_register : std_logic_vector(15 downto 0);
signal send_data, data_ready, uart_available : std_logic ;
-- nmea filter signals
signal new_nmea : std_logic ;
signal nmea_out : std_logic_vector(7 downto 0);
signal frame_error : std_logic ;
-- fifo signals
signal reset_fifo : std_logic ;
signal fifo_empty, fifo_full, pop_fifo : std_logic ;
signal fifo_out : std_logic_vector(15 downto 0);
-- 8 bit to 16 bit logic
signal new_nmea16, mod_count, end_of_frame : std_logic ;
signal char_buffer, nb_available, nmea_frame_size : std_logic_vector(7 downto 0);
signal nmea16 : std_logic_vector(15 downto 0);
-- double buffer signal
signal buffer_use : std_logic_vector(1 downto 0);
signal buffer_read_data : std_logic_vector(15 downto 0);
signal read_address, write_address : std_logic_vector(7 downto 0);
signal buffer_locked, free_buffer, end_of_frame_delayed : std_logic ;
signal write_buffer : std_logic ;
signal buffer_address, char_write_index : std_logic_vector(7 downto 0);
signal buffer_input : std_logic_vector(15 downto 0);
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
reset_fifo <= wbs_writedata(0) when write_ack = '1' else
--- '1' when frame_error = '1' else -- could corrupt ongoing frames ...
gls_reset;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
-- ctrl_register <= (others => '0');
-- wbs_readdata <= (others => '0');
read_ack <= '0' ;
elsif rising_edge(gls_clk) then
-- if read_ack = '1' and (wbs_strobe = '0' and wbs_cycle = '0' ) and wbs_address(4)='0' then -- reset when read
-- pop_fifo <= '1' ;
-- else
-- pop_fifo <= '0' ;
-- end if ;
--
-- ctrl_register(7 downto 0) <= nb_available ;
-- ctrl_register(15 downto 9) <= "0000000" ;
--
-- ctrl_register(8) <= fifo_full ;
--if reset_fifo = '1' then -- RS register for fifo full to detect overun
-- ctrl_register(8) <= '0' ;
-- elsif fifo_full = '1' then
-- ctrl_register(8) <= '1' ;
-- end if ;
-- if wbs_address(4) = '0' then
-- wbs_readdata <= fifo_out ;
-- else
-- wbs_readdata <= ctrl_register ;
-- end if ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1') then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
serial_0 : async_serial
generic map(CLK_FREQ => 100_000_000, BAUDRATE => baudrate)
port map( clk => gls_clk, reset => gls_reset ,
rx => rx_in,
tx => open,
data_out => rx_register,
data_in => (others => '0'),
data_ready => data_ready,
data_send => '0',
available => open
);
filter_nmea : nmea_frame_extractor
generic map(nmea_header => "$GPRMC")
port map(
clk => gls_clk, reset => (gls_reset or reset_fifo),
nmea_byte_in => rx_register,
new_byte_in => data_ready,
nmea_byte_out => nmea_out,
new_byte_out => new_nmea,
frame_size => nmea_frame_size,
end_of_frame => end_of_frame,
frame_error => frame_error
);
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
char_buffer <= (others => '0');
mod_count <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
char_buffer <= (others => '0');
mod_count <= '0' ;
elsif new_nmea = '1' then
char_buffer <= nmea_out ;
mod_count <= not mod_count ;
end if ;
end if ;
end process ;
new_nmea16 <= new_nmea and mod_count ;
nmea16 <= nmea_out & char_buffer ;
--
---- handling nb_available manually ...
--process(gls_clk, gls_reset)
--begin
-- if gls_reset = '1' then
-- nb_available <= (others => '0');
-- elsif gls_clk'event and gls_clk = '1' then
-- if reset_fifo = '1' then
-- nb_available <= (others => '0');
-- elsif new_nmea16 = '1' and fifo_full = '0' and pop_fifo = '0' then
-- nb_available <= nb_available + 1 ;
-- elsif pop_fifo = '1' and fifo_empty = '0' and new_nmea16 = '0' then
-- nb_available <= nb_available - 1 ;
-- end if ;
-- end if ;
--end process ;
--
--fifo_0 : small_fifo
--generic map( WIDTH => 16, DEPTH => 64, THRESHOLD => 4)
--port map(clk => gls_clk,
-- resetn => (not reset_fifo),
-- push => new_nmea16,
-- pop => pop_fifo,
-- full => fifo_full,
-- empty => fifo_empty,
-- limit => open,
-- data_in => nmea16,
-- data_out => fifo_out
-- );
-- handle address
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
char_write_index <= (others => '0');
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
char_write_index <= X"01";
elsif new_nmea16 = '1' then
char_write_index <= char_write_index + 1 ;
end if ;
end_of_frame_delayed <= end_of_frame ;
end if ;
end process ;
buffer_address <= (others => '0') when end_of_frame_delayed = '1' else
char_write_index ;
buffer_input <= (X"00" & nmea_frame_size) when end_of_frame_delayed = '1' else
nmea16 ;
write_buffer <= new_nmea16 OR end_of_frame OR end_of_frame_delayed;
buffer_locked <= read_ack ;
wbs_readdata <= buffer_read_data ;
-- ram being used to implement the double buffer memory
ram0 : dpram_NxN
generic map(SIZE => 256, NBIT => 16, ADDR_WIDTH=> 8) -- need to be computed
port map(
clk => gls_clk,
we => write_buffer ,
di => buffer_input,
a => write_address ,
dpra => read_address,
spo => open,
dpo => buffer_read_data
);
-- highest bit select buffer to write to
write_address(write_address'high) <= buffer_use(1) ;
write_address(write_address'high-1 downto 0) <= buffer_address(write_address'high-1 downto 0);
read_address(read_address'high) <= buffer_use(0) ;
read_address(read_address'high-1 downto 0) <= wbs_address(read_address'high-1 downto 0);
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
buffer_use <= "01" ;
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
free_buffer <= '1' ;
elsif free_buffer = '1' and buffer_locked = '0' then -- if write and one buffer at least is available
buffer_use <= not buffer_use ;
free_buffer <= '0' ;
end if ;
end if ;
end process ;
end Behavioral;
| lgpl-3.0 | e24f035fa0f5b71693de4f734d50ca2b | 0.612792 | 3 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_trylock_3.vhd | 2 | 15,473 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_trylock_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_trylock( mutex );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_trylock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_TRYLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= STATE_5;
-- hthread_mutex_unlock( mutex );
when STATE_5 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- Call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 520d27d54994a6bc1b411e5a4473c48e | 0.539973 | 3.833746 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_fsmlang_special_pic_v1_00_a/hdl/vhdl/complete_pic.vhd | 2 | 4,704 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity complete_pic is
generic(
IID_WIDTH : integer := 3;
REG_SIZE : integer := 9;
CMD_WIDTH : integer := 4;
C_NUM_INTERRUPTS : integer := 8
);
port
(
--User Interface Port(s)
msg_chan_channelDataIn : out std_logic_vector(0 to (8 - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (8 - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
go : in std_logic;
ack : out std_logic;
TID_IN : in std_logic_vector(0 to 7);
IID_IN : in std_logic_vector(0 to IID_WIDTH - 1);
CMD_IN : in std_logic_vector(0 to CMD_WIDTH - 1);
RET_OUT : out std_logic_vector(0 to 7);
TID_OUT : out std_logic_vector(0 to 7);
--Controller Port(s)
interrupts_in : in std_logic_vector(0 to C_NUM_INTERRUPTS - 1);
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity complete_pic;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of complete_pic is
-- Component Definitions
COMPONENT PIC
GENERIC(
IID_WIDTH : integer := 3;
REG_SIZE : integer := 9;
CMD_WIDTH : integer := 4;
C_NUM_INTERRUPTS : integer := 8
);
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
go : IN std_logic;
ack : OUT std_logic;
TID_IN : IN std_logic_vector(0 to 7);
IID_IN : IN std_logic_vector(0 to IID_WIDTH-1);
CMD_IN : IN std_logic_vector(0 to CMD_WIDTH-1);
RUPT_IN : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
IER_OUT : OUT std_logic_vector(0 to C_NUM_INTERRUPTS-1);
IAR_OUT : OUT std_logic_vector(0 to C_NUM_INTERRUPTS-1);
RET_OUT : OUT std_logic_vector(0 to 7);
TID_OUT : OUT std_logic_vector(0 to 7);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
COMPONENT INTC
generic(
C_NUM_INTERRUPTS : integer := 8;
NEW_IID_WIDTH : integer := 3
);
PORT(
interrupts_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
ier_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
iar_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
interrupts_out : OUT std_logic_vector(0 to C_NUM_INTERRUPTS-1);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
-- Signal Definitions
signal IER_sig : std_logic_vector(0 to C_NUM_INTERRUPTS-1);
signal IAR_sig : std_logic_vector(0 to C_NUM_INTERRUPTS-1);
signal PEND_sig : std_logic_vector(0 to C_NUM_INTERRUPTS-1);
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
begin
-- Component Interconnection
PIC_LOGIC : PIC
generic map(
IID_WIDTH => IID_WIDTH,
REG_SIZE => REG_SIZE,
CMD_WIDTH => CMD_WIDTH,
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS
)
port map(
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
go => go,
ack => ack,
TID_IN => TID_IN,
IID_IN => IID_IN,
CMD_IN => CMD_IN,
RUPT_IN => PEND_sig,
IER_OUT => IER_sig,
IAR_OUT => IAR_sig,
RET_OUT => RET_OUT,
TID_OUT => TID_OUT,
clock_sig => clock_sig,
reset_sig => reset_sig
);
INTC_LOGIC : INTC
generic map(
NEW_IID_WIDTH => IID_WIDTH,
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS
)
port map(
interrupts_in => interrupts_in,
ier_in => IER_sig,
iar_in => IAR_sig,
interrupts_out => PEND_sig,
clock_sig => clock_sig,
reset_sig => reset_sig
);
end architecture implementation;
| bsd-3-clause | 17b8a391623575a83ed5089b8c20efc7 | 0.579932 | 3.374462 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/or_gate.vhd | 2 | 9,211 | -------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
| bsd-3-clause | cacd4708b128a7c430e6f4863cd8e24b | 0.41331 | 4.970858 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.