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wfjm/w11 | rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd | 1 | 5,809 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n4 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 14.5-14.7; viv 2016.1-2018.3; ghdl 0.29-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.6.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.6 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.5.6 add sys_conf_dmpcnt
-- 2018-09-09 1044 1.5.5 use _cache_twidth TW=7 (32 kByte), timing issues
-- 2018-09-08 1043 1.5.3 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.5.2 re-enable dmcmon
-- 2017-01-29 847 1.5.1 add sys_conf_ibd_deuna
-- 2016-07-16 788 1.5 use cram_*delay functions to determine delays
-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype
-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise
-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt
-- 2016-05-28 770 1.4.2 sys_conf_mem_losize now type natural
-- 2016-05-26 768 1.4.1 set dmscnt=0 (vivado fsm issue); TW=8 (@90 MHz)
-- 2016-03-28 755 1.4 use serport_2clock2 -> define clkser
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth
-- 2016-03-13 742 1.2.2 add sysmon_bus
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions
-- 2015-02-07 643 1.1 drop bram and minisys options
-- 2013-09-34 534 1.0 Initial version (cloned from _n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
-- now under derived constants
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | f05c9916389a950dd8ee587c6045d0b7 | 0.5958 | 3.447478 | false | true | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys4d/tb/sys_conf_sim.vhd | 1 | 1,831 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n4d (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | e08dad121823e4cc57dcf14c18019563 | 0.617149 | 3.59725 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_02400_bad.vhd | 1 | 2,818 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02400_bad.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of reset name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity CNE_02400_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Rst_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_02400_bad;
architecture Behavioral of CNE_02400_bad is
signal Reset_temp_n : std_logic;
begin
Reset_temp_n <= i_Rst_n;
DFF1:DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => Reset_temp_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE | gpl-3.0 | 0e962a2ec73665034ff445f0e6c8f9e1 | 0.477289 | 4.410016 | false | false | false | false |
wfjm/w11 | rtl/bplib/basys3/tb/basys3_dummy.vhd | 1 | 1,743 | -- $Id: basys3_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: basys3_dummy - syn
-- Description: basys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_basys3
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0.1 fix typos
-- 2015-01-15 634 1.0 Initial version (derived from nexys4_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity basys3_dummy is -- BASYS 3 dummy (base; loopback)
-- implements basys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end basys3_dummy;
architecture syn of basys3_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
| gpl-3.0 | 25d363366455965b5d0262a9ed28cb71 | 0.487091 | 3.654088 | false | false | false | false |
jasonpeng/cg3207-proj | EX_MEM_BUFF.vhd | 1 | 3,144 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:20:35 10/31/2013
-- Design Name:
-- Module Name: EX_MEM_BUFF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EX_MEM_BUFF is
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
-- states received from EX
-- state registers
IN_EX_MemWrite : in STD_LOGIC;
IN_EX_MemToReg : in STD_LOGIC;
IN_EX_MemRead : in STD_LOGIC;
IN_EX_RegWrite : in STD_LOGIC;
-- alu related
IN_EX_OVF : in STD_LOGIC;
IN_EX_Zero : in STD_LOGIC;
IN_EX_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_ALU_Result_2 : in STD_LOGIC_VECTOR(31 downto 0);
IN_EX_MULDIV : in STD_LOGIC;
IN_EX_Data2 : in STD_LOGIC_VECTOR(31 downto 0); -- for DM Write Data
IN_EX_REG_WriteAddr : in STD_LOGIC_VECTOR(4 downto 0); -- register address
OUT_MEM_MemWrite : out STD_LOGIC;
OUT_MEM_MemToReg : out STD_LOGIC;
OUT_MEM_MemRead : out STD_LOGIC;
OUT_MEM_RegWrite : out STD_LOGIC;
-- alu related
OUT_MEM_OVF : out STD_LOGIC;
OUT_MEM_Zero : out STD_LOGIC;
OUT_MEM_ALU_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MEM_ALU_Result_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MEM_MULDIV : out STD_LOGIC;
OUT_MEM_Data2 : out STD_LOGIC_VECTOR(31 downto 0); -- for DM Write Data
OUT_MEM_REG_WriteAddr : out STD_LOGIC_VECTOR(4 downto 0) -- register address
);
end EX_MEM_BUFF;
architecture Behavioral of EX_MEM_BUFF is
begin
process(CLK, RESET)
begin
if (RESET = '1') then
OUT_MEM_MemWrite <= '0';
OUT_MEM_MemToReg <= '0';
OUT_MEM_MemRead <= '0';
OUT_MEM_RegWrite <= '0';
OUT_MEM_OVF <= '0';
OUT_MEM_Zero <= '0';
OUT_MEM_ALU_Result <= (others => '0');
OUT_MEM_ALU_Result_2 <= (others => '0');
OUT_MEM_MULDIV <= '0';
OUT_MEM_Data2 <= (others => '0');
OUT_MEM_REG_WriteAddr <= (others => '0');
elsif rising_edge(CLK) then
OUT_MEM_MemWrite <= IN_EX_MemWrite;
OUT_MEM_MemToReg <= IN_EX_MemToReg;
OUT_MEM_MemRead <= IN_EX_MemRead;
OUT_MEM_RegWrite <= IN_EX_RegWrite;
OUT_MEM_OVF <= IN_EX_OVF;
OUT_MEM_Zero <= IN_EX_Zero;
OUT_MEM_ALU_Result <= IN_EX_ALU_Result;
OUT_MEM_ALU_Result_2 <= IN_EX_ALU_Result_2;
OUT_MEM_MULDIV <= IN_EX_MULDIV;
OUT_MEM_Data2 <= IN_EX_Data2;
OUT_MEM_REG_WriteAddr <= IN_EX_REG_WriteAddr;
end if;
end process;
end Behavioral;
| gpl-2.0 | 265ac4e27e83f146d7f6b7994d329ad5 | 0.576654 | 3.122145 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rbd_bram.vhd | 1 | 6,149 | -- $Id: rbd_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_bram - syn
-- Description: rbus dev: rbus bram test target
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
--
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-26 349 12.1 M53d xc3s1000-4 23 61 - 34 s 6.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-13 593 4.1 no default rbus addess anymore, def=0
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2010-12-31 352 1.0.2 simplify irb_ack logic
-- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x
-- 2010-12-26 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 0 cntl r/w/- Control register
-- 15:10 nbusy r/w/- busy cycles
-- 9:00 addr r/w/- bram address (will auto-increment)
-- 1 15:00 data r/w/- Data register (read/write to bram via addr)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_bram is -- rbus dev: rbus bram test target
-- complete rrirp_aif interface
generic (
RB_ADDR : slv16 := (others=>'0'));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end entity rbd_bram;
architecture syn of rbd_bram is
constant rbaddr_cntl : slv1 := "0"; -- cntl address offset
constant rbaddr_data : slv1 := "1"; -- data address offset
subtype cntl_rbf_nbusy is integer range 15 downto 10;
subtype cntl_rbf_addr is integer range 9 downto 0;
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
addr : slv10; -- addr register
nbusy : slv6; -- nbusy setting
cntbusy : slv6; -- busy timer
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- addr
(others=>'0'), -- nbusy
(others=>'0') -- cntbusy
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM_DO : slv16 := (others=>'0');
begin
BRAM : ram_1swsr_wfirst_gen
generic map (
AWIDTH => 10,
DWIDTH => 16)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.addr,
DI => RB_MREQ.din,
DO => BRAM_DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, BRAM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable isbusy : slbit := '0';
variable ibramen : slbit := '0';
variable ibramwe : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
isbusy := '0';
if unsigned(r.cntbusy) /= 0 then
isbusy := '1';
end if;
ibramen := '0';
ibramwe := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 1)=RB_ADDR(15 downto 1) then
n.rbsel := '1';
ibramen := '1';
if irbena = '0' then -- addr valid and selected, but no req
n.cntbusy := r.nbusy; -- preset busy timer
end if;
end if;
-- rbus transactions
if r.rbsel = '1' then
if irbena = '1' then -- if request active
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
end if;
end if;
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(0 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
n.addr := RB_MREQ.din(cntl_rbf_addr);
end if;
when rbaddr_data =>
irb_busy := irbena and isbusy;
if isbusy = '0' then
if RB_MREQ.we = '1' then
ibramwe := '1';
end if;
if irbena = '1' then
n.addr := slv(unsigned(r.addr) + 1);
end if;
end if;
when others => null;
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(0 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_nbusy) := r.nbusy;
irb_dout(cntl_rbf_addr) := r.addr;
when rbaddr_data =>
irb_dout := BRAM_DO;
when others => null;
end case;
end if;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= '0';
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
| gpl-3.0 | 6e2c4d8bc9bf1792949d0041ef8f7c94 | 0.498292 | 3.515723 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd | 1 | 4,446 | -- $Id: s6_cmt_sfs_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s6_cmt_sfs - sim
-- Description: Spartan-6 CMT for simple frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1065 1.1 use sfs_gsim_core
-- 2016-08-18 799 1.0.1 remove 'assert false' from report statements
-- 2013-10-06 538 1.0 Initial version (derived from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s6_cmt_sfs;
architecture sim of s6_cmt_sfs is
begin
proc_init : process
-- currently frequency limits taken from Spartan-6 speed grade -2
constant f_vcomin_pll : integer := 400;
constant f_vcomax_pll : integer := 1000;
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 375;
variable t_vco : Delay_length := 0 ns;
variable t_vcomin : Delay_length := 0 ns;
variable t_vcomax : Delay_length := 0 ns;
variable t_pd : Delay_length := 0 ns;
variable t_pdmin : Delay_length := 0 ns;
variable t_pdmax : Delay_length := 0 ns;
begin
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "DCM") then
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
end if;
if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then
if GEN_TYPE = "PLL" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>52 or
VCO_MULTIPLY<1 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:52 VCO_MULTIPLY in 1:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
-- now check whether VCO and PD frequency is in range
t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
t_vco := t_pd / VCO_MULTIPLY;
if t_vco<t_vcomin or t_vco>t_vcomax then
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
report "assert(PD frequency out of range)"
severity failure;
end if;
end if; -- GEN_TYPE = "PLL"
if GEN_TYPE = "DCM" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>32 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>32 or
OUT_DIVIDE/=1
then
report
"assert(VCO_DIVIDE in 1:32 VCO_MULTIPLY in 2:32 OUT_DIVIDE=1)"
severity failure;
end if;
end if; -- GEN_TYPE = "MMCM"
end if; -- one factor /= 1
wait;
end process proc_init;
-- generate clock
SFS: sfs_gsim_core
generic map (
VCO_DIVIDE => VCO_DIVIDE,
VCO_MULTIPLY => VCO_MULTIPLY,
OUT_DIVIDE => OUT_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end sim;
| gpl-3.0 | ce66dfacd7cb14f9d25484e38aa533fd | 0.552182 | 3.605839 | false | false | false | false |
wfjm/w11 | rtl/bplib/issi/is61wv5128bll.vhd | 1 | 3,388 | -- $Id: is61wv5128bll.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: is61wv5128bll - sim
-- Description: ISSI IS61WV5128BLL SRAM model
-- Currently a truely minimalistic functional model, without
-- any timing checks. It assumes, that addr/data is stable at
-- the trailing edge of we.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version (derived from is61lv25616al)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Mode WE_N CE_N OE_N D
-- Not selected X H X high-Z
-- Output disabled H L H high-Z
-- X L X high-Z
-- Read H L L D_out
-- Write L L X D_in
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity is61wv5128bll is -- ISSI 61WV5128bll SRAM model
port (
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
ADDR : in slv19; -- address lines
DATA : inout slv8 -- data lines
);
end is61wv5128bll;
architecture sim of is61wv5128bll is
constant T_rc : Delay_length := 10 ns; -- read cycle time (min)
constant T_aa : Delay_length := 10 ns; -- address access time (max)
constant T_oha : Delay_length := 2 ns; -- output hold time (min)
constant T_ace : Delay_length := 10 ns; -- ce access time (max)
constant T_doe : Delay_length :=4.5 ns; -- oe access time (max)
constant T_hzoe : Delay_length := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : Delay_length := 0 ns; -- oe to low-Z output (min)
constant T_hzce : Delay_length := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : Delay_length := 3 ns; -- ce to low-Z output (min)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal WE_EFF : slbit := '0';
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
WE_EFF <= CE and WE;
proc_sram: process (CE, OE, WE, WE_EFF, ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
if falling_edge(WE_EFF) then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
end if;
if CE='1' and OE='1' and WE='0' then -- output driver
DATA <= ram(to_integer(unsigned(ADDR)));
else
DATA <= (others=>'Z');
end if;
end process proc_sram;
end sim;
| gpl-3.0 | 16512113aa3968aa85f1e5e88d06c0d3 | 0.522137 | 3.457143 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd | 1 | 1,506 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | c87088ff0b92c1a00d3201caaf0b2c45 | 0.545153 | 3.984127 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vhd | 1 | 15,533 | -- $Id: sys_tst_mig_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_mig_arty - syn
-- Description: test of arty ddr and its mig controller
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- cdclib/cdc_pulse
-- bplib/bpgen/bp_rs232_2line_iob
-- rlink/rlink_sp2c
-- tst_mig
-- bplib/arty/migui_arty (generated core)
-- bplib/sysmon/sysmonx_rbus_arty
-- rbus/rbd_usracc
-- rbus/rb_sres_or_3
--
-- Test bench: tb/tb_tst_mig_arty
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1l 4325 4197 415 1 1699
-- 2019-02-02 1108 2018.3 xc7a35t-1l 4323 4537 444 1 1874
-- 2019-02-02 1108 2017.2 xc7a35t-1l 4330 4773 444 1 1774
-- 2019-01-02 1101 2017.2 xc7a35t-1l 4320 4773 462 1 1770
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.0.1 use bufg_unisim
-- 2018-12-26 1094 1.0 Initial version
-- 2018-12-23 1092 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib_arty.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_mig_arty is -- top level
-- implements arty_mig_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_tst_mig_arty;
architecture syn of sys_tst_mig_arty is
signal CLK100_BUF : slbit := '0';
signal XX_CLK : slbit := '0'; -- kept to keep clock setup similar
signal XX_CE_USEC : slbit := '0'; -- to w11a or other 'normal' systems
signal XX_CE_MSEC : slbit := '0'; --
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG
signal MEM_RESET : slbit := '0';
signal MEM_RESET_RRI : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_CMD : slv3 := (others=>'0');
signal APP_EN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_WREN : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_WDF_RDY : slbit := '0';
signal APP_SR_REQ : slbit := '0';
signal APP_REF_REQ : slbit := '0';
signal APP_ZQ_REQ : slbit := '0';
signal APP_SR_ACTIVE : slbit := '0';
signal APP_REF_ACK : slbit := '0';
signal APP_ZQ_ACK : slbit := '0';
signal MIG_UI_CLK : slbit := '0';
signal MIG_UI_CLK_SYNC_RST : slbit := '0';
signal MIG_INIT_CALIB_COMPLETE : slbit := '0';
signal MIG_SYS_RST : slbit := '0';
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal R_DIMCNT : slv2 := (others=>'0');
signal R_DIMFLG : slbit := '0';
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0105"; -- tst_mig
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 10, -- vco 1000 MHz
CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => XX_CLK,
CE0_USEC => XX_CE_USEC,
CE0_MSEC => XX_CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
-- Note: CLK0 is generated as in 'normal' systems to keep PPL/MMCM setup
-- as similar as possible. The CE_USEC and CE_MSEC pulses are forwarded
-- from the 80 MHz CLK0 domain to the 83.333 MHz MIG UI_CLK domain
CDC_CEUSEC : cdc_pulse -- provide CLK side CE_USEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_USEC,
BUSY => open,
POUT => CE_USEC
);
CDC_CEMSEC : cdc_pulse -- provide CLK side CE_MSEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_MSEC,
BUSY => open,
POUT => CE_MSEC
);
CDC_CLKMIG_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLKMIG,
DI => LOCKED,
DO => LOCKED_CLKMIG
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 8, -- 256 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => '0', -- FIXME: no RESET
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_mig
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
MAWIDTH => mig_mawidth,
MWIDTH => mig_mwidth)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
MIG_UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
MIG_INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
MIG_DEVICE_TEMP_I => XADC_TEMP
);
MIG_CTL: migui_arty -- MIG iface -----------------
port map (
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
UI_CLK => CLK,
UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => XADC_TEMP,
SYS_RST => MIG_SYS_RST
);
MIG_SYS_RST <= (not LOCKED_CLKMIG) or I_BTN(3); -- provisional !
SMRB: sysmonx_rbus_arty
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
proc_dim: process (CLKMIG)
begin
if rising_edge(CLKMIG) then
R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1);
if unsigned(R_DIMCNT) = 0 then
R_DIMFLG <= '1';
else
R_DIMFLG <= '0';
end if;
end if;
end process proc_dim;
RB_LAM(0) <= RB_LAM_TST;
O_LED(1) <= SER_MONI.txact;
O_LED(0) <= SER_MONI.rxact;
-- red LED for serious error conditions
O_RGBLED0(0) <= R_DIMFLG and (I_BTN(0) or not LOCKED);
O_RGBLED1(0) <= R_DIMFLG and (I_BTN(0));
O_RGBLED2(0) <= R_DIMFLG and (I_BTN(0) or MIG_UI_CLK_SYNC_RST);
O_RGBLED3(0) <= R_DIMFLG and (I_BTN(0) or not MIG_INIT_CALIB_COMPLETE);
-- green LED for activity
O_RGBLED0(1) <= R_DIMFLG and (I_BTN(1));
O_RGBLED1(1) <= R_DIMFLG and (I_BTN(1));
O_RGBLED2(1) <= R_DIMFLG and (I_BTN(1) or not APP_RDY);
O_RGBLED3(1) <= R_DIMFLG and (I_BTN(1) or not APP_WDF_RDY);
-- blue LED currently unused
O_RGBLED0(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED1(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED2(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED3(2) <= R_DIMFLG and (I_BTN(2));
end syn;
| gpl-3.0 | dd9af6db7be70558ab0d18f4e2ed48da | 0.495075 | 3.154549 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys2/sys_conf2.vhd | 1 | 1,130 | -- $Id: sys_conf2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 60; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
end package sys_conf;
| gpl-3.0 | aa3ef07a4da0a3d2e81eb6fa0139cfeb | 0.582301 | 3.587302 | false | false | false | false |
wfjm/w11 | rtl/bplib/artys7/tb/sys_conf_sim.vhd | 1 | 1,714 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_artys7_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-05 1028 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | fabc8a83352e633a4d3474e595bc920e | 0.61902 | 3.623679 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys2/tb/sys_conf_sim.vhd | 1 | 1,738 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_* (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays
-- 2011-11-27 433 1.1.2 use /1*1 to skip dcm, _ssim fails with dcm
-- 2010-11-22 339 1.1.1 add memctl related constants; now clksys=60 MHz
-- 2010-11-13 338 1.1 add dcm related constants
-- 2010-05-25 294 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1; -- skip dcm for sim !!
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | cf0f7cc428fea5dccd9c0c0dc76577ff | 0.608746 | 3.462151 | false | false | false | false |
jasonpeng/cg3207-proj | IF_ID_BUFF.vhd | 1 | 1,354 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:23:47 10/31/2013
-- Design Name:
-- Module Name: if_id_reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------library IEEE;
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity IF_ID_REG is
port(
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
ID_STALL: in std_logic;
IF_ID_FLUSH: in std_logic;
PC_ADDR_IN: in STD_LOGIC_VECTOR(31 downto 0);
INST_REG_IN : in STD_LOGIC_VECTOR(31 downto 0);
PC_ADDR_OUT : out STD_LOGIC_VECTOR(31 downto 0);
INST_REG_OUT : out STD_LOGIC_VECTOR(31 downto 0)
);
end IF_ID_REG;
architecture IF_ID_REG_ARC of IF_ID_REG is
begin
process(Clk,Reset)
begin
if RESET = '1' then
INST_REG_OUT <= (others => '0');
PC_ADDR_OUT <= (others => '0');
elsif (Clk'event and Clk ='1') then
if IF_ID_FLUSH = '1' then
INST_REG_OUT <= (others =>'0');
PC_ADDR_OUT <= (others =>'0');
else
PC_ADDR_OUT <= PC_ADDR_IN;
INST_REG_OUT <= INST_REG_IN;
end if;
end if;
end process;
end IF_ID_REG_ARC; | gpl-2.0 | d229715823cbd1f88f95d1028f0d1e45 | 0.536928 | 3.091324 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_aunit.vhd | 1 | 7,920 | -- $Id: pdp11_aunit.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_aunit - syn
-- Description: pdp11: arithmetic unit for data (aunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.36
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 1.1.2 fix for ghdl V0.36 -Whide warnings
-- 2014-08-10 581 1.1.1 use c_cc_f_*
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
-- arithmetic unit for data, usage:
-- ADD: SRC + DST + 0 (dst+src)
-- SUB: ~SRC + DST + 1 (dst-src)
-- ADC: 0 + DST + CI (dst+ci)
-- SBC: ~0 + DST + ~CI (dst-ci)
-- CMP: SRC + ~DST + 1 (src-dst)
-- COM: 0 + ~DST + 0 (~dst)
-- NEG: 0 + ~DST + 1 (-dst)
-- INC: 0 + DST + 1 (dst+1)
-- DEC: ~0 + DST + 0 (dst-1)
-- CLR: 0 + 0 + 0 (0)
-- SOB: SRC + ~0 + 0 (src-1)
entity pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_aunit;
architecture syn of pdp11_aunit is
-- --------------------------------------
begin
process (DSRC, DDST, CI, CIMOD, CC1OP, CCMODE, SRCMOD, DSTMOD, BYTOP)
variable msrc : slv16 := (others=>'0'); -- effective src data
variable mdst : slv16 := (others=>'0'); -- effective dst data
variable mci : slbit := '0'; -- effective ci
variable sum : slv16 := (others=>'0'); -- sum
variable co8 : slbit := '0'; -- co 8 bit
variable co16 : slbit := '0'; -- co 16 bit
variable nno : slbit := '0'; -- local no
variable nzo : slbit := '0'; -- local zo
variable nvo : slbit := '0'; -- local vo
variable nco : slbit := '0'; -- local co
variable src_msb : slbit := '0'; -- msb from src (bit 15 or 7)
variable dst_msb : slbit := '0'; -- msb from dst (bit 15 or 7)
variable sum_msb : slbit := '0'; -- msb from sum (bit 15 or 7)
alias NO : slbit is CCOUT(c_cc_f_n);
alias ZO : slbit is CCOUT(c_cc_f_z);
alias VO : slbit is CCOUT(c_cc_f_v);
alias CO : slbit is CCOUT(c_cc_f_c);
-- procedure do_add8_ci_co: 8 bit adder with carry in and carry out
-- implemented following the recommended pattern for XST ISE V8.1
procedure do_add8_ci_co (
variable pa : in slv8; -- input a
variable pb : in slv8; -- input b
variable pci : in slbit; -- carry in
variable psum : out slv8; -- sum out
variable pco : out slbit -- carry out
) is
variable tmp: slv9;
begin
tmp := conv_std_logic_vector((conv_integer(pa) + conv_integer(pb) +
conv_integer(pci)),9);
psum := tmp(7 downto 0);
pco := tmp(8);
end procedure do_add8_ci_co;
begin
case SRCMOD is
when c_aunit_mod_pass => msrc := DSRC;
when c_aunit_mod_inv => msrc := not DSRC;
when c_aunit_mod_zero => msrc := (others=>'0');
when c_aunit_mod_one => msrc := (others=>'1');
when others => null;
end case;
case DSTMOD is
when c_aunit_mod_pass => mdst := DDST;
when c_aunit_mod_inv => mdst := not DDST;
when c_aunit_mod_zero => mdst := (others=>'0');
when c_aunit_mod_one => mdst := (others=>'1');
when others => null;
end case;
case CIMOD is
when c_aunit_mod_pass => mci := CI;
when c_aunit_mod_inv => mci := not CI;
when c_aunit_mod_zero => mci := '0';
when c_aunit_mod_one => mci := '1';
when others => null;
end case;
do_add8_ci_co(msrc(7 downto 0), mdst(7 downto 0), mci,
sum(7 downto 0), co8);
do_add8_ci_co(msrc(15 downto 8), mdst(15 downto 8), co8,
sum(15 downto 8), co16);
DOUT <= sum;
-- V ('overflow) bit set if
-- ADD : both operants of same sign but has result opposite sign
-- SUB : both operants of opposide sign and sign source equals sign result
-- CMP : both operants of opposide sign and sign dest. equals sign result
nno := '0';
nzo := '0';
nvo := '0';
nco := '0';
if BYTOP = '1' then
nno := sum(7);
if unsigned(sum(7 downto 0)) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co8;
src_msb := DSRC(7);
dst_msb := DDST(7);
sum_msb := sum(7);
else
nno := sum(15);
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co16;
src_msb := DSRC(15);
dst_msb := DDST(15);
sum_msb := sum(15);
end if;
-- the logic for 2 operand V+C is ugly. It is reverse engineered from
-- the MOD's the operation type.
if CC1OP = '0' then -- 2 operand cases
if unsigned(CIMOD) = unsigned(c_aunit_mod_zero) then -- case ADD
nvo := not(src_msb xor dst_msb) and (src_msb xor sum_msb);
else
if unsigned(SRCMOD) = unsigned(c_aunit_mod_inv) then -- case SUB
nvo := (src_msb xor dst_msb) and not (src_msb xor sum_msb);
else -- case CMP
nvo := (src_msb xor dst_msb) and not (dst_msb xor sum_msb);
end if;
nco := not nco; -- invert C for SUB and CMP
end if;
else -- 1 operand cases
case CCMODE is
when c_aunit_ccmode_clr|c_aunit_ccmode_tst =>
nvo := '0'; -- force v=0 for tst and clr
nco := '0'; -- force c=0 for tst and clr
when c_aunit_ccmode_com =>
nvo := '0'; -- force v=0 for com
nco := '1'; -- force c=1 for com
when c_aunit_ccmode_inc =>
nvo := sum_msb and not dst_msb;
nco := CI; -- C not affected for INC
when c_aunit_ccmode_dec =>
nvo := not sum_msb and dst_msb;
nco := CI; -- C not affected for DEC
when c_aunit_ccmode_neg =>
nvo := sum_msb and dst_msb;
nco := not nzo;
when c_aunit_ccmode_adc =>
nvo := sum_msb and not dst_msb;
when c_aunit_ccmode_sbc =>
nvo := not sum_msb and dst_msb;
nco := not nco;
when others => null;
end case;
end if;
NO <= nno;
ZO <= nzo;
VO <= nvo;
CO <= nco;
end process;
end syn;
| gpl-3.0 | ddd69f6864be046614c3d912006a8798 | 0.477778 | 3.537293 | false | false | false | false |
wfjm/w11 | rtl/vlib/comlib/byte2cdata.vhd | 1 | 4,078 | -- $Id: byte2cdata.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: byte2cdata - syn
-- Description: Byte stream to 9 bit comma,data converter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-10-17 596 2.0 re-write, commas now 2 byte sequences
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
entity byte2cdata is -- byte stream -> 9bit comma,data
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data
ENA : in slbit; -- input data enable
ERR : in slbit; -- input data error
BUSY : out slbit; -- input data busy
DO : out slv9; -- output data; bit 8 = comma flag
VAL : out slbit; -- output data valid
HOLD : in slbit -- output data hold
);
end byte2cdata;
architecture syn of byte2cdata is
type regs_type is record
data : slv9; -- data
dataval : slbit; -- data valid
edpend : slbit; -- edata pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- data
'0','0' -- dataval,edpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, DI, ENA, ERR, HOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idata : slv9 := (others=>'0');
variable iesc : slbit := '0';
variable ibusy : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
-- data path logic
idata := '1' & "00000" & "100"; -- clobber
iesc := '0';
if r.edpend = '1' then
if DI(c_cdata_edf_pref) = c_cdata_ed_pref and
(not DI(c_cdata_edf_eci)) = DI(c_cdata_edf_ec) then
case DI(c_cdata_edf_ec) is
when c_cdata_ec_xon =>
idata := '0' & c_cdata_xon;
when c_cdata_ec_xoff =>
idata := '0' & c_cdata_xoff;
when c_cdata_ec_fill =>
idata := '0' & c_cdata_fill;
when c_cdata_ec_esc =>
idata := '0' & c_cdata_escape;
when others =>
idata := '1' & "00000" & DI(c_cdata_edf_ec);
end case;
end if;
else
idata := '0' & DI;
if DI = c_cdata_escape then
iesc := '1';
end if;
end if;
-- control path logic
ibusy := '1';
if HOLD = '0' then
ibusy := '0';
n.dataval := '0';
n.data := idata;
if ENA = '1' then
if r.edpend = '0' then
if iesc = '0' then
n.dataval := '1';
else
n.edpend := '1';
end if;
else
n.dataval := '1';
n.edpend := '0';
end if;
elsif ERR = '1' then
n.dataval := '1';
end if;
end if;
N_REGS <= n;
DO <= r.data;
VAL <= r.dataval;
BUSY <= ibusy;
end process proc_next;
end syn;
| gpl-3.0 | d0c801de0ad5fcf906cd97c7fb23d725 | 0.474988 | 3.555362 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_mmu_padr.vhd | 1 | 8,689 | -- $Id: pdp11_mmu_padr.vhd 1279 2022-08-14 08:02:21Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu_sadr - syn
-- Description: pdp11: mmu PAR/PDR register set
--
-- Dependencies: memlib/ram_1swar_gen
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-08-13 1279 1.3.4 ssr->mmr rename
-- 2011-11-18 427 1.3.3 now numeric_std clean
-- 2010-12-30 351 1.3.2 BUGFIX: fix sensitivity list of proc_eaddr
-- 2010-10-23 335 1.3.1 change proc_eaddr logic, shorten logic path
-- 2010-10-17 333 1.3 use ibus V2 interface
-- 2008-08-22 161 1.2.2 rename ubf_ -> ibf_; use iblib
-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2008-01-01 109 1.2 renamed from _mmu_regfile.
-- redesign of _mmu register file, use one large dram.
-- logic from _mmu_regfile, interface from _mmu_regset
-- 2007-12-30 108 1.1.1 use ubf_byte[01]; move SADR memory address mux here
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu_padr is -- mmu PAR/PDR register set
port (
CLK : in slbit; -- clock
MODE : in slv2; -- mode
APN : in slv4; -- augmented page number (1+3 bit)
AIB_WE : in slbit; -- update AIB
AIB_SETA : in slbit; -- set access AIB
AIB_SETW : in slbit; -- set write AIB
PARPDR : out parpdr_type; -- combined PAR/PDR
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_mmu_padr;
architecture syn of pdp11_mmu_padr is
-- bit 1 111 1
-- bit 5 432 109 876 543 210
--
-- kmdr 172300 -> 1 111 010 011 000 000
-- kmar 172340 -> 1 111 010 011 100 000
-- smdr 172200 -> 1 111 010 010 000 000
-- smar 172240 -> 1 111 010 010 100 000
-- umdr 177600 -> 1 111 111 110 000 000
-- umar 177640 -> 1 111 111 110 100 000
--
-- mode => (addr(8), not addr(6)) [Note: km "00" sm "01" um "11"]
constant ibaddr_kmdar : slv16 := slv(to_unsigned(8#172300#,16));
constant ibaddr_smdar : slv16 := slv(to_unsigned(8#172200#,16));
constant ibaddr_umdar : slv16 := slv(to_unsigned(8#177600#,16));
subtype pdr_ibf_plf is integer range 14 downto 8;
subtype pdr_ibf_aib is integer range 7 downto 6;
subtype pdr_ibf_acf is integer range 3 downto 0;
signal PADR_ADDR : slv6 := (others=>'0'); -- address (from mmu or ibus)
signal PAR_HIGH_WE : slbit := '0'; -- write enables
signal PAR_LOW_WE : slbit := '0'; -- ...
signal PDR_PLF_WE : slbit := '0'; -- ...
signal PDR_AIB_WE : slbit := '0'; -- ...
signal PDR_LOW_WE : slbit := '0'; -- ...
signal R_IBSEL_DR : slbit := '0'; -- DR's selected from ibus
signal R_IBSEL_AR : slbit := '0'; -- AR's selected from ibus
signal PAF : slv16 := (others=>'0'); -- current PAF
signal PLF : slv7 := (others=>'0'); -- current PLF
signal AIB : slv2 := "00"; -- current AIB flags
signal N_AIB : slv2 := "00"; -- next AIB flags
signal ED_ACF : slv4 := "0000"; -- current ED & ACF
begin
PAR_HIGH : ram_1swar_gen
generic map (
AWIDTH => 6,
DWIDTH => 8)
port map (
CLK => CLK,
WE => PAR_HIGH_WE,
ADDR => PADR_ADDR,
DI => IB_MREQ.din(ibf_byte1),
DO => PAF(ibf_byte1));
PAR_LOW : ram_1swar_gen
generic map (
AWIDTH => 6,
DWIDTH => 8)
port map (
CLK => CLK,
WE => PAR_LOW_WE,
ADDR => PADR_ADDR,
DI => IB_MREQ.din(ibf_byte0),
DO => PAF(ibf_byte0));
PDR_PLF : ram_1swar_gen
generic map (
AWIDTH => 6,
DWIDTH => 7)
port map (
CLK => CLK,
WE => PDR_PLF_WE,
ADDR => PADR_ADDR,
DI => IB_MREQ.din(pdr_ibf_plf),
DO => PLF);
PDR_AIB : ram_1swar_gen
generic map (
AWIDTH => 6,
DWIDTH => 2)
port map (
CLK => CLK,
WE => PDR_AIB_WE,
ADDR => PADR_ADDR,
DI => N_AIB,
DO => AIB);
PDR_LOW : ram_1swar_gen
generic map (
AWIDTH => 6,
DWIDTH => 4)
port map (
CLK => CLK,
WE => PDR_LOW_WE,
ADDR => PADR_ADDR,
DI => IB_MREQ.din(pdr_ibf_acf),
DO => ED_ACF);
-- determine IBSEL's and the address for accessing the PADR's
proc_ibsel: process (CLK)
variable ibsel_dr : slbit := '0';
variable ibsel_ar : slbit := '0';
begin
if rising_edge(CLK) then
ibsel_dr := '0';
ibsel_ar := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr(12 downto 6)=ibaddr_kmdar(12 downto 6) or
IB_MREQ.addr(12 downto 6)=ibaddr_smdar(12 downto 6) or
IB_MREQ.addr(12 downto 6)=ibaddr_umdar(12 downto 6) then
if IB_MREQ.addr(5) = '0' then
ibsel_dr := '1';
else
ibsel_ar := '1';
end if;
end if;
end if;
R_IBSEL_DR <= ibsel_dr;
R_IBSEL_AR <= ibsel_ar;
end if;
end process proc_ibsel;
proc_ibres : process (R_IBSEL_DR, R_IBSEL_AR, IB_MREQ, PAF, PLF, AIB, ED_ACF)
variable parout : slv16 := (others=>'0'); -- IB par out
variable pdrout : slv16 := (others=>'0'); -- IB pdr out
begin
parout := (others=>'0');
if R_IBSEL_AR = '1' then
parout := PAF;
end if;
pdrout := (others=>'0');
if R_IBSEL_DR = '1' then
pdrout(pdr_ibf_plf) := PLF;
pdrout(pdr_ibf_aib) := AIB;
pdrout(pdr_ibf_acf) := ED_ACF;
end if;
IB_SRES.dout <= parout or pdrout;
IB_SRES.ack <= (R_IBSEL_DR or R_IBSEL_AR) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
-- the eaddr select should be done as early as possible, it is in the
-- mmu paadr logic path. Currently it's derived from 4 flops. If that's
-- to slow just use IB_MREQ.we or IB_MREQ.we, that should be sufficient
-- and reduce the eaddr mux to a 4-input LUT. Last resort is a 2 cycle ibus
-- access with a state flop marking the 2nd cycle of a re/we transaction.
proc_eaddr: process (IB_MREQ, MODE, APN, R_IBSEL_DR, R_IBSEL_AR)
variable eaddr : slv6 := (others=>'0');
variable idr : slbit := '0';
variable iar : slbit := '0';
begin
eaddr := MODE & APN;
if (R_IBSEL_DR='1' or R_IBSEL_AR='1') and
(IB_MREQ.re='1' or IB_MREQ.we='1') then
eaddr(5) := IB_MREQ.addr(8);
eaddr(4) := not IB_MREQ.addr(6);
eaddr(3 downto 0) := IB_MREQ.addr(4 downto 1);
end if;
PADR_ADDR <= eaddr;
end process proc_eaddr;
proc_comb : process (R_IBSEL_AR, R_IBSEL_DR, IB_MREQ, AIB_WE,
AIB_SETA, AIB_SETW,
PAF, PLF, AIB, ED_ACF)
begin
N_AIB <= "00";
PAR_HIGH_WE <= '0';
PAR_LOW_WE <= '0';
PDR_PLF_WE <= '0';
PDR_AIB_WE <= '0';
PDR_LOW_WE <= '0';
if IB_MREQ.we = '1' then
if R_IBSEL_AR = '1' then
if IB_MREQ.be1 = '1' then
PAR_HIGH_WE <= '1';
end if;
if IB_MREQ.be0 = '1' then
PAR_LOW_WE <= '1';
end if;
end if;
if R_IBSEL_DR = '1' then
if IB_MREQ.be1 = '1' then
PDR_PLF_WE <= '1';
end if;
if IB_MREQ.be0 = '1' then
PDR_LOW_WE <= '1';
end if;
end if;
if (R_IBSEL_AR or R_IBSEL_DR)='1' then
N_AIB <= "00";
PDR_AIB_WE <= '1';
end if;
end if;
if AIB_WE = '1' then
N_AIB(0) <= AIB(0) or AIB_SETW;
N_AIB(1) <= AIB(1) or AIB_SETA;
PDR_AIB_WE <= '1';
end if;
PARPDR.paf <= PAF;
PARPDR.plf <= PLF;
PARPDR.ed <= ED_ACF(3);
PARPDR.acf <= ED_ACF(2 downto 0);
end process proc_comb;
end syn;
| gpl-3.0 | a04debd8ce7e9f2cdf14aee450481957 | 0.518817 | 3.151614 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rblib.vhd | 1 | 8,105 | -- $Id: rblib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: rblib
-- Description: Definitions for rbus interface and bus entities
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 4.1 add rb_sres_6
-- 2014-09-14 593 4.0 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports
-- 2010-12-26 349 3.0.2 add rb_sel
-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
-- 2010-12-04 343 3.0 extracted from rrilib and rritblib;
-- rbus V3 interface: use aval,re,we
-- ... rrilib history removed ...
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package rblib is
type rb_mreq_type is record -- rbus - master request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
init : slbit; -- init
addr : slv16; -- address
din : slv16; -- data (input to slave)
end record rb_mreq_type;
constant rb_mreq_init : rb_mreq_type :=
('0','0','0','0', -- aval, re, we, init
(others=>'0'), -- addr
(others=>'0')); -- din
type rb_sres_type is record -- rbus - slave response
ack : slbit; -- acknowledge
busy : slbit; -- busy
err : slbit; -- error
dout : slv16; -- data (output from slave)
end record rb_sres_type;
constant rb_sres_init : rb_sres_type :=
('0','0','0', -- ack, busy, err
(others=>'0')); -- dout
component rb_sel is -- rbus address select logic
generic (
RB_ADDR : slv16; -- rbus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus request
SEL : out slbit -- select state bit
);
end component;
component rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_4 is -- rbus result or, 4 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_6 is -- rbus result or, 6 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5
RB_SRES_6 : in rb_sres_type := rb_sres_init; -- rb_sres input 6
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rbus_aif is -- rbus, abstract interface
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end component;
component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : in slv(DWIDTH-1 downto 0); -- data
RB_SRES : out rb_sres_type -- rbus response
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component rb_sres_or_mon is -- rbus result or monitor
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5
RB_SRES_6 : in rb_sres_type := rb_sres_init -- rb_sres input 6
);
end component;
-- simbus sb_cntl field usage for rbus
constant sbcntl_sbf_rbmon : integer := 13;
component rb_mon is -- rbus monitor
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end component;
component rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end component;
end package rblib;
| gpl-3.0 | 770133c23d069a9b7e2a9487b7e22467 | 0.504133 | 3.530052 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01500_bad.vhd | 1 | 3,584 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01500_bad.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of custom type name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01500_bad is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_Addr : in std_logic_vector(1 downto 0); -- Address to read from or write to
i_Rd : in std_logic; -- Read signal
i_Wr : in std_logic; -- Write signal
i_Data : in std_logic; -- Incoming data to write
o_Data : out std_logic -- Data read
);
end CNE_01500_bad;
--CODE
architecture Behavioral of CNE_01500_bad is
type reg is array (0 to 3) of std_logic; -- Array for signal registration
signal D : reg; -- Actual signal
signal Data : std_logic; -- Module output
begin
-- Describes a simple Register bank with Read and Write signals
P_Register_Bank:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D <= (others => '0');
Data <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Rd='1') then
-- Read memory
Data <= D(to_integer(unsigned(i_Addr)));
elsif (i_Wr='1') then
-- Write memory
D(to_integer(unsigned(i_Addr))) <= i_Data;
end if;
end if;
end process;
o_Data <= Data;
end Behavioral;
--CODE | gpl-3.0 | 4bce5b28603f17660770acfb5de69cd1 | 0.472377 | 4.60077 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/spi_master/spi_master_tb.vhd | 1 | 857 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
entity tb is
end tb;
architecture tb of tb is
signal clock, reset, we, valid, spi_clk, spi_mosi, spi_miso: std_logic := '0';
signal input, output: std_logic_vector(7 downto 0);
begin
reset <= '0', '1' after 5 ns, '0' after 500 ns;
process --25Mhz system clock
begin
clock <= not clock;
wait for 20 ns;
clock <= not clock;
wait for 20 ns;
end process;
we <= '0', '1' after 1000 ns, '0' after 1100 ns;
spi_miso <= '1';
input <= x"a1";
spi_core: entity work.spi_master
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clock,
rst_i => reset,
data_i => input,
data_o => output,
data_valid_o => valid,
wren_i => we,
spi_clk_o => spi_clk,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso
);
end tb;
| gpl-2.0 | 26139d021c2d23533418f0abaebd30c1 | 0.618436 | 2.558209 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_psr.vhd | 1 | 5,546 | -- $Id: pdp11_psr.vhd 1287 2022-08-27 09:40:43Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_psr - syn
-- Description: pdp11: processor status word register
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-08-27 1287 1.2.3 handle pm protection like cm, remove or'ing cm
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_psr;
architecture syn of pdp11_psr is
constant ibaddr_psr : slv16 := slv(to_unsigned(8#177776#,16));
signal IBSEL_PSR : slbit := '0';
signal R_PSW : psw_type := psw_init; -- ps register
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_psr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_PSR
);
proc_ibres: process (IBSEL_PSR, IB_MREQ, R_PSW)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_PSR = '1' then
idout(psw_ibf_cmode) := R_PSW.cmode;
idout(psw_ibf_pmode) := R_PSW.pmode;
idout(psw_ibf_rset) := R_PSW.rset;
idout(psw_ibf_pri) := R_PSW.pri;
idout(psw_ibf_tflag) := R_PSW.tflag;
idout(psw_ibf_cc) := R_PSW.cc;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_PSR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_psw : process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_PSW <= psw_init;
else
if CCWE = '1' then
R_PSW.cc <= CCIN;
end if;
if WE = '1' then
case FUNC is
when c_psr_func_wspl => -- wspl
R_PSW.pri <= DIN(2 downto 0);
when c_psr_func_wcc => -- wcc
if DIN(4) = '1' then -- set cc opcodes
R_PSW.cc <= R_PSW.cc or DIN(3 downto 0);
else -- clear cc opcodes
R_PSW.cc <= R_PSW.cc and not DIN(3 downto 0);
end if;
when c_psr_func_wint => -- wint (interupt handling)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.cmode; -- save current mode
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wrti => -- wrti (rti/rtt in non-kernel mode)
R_PSW.cmode <= R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.pmode or DIN(psw_ibf_pmode);
R_PSW.rset <= R_PSW.rset or DIN(psw_ibf_rset);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wall => -- wall (rti/rtt kernel mode)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= DIN(psw_ibf_pmode);
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
when others => null;
end case;
end if;
end if;
if IBSEL_PSR='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_PSW.cmode <= IB_MREQ.din(psw_ibf_cmode);
R_PSW.pmode <= IB_MREQ.din(psw_ibf_pmode);
R_PSW.rset <= IB_MREQ.din(psw_ibf_rset);
end if;
if IB_MREQ.be0 = '1' then
R_PSW.pri <= IB_MREQ.din(psw_ibf_pri);
R_PSW.cc <= IB_MREQ.din(psw_ibf_cc);
end if;
end if;
end if;
end process proc_psw;
PSW <= R_PSW;
end syn;
| gpl-3.0 | 941cc8d7174ee3c412d5558d78cdf357 | 0.486657 | 3.297265 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_1swar_gen_unisim.vhd | 1 | 3,071 | -- $Id: ram_1swar_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_gen_unisim - syn
-- Description: Single-Port RAM with with one synchronous write and one
-- asynchronius read port (as distributed RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0.1 use shorter label names
-- 2008-03-02 122 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swar_gen;
architecture syn of ram_1swar_gen is
begin
assert AWIDTH>=4 and AWIDTH<=6
report "assert(AWIDTH>=4 and AWIDTH<=6): only 4..6 bit AWIDTH supported"
severity failure;
AW_4: if AWIDTH = 4 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM16X1S
generic map (
INIT => X"0000")
port map (
O => DO(i),
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
D => DI(i),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_4;
AW_5: if AWIDTH = 5 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM32X1S
generic map (
INIT => X"00000000")
port map (
O => DO(i),
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
A4 => ADDR(4),
D => DI(i),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_5;
AW_6: if AWIDTH = 6 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM64X1S
generic map (
INIT => X"0000000000000000")
port map (
O => DO(i),
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
A4 => ADDR(4),
A5 => ADDR(5),
D => DI(i),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_6;
end syn;
| gpl-3.0 | 1177b8477d154ce0560221edf5610435 | 0.4803 | 3.600234 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vhd | 1 | 13,837 | -- $Id: sys_tst_sram_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_arty - syn
-- Description: test of arty ddr and its mig controller
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_2line_iob
-- rlink/rlink_sp2c
-- tst_sram
-- bplib/arty/sramif_mig_arty
-- bplib/bpgen/sn_humanio_eum_rbus
-- bplib/sysmon/sysmonx_rbus_arty
-- rbus/rbd_usracc
-- rbus/rb_sres_or_4
--
-- Test bench: tb/tb_tst_sram_arty
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1l 4648 4594 611 5 1849
-- 2019-02-02 1108 2018.3 xc7a35t-1l 4648 4968 644 5 1983
-- 2019-02-02 1108 2017.2 xc7a35t-1l 4643 5334 644 5 1929
-- 2019-01-02 1101 2017.2 xc7a35t-1l 4643 5334 644 5 1929
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.0.1 use bufg_unisim
-- 2018-12-20 1090 1.0 Initial version
-- 2018-11-17 1071 0.1 First draft (derived from sys_tst_sram_c7)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.miglib.all;
use work.miglib_arty.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_arty is -- top level
-- implements arty_sram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_tst_sram_arty;
architecture syn of sys_tst_sram_arty is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
signal GBL_RESET : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_RESET_RRI : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal R_DIMCNT : slv2 := (others=>'0');
signal R_DIMFLG : slbit := '0';
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 10, -- vco 1000 MHz
CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLK_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_CLK
);
GBL_RESET <= not LOCKED_CLK;
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 8, -- 256 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 18)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
MEM_RESET => MEM_RESET_RRI,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR(17 downto 0), -- ?? FIXME ?? allow AWIDTH=20
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM_ADDR(19 downto 18) <= (others=>'0'); --?? FIXME ?? allow AWIDTH=20
MEM_RESET <= not LOCKED_CLK or MEM_RESET_RRI;
MEMCTL: sramif_mig_arty -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLKMIG,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT
);
HIO : sn_humanio_emu_rbus
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3)
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
SMRB: sysmonx_rbus_arty
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
proc_dim: process (CLKMIG)
begin
if rising_edge(CLKMIG) then
R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1);
if unsigned(R_DIMCNT) = 0 then
R_DIMFLG <= '1';
else
R_DIMFLG <= '0';
end if;
end if;
end process proc_dim;
RB_LAM(0) <= RB_LAM_TST;
O_LED(1) <= SER_MONI.txact;
O_LED(0) <= SER_MONI.rxact;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
DSP_DP(7 downto 4) <= "0010";
DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
'0' & SER_MONI.abclkdiv_f;
-- red LED for serious error conditions
O_RGBLED0(0) <= R_DIMFLG and (I_BTN(0) or not LOCKED);
O_RGBLED1(0) <= R_DIMFLG and (I_BTN(0));
O_RGBLED2(0) <= R_DIMFLG and (I_BTN(0) or MIG_MONI.miguirst);
O_RGBLED3(0) <= R_DIMFLG and (I_BTN(0) or MIG_MONI.migcacow);
-- green LED for activity
O_RGBLED0(1) <= R_DIMFLG and (I_BTN(1) or MEM_ACT_R);
O_RGBLED1(1) <= R_DIMFLG and (I_BTN(1) or MEM_ACT_W);
O_RGBLED2(1) <= R_DIMFLG and (I_BTN(1) or (MIG_MONI.migcbusy xor I_BTN(3)));
O_RGBLED3(1) <= R_DIMFLG and (I_BTN(1) or MIG_MONI.migwbusy);
-- blue LED currently unused
O_RGBLED0(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED1(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED2(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED3(2) <= R_DIMFLG and (I_BTN(2));
end syn;
| gpl-3.0 | 810b27b257ab91f112811f16d8be6812 | 0.497001 | 3.103162 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | flipflop.vhd | 1 | 582 | library ieee;
use ieee.std_logic_1164.all;
entity flipflop is
generic(
DATA_WIDTH : natural := 32
);
port(
clk, rst : in std_logic;
D : in std_logic_vector ((DATA_WIDTH-1) downto 0);
Q : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
end flipflop;
architecture rtl of flipflop is
signal Temp: std_logic_vector((DATA_WIDTH-1) downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
Temp <= (others => '0');
elsif (rising_edge(clk))then
Temp <= D;
end if;
end process;
Q <= Temp;
end rtl;
| mit | 9b2208187177ab63083082c3e25a550b | 0.582474 | 2.881188 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/other_sim.vhd | 1 | 7,374 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity other_sim is
port(hi : in std_logic);
end other_sim;
architecture behavioral of other_sim is
component data_stack
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
e0_sel : in STD_LOGIC_VECTOR(1 downto 0);
e1_sel : in STD_LOGIC_VECTOR(1 downto 0);
e2_sel : in STD_LOGIC_VECTOR(1 downto 0);
e0_en : in STD_LOGIC;
e1_en : in STD_LOGIC;
e2_en : in STD_LOGIC;
push : in STD_LOGIC;
pop : in STD_LOGIC;
pop2 : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(31 downto 0);
e0_out : out STD_LOGIC_VECTOR(31 downto 0);
e1_out : out STD_LOGIC_VECTOR(31 downto 0));
end component;
signal clk, rst, e0_en, e1_en, e2_en, push, pop, pop2 : std_logic;
signal e0_sel, e1_sel, e2_sel : std_logic_vector(1 downto 0);
signal data_in, next_data_in, e0_out, e1_out : std_logic_vector(31 downto 0);
type ops_type is (reset, drop, swap, rot, nrot, push_op, dup, rd, nrd, rds, nrds, over, wr_mem);
signal op, next_op: ops_type;
begin
uut : data_stack
port map(
clk => clk,
rst => rst,
e0_sel => e0_sel,
e1_sel => e1_sel,
e2_sel => e2_sel,
e0_en => e0_en,
e1_en => e1_en,
e2_en => e2_en,
push => push,
pop => pop,
pop2 => pop2,
data_in => data_in,
e0_out => e0_out,
e1_out => e1_out
);
ctl : process (clk, rst) is
begin
if rst = '1' then
op <= reset;
data_in <= (others => '0');
elsif rising_edge(clk) then
op <= next_op;
data_in <= next_data_in;
end if;
end process;
ops : process is
begin
next_op <= reset;
next_data_in <= (others => '0');
wait for 100 ns;
next_op <= push_op;
next_data_in <= x"44444444";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"33333333";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"22222222";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"11111111";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"11111111";
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= swap;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= swap;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= over;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= dup;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= rot;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= nrot;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= rot;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"11111111";
wait for 20 ns;
next_op <= rd;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= drop;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"44444444";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"33333333";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"22222222";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"11111111";
wait for 20 ns;
next_op <= nrd;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"33333333";
wait for 20 ns;
next_op <= rot;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= rds;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"22222222";
wait for 20 ns;
next_op <= swap;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= nrds;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"88888888";
wait for 20 ns;
next_op <= push_op;
next_data_in <= x"BBBBBBBB";
wait for 20 ns;
next_op <= wr_mem;
next_data_in <= (others => '0');
wait for 20 ns;
next_op <= reset;
next_data_in <= (others => '0');
wait;
end process;
ctl_async : process (op) is
begin
case op is
when reset =>
e0_sel <= "00";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '0';
e1_en <= '0';
e2_en <= '0';
push <= '0';
pop <= '0';
pop2 <= '0';
when drop =>
e0_sel <= "01";
e1_sel <= "01";
e2_sel <= "01";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when swap =>
e0_sel <= "01";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '1';
e1_en <= '1';
e2_en <= '0';
push <= '0';
pop <= '0';
pop2 <= '0';
when nrot =>
e0_sel <= "01";
e1_sel <= "01";
e2_sel <= "10";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '0';
pop2 <= '0';
when rot =>
e0_sel <= "10";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '0';
pop2 <= '0';
when push_op =>
e0_sel <= "00";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '1';
pop <= '0';
pop2 <= '0';
when dup =>
e0_sel <= "00";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '0';
e1_en <= '1';
e2_en <= '1';
push <= '1';
pop <= '0';
pop2 <= '0';
when nrd =>
e0_sel <= "10";
e1_sel <= "00";
e2_sel <= "01";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when rd =>
e0_sel <= "00";
e1_sel <= "00";
e2_sel <= "01";
e0_en <= '0';
e1_en <= '0';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when nrds =>
e0_sel <= "00";
e1_sel <= "01";
e2_sel <= "01";
e0_en <= '0';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when rds =>
e0_sel <= "01";
e1_sel <= "00";
e2_sel <= "01";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '1';
pop2 <= '0';
when over =>
e0_sel <= "01";
e1_sel <= "00";
e2_sel <= "00";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '1';
pop <= '0';
pop2 <= '0';
when wr_mem =>
e0_sel <= "10";
e1_sel <= "10";
e2_sel <= "11";
e0_en <= '1';
e1_en <= '1';
e2_en <= '1';
push <= '0';
pop <= '0';
pop2 <= '1';
when others => null;
end case;
end process;
end behavioral; | mit | 46d4846389850012f0688ef18e20222d | 0.448468 | 2.496276 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/data_memory.vhd | 1 | 1,096 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity data_memory is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic);
end data_memory;
architecture Behavioral of data_memory is
type memory_data_type is array (1023 downto 0) of std_logic_vector(31 downto 0); --1 kB of data memory
signal memory_data : memory_data_type;
signal address_short : std_logic_vector(9 downto 0);
begin
address_short <= address(9 downto 0);
main : process (clk, rst) is
begin
if rst = '1' then
memory_data <= (others => (others => '0'));
elsif falling_edge(clk) then
if we = '1' then
memory_data(conv_integer(unsigned(address_short))) <= data_in;
end if;
end if;
end process;
data_out <= memory_data(conv_integer(unsigned(address_short)));
end Behavioral;
| mit | 2df6991ec2aab41cd812a96daab4462d | 0.655109 | 3.149425 | false | false | false | false |
jsyk/spnsyn-demo | t/tslink00/tb2.vhd | 1 | 5,213 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
use work.comp_tslink_ct.all;
entity tslink is
port (
clk : in std_ulogic;
rst : in std_ulogic;
LinkIn : in std_ulogic;
IValid : in std_ulogic;
QAck : in std_ulogic;
IData : in std_logic_vector(7 downto 0);
IAck : out std_ulogic;
QData : out std_logic_vector(7 downto 0);
LinkOut : out std_ulogic;
QValid : out std_ulogic
);
end entity;
architecture rtl of tslink is
signal ShiftEnable : std_ulogic;
signal s_qdata : std_logic_vector(7 downto 0);
begin
ct: tslink_ct
port map (
clk, -- : in std_ulogic;
rst, -- : in std_ulogic;
LinkIn, -- : in std_ulogic;
IValid, -- : in std_ulogic;
QAck, -- : in std_ulogic;
IData, -- : in std_logic_vector(7 downto 0);
IAck, -- : out std_ulogic;
ShiftEnable, -- : out std_ulogic;
LinkOut, -- : out std_ulogic;
QValid -- : out std_ulogic
);
shifter: process (clk)
begin
if rising_edge(clk) then
if rst='1' then
s_qdata <= (others => '0');
else
if ShiftEnable='1' then
s_qdata <= LinkIn & s_qdata(7 downto 1);
end if;
end if;
end if;
end process;
QData <= s_qdata;
end architecture rtl;
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
use work.comp_tslink_ct.all;
entity tb2 is
end entity;
architecture arch of tb2 is
component tslink is
port (
clk : in std_ulogic;
rst : in std_ulogic;
LinkIn : in std_ulogic;
IValid : in std_ulogic;
QAck : in std_ulogic;
IData : in std_logic_vector(7 downto 0);
IAck : out std_ulogic;
QData : out std_logic_vector(7 downto 0);
LinkOut : out std_ulogic;
QValid : out std_ulogic
);
end component;
signal eos : boolean := false;
signal clk : std_ulogic;
signal rst : std_ulogic;
signal LinkIn : std_ulogic;
signal LinkOut : std_ulogic;
signal IValid_1 : std_ulogic;
signal QAck_1 : std_ulogic;
signal IData_1 : std_logic_vector(7 downto 0);
signal IAck_1 : std_ulogic;
signal QData_1 : std_logic_vector(7 downto 0);
signal QValid_1 : std_ulogic;
signal IValid_2 : std_ulogic;
signal QAck_2 : std_ulogic;
signal IData_2 : std_logic_vector(7 downto 0);
signal IAck_2 : std_ulogic;
signal QData_2 : std_logic_vector(7 downto 0);
signal QValid_2 : std_ulogic;
begin
dut1: tslink
port map (
clk, -- : in std_ulogic;
rst, -- : in std_ulogic;
LinkIn, -- : in std_ulogic;
IValid_1, -- : in std_ulogic;
QAck_1, -- : in std_ulogic;
IData_1, -- : in std_logic_vector(7 downto 0);
IAck_1, -- : out std_ulogic;
QData_1,
LinkOut, -- : out std_ulogic;
QValid_1 -- : out std_ulogic
);
dut2: tslink
port map (
clk, -- : in std_ulogic;
rst, -- : in std_ulogic;
LinkOut, -- : in std_ulogic;
IValid_2, -- : in std_ulogic;
QAck_2, -- : in std_ulogic;
IData_2, -- : in std_logic_vector(7 downto 0);
IAck_2, -- : out std_ulogic;
QData_2,
LinkIn, -- : out std_ulogic;
QValid_2 -- : out std_ulogic
);
clkgen: process
begin
clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns; clk <= '0';
if eos then
wait;
end if;
end process;
tb1: process
begin
rst <= '1';
IValid_1 <= '0';
QAck_1 <= '0';
IData_1 <= x"00";
wait until rising_edge(clk);
rst <= '0';
wait until rising_edge(clk);
IData_1 <= x"A5";
IValid_1 <= '1';
wait until rising_edge(clk) and IAck_1='1';
IValid_1 <= '0';
wait until rising_edge(clk) and QValid_1='1';
QAck_1 <= '1';
wait until rising_edge(clk);
QAck_1 <= '0';
wait until rising_edge(clk);
IData_1 <= x"12";
IValid_1 <= '1';
wait until rising_edge(clk) and QValid_1='1';
QAck_1 <= '1';
wait until rising_edge(clk) and IAck_1='1';
IValid_1 <= '0';
QAck_1 <= '0';
wait for 30 ns;
eos <= true;
wait;
end process;
tb2: process
begin
IValid_2 <= '0';
QAck_2 <= '0';
IData_2 <= x"00";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk) and QValid_2='1';
QAck_2 <= '1';
wait until rising_edge(clk);
QAck_2 <= '0';
IData_2 <= x"5A";
IValid_2 <= '1';
wait until rising_edge(clk) and IAck_2='1';
IValid_2 <= '0';
wait until rising_edge(clk);
IData_2 <= x"23";
IValid_2 <= '1';
wait until rising_edge(clk) and QValid_2='1';
QAck_2 <= '1';
wait until rising_edge(clk) and IAck_2='1';
IValid_2 <= '0';
QAck_2 <= '0';
wait;
end process;
end architecture ; -- arch
| gpl-2.0 | c53b84b201659cb9e22be4a47fc64f0f | 0.523307 | 3.318269 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/bpgenlib.vhd | 1 | 15,760 | -- $Id: bpgenlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: bpgenlib
-- Description: Generic Board/Part components
--
-- Dependencies: -
-- Tool versions: ise 12.1-14.7; viv 2014.4-2018.2; ghdl 0.26-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.2.3 add s7_cmt_1ce1ce
-- 2018-08-11 1038 1.2.2 add rgbdrv_3x2mux
-- 2017-06-05 907 1.2.1 rgbdrv_analog: add ACTLOW generic
-- 2016-02-27 737 1.2 add rgbdrv entity
-- 2015-01-24 637 1.1.2 add generics to sn_humanio and sn_7segctl
-- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob
-- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib
-- 2013-01-06 472 1.0.7 add sn_humanio_demu_rbus
-- 2011-11-16 426 1.0.6 now numeric_std clean
-- 2011-10-10 413 1.0.5 add sn_humanio_demu
-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob
-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob
-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib
-- 2011-07-08 390 1.0.1 move in sn_(4x7segctl|humanio*) from s3boardlib
-- 2011-07-01 386 1.0 Initial version (with rs232_iob's and bp_swibtnled)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package bpgenlib is
component bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit -- pad-o: transmit data (board view)
);
end component;
component bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end component;
component bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
component bp_rs232_4l4l_iob is -- iob's for dual 4l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_CTS0_N : in slbit; -- pad-i: p0: clear to send (act. low)
O_RTS0_N : out slbit; -- pad-o: p0: request to send (act. low)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
component bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component sn_7segctl is -- 7 segment display controller
generic (
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv(4*(2**DCWIDTH)-1 downto 0); -- data 16 or 32
DP : in slv((2**DCWIDTH)-1 downto 0); -- decimal points 4 or 8
ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- anodes (act.low) 4 or 8
SEG_N : out slv8 -- segements (act.low)
);
end component;
component sn_humanio is -- human i/o handling: swi,btn,led,dsp
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end component;
component sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
component rgbdrv_master is -- rgbled driver: master
generic (
DWIDTH : positive := 8); -- dimmer width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
RGBCNTL : out slv3; -- rgb control
DIMCNTL : out slv(DWIDTH-1 downto 0) -- dim control
);
end component;
component rgbdrv_analog is -- rgbled driver: analog channel
generic (
DWIDTH : positive := 8; -- dimmer width
ACTLOW : slbit := '0'); -- invert output polarity
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
DIMR : in slv(DWIDTH-1 downto 0); -- dim red
DIMG : in slv(DWIDTH-1 downto 0); -- dim green
DIMB : in slv(DWIDTH-1 downto 0); -- dim blue
O_RGBLED : out slv3 -- pad-o: rgb led
);
end component;
component rgbdrv_binary is -- rgbled driver: binary channel
generic (
DWIDTH : positive := 8); -- dimmer width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
DIM : in slv(DWIDTH-1 downto 0); -- dim
ENARGB : in slv3; -- enable [0] red [1] green [2] blue
O_RGBLED : out slv3 -- pad-o: rgb led
);
end component;
component rgbdrv_3x4mux is -- rgbled driver: mux three 4bit inputs
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
DATR : in slv4; -- red data
DATG : in slv4; -- green data
DATB : in slv4; -- blue data
O_RGBLED0 : out slv3; -- pad-o: rgb led 0
O_RGBLED1 : out slv3; -- pad-o: rgb led 1
O_RGBLED2 : out slv3; -- pad-o: rgb led 2
O_RGBLED3 : out slv3 -- pad-o: rgb led 3
);
end component;
component rgbdrv_3x2mux is -- rgbled driver: mux three 2bit inputs
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
DATR : in slv2; -- red data
DATG : in slv2; -- green data
DATB : in slv2; -- blue data
O_RGBLED0 : out slv3; -- pad-o: rgb led 0
O_RGBLED1 : out slv3 -- pad-o: rgb led 1
);
end component;
component s7_cmt_1ce1ce is -- clocking block: 2 clk+CEs
generic (
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
CLK0_VCODIV : positive := 1; -- clk0: vco clock divide
CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply
CLK0_OUTDIV : positive := 1; -- clk0: output divide
CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM
CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width
CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse
CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse
CLK1_VCODIV : positive := 1; -- clk1: vco clock divide
CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply
CLK1_OUTDIV : positive := 1; -- clk1: output divide
CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM
CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width
CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse
CLK1_MSECDIV : positive := 1000); -- clk1: divider ratio for msec pulse
port (
CLKIN : in slbit; -- clock input
CLK0 : out slbit; -- clk0: clock output
CE0_USEC : out slbit; -- clk0: usec pulse
CE0_MSEC : out slbit; -- clk0: msec pulse
CLK1 : out slbit; -- clk1: clock output
CE1_USEC : out slbit; -- clk1: usec pulse
CE1_MSEC : out slbit; -- clk1: msec pulse
LOCKED : out slbit -- all PLL/MMCM locked
);
end component;
component s7_cmt_1ce1ce2c is -- clocking block: 2 clk+CEs; 2 clk
generic (
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
CLK0_VCODIV : positive := 1; -- clk0: vco clock divide
CLK0_VCOMUL : positive := 1; -- clk0: vco clock multiply
CLK0_OUTDIV : positive := 1; -- clk0: output divide
CLK0_GENTYPE : string := "PLL"; -- clk0: PLL or MMCM
CLK0_CDUWIDTH : positive := 7; -- clk0: usec clock divider width
CLK0_USECDIV : positive := 50; -- clk0: divider ratio for usec pulse
CLK0_MSECDIV : positive := 1000; -- clk0: divider ratio for msec pulse
CLK1_VCODIV : positive := 1; -- clk1: vco clock divide
CLK1_VCOMUL : positive := 1; -- clk1: vco clock multiply
CLK1_OUTDIV : positive := 1; -- clk1: output divide
CLK1_GENTYPE : string := "MMCM"; -- clk1: PLL or MMCM
CLK1_CDUWIDTH : positive := 7; -- clk1: usec clock divider width
CLK1_USECDIV : positive := 50; -- clk1: divider ratio for usec pulse
CLK1_MSECDIV : positive := 1000; -- clk1: divider ratio for msec pulse
CLK23_VCODIV : positive := 1; -- clk2+3: vco clock divide
CLK23_VCOMUL : positive := 1; -- clk2+3: vco clock multiply
CLK2_OUTDIV : positive := 1; -- clk2: output divide
CLK3_OUTDIV : positive := 1; -- clk3: output divide
CLK23_GENTYPE : string := "PLL"); -- clk2+3: PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLK0 : out slbit; -- clk0: clock output
CE0_USEC : out slbit; -- clk0: usec pulse
CE0_MSEC : out slbit; -- clk0: msec pulse
CLK1 : out slbit; -- clk1: clock output
CE1_USEC : out slbit; -- clk1: usec pulse
CE1_MSEC : out slbit; -- clk1: msec pulse
CLK2 : out slbit; -- clk2: clock output
CLK3 : out slbit; -- clk3: clock output
LOCKED : out slbit -- all PLL/MMCM locked
);
end component;
end package bpgenlib;
| gpl-3.0 | f3999f19f33393e68b67799dcfe44e93 | 0.51231 | 3.631336 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_irq.vhd | 1 | 5,357 | -- $Id: pdp11_irq.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_irq - syn
-- Description: pdp11: interrupt requester
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-23 1136 1.3 BUGFIX: re-write, ensure ACK send to correct device
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2008-08-22 161 1.1.4 use iblib
-- 2008-04-25 138 1.1.3 use BRESET to clear pirq
-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_irq is -- interrupt requester
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- bus reset
INT_ACK : in slbit; -- interrupt acknowledge from CPU
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PRI : out slv3; -- interrupt priority
VECT : out slv9_2; -- interrupt vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_irq;
architecture syn of pdp11_irq is
constant ibaddr_pirq : slv16 := slv(to_unsigned(8#177772#,16));
constant vect_pirq : slv9 := slv(to_unsigned(8#240#,9));
subtype pirq_ibf_pir is integer range 15 downto 9;
subtype pirq_ibf_pia_h is integer range 7 downto 5;
subtype pirq_ibf_pia_l is integer range 3 downto 1;
type regs_type is record -- state registers
pirq : slv8_1; -- pirq mask
eilast : slbit; -- ei won in last cycle
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- pirq
'0' -- eilast
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal IBSEL_PIRQ : slbit := '0';
signal PI_PRI : slv3 := (others => '0'); -- prog.int. priority
-- attribute PRIORITY_EXTRACT : string;
-- attribute PRIORITY_EXTRACT of PI_PRI : signal is "force";
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_pirq)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_PIRQ
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
PI_PRI <= "111" when R_REGS.pirq(7)='1' else
"110" when R_REGS.pirq(6)='1' else
"101" when R_REGS.pirq(5)='1' else
"100" when R_REGS.pirq(4)='1' else
"011" when R_REGS.pirq(3)='1' else
"010" when R_REGS.pirq(2)='1' else
"001" when R_REGS.pirq(1)='1' else
"000";
proc_next : process (R_REGS, IB_MREQ, IBSEL_PIRQ, PI_PRI,
EI_PRI, EI_VECT, INT_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
-- ibus transactions
if IBSEL_PIRQ = '1' then
idout(pirq_ibf_pir) := r.pirq;
idout(pirq_ibf_pia_h) := PI_PRI;
idout(pirq_ibf_pia_l) := PI_PRI;
if IB_MREQ.we='1'and IB_MREQ.be1='1' then
n.pirq := IB_MREQ.din(pirq_ibf_pir);
end if;
end if;
-- pirq vs ei_vect selection
if unsigned(EI_PRI) > unsigned(PI_PRI) then
n.eilast := '1';
PRI <= EI_PRI;
VECT <= EI_VECT;
else
n.eilast := '0';
PRI <= PI_PRI;
VECT <= vect_pirq(8 downto 2);
end if;
-- Note: INT_ACK comes one cycle after vector is latched !
-- therefore send INT_ACK to EI_ACKM only if EI was winner in last cycle
EI_ACKM <= '0';
if r.eilast = '1' then
EI_ACKM <= INT_ACK;
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_PIRQ and ibreq; -- ack all
IB_SRES.busy <= '0';
end process proc_next;
end syn;
| gpl-3.0 | 0211940b03754a8b8ea39bd73fbf9642 | 0.527161 | 3.331468 | false | false | false | false |
sjohann81/hf-risc | riscv/sim/hf-riscv_basic_standard_soc_ext_sram_tb.vhd | 1 | 9,949 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 14;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(15 downto 0);
signal gpiob_in, gpiob_out, gpiob_ddr: std_logic_vector(15 downto 0);
signal gpio_sig, gpio_sig2, gpio_sig3: std_logic := '0';
signal data_read_spi: std_logic_vector(31 downto 0);
signal data_mode: std_logic_vector(2 downto 0);
signal burst, wr, rd, we, stall_dly, stall_dly2, stall_spi, spi_sel, spi_cs, spi_cs2, spi_clk, spi_mosi, spi_miso, hold_n, spi_cs_n_s: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
wait for 100 us;
gpio_sig <= not gpio_sig;
gpio_sig2 <= not gpio_sig2;
end process;
process
begin
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
wait for 5 ms;
gpio_sig3 <= not gpio_sig3;
end process;
gpioa_in <= x"00" & "0000" & gpio_sig & "000";
gpiob_in <= "10000" & gpio_sig3 & "00" & "00000" & gpio_sig2 & "00";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
spi_sel <= '1' when address(31 downto 28) = "0011" else '0';
rd <= '1' when (spi_sel = '1' and data_we = "0000" and stall_dly2 = '0') else '0';
wr <= '1' when (spi_sel = '1' and data_we /= "0000" and stall_dly2 = '0') else '0';
-- data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_spi when spi_sel = '1' or stall_dly2 = '1' else
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_spi when spi_sel = '1' else
data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
hold_n <= '1';
burst <= '0';
stall_sig <= stall_spi;
-- stall_sig <= stall_spi or (not stall_dly and stall_dly2);
-- external SPI SRAM/EEPROM, 0x30000000 (26,25 - spi select, 24 - short address mode, 23 - EEPROM write enable latch)
spi_cs <= spi_cs_n_s when spi_sel = '1' and address(25) = '0' else '1';
-- external SPI SRAM/EEPROM, 0x32000000
spi_cs2 <= spi_cs_n_s when spi_sel = '1' and address(25) = '1' else '1';
we <= address(24) and address(23);
process(clock_in, reset, stall_spi)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
stall_dly <= '0';
stall_dly2 <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
stall_dly <= stall_spi;
stall_dly2 <= stall_dly;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => data_mode,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
sram_ctrl_core: entity work.spi_sram_ctrl
port map( clk_i => clock_in,
rst_i => reset,
addr_i => address(23 downto 0),
data_i => data_write,
data_o => data_read_spi,
burst_i => burst,
bmode_i => data_mode(2),
hmode_i => data_mode(1),
wr_i => wr,
rd_i => rd,
saddr_i => address(24),
wren_i => we,
data_ack_o => open,
cpu_stall_o => stall_spi,
spi_cs_n_o => spi_cs_n_s,
spi_clk_o => spi_clk,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso
);
spi_sram: entity work.M23LC1024
port map( SI_SIO0 => spi_mosi,
SO_SIO1 => spi_miso,
SCK => spi_clk,
CS_N => spi_cs,
SIO2 => open,
HOLD_N_SIO3 => hold_n,
RESET => reset
);
spi_eeprom: entity work.M25LC256
port map( SI => spi_mosi,
SO => spi_miso,
SCK => spi_clk,
CS_N => spi_cs2,
WP_N => hold_n,
HOLD_N => hold_n,
RESET => reset
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(30 downto 24));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"70000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | bbd1c0147225944f52fd47eee337a5e8 | 0.590411 | 2.6559 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/sim_top_TB.vhd | 2 | 686 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity sim_top_TB is
end sim_top_TB;
architecture Behavioral of sim_top_TB is
component sim_top is
port(clk : in std_logic;
rst : in std_logic);
end component;
signal rst, clk : std_logic;
begin
uut : sim_top
port map(clk => clk,
rst => rst);
clocker : process is
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
stim : process is
begin
rst <= '1';
wait for 1000 ns;
rst <= '0';
wait;
end process;
end Behavioral;
| mit | ebcacf0f8965be442be3d056bb9d4e22 | 0.609329 | 2.858333 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/bp_rs232_4line_iob.vhd | 1 | 2,339 | -- $Id: bp_rs232_4line_iob.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_4line_iob - syn
-- Description: iob's for 4 line rs232 (RXD,TXD and RTS,CTS)
--
-- Dependencies: xlib/iob_reg_i
-- xlib/iob_reg_o
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-01 386 1.1 moved and renamed to bpgen
-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_ext)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS)
port (
CLK : in slbit; -- clock
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD : in slbit; -- pad-i: receive data (board view)
O_TXD : out slbit; -- pad-o: transmit data (board view)
I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
O_RTS_N : out slbit -- pad-o: request to send (act. low)
);
end bp_rs232_4line_iob;
architecture syn of bp_rs232_4line_iob is
begin
IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
generic map (INIT => '1')
port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
IOB_CTS : iob_reg_i
port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N);
IOB_RTS : iob_reg_o
port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N);
end syn;
| gpl-3.0 | d3997329496dd155b7bcd279dc724203 | 0.477127 | 3.31773 | false | false | false | false |
abcsds/Micros | RS232Write_16/BaudRate.vhd | 6 | 1,850 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRate is
port(
RST : in std_logic;
CLK : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end BaudRate;
architecture simple of BaudRate is
signal Qp, Qn, NB : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1101110111110010001"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end process COMB;
FF: process(RST,CLK)
begin
if(RST='0')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
| gpl-3.0 | 383eb325352ebd786452049ab72906a4 | 0.577838 | 3.178694 | false | false | false | false |
jasonpeng/cg3207-proj | Decoder.vhd | 1 | 9,437 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity Decoder is
Port (
Clk : in std_logic;
Reset : in std_logic;
In_PC : in std_logic_vector (31 downto 0); --input PC, instruction position
In_Instr : in STD_LOGIC_VECTOR(31 downto 0);
write_address: in std_logic_vector(4 downto 0);
WriteData1 : in STD_LOGIC_VECTOR(31 downto 0);
WriteData2: in std_logic_vector(31 downto 0); -- in case it is a multiplication or division.
Mul_or_Div: in std_logic; -- to detect if it is a mul or div;
RegWrite_in : in std_logic;
-- Data Hazzard Detection
ID_EX_MEM_READ: in std_logic;
ID_EX_REG_RT: in std_logic_vector(4 downto 0); -- ID EX Register RT
ID_STALL: out std_logic;
-- wb
RegWrite: out std_logic;
MemtoReg: out std_logic;
--MEM
MemRead : OUT STD_LOGIC;
MemWrite : OUT STD_LOGIC;
--EX
RegDst : OUT STD_LOGIC;
ALUop : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
ALUSrc : OUT STD_LOGIC;
--JUMP
Jump : OUT STD_LOGIC;
JumpPC : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
BranchPC : OUT STD_LOGIC_VECTOR(31 downto 0);
-- Branch Controls
EX_MEM_REG_RD : in std_logic_vector(4 downto 0);
Branch_Sign_Extended: out std_logic_vector(31 downto 0);
PCSrc : OUT STD_LOGIC;
read_data_1: out std_logic_vector (31 downto 0);
read_data_2: out std_logic_vector (31 downto 0);
-- Check Registers
Reg_S1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S2 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S3 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S4 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S5 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S6 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S7 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Reg_S8 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Instr_25to21: out std_logic_vector(4 downto 0);
Instr_20to16 : out std_logic_vector(4 downto 0);
Instr_15to11: out std_logic_vector (4 downto 0)
);
end Decoder;
architecture Behavioral_Decoder of Decoder is
component Control
port(
Instr: in std_logic_vector(31 downto 0);
RegDst: out std_logic;
ALUSrc:out std_logic;
MemtoReg: out std_logic;
RegWrite:out std_logic;
MemRead:out std_logic;
MemWrite:out std_logic;
ALUOp: out std_logic_vector(2 downto 0));
end component;-- RegWrite internal signal
component RegisterFile
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RegWrite : in STD_LOGIC;
RegWriteAddr : in STD_LOGIC_VECTOR(4 downto 0);
RegWriteData : in STD_LOGIC_VECTOR(31 downto 0);
RegAddr_1 : in STD_LOGIC_VECTOR(4 downto 0);
RegAddr_2 : in STD_LOGIC_VECTOR(4 downto 0);
RegData_1 : out STD_LOGIC_VECTOR(31 downto 0);
RegData_2 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_1 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_2 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_3 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_4 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_5 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_6 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_7 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_8 : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
component HazardUnit is
Port (
ID_EX_MemRead : in std_logic;
ID_EX_RegRt : in std_logic_vector(4 downto 0);
IF_ID_RegRs : in std_logic_vector(4 downto 0);
IF_ID_RegRt : in std_logic_vector(4 downto 0);
Jump : in std_logic;
STALL : out std_logic
);
end component;
-- Registers
--TYPE register_file is array (0 to 31) of std_logic_vector (31 downto 0);
--signal register_array: register_file;
alias opcode: std_logic_vector(5 downto 0) is In_Instr(31 downto 26);
alias reg_rs: std_logic_vector(4 downto 0) is In_Instr(25 downto 21);
alias reg_rt: std_logic_vector(4 downto 0) is In_Instr(20 downto 16);
alias reg_rd: std_logic_vector(4 downto 0) is In_Instr(15 downto 11);
alias funct: std_logic_vector(5 downto 0) is In_Instr(5 downto 0);
-- signal register_low: std_logic_vector(31 downto 0);
-- signal register_high: std_logic_vector(31 downto 0);
signal imm_value : std_logic_vector (15 downto 0);
--
SIGNAL ALUSrc_out : STD_LOGIC;
SIGNAL Branch_out : STD_LOGIC;
SIGNAL RegDst_out : STD_LOGIC;
SIGNAL Regwrite_out : STD_LOGIC;
SIGNAL MemWrite_out : STD_LOGIC;
SIGNAL MemtoReg_out : STD_LOGIC;
SIGNAL MemRead_out : STD_LOGIC;
SIGNAL ALUop_out : STD_LOGIC_VECTOR( 2 DOWNTO 0 );
SIGNAL Jump_out : STD_LOGIC;
-- for data hazzard detection
signal stall : std_logic;
-- for control branch
signal SignExtended:std_logic_vector(31 downto 0);
signal Branch: std_logic;
signal Forward_c: std_logic;
signal Forward_d: std_logic;
signal cmp_A: std_logic_vector(31 downto 0);
signal cmp_B: std_logic_vector(31 downto 0);
signal cmp_result: std_logic;
signal Jump_buffer: std_logic;
signal RegAddr_1_buff : std_logic_vector(4 downto 0);
signal RegAddr_2_buff : std_logic_vector(4 downto 0);
signal RegData_1_buff : std_logic_vector(31 downto 0);
signal RegData_2_buff : std_logic_vector(31 downto 0);
begin
imm_value <= In_Instr(15 downto 0);
-- Read Register 1 Operation
SignExtended <= X"0000" & imm_value when imm_value(15)= '0'
else X"FFFF" & imm_value;
-- JumpPC = calculated address when JUMP is JAL or J I type
Jump_buffer <= '1' when (Opcode = "000010" or Opcode = "000011" or (Opcode = "000000" and funct = "001000") or (Opcode ="000000" and funct = "001001"))-- case for jump
else '0';
Jump <= Jump_buffer;
--JumpPC <= register_array(to_integer(unsigned(reg_rs))) when (Opcode= "000000")
-- else In_PC(31 downto 28) & In_Instr (25 DOWNTO 0) & "00";
JumpPC <= In_PC(31 downto 28) & In_Instr (25 DOWNTO 0) & "00";
-- -- for mul & div cases
-- register_low <= writedata1 when (Mul_or_Div = '1')
-- else x"00000000";
-- register_high <= writedata2 when (Mul_or_Div = '1')
-- else x"00000000";
-- Branch Control hazards
--control signal branch is 1 when BEQ, BGEZ,BGEZAL
Branch <= '1' when (Opcode= "000100" or Opcode="000001")
else '0';
-- for Branch cases, Forward_d is only valid in BEQ case,
Forward_c <= '1' when (Branch = '1' and (EX_MEM_REG_RD /= "00000")and (EX_MEM_REG_RD = reg_rs))
else '0';
Forward_d <= '1' when (Opcode ="000100" and (EX_MEM_REG_RD /= "00000")and (EX_MEM_REG_RD = reg_rt))
else '0';
-- CMP_A and CMP_B IN BEQ CASE
RegAddr_1_buff <= EX_MEM_REG_RD when (Forward_c = '1')
else reg_rs;
RegAddr_2_buff <= EX_MEM_REG_RD when (Forward_d = '1')
else reg_rt;
cmp_result <= '1' when ((Opcode= "000100" and (RegData_1_buff = RegData_2_buff)) -- case for BEQ
or (In_Instr(31 downto 26)="000001" and (RegData_1_buff(31) ='0'))) --case for BGEZ & BGEZAL
else '0';
PCSrc <= cmp_result and Branch;
BranchPC <= std_logic_vector(unsigned(In_PC) + (unsigned(SignExtended) sll 2));
-- register_array(31) <= (In_PC + X"0000004") when ((cmp_result ='1' and Branch ='1' and (reg_rt = "10001"))
-- or Opcode= "000011"); -- case JAL and BGEZAL, store PC+8 into register 31
-- register_array(to_integer(unsigned(reg_rd)) <= (In_PC + 4) when (Opcode = "000000" and funct = "001001") -- case jalr
-- else register_low when (Opcode="000000" and funct= "010010") -- case mvlo
-- else register_high when (Opcode= "000000" and funct= "010000"); -- case mvhi
read_data_1 <= RegData_1_buff;
read_data_2 <= RegData_2_buff;
ctrl: control port map
(
Instr => In_Instr,
RegDst =>RegDst_out,
ALUSrc => ALUSrc_out,
MemtoReg => MemtoReg_out,
RegWrite => RegWrite_out,
MemRead => MemRead_out,
MemWrite => MemWrite_out,
ALUOp => ALUOp_out
);
RF0 : RegisterFile port map (
CLK => CLK,
RESET => reset,
RegWrite => RegWrite_in,
RegWriteAddr => write_address,
RegWriteData => WriteData1,
RegAddr_1 => RegAddr_1_buff,
RegAddr_2 => RegAddr_2_buff,
RegData_1 => RegData_1_buff,
RegData_2 => RegData_2_buff,
Reg_1 => Reg_S1,
Reg_2 => Reg_S2,
Reg_3 => Reg_S3,
Reg_4 => Reg_S4,
Reg_5 => Reg_S5,
Reg_6 => Reg_S6,
Reg_7 => Reg_S7,
Reg_8 => Reg_S8
);
HZ: HazardUnit port map(
ID_EX_MemRead => ID_EX_MEM_READ,
ID_EX_RegRt => ID_EX_REG_RT,
IF_ID_RegRs => reg_rs,
IF_ID_RegRt => reg_rt,
Jump => Jump_buffer,
STALL => stall
);
pipeline_control: process (Reset, Stall, RegWrite_out, MemToReg_out, MemRead_out, MemWrite_out,
RegDst_out, ALUOp_out, ALUSrc_out, reg_rs, reg_rt, reg_rd, SignExtended)
begin
if Reset = '1' OR Stall = '1' then
RegWrite <= '0';
MemtoReg <= '0';
MemRead <='0';
MemWrite <='0';
RegDst <='0';
ALUop <="000";
ALUSrc <='0';
Instr_25to21 <= "00000";
Instr_20to16 <= "00000";
Instr_15to11 <= "00000";
Branch_Sign_extended <= (others => '0');
ID_Stall <= '1';
else
RegWrite <= RegWrite_out;
MemtoReg <= MemtoReg_out;
MemRead <= MemRead_out;
MemWrite <= MemWrite_out;
RegDst <= RegDst_out;
ALUOp <= ALUOp_out;
ALUSrc <= ALUSrc_out;
Instr_25to21 <= reg_rs;
Instr_20to16 <= reg_rt;
Instr_15to11 <= reg_rd;
Branch_Sign_extended <= SignExtended;
ID_Stall <= '0';
end if;
end process;
end Behavioral_Decoder;
| gpl-2.0 | 9d3e8cbb8d18a307deff081c2ad918f7 | 0.623503 | 3.028562 | false | false | false | false |
wfjm/w11 | rtl/vlib/simlib/simbus.vhd | 1 | 1,617 | -- $Id: simbus.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: simbus
-- Description: Global signals for support control in test benches
--
-- Dependencies: -
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 2.1 rename SB_CLKSTOP > SB_SIMSTOP; init with 'L'
-- 2011-12-23 444 2.0 remove global clock cycle signal SB_CLKCYCLE
-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package simbus is
signal SB_SIMSTOP : slbit := 'L'; -- global simulation stop
signal SB_CNTL : slv16 := (others=>'L'); -- global signals tb -> uut
signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
signal SB_VAL : slbit := 'L'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'L'); -- init bcast address
signal SB_DATA : slv16 := (others=>'L'); -- init bcast data
-- Note: SB_SIMSTOP, SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak
-- ('L','H') and strong ('0','1') drivers. Therefore always remove
-- strenght before using, e.g. with to_x01()
end package simbus;
| gpl-3.0 | bb7dc670446f2074c6e72888d00aa6eb | 0.554113 | 3.425847 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_04800_good.vhd | 1 | 4,819 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-20 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_04800_good.vhd
-- File Creation date : 2015-04-20
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Finite State Machine two processes based: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_04800_good is
port (
i_Clock : in std_logic; -- Clock input
i_Reset_n : in std_logic; -- Reset input
i_Start : in std_logic; -- Start counter signal
i_Stop : in std_logic -- Stop counter signal
);
end CNE_04800_good;
--CODE
architecture Behavioral of CNE_04800_good is
constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
type t_state is (init, loading, enabled, finished); -- Enumerated type for state encoding
signal sm_State : t_state; -- State signal
signal sm_Next_State : t_state; -- Next state
signal Raz : std_logic; -- Load the length value and initialize the counter
signal Enable : std_logic; -- Counter enable signal
signal Length : std_logic_vector(3 downto 0); -- Counter length for counting
signal End_Count : std_logic; -- End signal of counter
begin
Counter:pkg_Counter
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_Raz => Raz,
i_Enable => Enable,
i_Length => Length,
o_Done => End_Count
);
-- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop),
-- load the length value, and wait for it to finish
-- Process registration
P_FSM_State_Reg:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
sm_State <= init;
elsif (rising_edge(i_Clock)) then
sm_State <= sm_Next_State;
end if;
end process;
-- Outputs assertion
P_FSM_Output:process(sm_State, i_Start, i_Stop, End_Count)
begin
Raz <= '0';
Enable <= '0';
Length <= c_Length; -- Set the length value
case sm_State is
when init =>
sm_Next_State <= loading;
when loading =>
-- Load the counter and initialize it
Raz <= '1';
sm_Next_State <= enabled;
when enabled =>
-- Start or stop counting depending on inputs until it finishes
if (End_Count='0') then
Enable <= i_Start xor not i_Stop;
sm_Next_State <= enabled;
else
sm_Next_State <= finished;
end if;
when others =>
sm_Next_State <= init;
end case;
end process;
end Behavioral;
--CODE | gpl-3.0 | e38dda660f50b57eb996182289f75e02 | 0.490351 | 4.572106 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32i/control.vhd | 2 | 14,074 | -- control signals for HF-RISCV
--
-- alu_op: alu_src1: mem_write: jump:
-- 0000 -> and 0 -> r[rs1] 00 -> no mem write 00 -> no jump
-- 0001 -> or 1 -> pc_last2 01 -> sb 01 -> don't care
-- 0010 -> xor 10 -> sh 10 -> jal
-- 0011 -> don't care alu_src2: 11 -> sw 11 -> jalr
-- 0100 -> add 000 -> imm_u
-- 0101 -> sub 001 -> imm_i mem_read: branch:
-- 0110 -> lui, jal, jalr 010 -> imm_s 00 -> no mem read 000 -> no branch
-- 0111 -> slt 011 -> pc 01 -> lb 001 -> beq
-- 1000 -> sltu 100 -> rs2 10 -> lh 010 -> bne
-- 1001 -> sll 101 -> r[rs2] 11 -> lw 011 -> blt
-- 1010 -> srl 110 -> don't care 100 -> bge
-- 1011 -> don't care 111 -> don't care 101 -> bltu
-- 1100 -> sra 110 -> bgeu
-- 1101 -> don't care reg_write: sig_read: 111 -> system
-- 1110 -> don't care 0 -> no write 0 -> unsigned
-- 1111 -> don't care 1 -> write register 1 -> signed
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port ( opcode: in std_logic_vector(6 downto 0);
funct3: in std_logic_vector(2 downto 0);
funct7: in std_logic_vector(6 downto 0);
reg_write: out std_logic;
alu_src1: out std_logic;
alu_src2: out std_logic_vector(2 downto 0);
alu_op: out std_logic_vector(3 downto 0);
jump: out std_logic_vector(1 downto 0);
branch: out std_logic_vector(2 downto 0);
mem_write: out std_logic_vector(1 downto 0);
mem_read: out std_logic_vector(1 downto 0);
sig_read: out std_logic
);
end control;
architecture arch_control of control is
begin
process(opcode, funct3, funct7)
begin
case opcode is -- load immediate / jumps
when "0110111" => -- LUI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0110";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0010111" => -- AUIPC
reg_write <= '1';
alu_src1 <= '1';
alu_src2 <= "000";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1101111" => -- JAL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "011";
alu_op <= "0110";
jump <= "10";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1100111" => -- JALR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "011";
alu_op <= "0110";
jump <= "11";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "1100011" => -- branches
case funct3 is
when "000" => -- BEQ
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "001";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "001" => -- BNE
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "010";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "100" => -- BLT
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "011";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" => -- BGE
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "100";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "110" => -- BLTU
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "101";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- BGEU
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "110";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0000011" => -- loads
case funct3 is
when "000" => -- LB
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "01";
sig_read <= '1';
when "001" => -- LH
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "10";
sig_read <= '1';
when "010" => -- LW
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "11";
sig_read <= '1';
when "100" => -- LBU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "01";
sig_read <= '0';
when "101" => -- LHU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "10";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0100011" => -- stores
case funct3 is
when "000" => -- SB
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "01";
mem_read <= "00";
sig_read <= '0';
when "001" => -- SH
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "10";
mem_read <= "00";
sig_read <= '0';
when "010" => -- SW
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "010";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "11";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0010011" => -- imm computation
case funct3 is
when "000" => -- ADDI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "010" => -- SLTI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0111";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "011" => -- SLTIU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "1000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "100" => -- XORI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "110" => -- ORI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- ANDI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "001";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "001" => -- SLLI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" =>
case funct7 is
when "0000000" => -- SRLI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SRAI
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "100";
alu_op <= "1100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "0110011" => -- computation
case funct3 is
when "000" =>
case funct7 is
when "0000000" => -- ADD
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SUB
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0101";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "001" => -- SLL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "010" => -- SLT
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0111";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "011" => -- SLTU
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "100" => -- XOR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "101" =>
case funct7 is
when "0000000" => -- SRL
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1010";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "0100000" => -- SRA
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "1100";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "110" => -- OR
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0001";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when "111" => -- AND
reg_write <= '1';
alu_src1 <= '0';
alu_src2 <= "101";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
when "1110011" => -- SYSTEM
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "111";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
when others =>
reg_write <= '0';
alu_src1 <= '0';
alu_src2 <= "000";
alu_op <= "0000";
jump <= "00";
branch <= "000";
mem_write <= "00";
mem_read <= "00";
sig_read <= '0';
end case;
end process;
end arch_control;
| gpl-2.0 | a3eb32fa37249d614f0bb8455169966b | 0.389797 | 2.805262 | false | false | false | false |
wfjm/w11 | rtl/bplib/basys3/tb/tb_basys3_core.vhd | 1 | 1,675 | -- $Id: tb_basys3_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_basys3_core - sim
-- Description: Test bench for basys3 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any basys3 target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4; ghdl 0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_basys3_core is
port (
I_SWI : out slv16; -- b3 switches
I_BTN : out slv5 -- b3 buttons
);
end tb_basys3_core;
architecture sim of tb_basys3_core is
signal R_SWI : slv16 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
| gpl-3.0 | d716b738b44dd8d6a13e15bf950bc934 | 0.555224 | 3.190476 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_mmu_mmr12.vhd | 1 | 5,442 | -- $Id: pdp11_mmu_mmr12.vhd 1291 2022-09-03 07:00:27Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu_mmr12 - syn
-- Description: pdp11: mmu register mmr1 and mmr2
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-08-30 1291 1.2.4 use ra_delta to steer mmr1 updates
-- 2022-08-13 1279 1.2.3 ssr->mmr rename
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_mmu_mmr12;
architecture syn of pdp11_mmu_mmr12 is
constant ibaddr_mmr1 : slv16 := slv(to_unsigned(8#177574#,16));
constant ibaddr_mmr2 : slv16 := slv(to_unsigned(8#177576#,16));
subtype mmr1_ibf_rb_delta is integer range 15 downto 11;
subtype mmr1_ibf_rb_num is integer range 10 downto 8;
subtype mmr1_ibf_ra_delta is integer range 7 downto 3;
subtype mmr1_ibf_ra_num is integer range 2 downto 0;
signal IBSEL_MMR1 : slbit := '0';
signal IBSEL_MMR2 : slbit := '0';
signal R_MMR1 : mmu_mmr1_type := mmu_mmr1_init;
signal R_MMR2 : slv16 := (others=>'0');
signal N_MMR1 : mmu_mmr1_type := mmu_mmr1_init;
signal N_MMR2 : slv16 := (others=>'0');
begin
SEL_MMR1 : ib_sel
generic map (
IB_ADDR => ibaddr_mmr1)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_MMR1
);
SEL_MMR2 : ib_sel
generic map (
IB_ADDR => ibaddr_mmr2)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_MMR2
);
proc_ibres : process (IBSEL_MMR1, IBSEL_MMR2, IB_MREQ, R_MMR1, R_MMR2)
variable mmr1out : slv16 := (others=>'0');
variable mmr2out : slv16 := (others=>'0');
begin
mmr1out := (others=>'0');
if IBSEL_MMR1 = '1' then
mmr1out(mmr1_ibf_rb_delta) := R_MMR1.rb_delta;
mmr1out(mmr1_ibf_rb_num) := R_MMR1.rb_num;
mmr1out(mmr1_ibf_ra_delta) := R_MMR1.ra_delta;
mmr1out(mmr1_ibf_ra_num) := R_MMR1.ra_num;
end if;
mmr2out := (others=>'0');
if IBSEL_MMR2 = '1' then
mmr2out := R_MMR2;
end if;
IB_SRES.dout <= mmr1out or mmr2out;
IB_SRES.ack <= (IBSEL_MMR1 or IBSEL_MMR2) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_regs : process (CLK)
begin
if rising_edge(CLK) then
R_MMR1 <= N_MMR1;
R_MMR2 <= N_MMR2;
end if;
end process proc_regs;
proc_comb : process (CRESET, IBSEL_MMR1, IB_MREQ,
R_MMR1, R_MMR2, TRACE, MONI)
variable nmmr1 : mmu_mmr1_type := mmu_mmr1_init;
variable nmmr2 : slv16 := (others=>'0');
variable delta : slv5 := (others=>'0');
begin
nmmr1 := R_MMR1;
nmmr2 := R_MMR2;
delta := "0" & MONI.delta;
if CRESET = '1' then
nmmr1 := mmu_mmr1_init;
nmmr2 := (others=>'0');
elsif IBSEL_MMR1='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
nmmr1.rb_delta := IB_MREQ.din(mmr1_ibf_rb_delta);
nmmr1.rb_num := IB_MREQ.din(mmr1_ibf_rb_num);
end if;
if IB_MREQ.be0 = '1' then
nmmr1.ra_delta := IB_MREQ.din(mmr1_ibf_ra_delta);
nmmr1.ra_num := IB_MREQ.din(mmr1_ibf_ra_num);
end if;
elsif TRACE = '1' then
if MONI.istart = '1' then
nmmr1 := mmu_mmr1_init;
nmmr2 := MONI.pc;
elsif MONI.regmod = '1' then
if R_MMR1.ra_delta = "00000" then
nmmr1.ra_num := MONI.regnum;
if MONI.isdec = '0' then
nmmr1.ra_delta := delta;
else
nmmr1.ra_delta := slv(-signed(delta));
end if;
else
nmmr1.rb_num := MONI.regnum;
if MONI.isdec = '0' then
nmmr1.rb_delta := delta;
else
nmmr1.rb_delta := slv(-signed(delta));
end if;
end if;
end if;
end if;
N_MMR1 <= nmmr1;
N_MMR2 <= nmmr2;
end process proc_comb;
end syn;
| gpl-3.0 | bc5a43cc5aefea8edcc7783e96f8b482 | 0.54208 | 3.03683 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/serport_uart_tx_tb.vhd | 1 | 3,245 | -- $Id: serport_uart_tx_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_tx_tb - sim
-- Description: serial port UART - transmitter (SIM only!)
--
-- Dependencies: -
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-03 724 1.0 Initial version (copied from serport_uart_tx)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_tx_tb is -- serial port uart: transmit part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end serport_uart_tx_tb;
architecture sim of serport_uart_tx_tb is
type regs_type is record
ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
bcnt : slv4; -- bit counter
sreg : slv9; -- output shift register
busy : slbit;
end record regs_type;
constant cntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
cntzero,
(others=>'0'),
(others=>'1'), -- sreg to all 1 !!
'0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CLKDIV, TXDATA, TXENA)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ld_ccnt : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ld_ccnt := '0';
if r.busy = '0' then
ld_ccnt := '1';
n.bcnt := (others=>'0');
if TXENA = '1' then
n.sreg := TXDATA & '0'; -- add start (0) bit
n.busy := '1';
end if;
else
if unsigned(r.ccnt) = 0 then
ld_ccnt := '1';
n.sreg := '1' & r.sreg(8 downto 1);
n.bcnt := slv(unsigned(r.bcnt) + 1);
if unsigned(r.bcnt) = 9 then -- if 10 bits send
n.busy := '0'; -- declare all done
end if;
end if;
end if;
if RESET = '1' then
ld_ccnt := '1';
n.busy := '0';
end if;
if ld_ccnt = '1' then
n.ccnt := CLKDIV;
else
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
N_REGS <= n;
TXBUSY <= r.busy;
TXSD <= r.sreg(0);
end process proc_next;
end sim;
| gpl-3.0 | 6b43696f8e9b8a6c0f77adfbf2b1cfe2 | 0.503544 | 3.641975 | false | false | false | false |
sjohann81/hf-risc | mips/core_mips/control.vhd | 1 | 17,876 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port ( opcode: in std_logic_vector(5 downto 0);
rtx: in std_logic_vector(4 downto 0);
funct: in std_logic_vector(5 downto 0);
reg_dst: out std_logic;
reg_write: out std_logic;
alu_src: out std_logic;
alu_op: out std_logic_vector(3 downto 0);
jump: out std_logic_vector(1 downto 0);
branch: out std_logic_vector(2 downto 0);
br_link: out std_logic;
reg_to_mem: out std_logic;
mem_to_reg: out std_logic;
signed_imm: out std_logic;
mem_write: out std_logic_vector(1 downto 0);
mem_read: out std_logic_vector(1 downto 0);
signed_rd: out std_logic;
shift: out std_logic
);
end control;
architecture arch_control of control is
begin
process(opcode, funct, rtx)
begin
case opcode is
when "000000" => -- R type
case funct is
when "000000" => -- SLL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '1';
alu_op <= "1001";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000010" => -- SRL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '1';
alu_op <= "1010";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000011" => -- SRA
reg_dst <= '1';
reg_write <= '1';
alu_src <= '1';
alu_op <= "1011";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000100" => -- SLLV
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "1100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000110" => -- SRLV
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "1101";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "000111" => -- SRAV
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "1110";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '1';
when "001000" => -- JR
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0100";
jump <= "10";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001001" => -- JALR
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0100";
jump <= "10";
branch <= "000";
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "001100" => -- SYSCALL
-- when "001101" => -- BREAK
-- when "010000" => -- MFHI
-- when "010001" => -- MTHI
-- when "010010" => -- MFLO
-- when "010011" => -- MTLO
-- when "011000" => -- MULT
-- when "011001" => -- MULTU
-- when "011010" => -- DIV
-- when "011011" => -- DIVU
-- when "100000" => -- ADD
when "100001" => -- ADDU
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "100010" => -- SUB
when "100011" => -- SUBU
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100100" => -- AND
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100101" => -- OR
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0001";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100110" => -- XOR
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0010";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "100111" => -- NOR
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0011";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101010" => -- SLT
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0111";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101011" => -- SLTU
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "1000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when others => -- all other R type instructions, generate a NOP
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
when "000001" =>
case rtx is
when "00000" => -- BLTZ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "101";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "00001" => -- BGEZ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "110";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "10000" => -- BLTZAL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "101";
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "10001" => -- BGEZAL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "110";
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when others => -- invalid instruction, generate a NOP
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
when "000010" => -- J
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0100";
jump <= "01";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000011" => -- JAL
reg_dst <= '1';
reg_write <= '1';
alu_src <= '0';
alu_op <= "0100";
jump <= "01";
branch <= "000";
br_link <= '1';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000100" => -- BEQ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "001";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000101" => -- BNE
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "010";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000110" => -- BLEZ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "011";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "000111" => -- BGTZ
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0101";
jump <= "00";
branch <= "100";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "001000" => -- ADDI
when "001001" => -- ADDIU
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001010" => -- SLTI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0111";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001011" => -- SLTIU
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "1000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001100" => -- ANDI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0000";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001101" => -- ORI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0001";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001110" => -- XORI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0010";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "001111" => -- LUI
reg_dst <= '0';
reg_write <= '1';
alu_src <= '1';
alu_op <= "0110";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "010000" => -- COP0
-- when "010001" => -- COP1
-- when "010010" => -- COP2
-- when "010011" => -- COP3
when "100000" => -- LB
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "01";
signed_rd <= '1';
shift <= '0';
when "100001" => -- LH
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "10";
signed_rd <= '1';
shift <= '0';
-- when "100010" => -- LWL
when "100011" => -- LW
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "11";
signed_rd <= '0';
shift <= '0';
when "100100" => -- LBU
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "01";
signed_rd <= '0';
shift <= '0';
when "100101" => -- LHU
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '1';
signed_imm <= '1';
mem_write <= "00";
mem_read <= "10";
signed_rd <= '0';
shift <= '0';
-- when "100110" => -- LWR
when "101000" => -- SB
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "01";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
when "101001" => -- SH
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "10";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "101010" => -- SWL
when "101011" => -- SW
reg_dst <= '0';
reg_write <= '0';
alu_src <= '1';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '1';
mem_to_reg <= '0';
signed_imm <= '1';
mem_write <= "11";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
-- when "101110" => -- SWR
-- when "110000" => -- LWC0
-- when "110001" => -- LWC1
-- when "110010" => -- LWC2
-- when "110011" => -- LWC3
-- when "111000" => -- SWC0
-- when "111001" => -- SWC1
-- when "111010" => -- SWC2
-- when "111011" => -- SWC3
when others => -- invalid instruction, generate a NOP
reg_dst <= '0';
reg_write <= '0';
alu_src <= '0';
alu_op <= "0100";
jump <= "00";
branch <= "000";
br_link <= '0';
reg_to_mem <= '0';
mem_to_reg <= '0';
signed_imm <= '0';
mem_write <= "00";
mem_read <= "00";
signed_rd <= '0';
shift <= '0';
end case;
end process;
end arch_control;
| gpl-2.0 | e25efe688b4e2a0bd46bfca05ac01578 | 0.382468 | 2.640863 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/serport_master_tb.vhd | 1 | 4,591 | -- $Id: serport_master_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_master_tb - sim
-- Description: serial port: serial port module, master side (SIM only!)
--
-- Dependencies: serport_uart_rxtx_ab_tb
-- serport_xonrx_tb
-- serport_xontx_tb
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1087 1.1 add 100 ps RXSD,TXSD delay to allow clock jitter
-- 2016-01-03 724 1.0 Initial version (copied from serport_master)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_master_tb is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
ENAXON : in slbit := '0'; -- enable xon/xoff handling
ENAESC : in slbit := '0'; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXOK : in slbit := '1'; -- rx channel ok
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit := '0' -- transmit cts (uart view, act.low)
);
end serport_master_tb;
architecture sim of serport_master_tb is
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal UART_RXSD : slbit := '0';
signal UART_TXSD : slbit := '0';
signal TXOK : slbit := '0';
begin
UART : entity work.serport_uart_rxtx_tb -- uart, rx+tx combo
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => open,
TXSD => UART_TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
-- add some minor (100 ps) delay in the serial data path.
-- this makes transmission immune against small clock jitter between test
-- bench and UUT (e.g. from sfs re-phasing done differently in tb and UUT).
TXSD <= UART_TXSD after 100 ps;
UART_RXSD <= RXSD after 100 ps;
XONRX : entity work.serport_xonrx_tb -- xon/xoff logic rx path
port map (
CLK => CLK,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => '0',
RXOVR => open,
TXOK => TXOK
);
XONTX : entity work.serport_xontx_tb -- xon/xoff logic tx path
port map (
CLK => CLK,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => RXOK,
TXOK => TXOK
);
RXRTS_N <= not RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
end sim;
| gpl-3.0 | 5030795b3de3983e1f2d00739d0075aa | 0.525158 | 3.903912 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys4/tb/sys_conf_sim.vhd | 1 | 2,446 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n4 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.3 use cram_*delay functions to determine delays
-- 2016-07-10 786 1.2 memctl with page mode, new read1delay
-- 2016-06-18 775 1.1.1 use PLL for clkser_gentype
-- 2016-03-29 756 1.1 use serport_2clock2 -> define clkser
-- 2013-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | 02be4b395f4395c2215452ad81ad20d9 | 0.627555 | 3.504298 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd | 1 | 17,470 | -- $Id: sys_w11a_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n4d - syn
-- Description: w11a design for nexys4 DDR (with dram via mig)
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_4line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib//nexys4d/sramif_mig_nexys4d
-- bplib/fx2rlink/ioleds_sp1c
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_sys_w11a_n4d
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz
-- 2022-07-05 1247 2022.1 xc7a100t-1 6805 8961 869 17.5 3282 80
-- 2019-08-10 1201 2019.1 xc7a100t-1 6850 10258 901 17.5 3563 80
-- 2019-05-19 1150 2017.2 xc7a100t-1 6811 10322 901 17.5 3496 80 +dz11
-- 2019-02-02 1108 2018.3 xc7a100t-1 6558 9537 814 17.0 3443 80
-- 2019-02-02 1108 2017.2 xc7a100t-1 6538 9496 798 17.0 3308 80
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.1.1 use bufg_unisim
-- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK
-- 2019-01-02 1101 1.0 Initial version (derived from sys_w11a_n4 and arty)
------------------------------------------------------------------------------
--
-- w11a test design for nexys4d
-- w11a + rlink + serport
--
-- Usage of Nexys 4 DDR Switches, Buttons, LEDs
--
-- SWI(15:5): no function (only connected to sn_humanio_rbus)
-- (5): select DSP(7:4) display
-- 0 abclkdiv & abclkdiv_f
-- 1 PC
-- (4): select DSP(3:0) display
-- 0 DISPREG
-- 1 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2): unused-reserved (USB port select)
-- (1): 1 enable XON
-- (0): unused-reserved (serial port select)
--
-- LEDs if SWI(3) = 1
-- (15:0) DR emulation; shows R0 during wait like 11/45+70
--
-- LEDs if SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5)
-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4)
-- DP(3:0) shows IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.miglib.all;
use work.miglib_nexys4d.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n4d is -- top level
-- implements nexys4d_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end sys_w11a_n4d;
architecture syn of sys_w11a_n4d is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"08"; -- nexys4d
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 12, -- vco 1000 MHz
CLK2_OUTDIV => 12, -- mig sys 100.0 MHz (unused)
CLK3_OUTDIV => 6, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => open,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLK_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_CLK
);
GBL_RESET <= not LOCKED_CLK;
IOB_RS232 : bp_rs232_4line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 9, -- 512 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit
PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit
PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEMCTL: sramif_mig_nexys4d -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => GBL_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLK100_BUF,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR2_DQ => DDR2_DQ,
DDR2_DQS_P => DDR2_DQS_P,
DDR2_DQS_N => DDR2_DQS_N,
DDR2_ADDR => DDR2_ADDR,
DDR2_BA => DDR2_BA,
DDR2_RAS_N => DDR2_RAS_N,
DDR2_CAS_N => DDR2_CAS_N,
DDR2_WE_N => DDR2_WE_N,
DDR2_CK_P => DDR2_CK_P,
DDR2_CK_N => DDR2_CK_N,
DDR2_CKE => DDR2_CKE,
DDR2_CS_N => DDR2_CS_N,
DDR2_DM => DDR2_DM,
DDR2_ODT => DDR2_ODT
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => DSP_DP(3 downto 0)
);
DSP_DP(7 downto 4) <= "0010";
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 3)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SMRB : sysmonx_rbus_base -- always instantiated, needed for mig
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
-- setup unused outputs in nexys4
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 73b0f9d51b29819716747147f61fc293 | 0.482255 | 3.21909 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32im_nodiv/cpu.vhd | 1 | 1,925 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity processor is
port ( clk_i: in std_logic;
rst_i: in std_logic;
stall_i: in std_logic;
addr_o: out std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
data_w_o: out std_logic_vector(3 downto 0);
data_mode_o: out std_logic_vector(2 downto 0);
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0)
);
end processor;
architecture arch_processor of processor is
signal irq_cpu, irq_ack_cpu, exception_cpu, data_b_cpu, data_h_cpu, data_access_cpu: std_logic;
signal irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
signal data_w_cpu: std_logic_vector(3 downto 0);
begin
data_mode_o <= data_b_cpu & data_h_cpu & data_access_cpu;
-- HF-RISC core
core: entity work.datapath
port map( clock => clk_i,
reset => rst_i,
stall => stall_i,
irq_vector => irq_vector_cpu,
irq => irq_cpu,
irq_ack => irq_ack_cpu,
exception => exception_cpu,
address => address_cpu,
data_in => data_in_cpu,
data_out => data_out_cpu,
data_w => data_w_cpu,
data_b => data_b_cpu,
data_h => data_h_cpu,
data_access => data_access_cpu
);
-- interrupt controller
int_control: entity work.interrupt_controller
port map(
clock => clk_i,
reset => rst_i,
stall => stall_i,
irq_vector_cpu => irq_vector_cpu,
irq_cpu => irq_cpu,
irq_ack_cpu => irq_ack_cpu,
exception_cpu => exception_cpu,
address_cpu => address_cpu,
data_in_cpu => data_in_cpu,
data_out_cpu => data_out_cpu,
data_w_cpu => data_w_cpu,
data_access_cpu => data_access_cpu,
addr_mem => addr_o,
data_read_mem => data_i,
data_write_mem => data_o,
data_we_mem => data_w_o,
extio_in => extio_in,
extio_out => extio_out
);
end arch_processor;
| gpl-2.0 | c717a26ea0c5d94aaa04a7b8dc4deed1 | 0.654545 | 2.542933 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/serport_uart_rxtx_tb.vhd | 1 | 2,391 | -- $Id: serport_uart_rxtx_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rxtx_tb - syn
-- Description: serial port UART - transmitter + receiver (SIM only!)
--
-- Dependencies: serport_uart_rx_tb
-- serport_uart_tx_tb
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-03 724 1.0 Initial version (copied from serport_uart_rxtx)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_rxtx_tb is -- serial port uart: rx+tx combo
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end serport_uart_rxtx_tb;
architecture sim of serport_uart_rxtx_tb is
begin
RX : entity work.serport_uart_rx_tb
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
TX : entity work.serport_uart_tx_tb
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end sim;
| gpl-3.0 | a8b5620467254abeddc401b7b7bcae33 | 0.516102 | 4.108247 | false | false | false | false |
wfjm/w11 | rtl/w11a/tb/tbd_tba_pdp11core.vhd | 1 | 6,783 | -- $Id: tbd_tba_pdp11core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_tba_pdp11core - syn
-- Description: tbd for testing pdp11_core_rbus plus ibdr_minisys
--
-- Dependencies: genlib/clkdivce
-- pdp11_core_rbus
-- pdp11_core
-- pdp11_bram
-- ibus/ibdr_minisys
-- rbus/rb_sres_or_2
--
-- Test bench: tb_rlink_tba_pdp11core
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.6.2 use rbaddr_ constants
-- 2018-10-07 1054 1.6.1 drop ITIMER from core
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2011-11-18 427 1.4.1 now numeric_std clean
-- 2010-12-30 351 1.4 renamed from tbd_pdp11core_rri; rbv3 port;
-- 2010-10-23 335 1.3.2 rename RRI_LAM->RB_LAM;
-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-11 303 1.3 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.2.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- 2010-05-01 285 1.2 port to rri V2 interface
-- 2009-07-12 233 1.1.4 adapt to ibdr_minisys interface changes
-- 2008-08-22 161 1.1.3 use iblib, ibdlib
-- 2008-04-18 136 1.1.2 add RESET for ibdr_minisys
-- 2008-02-23 118 1.1.1 use sys_conf for bram size
-- 2008-02-17 117 1.1 adapt to em_ core interface; use pdp11_bram
-- 2008-01-20 113 1.0 Initial version (factored out from rrirp_pdp11core,
-- add rri access to ibdr now)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
use work.rblib.all;
entity tbd_tba_pdp11core is -- tbd pdp11_core_rbus plus ibdr_minisys
-- implements rbtba_aif
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ_aval : in slbit; -- rbus: request - aval
RB_MREQ_re : in slbit; -- rbus: request - re
RB_MREQ_we : in slbit; -- rbus: request - we
RB_MREQ_initt : in slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : in slv16; -- rbus: request - addr
RB_MREQ_din : in slv16; -- rbus: request - din
RB_SRES_ack : out slbit; -- rbus: response - ack
RB_SRES_busy : out slbit; -- rbus: response - busy
RB_SRES_err : out slbit; -- rbus: response - err
RB_SRES_dout : out slv16; -- rbus: response - dout
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4 -- rbus: status flags
);
end entity tbd_tba_pdp11core;
architecture syn of tbd_tba_pdp11core is
signal CE_USEC : slbit := '0';
signal GRESET : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal BRESET : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES : ib_sres_type := ib_sres_init;
begin
RB_MREQ.aval <= RB_MREQ_aval;
RB_MREQ.re <= RB_MREQ_re;
RB_MREQ.we <= RB_MREQ_we;
RB_MREQ.init <= RB_MREQ_initt;
RB_MREQ.addr <= RB_MREQ_addr;
RB_MREQ.din <= RB_MREQ_din;
RB_SRES_ack <= RB_SRES.ack;
RB_SRES_busy <= RB_SRES.busy;
RB_SRES_err <= RB_SRES.err;
RB_SRES_dout <= RB_SRES.dout;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => open
);
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_cpu0_core,
RB_ADDR_IBUS => rbaddr_cpu0_ibus)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM(0),
GRESET => GRESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT
);
W11A : pdp11_core
port map (
CLK => CLK,
RESET => GRESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
ESUSP_O => open,
ESUSP_I => '0',
HBPT => '0',
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ,
IB_SRES_M => IB_SRES,
DM_STAT_SE => open,
DM_STAT_DP => open,
DM_STAT_VM => open,
DM_STAT_CO => open
);
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => GRESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
RESET => GRESET,
BRESET => BRESET,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => open
);
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_IBD,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | bf75600789e42a50390af93381a3fce6 | 0.525431 | 3.080381 | false | false | false | false |
project-oak/silveroak | investigations/fpga/zcu104/leds/leds.vhdl | 1 | 2,100 | --
-- Copyright 2019 The Project Oak Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- A simple test program for the Xilinx ZCU104605 development board that
-- makes the user GPIO LEDs flash for the binary sequence 0..7, with a
-- reset from the push button GPIO_PB_SW3 SW18 at a 1 second frequency.
package counter_package is
subtype count_type is natural range 0 to 15;
end package counter_package;
library ieee;
use ieee.std_logic_1164.all;
use work.counter_package.all;
entity leds is
port (signal CLK_125_P : in std_ulogic; -- 125MHz clock P at pin H11 LVDS
signal CLK_125_N : in std_ulogic; -- 125MHz clock N at pin G11 LVDS
signal GPIO_PB_SW3 : in std_ulogic; -- pin C3 LVCMOS33 connected to push-button GPIO_PB_SW3 SW18
signal GPIO_LED : out count_type -- LEDs at pins D5 (LSB), D6, A5, B5 (MSB) LVCMOS33
);
end entity leds;
library unisim;
use unisim.vcomponents.all;
architecture behavioral of leds is
signal count : count_type := 0 ;
signal clk : std_ulogic;
begin
clock_buffer : ibufgds port map (o => clk, i => CLK_125_P, ib => CLK_125_N);
clock_divider : process is
variable divider_count : natural := 0;
begin
wait until clk'event and clk = '1';
if GPIO_PB_SW3 = '1' then
count <= 0;
divider_count := 0;
else
if divider_count = 125000000 then
divider_count := 0;
count <= (count + 1) mod 16;
else
divider_count := divider_count + 1;
end if;
end if;
end process clock_divider;
GPIO_LED <= count;
end architecture behavioral;
| apache-2.0 | c6aa434ad656d4509c334b21a084155f | 0.683333 | 3.633218 | false | false | false | false |
wfjm/w11 | rtl/bplib/micron/tb/tb_mt45w8mw16b.vhd | 1 | 7,461 | -- $Id: tb_mt45w8mw16b.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_mt45w8mw16b - sim
-- Description: Test bench for mt45w8mw16b memory model
--
-- Dependencies: mt45w8mw16b [UUT]
-- simlib/simbididly
--
-- To test: mt45w8mw16b
--
-- Verified (with tb_mt45w8mw16b_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2016-07-16 787 - 0.33 - - c:ok
-- 2010-05-16 291 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 787 1.2 test also CRE; use simbididly;
-- 2011-11-21 432 1.1.1 now numeric_std clean
-- 2010-05-16 291 1.0 Initial version (cloned from tb_is61lv25616al)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_mt45w8mw16b is
end tb_mt45w8mw16b;
architecture sim of tb_mt45w8mw16b is
constant pcb_delay : Delay_length := 1 ns;
signal MM_CE_N : slbit := '1';
signal MM_OE_N : slbit := '1';
signal MM_WE_N : slbit := '1';
signal MM_UB_N : slbit := '1';
signal MM_LB_N : slbit := '1';
signal MM_CRE : slbit := '0';
signal MM_MWAIT : slbit := '0';
signal MM_ADDR : slv23 := (others=>'0');
signal MM_DATA : slv16 := (others=>'Z');
signal TB_CE_N : slbit := '1';
signal TB_OE_N : slbit := '1';
signal TB_WE_N : slbit := '1';
signal TB_UB_N : slbit := '1';
signal TB_LB_N : slbit := '1';
signal TB_CRE : slbit := '0';
signal TB_MWAIT : slbit := '0';
signal TB_ADDR : slv23 := (others=>'0');
signal TB_DATA : slv16 := (others=>'Z');
begin
UUT : entity work.mt45w8mw16b
port map (
CLK => '0',
CE_N => MM_CE_N,
OE_N => MM_OE_N,
WE_N => MM_WE_N,
UB_N => MM_UB_N,
LB_N => MM_LB_N,
ADV_N => '0',
CRE => MM_CRE,
MWAIT => MM_MWAIT,
ADDR => MM_ADDR,
DATA => MM_DATA
);
MM_CE_N <= TB_CE_N after pcb_delay;
MM_OE_N <= TB_OE_N after pcb_delay;
MM_WE_N <= TB_WE_N after pcb_delay;
MM_UB_N <= TB_UB_N after pcb_delay;
MM_LB_N <= TB_LB_N after pcb_delay;
MM_CRE <= TB_CRE after pcb_delay;
MM_ADDR <= TB_ADDR after pcb_delay;
TB_MWAIT <= MM_MWAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => TB_DATA,
B => MM_DATA);
proc_stim: process
file fstim : text open read_mode is "tb_mt45w8mw16b_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idtime : Delay_length := 0 ns;
variable imatch : boolean := false;
variable ival : slbit := '0';
variable ival2 : slv2 := (others=>'0');
variable ival16 : slv16 := (others=>'0');
variable ival23 : slv23 := (others=>'0');
variable ice : slbit := '0';
variable ioe : slbit := '0';
variable iwe : slbit := '0';
variable ibe : slv2 := "00";
variable icre : slbit := '0';
variable iaddr : slv23 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ide : slbit := '0';
variable idchk : slv16 := (others=>'0');
begin
-- initial signal driver settings
TB_CE_N <= '1';
TB_OE_N <= '1';
TB_WE_N <= '1';
TB_UB_N <= '1';
TB_LB_N <= '1';
TB_CRE <= '0';
TB_ADDR <= (others=>'0');
TB_DATA <= (others=>'Z');
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wdo " => -- wdo
read_ea(iline, idtime);
wait for idtime;
readtagval_ea(iline, "ce", imatch, ival);
if imatch then ice := ival; end if;
readtagval_ea(iline, "cre", imatch, ival);
if imatch then icre := ival; end if;
readtagval_ea(iline, "oe", imatch, ival);
if imatch then ioe := ival; end if;
readtagval_ea(iline, "we", imatch, ival);
if imatch then iwe := ival; end if;
readtagval_ea(iline, "be", imatch, ival2, 2);
if imatch then ibe := ival2; end if;
readtagval_ea(iline, "a", imatch, ival23, 16);
if imatch then iaddr := ival23; end if;
readtagval_ea(iline, "de", imatch, ival);
if imatch then ide := ival; end if;
readtagval_ea(iline, "d", imatch, ival16, 16);
if imatch then idata := ival16; end if;
TB_CE_N <= not ice;
TB_OE_N <= not ioe;
TB_WE_N <= not iwe;
TB_LB_N <= not ibe(0);
TB_UB_N <= not ibe(1);
TB_CRE <= icre;
TB_ADDR <= iaddr;
if ide = '1' then
TB_DATA <= idata;
else
TB_DATA <= (others=>'Z');
end if;
write(oline, now, right, 12);
write(oline, string'(": wdo "));
write(oline, string'(" ce="));
write(oline, ice);
write(oline, string'(" oe="));
write(oline, ioe);
write(oline, string'(" we="));
write(oline, iwe);
if icre = '0' then
write(oline, string'(" be="));
write(oline, ibe, right, 2);
else
write(oline, string'(" cre=1"));
end if;
write(oline, string'(" a="));
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" de="));
write(oline, ide);
if ide = '1' then
write(oline, string'(" d="));
writegen(oline, idata, right, 4, 16);
end if;
readtagval_ea(iline, "D", imatch, idchk, 16);
if imatch then
write(oline, string'(" D="));
writegen(oline, TB_DATA, right, 4, 16);
write(oline, string'(" CHECK"));
if TB_DATA = idchk then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL exp="));
writegen(oline, idchk, right, 4, 16);
end if;
end if;
writeline(output, oline);
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop;
write(oline, now, right, 12);
write(oline, string'(": DONE"));
writeline(output, oline);
wait; -- suspend proc_stim forever
-- no clock, sim will end
end process proc_stim;
end sim;
| gpl-3.0 | 045d2ea1008b3435cb6a3c069190b2c7 | 0.487066 | 3.499531 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_InterruptController_Device.vhdl | 1 | 10,811 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze Interrupt Controller with up to 32 ports.
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.components.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_InterruptController_Device is
generic (
DEBUG : BOOLEAN := FALSE;
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
PORTS : POSITIVE := 4
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
-- PicoBlaze interrupt interface (direct coupled)
PB_Interrupt : out STD_LOGIC;
PB_Interrupt_Ack : in STD_LOGIC;
-- Interrupt source interface
Dev_Interrupt : in STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Dev_Interrupt_Ack : out STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Dev_Interrupt_Message : in T_SLVV_8(PORTS - 1 downto 0)
);
end entity;
architecture rtl of pb_InterruptController_Device is
attribute KEEP : BOOLEAN;
constant REQUIRED_REG_BYTES : POSITIVE := div_ceil(PORTS, 8);
-- Regarding REQUIRED_REG_BYTES, the position of the enable/disable marker bit is moved from LSB to MSB
-- Example 1:
-- REQUIRED_REG_BYTES = 1
-- -> no bit is required to address the register in the field, because it's only one byte
-- => enable/disable bit is located at bit 0
--
-- Example 2:
-- REQUIRED_REG_BYTES = 3
-- -> 2 bits are required to address 3 registers in the field [23:0]
-- -> [1:0] is used to address the correct byte/register
-- => enable/disable bit is located at bit 2
constant BIT_EN_DIS : NATURAL := log2ceil(REQUIRED_REG_BYTES);
constant BIT_VEC_MES : NATURAL := log2ceil(REQUIRED_REG_BYTES);
constant REG_WO_ENABLE_BIT_VALUE : STD_LOGIC := '0';
constant REG_WO_DISABLE_BIT_VALUE : STD_LOGIC := '1';
constant REG_RO_VECTOR_BIT_VALUE : STD_LOGIC := '0';
constant REG_RO_MESSAGE_BIT_VALUE : STD_LOGIC := '1';
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_InterruptEnable_slvv : T_SLVV_8(REQUIRED_REG_BYTES - 1 downto 0) := (others => (others => '0'));
signal Reg_InterruptEnable : STD_LOGIC_VECTOR((REQUIRED_REG_BYTES * 8) - 1 downto 0);
type T_STATE is (ST_IDLE, ST_INTERRUPT_PENDING, ST_INTERRUPT_MESSAGE);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal Interrupt_re : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal InterruptPending_r : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := (others => '0');
signal InterruptMessages_d : T_SLVV_8(PORTS - 1 downto 0) := (others => (others => '0'));
signal InterruptRequestsOpen : STD_LOGIC;
signal InterruptRequestVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal InterruptSource_Read : STD_LOGIC;
signal FSM_DataOut : T_SLV_8;
signal FSM_Arbitrate : STD_LOGIC;
signal FSM_InterruptClearVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal Arb_GrantVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal Arb_GrantVector_bin : STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
attribute KEEP of FSM_Arbitrate : signal is DEBUG;
attribute KEEP of Arb_GrantVector : signal is DEBUG;
attribute KEEP of InterruptRequestVector : signal is DEBUG;
begin
assert (PORTS <= 32)
report "InterruptController supports only up to 32 interrupt sources!"
severity failure;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_Address => Address,
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Data => DataIn,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_Data => AdrDec_Data
);
process(Clock, AdrDec_WriteAddress)
variable index : NATURAL;
begin
index := to_index(AdrDec_WriteAddress(BIT_EN_DIS - 1 downto 0));
if rising_edge(Clock) then
if (Reset = '1') then
Reg_InterruptEnable_slvv <= (others => (others => '0'));
elsif (AdrDec_we = '1') then
case AdrDec_WriteAddress(BIT_EN_DIS) is
when REG_WO_ENABLE_BIT_VALUE => Reg_InterruptEnable_slvv(index) <= Reg_InterruptEnable_slvv(index) or AdrDec_Data;
when REG_WO_DISABLE_BIT_VALUE => Reg_InterruptEnable_slvv(index) <= Reg_InterruptEnable_slvv(index) and not AdrDec_Data;
when others => null;
end case;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_InterruptEnable_slvv, FSM_DataOut)
variable index : NATURAL;
begin
index := to_index(AdrDec_ReadAddress(BIT_VEC_MES - 1 downto 0));
DataOut <= FSM_DataOut;
case AdrDec_ReadAddress(BIT_VEC_MES) is
when REG_RO_VECTOR_BIT_VALUE => DataOut <= Reg_InterruptEnable_slvv(index);
when REG_RO_MESSAGE_BIT_VALUE => DataOut <= FSM_DataOut;
when others => DataOut <= (others => 'X');
end case;
InterruptSource_Read <= AdrDec_re and to_sl(AdrDec_ReadAddress(BIT_VEC_MES) = REG_RO_MESSAGE_BIT_VALUE);
end process;
Interrupt <= '0';
Message <= x"00";
genPort : for i in 0 to PORTS - 1 generate
signal Interrupt_d : STD_LOGIC := '0';
begin
Interrupt_d <= Dev_Interrupt(i) when rising_edge(Clock);
Interrupt_re(i) <= not Interrupt_d and Dev_Interrupt(i);
-- RS-FFs to latch the interrupt signal and the message
InterruptPending_r(i) <= ffrs(q => InterruptPending_r(i), rst => (Reset or FSM_InterruptClearVector(i)), set => Interrupt_re(i)) when rising_edge(Clock);
InterruptMessages_d(i) <= ffdre(q => InterruptMessages_d(i), d => Dev_Interrupt_Message(i), rst => (Reset or FSM_InterruptClearVector(i)), en => Interrupt_re(i)) when rising_edge(Clock);
end generate;
Reg_InterruptEnable <= to_slv(Reg_InterruptEnable_slvv);
InterruptRequestVector <= InterruptPending_r and Reg_InterruptEnable(InterruptPending_r'range);
InterruptRequestsOpen <= slv_or(InterruptRequestVector and not FSM_InterruptClearVector);
Arb : entity PoC.bus_Arbiter
generic map (
STRATEGY => "RR",
PORTS => PORTS,
WEIGHTS => (0 to PORTS - 1 => 1),
OUTPUT_REG => FALSE
)
port map (
Clock => Clock,
Reset => Reset,
Arbitrate => FSM_Arbitrate,
Request_Vector => InterruptRequestVector,
Grant_Vector => Arb_GrantVector,
Grant_Index => Arb_GrantVector_bin
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, InterruptRequestsOpen, Arb_GrantVector, Arb_GrantVector_bin, PB_Interrupt_Ack, InterruptSource_Read, InterruptMessages_d)
begin
NextState <= State;
PB_Interrupt <= InterruptRequestsOpen;
FSM_DataOut <= resize(Arb_GrantVector_bin, FSM_DataOut'length);
Dev_Interrupt_Ack <= (others => '0');
FSM_Arbitrate <= '0';
FSM_InterruptClearVector <= (others => '0');
case State is
when ST_IDLE =>
if (InterruptRequestsOpen = '1') then
FSM_Arbitrate <= '1';
NextState <= ST_INTERRUPT_PENDING;
end if;
when ST_INTERRUPT_PENDING =>
FSM_DataOut <= resize(Arb_GrantVector_bin, FSM_DataOut'length);
if (InterruptSource_Read = '1') then
NextState <= ST_INTERRUPT_MESSAGE;
end if;
when ST_INTERRUPT_MESSAGE =>
FSM_DataOut <= InterruptMessages_d(to_index(Arb_GrantVector_bin));
if (PB_Interrupt_Ack = '1') then
FSM_InterruptClearVector <= Arb_GrantVector;
Dev_Interrupt_Ack <= Arb_GrantVector;
if (InterruptRequestsOpen = '1') then
FSM_Arbitrate <= '1';
NextState <= ST_INTERRUPT_PENDING;
else
NextState <= ST_IDLE;
end if;
end if;
end case;
end process;
end;
| apache-2.0 | c75d276a1d4b135f45df1f6e9dc1f45c | 0.586995 | 3.362675 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01000_good.vhd | 1 | 3,690 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01000_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of variable name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01000_good is
generic (
g_Width : positive := 4 -- Data Width
);
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Data : in std_logic_vector(g_Width-1 downto 0); -- Data from which to count ones
o_Nb_One : out std_logic_vector(g_Width-1 downto 0) -- Number of ones in i_Data signal
);
end CNE_01000_good;
architecture Behavioral of CNE_01000_good is
-- Function to get the number of ones in a signal
function Get_Ones(data : in std_logic_vector(g_Width-1 downto 0)) return integer is
-- Number of ones in the input signal
variable v_Nb_Ones : integer range 0 to g_Width;
begin
v_Nb_Ones := 0;
-- Loop on each signal's bit
for i in 0 to g_Width-1 loop
if (data(i)='1') then
v_Nb_Ones := v_Nb_Ones + 1;
end if;
end loop;
return v_Nb_Ones;
end function;
-- Module output
signal Nb_One : std_logic_vector(g_Width-1 downto 0);
begin
-- Counts the number of ones in a signal and register this count.
p_Count_Ones:process(i_Reset_n,i_Clock)
begin
if (i_Reset_n='0') then
Nb_One <= (others => '0');
elsif (rising_edge(i_Clock)) then
Nb_One <= std_logic_vector(to_unsigned(Get_Ones(i_Data),Nb_One'length));
end if;
end process;
o_Nb_One <= Nb_One;
end Behavioral; | gpl-3.0 | 4ef565126046b5738d1d68ac82d50da5 | 0.501626 | 4.336075 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_cache.vhd | 1 | 18,352 | -- $Id: pdp11_cache.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_cache - syn
-- Description: pdp11: cache
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
--
-- Synthesis results
-- clw = cache line width (tag+data)
-- eff = efficiency (fraction of used BRAM colums)
-- - 2016-03-22 (r750) with viv 2015.4 for xc7a100t-1
-- TWIDTH size flop lutl lutm RAMB36 RAMB18 bram clw eff
-- 9 8k 43 106 0 0 5 2.5 45 100%
-- 8 16k 43 109 0 5 0 5.0 44 97%
-- 7 32k 43 107 0 10 4 12.0 43 89%
-- 6 64k 43 106 0 19 4 21.0 42 100%
-- 5 128k 58! 106 0 41 0 41.0 41 100%
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-06 1053 1.2 drop CHIT, use DM_STAT_CA, detailed monitoring
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-03-22 751 1.1 now configurable size (8,16,32,64,128 kB)
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim
-- factor invariants out of if's; fix tag rmiss logic
-- 2008-02-17 117 1.0.1 use em_(mreq|sres) interface; use req,we for mem
-- recode, ghdl doesn't like partial vector port maps
-- 2008-02-16 116 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.pdp11.all;
entity pdp11_cache is -- cache
generic (
TWIDTH : positive := 9); -- tag width (5 to 9)
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type; -- em response
FMISS : in slbit; -- force miss
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_CA : out dm_stat_ca_type -- debug and monitor status - cache
);
end pdp11_cache;
architecture syn of pdp11_cache is
constant lwidth: positive := 22-2-TWIDTH; -- line address width
subtype t_range is integer range TWIDTH-1 downto 0; -- tag value regs
subtype l_range is integer range lwidth-1 downto 0; -- line addr regs
subtype af_tag is integer range 22-1 downto 22-TWIDTH; -- tag address
subtype af_line is integer range 22-TWIDTH-1 downto 2; -- line address
subtype df_byte3 is integer range 31 downto 24;
subtype df_byte2 is integer range 23 downto 16;
subtype df_byte1 is integer range 15 downto 8;
subtype df_byte0 is integer range 7 downto 0;
subtype df_word1 is integer range 31 downto 16;
subtype df_word0 is integer range 15 downto 0;
type state_type is (
s_idle, -- s_idle: wait for req
s_read, -- s_read: read cycle
s_rmiss, -- s_rmiss: read miss
s_write -- s_write: write cycle
);
type regs_type is record
state : state_type; -- state
addr_w : slbit; -- address - word select
addr_l : slv(l_range); -- address - cache line address
addr_t : slv(t_range); -- address - cache tag part
be : slv4; -- byte enables (at 4 byte level)
di : slv16; -- data
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0', -- addr_w
slv(to_unsigned(0,lwidth)), -- addr_l
slv(to_unsigned(0,TWIDTH)), -- addr_t
(others=>'0'), -- be
(others=>'0') -- di
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal CMEM_TAG_CEA : slbit := '0';
signal CMEM_TAG_CEB : slbit := '0';
signal CMEM_TAG_WEA : slbit := '0';
signal CMEM_TAG_WEB : slbit := '0';
signal CMEM_TAG_DIB : slv(t_range) := (others=>'0');
signal CMEM_TAG_DOA : slv(t_range) := (others=>'0');
signal CMEM_DAT_CEA : slbit := '0';
signal CMEM_DAT_CEB : slbit := '0';
signal CMEM_DAT_WEA : slv4 := "0000";
signal CMEM_DAT_WEB : slv4 := "0000";
signal CMEM_DIA_0 : slv9 := (others=>'0');
signal CMEM_DIA_1 : slv9 := (others=>'0');
signal CMEM_DIA_2 : slv9 := (others=>'0');
signal CMEM_DIA_3 : slv9 := (others=>'0');
signal CMEM_DIB_0 : slv9 := (others=>'0');
signal CMEM_DIB_1 : slv9 := (others=>'0');
signal CMEM_DIB_2 : slv9 := (others=>'0');
signal CMEM_DIB_3 : slv9 := (others=>'0');
signal CMEM_DOA_0 : slv9 := (others=>'0');
signal CMEM_DOA_1 : slv9 := (others=>'0');
signal CMEM_DOA_2 : slv9 := (others=>'0');
signal CMEM_DOA_3 : slv9 := (others=>'0');
begin
assert TWIDTH>=5 and TWIDTH<=9
report "assert(TWIDTH>=5 and TWIDTH<=9): unsupported TWIDTH"
severity failure;
CMEM_TAG : ram_2swsr_rfirst_gen
generic map (
AWIDTH => lwidth,
DWIDTH => twidth)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_TAG_CEA,
ENB => CMEM_TAG_CEB,
WEA => CMEM_TAG_WEA,
WEB => CMEM_TAG_WEB,
ADDRA => EM_MREQ.addr(af_line),
ADDRB => R_REGS.addr_l,
DIA => EM_MREQ.addr(af_tag),
DIB => CMEM_TAG_DIB,
DOA => CMEM_TAG_DOA,
DOB => open
);
CMEM_DAT0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => lwidth,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_DAT_CEA,
ENB => CMEM_DAT_CEB,
WEA => CMEM_DAT_WEA(0),
WEB => CMEM_DAT_WEB(0),
ADDRA => EM_MREQ.addr(af_line),
ADDRB => R_REGS.addr_l,
DIA => CMEM_DIA_0,
DIB => CMEM_DIB_0,
DOA => CMEM_DOA_0,
DOB => open
);
CMEM_DAT1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => lwidth,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_DAT_CEA,
ENB => CMEM_DAT_CEB,
WEA => CMEM_DAT_WEA(1),
WEB => CMEM_DAT_WEB(1),
ADDRA => EM_MREQ.addr(af_line),
ADDRB => R_REGS.addr_l,
DIA => CMEM_DIA_1,
DIB => CMEM_DIB_1,
DOA => CMEM_DOA_1,
DOB => open
);
CMEM_DAT2 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => lwidth,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_DAT_CEA,
ENB => CMEM_DAT_CEB,
WEA => CMEM_DAT_WEA(2),
WEB => CMEM_DAT_WEB(2),
ADDRA => EM_MREQ.addr(af_line),
ADDRB => R_REGS.addr_l,
DIA => CMEM_DIA_2,
DIB => CMEM_DIB_2,
DOA => CMEM_DOA_2,
DOB => open
);
CMEM_DAT3 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => lwidth,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_DAT_CEA,
ENB => CMEM_DAT_CEB,
WEA => CMEM_DAT_WEA(3),
WEB => CMEM_DAT_WEB(3),
ADDRA => EM_MREQ.addr(af_line),
ADDRB => R_REGS.addr_l,
DIA => CMEM_DIA_3,
DIB => CMEM_DIB_3,
DOA => CMEM_DOA_3,
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, EM_MREQ, FMISS,
CMEM_TAG_DOA,
CMEM_DOA_0, CMEM_DOA_1, CMEM_DOA_2, CMEM_DOA_3,
MEM_BUSY, MEM_ACK_R, MEM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iaddr_w : slbit := '0';
variable iaddr_l : slv(l_range) := (others=>'0');
variable iaddr_t : slv(t_range) := (others=>'0');
variable itagok : slbit := '0';
variable ivalok : slbit := '0';
variable icmem_tag_cea : slbit := '0';
variable icmem_tag_ceb : slbit := '0';
variable icmem_tag_wea : slbit := '0';
variable icmem_tag_web : slbit := '0';
variable icmem_tag_dib : slv(t_range) := (others=>'0');
variable icmem_dat_cea : slbit := '0';
variable icmem_dat_ceb : slbit := '0';
variable icmem_dat_wea : slv4 := "0000";
variable icmem_dat_web : slv4 := "0000";
variable icmem_val_doa : slv4 := "0000";
variable icmem_dat_doa : slv32 := (others=>'0');
variable icmem_val_dib : slv4 := "0000";
variable icmem_dat_dib : slv32 := (others=>'0');
variable iackr : slbit := '0';
variable iackw : slbit := '0';
variable iosel : slv2 := "11";
variable istat : dm_stat_ca_type := dm_stat_ca_init;
variable imem_reqr : slbit := '0';
variable imem_reqw : slbit := '0';
variable imem_be : slv4 := "0000";
begin
r := R_REGS;
n := R_REGS;
iaddr_w := EM_MREQ.addr(1); -- get word select
iaddr_l := EM_MREQ.addr(af_line); -- get cache line addr
iaddr_t := EM_MREQ.addr(af_tag); -- get cache tag part
icmem_tag_cea := '0';
icmem_tag_ceb := '0';
icmem_tag_wea := '0';
icmem_tag_web := '0';
icmem_tag_dib := r.addr_t; -- default, local define whenver used
icmem_dat_cea := '0';
icmem_dat_ceb := '0';
icmem_dat_wea := "0000";
icmem_dat_web := "0000";
icmem_val_dib := "0000";
icmem_dat_dib := MEM_DO; -- default, local define whenver used
icmem_val_doa(0) := CMEM_DOA_0(8);
icmem_dat_doa(df_byte0) := CMEM_DOA_0(df_byte0);
icmem_val_doa(1) := CMEM_DOA_1(8);
icmem_dat_doa(df_byte1) := CMEM_DOA_1(df_byte0);
icmem_val_doa(2) := CMEM_DOA_2(8);
icmem_dat_doa(df_byte2) := CMEM_DOA_2(df_byte0);
icmem_val_doa(3) := CMEM_DOA_3(8);
icmem_dat_doa(df_byte3) := CMEM_DOA_3(df_byte0);
itagok := '0';
if CMEM_TAG_DOA = r.addr_t then -- cache tag hit
itagok := '1';
end if;
ivalok := '0';
if (icmem_val_doa and r.be) = r.be then
ivalok := '1';
end if;
iackr := '0';
iackw := '0';
iosel := "11"; -- default to ext. mem data
-- this prevents U's from cache bram's
-- to propagate to dout in beginning...
istat := dm_stat_ca_init;
imem_reqr := '0';
imem_reqw := '0';
imem_be := r.be;
case r.state is
when s_idle => -- s_idle: wait for req
n.addr_w := iaddr_w; -- capture address: word select
n.addr_l := iaddr_l; -- capture address: cache line addr
n.addr_t := iaddr_t; -- capture address: cache tag part
n.be := "0000";
icmem_tag_cea := '1'; -- access cache tag port A
icmem_dat_cea := '1'; -- access cache data port A
if iaddr_w = '0' then -- capture byte enables at 4 byte lvl
n.be(1 downto 0) := EM_MREQ.be;
else
n.be(3 downto 2) := EM_MREQ.be;
end if;
n.di := EM_MREQ.din; -- capture data
if EM_MREQ.req = '1' then -- if access requested
if EM_MREQ.we = '0' then -- if READ requested
n.state := s_read; -- next: read
else -- if WRITE requested
icmem_tag_wea := '1'; -- write tag
icmem_dat_wea := n.be; -- write cache data
n.state := s_write; -- next: write
end if;
end if;
when s_read => -- s_read: read cycle
iosel := '0' & r.addr_w; -- output select: cache
imem_be := "1111"; -- mem read: all 4 bytes
if EM_MREQ.cancel = '0' then
if FMISS='0' and itagok='1' and ivalok='1' then -- read tag&val hit
istat.rd := '1'; -- moni read request (hit)
iackr := '1'; -- signal read acknowledge
istat.rdhit := '1'; -- moni read hit
n.state := s_idle; -- next: back to idle
else -- read miss
if MEM_BUSY = '0' then -- if mem not busy
istat.rd := '1'; -- moni read request (!hit & !wait)
imem_reqr :='1'; -- request mem read
istat.rdmem := '1'; -- moni mem read
n.state := s_rmiss; -- next: rmiss, wait for mem data
else -- else mem busy
istat.wrwait := '1'; -- moni mem busy
end if;
end if;
else
n.state := s_idle; -- next: back to idle
end if;
when s_rmiss => -- s_rmiss: read cycle
iosel := '1' & r.addr_w; -- output select: memory
icmem_tag_web := '1'; -- cache update: write tag
icmem_tag_dib := r.addr_t; -- cache update: new tag
icmem_val_dib := "1111"; -- cache update: all valid
icmem_dat_dib := MEM_DO; -- cache update: data from mem
icmem_dat_web := "1111"; -- cache update: write all 4 bytes
istat.rdwait := '1'; -- moni read wait
if MEM_ACK_R = '1' then -- mem data valid
iackr := '1'; -- signal read acknowledge
icmem_tag_ceb := '1'; -- access cache tag port B
icmem_dat_ceb := '1'; -- access cache data port B
n.state := s_idle; -- next: back to idle
end if;
when s_write => -- s_write: write cycle
icmem_tag_dib := CMEM_TAG_DOA; -- cache restore: last state
icmem_dat_dib := icmem_dat_doa; -- cache restore: last state
if EM_MREQ.cancel = '0' then -- request ok
if MEM_BUSY = '0' then -- if mem not busy
istat.wr := '1'; -- moni write request
if itagok = '0' then -- if write tag miss
icmem_dat_ceb := '1'; -- access cache (invalidate)
icmem_dat_web := not r.be; -- write missed bytes
icmem_val_dib := "0000"; -- invalidate missed bytes
else
istat.wrhit := '1'; -- moni write hit
end if;
imem_reqw := '1'; -- write back to main memory
istat.wrmem := '1'; -- moni mem write
iackw := '1'; -- and done
n.state := s_idle; -- next: back to idle
else -- else mem busy
istat.wrwait := '1'; -- moni mem busy
end if;
else -- request canceled -> restore
icmem_tag_ceb := '1'; -- access cache line
icmem_tag_web := '1'; -- write tag
icmem_dat_ceb := '1'; -- access cache line
icmem_dat_web := "1111"; -- restore cache line
icmem_val_dib := icmem_val_doa; -- cache restore: last state
n.state := s_idle; -- next: back to idle
end if;
when others => null;
end case;
N_REGS <= n;
CMEM_TAG_CEA <= icmem_tag_cea;
CMEM_TAG_CEB <= icmem_tag_ceb;
CMEM_TAG_WEA <= icmem_tag_wea;
CMEM_TAG_WEB <= icmem_tag_web;
CMEM_TAG_DIB <= icmem_tag_dib;
CMEM_DAT_CEA <= icmem_dat_cea;
CMEM_DAT_CEB <= icmem_dat_ceb;
CMEM_DAT_WEA <= icmem_dat_wea;
CMEM_DAT_WEB <= icmem_dat_web;
CMEM_DIA_0(8) <= '1';
CMEM_DIA_0(df_byte0) <= EM_MREQ.din(df_byte0);
CMEM_DIA_1(8) <= '1';
CMEM_DIA_1(df_byte0) <= EM_MREQ.din(df_byte1);
CMEM_DIA_2(8) <= '1';
CMEM_DIA_2(df_byte0) <= EM_MREQ.din(df_byte0);
CMEM_DIA_3(8) <= '1';
CMEM_DIA_3(df_byte0) <= EM_MREQ.din(df_byte1);
CMEM_DIB_0(8) <= icmem_val_dib(0);
CMEM_DIB_0(df_byte0) <= icmem_dat_dib(df_byte0);
CMEM_DIB_1(8) <= icmem_val_dib(1);
CMEM_DIB_1(df_byte0) <= icmem_dat_dib(df_byte1);
CMEM_DIB_2(8) <= icmem_val_dib(2);
CMEM_DIB_2(df_byte0) <= icmem_dat_dib(df_byte2);
CMEM_DIB_3(8) <= icmem_val_dib(3);
CMEM_DIB_3(df_byte0) <= icmem_dat_dib(df_byte3);
EM_SRES <= em_sres_init;
EM_SRES.ack_r <= iackr;
EM_SRES.ack_w <= iackw;
case iosel is
when "00" => EM_SRES.dout <= icmem_dat_doa(df_word0);
when "01" => EM_SRES.dout <= icmem_dat_doa(df_word1);
when "10" => EM_SRES.dout <= MEM_DO(df_word0);
when "11" => EM_SRES.dout <= MEM_DO(df_word1);
when others => null;
end case;
DM_STAT_CA <= istat;
MEM_REQ <= imem_reqr or imem_reqw;
MEM_WE <= imem_reqw;
MEM_ADDR <= r.addr_t & r.addr_l;
MEM_BE <= imem_be;
MEM_DI <= r.di & r.di;
end process proc_next;
end syn;
| gpl-3.0 | ad239a2768bb45af4b6260a767a556be | 0.482018 | 3.403561 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rb_sres_or_4.vhd | 1 | 2,492 | -- $Id: rb_sres_or_4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_4 - syn
-- Description: rbus result or, 4 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_4 is -- rbus result or, 4 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_4;
architecture syn of rb_sres_or_4 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3, RB_SRES_4)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack or
RB_SRES_3.ack or
RB_SRES_4.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy or
RB_SRES_3.busy or
RB_SRES_4.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err or
RB_SRES_3.err or
RB_SRES_4.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout or
RB_SRES_3.dout or
RB_SRES_4.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => RB_SRES_3,
RB_SRES_4 => RB_SRES_4
);
-- synthesis translate_on
end syn;
| gpl-3.0 | 7ce7e5c788f8b1ce581948a163c3b4ab | 0.483547 | 3.142497 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tb/tb_rlink_tba.vhd | 1 | 26,622 | -- $Id: tb_rlink_tba.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink_tba - sim
-- Description: Test bench for rbus devices via rlink_tba
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- genlib/tb/clkdivce_tb
-- rlink_tba
-- rlink_core
-- rbtba_aif [UUT]
-- rlink_mon
-- rb_mon
--
-- To test: generic, any rbtba_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2-2019.1; ghdl 0.18-0.36
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 4.0.2 fix for ghdl V0.36 -Whide warnings
-- 2016-09-10 806 4.0.1 use clkdivce_tb
-- 2014-12-20 616 4.0.1 add dcnt check (with -n=) and .ndef
-- 2014-09-21 595 4.0 now full rlink v4 iface, 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-23 444 3.2 use new simclk/simclkcnt
-- 2011-11-22 432 3.1.1 now numeric_std clean
-- 2010-12-29 351 3.1 use rbtba_aif now, support _ssim level again
-- 2010-12-28 350 3.0.3 list cmd address, list send data for wreg/init
-- 2010-12-27 349 3.0.2 suppress D CHECK message for all masked rreg/rblk
-- 2010-12-25 348 3.0.1 drop RL_FLUSH support, add RL_MONI for rlink_core
-- 2010-12-24 347 3.0 rm tb_rritba->tb_rlink_tba, CP_*->RL_*;rbus v3 port
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-05 301 2.1.3 rename _rpmon -> _rbmon, .rpmon -> .rbmon
-- 2010-06-03 299 2.1.2 use sv_ prefix for shared variables
-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.4 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.1.3 default .sdef now checks for errors, ignore
-- status bits and the attn flag.
-- 2008-01-20 112 1.1.2 rename clkgen->clkdivce
-- 2007-12-23 105 1.1.1 add .dbas[io] (allows to set base for data values)
-- 2007-11-24 98 1.1 add RP_IINT support
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.genlib.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.simlib.all;
entity tb_rlink_tba is
end tb_rlink_tba;
architecture sim of tb_rlink_tba is
signal CLK : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RESET : slbit := '0';
signal TBA_CNTL : rlink_tba_cntl_type := rlink_tba_cntl_init;
signal TBA_DI : slv16 := (others=>'0');
signal TBA_STAT : rlink_tba_stat_type := rlink_tba_stat_init;
signal TBA_DO : slv16 := (others=>'0');
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RL_MONI : rl_moni_type := rl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal RB_MREQ_aval : slbit := '0';
signal RB_MREQ_re : slbit := '0';
signal RB_MREQ_we : slbit := '0';
signal RB_MREQ_initt: slbit := '0';
signal RB_MREQ_addr : slv16 := (others=>'0');
signal RB_MREQ_din : slv16 := (others=>'0');
signal RB_SRES_ack : slbit := '0';
signal RB_SRES_busy : slbit := '0';
signal RB_SRES_err : slbit := '0';
signal RB_SRES_dout : slv16 := (others=>'0');
signal RLMON_EN : slbit := '0';
signal RBMON_EN : slbit := '0';
signal N_CMD_CODE : string(1 to 4) := (others=>' ');
signal N_CMD_ADDR : slv16 := (others=>'0');
signal N_CMD_DATA : slv16 := (others=>'0');
signal N_CHK_DATA : boolean := false;
signal N_REF_DATA : slv16 := (others=>'0');
signal N_MSK_DATA : slv16 := (others=>'0');
signal N_CHK_DONE : boolean := false;
signal N_REF_DONE : slv16 := (others=>'0');
signal N_CHK_STAT : boolean := false;
signal N_REF_STAT : slv8 := (others=>'0');
signal N_MSK_STAT : slv8 := (others=>'0');
signal R_CMD_CODE : string(1 to 4) := (others=>' ');
signal R_CMD_ADDR : slv16 := (others=>'0');
signal R_CMD_DATA : slv16 := (others=>'0');
signal R_CHK_DATA : boolean := false;
signal R_REF_DATA : slv16 := (others=>'0');
signal R_MSK_DATA : slv16 := (others=>'0');
signal R_CHK_DONE : boolean := false;
signal R_REF_DONE : slv16 := (others=>'0');
signal R_CHK_STAT : boolean := false;
signal R_REF_STAT : slv8 := (others=>'0');
signal R_MSK_STAT : slv8 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
shared variable sv_dbasi : integer := 2;
shared variable sv_dbaso : integer := 2;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
CLKDIV : entity work.clkdivce_tb
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
TBA : rlink_tba
port map (
CLK => CLK,
RESET => RESET,
CNTL => TBA_CNTL,
DI => TBA_DI,
STAT => TBA_STAT,
DO => TBA_DO,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
RLINK : rlink_core
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => (others=>'0'))
port map (
CLK => CLK,
CE_INT => CE_MSEC,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RB_MREQ_aval <= RB_MREQ.aval;
RB_MREQ_re <= RB_MREQ.re;
RB_MREQ_we <= RB_MREQ.we;
RB_MREQ_initt<= RB_MREQ.init;
RB_MREQ_addr <= RB_MREQ.addr;
RB_MREQ_din <= RB_MREQ.din;
RB_SRES.ack <= RB_SRES_ack;
RB_SRES.busy <= RB_SRES_busy;
RB_SRES.err <= RB_SRES_err;
RB_SRES.dout <= RB_SRES_dout;
UUT : rbtba_aif
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RLMON : rlink_mon
generic map (
DWIDTH => RL_DI'length)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RLMON_EN,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
RBMON : rb_mon
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RBMON_EN,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
proc_stim: process
file fstim : text open read_mode is "tb_rlink_tba_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable ien : slbit := '0';
variable iaddr : slv16 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable bcnt : integer := 0;
variable ccnt : integer := 0;
variable cmax : integer := 32;
variable nwait : integer := 0;
variable amnemo : string(1 to 6) := (others=>' ');
variable newline : boolean := true;
variable chk_data : boolean := false;
variable ref_data : slv16 := (others=>'0');
variable msk_data : slv16 := (others=>'0');
variable chk_stat : boolean := false;
variable ref_stat : slv8 := (others=>'0');
variable msk_stat : slv8 := (others=>'0');
variable chk_sdef : boolean := true;
variable ref_sdef : slv8 := (others=>'0');
variable msk_sdef : slv8 := "11111000"; -- ignore status bits and attn
variable chk_ndef : boolean := true;
type amrec_type is record
name : string(1 to 6);
addr : slv16;
end record;
constant amrec_init : amrec_type := ((others=>' '),
(others=>'0'));
constant amtbl_size : integer := 256;
type amtbl_type is array (1 to amtbl_size) of amrec_type;
variable amtbl_defs : integer := 0;
variable amtbl : amtbl_type := (others=>amrec_init);
procedure get_addr(L: inout line;
addr: out slv16) is
variable ichar : character := ' ';
variable name : string(1 to 6) := (others=>' ');
variable lok : boolean := false;
variable liaddr : slv16 := (others=>'0');
variable iaddr_or : slv16 := (others=>'0');
begin
readwhite(L);
readoptchar(L, '.', lok);
if lok then
readword_ea(L, name);
for i in 1 to amtbl_defs loop
if amtbl(i).name = name then
liaddr := amtbl(i).addr;
readoptchar(L, '|', lok);
if lok then
readgen_ea(L, iaddr_or);
for j in iaddr_or'range loop
if iaddr_or(j) = '1' then
liaddr(j) := '1';
end if;
end loop;
end if;
addr := liaddr;
return;
end if;
end loop;
report "address mnemonic not defined: " & name
severity failure;
end if;
readgen_ea(L, addr);
end procedure get_addr;
procedure cmd_waitdone is
variable lnwait : integer := 0;
begin
lnwait := 0;
while TBA_STAT.busy='1' loop
lnwait := lnwait + 1;
assert lnwait<2000 report "assert(lnwait<2000)" severity failure;
wait for clock_period;
end loop;
end procedure cmd_waitdone;
procedure setup_check_n (
pbcnt : in integer)
is
variable chk_done : boolean := false;
variable ref_done : slv16 := (others=>'0');
begin
readtagval_ea(iline, "n", chk_done, ref_done, 10);
if chk_done then
N_CHK_DONE <= chk_done;
N_REF_DONE <= ref_done;
else
N_CHK_DONE <= chk_ndef;
N_REF_DONE <= slv(to_unsigned(pbcnt,16));
end if;
end procedure setup_check_n;
procedure setup_check_d is
variable lchk_data : boolean := false;
variable lref_data : slv16 := (others=>'0');
variable lmsk_data : slv16 := (others=>'0');
begin
readtagval2_ea(iline, "d", lchk_data, lref_data, lmsk_data, sv_dbasi);
N_CHK_DATA <= lchk_data;
N_REF_DATA <= lref_data;
N_MSK_DATA <= lmsk_data;
end procedure setup_check_d;
procedure setup_check_s is
variable lchk_stat : boolean := false;
variable lref_stat : slv8 := (others=>'0');
variable lmsk_stat : slv8 := (others=>'0');
begin
readtagval2_ea(iline, "s", lchk_stat, lref_stat, lmsk_stat);
if lchk_stat then
N_CHK_STAT <= lchk_stat;
N_REF_STAT <= lref_stat;
N_MSK_STAT <= lmsk_stat;
else
N_CHK_STAT <= chk_sdef;
N_REF_STAT <= ref_sdef;
N_MSK_STAT <= msk_sdef;
end if;
end procedure setup_check_s;
procedure cmd_start (
pcmd : in slv3;
paddr : in slv16 := (others=>'0');
pdata : in slv16 := (others=>'0');
pbcnt : in integer := 1) is
begin
TBA_CNTL <= rlink_tba_cntl_init;
TBA_CNTL.cmd <= pcmd;
TBA_CNTl.addr <= paddr;
TBA_CNTL.cnt <= slv(to_unsigned(pbcnt,16));
TBA_DI <= pdata;
ccnt := ccnt + 1;
if ccnt >= cmax then
ccnt := 0;
TBA_CNTL.eop <= '1';
end if;
TBA_CNTL.ena <= '1';
wait for clock_period;
TBA_CNTL.ena <= '0';
TBA_CNTL.eop <= '0';
end procedure cmd_start;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
if TBA_STAT.ack = '1' and -- if ack cycle
iline'length>0 then -- and non empty line
if iline(1) = 'C' then -- and leading 'C'
wait for clock_period; -- wait cycle to ensure that comment
-- comes after moni response
end if;
end if;
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
N_CMD_CODE <= " ";
N_CHK_DATA <= false;
N_CHK_DONE <= false;
N_CHK_STAT <= false;
case dname is
when ".mode " => -- .mode
readword_ea(iline, dname);
assert dname="rri "
report "assert .mode == rri" severity failure;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
RLMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
RBMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".sdef " => -- .sdef , set default for status chk
readtagval2_ea(iline, "s", chk_sdef, ref_sdef, msk_sdef);
when ".ndef " => -- .ndef , enable/disable done chk
read_ea(iline, idata(0));
chk_ndef := idata(0) = '1';
when ".amclr" => -- .amclr , clear addr mnemo table
amtbl_defs := 0;
amtbl := (others=>amrec_init);
when ".amdef" => -- .amdef , define addr mnemo table
assert amtbl_defs<amtbl_size
report "assert(amtbl_defs<amtbl_size): too many .amdef's"
severity failure;
readword_ea(iline, amnemo);
readgen_ea(iline, iaddr);
amtbl_defs := amtbl_defs + 1;
amtbl(amtbl_defs).name := amnemo;
amtbl(amtbl_defs).addr := iaddr;
when ".dbasi" => -- .dbasi
read_ea(iline, idelta);
assert idelta=2 or idelta=8 or idelta=16
report "assert(dbasi = 2,8, or 16)"
severity failure;
sv_dbasi := idelta;
when ".dbaso" => -- .dbaso
read_ea(iline, idelta);
assert idelta=2 or idelta=8 or idelta=16
report "assert(dbaso = 2,8, or 16)"
severity failure;
sv_dbaso := idelta;
when ".cmax " => -- .cmax
readint_ea(iline, cmax, 1, 32);
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".wtlam" => -- .wtlam
read_ea(iline, idelta);
nwait := 0;
loop
if TBA_STAT.ano='1' or nwait>=idelta then
writetimestamp(oline, CLK_CYCLE, ": .wtlam" & " nwait=");
write(oline, nwait, left);
if TBA_STAT.ano = '0' then
write(oline, string'(" FAIL TIMEOUT"));
end if;
writeline(output, oline);
exit;
end if;
nwait := nwait + 1;
wait for clock_period;
end loop;
when ".eop " => -- .eop
TBA_CNTL <= rlink_tba_cntl_init;
TBA_CNTL.eop <= '1';
wait for clock_period;
TBA_CNTL.eop <= '0';
wait for clock_period; -- wait (or rlink_tba will hang...)
ccnt := 0;
when "rreg " => -- rreg
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_rreg, paddr=>iaddr);
cmd_waitdone;
when "rblk " => -- rblk
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
read_ea(iline, bcnt);
assert bcnt>0 report "assert(bcnt>0)" severity failure;
setup_check_n(bcnt);
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_rblk, paddr=>iaddr, pbcnt=>bcnt);
testempty_ea(iline);
newline := true;
for i in 1 to bcnt loop
while TBA_STAT.bwe='0' loop
wait for clock_period;
end loop;
if newline then
rblk_line: loop
readline (fstim, iline);
readcomment(iline, ok);
exit rblk_line when not ok;
end loop;
end if;
readtagval2_ea(iline, "d", chk_data, ref_data, msk_data,sv_dbasi);
N_CHK_DATA <= chk_data;
N_REF_DATA <= ref_data;
N_MSK_DATA <= msk_data;
testempty(iline, newline);
wait for clock_period;
end loop;
N_CHK_DATA <= false;
cmd_waitdone;
when "wreg " => -- wreg
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
readgen_ea(iline, idata, sv_dbasi);
N_CMD_DATA <= idata;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_wreg, paddr=>iaddr, pdata=>idata);
cmd_waitdone;
when "wblk " => -- wblk
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
read_ea(iline, bcnt);
assert bcnt>0 report "assert(bcnt>0)" severity failure;
setup_check_n(bcnt);
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_wblk, paddr=>iaddr, pbcnt=>bcnt);
testempty_ea(iline);
newline := true;
for i in 1 to bcnt loop
while TBA_STAT.bre='0' loop
wait for clock_period;
end loop;
if newline then
wblk_line: loop
readline (fstim, iline);
readcomment(iline, ok);
exit wblk_line when not ok;
end loop;
end if;
readgen_ea(iline, idata, sv_dbasi);
TBA_DI <= idata;
testempty(iline, newline);
wait for clock_period;
end loop;
cmd_waitdone;
when "labo " => -- labo
N_CMD_CODE <= dname(N_CMD_CODE'range);
N_CMD_ADDR <= (others=>'0');
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_labo);
cmd_waitdone;
when "attn " => -- attn
N_CMD_CODE <= dname(N_CMD_CODE'range);
N_CMD_ADDR <= (others=>'0');
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_attn);
cmd_waitdone;
when "init " => -- init
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
readgen_ea(iline, idata, sv_dbasi);
N_CMD_DATA <= idata;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_init, paddr=>iaddr, pdata=>idata);
cmd_waitdone;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
wait for 4*clock_period;
CLK_STOP <= '1';
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable chk_ok : boolean := true;
begin
loop
wait until rising_edge(CLK);
R_CMD_CODE <= N_CMD_CODE;
R_CMD_ADDR <= N_CMD_ADDR;
R_CMD_DATA <= N_CMD_DATA;
R_CHK_DATA <= N_CHK_DATA;
R_REF_DATA <= N_REF_DATA;
R_MSK_DATA <= N_MSK_DATA;
R_CHK_DONE <= N_CHK_DONE;
R_REF_DONE <= N_REF_DONE;
R_CHK_STAT <= N_CHK_STAT;
R_REF_STAT <= N_REF_STAT;
R_MSK_STAT <= N_MSK_STAT;
if TBA_STAT.bwe = '1' then
writetimestamp(oline, CLK_CYCLE, ": rblk ");
writehex(oline, R_CMD_ADDR, right, 4);
write(oline, string'(" bwe=1 "));
writegen(oline, TBA_DO, right, base=>sv_dbaso);
if N_CHK_DATA then
if N_MSK_DATA /= "1111111111111111" then -- not all masked off
write(oline, string'(" .D.-CHECK"));
else
write(oline, string'(" ...-CHECK"));
end if;
if unsigned((TBA_DO xor N_REF_DATA) and (not N_MSK_DATA)) /= 0 then
write(oline, string'(" FAIL d="));
writegen(oline, N_REF_DATA, base=>sv_dbaso);
if unsigned(N_MSK_DATA) /= 0 then
write(oline, string'(","));
writegen(oline, N_MSK_DATA, base=>sv_dbaso);
end if;
else
write(oline, string'(" OK"));
end if;
end if;
writeline(output, oline);
end if;
if TBA_STAT.ack = '1' then
writetimestamp(oline, CLK_CYCLE, ": ");
write(oline, R_CMD_CODE);
writehex(oline, R_CMD_ADDR, right, 5);
write(oline, string'(" "));
write(oline, TBA_STAT.err, right, 1);
write(oline, TBA_STAT.stat, right, 9);
write(oline, string'(" "));
if R_CMD_CODE="wreg" or R_CMD_CODE="init" then
writegen(oline, R_CMD_DATA, right, base=>sv_dbaso);
else
writegen(oline, TBA_DO, right, base=>sv_dbaso);
end if;
if R_CHK_DATA or R_CHK_DONE or R_CHK_STAT then
chk_ok := true;
write(oline, string'(" "));
if R_CHK_DONE then
write(oline, string'("N"));
else
write(oline, string'("."));
end if;
if R_CHK_DATA and R_MSK_DATA/="1111111111111111" then
write(oline, string'("D"));
else
write(oline, string'("."));
end if;
if R_CHK_STAT and R_MSK_STAT/="11111111" then
write(oline, string'("S"));
else
write(oline, string'("."));
end if;
write(oline, string'("-CHECK"));
if R_CHK_DONE then
if TBA_STAT.dcnt /= R_REF_DONE then
chk_ok := false;
write(oline, string'(" FAIL n="));
write(oline, to_integer(unsigned(R_REF_DONE)));
end if;
end if;
if R_CHK_DATA then
if unsigned((TBA_DO xor R_REF_DATA) and (not R_MSK_DATA)) /= 0 then
chk_ok := false;
write(oline, string'(" FAIL d="));
writegen(oline, R_REF_DATA, base=>sv_dbaso);
if unsigned(R_MSK_DATA) /= 0 then
write(oline, string'(","));
writegen(oline, R_MSK_DATA, base=>sv_dbaso);
end if;
end if;
end if;
if R_CHK_STAT then
if unsigned((TBA_STAT.stat xor R_REF_STAT) and
(not R_MSK_STAT)) /= 0 then
chk_ok := false;
write(oline, string'(" FAIL s="));
write(oline, R_REF_STAT);
if unsigned(R_MSK_STAT) /= 0 then
write(oline, string'(","));
write(oline, R_MSK_STAT);
end if;
end if;
end if;
if chk_ok then
write(oline, string'(" OK"));
end if;
end if;
writeline(output, oline);
end if;
if TBA_STAT.ano = '1' then
writetimestamp(oline, CLK_CYCLE, ": ---- attn notify ---- ");
write(oline, TBA_STAT.apat, right, 16);
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | 396fce5827ca813470488f5b07562ef9 | 0.494103 | 3.608784 | false | false | false | false |
wfjm/w11 | rtl/bplib/basys3/tb/sys_conf_sim.vhd | 1 | 1,728 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_basys3_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-10-01 810 1.0 Initial version (cloned from nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 293e1191078b48fbb076758204771d39 | 0.619792 | 3.637895 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/iob_reg_io_gen.vhd | 1 | 3,657 | -- $Id: iob_reg_io_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2008 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_io_gen - syn
-- Description: Registered IOB, in/output, vector
--
-- Dependencies: iob_keeper_gen [sim only]
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2008-05-22 149 1.0.4 use internally TE to match OBUFT T polarity
-- 2008-05-22 148 1.0.3 remove UNISIM prim's; PULL implemented only for sim
-- 2008-05-18 147 1.0.2 add PULL generic, to enable PULL-UP,-DOWN or KEEPER
-- 2007-12-16 101 1.0.1 add INIT generic ports
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_io_gen is -- registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_reg_io_gen;
architecture syn of iob_reg_io_gen is
signal R_TE : slbit := not INITE;
signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INITI);
signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INITO);
constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
constant all_l : slv(DWIDTH-1 downto 0) := (others=>'L');
constant all_h : slv(DWIDTH-1 downto 0) := (others=>'H');
attribute iob : string;
attribute iob of R_TE : signal is "true";
attribute iob of R_DI : signal is "true";
attribute iob of R_DO : signal is "true";
begin
assert PULL="NONE" or PULL="UP" or PULL="DOWN" or PULL="KEEP"
report "assert(PULL): only NONE, UP, DOWN, OR KEEP supported"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_TE <= not OE;
if CEI = '1' then
R_DI <= to_x01(PAD);
end if;
if CEO = '1' then
R_DO <= DO;
end if;
end if;
end process proc_regs;
proc_comb: process (R_TE, R_DO)
begin
if R_TE = '1' then
PAD <= all_z;
else
PAD <= R_DO;
end if;
end process proc_comb;
DI <= R_DI;
-- Note: PULL (UP, DOWN or KEEP) is only implemented for simulation, not
-- for inference in synthesis. Use pin attributes in UCF's or XDC's
--
-- synthesis translate_off
PULL_UP: if PULL = "UP" generate
PAD <= all_h;
end generate PULL_UP;
PULL_DOWN: if PULL = "DOWN" generate
PAD <= all_l;
end generate PULL_DOWN;
PULL_KEEP: if PULL = "KEEP" generate
KEEPER : iob_keeper_gen
generic map (DWIDTH => DWIDTH)
port map (PAD => PAD);
end generate PULL_KEEP;
-- synthesis translate_on
end syn;
| gpl-3.0 | e2d53543eb4b1cd2c655727f5d2a114b | 0.558928 | 3.345837 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_decode.vhd | 1 | 19,868 | -- $Id: pdp11_decode.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_decode - syn
-- Description: pdp11: instruction decoder
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.0.8 rename _gpr -> _gr
-- 2022-10-03 1301 1.0.7 add STAT.is_dstpcmode1
-- 2011-11-18 427 1.0.6 now numeric_std clean
-- 2010-09-18 300 1.0.5 rename (adlm)box->(oalm)unit
-- 2008-11-30 174 1.0.4 BUGFIX: add updt_dstadsrc; set for MFP(I/D)
-- 2008-05-03 143 1.0.3 get fork_srcr,fork_dstr,fork_dsta assign out of if
-- 2008-04-27 139 1.0.2 BUGFIX: mtp now via do_fork_op; is_dsta logic mods
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end pdp11_decode;
architecture syn of pdp11_decode is
begin
proc_idecode: process (IREG)
alias OPCODE : slv4 is IREG(15 downto 12); -- basic opcode (upper 4 bits)
alias OPPRIM : slv3 is IREG(14 downto 12); -- basic opcode without B bit
alias OPBYTE : slbit is IREG(15); -- byte flag of basic opcode
alias OPEXT1 : slv3 is IREG(11 downto 9); -- extended opcode, part 1
alias OPEXT2 : slv3 is IREG(8 downto 6); -- extended opcode, part 2
alias OPEXT3 : slv3 is IREG(5 downto 3); -- extended opcode, part 3
alias OPEXT4 : slv3 is IREG(2 downto 0); -- extended opcode, part 4
alias SRCMODF : slv3 is IREG(11 downto 9); -- src register full mode
alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
alias SRCDEF : slbit is IREG(9); -- src register mode defered
alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
alias DSTDEF : slbit is IREG(3); -- dst register mode defered
alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
variable nstat : decode_stat_type;
variable is_srcr : slbit := '0'; -- source is read
variable is_dstr : slbit := '0'; -- destination is read
variable is_dstm : slbit := '0'; -- destination is modified
variable is_dstw : slbit := '0'; -- destination is written
variable is_srcmode0 : slbit := '0'; -- source is register mode
variable is_dstmode0notpc : slbit := '0'; -- dest. is register mode, not PC
begin
is_srcr := '0';
is_dstr := '0';
is_dstm := '0';
is_dstw := '0';
is_srcmode0 := '0';
is_dstmode0notpc := '0';
nstat.is_dstmode0 := '0';
nstat.is_srcpc := '0';
nstat.is_srcpcmode1 := '0';
nstat.is_dstpc := '0';
nstat.is_dstpcmode1 := '0';
nstat.is_dstw_reg := '0';
nstat.is_dstw_pc := '0';
nstat.is_rmwop := '0';
nstat.is_bytop := '0';
nstat.is_res := '1';
nstat.op_rtt := '0';
nstat.op_mov := '0';
nstat.trap_vec := "000";
nstat.force_srcsp := '0';
nstat.updt_dstadsrc := '0';
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_pass;
nstat.aunit_cc1op := '0';
nstat.aunit_ccmode := IREG(8 downto 6); -- STATIC
nstat.lunit_func := (others=>'0');
nstat.munit_func := (others=>'0');
nstat.res_sel := c_dpath_res_ounit;
nstat.fork_op := (others=>'0');
nstat.fork_srcr := (others=>'0');
nstat.fork_dstr := (others=>'0');
nstat.fork_dsta := (others=>'0');
nstat.fork_opg := (others=>'0');
nstat.fork_opa := (others=>'0');
nstat.do_fork_op := '0';
nstat.do_fork_srcr := '0';
nstat.do_fork_dstr := '0';
nstat.do_fork_dsta := '0';
nstat.do_fork_opg := '0';
nstat.do_pref_dec := '0';
if SRCMODF = "000" then
is_srcmode0 := '1';
end if;
if DSTMODF = "000" then
nstat.is_dstmode0 := '1';
if DSTREG /= c_gr_pc then
is_dstmode0notpc := '1';
end if;
end if;
if SRCREG = c_gr_pc then
nstat.is_srcpc := '1';
if SRCMODF = "001" then
nstat.is_srcpcmode1 := '1';
end if;
end if;
if DSTREG = c_gr_pc then
nstat.is_dstpc := '1';
if DSTMODF = "001" then
nstat.is_dstpcmode1 := '1';
end if;
end if;
if OPPRIM = "000" then
if OPBYTE='0' and OPEXT1="000" then
if OPEXT2="000" and OPEXT3="000" then -- HALT,...,RTT
nstat.is_res := '0';
case OPEXT4 is
when "000" => -- HALT
nstat.fork_op := c_fork_op_halt;
nstat.do_fork_op := '1';
when "001" => -- WAIT
nstat.fork_op := c_fork_op_wait;
nstat.do_fork_op := '1';
when "010" => -- RTI
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rtti;
nstat.do_fork_op := '1';
when "011" => -- BPT (trap to 14)
nstat.trap_vec := "011";
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
when "100" => -- IOT (trap to 20)
nstat.trap_vec := "100";
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
when "101" => -- RESET
nstat.fork_op := c_fork_op_reset;
nstat.do_fork_op := '1';
when "110" => -- RTT
nstat.op_rtt := '1';
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rtti;
nstat.do_fork_op := '1';
when others =>
nstat.is_res := '1';
end case;
end if;
if OPEXT2 = "001" then -- JMP
nstat.is_res := '0';
nstat.fork_opa := c_fork_opa_jmp;
nstat.do_fork_dsta := '1';
end if;
if OPEXT2 = "010" then
if OPEXT3 = "000" then -- RTS
nstat.is_res := '0';
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rts;
nstat.do_fork_op := '1';
end if;
if OPEXT3 = "011" then -- SPL
nstat.is_res := '0';
nstat.fork_op := c_fork_op_spl;
nstat.do_fork_op := '1';
end if;
end if;
if OPEXT2 = "010" then
if OPEXT3(2) = '1' then -- SEx/CLx
nstat.is_res := '0';
nstat.fork_op := c_fork_op_mcc;
nstat.do_fork_op := '1';
--!!!nstat.do_pref_dec := '1'; --??? ensure ireg_we ....
end if;
end if;
if OPEXT2 = "011" then -- SWAP
nstat.is_res := '0';
is_dstm := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
nstat.lunit_func := c_lunit_func_swap;
nstat.res_sel := c_dpath_res_lunit;
end if;
end if; -- OPBYTE='0' and OPEXT1="000"
if OPEXT1(2)='0' and -- BR class instructions
((OPBYTE='0' and OPEXT2(2)='1') or -- BR
(OPBYTE='0' and (OPEXT1(0)='1' or OPEXT1(1)='1')) or -- BNE,..,BLE
OPBYTE='1') then -- BPL,..,BCS
nstat.is_res := '0';
nstat.fork_op := c_fork_op_br;
nstat.do_fork_op := '1';
end if;
if OPBYTE='0' and OPEXT1="100" then -- JSR
nstat.is_res := '0';
nstat.fork_opa := c_fork_opa_jsr;
nstat.do_fork_dsta := '1';
end if;
if OPBYTE='1' and OPEXT1="100" then -- EMT, TRAP
nstat.is_res := '0';
if OPEXT2(2) = '0' then -- EMT (trap tp 30)
nstat.trap_vec := "110";
else -- TRAP (trap to 34)
nstat.trap_vec := "111";
end if;
nstat.fork_op := c_fork_op_trap;
nstat.do_fork_op := '1';
end if;
if OPEXT1 = "101" then -- CLR(B),...,TST(B)
nstat.is_res := '0';
nstat.res_sel := c_dpath_res_aunit;
if OPBYTE = '1' then
nstat.is_bytop := '1';
end if;
nstat.aunit_cc1op := '1';
case OPEXT2 is
when "000" => -- CLR: 0 + 0 + 0 (0)
is_dstw := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_zero;
nstat.aunit_cimod := c_aunit_mod_zero;
when "001" => -- COM: 0 + ~DST + 0 (~dst)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_zero;
when "010" => -- INC: 0 + DST + 1 (dst+1)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_one;
when "011" => -- DEC: ~0 + DST + 0 (dst-1)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_one;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
when "100" => -- NEG: 0 + ~DST + 1 (-dst)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_one;
when "101" => -- ADC: 0 + DST + CI (dst+ci)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_pass;
when "110" => -- SBC: ~0 + DST + ~CI (dst-ci)
is_dstm := '1';
nstat.aunit_srcmod := c_aunit_mod_one;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_inv;
when "111" => -- TST: 0 + DST + 0 (dst)
is_dstr := '1';
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
when others => null;
end case;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
end if;
if OPEXT1 = "110" then
if OPEXT2(2) = '0' then -- ROR(B),...,ASL(B)
nstat.is_res := '0';
is_dstm := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
if OPBYTE = '1' then
nstat.is_bytop := '1';
end if;
nstat.res_sel := c_dpath_res_lunit;
case OPEXT2(1 downto 0) is
when "00" => -- ROR
nstat.lunit_func := c_lunit_func_ror;
when "01" => -- ROL
nstat.lunit_func := c_lunit_func_rol;
when "10" => -- ASR
nstat.lunit_func := c_lunit_func_asr;
when "11" => -- ASL
nstat.lunit_func := c_lunit_func_asl;
when others => null;
end case;
end if;
if OPBYTE='0' and OPEXT2="100" then -- MARK
nstat.is_res := '0';
nstat.fork_op := c_fork_op_mark;
nstat.do_fork_op := '1';
end if;
if OPEXT2 = "101" then -- MFP(I/D)
nstat.is_res := '0';
nstat.force_srcsp := '1';
if DSTREG = c_gr_sp then -- is dst reg == sp ?
nstat.updt_dstadsrc := '1'; -- ensure DSRC update in dsta flow
end if;
nstat.res_sel := c_dpath_res_ounit;
if nstat.is_dstmode0 = '1' then
nstat.fork_opa := c_fork_opa_mfp_reg;
else
nstat.fork_opa := c_fork_opa_mfp_mem;
end if;
nstat.do_fork_dsta := '1';
end if;
if OPEXT2 = "110" then -- MTP(I/D)
nstat.is_res := '0';
nstat.force_srcsp := '1';
nstat.res_sel := c_dpath_res_ounit;
nstat.fork_opa := c_fork_opa_mtp;
nstat.fork_op := c_fork_op_mtp;
nstat.do_fork_op := '1';
end if;
if OPBYTE='0' and OPEXT2="111" then -- SXT
nstat.is_res := '0';
is_dstw := '1';
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
nstat.lunit_func := c_lunit_func_sxt;
nstat.res_sel := c_dpath_res_lunit;
end if;
end if;
end if; -- OPPRIM="000"
if OPPRIM/="000" and OPPRIM/="111" then
nstat.is_res := '0';
case OPPRIM is
when "001" => -- MOV
is_srcr := '1';
is_dstw := '1';
nstat.op_mov := '1';
nstat.lunit_func := c_lunit_func_mov;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "010" => -- CMP
is_srcr := '1';
is_dstr := '1';
nstat.res_sel := c_dpath_res_aunit;
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_one;
nstat.is_bytop := OPBYTE;
when "011" => -- BIT
is_srcr := '1';
is_dstr := '1';
nstat.lunit_func := c_lunit_func_bit;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "100" => -- BIC
is_srcr := '1';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_bic;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "101" => -- BIS
is_srcr := '1';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_bis;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "110" =>
is_srcr := '1';
is_dstm := '1';
nstat.res_sel := c_dpath_res_aunit;
if OPBYTE = '0' then -- ADD
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
else -- SUB
nstat.aunit_srcmod := c_aunit_mod_inv;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_one;
end if;
when others => null;
end case;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_srcmode0 and is_dstmode0notpc;
end if;
if OPBYTE='0' and OPPRIM="111" then
case OPEXT1 is
when "000" => -- MUL
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_mul;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_mul;
nstat.do_fork_opg := '1';
when "001" => -- DIV
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_div;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_div;
nstat.do_fork_opg := '1';
when "010" => -- ASH
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_ash;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_ash;
nstat.do_fork_opg := '1';
when "011" => -- ASHC
nstat.is_res := '0';
is_dstr := '1';
nstat.munit_func := c_munit_func_ashc;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_ashc;
nstat.do_fork_opg := '1';
when "100" => -- XOR
nstat.is_res := '0';
is_dstm := '1';
nstat.lunit_func := c_lunit_func_xor;
nstat.res_sel := c_dpath_res_lunit;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
when "111" => -- SOB: SRC + ~0 + 0 (src-1)
nstat.is_res := '0';
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_one;
nstat.aunit_cimod := c_aunit_mod_zero;
nstat.res_sel := c_dpath_res_aunit;
nstat.fork_op := c_fork_op_sob;
nstat.do_fork_op := '1';
when others => null;
end case;
end if;
if OPBYTE='1' and OPPRIM="111" then -- FPU
nstat.is_res := '1'; -- ??? FPU not yet handled
end if;
case SRCMOD is
when "00" => nstat.fork_srcr := c_fork_srcr_def;
when "01" => nstat.fork_srcr := c_fork_srcr_inc;
when "10" => nstat.fork_srcr := c_fork_srcr_dec;
when "11" => nstat.fork_srcr := c_fork_srcr_ind;
when others => null;
end case;
if is_srcr='1' and SRCMODF /="000" then
nstat.do_fork_srcr := '1';
end if;
case DSTMOD is
when "00" => nstat.fork_dstr := c_fork_dstr_def;
when "01" => nstat.fork_dstr := c_fork_dstr_inc;
when "10" => nstat.fork_dstr := c_fork_dstr_dec;
when "11" => nstat.fork_dstr := c_fork_dstr_ind;
when others => null;
end case;
if (is_dstr or is_dstm)='1' and nstat.is_dstmode0='0' then
nstat.do_fork_dstr := '1';
end if;
if is_dstw='1' and nstat.is_dstmode0='0' then
case DSTMOD is
when "00" => nstat.fork_opg := c_fork_opg_wdef;
when "01" => nstat.fork_opg := c_fork_opg_winc;
when "10" => nstat.fork_opg := c_fork_opg_wdec;
when "11" => nstat.fork_opg := c_fork_opg_wind;
when others => null;
end case;
end if;
if is_dstm='1' and nstat.is_dstmode0='0' then
nstat.is_rmwop := '1';
end if;
case DSTMOD is
when "00" => nstat.fork_dsta := c_fork_dsta_def;
when "01" => nstat.fork_dsta := c_fork_dsta_inc;
when "10" => nstat.fork_dsta := c_fork_dsta_dec;
when "11" => nstat.fork_dsta := c_fork_dsta_ind;
when others => null;
end case;
if (is_dstw or is_dstm)='1' and nstat.is_dstmode0='1' then
nstat.is_dstw_reg := '1';
if DSTREG = c_gr_pc then
nstat.is_dstw_pc := '1'; --??? hack rename -> is_dstw_pc
end if;
end if;
STAT <= nstat;
end process proc_idecode;
end syn;
| gpl-3.0 | 7f3121f35cceab532c06f9b8b3678331 | 0.467989 | 3.374894 | false | false | false | false |
nanomolina/vhdl_examples | mux2/mux2.vhd | 4 | 433 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY mux2 IS
GENERIC (N: INTEGER:=32);
PORT (d0, d1: IN std_logic_vector(N-1 DOWNTO 0);
s: IN std_logic;
y: OUT std_logic_vector(N-1 DOWNTO 0));
END mux2;
ARCHITECTURE mux_est OF mux2 IS
BEGIN
PROCESS(s)
BEGIN
IF (s='0') THEN
y <= d0;
ELSIF (s='1') THEN
y <= d1;
END IF;
END PROCESS;
END mux_est;
| gpl-3.0 | dc3f2a7f1ef05e0ad51757af5f3e2f51 | 0.538106 | 3.006944 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_tmu.vhd | 1 | 9,858 | -- $Id: pdp11_tmu.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_tmu - sim
-- Description: pdp11: trace and monitor unit
--
-- Dependencies: -
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: viv 2016.2-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.3.2 rename _gpr -> _gr
-- 2018-10-05 1053 1.3.1 use DM_STAT_CA instead of DM_STAT_SY
-- 2016-12-28 833 1.3 open tmu_ofile only when used
-- 2015-07-03 697 1.2.1 adapt to new DM_STAT_SY/DM_STAT_VM
-- 2015-05-03 674 1.2 start/stop/suspend overhaul
-- 2011-12-23 444 1.1 use local clkcycle count instead of simbus global
-- 2011-11-18 427 1.0.7 now numeric_std clean
-- 2010-10-17 333 1.0.6 use ibus V2 interface
-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
-- 2008-04-19 137 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
);
end pdp11_tmu;
architecture sim of pdp11_tmu is
signal R_FIRST : slbit := '1';
begin
proc_tm: process (CLK)
variable oline : line;
variable clkcycle : integer := 0;
variable ipsw : slv16 := (others=>'0');
variable ibaddr : slv16 := (others=>'0');
variable emaddr : slv22 := (others=>'0');
variable dp_ireg_we_last : slbit := '0';
variable vm_ibsres_busy_last : slbit := '0';
variable vm_ibsres_ack_last : slbit := '0';
variable wcycle : boolean := false;
file ofile : text;
begin
if rising_edge(CLK) then
clkcycle := clkcycle + 1;
if ENA = '1' and R_FIRST = '1' then
-- open output file on first usage
file_open(ofile, "tmu_ofile", WRITE_MODE);
R_FIRST <= '0';
-- sequence of field desciptors must equal the sequence of writes later
write(oline, string'("#"));
write(oline, string'(" clkcycle:d"));
write(oline, string'(" cpu:o"));
write(oline, string'(" dp.pc:o"));
write(oline, string'(" dp.psw:o"));
write(oline, string'(" dp.ireg:o"));
write(oline, string'(" dp.ireg_we:b"));
write(oline, string'(" dp.ireg_we_last:b")); -- is ireg_we last cycle
write(oline, string'(" dp.dsrc:o"));
write(oline, string'(" dp.ddst:o"));
write(oline, string'(" dp.dtmp:o"));
write(oline, string'(" dp.dres:o"));
write(oline, string'(" dp.gr_adst:o"));
write(oline, string'(" dp.gr_mode:o"));
write(oline, string'(" dp.gr_bytop:b"));
write(oline, string'(" dp.gr_we:b"));
write(oline, string'(" vm.ibmreq.aval:b"));
write(oline, string'(" vm.ibmreq.re:b"));
write(oline, string'(" vm.ibmreq.we:b"));
write(oline, string'(" vm.ibmreq.rmw:b"));
write(oline, string'(" vm.ibmreq.be0:b"));
write(oline, string'(" vm.ibmreq.be1:b"));
write(oline, string'(" vm.ibmreq.cacc:b"));
write(oline, string'(" vm.ibmreq.racc:b"));
write(oline, string'(" vm.ibmreq.addr:o"));
write(oline, string'(" vm.ibmreq.din:o"));
write(oline, string'(" vm.ibsres.ack:b"));
write(oline, string'(" vm.ibsres.busy:b"));
write(oline, string'(" vm.ibsres.dout:o"));
write(oline, string'(" vm.emmreq.req:b"));
write(oline, string'(" vm.emmreq.we:b"));
write(oline, string'(" vm.emmreq.be:b"));
write(oline, string'(" vm.emmreq.cancel:b"));
write(oline, string'(" vm.emmreq.addr:o"));
write(oline, string'(" vm.emmreq.din:o"));
write(oline, string'(" vm.emsres.ack_r:b"));
write(oline, string'(" vm.emsres.ack_w:b"));
write(oline, string'(" vm.emsres.dout:o"));
write(oline, string'(" co.cpugo:b"));
write(oline, string'(" co.cpususp:b"));
write(oline, string'(" co.suspint:b"));
write(oline, string'(" co.suspext:b"));
write(oline, string'(" ca.rd:b"));
write(oline, string'(" ca.wr:b"));
write(oline, string'(" ca.rdhit:b"));
write(oline, string'(" ca.wrhit:b"));
write(oline, string'(" ca.rdmem:b"));
write(oline, string'(" ca.wrmem:b"));
write(oline, string'(" ca.rdwait:b"));
write(oline, string'(" ca.wrwait:b"));
writeline(ofile, oline);
end if;
ipsw := (others=>'0');
ipsw(psw_ibf_cmode) := DM_STAT_DP.psw.cmode;
ipsw(psw_ibf_pmode) := DM_STAT_DP.psw.pmode;
ipsw(psw_ibf_rset) := DM_STAT_DP.psw.rset;
ipsw(psw_ibf_pri) := DM_STAT_DP.psw.pri;
ipsw(psw_ibf_tflag) := DM_STAT_DP.psw.tflag;
ipsw(psw_ibf_cc) := DM_STAT_DP.psw.cc;
ibaddr := "1110000000000000";
ibaddr(DM_STAT_VM.ibmreq.addr'range) := DM_STAT_VM.ibmreq.addr;
emaddr := (others=>'0');
emaddr(DM_STAT_VM.emmreq.addr'range) := DM_STAT_VM.emmreq.addr;
wcycle := false;
if dp_ireg_we_last='1' or
DM_STAT_DP.gr_we='1' or
DM_STAT_VM.emmreq.req='1' or
DM_STAT_VM.emsres.ack_r='1' or
DM_STAT_VM.emsres.ack_w='1' or
DM_STAT_VM.emmreq.cancel='1' or
DM_STAT_VM.ibmreq.re='1' or
DM_STAT_VM.ibmreq.we='1' or
DM_STAT_VM.ibsres.ack='1'
then
wcycle := true;
end if;
if DM_STAT_VM.ibsres.busy='0' and
(vm_ibsres_busy_last='1' and vm_ibsres_ack_last='0')
then
wcycle := true;
end if;
if ENA = '0' then -- if not enabled
wcycle := false; -- force to not logged...
end if;
if wcycle then
-- sequence of writes must equal the sequence of field desciptors above
write(oline, clkcycle, right, 9);
write(oline, string'(" 0"));
writeoct(oline, DM_STAT_DP.pc, right, 7);
writeoct(oline, ipsw, right, 7);
writeoct(oline, DM_STAT_DP.ireg, right, 7);
write(oline, DM_STAT_DP.ireg_we, right, 2);
write(oline, dp_ireg_we_last, right, 2);
writeoct(oline, DM_STAT_DP.dsrc, right, 7);
writeoct(oline, DM_STAT_DP.ddst, right, 7);
writeoct(oline, DM_STAT_DP.dtmp, right, 7);
writeoct(oline, DM_STAT_DP.dres, right, 7);
writeoct(oline, DM_STAT_DP.gr_adst, right, 2);
writeoct(oline, DM_STAT_DP.gr_mode, right, 2);
write(oline, DM_STAT_DP.gr_bytop, right, 2);
write(oline, DM_STAT_DP.gr_we, right, 2);
write(oline, DM_STAT_VM.ibmreq.aval, right, 2);
write(oline, DM_STAT_VM.ibmreq.re, right, 2);
write(oline, DM_STAT_VM.ibmreq.we, right, 2);
write(oline, DM_STAT_VM.ibmreq.rmw, right, 2);
write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
writeoct(oline, ibaddr, right, 7);
writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
write(oline, DM_STAT_VM.ibsres.ack, right, 2);
write(oline, DM_STAT_VM.ibsres.busy, right, 2);
writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7);
write(oline, DM_STAT_VM.emmreq.req, right, 2);
write(oline, DM_STAT_VM.emmreq.we, right, 2);
write(oline, DM_STAT_VM.emmreq.be, right, 3);
write(oline, DM_STAT_VM.emmreq.cancel, right, 2);
writeoct(oline, emaddr, right, 9);
writeoct(oline, DM_STAT_VM.emmreq.din, right, 7);
write(oline, DM_STAT_VM.emsres.ack_r, right, 2);
write(oline, DM_STAT_VM.emsres.ack_w, right, 2);
writeoct(oline, DM_STAT_VM.emsres.dout, right, 7);
write(oline, DM_STAT_CO.cpugo, right, 2);
write(oline, DM_STAT_CO.cpususp, right, 2);
write(oline, DM_STAT_CO.suspint, right, 2);
write(oline, DM_STAT_CO.suspext, right, 2);
write(oline, DM_STAT_CA.rd, right, 2);
write(oline, DM_STAT_CA.wr, right, 2);
write(oline, DM_STAT_CA.rdhit, right, 2);
write(oline, DM_STAT_CA.wrhit, right, 2);
write(oline, DM_STAT_CA.rdmem, right, 2);
write(oline, DM_STAT_CA.wrmem, right, 2);
write(oline, DM_STAT_CA.rdwait, right, 2);
write(oline, DM_STAT_CA.wrwait, right, 2);
writeline(ofile, oline);
end if;
dp_ireg_we_last := DM_STAT_DP.ireg_we;
vm_ibsres_busy_last := DM_STAT_VM.ibsres.busy;
vm_ibsres_ack_last := DM_STAT_VM.ibsres.ack;
end if;
end process proc_tm;
end sim;
| gpl-3.0 | 1ef2154c17304088a327c028a1ea4c89 | 0.554981 | 3.182053 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01300_good.vhd | 1 | 3,298 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01300_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of constant name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01300_good is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end CNE_01300_good;
architecture Behavioral of CNE_01300_good is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
constant c_Length : unsigned(3 downto 0) := "1001"; -- Counter period
begin
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count>=c_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable='1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral; | gpl-3.0 | 81a970892c6316de2f0847911adf374f | 0.497271 | 4.638537 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys3/tb/sys_conf_sim.vhd | 1 | 1,797 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | b6d2baed9ff8bcb6c42df9b85f447f22 | 0.611575 | 3.544379 | false | false | false | false |
sjohann81/hf-risc | mips/core_mips/alu.vhd | 1 | 1,875 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port ( op1: in std_logic_vector(31 downto 0);
op2: in std_logic_vector(31 downto 0);
alu_op: in std_logic_vector(3 downto 0);
result: out std_logic_vector(31 downto 0);
zero: out std_logic;
less_than: out std_logic
);
end alu;
architecture arch_alu of alu is
signal r, shift: std_logic_vector(31 downto 0);
signal shift_op2: std_logic_vector(4 downto 0);
signal addsub: std_logic_vector(32 downto 0);
signal less, left, logical: std_logic;
begin
process(op1, op2, alu_op, addsub, less, shift_op2, shift)
begin
case alu_op is
when "0000" => r <= op1 and op2;
when "0001" => r <= op1 or op2;
when "0010" => r <= op1 xor op2;
when "0011" => r <= op1 nor op2;
when "0100" | "0101" => r <= addsub(31 downto 0);
when "0110" => r <= op2(15 downto 0) & x"0000";
when "0111" | "1000" => r <= x"0000000" & "000" & less;
when others => r <= shift;
end case;
end process;
addsub <= ('0' & op1) - ('0' & op2) when alu_op > "0100" else ('0' & op1) + ('0' & op2);
less <= addsub(32) when op1(31) = op2(31) or alu_op = "1000" else op1(31);
less_than <= less;
zero <= not (r(31) or r(30) or r(29) or r(28) or r(27) or r(26) or r(25) or r(24) or
r(23) or r(22) or r(21) or r(20) or r(19) or r(18) or r(17) or r(16) or
r(15) or r(14) or r(13) or r(12) or r(11) or r(10) or r(9) or r(8) or
r(7) or r(6) or r(5) or r(4) or r(3) or r(2) or r(1) or r(0));
shift_op2 <= op2(10 downto 6) when alu_op < "1100" else op2(4 downto 0);
left <= '1' when alu_op = "1001" or alu_op = "1100" else '0';
logical <= '0' when alu_op = "1011" or alu_op = "1110" else '1';
barrel_shifter: entity work.bshift
port map( left => left,
logical => logical,
shift => shift_op2,
input => op1,
output => shift
);
result <= r;
end arch_alu;
| gpl-2.0 | b00b3a51a7dd30e2591d339e8b41613c | 0.596267 | 2.364439 | false | false | false | false |
mossmann/hackrf | firmware/cpld/sgpio_if/top.vhd | 2 | 5,832 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_SYNC_EN : in std_logic;
HOST_SYNC_CMD : out std_logic;
HOST_SYNC : in std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_rx_i : std_logic;
signal codec_clk_tx_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal host_sync_enable : std_logic := '0';
signal host_sync_o : std_logic := '0';
signal host_sync_i : std_logic := '0';
signal host_sync_latched : std_logic := '0';
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
HOST_CAPTURE <= host_data_capture_o;
host_sync_enable <= HOST_SYNC_EN;
host_sync_i <= HOST_SYNC;
HOST_SYNC_CMD <= host_sync_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
------------------------------------------------
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7f" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
codec_clk_rx_i <= CODEC_CLK;
adc_data_i <= DA(7 downto 0);
if (transfer_direction_i = from_adc) then
if codec_clk_rx_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end if;
end process;
process(host_clk_i)
begin
if falling_edge(host_clk_i) then
codec_clk_tx_i <= CODEC_CLK;
data_from_host_i <= HOST_DATA;
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process (host_data_enable_i, host_sync_i)
begin
host_sync_o <= host_data_enable_i;
if host_data_enable_i = '1' then
if rising_edge(host_sync_i) then
host_sync_latched <= host_sync_i;
end if;
else
host_sync_latched <= '0';
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
else
if codec_clk_rx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 71ea2b2533b14971f20328b4e7ef98a3 | 0.522634 | 3.691139 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd | 1 | 9,883 | -- $Id: sys_tst_rlink_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n3 - syn
-- Description: rlink tester design for nexys3
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-03-13 743 14.7 131013 xc6slx16-2 950 1380 70 504
-- 2014-12-20 614 14.7 131013 xc6slx16-2 917 1379 64 513 t 8.9
-- 2011-12-18 440 13.1 O40d xc6slx16-2 752 1258 48 439 t 7.9
-- 2011-11-26 433 13.1 O40d xc6slx16-2 722 1199 36 423 t 9.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-19 748 1.4.2 define rlink SYSID
-- 2015-04-11 666 1.4.1 rearrange XON handling
-- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-18 440 1.1.1 use [rt]xok for DSP_DP
-- 2011-12-11 438 1.1 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(1): timer 1 busy
-- LED(0): timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_n3;
architecture syn of sys_tst_rlink_n3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"03"; -- nexys3
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
| gpl-3.0 | e6f39850332fc7e0c51d1744a345ae81 | 0.494587 | 3.106885 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibd_m9312.vhd | 1 | 5,405 | -- $Id: ibd_m9312.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_m9312 - syn
-- Description: ibus dev: M9312
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_m9312 is -- ibus dev: M9312
-- fixed address: 165***,173***
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end ibd_m9312;
architecture syn of ibd_m9312 is
-- 1 111 110 000 000 000
-- 5 432 109 876 543 210
-- Note: LO-ROM addr is 165xxx: 1 110 101 xxx xxx xx0
-- HI-ROM addr is 173xxx: 1 111 011 xxx xxx xx0
-- --> addr(12) is 0 for LO and 1 for HI
constant ibaddr_m9312_lo : slv16 := slv(to_unsigned(8#165000#,16));
constant ibaddr_m9312_hi : slv16 := slv(to_unsigned(8#173000#,16));
constant csr_ibf_locwe : integer := 7;
constant csr_ibf_enahi : integer := 1;
constant csr_ibf_enalo : integer := 0;
type regs_type is record -- state registers
ibselcsr : slbit; -- ibus select csr: LO-ROM(0)
ibselmem : slbit; -- ibus select mem: LO-ROM or HI-ROM
locwe : slbit; -- write enable for loc access
enahi : slbit; -- HI-ROM loc visible
enalo : slbit; -- LO-ROM loc visible
end record regs_type;
constant regs_init : regs_type := (
'0','0', -- ibselcsr,ibselmem
'0', -- locwe
'0','0' -- enahi,enalo
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_WE : slbit := '0';
signal BRAM_DO : slv16 := (others=>'0');
signal BRAM_ADDR : slv9 := (others=>'0');
begin
BRAM : ram_1swsr_wfirst_gen
generic map (
AWIDTH => 9,
DWIDTH => 16)
port map (
CLK => CLK,
EN => '1',
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => IB_MREQ.din,
DO => BRAM_DO
);
BRAM_ADDR <= IB_MREQ.addr(12) & IB_MREQ.addr(8 downto 1);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, BRAM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable iback : slbit := '0';
variable imemwe : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
iback := '0';
imemwe := '0';
-- ibus address decoder
n.ibselcsr := '0';
n.ibselmem := '0';
if IB_MREQ.aval='1' then
if IB_MREQ.addr(12 downto 1)=ibaddr_m9312_lo(12 downto 1) then
n.ibselcsr := '1';
end if;
if IB_MREQ.addr(12 downto 9)=ibaddr_m9312_lo(12 downto 9) or
IB_MREQ.addr(12 downto 9)=ibaddr_m9312_hi(12 downto 9) then
n.ibselmem := '1';
end if;
end if;
-- ibus transactions
if IB_MREQ.racc = '1' then -- rem side --------------------------
if r.ibselcsr = '1' then -- csr access
idout(csr_ibf_locwe) := r.locwe;
idout(csr_ibf_enahi) := r.enahi;
idout(csr_ibf_enalo) := r.enalo;
if IB_MREQ.we = '1' then
n.locwe := IB_MREQ.din(csr_ibf_locwe);
n.enahi := IB_MREQ.din(csr_ibf_enahi);
n.enalo := IB_MREQ.din(csr_ibf_enalo);
end if;
iback := ibreq;
end if;
else -- loc side --------------------------
if r.ibselmem = '1' then -- mem access
idout := BRAM_DO;
if IB_MREQ.re = '1' then -- read request
if IB_MREQ.addr(12) = '0' then -- LO-ROM
iback := r.enalo; -- ack if enabled
else -- HI-ROM
iback := r.enahi; -- ack if enabled
end if;
elsif IB_MREQ.we = '1' then -- write request
iback := r.locwe;
imemwe := r.locwe;
end if;
end if;
end if; -- IB_MREQ.racc
N_REGS <= n;
BRAM_WE <= imemwe;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= '0';
end process proc_next;
end syn;
| gpl-3.0 | 15007894eae20b224ed5fd5e2459652f | 0.475116 | 3.546588 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/s3board/sys_tst_sram_s3.vhd | 1 | 10,036 | -- $Id: sys_tst_sram_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_s3 - syn
-- Description: test of s3board sram and its controller
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_sp1c
-- tst_sram
-- bplib/s3board/s3_sram_memctl
--
-- Test bench: tb/tb_tst_sram_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-12-20 614 14.7 131013 xc3s1000-4 816 1801 96 1135 t 18.3 ns
-- 2014-08-13 581 14.7 131013 xc3s1000-4 664 1433 64 899 t 16.3 ns
-- 2011-12-21 352 12.1 M53d xc3s1000-4 664 1433 64 898 p 17.1 ns
-- 2010-12-31 352 12.1 M53d xc3s200-4 644 1366 36 856 p 14.6 ns
-- 2010-11-06 336 12.1 M53d xc3s200-4 605 1334 36 824 p 14.6 ns
-- 2010-05-21 291 11.4 L68 xc3s200-4 600 1301 18 795 p 16.6 ns
-- 2010-05-16 291 11.4 L68 xc3s200-4 594 1273 18 764 p 15.3 ns
-- 2010-04-04 274 11.4 L68 xc3s200-4 607 1303 18 807 p 14.2 ns
-- 2009-11-14 249 11.2 L46 xc3s1000-4 603 1340 18 795 p 18.8 ns
-- 2009-11-08 248 11.2 L46 xc3s1000-4 594 1329 18 771 p 15.4 ns
-- 2009-11-08 248 8.2.3 I34 xc3s1000-4 616 1320 18 805 p 16.3 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-10 785 2.3.4 SWI(1) now XON
-- 2016-07-09 784 2.3.3 tst_sram with AWIDTH and 22bit support
-- 2016-03-19 748 2.3.2 define rlink SYSID
-- 2015-04-11 666 2.3.1 rearrange XON handling
-- 2014-08-28 588 2.3 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 2.2 rb_mreq addr now 16 bit
-- 2011-12-21 442 2.1.4 use rlink_sp1c
-- 2011-11-21 432 2.1.3 now numeric_std clean
-- 2011-07-08 390 2.1.2 use now sn_humanio
-- 2011-07-02 387 2.1.1 use bp_rs232_2line_iob now
-- 2010-12-31 352 2.1 port to rbv3
-- 2010-11-06 336 2.0.5 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 2.0.4 rename RRI_LAM->RB_LAM;
-- 2010-06-03 300 2.0.3 use default FAWIDTH for rri_core_serport
-- 2010-05-32 294 2.0.2 rename sys_tst_sram -> sys_tst_sram_s3
-- 2010-05-21 292 2.0.1 move memory controller to top level entity
-- 2010-05-16 291 2.0 move tester code to tst_sram; use s3_rs232_iob_int
-- 2010-05-02 287 1.1.6 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- 2010-05-01 286 1.1.5 set RTSFLUSH=>false till tested; rri_a_ -> rbaddr_
-- 2010-04-24 281 1.1.4 mv from vlib/s3board/sys/sys_s3board_memtest.vhd
-- 2010-04-18 279 1.1.3 drop RTSFBUF generic for rri_serport
-- 2010-04-10 275 1.1.2 use s3_humanio, rri_core_serport;
-- 2010-04-04 274 1.1.1 add CE_USEC, CP_FLUSH, CTS_N, RTS_N signals
-- 2009-11-14 249 1.1 ported to rri V2 rb_mreq/rb_sres interface; cleaner
-- rbus logic, should work with 2nd rbus device
-- 2008-02-17 117 1.0.5 use req,we rather req_r,req_w interface
-- 2008-01-20 113 1.0.4 rename memdrv->memctl_s3sram
-- 2008-01-20 112 1.0.3 rename clkgen->clkdivce
-- 2007-12-24 105 1.0.2 now fully implemented
-- 2007-12-22 104 1.0.1 finish mblk, add smem and sblk.
-- 2007-12-20 103 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_s3 is -- top level
-- implements s3board_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end sys_tst_sram_s3;
architecture syn of sys_tst_sram_s3 is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv18 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"01"; -- s3board
constant sysid_vers : slv8 := x"00";
begin
CLK <= I_CLK50; -- use 50MHz as system clock
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
HIO : sn_humanio
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
RTAWIDTH => 12,
SYSID => (others=>'0'),
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => x"ffe8")
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 18)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
MEM_RESET => MEM_RESET,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
SRAMCTL : s3_sram_memctl
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
RB_SRES <= RB_SRES_TST; -- can be sres_or later...
RB_LAM(0) <= RB_LAM_TST;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
end syn;
| gpl-3.0 | a1e3997db3504a7bd02299efc4ac3504 | 0.512654 | 2.902256 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_uart_autobaud.vhd | 1 | 6,458 | -- $Id: serport_uart_autobaud.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_autobaud - syn
-- Description: serial port UART - autobauder
--
-- Dependencies: -
-- Test bench: tb/tb_serport_autobaud
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-02-01 641 1.1 add CLKDIV_F
-- 2011-10-22 417 1.0.4 now numeric_std clean
-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_autobaud is -- serial port uart: autobauder
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
CLKDIV_F: out slv3; -- clock divider fractional part
ACT : out slbit; -- active; if 1 clkdiv is invalid
DONE : out slbit -- resync done
);
end serport_uart_autobaud;
architecture syn of serport_uart_autobaud is
type state_type is (
s_idle,
s_break,
s_wait,
s_sync
);
type regs_type is record
ccnt : slv(CDWIDTH-1+3 downto 0); -- clock divider counter
mcnt : slv7; -- msec counter
seen1 : slbit; -- seen a '1' in this msec
state : state_type; -- state
end record regs_type;
-- Note on initialization of ccnt:
-- - in the current logic ccnt is incremented n-1 times when n is number
-- clock cycles with a RXD of '0'. When running at 50 MBaud, ccnt will
-- be incremented 7 (not 8!) times.
-- - the three LSBs of ccnt should be at 100 under perfect conditions, this
-- gives the best rounded estimate of CLKDIV.
-- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100
-- --> ccntinit = -3
constant ccntinit : slv(CDWIDTH-1+3 downto 0) :=
slv(to_unsigned(2**(CDWIDTH+3)-3, CDWIDTH+3));
constant mcntzero : slv7 := (others=>'0');
constant mcntlast : slv7 := (others=>'1');
constant regs_init : regs_type := (
slv(to_unsigned(CDINIT,CDWIDTH))&"000",
(others=>'0'),
'0',
s_idle
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
begin
assert CDINIT <= 2**CDWIDTH-1
report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, RESET, RXSD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iact : slbit := '0';
variable idone : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
iact := '1';
idone := '0';
case r.state is
when s_idle => -- s_idle: idle, detect break --------
iact := '0';
if CE_MSEC = '1' then -- if end of msec
if r.seen1 = '0' then -- if no '1' seen on RXD
n.mcnt := slv(unsigned(r.mcnt) + 1); -- up break timer counter
if r.mcnt = mcntlast then -- after 127 msec
n.state := s_break; -- break detected !
end if;
else -- otherwise if '1' seen
n.mcnt := mcntzero; -- clear break timer again
end if;
n.seen1 := RXSD; -- latch current RXD value
else -- otherwise if not at end-of-msec
n.seen1 := r.seen1 or RXSD; -- remember whether RXS=1 seen
end if;
when s_break => -- s_break: detect end of break ------
if RXSD = '1' then -- if end of break seen
n.state := s_wait; -- to s_wait to wait for sync char
n.ccnt := ccntinit; -- and initialize ccnt
end if; -- otherwise stay in s_break
when s_wait => -- s_wait: wait for sync char --------
if RXSD = '0' then -- if start bit if sync char seen
n.state := s_sync; -- to s_sync to wait for end of '0'
end if; -- otherwise stay in s_wait
when s_sync => -- s_sync: wait for end of '0' bits --
if RXSD = '1' then -- if end of '0' bits seen
n.state := s_idle; -- to s_idle, autobauding done
idone := '1'; -- emit done pulse
else -- otherwise still in '0' of sync
n.ccnt := slv(unsigned(n.ccnt) + 1); -- increment ccnt
end if;
when others => null; -- -----------------------------------
end case;
N_REGS <= n;
CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3);
CLKDIV_F <= r.ccnt(2 downto 0);
ACT <= iact or RESET;
DONE <= idone;
end process proc_next;
end syn;
| gpl-3.0 | 28d7cd3e075f23d928b9891bce4781fa | 0.510684 | 3.895054 | false | false | false | false |
jasonpeng/cg3207-proj | ALU/Logical.vhd | 1 | 1,694 | --------------------------------------------------------------------------
-- Logical
--------------------------------------------------------------------------
-- 0,00,000 NOP
-- 0,00,001 AND
-- 0,00,010 OR
-- 0,00,011 XOR
-- 0,00,100 NOR
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity logic is
Port (
Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end logic;
architecture beh_logic of logic is
begin
process (Control, Operand1, Operand2)
variable temp : STD_LOGIC_VECTOR (31 downto 0);
begin
case Control is
when "000" => -- NOP
Result1 <= Operand1;
Result2 <= Operand2;
Debug <= X"0000000";
when "001" => -- AND
Result1 <= Operand1 and Operand2;
Result2 <= X"00000000";
Debug <= X"0000000";
when "010" => -- OR
Result1 <= Operand1 or Operand2;
Result2 <= X"00000000";
Debug <= X"0000000";
when "011" => -- XOR
Result1 <= Operand1 xor Operand2;
Result2 <= X"00000000";
Debug <= X"0000000";
when "100" => -- NOR
Result1 <= Operand1 nor Operand2;
Result2 <= X"00000000";
Debug <= X"0000000";
when others =>
Result1 <= X"FFFFFFFF";
Result2 <= X"FFFFFFFF";
Debug <= X"FFFFFFF";
end case;
end process;
end beh_logic;
| gpl-2.0 | becf15d987dcd89e3edd99b2672d7115 | 0.507674 | 3.706783 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/tb_serport_uart_rxtx.vhd | 1 | 7,277 | -- $Id: tb_serport_uart_rxtx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_uart_rxtx - sim
-- Description: Test bench for serport_uart_rxtx
--
-- Dependencies: simlib/simclk
-- tbd_serport_uart_rxtx [UUT]
--
-- To test: serport_uart_rxtx
--
-- Target Devices: generic
--
-- Verified (with tb_serport_uart_rxtx_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-21 91 - 0.26 - - c:ok
-- 2007-10-14 89 - 0.26 - - c:ok
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-12 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.2 use new simclk/simclkcnt
-- 2011-10-22 417 1.1.3 now numeric_std clean
-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serportlib.all;
entity tb_serport_uart_rxtx is
end tb_serport_uart_rxtx;
architecture sim of tb_serport_uart_rxtx is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(15, 13));
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXSD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_serport_uart_rxtx
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_uart_rxtx_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable irate : integer := 16;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
read_ea(iline, irate);
CLKDIV <= slv(to_unsigned(irate-1, 13));
when "send " => -- send
read_ea(iline, idelta);
read_ea(iline, itxdata);
while TXBUSY='1' loop
wait for clock_period;
end loop;
wait for idelta*clock_period;
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
TXDATA <= itxdata;
TXENA <= '1';
N_MON_VAL <= '1';
N_MON_DAT <= itxdata;
wait for clock_period;
TXENA <= '0';
N_MON_VAL <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
idelta := 0;
while TXBUSY='1' or RXACT='1' loop
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 12*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_DAT_1 <= N_MON_DAT;
if RXVAL='1' or RXERR='1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | fac44d718eb80a2e9d62bd2fa38a2c33 | 0.511475 | 3.615002 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/ALU.vhd | 1 | 2,700 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.fixed_pkg.all;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (3 downto 0);
result : out STD_LOGIC_VECTOR (31 downto 0);
flags : out STD_LOGIC_VECTOR (3 downto 0));
end ALU;
architecture Behavioral of ALU is
component fixed_point_alu
port(
A : in STD_LOGIC_VECTOR(31 downto 0);
B : in STD_LOGIC_VECTOR(31 downto 0);
result : out STD_LOGIC_VECTOR(31 downto 0);
sel : in STD_LOGIC);
end component;
signal output, normal_output : std_logic_vector(32 downto 0);
signal fixed_output : std_logic_vector(31 downto 0);
begin
main: process(A, B, sel, fixed_output, normal_output, output) is
begin
--Set flags to 0 as default
flags <= "0000";
--This actually performs the operation chosen by the select lines
--The reason the output variable is 33 bits wide is to accomodate for
--the carry bit, and it also helps a lot with shifting operations. By
--the way, I did try the built-in shift operations, but without much
--luck.
case sel is
when "0000" => --add
normal_output <= ('0' & A(31 downto 0)) + ('0' & B(31 downto 0));
when "0001" => --sub
normal_output <= ('0' & A(31 downto 0)) - ('0' & B(31 downto 0));
when "0010" => --and
normal_output <= '0' & (A and B);
when "0011" => --or
normal_output <= '0' & (A or B);
when "0100" => --xor
normal_output <= '0' & (A xor B);
when "0101" => --cp
normal_output <= ('0' & A);
when "0110" => --sll
normal_output <= (A(31 downto 0) & '0');
when "0111" => --srl
normal_output <= ("00" & A(31 downto 1));
when "1000" => --rol
normal_output <= (A(0) & A(0) & A(31 downto 1));
when "1001" => --ror
normal_output <= (A(30) & A(30 downto 0) & A(31));
when others =>
normal_output <= ('0' & A);
end case;
if sel(3 downto 1) = "101" then
output <= '0' & fixed_output;
else
output <= normal_output;
end if;
--This if statement generates the flags
if (A > B) then --Greater than
flags(1) <= '1';
elsif (A = B) then --Equal to
flags(2) <= '1';
elsif (A < B) then --Less than
flags(3) <= '1';
end if;
flags(0) <= output(32); --Carry flag (33rd bit)
result <= output(31 downto 0);
end process;
fpalu : fixed_point_alu
port map(
A => A,
B => B,
result => fixed_output,
sel => sel(0)
);
end Behavioral;
| mit | 51f7544258343866486f8d7061aa520b | 0.571481 | 3 | false | false | false | false |
nanomolina/vhdl_examples | ROM/test_imem.vhd | 2 | 727 | library ieee;
use ieee.std_logic_1164.all;
entity test_imem is
end entity;
architecture arq_test_imem of test_imem is
component imem
port (a: in std_logic_vector(5 downto 0);
y: out std_logic_vector(31 downto 0));
end component;
signal a1: std_logic_vector(5 downto 0):="000000";
signal y1: std_logic_vector(31 downto 0);
begin
prueba0: imem port map (a=>a1, y=>y1);
process
begin
a1 <= "100000";
wait for 5 ns;
a1 <= "000100";
wait for 5 ns;
a1 <= "111000";
wait for 5 ns;
a1 <= "111111";
wait for 5 ns;
a1 <= "110000";
wait for 5 ns;
a1 <= "101010";
end process;
end architecture;
| gpl-3.0 | 404473217b085c9f0c0086b1d7e01ac1 | 0.557084 | 3.413146 | false | true | false | false |
wfjm/w11 | rtl/ibus/ibdr_tm11.vhd | 1 | 16,946 | -- $Id: ibdr_tm11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_tm11 - syn
-- Description: ibus dev(rem): TM11
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-06-04 686 14.7 131013 xc6slx16-2 79 144 0 53 s 4.4
-- 2015-05-15 682 14.7 131013 xc6slx16-2 117 209 0 76 s 3.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-06-27 695 1.0.1 add missing BESET to sensitivity list
-- 2015-06-04 686 1.0 Initial version
-- 2015-05-15 682 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_tm11 is -- ibus dev(rem): TM11
-- fixed address: 172520
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_tm11;
architecture syn of ibdr_tm11 is
constant ibaddr_tm11 : slv16 := slv(to_unsigned(8#172520#,16));
constant ibaddr_sr : slv3 := "000"; -- sr address offset
constant ibaddr_cr : slv3 := "001"; -- cr address offset
constant ibaddr_bc : slv3 := "010"; -- bc address offset
constant ibaddr_ba : slv3 := "011"; -- ba address offset
constant ibaddr_db : slv3 := "100"; -- db address offset
constant ibaddr_rl : slv3 := "101"; -- rl address offset
constant sr_ibf_icmd : integer := 15;
constant sr_ibf_eof : integer := 14;
constant sr_ibf_pae : integer := 12;
constant sr_ibf_eot : integer := 10;
constant sr_ibf_rle : integer := 9;
constant sr_ibf_bte : integer := 8;
constant sr_ibf_nxm : integer := 7;
constant sr_ibf_onl : integer := 6;
constant sr_ibf_bot : integer := 5;
constant sr_ibf_wrl : integer := 2;
constant sr_ibf_rew : integer := 1;
constant sr_ibf_tur : integer := 0;
constant cr_ibf_err : integer := 15;
subtype cr_ibf_den is integer range 14 downto 13;
constant cr_ibf_ini : integer := 12;
constant cr_ibf_pevn : integer := 11;
constant cr_ibf_unit2 : integer := 10;
subtype cr_ibf_unit is integer range 9 downto 8;
constant cr_ibf_rdy : integer := 7;
constant cr_ibf_ie : integer := 6;
subtype cr_ibf_ea is integer range 5 downto 4;
subtype cr_ibf_func is integer range 3 downto 1;
constant cr_ibf_go : integer := 0;
subtype ba_ibf_ba is integer range 15 downto 1;
subtype db_ibf_db is integer range 7 downto 0;
constant rl_ibf_reof : integer := 10;
constant rl_ibf_reot : integer := 9;
constant rl_ibf_ronl : integer := 8;
constant rl_ibf_rbot : integer := 7;
constant rl_ibf_rwrl : integer := 6;
constant rl_ibf_rrew : integer := 5;
subtype rl_ibf_runit is integer range 2 downto 1;
constant func_unload : slv3 := "000"; -- func: unload
constant func_read : slv3 := "001"; -- func: read
constant func_write : slv3 := "010"; -- func: write
constant func_weof : slv3 := "011"; -- func: write eof
constant func_sforw : slv3 := "100"; -- func: space forward
constant func_sback : slv3 := "101"; -- func: space backward
constant func_wrteg : slv3 := "110"; -- func: write extend interrec gap
constant func_rewind : slv3 := "111"; -- func: rewind
constant rfunc_wunit : slv3 := "001"; -- rem func: write runit
constant rfunc_done : slv3 := "010"; -- rem func: done (set rdy)
-- cs1 usage for rem functions
subtype cr_ibf_runit is integer range 5 downto 4; -- new runit (_wunit)
constant cr_ibf_ricmd : integer := 15; -- new icmd (_done)
constant cr_ibf_rpae : integer := 12; -- new pae (_done)
constant cr_ibf_rrle : integer := 9; -- new rle (_done)
constant cr_ibf_rbte : integer := 8; -- new bte (_done)
constant cr_ibf_rnxm : integer := 7; -- new nxm (_done)
constant cr_ibf_reaena : integer := 6; -- ena ea (_done)
subtype cr_ibf_rea is integer range 5 downto 4; -- new ea (_done)
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
sricmd : slbit; -- sr: invalid command
srpae: slbit; -- sr: parity error
srrle: slbit; -- sr: record length error
srbte: slbit; -- sr: bad tape error
srnxm: slbit; -- sr: non-existent memory
sreof: slv4; -- sr: eof-of-file
sreot: slv4; -- sr: eof-of-tape
sronl: slv4; -- sr: online
srbot: slv4; -- sr: begin-of-tape
srwrl: slv4; -- sr: write-locked
srrew: slv4; -- sr: rewinding
crden: slv2; -- cr: density
crpevn: slbit; -- cr: even oarity
crunit2: slbit; -- cr: unit[2]
crunit: slv2; -- cr: unit[1:0]
crrdy: slbit; -- cr: controller ready
crie: slbit; -- cr: interrupt enable
crea: slv2; -- cr: address extension
crfunc: slv3; -- cr: func code
bc : slv16; -- bc: byte count
ba : slv16_1; -- ba: bus address
runit : slv2; -- rem access unit
resreq : slbit; -- reset requested
ireq : slbit; -- interrupt request flag
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0','0','0', -- sricmd,srpae,srrle,srbte,srnxm
(others=>'0'), -- sreof
(others=>'0'), -- sreot
(others=>'0'), -- sronl
(others=>'0'), -- srbot
(others=>'0'), -- srwrl
(others=>'0'), -- srrew
(others=>'0'), -- crden
'0','0', -- crpevn,crunit2
(others=>'0'), -- crunit
'1','0', -- crrdy, crie
(others=>'0'), -- crea
(others=>'0'), -- crfunc
(others=>'0'), -- bc
(others=>'0'), -- ba
(others=>'0'), -- runit
'0', -- resreq
'0' -- ireq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK, BRESET)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 4)=ibaddr_tm11(12 downto 4) and
unsigned(IB_MREQ.addr(3 downto 1)) <= unsigned(ibaddr_rl) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel='1' then -- selected
case IB_MREQ.addr(3 downto 1) is
when ibaddr_sr => -- SR -- status register ----------
idout(sr_ibf_icmd) := r.sricmd;
idout(sr_ibf_pae) := r.srpae;
idout(sr_ibf_rle) := r.srrle;
idout(sr_ibf_bte) := r.srbte;
idout(sr_ibf_nxm) := r.srnxm;
idout(sr_ibf_tur) := r.crrdy; -- FIXME: is this correct ??
-- only units 0,..3 supported, for unit 4,..,7 return 0 --> ONL=0
if r.crunit2 = '0' then
idout(sr_ibf_eof) := r.sreof(to_integer(unsigned(r.crunit)));
idout(sr_ibf_eot) := r.sreot(to_integer(unsigned(r.crunit)));
idout(sr_ibf_onl) := r.sronl(to_integer(unsigned(r.crunit)));
idout(sr_ibf_bot) := r.srbot(to_integer(unsigned(r.crunit)));
idout(sr_ibf_wrl) := r.srwrl(to_integer(unsigned(r.crunit)));
idout(sr_ibf_rew) := r.srrew(to_integer(unsigned(r.crunit)));
end if;
when ibaddr_cr => -- CR -- control register ---------
idout(cr_ibf_err) := r.sricmd or
r.sreof(to_integer(unsigned(r.crunit))) or
r.srpae or
r.sreot(to_integer(unsigned(r.crunit))) or
r.srrle or
r.srnxm;
idout(cr_ibf_den) := r.crden;
idout(cr_ibf_pevn) := r.crpevn;
idout(cr_ibf_unit2) := r.crunit2;
idout(cr_ibf_unit) := r.crunit;
idout(cr_ibf_rdy) := r.crrdy;
idout(cr_ibf_ie) := r.crie;
idout(cr_ibf_ea) := r.crea;
idout(cr_ibf_func) := r.crfunc;
if IB_MREQ.we = '1' then
if ibrem = '0' then
if r.crrdy = '1' then
if IB_MREQ.be1 = '1' then
n.crden := IB_MREQ.din(cr_ibf_den);
if IB_MREQ.din(cr_ibf_ini) = '1' then
n.resreq := '1';
end if;
n.crpevn := IB_MREQ.din(cr_ibf_pevn);
n.crunit2 := IB_MREQ.din(cr_ibf_unit2);
n.crunit := IB_MREQ.din(cr_ibf_unit);
end if;
if IB_MREQ.be0 = '1' then
n.crie := IB_MREQ.din(cr_ibf_ie);
if n.crie = '0' then -- if IE set to 0
n.ireq := '0'; -- cancel pending interrupt
end if;
n.crea := IB_MREQ.din(cr_ibf_ea);
n.crfunc := IB_MREQ.din(cr_ibf_func);
if IB_MREQ.din(cr_ibf_go) = '1' then
n.sricmd := '0'; -- clear errors
n.srpae := '0';
n.srrle := '0';
n.srbte := '0';
n.srnxm := '0';
n.sreof := (others=>'0'); -- clear position status flags
n.sreot := (others=>'0');
n.srbot := (others=>'0');
n.srrew := (others=>'0');
n.crrdy := '0'; -- mark busy
ilam := '1'; -- rri lam
else
if r.crie='0' and n.crie='1' then -- if IDE 0->1 transition
n.ireq := '1'; -- issue software interrupt
end if;
end if;
end if;
else
n.sricmd := '1';
end if;
else -- rem write access. GO not checked
-- always treated as remote function
case IB_MREQ.din(cr_ibf_func) is
when rfunc_wunit => -- rfunc: wunit -----------------
n.runit := IB_MREQ.din(cr_ibf_runit);
when rfunc_done => -- rfunc: done ------------------
n.sricmd := IB_MREQ.din(cr_ibf_ricmd);
n.srpae := IB_MREQ.din(cr_ibf_rpae);
n.srrle := IB_MREQ.din(cr_ibf_rrle);
n.srbte := IB_MREQ.din(cr_ibf_rbte);
n.srnxm := IB_MREQ.din(cr_ibf_rnxm);
if IB_MREQ.din(cr_ibf_reaena) = '1' then
n.crea := IB_MREQ.din(cr_ibf_rea);
end if;
n.crrdy := '1';
if r.crie = '1' then
n.ireq := '1';
end if;
when others => null; -- <>
end case;
end if; -- if ibrem
end if; -- if IB_MREQ.we='1'
when ibaddr_bc => -- BC -- byte count register -------
idout := r.bc;
if ibw1 = '1' then
n.bc(15 downto 8) := IB_MREQ.din(15 downto 8);
end if;
if ibw0 = '1' then
n.bc( 7 downto 0) := IB_MREQ.din( 7 downto 0);
end if;
when ibaddr_ba => -- BA -- bus address register ------
idout(ba_ibf_ba) := r.ba;
if ibw1 = '1' then
n.ba(15 downto 8) := IB_MREQ.din(15 downto 8);
end if;
if ibw0 = '1' then
n.ba( 7 downto 1) := IB_MREQ.din( 7 downto 1);
end if;
when ibaddr_db => -- DB -- data buffer ---------------
null;
when ibaddr_rl => -- RL -- read lines ----------------
if ibrem = '0' then
null;
else
idout(rl_ibf_reof) := r.sreof(to_integer(unsigned(r.runit)));
idout(rl_ibf_reot) := r.sreot(to_integer(unsigned(r.runit)));
idout(rl_ibf_ronl) := r.sronl(to_integer(unsigned(r.runit)));
idout(rl_ibf_rbot) := r.srbot(to_integer(unsigned(r.runit)));
idout(rl_ibf_rwrl) := r.srwrl(to_integer(unsigned(r.runit)));
idout(rl_ibf_rrew) := r.srrew(to_integer(unsigned(r.runit)));
idout(rl_ibf_runit) := r.runit;
if IB_MREQ.we = '1' then
n.sreof(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_reof);
n.sreot(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_reot);
n.sronl(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_ronl);
n.srbot(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_rbot);
n.srwrl(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_rwrl);
n.srrew(to_integer(unsigned(r.runit))) := IB_MREQ.din(rl_ibf_rrew);
end if;
end if;
when others => -- doesn't happen, ibsel only for
-- subrange up to rl, and all regs are
-- decoded above
null;
end case;
end if;
if BRESET = '1' then
n.resreq := '1';
end if;
if r.resreq = '1' then
n.sricmd := '0';
n.srpae := '0';
n.srrle := '0';
n.srbte := '0';
n.srnxm := '0';
n.sreof := (others=>'0');
n.sreot := (others=>'0');
n.crden := (others=>'0');
n.crpevn := '0';
n.crunit2 := '0';
n.crunit := (others=>'0');
n.crrdy := '1';
n.crie := '0';
n.crea := (others=>'0');
n.crfunc := (others=>'0');
n.bc := (others=>'0');
n.ba := (others=>'0');
n.resreq := '0';
n.ireq := '0';
end if;
if EI_ACK = '1' or n.crie = '0' then -- interrupt executed or ie disabled
n.ireq := '0'; -- cancel request
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= r.ireq;
end process proc_next;
end syn;
| gpl-3.0 | 774f6c081262a10f862185ba6493f930 | 0.446831 | 3.578125 | false | false | false | false |
kb3gtn/fpga_edc | src/spi_master.vhd | 1 | 10,055 | -----------------------------------------------------------------------------
-- SPI_MASTER.vhd
--
-- This block is a SPI Master uart that is designed to interface with
-- a simple databus master address/data bus inteface.
--
-- This register exposes 3 registers
--
-- A status Register, and a data registers, Clock Rate Register
--
-- Conf register:
--
-- Bit0 - Chip Select 0 line value.. '1' -- asserted, '0' -- de-asserted
-- Bit1 - Chip Select 1 line value.. '1' -- asserted, '0' -- de-asserted
-- Bit2 - Chip Select 2 line value.. '1' -- asserted, '0' -- de-asserted
-- Bit3 - Chip Select 4 line value.. '1' -- asserted, '0' -- de-asserted
-- Bit4 - Clk Edge for data change.. '1' -- falling, '0' -- rising (clk polarity)
-- Bit5 - Data Polarity.. '1' -- Inverted, '0' -- Normal
-- Bit6 - Bit Order.. '1' -- msb first, '0' -- lsb first
-- Bit7 - Reset.. '1' asserted, '0' de-asserted ( running )
--
-- Chip selects are basically GPIO..
-- Can have multiple chip select asserted if you so desire..
--
-- Data register:
-- Bit(7 - 0) -- data byte to transmit
--
--
-- Clock Rate Register
-- This register takes a value that defines the clock rate used in SPI operations
--
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_master is
generic (
-- default address for this module to use..
data_reg_addr : std_logic_vector( 6 downto 0) := "000000"; -- address 0
conf_reg_addr : std_logic_vector( 6 downto 0) := "000001"; -- address 1
baud_reg_addr : std_logic_vector( 6 downto 0) := "000010" -- address 2
);
port (
i_clk : in std_logic; -- input system clock (50 MHz)
i_srst : in std_logic; -- input sync reset to i_clk
-- spi interface
o_spi_sclk : out std_logic; -- spi clock signal
o_spi_mosi : out std_logic; -- spi master data output
i_spi_miso : in std_logic; -- spi master data input
o_spi_cs_n : out std_logic_vector( 3 downto 0); -- chip select signals. (active low)
-- data bus interface
i_db_addr : in std_logic_vector( 6 downto 0);
i_db_wr_strb : in std_logic;
i_db_rd_strb : in std_logic;
i_db_wr_data : in std_logic_vector( 7 downto 0 );
o_db_rd_data : out std_logic_vector( 7 downto 0 )
);
end entity;
architecture b of spi_master is
--##########################################
--# SIGNALS
--##########################################
signal app_rst : std_logic;
signal spi_sclk_strb : std_logic; -- clock enable strobe for sclk state change.
signal spi_sclk : std_logic; -- clock normal (data change on rising edge)
signal spi_sclk_n : std_logic; -- clock inverted (data change on falling edge)
signal spi_mosi : std_logic; -- mosi normal
signal spi_mosi_n : std_logic; -- mosi inverted
signal spi_miso : std_logic; -- miso normal
signal spi_miso_n : std_logic; -- miso inverted
signal db_rd_data : std_logic_vector( 7 downto 0);
signal spi_register : std_logic_vector( 7 downto 0 ); -- spi shift register
signal chip_selects : std_logic_vector( 3 downto 0 ); -- chip select outputs (gpio)
signal spi_active : std_logic; -- spi transaction in progress
signal spi_start_strb : std_logic; -- start spi transaction strobe/flag/clock enable
signal spi_bit_cntr : integer; -- number of bits sent
signal baud_cntr : unsigned( 11 downto 0 );
signal baud_val : unsigned( 11 downto 0 );
-- memory map regsiters
signal baud_reg : std_logic_vector( 7 downto 0 );
signal conf_reg : std_logic_vector( 7 downto 0 );
signal spi_data_reg : std_logic_vector( 7 downto 0 );
begin
-- internal register to output bus
o_db_rd_data <= db_rd_data;
-- chip select outputs
o_spi_cs_n <= conf_reg( 3 downto 0 );
-- databus interface
db_slave : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
app_rst <= '0';
baud_reg <= (others=>'0');
conf_reg <= (others=>'0');
db_rd_data <= (others=>'Z');
else
-- writes over reads
if ( i_db_wr_strb = '1' ) then
-- we have a write on the bus
-- mux based on address
if ( i_db_addr = data_reg_addr ) then
spi_data_reg <= i_db_wr_data;
spi_start_strb <= '1'; -- signal we have a new byte to send..
end if;
if ( i_db_addr = baud_reg_addr ) then
baud_reg <= i_db_wr_data;
end if;
if ( i_db_addr = conf_reg_addr ) then
conf_reg <= i_db_wr_data;
end if;
-- in all cases, we are not performing a read..
-- high Z our drive on the read bus
db_rd_data <= (others=>'Z');
else
spi_start_strb <= '0';
if ( i_db_rd_strb = '1' ) then
if( i_db_addr = data_reg_addr ) then
db_rd_data <= spi_register;
end if;
if ( i_db_addr = baud_reg_addr ) then
db_rd_data <= baud_reg;
end if;
if ( i_db_addr = conf_reg_addr ) then
db_rd_data <= conf_reg;
end if;
else
db_rd_data <= (others=>'Z'); -- high Z bus
end if;
end if;
end if;
end if;
end process;
-- power of 2 scaling factor to baud value from memory mapped register
-- to internal counter limit..
baud_val <= unsigned( "00" & baud_reg & "00" ); -- multiply by 4
-- simple clock divider to get
-- bit rate for spi uart.
baud_gen : process( i_clk )
begin
if ( rising_edge(i_clk) ) then
if ( i_srst = '1' or app_rst = '1' ) then
baud_cntr <= (others=>'0');
spi_sclk_strb <= '0';
else
if ( baud_cntr = baud_val ) then
spi_sclk_strb <= '1'; -- next bit period strobe..
baud_cntr <= (others=>'0');
else
spi_sclk_strb <= '0';
baud_cntr <= baud_cntr + 1;
end if;
end if;
end if;
end process;
-- generate inverted/normal sclk as needed
o_spi_sclk <= conf_reg(4) xor spi_sclk; -- if conf_reg = '1', clock will be inverted.
-- update spi_sclk when we get a strobe.
clk_gen : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' or app_rst = '1' ) then
spi_sclk <= '0';
else
if ( spi_sclk_strb = '1' and spi_active = '1' ) then
if ( spi_sclk = '1' ) then
spi_sclk <= '0';
else
spi_sclk <= '1';
end if;
else
spi_sclk <= '0';
end if;
end if;
end if;
end process;
-- SPI shift register
spi_shiftreg : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' or app_rst = '1' ) then
spi_register <= (others=>'0');
spi_bit_cntr <= 0;
spi_active <= '0';
else
if ( spi_active = '0' and spi_start_strb = '1' ) then
spi_active <= '1';
spi_register <= spi_data_reg; -- load in new contents to send
spi_bit_cntr <= 0;
else
if ( spi_sclk_strb = '1' and spi_active = '1' ) then
if ( spi_bit_cntr = 7 ) then
spi_bit_cntr <= 0;
spi_active <= '0';
else
spi_bit_cntr <= spi_bit_cntr + 1;
end if;
if ( conf_reg(6) = '1' ) then
-- send MSB first
spi_mosi <= spi_register(7);
spi_register <= spi_register( 6 downto 0 ) & spi_miso;
else
-- send LSB first
spi_mosi <= spi_register(0);
spi_register <= spi_miso & spi_register( 7 downto 1 );
end if;
end if;
end if;
end if;
end if;
end process;
-- data polarity selector
-- also performs sampling of input data line to i_clk domain
spi_pol_select : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' or app_rst = '1' ) then
o_spi_mosi <= '0';
spi_miso <= '0';
else
if ( conf_reg(5) = '1' ) then
-- use inverted data
o_spi_mosi <= not spi_mosi;
spi_miso <= not i_spi_miso;
else
-- use normal data
o_spi_mosi <= spi_mosi;
spi_miso <= i_spi_miso;
end if;
end if;
end if;
end process;
end architecture;
| apache-2.0 | 713114f1272c73d127b3e4d8fa093ceb | 0.445351 | 4.092389 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/IO Adapter/pb_GPIO_Adapter.vhdl | 1 | 5,029 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze General Perpose I/O Adapter
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_GPIO_Adapter is
generic (
DEBUG : BOOLEAN := TRUE;
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
BITS : POSITIVE := 8
);
port (
Clock : IN STD_LOGIC;
Reset : IN STD_LOGIC;
-- PicoBlaze interface
Address : IN T_SLV_8;
WriteStrobe : IN STD_LOGIC;
WriteStrobe_K : IN STD_LOGIC;
ReadStrobe : IN STD_LOGIC;
DataIn : IN T_SLV_8;
DataOut : OUT T_SLV_8;
Interrupt : OUT STD_LOGIC;
Interrupt_Ack : IN STD_LOGIC;
Message : OUT T_SLV_8;
-- GPIO interface
GPIO_Out : OUT STD_LOGIC_VECTOR(BITS - 1 downto 0);
GPIO_In : IN STD_LOGIC_VECTOR(BITS - 1 downto 0)
);
end entity;
architecture rtl of pb_GPIO_Adapter is
constant REG_RW_DATAOUT : UNSIGNED(0 downto 0) := "0";
constant REG_RO_DATAIN : UNSIGNED(0 downto 0) := "1";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_DataOut : T_SLV_8 := (others => '0');
signal Reg_DataIn : T_SLV_8 := (others => '0');
begin
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Reg_DataOut <= (others => '0');
Reg_DataIn <= (others => '0');
else
if (AdrDec_we = '1') THEN
case unsigned(AdrDec_WriteAddress(0 downto 0)) is
when REG_RW_DATAOUT =>
Reg_DataOut <= AdrDec_Data;
when others =>
null;
end case;
end if;
Reg_DataIn <= GPIO_In;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_DataIn, Reg_DataOut)
begin
DataOut <= Reg_DataIn;
case unsigned(AdrDec_ReadAddress(0 downto 0)) is
when REG_RW_DATAOUT =>
DataOut <= Reg_DataOut;
when REG_RO_DATAIN =>
DataOut <= Reg_DataIn;
when others =>
null;
end case;
end process;
Interrupt <= '0';
Message <= x"00";
GPIO_Out <= Reg_DataOut;
end;
| apache-2.0 | 2d913edd6f3b6de06916f2104a59e8d2 | 0.506264 | 3.393387 | false | false | false | false |
nanomolina/vhdl_examples | ALU/ALU.vhd | 2 | 1,352 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ALU IS
PORT (a: IN std_logic_vector(31 DOWNTO 0);
b: IN std_logic_vector(31 DOWNTO 0);
alucontrol: IN bit_vector(2 DOWNTO 0);
zero: OUT bit;
result: OUT std_logic_vector(31 DOWNTO 0));
END ALU;
ARCHITECTURE ALU_arq OF ALU IS
BEGIN
PROCESS(a, b, alucontrol)
VARIABLE temp: std_logic_vector(31 DOWNTO 0);
BEGIN
CASE alucontrol IS
WHEN "000" => temp:= a AND b;
WHEN "001" => temp:= a OR b;
WHEN "010" => temp:= std_logic_vector(unsigned(a) + unsigned(b));
WHEN "011" => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
WHEN "100" => temp:= a AND (NOT b);
WHEN "101" => temp:= a OR (NOT b);
WHEN "110" => temp:= std_logic_vector(unsigned(a) - unsigned(b));
WHEN "111" =>
IF a<b THEN
temp := x"00000001";
ELSE
temp := x"00000000";
END IF;
WHEN OTHERS => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
END CASE;
result <= temp;
IF temp=x"00000000" THEN
zero <= '1';
ELSIF temp=x"00000001" THEN
zero <= '0';
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-3.0 | 8bb35093c0d3c31273606cc203002485 | 0.512574 | 3.988201 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/tb/tb_fifo_2c_dram2.vhd | 1 | 9,615 | -- $Id: tb_fifo_2c_dram2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_fifo_2c_dram2 - sim
-- Description: Test bench for fifo_2c_dram2
--
-- Dependencies: simlib/simclkv
-- simlib/simclkvcnt
-- tbd_fifo_2c_dram [UUT]
--
-- To test: fifo_2c_dram2
--
-- Target Devices: generic
-- Tool versions: viv 2015.5; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-25 751 1.0 Initial version (derived from tb_fifo_2c_dram)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_fifo_2c_dram2 is
end tb_fifo_2c_dram2;
architecture sim of tb_fifo_2c_dram2 is
signal CLKW : slbit := '0';
signal CLKR : slbit := '0';
signal RESETW : slbit := '0';
signal RESETR : slbit := '0';
signal DI : slv16 := (others=>'0');
signal ENA : slbit := '0';
signal BUSY : slbit := '0';
signal DO : slv16 := (others=>'0');
signal VAL : slbit := '0';
signal SIZEW : slv4 := (others=>'0');
signal SIZER : slv4 := (others=>'0');
signal N_HOLD : slbit := '0';
signal R_HOLD : slbit := '0';
signal CLKW_PERIOD : Delay_length := 20 ns;
signal CLKR_PERIOD : Delay_length := 20 ns;
signal CLK_HOLD : slbit := '1';
signal CLK_STOP : slbit := '0';
signal CLKW_CYCLE : integer := 0;
signal CLKR_CYCLE : integer := 0;
signal CLKR_C2OUT : Delay_length := 10 ns;
shared variable sv_nrstr : integer := 0;
shared variable sv_ndatar : integer := 0; -- data counter (fifo data output)
begin
CLKWGEN : simclkv
port map (
CLK => CLKW,
CLK_PERIOD => CLKW_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKWCNT : simclkcnt port map (CLK => CLKW, CLK_CYCLE => CLKW_CYCLE);
CLKRGEN : simclkv
port map (
CLK => CLKR,
CLK_PERIOD => CLKR_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKRCNT : simclkcnt port map (CLK => CLKR, CLK_CYCLE => CLKR_CYCLE);
UUT : entity work.tbd_fifo_2c_dram2
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => R_HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
proc_stim: process
file fstim : text open read_mode is "tb_fifo_2c_dram2_stim";
variable iline : line;
variable oline : line;
variable dname : string(1 to 6) := (others=>' ');
variable ok : boolean;
variable dtime : Delay_length := 0 ns;
variable nwait : integer := 0; --
variable nword : integer := 0; --
variable nbusy : integer := 0; -- number of busy before accept
variable idi : slv16 := (others=>'0');
variable ndataw : integer := 0; -- data counter (fifo data input)
variable iclkw_period : Delay_length := 20 ns;
variable iclkw_setup : Delay_length := 5 ns;
variable iclkr_period : Delay_length := 20 ns;
variable iclkr_c2out : Delay_length := 10 ns;
begin
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".chold" => -- .chold time
write(oline, string'(".chold"));
writeline(output, oline);
read_ea(iline, dtime);
CLK_HOLD <= '1';
wait for dtime;
CLK_HOLD <= '0';
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
when ".cdef " => -- .cdef wper wset rper rout
write(oline, string'(".cdef "));
writeline(output, oline);
read_ea(iline, iclkw_period);
read_ea(iline, iclkw_setup);
read_ea(iline, iclkr_period);
read_ea(iline, iclkr_c2out);
CLKW_PERIOD <= iclkw_period;
CLKR_PERIOD <= iclkr_period;
CLKR_C2OUT <= iclkr_c2out;
if CLK_HOLD = '0' then
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
end if;
when ".ndata" => -- .ndata num
read_ea(iline, ndataw);
sv_ndatar := ndataw;
when ".hold " => -- .hold time
read_ea(iline, dtime);
if dtime > 0 ns then
N_HOLD <= '1', '0' after dtime;
else -- allow hold abort with 0ns
N_HOLD <= '0';
end if;
when ".wait " => -- .wait ncyc
read_ea(iline, nwait);
wait for nwait*iclkw_period;
when "resetw" => -- resetw ncyc
read_ea(iline, nwait);
RESETW <= '1';
wait for nwait*iclkw_period;
RESETW <= '0';
when "resetr" => -- resetr ncyc
read_ea(iline, nwait);
sv_nrstr := nwait;
when "send " => -- send nw nd
read_ea(iline, nwait);
read_ea(iline, nword);
for i in 1 to nword loop
wait for nwait*iclkw_period;
idi := slv(to_unsigned(ndataw, 16));
ndataw := ndataw + 1;
DI <= idi;
ENA <= '1';
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for iclkw_period;
end loop;
writetimestamp(oline, CLKW_CYCLE, ": stim ");
write(oline, idi, right, 18);
write(oline, SIZEW, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(idi)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZEW)), right, 2);
write(oline, string'(")"));
if nbusy > 0 then
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
end if;
writeline(output, oline);
wait for iclkw_period;
ENA <= '0';
end loop; -- i
when others => -- bad directive
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
if N_HOLD = '1' then
wait until N_HOLD='0';
end if;
wait for 20*(iclkw_period+iclkr_period);
CLK_STOP <= '1';
writetimestamp(oline, CLKW_CYCLE, ": DONE-w ");
writeline(output, oline);
writetimestamp(oline, CLKR_CYCLE, ": DONE-r ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable nhold : integer := 0; -- number of hold cycles before accept
variable isizer_last : slv4 := (others=>'0');
variable ido : slv16 := (others=>'0');
begin
loop
wait until rising_edge(CLKR);
wait for CLKR_C2OUT;
if VAL = '1' then
if R_HOLD = '1' then
nhold := nhold + 1;
else
ido := slv(to_unsigned(sv_ndatar, 16));
sv_ndatar := sv_ndatar + 1;
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, DO, right, 18);
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(DO)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
if nhold > 0 then
write(oline, string'(" nhold="));
write(oline, nhold, right, 2);
end if;
if DO = ido then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, ido, right, 18);
end if;
writeline(output, oline);
nhold := 0;
end if;
else
if SIZER /= isizer_last then
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, string'(" "));
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
writeline(output, oline);
end if;
end if;
isizer_last := SIZER;
end loop;
end process proc_moni;
proc_clkr: process (CLKR)
begin
if rising_edge(CLKR) then
R_HOLD <= N_HOLD;
if sv_nrstr > 0 then
RESETR <= '1';
sv_nrstr := sv_nrstr - 1;
else
RESETR <= '0';
end if;
end if;
end process proc_clkr;
end sim;
| gpl-3.0 | 8c6375118a866bcc5cb0a4a0f08d26bd | 0.493188 | 3.984666 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_02400_good.vhd | 1 | 2,764 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02400_good.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of reset name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity CNE_02400_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_02400_good;
architecture Behavioral of CNE_02400_good is
begin
DFF1:DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE | gpl-3.0 | 4f715d77940951791021b6c4a74ac6ff | 0.473951 | 4.501629 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/prog_counter.vhd | 2 | 1,076 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity prog_counter is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
load : in std_logic;
increment : in std_logic
);
end prog_counter;
architecture Behavioral of prog_counter is
signal program_counter : std_logic_vector(31 downto 0); --The actual register
signal program_counter_inc : std_logic_vector(31 downto 0); --The incremented value
begin
main : process (clk, rst) is
begin
if rst = '1' then
program_counter <= (others => '0');
elsif falling_edge(clk) then
if load = '1' then
program_counter <= data_in;
end if;
if increment = '1' then
program_counter <= program_counter_inc;
end if;
end if;
end process;
data_out <= program_counter;
program_counter_inc <= program_counter + 1;
end Behavioral;
| mit | 2c8a0b794bc0da65a8cecc466c863e86 | 0.643123 | 3.270517 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/dcm_sfs_unisim_s3.vhd | 1 | 2,479 | -- $Id: dcm_sfs_unisim_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: dcm_sfs - syn
-- Description: DCM for simple frequency synthesis; SPARTAN-3 version
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-17 426 1.0.3 rename dcm_sp_sfs -> dcm_sfs, SPARTAN-3 version
-- 2011-11-10 423 1.0.2 add FAMILY generic, SPARTAN-3 support
-- 2010-11-12 338 1.0.1 drop SB_CLK generic; allow DIV=1,MUL=1 without DCM
-- 2010-11-07 337 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
architecture syn of dcm_sfs is
begin
assert (CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1) or CLKFX_MULTIPLY>=2
report "assert((FX_DIV=1 and FX_MULT)=1 or FX_MULT>=2"
severity failure;
DCM0: if CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate DCM0;
DCM1: if CLKFX_MULTIPLY>=2 generate
DCM : dcm
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => CLKFX_DIVIDE,
CLKFX_MULTIPLY => CLKFX_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE")
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end generate DCM1;
end syn;
| gpl-3.0 | c28f0bb924c997e1976d8203101e996d | 0.552642 | 3.640235 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/rlink_core.vhd | 1 | 71,684 | -- $Id: rlink_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_core - syn
-- Description: rlink core with 9bit interface (with rlmon+rbmon)
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- memlib/fifo_1c_dram
-- comlib/crc16
-- rb_sel
-- rb_sres_or_2
-- rlink_mon_sb [sim only]
-- rbus/rb_mon_sb [sim only]
--
-- Test bench: tb/tb_rlink_direct
-- tb/tb_rlink_serport
-- tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.1; ghdl 0.18-0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-05-01 892 14.7 131013 xc6slx16-2 298 709 20 226 s 7.3
-- 2016-08-21 799 14.7 131013 xc6slx16-2 297 717 20 227 s 7.2 ?incr?
-- 2015-12-26 718 14.7 131013 xc6slx16-2 312 460 16 150 s 7.0 ver 4.1
-- 2014-12-20 614 14.7 131013 xc6slx16-2 310 453 16 146 s 6.8 ver 4.0
-- 2014-08-13 581 14.7 131013 xc6slx16-2 160 230 0 73 s 6.0 ver 3.0
-- 2014-08-13 581 14.7 131013 xc3s1000-4 160 358 0 221 s 8.9 ver 3.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-05-01 892 4.2 BUGFIX: correct re-transmit after nak aborts
-- 2016-08-18 799 4.1.3 remove 'assert false' from report statements
-- 2016-05-22 767 4.1.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-26 718 4.1.1 add proc_sres: strip 'x' from RB_SRES.dout
-- 2014-12-21 617 4.1 use stat(_rbf_rbtout) to signal rbus timeout
-- 2014-12-20 614 4.0 largely rewritten; 2 FSMs; v3 protocol; 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add s_rxaddrl state
-- 2011-11-19 427 3.1.3 now numeric_std clean
-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now;
-- rename stat flags: [cd]crc->[cd]err, ioto->rbnak,
-- ioerr->rberr; '111' cmd now aborts via s_txnak and
-- sets cerr flag; set [cd]err on eop/nak aborts;
-- 2010-12-04 343 3.0 renamed rri_ -> rlink_; rbus V3 interface: use now
-- aval,re,we; add new states: s_rstart, s_wstart
-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
-- now nak on reserved cmd 111; use do_comma_abort();
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.1 add CP_FLUSH output
-- 2009-07-12 233 2.0.1 remove snoopers
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-02 121 1.1.1 comment out snoopers
-- 2007-11-24 98 1.1 new internal init handling (addr=11111111)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-15 82 1.0 Initial version, fully functional
-- 2007-06-17 58 0.5 First preliminary version
------------------------------------------------------------------------------
-- 7 supported commands:
-- nak aborts to _txnak are indicated as [nak:<nakcode>]
-- commands to rbus engine are indicated as [bcmd:<bfunc>]
--
-- 000 read reg (rreg):
-- rx: cmd al ah ccrcl ccrch
-- tx: cmd dl dh stat crcl crch
-- seq: _rxcmd _rxaddrl _rxaddrh
-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
-- _rstart[bcmd:rblk] {_txdat}*
-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
--
-- 001 read blk (rblk):
-- rx: cmd al ah cl ch ccrcl ccrch
-- tx: cmd cnt dl dh ... dcl dch stat crcl crch
-- seq: _rxcmd _rxaddrl _rxaddrh _rxcntl _rxcnth
-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
-- _txcntl _txcnth _rstart[bcmd:rblk] {_txdat}* _txdcntl _txdcnth
-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
--
-- 010 write reg (wreg):
-- rx: cmd al ah dl dh ccrcl ccrch
-- tx: cmd stat crcl crch
-- seq: _rxcmd _rxaddrl _rxaddrh _rxdatl _rxdath
-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
-- _txcmd[bcmd:wblk] _wwait0
-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
--
-- 011 write blk (wblk):
-- rx: cmd al ah cnt ccrcl ccrch dl dh ... dcrcl dcrch
-- tx: cmd dcl dch stat crcl crch
-- seq: _rxcmd _rxaddrl _rxaddrh _rxcntl _rxcnth
-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
-- _wblk {_rxwblk}* _rxdcrc[nak:dcrc,rtwblk]
-- _wblk0 _wblk1 _wblk2[bcmd:wblk] {_wblkl _wblkh}*
-- _wwait0 _wwait1 _txdcntl _txdcnth
-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
--
-- 100 list abort (labo):
-- rx: cmd ccrcl ccrch
-- tx: cmd babo stat crcl crch
-- seq: _rxcmd
-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
-- _txlabo
-- _txstat_txcrcl[nak:rtovfl] -> _txcrch -> [_rxcmd|_rxeop]
--
-- 101 read attn (attn):
-- rx: cmd ccrcl ccrch
-- tx: cmd dl dh stat crcl crch
-- seq: _rxcmd
-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd
-- _attn _txcntl _txcnth
-- _txstat _txcrcl[nak:rtovfl] -> _txcrch -> _rxcmd
--
-- 110 write init (init):
-- rx: cmd al ah dl dh ccrcl ccrch
-- tx: cmd stat crcl crch
-- seq: _rxcmd _rxaddrl _rxaddrh _rxdatl _rxdath
-- _rxccrcl[nak:ccrc] _rxccrch[nak:ccrc] _txcmd[bcmd:init]
-- _txstat _txcrc[nak:rtovfl] -> _rxcmd
--
-- 111 is currently not a legal command and causes a nak
-- seq: _txnak
--
-- The different rbus cycle types are encoded as:
--
-- init aval re we
-- 0 0 0 0 idle
-- 0 1 1 0 read
-- 0 1 0 1 write
-- 1 0 0 0 init
-- 0 0 1 0 not allowed
-- 0 0 0 1 not allowed
-- 1 0 0 1 not allowed
-- 1 0 1 0 not allowed
-- * * 1 1 not allowed
-- 1 1 * * not allowed
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
entity rlink_core is -- rlink core with 9bit interface
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit; -- rlink 9b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
attribute fsm_encoding : string;
attribute fsm_encoding of rlink_core : entity is "one-hot";
end entity rlink_core;
architecture syn of rlink_core is
-- core config registers (top 4 in rbus space)
constant rbaddr : slv16 := x"fffc"; -- fffc/4: 1111 1111 1111 11xx
constant rbaddr_cntl : slv2 := "11"; -- cntl address offset
constant rbaddr_stat : slv2 := "10"; -- stat address offset
constant rbaddr_id1 : slv2 := "01"; -- id1 address offset
constant rbaddr_id0 : slv2 := "00"; -- id0 address offset
constant d_f_cflag : integer := 8; -- d9: comma flag
subtype d_f_ctyp is integer range 2 downto 0; -- d9: comma type
subtype d_f_data is integer range 7 downto 0; -- d9: data field
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
constant cntl_rbf_anena : integer := 15; -- anena flag
constant cntl_rbf_atoena : integer := 14; -- atoena flag
subtype cntl_rbf_atoval is integer range 7 downto 0; -- atoval value
subtype stat_rbf_lcmd is integer range 15 downto 8; -- lcmd
constant stat_rbf_babo : integer := 7; -- block abort flag
constant stat_rbf_arpend : integer := 6; -- attn read pend
subtype stat_rbf_rbsize is integer range 2 downto 0; -- rbuf size
-- following 4 constants can derived from c_rlink_dat_sop,...
-- defined directly here to work around a ghdl bug
constant c_sop : slv3 := "000";
constant c_eop : slv3 := "001";
constant c_nak : slv3 := "010";
constant c_attn : slv3 := "011";
constant c_bcmd_stat : slv2 := "00";
constant c_bcmd_init : slv2 := "01";
constant c_bcmd_rblk : slv2 := "10";
constant c_bcmd_wblk : slv2 := "11";
constant cntawidth : positive := RTAWIDTH-1; -- cnt is word count
subtype cnt_f_dat is integer range cntawidth-1 downto 0; -- cnt data
-- link FSM states and state vector ----------------------------------------
type lstate_type is (
sl_idle, -- sl_idle: wait for sop
sl_txanot, -- sl_txanot: send attn notify
sl_txsop, -- sl_txsop: send sop
sl_txnak, -- sl_txnak: send nak
sl_txnakcode, -- sl_txnakcode: send nakcode
sl_txrtbuf, -- sl_txrtbuf: send rtbuf
sl_txeop, -- sl_txeop: send eop
sl_rxeop, -- sl_rxeop: wait for eop
sl_rxcmd, -- sl_rxcmd: wait for cmd
sl_rxaddrl, -- sl_rxaddrl: wait for addr low
sl_rxaddrh, -- sl_rxaddrh: wait for addr high
sl_rxdatl, -- sl_rxdatl: wait for data low
sl_rxdath, -- sl_rxdath: wait for data high
sl_rxcntl, -- sl_rxcntl: wait for count low
sl_rxcnth, -- sl_rxcnth: wait for count low
sl_rxccrcl, -- sl_rxccrcl: wait for command crc low
sl_rxccrch, -- sl_rxccrcl: wait for command crc high
sl_txcmd, -- sl_txcmd: send cmd
sl_txcntl, -- sl_txcntl: send cnt lsb
sl_txcnth, -- sl_txcnth: send cnt msb
sl_rstart, -- sl_rstart: start rreg or rblk
sl_txdat, -- sl_txdat: send data
sl_wblk, -- sl_wblk: setup rx wblk data
sl_rxwblk, -- sl_rxwblk: wait for wblk data
sl_rxdcrcl, -- sl_rxdcrcl: wait for data crc low
sl_rxdcrch, -- sl_rxdcrch: wait for data crc high
sl_wblk0, -- sl_wblk0: start wblk pipe
sl_wblk1, -- sl_wblk1: start wblk data lsb
sl_wblk2, -- sl_wblk2: start wblk data msb
sl_wblkl, -- sl_wblkl: wblk data lsb
sl_wblkh, -- sl_wblkh: wblk data msb
sl_wwait0, -- sl_wwait0: wait for wdone
sl_wwait1, -- sl_wwait1: wait for dcnt
sl_txdcntl, -- sl_txdcntl: send dcnt lsb
sl_txdcnth, -- sl_txdcnth: send dcnt lsb
sl_txlabo, -- sl_txlabo: send labo flag
sl_attn, -- sl_attn: handle attention flags
sl_txstat, -- sl_txstat: send status
sl_txcrcl, -- sl_txcrcl: send crc low
sl_txcrch -- sl_txcrch: send crc high
);
type lregs_type is record
state : lstate_type; -- state
rcmd : slv8; -- received command
lcmd : slv8; -- last command
addr : slv16; -- rbus register address
din : slv16; -- rbus input data
cnt : slv16; -- block transfer count
bcnt : slv(RTAWIDTH-1 downto 0); -- blk counter (byte and word)
attn : slv16; -- attn mask
anreq : slbit; -- attn notify request
anact : slbit; -- attn notify active
arpend : slbit; -- attn read pending
atocnt : slv8; -- attn timeout counter
babo : slbit; -- last blk aborted
nakdone : slbit; -- nak done
nakcode : slv3; -- nak code
cmdseen : slbit; -- 1st command seen
doretra : slbit; -- do a retransmit
dinl : slv8; -- din lsb for wblk pipeline
rtaddra : slv(RTAWIDTH-1 downto 0); -- rtbuf port a addr (write pointer)
rtaddra_red : slbit; -- rtaddra red (at max)
rtaddra_bad : slbit; -- rtaddra bad (inc beyond max)
rtaddra_zero : slbit; -- rtaddra was 0 in last cycle
rtaddrb : slv(RTAWIDTH-1 downto 0); -- rtbuf port b addr (aux pointer)
rtaddrb_red : slbit; -- rtaddrb red (at max)
rtaddrb_bad : slbit; -- rtaddrb bad (inc beyond max)
moneop : slbit; -- rl_moni: eop send pulse
monattn : slbit; -- rl_moni: attn send pulse
end record lregs_type;
constant bcnt_zero : slv(RTAWIDTH-1 downto 0) := (others=>'0');
constant rtaddr_zero : slv(RTAWIDTH-1 downto 0) := (others=>'0');
constant rtaddr_tred : slv(RTAWIDTH-1 downto 0) := (0=>'0', others=>'1');
constant lregs_init : lregs_type := (
sl_idle, -- state
(others=>'0'), -- rcmd
(others=>'1'), -- lcmd
(others=>'0'), -- addr
(others=>'0'), -- din
(others=>'0'), -- cnt
bcnt_zero, -- bcnt
(others=>'0'), -- attn
'0','0','0', -- anreq,anact,arpend
(others=>'0'), -- atocnt
'0', -- babo
'0', -- nakdone
(others=>'0'), -- nakcode
'0','0', -- cmdseen,doretra
(others=>'0'), -- dinl
rtaddr_zero, -- rtaddra
'0','0','0', -- rtaddra_(red|bad|zero)
rtaddr_zero, -- rtaddrb
'0','0', -- rtaddrb_(red,bad)
'0','0' -- moneop,monattn
);
-- bus FSM states and state vector -----------------------------------------
type bstate_type is (
sb_idle, -- sb_idle: wait for cmd
sb_rstart, -- sb_rstart: start rblk
sb_rreg0, -- sb_rreg0: rbus read cycle
sb_rreg1, -- sb_rreg1: send read data
sb_rwait, -- sb_rwait: wait for fifo
sb_rend, -- sb_rend: send last read data
sb_rabo0, -- sb_rabo0: rblk abort, lsb data
sb_rabo1, -- sb_rabo1: rblk abort, msb data
sb_wstart, -- sb_wstart: start wblk
sb_wreg0, -- sb_wreg0: rbus write cycle
sb_wreg1, -- sb_wreg1: wait write data
sb_wabo0, -- sb_wabo0: wblk abort, drop data
sb_wabo1 -- sb_wabo1: wblk abort, wait
);
type bregs_type is record
state : bstate_type; -- state
rbinit : slbit; -- rbus init signal
rbaval : slbit; -- rbus aval signal
rbre : slbit; -- rbus re signal
rbwe : slbit; -- rbus we signal
rbdout : slv16; -- rbus dout
rbtout: slbit; -- rbus timeout
rbnak: slbit; -- rbus no ack
rberr : slbit; -- rbus err bit set
blkabo : slbit; -- blk abort
cnt : slv(cntawidth-1 downto 0); -- word count for rblk and wblk
dcnt : slv(cntawidth-1 downto 0); -- done count for rblk and wblk
btocnt : slv(BTOWIDTH-1 downto 0); -- rbus timeout counter
dathpend : slbit; -- dat msb pending
wfifo : slbit; -- wait for fifo
stat : slv4; -- external status flags
end record bregs_type;
constant btocnt_init : slv(BTOWIDTH-1 downto 0) := (others=>'1');
constant cnt_zero : slv(cntawidth-1 downto 0) := (others=>'0');
constant bregs_init : bregs_type := (
sb_idle, -- state
'0','0','0','0', -- rbinit,rbaval,rbre,rbwe
(others=>'0'), -- rbdout
'0','0','0', -- rbtout,rbnak,rberr
'0', -- blkabo
cnt_zero, -- cnt
cnt_zero, -- dcnt
btocnt_init, -- btocnt
'0','0', -- dathpend,wfifo
(others=>'0') -- stat
);
-- config state regs --------------------------------------------------------
type cregs_type is record
anena : slbit; -- attn notification enable flag
atoena : slbit; -- attn timeout enable flag
atoval : slv8; -- attn timeout value
end record cregs_type;
constant cregs_init : cregs_type := (
'0','0', -- anena,atoena
(others=>'0') -- atoval
);
signal R_LREGS : lregs_type := lregs_init; -- state registers link FSM
signal N_LREGS : lregs_type; -- don't init (vivado fix for fsm infer)
signal R_BREGS : bregs_type := bregs_init; -- state registers bus FSM
signal N_BREGS : bregs_type; -- don't init (vivado fix for fsm infer)
signal R_CREGS : cregs_type := cregs_init; -- state registers config
signal N_CREGS : cregs_type := cregs_init; -- next value state regs config
signal RTBUF_ENB : slbit := '0';
signal RTBUF_WEA : slbit := '0';
signal RTBUF_WEB : slbit := '0';
signal RTBUF_DIA : slv8 := (others=>'0');
signal RTBUF_DIB : slv8 := (others=>'0');
signal RTBUF_DOB : slv8 := (others=>'0');
signal DOFIFO_DI : slv8 := (others=>'0');
signal DOFIFO_ENA : slbit := '0';
signal DOFIFO_DO : slv8 := (others=>'0');
signal DOFIFO_VAL : slbit := '0';
signal DOFIFO_HOLD : slbit := '0';
signal DOFIFO_SIZE : slv6 := (others=>'0');
signal CRC_RESET : slbit := '0';
signal ICRC_ENA : slbit := '0';
signal OCRC_ENA : slbit := '0';
signal ICRC_OUT : slv16 := (others=>'0');
signal OCRC_OUT : slv16 := (others=>'0');
signal OCRC_IN : slv8 := (others=>'0');
signal RBSEL : slbit := '0';
signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- internal mreq
signal RB_SRES_CLEAN : rb_sres_type := rb_sres_init; -- cleaned rb_sres
signal RB_SRES_CONF : rb_sres_type := rb_sres_init; -- config sres
signal RB_SRES_TOT : rb_sres_type := rb_sres_init; -- total sres
signal RL_BUSY_L : slbit := '0';
signal RL_DO_L : slv9 := (others=>'0');
signal RL_VAL_L : slbit := '0';
signal L2B_GO : slbit := '0';
signal L2B_CMD : slv2 := (others=>'0');
signal B2L_WDONE : slbit := '0';
begin
-- allow 11 bit (1 x 18kbit BRAM) to 15 bit (8 x 36 kbit BRAMs)
assert RTAWIDTH>=11 and RTAWIDTH<=14
report "assert(RTAWIDTH>=11 and RTAWIDTH<=15): unsupported RTAWIDTH"
severity failure;
RTBUF : ram_2swsr_rfirst_gen
generic map (
AWIDTH => RTAWIDTH,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => RTBUF_WEA, -- port A write only, thus en=we
ENB => RTBUF_ENB,
WEA => RTBUF_WEA,
WEB => RTBUF_WEB,
ADDRA => R_LREGS.rtaddra,
ADDRB => R_LREGS.rtaddrb,
DIA => RTBUF_DIA,
DIB => RTBUF_DIB,
DOA => open,
DOB => RTBUF_DOB
);
DOFIFO : fifo_1c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => DOFIFO_DI,
ENA => DOFIFO_ENA,
BUSY => open,
DO => DOFIFO_DO,
VAL => DOFIFO_VAL,
HOLD => DOFIFO_HOLD,
SIZE => DOFIFO_SIZE
);
ICRC : crc16 -- crc generator for input data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => ICRC_ENA,
DI => RL_DI(d_f_data),
CRC => ICRC_OUT
);
OCRC : crc16 -- crc generator for output data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => OCRC_ENA,
DI => OCRC_IN,
CRC => OCRC_OUT
);
SEL : rb_sel -- rbus address select for config regs
generic map (
RB_ADDR => rbaddr,
SAWIDTH => 2)
port map (
CLK => CLK,
RB_MREQ => RB_MREQ_L,
SEL => RBSEL
);
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CLEAN,
RB_SRES_2 => RB_SRES_CONF,
RB_SRES_OR => RB_SRES_TOT
);
proc_sres: process (RB_SRES)
variable sres : rb_sres_type := rb_sres_init;
variable datax01 : slv16 := (others=>'0');
variable data01 : slv16 := (others=>'0');
begin
sres.ack := to_x01(RB_SRES.ack);
sres.busy := to_x01(RB_SRES.busy);
sres.err := to_x01(RB_SRES.err);
sres.dout := to_x01(RB_SRES.dout);
if sres.ack = '1' and sres.busy = '0' and is_x(sres.dout) then
report "rlink_core: seen 'x' in rb_sres.data"
severity warning;
sres.dout := (others=>'1');
end if;
RB_SRES_CLEAN <= sres;
end process proc_sres;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_LREGS <= lregs_init;
R_BREGS <= bregs_init;
R_CREGS <= cregs_init;
else
R_LREGS <= N_LREGS;
R_BREGS <= N_BREGS;
R_CREGS <= N_CREGS;
end if;
end if;
end process proc_regs;
-- link FSM ================================================================
proc_lnext: process (R_LREGS, R_CREGS, R_BREGS,
CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,
ICRC_OUT, OCRC_OUT, RTBUF_DOB,
DOFIFO_DO, DOFIFO_VAL,
B2L_WDONE)
variable r : lregs_type := lregs_init;
variable n : lregs_type := lregs_init;
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable ido : slv9 := (others=>'0');
variable crcreset : slbit := '0';
variable icrcena : slbit := '0';
variable ocrcena : slbit := '0';
variable has_attn : slbit := '0';
variable idi8 : slv8 := (others=>'0');
variable is_comma : slbit := '0';
variable comma_typ : slv3 := "000";
variable idohold : slbit := '0';
variable cnt_iszero : slbit := '0';
variable bcnt_load : slbit := '0';
variable bcnt_val : slv(RTAWIDTH-1 downto 0) := (others=>'0');
variable bcnt_dec : slbit := '0';
variable bcnt_end : slbit := '0';
variable irtwea : slbit := '0';
variable irtreb : slbit := '0';
variable irtweb : slbit := '0';
variable addra_clear : slbit := '0';
variable addrb_load : slbit := '0';
variable addrb_sela : slbit := '0';
variable ibcmd : slv2 := (others=>'0');
variable ibgo : slbit := '0';
begin
r := R_LREGS;
n := R_LREGS;
n.moneop := '0'; -- default '0', only set by states
n.monattn := '0'; -- "
ival := '0';
ibusy := '1'; -- default is to hold input
ido := (others=>'0');
crcreset := '0';
icrcena := '0';
ocrcena := '0';
has_attn := '0';
is_comma := RL_DI(d_f_cflag); -- get comma marker
comma_typ := RL_DI(d_f_ctyp); -- get comma type
idi8 := RL_DI(d_f_data); -- get data part of RL_DI
idohold := '1'; -- default is to hold DOFIFO
cnt_iszero := '0';
if unsigned(r.cnt(cnt_f_dat)) = 0 then
cnt_iszero := '1';
end if;
bcnt_load := '0';
bcnt_val := r.cnt(cnt_f_dat) & '0'; -- default: 2*cnt (most used)
bcnt_dec := '0';
bcnt_end := '0';
if unsigned(r.bcnt) = 1 then
bcnt_end := '1';
end if;
irtwea := '0';
irtreb := '0';
irtweb := '0';
addra_clear := '0';
addrb_load := '0';
addrb_sela := '1'; -- default: addra (most used)
ibcmd := (others=>'0');
ibgo := '0';
-- handle attention "LAM's"
n.attn := r.attn or RB_LAM;
-- detect attn notify requests
if unsigned(r.attn) /= 0 then -- if any of the attn bits set
has_attn := '1';
if R_CREGS.anena='1' and r.arpend='0' then -- if attn to be send
n.anreq := '1'; -- set notify request flag
end if;
end if;
-- handle attn read timeouts
-- atocnt is held in reset when no attn read is pending
-- counting down in CE_INT cycles till zero
-- when zero, an attn notify is requested when atoena is set
-- the attn notify flag will reset atocnt to its start value
-- --> when atoena='1' this creates a notify every atoval CE_INT periods
-- --> when atoena='0' atocnt will count to zero and stay there
if r.arpend = '0' or r.anreq = '1' then -- if no attn read pending
n.atocnt := R_CREGS.atoval; -- keep at start value
else -- otherwise
if CE_INT = '1' then -- if CE_INT
if unsigned(r.atocnt) = 0 then -- alread counted down
n.anreq := R_CREGS.atoena; -- request attn notify if enabled
else -- not yet down
n.atocnt := slv(unsigned(r.atocnt) - 1); -- decrement
end if;
end if;
end if;
case r.state is
when sl_idle => -- sl_idle: wait for sop -------------
bcnt_val := r.rtaddra; -- used for nak handling
addrb_sela := '0';
n.anact := '0';
n.doretra := '0';
crcreset := '1'; -- reset crc generators
if r.anreq = '1' then -- if attn notify requested
n.anreq := '0'; -- acknowledge request
n.arpend := '1'; -- mark attn read pending
n.state := sl_txanot; -- next: send attn notify
else
ibusy := '0'; -- accept input
if RL_ENA = '1' then -- if input
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop
n.cmdseen := '0'; -- clear cmd seen flag
n.state := sl_txsop; -- next: echo it
when c_attn => -- if attn
n.state := sl_txanot; -- next: send attn notify
when c_nak =>
addrb_load := '1';
bcnt_load := '1';
n.doretra := '1';
n.state := sl_txsop; -- next: send sop
when others => null; -- other commas: silently ignore
-- especially: eop is ignored
end case;
else -- if normal data
n.state := sl_idle; -- silently dropped
end if;
end if;
end if;
when sl_txanot => -- sl_txanot: send attn notify -------
n.cnt := r.attn; -- transfer attn to cnt for transmit
n.anact := '1'; -- signal attn notify active
ido := c_rlink_dat_attn; -- send attn symbol
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.monattn := '1'; -- signal on rl_moni
n.state := sl_txcntl; -- next: send cnt lsb
end if;
when sl_txsop => -- sl_txsop: send sop ----------------
ido := c_rlink_dat_sop; -- send sop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
if r.doretra = '1' then -- if retra request
if r.rtaddra_zero = '1' then -- nothing to send
if r.nakdone = '0' then -- if no nak active
n.state := sl_txeop; -- next: send eop
else
n.state := sl_txnak; -- next: send nak
end if;
else -- something to send
irtreb := '1'; -- request first byte
n.state := sl_txrtbuf; -- next: send rtbuf
end if;
else -- or normal command
n.state := sl_rxcmd; -- next: read first command
end if;
end if;
when sl_txnak => -- sl_txnak: send nak ----------------
n.nakdone := '1'; -- set nakdone flag
ido := c_rlink_dat_nak; -- send nak character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.state := sl_txnakcode; -- next: send nakcode
end if;
when sl_txnakcode => -- sl_txnakcode: send nakcode --------
ido := '0' & "10" & (not r.nakcode) & r.nakcode;
ival := '1';
if RL_HOLD = '0' then -- wait for accept
if r.doretra = '0' then -- if no nak active
n.state := sl_rxeop; -- next: wait for eop
else -- else of nak active
n.state := sl_txeop; -- next: send eop
end if;
end if;
when sl_rxeop => -- sl_rxeop: wait for eop ------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' and comma_typ = c_eop then -- if eop seen
n.state := sl_txeop; -- next: echo eop
end if;
end if;
when sl_txrtbuf => -- sl_txrtbuf: send rtbuf ------------
ido := '0' & RTBUF_DOB; -- send rtbuf data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
bcnt_dec := '1';
if bcnt_end = '0' then -- if not yet done
irtreb := '1'; -- request next byte
else -- all done
if r.nakdone = '0' then -- if no nak active
n.state := sl_txeop; -- next: send eop
else
n.state := sl_txnak; -- next: send nak
end if;
end if;
end if;
when sl_txeop => -- sl_txeop: send eop ----------------
n.state := sl_txeop; -- needed to prevent vivado iSTATE
ido := c_rlink_dat_eop; -- send eop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.moneop := '1'; -- signal on rl_moni
n.state := sl_idle; -- next: idle state, wait for sop
end if;
when sl_rxcmd => -- sl_rxcmd: wait for cmd ------------
ibusy := '0'; -- accept input
n.cnt := slv(to_unsigned(1,16)); -- preset cnt=1 (used for rreg)
n.rcmd := idi8; -- latch cmd (follow till valid)
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
if comma_typ = c_eop then -- eop seen
n.state := sl_txeop; -- next: echo eop
else -- any other comma seen
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
end if;
else -- if not comma
if r.cmdseen = '0' then -- if first cmd
n.nakdone := '0'; -- clear nakdone flag
addra_clear := '1'; -- clear rtbuf
end if;
n.cmdseen := '1'; -- set cmd seen flag
icrcena := '1'; -- update input crc
case RL_DI(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg |
c_rlink_cmd_rblk |
c_rlink_cmd_wreg |
c_rlink_cmd_wblk |
c_rlink_cmd_init => -- for commands needing addr(data)
n.state := sl_rxaddrl; -- next: read address lsb
when c_rlink_cmd_labo |
c_rlink_cmd_attn => -- labo and attn commands
n.state := sl_rxccrcl; -- next: read command crc low
when others =>
n.nakcode := c_rlink_nakcode_cmd; -- signal bad cmd
n.state := sl_txnak; -- next: send nak
end case;
end if;
end if;
when sl_rxaddrl => -- sl_rxaddrl: wait for addr lsb -----
ibusy := '0'; -- accept input
n.addr(f_byte0) := idi8; -- latch addr lsb (follow till valid)
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak,
else
icrcena := '1'; -- update input crc
n.state := sl_rxaddrh; -- next: read addr msb
end if;
end if;
when sl_rxaddrh => -- sl_rxaddrh: wait for addr msb -----
ibusy := '0'; -- accept input
n.addr(f_byte1) := idi8; -- latch addr msb (follow till valid)
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
icrcena := '1'; -- update input crc
case r.rcmd(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg => -- for rreg command
n.state := sl_rxccrcl; -- next: read command crc low
when c_rlink_cmd_wreg |
c_rlink_cmd_init => -- for wreg, init command
n.state := sl_rxdatl; -- next: read data lsb
when others => -- for rblk or wblk
n.state := sl_rxcntl; -- next: read count lsb
end case;
end if;
end if;
when sl_rxdatl => -- sl_rxdatl: wait for data low ------
ibusy := '0'; -- accept input
n.din(f_byte0) := idi8; -- latch data lsb (follow till valid)
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
icrcena := '1'; -- update input crc
n.state := sl_rxdath; -- next: read data msb
end if;
end if;
when sl_rxdath => -- sl_rxdath: wait for data high -----
ibusy := '0'; -- accept input
n.din(f_byte1) := idi8; -- latch data msb (follow till valid)
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
icrcena := '1'; -- update input crc
n.state := sl_rxccrcl; -- next: read command crc low
end if;
end if;
when sl_rxcntl => -- sl_rxcntl: wait for count lsb -----
ibusy := '0'; -- accept input
n.cnt(f_byte0) := idi8; -- latch count lsb (follow till valid)
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
icrcena := '1'; -- update input crc
n.state := sl_rxcnth; -- next: read count msb
end if;
end if;
when sl_rxcnth => -- sl_rxcnth: wait for count msb -----
ibusy := '0'; -- accept input
n.cnt(f_byte1) := idi8; -- latch count lsb (follow till valid)
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
icrcena := '1'; -- update input crc
if unsigned(idi8(7 downto cntawidth-8)) = 0 then -- if cnt ok
n.state := sl_rxccrcl; -- next: read command crc low
else
n.nakcode := c_rlink_nakcode_cnt; -- signal bad cnt
n.state := sl_txnak; -- next: send nak
end if;
end if;
end if;
when sl_rxccrcl => -- sl_rxccrcl: wait for command crc low
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
if idi8 /= ICRC_OUT(f_byte0) then -- if crc error (lsb)
n.nakcode := c_rlink_nakcode_ccrc; -- signal bad ccrc
n.state := sl_txnak; -- next: send nak
else -- if crc ok
n.state := sl_rxccrch; -- next: wait for command crc high
end if;
end if;
end if;
when sl_rxccrch => -- sl_rxccrcl: wait for command crc high
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
if idi8 /= ICRC_OUT(f_byte1) then -- if crc error (msb)
n.nakcode := c_rlink_nakcode_ccrc; -- signal bad ccrc
n.state := sl_txnak; -- next: send nak
else -- if crc ok
n.state := sl_txcmd; -- next: echo command
end if;
end if;
end if;
when sl_txcmd => -- sl_txcmd: send cmd -----------------
ido := '0' & r.rcmd; -- send read command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
irtwea := '1';
ocrcena := '1'; -- update output crc
ibcmd := c_bcmd_stat; -- latch external status bits
ibgo := '1';
case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher
when c_rlink_cmd_rreg => -- rreg ----------------
n.state := sl_rstart; -- next: start rreg
when c_rlink_cmd_rblk => -- rblk ----------------
n.babo := '0'; -- clear babo flag
n.state := sl_txcntl;
when c_rlink_cmd_wreg => -- wreg ----------------
ibcmd := c_bcmd_wblk;
ibgo := '1';
n.state := sl_wwait0; -- next: wait for wdone
when c_rlink_cmd_wblk => -- wblk ----------------
n.babo := '0'; -- clear babo flag
if cnt_iszero = '0' then -- if cnt /= 0
n.state := sl_wblk; -- next: read wblk data
else -- otherwise cnt = 0
n.state := sl_rxdcrcl; -- next: wait for dcrc low
end if;
when c_rlink_cmd_labo => -- labo ----------------
n.state := sl_txlabo;
when c_rlink_cmd_attn => -- attn ----------------
n.state := sl_attn;
when c_rlink_cmd_init => -- init ----------------
ibcmd := c_bcmd_init;
ibgo := '1';
n.state := sl_txstat;
when others => -- '111' ---------------
n.nakcode := c_rlink_nakcode_cmd; -- signal bad cmd
n.state := sl_txnak; -- send NAK on reserved command
end case;
end if;
when sl_txcntl => -- sl_txcntl: send cnt lsb ------------
ido := '0' & r.cnt(f_byte0); -- send cnt lsb
ival := '1';
if RL_HOLD = '0' then -- wait for accept
irtwea := not r.anact; -- no rtbuf for attn notify
ocrcena := '1'; -- update output crc
n.state := sl_txcnth; -- next: send cnt msb
end if;
when sl_txcnth => -- sl_txcnth: send cnt msb ------------
ido := '0' & r.cnt(f_byte1); -- send cnt msb
ival := '1';
if RL_HOLD = '0' then -- wait for accept
irtwea := not r.anact; -- no rtbuf for attn notify
ocrcena := '1'; -- update output crc
if r.anact = '1' then -- if in attn notify
n.state := sl_txcrcl; -- next: send crc low
elsif r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
if cnt_iszero = '0' then -- if cnt /= 0
n.state := sl_rstart; -- next: start rblk
else -- otherwise cnt = 0
n.state := sl_txdcntl; -- next: send dcnt lsb
end if;
else -- otherwise, must be attn
n.state := sl_txstat; -- next: send stat
end if;
end if;
when sl_rstart => -- sl_rstart: start rreg or rblk -----
ibcmd := c_bcmd_rblk;
ibgo := '1';
bcnt_load := '1';
bcnt_val := r.cnt(cnt_f_dat) & '0'; -- 2*cnt
n.state := sl_txdat;
when sl_txdat => -- sl_txdat: send data ---------------
ido := '0' & DOFIFO_DO;
if DOFIFO_VAL = '1' then -- wait for input
ival := '1';
if RL_HOLD = '0' then -- wait for accept
idohold := '0';
irtwea := '1';
ocrcena := '1'; -- update output crc
bcnt_dec := '1';
if bcnt_end = '1' then
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := sl_txdcntl;
else
n.state := sl_txstat;
end if;
end if;
end if;
end if;
when sl_wblk => -- sl_wblk: setup rx wblk data -------
addrb_load := '1'; -- must be done here because addra
addrb_sela := '1'; -- is incremented in _txcmd
bcnt_load := '1';
bcnt_val := r.cnt(cnt_f_dat) & '0'; -- 2*cnt
n.state := sl_rxwblk;
when sl_rxwblk => -- sl_rxwblk: wait for wblk data -----
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
icrcena := '1'; -- update input crc
irtweb := '1'; -- write into rtbuf via b port
bcnt_dec := '1';
if bcnt_end = '1' then -- if all done
n.state := sl_rxdcrcl; -- next: wait for data crc low
end if;
end if;
end if;
when sl_rxdcrcl => -- sl_rxdcrcl: wait for data crc low -
ibusy := '0'; -- accept input
bcnt_val := r.cnt(cnt_f_dat) & '0'; -- 2 * cnt
addrb_sela := '1';
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
if idi8 /= ICRC_OUT(f_byte0) then -- if crc error lsb
n.nakcode := c_rlink_nakcode_dcrc; -- signal bad dcrc
n.state := sl_txnak; -- next: send nak
else -- if crc ok
n.state := sl_rxdcrch; -- next: wait for data crc high
end if;
end if;
end if;
when sl_rxdcrch => -- sl_rxdcrch: wait for data crc high
ibusy := '0'; -- accept input
bcnt_val := r.cnt(cnt_f_dat) & '0'; -- 2 * cnt
addrb_sela := '1';
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
n.nakcode := c_rlink_nakcode_frame; -- signal framing error
n.state := sl_txnak; -- next: send nak
else
if idi8 /= ICRC_OUT(f_byte1) then -- if crc error msb
n.nakcode := c_rlink_nakcode_dcrc; -- signal bad dcrc
n.state := sl_txnak; -- next: send nak
else -- if crc ok
addrb_load := '1';
bcnt_load := '1';
if r.rtaddrb_bad = '0' then -- if rtbuf ok
n.state := sl_wblk0; -- next: start wblk pipe
else -- else rtbuf ovfl
n.nakcode := c_rlink_nakcode_rtwblk; -- signal ovfl in wblk
n.state := sl_txnak; -- next: send nak
end if;
end if;
end if;
end if;
when sl_wblk0 => -- sl_wblk0: start wblk pipe ---------
if cnt_iszero = '0' then -- if cnt /= 0
irtreb := '1'; -- request next byte
n.state := sl_wblk1; -- next: start data lsb
else -- otherwise cnt = 0
n.state := sl_txdcntl; -- next: send dcnt lsb
end if;
when sl_wblk1 => -- sl_wblk1: start wblk data lsb -----
n.dinl := RTBUF_DOB; -- latch data lsb
irtreb := '1'; -- request next byte
bcnt_dec := '1';
n.state := sl_wblk2; -- next: start data msb
when sl_wblk2 => -- sl_wblk2: start wblk data msb -----
n.din := RTBUF_DOB & r.dinl; -- setup din
bcnt_dec := '1';
ibcmd := c_bcmd_wblk; -- start rbus sequencer
ibgo := '1';
if bcnt_end = '0' then -- if not yet done
irtreb := '1'; -- request next byte
n.state := sl_wblkl; -- next: enter wblk pipe
else -- all done
n.state := sl_wwait0; -- next: wait for wdone
end if;
when sl_wblkl => -- sl_wblkl: pipe wblk data lsb ------
n.dinl := RTBUF_DOB; -- latch data lsb
irtreb := '1'; -- request next byte
bcnt_dec := '1';
n.state := sl_wblkh; -- next: pipe msb
when sl_wblkh => -- sl_wblkh: pipe wblk data msb ------
if B2L_WDONE = '1' then -- if last write done
n.din := RTBUF_DOB & r.dinl; -- setup next din
bcnt_dec := '1';
if bcnt_end = '0' then -- if not yet done
irtreb := '1';
n.state := sl_wblkl; -- next: pipe lsb
else -- all done
n.state := sl_wwait0; -- next: wait last wdone
end if;
end if;
when sl_wwait0 => -- sl_wwait0: wait for wdone ---------
if B2L_WDONE = '1' then
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.state := sl_wwait1; -- next: wait for dcnt
else
n.state := sl_txstat; -- next: send stat
end if;
end if;
when sl_wwait1 => -- sl_wwait1: wait for dcnt ----------
n.state := sl_txdcntl; -- next: send dcnt lsb
when sl_txdcntl => -- sl_txdcntl: send dcnt lsb ---------
n.babo := R_BREGS.blkabo; -- remember blk abort
ido := '0' & R_BREGS.dcnt(f_byte0); -- send dcnt lsb
ival := '1';
if RL_HOLD = '0' then -- wait for accept
irtwea := '1';
ocrcena := '1'; -- update output crc
n.state := sl_txdcnth; -- next: send dcnt msb
end if;
when sl_txdcnth => -- sl_txdcnth: send dcnt msb ---------
ido := (others=>'0'); -- send dcnt msb
ido(cntawidth-9 downto 0) := R_BREGS.dcnt(cntawidth-1 downto 8);
ival := '1';
if RL_HOLD = '0' then -- wait for accept
irtwea := '1';
ocrcena := '1'; -- update output crc
n.state := sl_txstat; -- next: send stat
end if;
when sl_txlabo => -- sl_txlabo: send labo flag ---------
ido := '0' & "0000000" & r.babo; -- send babo
ival := '1';
if RL_HOLD = '0' then -- wait for accept
irtwea := '1';
ocrcena := '1'; -- update output crc
n.state := sl_txstat; -- next: send stat
end if;
when sl_attn => -- sl_attn: handle attention flags ---
n.cnt := r.attn; -- use cnt to latch attn status
n.attn := RB_LAM; -- LAM in current cycle send next time
n.arpend := '0'; -- reenable attn nofification
n.anreq := '0'; -- cancel pending notify requests
n.state := sl_txcntl; -- next: send cnt lsb (holding attn)
when sl_txstat => -- sl_txstat: send status ------------
ido(c_rlink_stat_rbf_stat) := R_BREGS.stat;
ido(c_rlink_stat_rbf_attn) := has_attn;
ido(c_rlink_stat_rbf_rbtout) := R_BREGS.rbtout;
ido(c_rlink_stat_rbf_rbnak) := R_BREGS.rbnak;
ido(c_rlink_stat_rbf_rberr) := R_BREGS.rberr;
ival := '1';
if RL_HOLD ='0' then -- wait for accept
irtwea := '1';
ocrcena := '1'; -- update output crc
n.state := sl_txcrcl; -- next: send crc low
end if;
when sl_txcrcl => -- sl_txcrcl: send crc low -----------
ido := "0" & OCRC_OUT(f_byte0); -- send crc code low
ival := '1';
if RL_HOLD = '0' then -- wait for accept
irtwea := not r.anact; -- no rtbuf for attn notify
n.state := sl_txcrch; -- next: send crc high
end if;
when sl_txcrch => -- sl_txcrch: send crc high ----------
ido := "0" & OCRC_OUT(f_byte1); -- send crc code high
-- here check for rtbuf overflow
-- if space for 1 byte complete command and write crc
if r.rtaddra_red = '0' then -- if space for 1 byte
n.lcmd := r.rcmd; -- latch current command in lcmd
ival := '1';
if RL_HOLD = '0' then -- wait for accept
irtwea := not r.anact; -- no rtbuf for attn notify
-- if this was attn notify, back to idle
if r.anact = '1' then
n.state := sl_txeop; -- next: send eop
-- here handle labo: if labo cmd and babo set, eat rest of list
elsif r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_labo and
r.babo='1' then
n.state := sl_rxeop; -- next: wait for eop
else
n.state := sl_rxcmd; -- next: read command or eop
end if;
end if;
else
n.nakcode := c_rlink_nakcode_rtovfl; -- signal rtbuf ovfl
n.state := sl_txnak; -- next: send nak
end if;
when others => null; -- <> --------------------------------
end case;
-- addra logic (write pointer)
if addra_clear = '1' then -- clear
n.rtaddra := (others=>'0');
n.rtaddra_red := '0';
n.rtaddra_bad := '0';
else
if irtwea = '1' then -- inc when write on port a
if r.rtaddra_red = '1' then -- if already red
n. rtaddra_bad := '1'; -- than flag bad
else -- still ok
n.rtaddra := slv(unsigned(r.rtaddra) + 1); -- inc
if r.rtaddra = rtaddr_tred then -- if inc'ed to red
n. rtaddra_red := '1'; -- flag red
end if;
end if;
end if;
end if;
if r.rtaddra = rtaddr_zero then
n.rtaddra_zero := '1';
else
n.rtaddra_zero := '0';
end if;
-- addrb logic (write and read pointer)
if addrb_load = '1' then -- load
if addrb_sela = '1' then
n.rtaddrb := r.rtaddra;
n.rtaddrb_red := r.rtaddra_red;
n.rtaddrb_bad := r.rtaddra_bad;
else
n.rtaddrb := (others=>'0');
n.rtaddrb_red := '0';
n.rtaddrb_bad := '0';
end if;
else
if irtreb = '1' or irtweb = '1' then -- inc when read/write on port b
if r.rtaddrb_red = '1' then -- if already red
n. rtaddrb_bad := '1'; -- than flag bad
else -- still ok
n.rtaddrb := slv(unsigned(r.rtaddrb) + 1); -- inc
if r.rtaddrb = rtaddr_tred then -- if inc'ed to red
n. rtaddrb_red := '1'; -- flag red
end if;
end if;
end if;
end if;
-- bcnt logic
if bcnt_load = '1' then
n.bcnt := bcnt_val;
else
if bcnt_dec ='1' then
n.bcnt := slv(unsigned(r.bcnt) - 1);
end if;
end if;
N_LREGS <= n;
RL_BUSY_L <= ibusy;
RL_DO_L <= ido;
RL_VAL_L <= ival;
RL_MONI.eop <= r.moneop;
RL_MONI.attn <= r.monattn;
RL_MONI.lamp <= r.arpend;
DOFIFO_HOLD <= idohold;
RTBUF_WEA <= irtwea;
RTBUF_DIA <= ido(d_f_data);
RTBUF_ENB <= irtreb or irtweb;
RTBUF_WEB <= irtweb;
RTBUF_DIB <= idi8;
CRC_RESET <= crcreset;
ICRC_ENA <= icrcena;
OCRC_ENA <= ocrcena;
OCRC_IN <= ido(d_f_data);
L2B_CMD <= ibcmd;
L2B_GO <= ibgo;
end process proc_lnext;
-- bus FSM =================================================================
proc_bnext: process (R_BREGS, R_LREGS,
RB_STAT, RB_SRES_TOT,
DOFIFO_SIZE,
L2B_CMD, L2B_GO)
variable r : bregs_type := bregs_init;
variable n : bregs_type := bregs_init;
variable bto_go : slbit := '0';
variable bto_end : slbit := '0';
variable cnt_load : slbit := '0';
variable cnt_dec : slbit := '0';
variable cnt_end : slbit := '0';
variable dcnt_clear : slbit := '0';
variable dcnt_inc : slbit := '0';
variable ival : slbit := '0';
variable ido : slv8 := (others=>'0');
variable iwdone : slbit := '0';
begin
r := R_BREGS;
n := R_BREGS;
bto_go := '0'; -- default: keep rbus timeout in reset
bto_end := '0';
if unsigned(r.btocnt) = 0 then -- if rbus timeout count at zero
bto_end := '1'; -- signal expiration
end if;
cnt_load := '0';
cnt_dec := '0';
cnt_end := '0';
if unsigned(r.cnt) = 0 then
cnt_end := '1';
end if;
dcnt_clear := '0';
dcnt_inc := '0';
ival := '0';
ido := (others=>'0');
iwdone := '0';
-- FIXME: what is proper almost full limit ?
if unsigned(DOFIFO_SIZE) >= 28 then -- almost full
n.wfifo := '1';
elsif unsigned(DOFIFO_SIZE) <= 2 then -- almost empty
n.wfifo := '0';
end if;
n.rbinit := '0'; -- clear rb(init|aval|re|we) by default
n.rbaval := '0'; -- they must always be set by the
n.rbre := '0'; -- 'previous state'
n.rbwe := '0'; --
case r.state is
when sb_idle => -- sb_idle: wait for cmd ------------
if L2B_GO = '1' then -- if cmd seen
n.stat := RB_STAT; -- always latch external status bits
n.rbtout := '0';
n.rbnak := '0';
n.rberr := '0';
n.blkabo := '0';
n.dathpend := '0';
dcnt_clear := '1';
cnt_load := '1';
case L2B_CMD is
when c_bcmd_stat => -- stat ---------------------
null; -- nothing else todo
when c_bcmd_init => -- init ---------------------
n.rbinit := '1'; -- send init pulse
when c_bcmd_rblk => -- rblk ---------------------
n.rbaval := '1'; -- start aval chunk
n.state := sb_rstart; -- next: start rblk
when c_bcmd_wblk => -- wblk ---------------------
n.rbaval := '1'; -- start aval chunk
n.state := sb_wstart; -- next: start wblk
when others => null;
end case;
end if;
when sb_rstart => -- sb_rstart: start rblk -------------
n.rbaval := '1'; -- extend aval
n.rbre := '1'; -- start read cycle
n.state := sb_rreg0; -- next: do rreg
when sb_rreg0 => -- sb_rreg0: rbus read cycle ---------
ido := r.rbdout(f_byte1);
n.stat := RB_STAT; -- follow external status bits
if r.dathpend = '1' then -- if pending data msb
ival := '1';
n.dathpend := '0';
end if;
n.rbaval := '1'; -- extend aval
bto_go := '1'; -- activate rbus timeout counter
if RB_SRES_TOT.err = '1' then -- latch rbus error flag
n.rberr := '1';
n.blkabo := '1';
end if;
n.rbdout := RB_SRES_TOT.dout; -- latch data (follow till valid)
if RB_SRES_TOT.busy='0' or bto_end='1' then -- wait non-busy or timeout
if RB_SRES_TOT.busy='1' and bto_end='1' then -- if timeout and busy
n.rbtout := '1'; -- set rbus timeout flag
n.blkabo := '1';
elsif RB_SRES_TOT.ack = '0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
n.blkabo := '1';
end if;
cnt_dec := '1';
n.state := sb_rreg1; -- next: send data lsb
else -- otherwise rbus read continues
n.rbre := '1'; -- extend read cycle
end if;
when sb_rreg1 => -- sb_rreg1: send read data ----------
ido := r.rbdout(f_byte0);
ival := '1'; -- send lsb
n.dathpend := '1'; -- signal mdb pending
dcnt_inc := not r.blkabo; -- inc dcnt if no error
if cnt_end = '0' then -- if not yet done
if r.blkabo = '0' then -- if no errors
if r.wfifo = '0' then -- if fifo fine
n.rbaval := '1'; -- extend aval
n.rbre := '1'; -- start read cycle
n.state := sb_rreg0; -- next: do rreg
else -- fifo is full
n.state := sb_rwait; -- next: fifo wait
end if;
else -- errors seen, rblk abort
n.state := sb_rabo1; -- next: send rblk abort msb data
end if;
else -- all done
n.state := sb_rend;
end if;
when sb_rwait => -- sb_rwait: wait for fifo -----------
if r.wfifo = '0' then -- if fifo fine
n.rbaval := '1'; -- start aval chunk
n.state := sb_rstart; -- restart rblk
end if;
when sb_rend => -- sb_rend: send last read data ------
ido := r.rbdout(f_byte1);
ival := '1'; -- send msb
n.dathpend := '0';
n.state := sb_idle; -- next: idle
when sb_rabo0 => -- sb_rabo0: rblk abort, lsb data ----
ido := (others=>'0');
ival := '1';
cnt_dec := '1';
n.state := sb_rabo1; -- next: send rblk abort, msb data
when sb_rabo1 => -- sb_rabo1: rblk abort, msb data ----
ido := (others=>'0');
if r.wfifo = '0' then
n.dathpend := '0'; -- cancel msb pend
ival := '1';
if cnt_end = '0' then -- if not yet done
n.state := sb_rabo0; -- next: send rblk abort, lsb data
else -- all done
n.state := sb_idle; -- next: idle
end if;
end if;
when sb_wstart => -- sb_wstart: start wblk
n.rbaval := '1'; -- start aval chunk
n.rbwe := '1'; -- start write cycle
n.state := sb_wreg0;
when sb_wreg0 => -- sb_wreg0: rbus write cycle
n.stat := RB_STAT; -- follow external status bits
n.rbaval := '1'; -- extend aval
bto_go := '1'; -- activate rbus timeout counter
if RB_SRES_TOT.err = '1' then -- latch rbus error flag
n.rberr := '1';
n.blkabo := '1';
end if;
if RB_SRES_TOT.busy='0' or bto_end='1' then -- wait non-busy or timeout
if RB_SRES_TOT.busy='1' and bto_end='1' then -- if timeout and busy
n.rbtout := '1'; -- set rbus timeout flag
n.blkabo := '1';
elsif RB_SRES_TOT.ack='0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
n.blkabo := '1';
end if;
cnt_dec := '1';
iwdone := '1';
n.state := sb_wreg1;
else -- otherwise rbus write continues
n.rbwe := '1'; -- extend write cycle
end if;
when sb_wreg1 => -- sb_wreg1: wait write data
dcnt_inc := not r.blkabo; -- inc dcnt if no error
if cnt_end = '0' then -- if not yet done
if r.blkabo = '0' then -- if no errors
n.rbaval := '1'; -- extend aval
n.rbwe := '1'; -- start write cycle
n.state := sb_wreg0;
else -- errors seen, rblk abort
n.state := sb_wabo0; -- next: drop wblk rest
end if;
else -- all done
n.state := sb_idle; -- next: idle
end if;
when sb_wabo0 => -- sb_wabo0: wblk abort, drop data --
iwdone := '1'; -- drop data
cnt_dec := '1';
n.state := sb_wabo1; -- next: wblk abort, wair
when sb_wabo1 => -- sb_wabo1: wblk abort, wait --------
if cnt_end = '0' then -- if not yet done
n.state := sb_wabo0; -- next: wblk abort, drop
else -- all done
n.state := sb_idle; -- next: idle
end if;
when others => null; -- <> --------------------------------
end case;
if bto_go = '0' then -- handle access timeout counter
n.btocnt := btocnt_init; -- if bto_go=0, keep in reset
else
n.btocnt := slv(unsigned(r.btocnt) - 1);-- otherwise count down
end if;
if cnt_load = '1' then
n.cnt := R_LREGS.cnt(cnt_f_dat);
else
if cnt_dec ='1' then
n.cnt := slv(unsigned(r.cnt) - 1);
end if;
end if;
if dcnt_clear = '1' then
n.dcnt := (others=>'0');
else
if dcnt_inc ='1' then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
end if;
N_BREGS <= n;
DOFIFO_DI <= ido;
DOFIFO_ENA <= ival;
B2L_WDONE <= iwdone;
end process proc_bnext;
-- config rbus iface =======================================================
proc_cnext: process (R_CREGS, R_LREGS, RBSEL, RB_MREQ_L)
variable r : cregs_type := cregs_init;
variable n : cregs_type := cregs_init;
variable irb_ack : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
begin
r := R_CREGS;
n := R_CREGS;
irb_ack := '0';
irb_dout := (others=>'0');
-- rbus transactions
if RBSEL = '1' then
irb_ack := RB_MREQ_L.re or RB_MREQ_L.we;
-- config register writes
if RB_MREQ_L.we = '1' then
case RB_MREQ_L.addr(1 downto 0) is
when rbaddr_cntl =>
n.anena := RB_MREQ_L.din(cntl_rbf_anena);
n.atoena := RB_MREQ_L.din(cntl_rbf_atoena);
n.atoval := RB_MREQ_L.din(cntl_rbf_atoval);
when others => null;
end case;
end if;
-- rbus output driver
case RB_MREQ_L.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_anena) := r.anena;
irb_dout(cntl_rbf_atoena) := r.atoena;
irb_dout(cntl_rbf_atoval) := r.atoval;
when rbaddr_stat =>
irb_dout(stat_rbf_lcmd) := R_LREGS.lcmd;
irb_dout(stat_rbf_babo) := R_LREGS.babo;
irb_dout(stat_rbf_arpend) := R_LREGS.arpend;
irb_dout(stat_rbf_rbsize) := slv(to_unsigned(RTAWIDTH-10,3));
when rbaddr_id0 =>
irb_dout := SYSID(15 downto 0);
when rbaddr_id1 =>
irb_dout := SYSID(31 downto 16);
when others => null;
end case;
end if;
N_CREGS <= n;
RB_SRES_CONF.dout <= irb_dout;
RB_SRES_CONF.ack <= irb_ack;
RB_SRES_CONF.err <= '0';
RB_SRES_CONF.busy <= '0';
end process proc_cnext;
-- rbus driver -----------------------------------------------------
proc_mreq: process (R_LREGS, R_BREGS)
begin
RB_MREQ_L <= rb_mreq_init;
RB_MREQ_L.aval <= R_BREGS.rbaval;
RB_MREQ_L.re <= R_BREGS.rbre;
RB_MREQ_L.we <= R_BREGS.rbwe;
RB_MREQ_L.init <= R_BREGS.rbinit;
RB_MREQ_L.addr <= R_LREGS.addr;
RB_MREQ_L.din <= R_LREGS.din;
end process proc_mreq;
RB_MREQ <= RB_MREQ_L;
RL_BUSY <= RL_BUSY_L;
RL_DO <= RL_DO_L;
RL_VAL <= RL_VAL_L;
-- synthesis translate_off
RLMON: if ENAPIN_RLMON >= 0 generate
MON : rlink_mon_sb
generic map (
DWIDTH => RL_DI'length,
ENAPIN => ENAPIN_RLMON)
port map (
CLK => CLK,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY_L,
RL_DO => RL_DO_L,
RL_VAL => RL_VAL_L,
RL_HOLD => RL_HOLD
);
end generate RLMON;
RBMON: if ENAPIN_RBMON >= 0 generate
MON : rb_mon_sb
generic map (
DBASE => 8,
ENAPIN => ENAPIN_RBMON)
port map (
CLK => CLK,
RB_MREQ => RB_MREQ_L,
RB_SRES => RB_SRES_TOT,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
end generate RBMON;
-- synthesis translate_on
end syn;
| gpl-3.0 | 7b46472b2c4c9cb9de47550e7e57c89d | 0.440433 | 3.901382 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd | 1 | 5,075 | -- $Id: ram_1swar_1ar_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_1ar_gen - syn
-- Description: Dual-Port RAM with with one synchronous write and two
-- asynchronius read ports (as distributed RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's
-- 2008-03-08 123 1.0.1 use shorter label names
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_1swar_1ar_gen;
architecture syn of ram_1swar_1ar_gen is
begin
assert AWIDTH>=4 and AWIDTH<=5
report "assert(AWIDTH>=4 and AWIDTH<=5): only 4..5 bit AWIDTH supported"
severity failure;
AW_4: if AWIDTH = 4 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB(i),
SPO => DOA(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_4;
-- Note: Spartan-3 doesn't support RAM32X1D, therefore this kludge..
AW_5: if AWIDTH = 5 generate
signal WE0 : slbit := '0';
signal WE1 : slbit := '0';
signal DOA0 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOA1 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOB0 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOB1 : slv(DWIDTH-1 downto 0) := (others=>'0');
begin
WE0 <= WE and not ADDRA(4);
WE1 <= WE and ADDRA(4);
GL: for i in DWIDTH-1 downto 0 generate
MEM0 : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB0(i),
SPO => DOA0(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE0
);
MEM1 : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB1(i),
SPO => DOA1(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE1
);
DOA <= DOA0 when ADDRA(4)='0' else DOA1;
DOB <= DOB0 when ADDRB(4)='0' else DOB1;
end generate GL;
end generate AW_5;
-- AW_6: if AWIDTH = 6 generate
-- GL: for i in DWIDTH-1 downto 0 generate
-- MEM : RAM64X1D
-- generic map (
-- INIT => X"0000000000000000")
-- port map (
-- DPO => DOB(i),
-- SPO => DOA(i),
-- A0 => ADDRA(0),
-- A1 => ADDRA(1),
-- A2 => ADDRA(2),
-- A3 => ADDRA(3),
-- A4 => ADDRA(4),
-- A5 => ADDRA(5),
-- D => DI(i),
-- DPRA0 => ADDRB(0),
-- DPRA1 => ADDRB(1),
-- DPRA2 => ADDRB(2),
-- DPRA3 => ADDRB(3),
-- DPRA4 => ADDRB(4),
-- DPRA5 => ADDRB(5),
-- WCLK => CLK,
-- WE => WE
-- );
-- end generate GL;
-- end generate AW_6;
end syn;
-- Note: The VHDL instantiation example in the 8.1i Librariers Guide is wrong.
-- The annotation states that DPO is the port A output and SPO is port B
-- output. The text before is correct, DPO is port B and SPO is port A.
| gpl-3.0 | 8e4220264ee61d94ef664d8753f02d81 | 0.477044 | 3.401475 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_rl11.vhd | 1 | 27,571 | -- $Id: ibdr_rl11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rl11 - syn
-- Description: ibus dev(rem): RL11
--
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-02-28 653 14.7 131013 xc6slx16-2 80 197 12 80 s 7.9
-- 2014-06-15 562 14.7 131013 xc6slx16-2 81 199 13 78 s 8.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.0.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore
-- 2015-02-28 653 1.0 Initial verison
-- 2014-06-09 561 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_rl11 is -- ibus dev(rem): RL11
-- fixed address: 174400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_rl11;
architecture syn of ibdr_rl11 is
constant ibaddr_rl11 : slv16 := slv(to_unsigned(8#174400#,16));
constant ibaddr_rlcs : slv2 := "00"; -- rlcs address offset
constant ibaddr_rlba : slv2 := "01"; -- rlba address offset
constant ibaddr_rlda : slv2 := "10"; -- rlda address offset
constant ibaddr_rlmp : slv2 := "11"; -- rlmp address offset
-- usage of 16x16 memory bank
-- 0 0000 unused (but mirrors rlcs)
-- 1 0001 rlba
-- 2 0010 unused (but mirrors rlda)
-- 3 0011 rlmp (1st value)
-- 4 0100 rlmp (3rd value after gs; the crc)
-- 5 0101 unused
-- 6 0110 unused
-- 7 0111 unused (target for bad mprem states)
-- 11: 8 10-- sta(ds) (drive status)
-- 15:12 11-- pos(ds) (drive disk address)
constant imem_cs : slv4 := "0000"; -- unused
constant imem_ba : slv4 := "0001";
constant imem_da : slv4 := "0010"; -- unused
constant imem_mp : slv4 := "0011";
constant imem_crc : slv4 := "0100";
constant imem_bad : slv4 := "0111"; -- target for bad mprem states
constant imem_sta : slv4 := "1000";
constant imem_pos : slv4 := "1100";
subtype imf_typ is integer range 3 downto 2;
subtype imf_ds is integer range 1 downto 0;
constant rlcs_ibf_err : integer := 15;
constant rlcs_ibf_de : integer := 14;
subtype rlcs_ibf_e is integer range 13 downto 10;
subtype rlcs_ibf_ds is integer range 9 downto 8;
constant rlcs_ibf_crdy : integer := 7;
constant rlcs_ibf_ie : integer := 6;
subtype rlcs_ibf_bae is integer range 5 downto 4;
subtype rlcs_ibf_func is integer range 3 downto 1;
constant rlcs_ibf_drdy : integer := 0;
constant func_noop : slv3 := "000"; -- func: noop
constant func_wchk : slv3 := "001"; -- func: write check
constant func_gs : slv3 := "010"; -- func: get status
constant func_seek : slv3 := "011"; -- func: seek
constant func_rhdr : slv3 := "100"; -- func: read header
constant func_write : slv3 := "101"; -- func: write data
constant func_read : slv3 := "110"; -- func: read data
constant func_rnhc : slv3 := "111"; -- func: read data without header check
constant e_ok : slv4 := "0000"; -- e code: ok
constant e_incomp : slv4 := "0001"; -- e code: operation incomplete
-- defs for rem access of rlcs; func codes
constant rfunc_wcs : slv3 := "001"; -- rem func: write cs (err,de,e,drdy)
constant rfunc_wmp : slv3 := "010"; -- rem func: write mprem or mploc
-- rlcs usage or rem func=wmp
subtype rlcs_ibf_mprem is integer range 15 downto 11;
subtype rlcs_ibf_mploc is integer range 10 downto 8;
constant rlcs_ibf_ena_mprem : integer := 5;
constant rlcs_ibf_ena_mploc : integer := 4;
subtype rlda_ibf_seek_df is integer range 15 downto 7;
constant rlda_ibf_seek_hs : integer := 4;
constant rlda_ibf_seek_dir : integer := 2;
constant rlda_msk_seek : slv16 := "0000000000001011";
constant rlda_val_seek : slv16 := "0000000000000001";
constant rlda_ibf_gs_rst : integer := 3;
constant rlda_msk_gs : slv16 := "0000000011110111";
constant rlda_val_gs : slv16 := "0000000000000011";
constant sta_ibf_wde : integer := 15; -- Write data error - always 0
constant sta_ibf_che : integer := 14; -- Current head error - always 0
constant sta_ibf_wl : integer := 13; -- Write lock - used
constant sta_ibf_sto : integer := 12; -- Seek time out - used
constant sta_ibf_spe : integer := 11; -- Spin error - used
constant sta_ibf_wge : integer := 10; -- Write gate error - used
constant sta_ibf_vce : integer := 9; -- Volume check - used
constant sta_ibf_dse : integer := 8; -- Drive select error - used
constant sta_ibf_dt : integer := 7; -- Drive type - used
constant sta_ibf_hs : integer := 6; -- Head select - used
constant sta_ibf_co : integer := 5; -- Cover open - used
constant sta_ibf_ho : integer := 4; -- Heads out - used
constant sta_ibf_bh : integer := 3; -- Brush home - always 1
subtype sta_ibf_st is integer range 2 downto 0; -- Drive state
constant st_load : slv3 := "000"; -- st: Load(ing) cartidge - used
constant st_spin : slv3 := "001"; -- st: Spin(ing) up - !unused!
constant st_brush : slv3 := "010"; -- st: Brush(ing) cycle - !unused!
constant st_hload : slv3 := "011"; -- st: Load(ing) heads - !unused!
constant st_seek : slv3 := "100"; -- st: Seek(ing) - may be used
constant st_lock : slv3 := "101"; -- st: Lock(ed) on - used
constant st_unl : slv3 := "110"; -- st: Unload(ing) heads - !unused!
constant st_down : slv3 := "111"; -- st: Spin(ing) down - !unused!
-- only two mayor drive states are used
-- on: st=lock; ho=1; co=0; ( file connected in backend)
-- off: st=load; ho=0; co=1; (no file connected in backend)
subtype pos_ibf_ca is integer range 15 downto 7;
constant pos_ibf_hs : integer := 6;
subtype pos_ibf_sa is integer range 5 downto 0;
constant mploc_mp : slv3 := "000"; -- return imem(mp)
constant mploc_sta : slv3 := "001"; -- return sta(ds)
constant mploc_pos : slv3 := "010"; -- return pos(ds)
constant mploc_zero : slv3 := "011"; -- return 0
constant mploc_crc : slv3 := "100"; -- return imem(crc)
constant mprem_f_map : integer := 4; -- mprem map enable
subtype mprem_f_addr is integer range 3 downto 0;
constant mprem_f_seq : integer := 3; -- mprem seq enable
subtype mprem_f_state is integer range 2 downto 0;
constant mprem_mapseq : slv2 := "11"; -- enable map + seq
constant mprem_s_mp : slv3 := "000"; -- access imem(mp)
constant mprem_s_sta : slv3 := "001"; -- access sta(ds)
constant mprem_s_pos : slv3 := "010"; -- access pos(ds)
constant mprem_init : slv5 := "10000"; -- enable map,fix, show mp
constant ca_max_rl01 : slv9 := "011111111"; -- max cylinder for RL01 (255)
constant ca_max_rl02 : slv9 := "111111111"; -- max cylinder for RL02 (511)
type state_type is (
s_idle, -- idle: handle ibus
s_csread, -- csread: handle cs read
s_gs_rpos, -- gs_rpos: read pos(ds)
s_gs_sta, -- gs_sta: handle status
s_seek_rsta, -- seek_rsta: read sta(ds)
s_seek_rpos, -- seek_rpos: read pos(ds)
s_seek_clip, -- seek_clip: clip new ca
s_seek_wpos, -- seek_wpos: write pos(ds)
s_init -- init: handle init
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
iaddr : slv4; -- init addr counter
cserr : slbit; -- rlcs: composite error
csde : slbit; -- rlcs: drive error
cse : slv4; -- rlcs: error
csds : slv2; -- rlcs: drive select
cscrdy : slbit; -- rlcs: controller ready
csie : slbit; -- rlcs: interrupt enable
csbae : slv2; -- rlcs: bus address extenstion
csfunc : slv3; -- rlcs: function code
csdrdy : slbit; -- rlcs: drive ready
da : slv16; -- rlda shadow reg
gshs : slbit; -- gs: pos(ds)(hs) (head select)
seekdt : slbit; -- seek: drive type: 0=RL01, 1=RL02
seekcan: slv10; -- seek: cylinder address, new
seekcac: slv9; -- seek: cylinder address, clipped
ireq : slbit; -- interrupt request flag
mploc : slv3; -- mp loc state
mprem : slv5; -- mp rem state
crdone : slbit; -- control reset done since last fdone
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
s_init, -- state
imem_ba, -- iaddr
'0','0', -- cserr,csde
(others=>'0'), -- cse
(others=>'0'), -- csds
'1','0', -- cscrdy, csie
(others=>'0'), -- csbae
(others=>'0'), -- csfunc
'0', -- csdrdy
(others=>'0'), -- da
'0', -- gshs
'0', -- seekdt
(others=>'0'), -- seekcan
(others=>'0'), -- seekcac
'0', -- ireq
mploc_mp, -- mploc
mprem_init, -- mprem
'1' -- crdone
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';
signal MEM_ADDR : slv4 := (others=>'0');
signal MEM_DIN : slv16 := (others=>'0');
signal MEM_DOUT : slv16 := (others=>'0');
begin
MEM_1 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_1_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte1),
DO => MEM_DOUT(ibf_byte1));
MEM_0 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_0_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte0),
DO => MEM_DOUT(ibf_byte0));
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET='1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, MEM_DOUT, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
variable iei_req : slbit := '0';
variable imem_we0 : slbit := '0';
variable imem_we1 : slbit := '0';
variable imem_addr : slv4 := (others=>'0');
variable imem_din : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
iei_req := '0';
imem_we0 := '0';
imem_we1 := '0';
imem_addr := "00" & IB_MREQ.addr(2 downto 1);
imem_din := IB_MREQ.din;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 3)=ibaddr_rl11(12 downto 3) then
n.ibsel := '1';
end if;
-- internal state machine
case r.state is
when s_idle => -- idle: handle ibus -----------------
if r.ibsel='1' then -- selected
idout := MEM_DOUT;
imem_we0 := ibw0;
imem_we1 := ibw1;
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rlcs => -- RLCS - control register -------
imem_we0 := '0'; -- MEM not used for rlcs
imem_we1 := '0';
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
-- determine DRDY
n.csdrdy := '1';
if MEM_DOUT(sta_ibf_st) /= st_lock or -- drive not on and locked
MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check
-- ??? also CRDY=0 here ???
n.csdrdy := '0';
end if;
-- determine DE and ERR
n.cserr := '0';
if MEM_DOUT(sta_ibf_st) = st_load or -- drive off
MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check
n.csde := '1';
n.cserr := '1';
end if;
if r.csde = '1' or r.cse /= e_ok then
n.cserr := '1';
end if;
if ibrd = '1' then -- cs read
ibhold := '1';
n.state := s_csread;
elsif IB_MREQ.we = '1' then -- cs write
if ibrem = '0' then -- loc write access
if IB_MREQ.be1 = '1' then
if r.cscrdy = '1' then -- freeze csds when busy
n.csds := IB_MREQ.din(rlcs_ibf_ds);
end if;
end if;
if IB_MREQ.be0 = '1' then
n.csie := IB_MREQ.din(rlcs_ibf_ie);
n.csbae := IB_MREQ.din(rlcs_ibf_bae);
if r.cscrdy = '1' then -- controller ready
n.csfunc := IB_MREQ.din(rlcs_ibf_func); -- latch func
if IB_MREQ.din(rlcs_ibf_crdy) = '1' then -- no crdy clr
if IB_MREQ.din(rlcs_ibf_ie) = '1' and r.csie = '0' then
n.ireq := '1';
end if;
else -- crdy clr --> handle func
n.cserr := '0'; -- clear errors
n.csde := '0';
n.cse := "0000";
case IB_MREQ.din(rlcs_ibf_func) is
when func_noop => -- noop -------
n.ireq := r.csie; -- interrupt
when func_gs => -- get status -
if (r.da and rlda_msk_gs) /= rlda_val_gs then
n.cserr := '1';
n.cse := e_incomp;
n.ireq := IB_MREQ.din(rlcs_ibf_ie);
else
ibhold := '1';
n.state := s_gs_rpos;
end if;
when func_seek => -- seek -------
if (r.da and rlda_msk_seek) /= rlda_val_seek then
n.cserr := '1';
n.cse := e_incomp;
n.ireq := IB_MREQ.din(rlcs_ibf_ie);
else
ibhold := '1';
n.state := s_seek_rsta;
end if;
when others => -- all other funcs
n.cscrdy := '0'; -- signal cntl busy
ilam := '1'; -- issue lam
end case;
end if; -- else IB_MREQ.din(rlcs_ibf_crdy) = '1'
end if; -- r.cscrdy = '1'
end if; -- IB_MREQ.be0 = '1'
else -- rem write access
case IB_MREQ.din(rlcs_ibf_func) is
when rfunc_wcs =>
n.csde := IB_MREQ.din(rlcs_ibf_de);
n.cse := IB_MREQ.din(rlcs_ibf_e);
n.cscrdy := IB_MREQ.din(rlcs_ibf_crdy);
n.csbae := IB_MREQ.din(rlcs_ibf_bae);
if r.cscrdy = '0' and IB_MREQ.din(rlcs_ibf_crdy) = '1' then
n.ireq := r.csie;
end if;
when rfunc_wmp =>
if IB_MREQ.din(rlcs_ibf_ena_mprem) = '1' then
n.mprem := IB_MREQ.din(rlcs_ibf_mprem);
end if;
if IB_MREQ.din(rlcs_ibf_ena_mploc) = '1' then
n.mploc := IB_MREQ.din(rlcs_ibf_mploc);
end if;
when others => null;
end case;
end if;
end if;
when ibaddr_rlba => -- RLBA - bus address register ---
imem_din(0) := '0'; -- lsb forced 0
null;
when ibaddr_rlda => -- RLDA - disk address register --
if ibw1 = '1' then
n.da(15 downto 8) := IB_MREQ.din(15 downto 8);
end if;
if ibw0 = '1' then
n.da( 7 downto 0) := IB_MREQ.din( 7 downto 0);
end if;
when ibaddr_rlmp => -- RLMP - multipurpose register --
if ibrem = '0' then -- loc access
if ibrd = '1' then -- loc mp read
case r.mploc is
when mploc_mp => -- return imem(mp)
null;
when mploc_sta => -- return sta(ds)
imem_addr := imem_sta(imf_typ) & r.csds;
when mploc_pos => -- return pos(ds)
imem_addr := imem_pos(imf_typ) & r.csds;
n.mploc := mploc_zero;
when mploc_zero => -- return 0
idout := (others => '0');
n.mploc := mploc_crc;
when mploc_crc => -- return imem(crc)
imem_addr := imem_crc;
when others => null;
end case;
elsif IB_MREQ.we = '1' then -- loc mp write
n.mploc := mploc_mp; -- use main mp reg in future
end if;
else -- rem access
if r.mprem(mprem_f_map) = '0' then -- map off - fixed addr
imem_addr := r.mprem(mprem_f_addr);
else -- sequence
case r.mprem(mprem_f_state) is
when mprem_s_mp => -- mp {used as wc}
imem_addr := imem_mp;
if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!!
n.mprem := mprem_mapseq & mprem_s_sta;
end if;
when mprem_s_sta => -- sta(ds)
imem_addr := imem_sta(imf_typ) & r.csds;
if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!!
n.mprem := mprem_mapseq & mprem_s_pos;
end if;
when mprem_s_pos => -- pos(ds)
imem_addr := imem_pos(imf_typ) & r.csds;
when others => -- bad state
imem_addr := imem_bad;
end case;
end if;
end if;
when others => null;
end case;
end if;
when s_csread => -- csread: handle cs read -----------
idout(rlcs_ibf_err) := r.cserr;
idout(rlcs_ibf_de) := r.csde;
idout(rlcs_ibf_e) := r.cse;
idout(rlcs_ibf_ds) := r.csds;
idout(rlcs_ibf_crdy) := r.cscrdy;
idout(rlcs_ibf_ie) := r.csie;
idout(rlcs_ibf_bae) := r.csbae;
idout(rlcs_ibf_func) := r.csfunc;
idout(rlcs_ibf_drdy) := r.csdrdy;
n.state := s_idle;
when s_gs_rpos => -- gs_rpos: read pos(ds) -----------
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
n.gshs := MEM_DOUT(pos_ibf_hs); -- get hs bit
ibhold := r.ibsel;
n.state := s_gs_sta;
when s_gs_sta => -- gs_sta: handle status -----------
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
imem_we0 := '1'; -- always update
imem_we1 := '1';
imem_din := MEM_DOUT;
imem_din(sta_ibf_hs) := r.gshs;
if r.da(rlda_ibf_gs_rst) = '1' then -- if RST set
imem_din(sta_ibf_wde) := '0'; -- clear error bits
imem_din(sta_ibf_che) := '0';
imem_din(sta_ibf_sto) := '0';
imem_din(sta_ibf_spe) := '0';
imem_din(sta_ibf_wge) := '0';
imem_din(sta_ibf_vce) := '0';
imem_din(sta_ibf_dse) := '0';
end if;
n.mploc := mploc_sta; -- use sta(ds) as mp
n.ireq := r.csie; -- interrupt
n.state := s_idle;
when s_seek_rsta => -- seek_rsta: read sta(ds) -----------
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
n.seekdt := MEM_DOUT(sta_ibf_dt);
imem_din := MEM_DOUT;
if MEM_DOUT(sta_ibf_st) /= st_lock then -- drive off
imem_we0 := '1'; -- update sta
imem_we1 := '1';
imem_din(sta_ibf_sto) := '1'; -- set STO (seek time out)
n.cse := e_incomp;
n.ireq := r.csie; -- interrupt
n.state := s_idle;
else -- drive on
ibhold := r.ibsel;
n.state := s_seek_rpos;
end if;
when s_seek_rpos => -- seek_rpos: read pos(ds) -----------
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
if r.da(rlda_ibf_seek_dir) = '1' then
n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) +
unsigned('0' & r.da(rlda_ibf_seek_df)) );
else
n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) -
unsigned('0' & r.da(rlda_ibf_seek_df)) );
end if;
ibhold := r.ibsel;
n.state := s_seek_clip;
when s_seek_clip => -- seek_clip: clip new ca ------------
n.seekcac := r.seekcan(8 downto 0);
-- new ca overflowed ? for RL02 (9) and for RL01 (9:8) must be "00"
if r.seekcan(9) = '1' or
(r.seekdt = '0' and r.seekcan(8) = '1') then
if r.da(rlda_ibf_seek_dir) = '1' then -- outward seek
if r.seekdt = '1' then -- is RL02
n.seekcac := ca_max_rl02; -- clip to RL02 max ca
else -- is RL01
n.seekcac := ca_max_rl01; -- clip to RL01 max ca
end if;
else -- inward seek
n.seekcac := "000000000"; -- clip to 0
end if;
end if;
ibhold := r.ibsel;
n.state := s_seek_wpos;
when s_seek_wpos => -- seek_wpos: write pos(ds) ----------
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
imem_we0 := '1';
imem_we1 := '1';
imem_din := MEM_DOUT;
imem_din(pos_ibf_ca) := r.seekcac;
imem_din(pos_ibf_hs) := r.da(rlda_ibf_seek_hs);
n.ireq := r.csie; -- interrupt
n.state := s_idle;
when s_init => -- init: handle init -----------------
ibhold := r.ibsel; -- hold ibus when controller busy
imem_addr := r.iaddr;
imem_din := (others=>'0');
imem_we0 := '1';
imem_we1 := '1';
if r.iaddr(imf_typ) = imem_sta(imf_typ) then -- if sta(x)
imem_din := MEM_DOUT; -- keep state
imem_din(sta_ibf_wde) := '0'; -- and clear err
imem_din(sta_ibf_che) := '0';
imem_din(sta_ibf_sto) := '0';
imem_din(sta_ibf_spe) := '0';
imem_din(sta_ibf_wge) := '0';
imem_din(sta_ibf_vce) := '0';
imem_din(sta_ibf_dse) := '0';
end if;
n.iaddr := slv(unsigned(r.iaddr) + 1);
if unsigned(r.iaddr) = unsigned(imem_sta)+3 then -- stop after sta(3)
n.state := s_idle;
end if;
when others => null;
end case;
iei_req := r.ireq; -- ??? simplify, use r.ireq directly
if EI_ACK = '1' or r.csie = '0' then -- interrupt executed or ie disabled
n.ireq := '0'; -- cancel request
end if;
N_REGS <= n;
MEM_0_WE <= imem_we0;
MEM_1_WE <= imem_we1;
MEM_ADDR <= imem_addr;
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
end syn;
| gpl-3.0 | 7b38a57910d5c3f14cb3cfb856518eea | 0.438178 | 3.704286 | false | false | false | false |
sjohann81/hf-risc | riscv/platform/spartan3e_nexys2/spartan3e_nexys2_standard_soc_ext_sram.vhd | 1 | 6,775 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
-- external SRAM / EEPROM SPI interface
spi_ssn_o: out std_logic;
spi_ssn2_o: out std_logic;
spi_clk_o: out std_logic;
spi_mosi_o: out std_logic;
spi_miso_i: in std_logic;
-- GPIO port A
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
-- GPIO port B
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, boot_enable_n, ram_enable_n, stall_sig, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal data_read_spi: std_logic_vector(31 downto 0);
signal data_mode: std_logic_vector(2 downto 0);
signal burst, wr, rd, we, stall_dly, stall_dly2, stall_spi, spi_sel, spi_cs_n_s: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (rst_i, clk_i, clock)
begin
if rst_i = '1' then
clock <= '0';
else
if clk_i'event and clk_i = '1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, rst_i)
begin
if (rst_i = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (clock, reset, stall_spi)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
stall_dly <= '0';
stall_dly2 <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
stall_dly <= stall_spi;
stall_dly2 <= stall_dly;
end if;
end process;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') else '1';
spi_sel <= '1' when address(31 downto 28) = "0011" else '0';
rd <= '1' when (spi_sel = '1' and data_we = "0000" and stall_dly2 = '0') else '0';
wr <= '1' when (spi_sel = '1' and data_we /= "0000" and stall_dly2 = '0') else '0';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_spi when spi_sel = '1' or stall_dly2 = '1' else
data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
burst <= '0';
stall_sig <= stall_spi;
-- external SPI SRAM/EEPROM, 0x30000000 (26,25 - spi select, 24 - short address mode, 23 - EEPROM write enable latch)
spi_ssn_o <= spi_cs_n_s when spi_sel = '1' and address(25) = '0' else '1';
-- external SPI SRAM/EEPROM, 0x32000000
spi_ssn2_o <= spi_cs_n_s when spi_sel = '1' and address(25) = '1' else '1';
we <= address(24) and address(23);
ext_irq <= "0000000" & periph_irq;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => data_mode,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
sram_ctrl_core: entity work.spi_sram_ctrl
port map( clk_i => clock,
rst_i => reset,
addr_i => address(23 downto 0),
data_i => data_write,
data_o => data_read_spi,
burst_i => burst,
bmode_i => data_mode(2),
hmode_i => data_mode(1),
wr_i => wr,
rd_i => rd,
saddr_i => address(24),
wren_i => we,
data_ack_o => open,
cpu_stall_o => stall_spi,
spi_cs_n_o => spi_cs_n_s,
spi_clk_o => spi_clk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i
);
-- instruction and data memory (boot RAM)
boot_enable <= not boot_enable_n;
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | 888c7edb371e7a8c31e2912f84f68e19 | 0.622878 | 2.558535 | false | false | false | false |
wfjm/w11 | rtl/bplib/cmoda7/tb/tb_cmoda7_sram.vhd | 1 | 5,910 | -- $Id: tb_cmoda7_sram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_cmoda7_sram - sim
-- Description: Test bench for cmoda7 (base+sram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_cmoda7_core
-- serport/tb/serport_master_tb
-- cmoda7_sram_aif [UUT]
-- simlib/simbididly
-- bplib/issi/is61wv5128bll
--
-- To test: generic, any cmoda7_sram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.4-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-06-04 906 1.0 Initial version (derived from tb_nexys4_cram)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.cmoda7lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_cmoda7_sram is
end tb_cmoda7_sram;
architecture sim of tb_cmoda7_sram is
signal CLKOSC : slbit := '0'; -- board clock (12 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_BTN : slv2 := (others=>'0');
signal O_LED : slv2 := (others=>'0');
signal O_RGBLED0_N : slv3 := (others=>'0');
signal TB_MEM_CE_N : slbit := '1';
signal TB_MEM_WE_N : slbit := '1';
signal TB_MEM_OE_N : slbit := '1';
signal TB_MEM_ADDR : slv19 := (others=>'Z');
signal TB_MEM_DATA : slv8 := (others=>'0');
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADDR : slv19 := (others=>'Z');
signal MM_MEM_DATA : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 83.333 ns;
constant clock_offset : Delay_length := 2000 ns;
constant pcb_delay : Delay_length := 1 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
C7CORE : entity work.tb_cmoda7_core
port map (
I_BTN => I_BTN
);
UUT : cmoda7_sram_aif
port map (
I_CLK12 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0_N => O_RGBLED0_N,
O_MEM_CE_N => TB_MEM_CE_N,
O_MEM_WE_N => TB_MEM_WE_N,
O_MEM_OE_N => TB_MEM_OE_N,
O_MEM_ADDR => TB_MEM_ADDR,
IO_MEM_DATA => TB_MEM_DATA
);
MM_MEM_CE_N <= TB_MEM_CE_N after pcb_delay;
MM_MEM_WE_N <= TB_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= TB_MEM_OE_N after pcb_delay;
MM_MEM_ADDR <= TB_MEM_ADDR after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 8)
port map (
A => TB_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.is61wv5128bll
port map (
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most cmoda7 designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 6c9c0fbb90780f877827e6f7a90fafaf | 0.540948 | 3.225983 | false | false | false | false |
nanomolina/vhdl_examples | register/regfile.vhd | 4 | 990 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity regfile is
port (ra1, ra2, wa3: in std_logic_vector(4 downto 0);
wd3: in std_logic_vector(31 downto 0);
we3, clk: in std_logic;
rd1, rd2: out std_logic_vector(31 downto 0));
end entity;
architecture arq_regfile of regfile is
type mem is array (0 to 31) of std_logic_vector(31 downto 0);
begin
process(clk)
variable my_mem: mem := (0 => x"00000000", others => "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU");
variable pos_ra1, pos_ra2, pos_wa3: integer;
begin
if clk'EVENT and clk='1' then
pos_ra1 := to_integer(unsigned(ra1));
pos_ra2 := to_integer(unsigned(ra2));
rd1 <= my_mem(pos_ra1);
rd2 <= my_mem(pos_ra2);
if we3='1' then
pos_wa3 := to_integer(unsigned(wa3));
my_mem(pos_wa3) := wd3;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | e18da0640d7f67d7f196970ad42d849d | 0.575758 | 3.3 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys2/sys_conf.vhd | 1 | 1,921 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays
-- 2012-12-20 614 1.1.4 use 85 MHz (max after rlv4 update)
-- 2010-11-27 341 1.1.3 add sys_conf_clksys_mhz (clksys in MHz)
-- 2010-11-26 340 1.1.2 default now clksys=60 MHz
-- 2010-11-22 339 1.1.1 add memctl related constants
-- 2010-11-13 338 1.1 add dcm related constants
-- 2010-05-23 294 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 10;
constant sys_conf_clkfx_multiply : positive := 17;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | 0de713bc5f99f764604bf95d8c474c0e | 0.618948 | 3.34669 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4/tb/nexys4_dummy.vhd | 1 | 2,266 | -- $Id: nexys4_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys4_dummy - syn
-- Description: nexys4 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys4
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.3 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nexys4_dummy is -- NEXYS 4 dummy (base; loopback)
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end nexys4_dummy;
architecture syn of nexys4_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
| gpl-3.0 | 682386277613a039d105f4593d271ff7 | 0.488526 | 3.443769 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys2/tb/nexys2_fusp_dummy.vhd | 1 | 3,490 | -- $Id: nexys2_fusp_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys2_fusp_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback)
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end nexys2_fusp_dummy;
architecture syn of nexys2_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
| gpl-3.0 | 3092a9868532e8f6edf0e87254403119 | 0.502292 | 3.190128 | false | false | false | false |
jasonpeng/cg3207-proj | Control.vhd | 1 | 2,295 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Control is
port(
Instr: in std_logic_vector(31 downto 0);
RegDst: out std_logic;
ALUSrc:out std_logic;
MemtoReg: out std_logic;
RegWrite:out std_logic;
MemRead:out std_logic;
MemWrite:out std_logic;
ALUOp: out std_logic_vector(2 downto 0)); -- input instruction after fetch
end Control;
architecture Behavioral of Control is
alias InstrOp : std_logic_vector(5 downto 0) is Instr(31 downto 26);
alias Instrbit20: std_logic is Instr(20);
alias Funct: std_logic_vector(5 downto 0) is Instr(5 downto 0);
begin
RegDst <= '1' when (InstrOp = "000000" ) AND (Instr /= X"00000000") -- case R format
else '0'; -- other cases, like lw, lui, ori
ALUSrc <= '1' when (InstrOp = "100011" or InstrOp = "101011"
or InstrOp = "001101" or InstrOp = "001111"
or InstrOp = "001000" or InstrOp = "001010")
-- case for lw and sw,lui,ori, addi, slti
else '0'; -- case R-format and beq
MemtoReg <= '1' when (InstrOp = "100011") -- case lw
else '0'; -- case for others
RegWrite <= '1' when ((InstrOp = "000000" or InstrOp = "100011" -- case R format or case LW
or InstrOp = "001101" or InstrOp = "001111" -- case for ori or case LUI
or InstrOp = "001010" -- case for slti
or InstrOp = "001000" -- case for addi
) AND (Instr /= X"00000000"))
else '0';-- case SW and BEQ
MemRead <= '1' when (InstrOp = "100011") -- case for lw
else '0';
MemWrite <= '1' when (InstrOp = "101011") -- case for sw
else '0';
-- case jump,jr,jarl,jal
ALUOp <= "100" when (InstrOp = "000000" and Instr/= X"00000000")
-- case for R-format(ADD,SUB,DIV, DIVU, MUL and/or MULT, MULU, MFHI, MFLO,AND,NOR,OR,XOR,SLL,SLLV,SRL,SRLV,SRA,SRAV,SLT)
else "001" when (InstrOp = "001000" or InstrOp = "100011" or InstrOp ="101011") -- case for Addi,LW,SW
else "010" when (InstrOp = "001010") -- case for slti
else "011" when (InstrOp = "001111") -- case for LUI
else "111" when (InstrOp = "001101") -- case for ORI
else "000" ; -- case for nop
end Behavioral;
| gpl-2.0 | 8bc93e658f8624611b4febc5fa92d64a | 0.576906 | 3.375 | false | false | false | false |
wfjm/w11 | rtl/bplib/arty/tb/tb_arty.vhd | 1 | 5,385 | -- $Id: tb_arty.vhd 1211 2021-08-28 11:20:34Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_arty - sim
-- Description: Test bench for arty (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_arty_core
-- serport/tb/serport_master_tb
-- arty_aif [UUT]
--
-- To test: generic, any arty_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.3.1 use sfs_gsim_core
-- 2016-09-18 809 1.3 add gsr_pulse (provisional....)
-- 2016-09-02 805 1.2.1 tbcore_rlink without CLK_STOP now
-- 2016-03-20 748 1.2 BUGFIX: add PORTSEL_XON logic
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-02-20 734 1.0.2 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.0.1 direct instantiation of tbcore_rlink
-- 2016-01-31 726 1.0 Initial version (derived from tb_basys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.artylib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_arty is
end tb_arty;
architecture sim of tb_arty is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv4 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv4 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_RGBLED2 : slv3 := (others=>'0');
signal O_RGBLED3 : slv3 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
ARTYCORE : entity work.tb_arty_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : arty_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_RGBLED2 => O_RGBLED2,
O_RGBLED3 => O_RGBLED3,
A_VPWRN => (others=>'0'),
A_VPWRP => (others=>'0')
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most arty designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 6bbc965ebe47eebbc21d34920f80263b | 0.543733 | 3.361423 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd | 1 | 18,787 | -- $Id: sys_tst_mig_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_mig_n4d - syn
-- Description: test of nexyx4d ddr and its mig controller
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- cdclib/cdc_pulse
-- bplib/bpgen/bp_rs232_4line_iob
-- rlink/rlink_sp2c
-- tst_mig
-- bplib/nexyx4d/migui_nexyx4d (generated core)
-- bplib/sysmon/sysmonx_rbus_base
-- rbus/rbd_usracc
-- rbus/rb_sres_or_3
--
-- Test bench: tb/tb_tst_mig_n4d
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1l 4216 3821 412 1 1726
-- 2019-08-10 1201 2019.1 xc7a100t-1l 4217 4173 440 1 1709 +clkmon
-- 2019-02-02 1108 2018.3 xc7a100t-1l 4106 4145 440 1 1689
-- 2019-02-02 1108 2017.2 xc7a100t-1l 4097 4310 440 1 1767
-- 2019-01-02 1101 2017.2 xc7a100t-1l 4097 4310 457 1 1767
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.1.1 use bufg_unisim
-- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK; add clock monitor
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Nexys 4 Switches, Buttons, LEDs
--
-- SWI -- unused --
--
-- BTN
-- (4) ce -- unused --
-- (3) le issue MIG_SYS_RST
-- (2) do light LED(12:15)
-- (1) ri light LED(8:11)
-- (0) up light LED(4:7)
--
-- LEDs
-- (15) I_BTN(2) or R_FLG_UI_CLK (MIG UI clock monitor 75 MHz)
-- (14) I_BTN(2) or R_FLG_CLKREF (CLKREF clock monitor 200 MHz)
-- (13) I_BTN(2) or R_FLG_CLKSER (CLKSER clock monitor 120 MHz)
-- (12) I_BTN(2) or R_FLG_XX_CLK (sysclk clock monitor 80 MHz)
-- (11) I_BTN(1) or not APP_WDF_RDY
-- (10) I_BTN(1) or not APP_RDY
-- (8:9) I_BTN(1)
-- (7) I_BTN(0) or not MIG_INIT_CALIB_COMPLETE
-- (6) I_BTN(0) or MIG_UI_CLK_SYNC_RST
-- (5) I_BTN(0)
-- (4) I_BTN(0) or not LOCKED
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib_nexys4d.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_mig_n4d is -- top level
-- implements nexys4d_mig_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end sys_tst_mig_n4d;
architecture syn of sys_tst_mig_n4d is
signal CLK100_BUF : slbit := '0';
signal XX_CLK : slbit := '0'; -- kept to keep clock setup similar
signal XX_CE_USEC : slbit := '0'; -- to w11a or other 'normal' systems
signal XX_CE_MSEC : slbit := '0'; --
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_CMD : slv3 := (others=>'0');
signal APP_EN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_WREN : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_WDF_RDY : slbit := '0';
signal APP_SR_REQ : slbit := '0';
signal APP_REF_REQ : slbit := '0';
signal APP_ZQ_REQ : slbit := '0';
signal APP_SR_ACTIVE : slbit := '0';
signal APP_REF_ACK : slbit := '0';
signal APP_ZQ_ACK : slbit := '0';
signal MIG_UI_CLK : slbit := '0';
signal MIG_UI_CLK_SYNC_RST : slbit := '0';
signal MIG_INIT_CALIB_COMPLETE : slbit := '0';
signal MIG_SYS_RST : slbit := '0';
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal R_CNT_UI_CLK : slv(25 downto 0) := (others=>'0');
signal R_CNT_CLKREF : slv(26 downto 0) := (others=>'0');
signal R_CNT_CLKSER : slv(25 downto 0) := (others=>'0');
signal R_CNT_XX_CLK : slv(25 downto 0) := (others=>'0');
signal R_FLG_UI_CLK : slbit := '0';
signal R_FLG_CLKREF : slbit := '0';
signal R_FLG_CLKSER : slbit := '0';
signal R_FLG_XX_CLK : slbit := '0';
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0105"; -- tst_mig
constant sysid_board : slv8 := x"08"; -- nexys4d
constant sysid_vers : slv8 := x"00";
begin
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 12, -- vco 1200 MHz
CLK2_OUTDIV => 12, -- mig sys 100.0 MHz (unused)
CLK3_OUTDIV => 6, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => XX_CLK,
CE0_USEC => XX_CE_USEC,
CE0_MSEC => XX_CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => open,
CLK3 => CLKREF,
LOCKED => LOCKED
);
-- Note: CLK0 is generated as in 'normal' systems to keep PPL/MMCM setup
-- as similar as possible. The CE_USEC and CE_MSEC pulses are forwarded
-- from the 80 MHz CLK0 domain to the 75.000 MHz MIG UI_CLK domain
CDC_CEUSEC : cdc_pulse -- provide CLK side CE_USEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_USEC,
BUSY => open,
POUT => CE_USEC
);
CDC_CEMSEC : cdc_pulse -- provide CLK side CE_MSEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_MSEC,
BUSY => open,
POUT => CE_MSEC
);
CDC_CLKMIG_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK100_BUF,
DI => LOCKED,
DO => LOCKED_CLKMIG
);
IOB_RS232 : bp_rs232_4line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 8, -- 256 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => '0', -- FIXME: no RESET
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '0',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_mig
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
MAWIDTH => mig_mawidth,
MWIDTH => mig_mwidth)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
MIG_UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
MIG_INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
MIG_DEVICE_TEMP_I => XADC_TEMP
);
MIG_CTL: migui_nexys4d -- MIG iface -----------------
port map (
DDR2_DQ => DDR2_DQ,
DDR2_DQS_P => DDR2_DQS_P,
DDR2_DQS_N => DDR2_DQS_N,
DDR2_ADDR => DDR2_ADDR,
DDR2_BA => DDR2_BA,
DDR2_RAS_N => DDR2_RAS_N,
DDR2_CAS_N => DDR2_CAS_N,
DDR2_WE_N => DDR2_WE_N,
DDR2_CK_P => DDR2_CK_P,
DDR2_CK_N => DDR2_CK_N,
DDR2_CKE => DDR2_CKE,
DDR2_CS_N => DDR2_CS_N,
DDR2_DM => DDR2_DM,
DDR2_ODT => DDR2_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
UI_CLK => CLK,
UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
SYS_CLK_I => CLK100_BUF,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => XADC_TEMP,
SYS_RST => MIG_SYS_RST
);
MIG_SYS_RST <= (not LOCKED_CLKMIG) or I_BTN(3); -- provisional !
SMRB: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
proc_mon_ui_clk: process (CLK, I_BTN(3))
begin
if I_BTN(3) = '1' then
R_FLG_UI_CLK <= '1';
R_CNT_UI_CLK <= (others=>'0');
end if;
if rising_edge(CLK) then
if unsigned(R_CNT_UI_CLK) = 37500000-1 then
R_FLG_UI_CLK <= not R_FLG_UI_CLK;
R_CNT_UI_CLK <= (others=>'0');
else
R_CNT_UI_CLK <= slv(unsigned(R_CNT_UI_CLK) + 1);
end if;
end if;
end process proc_mon_ui_clk;
proc_mon_clkref: process (CLKREF, I_BTN(3))
begin
if I_BTN(3) = '1' then
R_FLG_CLKREF <= '1';
R_CNT_CLKREF <= (others=>'0');
end if;
if rising_edge(CLKREF) then
if unsigned(R_CNT_CLKREF) = 100000000-1 then
R_FLG_CLKREF <= not R_FLG_CLKREF;
R_CNT_CLKREF <= (others=>'0');
else
R_CNT_CLKREF <= slv(unsigned(R_CNT_CLKREF) + 1);
end if;
end if;
end process proc_mon_clkref;
proc_mon_clkser: process (CLKS, I_BTN(3))
begin
if I_BTN(3) = '1' then
R_FLG_CLKSER <= '1';
R_CNT_CLKSER <= (others=>'0');
end if;
if rising_edge(CLKS) then
if unsigned(R_CNT_CLKSER) = 60000000-1 then
R_FLG_CLKSER <= not R_FLG_CLKSER;
R_CNT_CLKSER <= (others=>'0');
else
R_CNT_CLKSER <= slv(unsigned(R_CNT_CLKSER) + 1);
end if;
end if;
end process proc_mon_clkser;
proc_mon_xx_clk: process (XX_CLK, I_BTN(3))
begin
if I_BTN(3) = '1' then
R_FLG_XX_CLK <= '1';
R_CNT_XX_CLK <= (others=>'0');
end if;
if rising_edge(XX_CLK) then
if unsigned(R_CNT_XX_CLK) = 40000000-1 then
R_FLG_XX_CLK <= not R_FLG_XX_CLK;
R_CNT_XX_CLK <= (others=>'0');
else
R_CNT_XX_CLK <= slv(unsigned(R_CNT_XX_CLK) + 1);
end if;
end if;
end process proc_mon_xx_clk;
RB_LAM(0) <= RB_LAM_TST;
-- LED group(0:3): rlink traffic
O_LED(0) <= SER_MONI.rxact;
O_LED(1) <= not SER_MONI.rxok;
O_LED(2) <= SER_MONI.txact;
O_LED(3) <= not SER_MONI.txok;
-- LED group(4:7) serious error conditions
O_LED(4) <= I_BTN(0) or not LOCKED;
O_LED(5) <= I_BTN(0);
O_LED(6) <= I_BTN(0) or MIG_UI_CLK_SYNC_RST;
O_LED(7) <= I_BTN(0) or not MIG_INIT_CALIB_COMPLETE;
-- LED group(8:11) for activity
O_LED(8) <= I_BTN(1);
O_LED(9) <= I_BTN(1);
O_LED(10) <= I_BTN(1) or not APP_RDY;
O_LED(11) <= I_BTN(1) or not APP_WDF_RDY;
-- LED group(12:15) for clock monitoring
O_LED(12) <= I_BTN(2) or R_FLG_XX_CLK;
O_LED(13) <= I_BTN(2) or R_FLG_CLKSER;
O_LED(14) <= I_BTN(2) or R_FLG_CLKREF;
O_LED(15) <= I_BTN(2) or R_FLG_UI_CLK;
-- RGB LEDs unused
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>'0');
-- 7 segment disp unused
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
| gpl-3.0 | 037edefb10df45005f88de77612b7739 | 0.498057 | 3.020904 | false | false | false | false |
jasonpeng/cg3207-proj | ID_EX_BUFF.vhd | 1 | 3,970 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:19:27 10/31/2013
-- Design Name:
-- Module Name: ID_EX_BUFF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ID_EX_BUFF is
Port (
CLK : in STD_LOGIC; -- clock signal for synchronization
RESET : in STD_LOGIC;
-- IN --
IN_ID_ALUOp : in STD_LOGIC_VECTOR(2 downto 0);
IN_ID_SignExtended : in STD_LOGIC_VECTOR(31 downto 0); -- extended signed immediate value; also used for ALU opcode
IN_ID_ALUSrc : in STD_LOGIC; -- selects second operand for ALU
IN_ID_Data1 : in STD_LOGIC_VECTOR(31 downto 0); -- data1 from register
IN_ID_Data2 : in STD_LOGIC_VECTOR(31 downto 0); -- data2 from register
-- register writeback
IN_ID_RegDst : in STD_LOGIC; --selects writeback address
IN_ID_Instr_25_21 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_Instr_20_16 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_Instr_15_11 : in STD_LOGIC_VECTOR(4 downto 0);
-- states received from the previous stage
IN_ID_MemWrite : in STD_LOGIC;
IN_ID_MemToReg : in STD_LOGIC;
IN_ID_MemRead : in STD_LOGIC;
IN_ID_RegWrite : in STD_LOGIC;
-- OUT --
OUT_EX_ALUOp : out STD_LOGIC_VECTOR(2 downto 0);
OUT_EX_SignExtended : out STD_LOGIC_VECTOR(31 downto 0); -- extended signed immediate value; also used for ALU opcode
OUT_EX_ALUSrc : out STD_LOGIC; -- selects second operand for ALU
OUT_EX_Data1 : out STD_LOGIC_VECTOR(31 downto 0); -- data1 from register
OUT_EX_Data2 : out STD_LOGIC_VECTOR(31 downto 0); -- data2 from register
-- register writeback
OUT_EX_RegDst : out STD_LOGIC; --selects writeback address
OUT_EX_Instr_25_21 : out STD_LOGIC_VECTOR(4 downto 0);
OUT_EX_Instr_20_16 : out STD_LOGIC_VECTOR(4 downto 0);
OUT_EX_Instr_15_11 : out STD_LOGIC_VECTOR(4 downto 0);
-- states received from the previous stage
OUT_EX_MemWrite : out STD_LOGIC;
OUT_EX_MemToReg : out STD_LOGIC;
OUT_EX_MemRead : out STD_LOGIC;
OUT_EX_RegWrite : out STD_LOGIC
);
end ID_EX_BUFF;
architecture Behavioral of ID_EX_BUFF is
begin
process(CLK, RESET)
begin
if (RESET = '1') then
OUT_EX_ALUOp <= "000";
OUT_EX_SignExtended <= (others => '0');
OUT_EX_ALUSrc <= '0';
OUT_EX_Data1 <= (others => '0');
OUT_EX_Data2 <= (others => '0');
OUT_EX_RegDst <= '0';
OUT_EX_Instr_25_21 <= (others => '0');
OUT_EX_Instr_20_16 <= (others => '0');
OUT_EX_Instr_15_11 <= (others => '0');
OUT_EX_MemWrite <= '0';
OUT_EX_MemToReg <= '0';
OUT_EX_MemRead <= '0';
OUT_EX_RegWrite <= '0';
elsif(Clk'event and Clk='1') then
OUT_EX_ALUOp <= IN_ID_ALUop;
OUT_EX_SignExtended <= IN_ID_SignExtended;
OUT_EX_ALUSrc <= IN_ID_ALUSrc;
OUT_EX_Data1 <= IN_ID_Data1;
OUT_EX_Data2 <= IN_ID_Data2;
OUT_EX_RegDst <= IN_ID_RegDst;
OUT_EX_Instr_25_21 <= IN_ID_Instr_25_21;
OUT_EX_Instr_20_16 <= IN_ID_Instr_20_16;
OUT_EX_Instr_15_11 <= IN_ID_Instr_15_11;
OUT_EX_MemWrite <= IN_ID_MemWrite;
OUT_EX_MemToReg <= IN_ID_MemToReg;
OUT_EX_MemRead <= IN_ID_MemRead;
OUT_EX_RegWrite <= IN_ID_RegWrite;
end if;
end process;
end Behavioral;
| gpl-2.0 | 2ac40e155d48beec9c7a0928080da45d | 0.588665 | 3.108849 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd | 1 | 4,064 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_s3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.3.6 drop iist
-- 2018-09-22 1050 1.3.5 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.3.4 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.3.3 use sys_conf_dmcmon_awidth=8 (proper value)
-- 2017-01-29 847 1.3.2 add sys_conf_ibd_deuna
-- 2016-05-28 770 1.3.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions
-- 2014-12-22 619 1.1.2 add _rbmon_awidth
-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce
-- 2008-02-23 118 1.1 add memory config
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : natural := 8#037777#; -- 1 MByte
--constant sys_conf_mem_losize : natural := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
-- constant sys_conf_mem_losize : natural := 8#001777#; -- 64 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 4; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 4; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 5; -- DZ11
constant sys_conf_ibd_pc11 : integer := 4; -- PC11
constant sys_conf_ibd_lp11 : integer := 5; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := false; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
end package sys_conf;
| gpl-3.0 | ebf7f5cbadf8b33c76869ced000b247f | 0.582677 | 3.2512 | false | true | false | false |
hubertokf/VHDL-MIPS-Pipeline | memInst2.vhd | 1 | 1,477 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memInst2 is
generic (
wlength: integer := 32;
words : integer := 10
);
Port(
data: IN std_logic_vector(wlength-1 downto 0);
address: IN std_logic_vector(words-1 downto 0);
clock, wren: IN std_logic;
q: OUT std_logic_vector(wlength-1 downto 0)
);
end memInst2;
ARCHITECTURE rlt OF memInst2 is
type memory_type is array (2**words-1 downto 0) of std_logic_vector(wlength -1 downto 0);
signal memory: memory_type;
begin
gen_init_mem: for i in 11 to 1023 generate
memory(i) <= "00000000000000000000000000000000";
end generate gen_init_mem;
memory(0) <= "00100000000000100000000000000011";
memory(1) <= "00100000000000110000000000000100";
memory(2) <= "00100000000001000000000000000101";
memory(3) <= "00100000011000110000000000000100";
memory(4) <= "00100000000001100000000000000111";
memory(5) <= "10101100000000100000000000000100";
memory(6) <= "10001100000001110000000000000100";
memory(7) <= "00000000000001111000100000100000";
memory(8) <= "00000000000001111001000000100000";
memory(9) <= "00000000000001111001100000100000";
memory(10) <= "00010000000000000000000000000010";
process (clock, memory, address, wren)
begin
-- if clock'event and clock ='1' then
-- if wren = '1' then
-- memory(to_integer(unsigned(address))) <= data;
-- end if;
-- end if;
q <= memory(to_integer(unsigned(address))) after 1ns;
end process;
end rlt; | mit | a40b08b25ce00023aaa7d9296e553d86 | 0.714286 | 3.296875 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32e/reg_bank.vhd | 1 | 1,127 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg_bank is
port ( clock: in std_logic;
read_reg1: in std_logic_vector(3 downto 0);
read_reg2: in std_logic_vector(3 downto 0);
write_reg: in std_logic_vector(3 downto 0);
wreg: in std_logic;
write_data: in std_logic_vector(31 downto 0);
read_data1: out std_logic_vector(31 downto 0);
read_data2: out std_logic_vector(31 downto 0)
);
end reg_bank;
architecture arch_reg_bank of reg_bank is
type bank is array(0 to 15) of std_logic_vector(31 downto 0);
signal registers: bank := (others => (others => '0'));
begin
process(clock, write_reg, wreg, write_data, read_reg1, read_reg2, registers)
begin
if clock'event and clock = '1' then
if write_reg /= "00000" and wreg = '1' then
registers(conv_integer(write_reg)) <= write_data;
end if;
end if;
end process;
read_data1 <= registers(conv_integer(read_reg1)) when read_reg1 /= "00000" else (others => '0');
read_data2 <= registers(conv_integer(read_reg2)) when read_reg2 /= "00000" else (others => '0');
end arch_reg_bank;
| gpl-2.0 | 3ad1cc4361079c7bffbf36fc99759c2c | 0.664596 | 2.762255 | false | false | false | false |
wfjm/w11 | rtl/bplib/arty/tb/tb_arty_dram.vhd | 1 | 5,635 | -- $Id: tb_arty_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_arty_dram - sim
-- Description: Test bench for arty (base+dram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_arty_core
-- serport/tb/serport_master_tb
-- arty_dram_aif [UUT]
--
-- To test: generic, any arty_dram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.1.1 use sfs_gsim_core
-- 2018-10-28 1063 1.0 Initial version (derived from tb_arty)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.artylib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_arty_dram is
end tb_arty_dram;
architecture sim of tb_arty_dram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv4 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv4 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_RGBLED2 : slv3 := (others=>'0');
signal O_RGBLED3 : slv3 := (others=>'0');
signal IO_DDR3_DQ : slv16 := (others=>'Z');
signal IO_DDR3_DQS_P : slv2 := (others=>'Z');
signal IO_DDR3_DQS_N : slv2 := (others=>'Z');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
GINIT : entity work.gsr_pulse;
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
ARTYCORE : entity work.tb_arty_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : arty_dram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_RGBLED2 => O_RGBLED2,
O_RGBLED3 => O_RGBLED3,
A_VPWRN => (others=>'0'),
A_VPWRP => (others=>'0'),
DDR3_DQ => IO_DDR3_DQ,
DDR3_DQS_P => IO_DDR3_DQS_P,
DDR3_DQS_N => IO_DDR3_DQS_N,
DDR3_ADDR => open,
DDR3_BA => open,
DDR3_RAS_N => open,
DDR3_CAS_N => open,
DDR3_WE_N => open,
DDR3_RESET_N => open,
DDR3_CK_P => open,
DDR3_CK_N => open,
DDR3_CKE => open,
DDR3_CS_N => open,
DDR3_DM => open,
DDR3_ODT => open
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most arty designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | d9c3f970ef97dd6109a491ea75a136ea | 0.527418 | 3.33432 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_pc11_buf.vhd | 1 | 19,671 | -- $Id: ibdr_pc11_buf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_pc11_buf - syn
-- Description: ibus dev(rem): PC11
--
-- Dependencies: fifo_simple_dram
-- ib_rlim_slv
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-05-31 1156 1.0.1 size->fuse rename; re-organize rlim handling
-- 2019-04-24 1137 1.0 Initial version
-- 2019-04-07 1129 0.1 First draft (derived from ibdr_pc11)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_pc11_buf is -- ibus dev(rem): PC11
-- fixed address: 177550
generic (
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end ibdr_pc11_buf;
architecture syn of ibdr_pc11_buf is
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
constant rcsr_ibf_rerr : integer := 15;
subtype rcsr_ibf_rlim is integer range 14 downto 12;
constant rcsr_ibf_rbusy : integer := 11;
subtype rcsr_ibf_type is integer range 10 downto 8;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_rir : integer := 5;
constant rcsr_ibf_rlb : integer := 4;
constant rcsr_ibf_ique : integer := 3;
constant rcsr_ibf_iack : integer := 2;
constant rcsr_ibf_fclr : integer := 1;
constant rcsr_ibf_renb : integer := 0;
constant rbuf_ibf_rbusy : integer := 15;
subtype rbuf_ibf_rfuse is integer range AWIDTH-1+8 downto 8;
subtype rbuf_ibf_pfuse is integer range AWIDTH-1 downto 0;
subtype rbuf_ibf_data is integer range 7 downto 0;
constant pcsr_ibf_perr : integer := 15;
subtype pcsr_ibf_rlim is integer range 14 downto 12;
constant pcsr_ibf_prdy : integer := 7;
constant pcsr_ibf_pie : integer := 6;
constant pcsr_ibf_pir : integer := 5;
constant pcsr_ibf_rlb : integer := 4;
constant pbuf_ibf_pval : integer := 15;
subtype pbuf_ibf_fuse is integer range AWIDTH-1+8 downto 8;
subtype pbuf_ibf_data is integer range 7 downto 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rerr : slbit; -- rcsr: reader error
rrlim : slv3; -- rcsr: reader rlim
rbusy : slbit; -- rcsr: reader busy
rdone : slbit; -- rcsr: reader done
rie : slbit; -- rcsr: reader interrupt enable
rintreq : slbit; -- ptr interrupt request
rique : slbit; -- ptr interrupt queued (req set)
riack : slbit; -- ptr interrupt acknowledged
perr : slbit; -- pcsr: punch error
prlim : slv3; -- pcsr: punch rlim
prdy : slbit; -- pcsr: punch ready
pie : slbit; -- pcsr: punch interrupt enable
pintreq : slbit; -- ptp interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- rerr (init=1!)
"000", -- rrlim
'0','0','0', -- rbusy,rdone,rie
'0','0','0', -- rintreq,rique,riack
'1', -- perr (init=1!)
"000", -- prlim
'1', -- prdy (init=1!)
'0', -- pie
'0' -- pintreq
);
constant c_fuse1 : slv(AWIDTH-1 downto 0) := slv(to_unsigned(1,AWIDTH));
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal RBUF_CE : slbit := '0';
signal RBUF_WE : slbit := '0';
signal RBUF_DO : slv8 := (others=>'0');
signal RBUF_RESET : slbit := '0';
signal RBUF_EMPTY : slbit := '0';
signal RBUF_FULL : slbit := '0';
signal RBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal PBUF_CE : slbit := '0';
signal PBUF_WE : slbit := '0';
signal PBUF_DO : slv8 := (others=>'0');
signal PBUF_RESET : slbit := '0';
signal PBUF_EMPTY : slbit := '0';
signal PBUF_FULL : slbit := '0';
signal PBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RRLIM_START : slbit := '0';
signal RRLIM_BUSY : slbit := '0';
signal PRLIM_START : slbit := '0';
signal PRLIM_BUSY : slbit := '0';
begin
assert AWIDTH>=4 and AWIDTH<=7
report "assert(AWIDTH>=4 and AWIDTH<=7): unsupported AWIDTH"
severity failure;
RBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RBUF_RESET,
CE => RBUF_CE,
WE => RBUF_WE,
DI => IB_MREQ.din(rbuf_ibf_data),
DO => RBUF_DO,
EMPTY => RBUF_EMPTY,
FULL => RBUF_FULL,
SIZE => RBUF_FUSE
);
PBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => PBUF_RESET,
CE => PBUF_CE,
WE => PBUF_WE,
DI => IB_MREQ.din(pbuf_ibf_data),
DO => PBUF_DO,
EMPTY => PBUF_EMPTY,
FULL => PBUF_FULL,
SIZE => PBUF_FUSE
);
RRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rrlim,
START => RRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RRLIM_BUSY
);
PRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.prlim,
START => PRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => PRLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rerr <= N_REGS.rerr; -- keep RERR flag
R_REGS.rrlim <= N_REGS.rrlim; -- keep RRLIM field
R_REGS.perr <= N_REGS.perr; -- keep PERR flag
R_REGS.prlim <= N_REGS.prlim; -- keep PRLIM field
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP, RESET,
RBUF_DO, RBUF_EMPTY, RBUF_FULL, RBUF_FUSE, RRLIM_BUSY,
PBUF_DO, PBUF_EMPTY, PBUF_FULL, PBUF_FUSE, PRLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable iback : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable irbufce : slbit := '0';
variable irbufwe : slbit := '0';
variable irbufrst : slbit := '0';
variable irrlimsta : slbit := '0';
variable ipbufce : slbit := '0';
variable ipbufwe : slbit := '0';
variable iprlimsta : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
iback := r.ibsel and ibreq;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
irbufce := '0';
irbufwe := '0';
irbufrst := RESET or r.rerr;
irrlimsta := '0';
ipbufce := '0';
ipbufwe := '0';
iprlimsta := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then -- ibus selected ---------------------
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- reader control status -----
idout(rcsr_ibf_rerr) := r.rerr;
idout(rcsr_ibf_rbusy) := r.rbusy;
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rie = '0' and -- IE 0->1 transition
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
(r.rerr='1' or r.rdone='1') then -- but err or done set
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupts
end if;
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
if r.rerr = '0' then -- if not in error state
n.rbusy := '1'; -- set busy
n.rdone := '0'; -- clear done
n.rintreq := '0'; -- cancel interrupt
n.rique := '0'; -- and que flag
n.riack := '0'; -- and ack flag
else -- if in error state
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rlim) := r.rrlim;
idout(rcsr_ibf_type) := slv(to_unsigned(AWIDTH,3));
idout(rcsr_ibf_rir) := r.rintreq;
idout(rcsr_ibf_rlb) := RRLIM_BUSY;
idout(rcsr_ibf_ique) := r.rique;
idout(rcsr_ibf_iack) := r.riack;
if ibw1 = '1' then
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
n.rrlim := IB_MREQ.din(rcsr_ibf_rlim); -- set RLIM field
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
and r.rerr='0' and r.rie = '1' then -- and interrupts on
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
if ibw0 = '1' then
if IB_MREQ.din(rcsr_ibf_fclr) = '1' then -- 1 written to FCLR
irbufrst := '1'; -- then reset fifo
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- reader data buffer --------
if IB_MREQ.racc = '0' then -- cpu ---------------------
-- the PC11 clears the reader data buffer when read (unusual!!)
-- this is emulated by returning fifo data only when DONE=1
if r.rdone = '1' then
idout(rbuf_ibf_data) := RBUF_DO;
end if;
if ibreq = '1' then -- !! PC11 is unusual !!
n.rdone := '0'; -- *any* read or write will clear done
n.rintreq := '0'; -- also interrupt is canceled
if r.rdone = '1' then -- data available
irbufce := '1'; -- read next value from fifo
irbufwe := '0';
if RBUF_FUSE = c_fuse1 then -- last value (fuse=1)
ilam := '1'; -- rri lam
end if;
end if;
end if;
else -- rri ---------------------
idout(rbuf_ibf_rbusy) := r.rbusy;
idout(rbuf_ibf_rfuse) := RBUF_FUSE;
idout(rbuf_ibf_pfuse) := PBUF_FUSE;
if ibw0 = '1' then
if RBUF_FULL = '0' then -- fifo not full
irbufce := '1'; -- write to fifo
irbufwe := '1';
else -- write to full fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when ibaddr_pcsr => -- PCSR -- punch control status ------
idout(pcsr_ibf_perr) := r.perr;
idout(pcsr_ibf_prdy) := r.prdy;
idout(pcsr_ibf_pie) := r.pie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.pie := IB_MREQ.din(pcsr_ibf_pie);
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
if r.pie='0' and -- IE 0->1 transition
(r.perr='1' or r.prdy='1') then -- but err or done set
n.pintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.pintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
idout(pcsr_ibf_rlim) := r.prlim;
idout(pcsr_ibf_pir) := r.pintreq;
idout(pcsr_ibf_rlb) := PRLIM_BUSY;
if ibw1 = '1' then
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
n.prlim := IB_MREQ.din(pcsr_ibf_rlim); -- set RLIM field
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
and r.perr='0' then
n.prdy := '1'; -- set ready
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.perr = '0' then -- if not in error state
if r.prdy = '1' then -- ignore buf write when rdy=0
n.prdy := '0'; -- clear ready
n.pintreq := '0'; -- cancel interrupt
if PBUF_FULL = '0' then -- fifo not full
ipbufce := '1'; -- write to fifo
ipbufwe := '1';
if PBUF_EMPTY = '1' then -- first write to empty fifo
ilam := '1'; -- request attention
end if;
end if;
end if;
else -- if in error state
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri ---------------------
idout(pbuf_ibf_pval) := not PBUF_EMPTY;
idout(pbuf_ibf_fuse) := PBUF_FUSE;
idout(pbuf_ibf_data) := PBUF_DO;
if ibrd = '1' then
if PBUF_EMPTY = '0' then -- fifo not empty
ipbufce := '1'; -- read from fifo
ipbufwe := '0';
else -- read from empty fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when others => null;
end case;
else -- ibus not selected -----------------
-- handle pr done, timer and interrupt
if RBUF_EMPTY='0' and RRLIM_BUSY='0' then -- not empty and not busy ?
if r.rbusy = '1' then -- reader enabled ?
n.rbusy := '0'; -- clear busy
n.rdone := '1'; -- set done
irrlimsta := '1'; -- start timer
if r.rdone='0' and -- done going 0->1
r.rerr='0' and r.rie='1' then -- and err=0 and ie=1
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
end if;
-- handle pp ready, timer and interrupt
if PBUF_FULL='0' and PRLIM_BUSY='0' then -- not full and not busy ?
if r.prdy = '0' then -- ready not set ?
n.prdy := '1'; -- set ready
iprlimsta := '1'; -- start timer
if r.perr='0' and r.pie='1' then -- err=0 and irupt enabled
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if; -- else r.ibsel='1'
-- other state changes
if EI_ACK_PTR = '1' then
n.rintreq := '0';
n.riack := '1';
end if;
if EI_ACK_PTP = '1' then
n.pintreq := '0';
end if;
N_REGS <= n;
RBUF_RESET <= irbufrst;
RBUF_CE <= irbufce;
RBUF_WE <= irbufwe;
RRLIM_START <= irrlimsta;
PBUF_RESET <= RESET or r.perr;
PBUF_CE <= ipbufce;
PBUF_WE <= ipbufwe;
PRLIM_START <= iprlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_PTR <= r.rintreq;
EI_REQ_PTP <= r.pintreq;
end process proc_next;
end syn;
| gpl-3.0 | ba24959961db5f42433b04f77b8fefff | 0.437293 | 3.994112 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/arty/tb/sys_conf_sim.vhd | 1 | 4,314 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_arty (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.0.1 down-rate to 75 MHz, viv 2018.3 fails with 80 MHz
-- 2018-11-17 1071 1.0 Initial version (derived from _br_arty version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 9; -- vco 900 MHz
constant sys_conf_clksys_outdivide : positive := 12; -- sys 75 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable, 8 to use
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 7; -- 32kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 121af4ae464c3a9d6a8ab1eb3c662c05 | 0.585999 | 3.687179 | false | true | false | false |
marcoep/LogicAnalyzerNano | IP/StorageRAM.vhd | 1 | 6,623 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: StorageRAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.2 Build 209 09/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY StorageRAM IS
PORT
(
aclr : IN STD_LOGIC := '0';
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END StorageRAM;
ARCHITECTURE SYN OF storageram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0);
BEGIN
q <= sub_wire0(2 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RAM1",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "DONT_CARE",
widthad_a => 13,
width_a => 3,
width_byteena_a => 1
)
PORT MAP (
aclr0 => aclr,
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "1"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "RAM1"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "3"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RAM1"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL "data[2..0]"
-- Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 3 0 data 0 0 3 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL StorageRAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL StorageRAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL StorageRAM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL StorageRAM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL StorageRAM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | 5fefcce4cd9562197c5bbf5605c2ab08 | 0.678544 | 3.661139 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_lp11.vhd | 1 | 7,931 | -- $Id: ibdr_lp11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_lp11 - syn
-- Description: ibus dev(rem): LP11
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 12 35 0 24 s 5.6
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-24 1138 1.3.3 add csr.ir (intreq monitor)
-- 2019-03-10 1121 1.3.2 ignore buf write if csr.err=1 for lp11_buf compat
-- 2019-03-03 1118 1.3.1 VAL in bit 15 and 8 for lp11_buf compat
-- 2013-05-04 515 1.3 BUGFIX: r.err was cleared in racc read !
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1
-- 2009-05-30 220 1.0 Initial version
------------------------------------------------------------------------------
--
-- Notes:
-- - the ERR bit is just a status flag
-- - no hardware interlock (DONE forced 0 when ERR=1), like in simh
-- - also no interrupt when ERR goes 1, like in simh
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_lp11 is -- ibus dev(rem): LP11
-- fixed address: 177514
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_lp11;
architecture syn of ibdr_lp11 is
constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16));
constant ibaddr_csr : slv1 := "0"; -- csr address offset
constant ibaddr_buf : slv1 := "1"; -- buf address offset
constant csr_ibf_err : integer := 15;
constant csr_ibf_done : integer := 7;
constant csr_ibf_ie : integer := 6;
constant csr_ibf_ir : integer := 5;
constant buf_ibf_val : integer := 15;
constant buf_ibf_val8: integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
err : slbit; -- csr: error flag
done : slbit; -- csr: done flag
ie : slbit; -- csr: interrupt enable
buf : slv7; -- buf:
intreq : slbit; -- interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- err !! is set !!
'1', -- done !! is set !!
'0', -- ie
(others=>'0'), -- buf
'0' -- intreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.err <= N_REGS.err; -- don't reset ERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(1 downto 1) is
when ibaddr_csr => -- CSR -- control status -------------
idout(csr_ibf_err) := r.err;
idout(csr_ibf_done) := r.done;
idout(csr_ibf_ie) := r.ie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.ie := IB_MREQ.din(csr_ibf_ie);
if IB_MREQ.din(csr_ibf_ie) = '1' then
if r.done='1' and r.ie='0' then -- ie set while done=1
n.intreq := '1'; -- request interrupt
end if;
else
n.intreq := '0';
end if;
end if;
else -- rri ---------------------
idout(csr_ibf_ir) := r.intreq;
if ibw1 = '1' then
n.err := IB_MREQ.din(csr_ibf_err);
if IB_MREQ.din(csr_ibf_err) = '1' then
n.done := '1';
n.intreq := '0'; -- clear irupt (like simh!)
end if;
end if;
end if;
when ibaddr_buf => -- BUF -- data buffer ----------------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.done = '1' then -- ignore buf write when done=0
n.buf := IB_MREQ.din(n.buf'range);
if r.err = '0' then -- if online (handle via rbus)
ilam := '1'; -- request attention
n.done := '0'; -- clear done
n.intreq := '0'; -- clear interrupt
else -- if offline (discard locally)
n.done := '1'; -- set done
if r.ie = '1' then -- if interrupts enabled
n.intreq := '1'; -- request interrupt
end if;
end if; -- r.err = '0'
end if; -- r.done = '1'
end if; -- ibw0 = '1'
else -- rri ---------------------
idout(r.buf'range) := r.buf;
idout(buf_ibf_val) := not r.done;
idout(buf_ibf_val8) := not r.done;
if ibrd = '1' then
n.done := '1';
if r.ie = '1' then
n.intreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ <= r.intreq;
end process proc_next;
end syn;
| gpl-3.0 | 08e5cd5439f6c695a3f8a84fa8c8c577 | 0.447358 | 3.668363 | false | false | false | false |
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