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wfjm/w11 | rtl/bplib/arty/tb/sys_conf_sim.vhd | 1 | 1,705 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_arty_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 55166cf66ca04d3ca5a946dbd4d06905 | 0.617595 | 3.643162 | false | false | false | false |
wfjm/w11 | rtl/ibus/ib_intmap.vhd | 1 | 6,072 | -- $Id: ib_intmap.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_intmap - syn
-- Description: pdp11: external interrupt mapper (15 line)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz
-- 2016-05-26 641 2016.4 xc7a100t-1 0 30 0 0 - -
-- 2015-02-22 641 i 14.7 xc6slx16-2 0 20 0 0 9 -
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-23 1136 1.2 BUGFIX: ensure ACK send to correct device
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib
-- 2008-01-20 112 1.2 add INTMAP generic to externalize config
-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE
-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_intmap is -- external interrupt mapper
generic (
INTMAP : intmap_array_type := intmap_array_init);
port (
CLK : in slbit; -- clock
EI_REQ : in slv16_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end ib_intmap;
architecture syn of ib_intmap is
signal EI_LINE : slv4 := (others=>'0'); -- external interrupt line
signal R_LINE : slv4 := (others=>'0'); -- line on last cycle
type intp_type is array (15 downto 0) of slv3;
type intv_type is array (15 downto 0) of slv9;
constant conf_intp : intp_type :=
(slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
);
constant conf_intv : intv_type :=
(slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
);
-- attribute PRIORITY_EXTRACT : string;
-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
begin
EI_LINE <= "1111" when EI_REQ(15)='1' else
"1110" when EI_REQ(14)='1' else
"1101" when EI_REQ(13)='1' else
"1100" when EI_REQ(12)='1' else
"1011" when EI_REQ(11)='1' else
"1010" when EI_REQ(10)='1' else
"1001" when EI_REQ( 9)='1' else
"1000" when EI_REQ( 8)='1' else
"0111" when EI_REQ( 7)='1' else
"0110" when EI_REQ( 6)='1' else
"0101" when EI_REQ( 5)='1' else
"0100" when EI_REQ( 4)='1' else
"0011" when EI_REQ( 3)='1' else
"0010" when EI_REQ( 2)='1' else
"0001" when EI_REQ( 1)='1' else
"0000";
proc_line: process (CLK)
begin
if rising_edge(CLK) then
R_LINE <= EI_LINE;
end if;
end process proc_line;
-- Note: EI_ACKM comes one cycle after vector is latched ! Therefore
-- - use EI_LINE to select vector to send to EI_PRI and EI_VECT
-- - use R_LINE to select EI_ACM line for acknowledge
proc_intmap : process (EI_LINE, EI_ACKM, R_LINE)
variable ilinecur : integer := 0;
variable ilinelst : integer := 0;
variable iei_ack : slv16 := (others=>'0');
begin
ilinecur := to_integer(unsigned(EI_LINE));
ilinelst := to_integer(unsigned(R_LINE));
-- send info of currently highest priority request
EI_PRI <= conf_intp(ilinecur);
EI_VECT <= conf_intv(ilinecur)(8 downto 2);
-- route acknowledge back to winner line of last cycle
iei_ack := (others=>'0');
if EI_ACKM = '1' then
iei_ack(ilinelst) := '1';
end if;
EI_ACK <= iei_ack(EI_ACK'range);
end process proc_intmap;
end syn;
| gpl-3.0 | 0d135fef5f17dd8cec36ef4b02f91f0a | 0.543314 | 3.185729 | false | false | false | false |
wfjm/w11 | rtl/bplib/cmoda7/tb/cmoda7_sram_dummy.vhd | 1 | 2,201 | -- $Id: cmoda7_sram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cmoda7_sram_dummy - syn
-- Description: cmoda7 target (base; serport loopback, sram protect)
--
-- Dependencies: -
-- To test: tb_cmoda7_sram
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cmoda7_sram_dummy is -- CmodA7 dummy (base+sram)
-- implements cmoda7_sram_aif
port (
I_CLK12 : in slbit; -- 12 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3; -- c7 rgb-led 0 (act.low)
O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv19; -- sram: address lines
IO_MEM_DATA : inout slv8 -- sram: data lines
);
end cmoda7_sram_dummy;
architecture syn of cmoda7_sram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_BTN; -- mirror BTN on LED
O_RGBLED0_N(0) <= not I_BTN(0); -- mirror BTN on RGBLED 0 -> red
O_RGBLED0_N(1) <= not I_BTN(1); -- 1 -> green
O_RGBLED0_N(2) <= not (I_BTN(0) and I_BTN(1)); -- 0+1 -> white
O_MEM_CE_N <= '1';
O_MEM_WE_N <= '1';
O_MEM_OE_N <= '1';
O_MEM_ADDR <= (others=>'0');
IO_MEM_DATA <= (others=>'Z');
end syn;
| gpl-3.0 | 3315fe2538ddf2a6265dc0615c6c4f58 | 0.478873 | 3.355183 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_mig/arty/sys_conf.vhd | 1 | 2,005 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_mig_arty (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-23 1092 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | 46d73914a96d13759e410a78649a1403 | 0.61596 | 3.692449 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/Fixed_Point_ALU.vhd | 1 | 1,019 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.fixed_pkg.all;
entity Fixed_Point_ALU is
port( A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
result : out std_logic_vector(31 downto 0);
sel : in std_logic);
end Fixed_Point_ALU;
architecture behavioral of Fixed_Point_ALU is
signal A_fixed : sfixed(2 downto -29);
signal B_fixed : sfixed(2 downto -29);
signal result_fixed : sfixed(2 downto -29);
begin
A_fixed <= to_sfixed(A, 2, -29);
B_fixed <= to_sfixed(B, 2, -29);
result <= to_slv(result_fixed);
process (A_fixed, B_fixed, sel)
begin
if sel = '0' then --multiply
result_fixed <= resize(A_fixed * B_fixed, result_fixed'high, result_fixed'low);
else --divide
result_fixed <= resize(A_fixed / B_fixed, result_fixed'high, result_fixed'low);
end if;
end process;
end behavioral;
| mit | 8825e88272be671f416dc48c45dbdfe4 | 0.648675 | 2.945087 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/tbd_serport_autobaud.vhd | 1 | 4,482 | -- $Id: tbd_serport_autobaud.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_autobaud - syn
-- Description: Wrapper for serport_uart_autobaud and serport_uart_rxtx to
-- avoid records. It has a port interface which will not be
-- modified by xst synthesis (no records, no generic port).
--
-- Dependencies: clkdivce
-- serport_uart_autobaud
-- serport_uart_rxtx
-- serport_uart_rx
--
-- To test: serport_uart_autobaud
-- serport_uart_rxtx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 151 291 0 - t 9.23
-- 2007-10-27 92 9.1 J30 xc3s1000-4 151 291 0 - t 9.23
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 338 0 178 s 9.45
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 152 293 0 - s 9.40
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2008-01-20 112 1.0.1 rename clkgen->clkdivce
-- 2007-06-24 60 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
entity tbd_serport_autobaud is -- serial port autobaud [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CE_USEC : out slbit; -- usec pulse (here every 4 clocks)
CE_MSEC : out slbit; -- msec pulse (here every 20 clocks)
CLKDIV : out slv13; -- clock divider setting
ABACT : out slbit; -- autobaud active
ABDONE : out slbit; -- autobaud done
RXDATA : out slv8; -- receiver data out (1st rx)
RXVAL : out slbit; -- receiver data valid (1st rx)
RXERR : out slbit; -- receiver data error (1st rx)
RXACT : out slbit; -- receiver active (1st rx)
TXSD2 : out slbit; -- transmit serial data (2nd tx)
RXDATA3 : out slv8; -- receiver data out (3rd rx)
RXVAL3 : out slbit; -- receiver data valid (3rd rx)
RXERR3 : out slbit; -- receiver data error (3rd rx)
RXACT3 : out slbit -- receiver active (3rd rx)
);
end tbd_serport_autobaud;
architecture syn of tbd_serport_autobaud is
constant cdwidth : positive := 13;
signal LCE_MSEC : slbit := '0';
signal LCLKDIV : slv13 := (others=>'0');
signal LRXDATA : slv8 := (others=>'0');
signal LRXVAL : slbit := '0';
signal LTXSD2 : slbit := '0';
signal LABACT : slbit := '0';
begin
CKLDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => LCE_MSEC
);
AUTOBAUD : serport_uart_autobaud
generic map (
CDWIDTH => cdwidth,
CDINIT => 15)
port map (
CLK => CLK,
CE_MSEC => LCE_MSEC,
RESET => RESET,
RXSD => RXSD,
CLKDIV => LCLKDIV,
ACT => LABACT,
DONE => ABDONE
);
UART1 : serport_uart_rxtx
generic map (
CDWIDTH => cdwidth)
port map (
CLK => CLK,
RESET => LABACT,
CLKDIV => LCLKDIV,
RXSD => RXSD,
RXDATA => LRXDATA,
RXVAL => LRXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => LTXSD2,
TXDATA => LRXDATA,
TXENA => LRXVAL,
TXBUSY => open
);
UART2 : serport_uart_rx
generic map (
CDWIDTH => cdwidth)
port map (
CLK => CLK,
RESET => LABACT,
CLKDIV => LCLKDIV,
RXSD => LTXSD2,
RXDATA => RXDATA3,
RXVAL => RXVAL3,
RXERR => RXERR3,
RXACT => RXACT3
);
CE_MSEC <= LCE_MSEC;
CLKDIV <= LCLKDIV;
ABACT <= LABACT;
RXDATA <= LRXDATA;
RXVAL <= LRXVAL;
TXSD2 <= LTXSD2;
end syn;
| gpl-3.0 | cd9e2ec09ff75d329ca3d32e4ae3205d | 0.511379 | 3.738115 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd | 1 | 8,521 | -- $Id: sys_tst_rlink_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_s3 - syn
-- Description: rlink tester design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- bplib/s3board/s3_sram_dummy
--
-- Test bench: tb/tb_tst_rlink_s3
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-03-12 743 14.7 131013 xc3s1000e-4 931 2078 128 1383
-- 2014-12-20 614 14.7 131013 xc3s1000e-4 916 1973 128 1316 t 15.9
-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-19 748 1.2.2 define rlink SYSID
-- 2015-04-11 666 1.2.1 rearrange XON handling
-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of S3board switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(1): timer 1 busy
-- LED(0): timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_s3 is -- top level
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_s3;
architecture syn of sys_tst_rlink_s3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"01"; -- s3board
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
| gpl-3.0 | 4a0491c64ab2eaa86c2a9ca97aec787a | 0.493604 | 3.113263 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/sn_humanio_rbus.vhd | 1 | 14,745 | -- $Id: sn_humanio_rbus.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_rbus - syn
-- Description: sn_humanio with rbus interceptor
--
-- Dependencies: bpgen/sn_humanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 11.4-14.7; viv 2014.4-2019.1; ghdl 0.26-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-01-28 639 14.7 131013 xc6slx16-2 253 223 0 97 s 3.6 ns (n4)
-- 2015-01-28 639 14.7 131013 xc6slx16-2 141 120 0 42 s 3.5 ns (n2)
-- 2015-01-25 583 14.7 131013 xc6slx16-2 140 120 0 46 s 3.5 ns
-- 2011-08-14 406 12.1 M53d xc3s1000-4 142 156 0 123 s 5.1 ns
-- 2011-08-07 404 12.1 M53d xc3s1000-4 142 157 0 124 s 5.1 ns
-- 2010-12-29 351 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns
-- 2010-06-03 300 11.4 L68 xc3s1000-4 92 137 0 111 s 6.7 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 2.0.1 add stat_rbf_emu (=0); single cycle btn pulses
-- 2015-01-31 640 2.0 add SWIDTH,LWIDTH,DCWIDTH, change register layout
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2011-11-19 427 1.2.1 now numeric_std clean
-- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus
-- 2011-08-07 404 1.3 add pipeline regs ledin,(swi,btn,led,dp,dat)eff
-- 2011-07-08 390 1.2 renamed from s3_humanio_rbus, add BWIDTH generic
-- 2010-12-29 351 1.1 renamed from s3_humanio_rri; ported to rbv3
-- 2010-06-18 306 1.0.1 rename rbus data fields to _rbf_
-- 2010-06-03 300 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 000 stat r/-/- Status register
-- 15 emu r/-/- emulation (always 0)
-- 14:12 hdig r/-/- display size as (2**DCWIDTH)-1
-- 11:08 hled r/-/- led size as LWIDTH-1
-- 7:04 hbtn r/-/- button size as BWIDTH-1
-- 3:00 hswi r/-/- switch size as SWIDTH-1
--
-- 001 cntl r/w/- Control register
-- 4 dsp1_en r/w/- if 1 display msb will be driven by rbus
-- 3 dsp0_en r/w/- if 1 display lsb will be driven by rbus
-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
-- 1 led_en r/w/- if 1 LED will be driven by rbus
-- 0 swi_en r/w/- if 1 SWI will be driven by rbus
--
-- 010 x:00 btn r/-/f r: return hio BTN status
-- w: will pulse BTN
--
-- 011 x:00 swi r/w/- r: return hio SWI status
-- w: will drive SWI when swi_en=1
--
-- 100 x:00 led r/w/- r: return hio LED status
-- w: will drive LED when led_en=1
--
-- 101 x:00 dp r/w/- r: return hio DSP_DP status
-- w: will drive dp's when dp_en=1
--
-- 110 15:00 dsp0 r/w/- r: return hio DSP_DAT lsb status
-- w: will drive DSP_DAT lsb when dsp_en=1
-- 111 15:00 dsp1 r/w/- r: return hio DSP_DAT msb status
-- w: will drive DSP_DAT msb when dsp_en=1
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
SWIDTH : positive := 8; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 8; -- LED port width
DCWIDTH : positive := 2; -- digit counter width (2 or 3)
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv16 := x"fef0");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
DSP_DAT : in slv(4*(2**DCWIDTH)-1 downto 0); -- display data
DSP_DP : in slv((2**DCWIDTH)-1 downto 0); -- display decimal points
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0); -- pad-o: leds
O_ANO_N : out slv((2**DCWIDTH)-1 downto 0); -- pad-o: disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: disp: segments (act.low)
);
end sn_humanio_rbus;
architecture syn of sn_humanio_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv(SWIDTH-1 downto 0); -- rbus swi
btn : slv(BWIDTH-1 downto 0); -- rbus btn
led : slv(LWIDTH-1 downto 0); -- rbus led
dsp_dat : slv(4*(2**DCWIDTH)-1 downto 0); -- rbus dsp_dat
dsp_dp : slv((2**DCWIDTH)-1 downto 0); -- rbus dsp_dp
ledin : slv(LWIDTH-1 downto 0); -- led from design
swieff : slv(SWIDTH-1 downto 0); -- effective swi
btneff : slv(BWIDTH-1 downto 0); -- effective btn
ledeff : slv(LWIDTH-1 downto 0); -- effective led
dateff : slv(4*(2**DCWIDTH)-1 downto 0); -- effective dsp_dat
dpeff : slv((2**DCWIDTH)-1 downto 0); -- effective dsp_dp
swi_en : slbit; -- enable: swi from rbus
led_en : slbit; -- enable: led from rbus
dsp0_en : slbit; -- enable: dsp_dat lsb from rbus
dsp1_en : slbit; -- enable: dsp_dat msb from rbus
dp_en : slbit; -- enable: dsp_dp from rbus
end record regs_type;
constant swizero : slv(SWIDTH-1 downto 0) := (others=>'0');
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant ledzero : slv(LWIDTH-1 downto 0) := (others=>'0');
constant dpzero : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
constant datzero : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
swizero, -- swi
btnzero, -- btn
ledzero, -- led
datzero, -- dsp_dat
dpzero, -- dsp_dp
ledzero, -- ledin
swizero, -- swieff
btnzero, -- btneff
ledzero, -- ledeff
datzero, -- dateff
dpzero, -- dpeff
'0','0','0','0','0' -- (swi|led|dsp0|dsp1|dp)_en
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
constant stat_rbf_emu: integer := 15;
subtype stat_rbf_hdig is integer range 14 downto 12;
subtype stat_rbf_hled is integer range 11 downto 8;
subtype stat_rbf_hbtn is integer range 7 downto 4;
subtype stat_rbf_hswi is integer range 3 downto 0;
constant cntl_rbf_dsp1_en: integer := 4;
constant cntl_rbf_dsp0_en: integer := 3;
constant cntl_rbf_dp_en: integer := 2;
constant cntl_rbf_led_en: integer := 1;
constant cntl_rbf_swi_en: integer := 0;
constant rbaddr_stat: slv3 := "000"; -- 0 r/-/-
constant rbaddr_cntl: slv3 := "001"; -- 0 r/w/-
constant rbaddr_btn: slv3 := "010"; -- 1 r/-/f
constant rbaddr_swi: slv3 := "011"; -- 1 r/w/-
constant rbaddr_led: slv3 := "100"; -- 2 r/w/-
constant rbaddr_dp: slv3 := "101"; -- 3 r/w/-
constant rbaddr_dsp0: slv3 := "110"; -- 4 r/w/-
constant rbaddr_dsp1: slv3 := "111"; -- 5 r/w/-
subtype dspdat_msb is integer range 4*(2**DCWIDTH)-1 downto 4*(2**DCWIDTH)-16;
subtype dspdat_lsb is integer range 15 downto 0;
signal HIO_SWI : slv(SWIDTH-1 downto 0) := (others=>'0');
signal HIO_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
signal HIO_LED : slv(LWIDTH-1 downto 0) := (others=>'0');
signal HIO_DSP_DAT : slv(4*(2**DCWIDTH)-1 downto 0) := (others=>'0');
signal HIO_DSP_DP : slv((2**DCWIDTH)-1 downto 0) := (others=>'0');
begin
assert SWIDTH<=16
report "assert (SWIDTH<=16)"
severity failure;
assert BWIDTH<=8
report "assert (BWIDTH<=8)"
severity failure;
assert LWIDTH<=16
report "assert (LWIDTH<=16)"
severity failure;
assert DCWIDTH=2 or DCWIDTH=3
report "assert(DCWIDTH=2 or DCWIDTH=3): unsupported DCWIDTH"
severity FAILURE;
HIO : sn_humanio
generic map (
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,
LWIDTH => LWIDTH,
DCWIDTH => DCWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => HIO_SWI,
BTN => HIO_BTN,
LED => HIO_LED,
DSP_DAT => HIO_DSP_DAT,
DSP_DP => HIO_DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- input register for LED signal
n.ledin := LED;
-- clear btn register --> cause single cycle pulses
n.btn := (others=>'0');
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(2 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_emu) := '0';
irb_dout(stat_rbf_hdig) := slv(to_unsigned((2**DCWIDTH)-1,3));
irb_dout(stat_rbf_hled) := slv(to_unsigned(LWIDTH-1,4));
irb_dout(stat_rbf_hbtn) := slv(to_unsigned(BWIDTH-1,4));
irb_dout(stat_rbf_hswi) := slv(to_unsigned(SWIDTH-1,4));
if RB_MREQ.we = '1' then
irb_ack := '0';
end if;
when rbaddr_cntl =>
irb_dout(cntl_rbf_dsp1_en) := r.dsp1_en;
irb_dout(cntl_rbf_dsp0_en) := r.dsp0_en;
irb_dout(cntl_rbf_dp_en) := r.dp_en;
irb_dout(cntl_rbf_led_en) := r.led_en;
irb_dout(cntl_rbf_swi_en) := r.swi_en;
if RB_MREQ.we = '1' then
n.dsp1_en := RB_MREQ.din(cntl_rbf_dsp1_en);
n.dsp0_en := RB_MREQ.din(cntl_rbf_dsp0_en);
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
end if;
when rbaddr_btn =>
irb_dout(HIO_BTN'range) := HIO_BTN;
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(n.btn'range);
end if;
when rbaddr_swi =>
irb_dout(HIO_SWI'range) := HIO_SWI;
if RB_MREQ.we = '1' then
n.swi := RB_MREQ.din(n.swi'range);
end if;
when rbaddr_led =>
irb_dout(r.ledin'range) := r.ledin;
if RB_MREQ.we = '1' then
n.led := RB_MREQ.din(n.led'range);
end if;
when rbaddr_dp =>
irb_dout(HIO_DSP_DP'range) := HIO_DSP_DP;
if RB_MREQ.we = '1' then
n.dsp_dp := RB_MREQ.din(n.dsp_dp'range);
end if;
when rbaddr_dsp0 =>
irb_dout := HIO_DSP_DAT(dspdat_lsb);
if RB_MREQ.we = '1' then
n.dsp_dat(dspdat_lsb) := RB_MREQ.din;
end if;
when rbaddr_dsp1 =>
irb_dout := HIO_DSP_DAT(dspdat_msb);
if RB_MREQ.we = '1' then
n.dsp_dat(dspdat_msb) := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
n.btneff := HIO_BTN or r.btn;
if r.swi_en = '0' then
n.swieff := HIO_SWI;
else
n.swieff := r.swi;
end if;
if r.led_en = '0' then
n.ledeff := r.ledin;
else
n.ledeff := r.led;
end if;
if r.dp_en = '0' then
n.dpeff := DSP_DP;
else
n.dpeff := r.dsp_dp;
end if;
if r.dsp0_en = '0' then
n.dateff(dspdat_lsb) := DSP_DAT(dspdat_lsb);
else
n.dateff(dspdat_lsb) := r.dsp_dat(dspdat_lsb);
end if;
if DCWIDTH=3 then
if r.dsp1_en = '0' then
n.dateff(dspdat_msb) := DSP_DAT(dspdat_msb);
else
n.dateff(dspdat_msb) := r.dsp_dat(dspdat_msb);
end if;
end if;
N_REGS <= n;
BTN <= R_REGS.btneff;
SWI <= R_REGS.swieff;
HIO_LED <= R_REGS.ledeff;
HIO_DSP_DP <= R_REGS.dpeff;
HIO_DSP_DAT <= R_REGS.dateff;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 | 2f9249dc795b4fabb0ee107abd267940 | 0.496372 | 3.27303 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_2clock.vhd | 1 | 12,604 | -- $Id: serport_2clock.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_2clock - syn
-- Description: serial port: serial port module, 2 clock domain
--
-- Dependencies: cdclib/cdc_pulse
-- serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-04-12 666 14.7 131013 xc6slx16-2 285 283 32 138 s 6.2/5.9
-- 2011-11-13 424 13.1 O40d xc3s1000-4 224 362 64 295 s 8.6/10.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-28 755 1.1.2 check assertions only at raising clock
-- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR
-- 2015-02-01 641 1.1 add CLKDIV_F for autobaud;
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-11-07 421 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.cdclib.all;
use work.memlib.all;
entity serport_2clock is -- serial port module, 2 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- clock (backend:user)
RESET : in slbit; -- reset
CLKS : in slbit; -- clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end serport_2clock;
architecture syn of serport_2clock is
type synu_type is record
rxact_c : slbit; -- rxact (capt from CLKS->CLKU)
rxact_s : slbit; -- rxact (sync in CLKU)
txact_c : slbit; -- txact (capt from CLKS->CLKU)
txact_s : slbit; -- txact (sync in CLKU)
abact_c : slbit; -- abact (capt from CLKS->CLKU)
abact_s : slbit; -- abact (sync in CLKU)
rxok_c : slbit; -- rxok (capt from CLKS->CLKU)
rxok_s : slbit; -- rxok (sync in CLKU)
txok_c : slbit; -- txok (capt from CLKS->CLKU)
txok_s : slbit; -- txok (sync in CLKU)
abclkdiv_c : slv(CDWIDTH-1 downto 0); -- abclkdiv (capt from CLKS->CLKU)
abclkdiv_s : slv(CDWIDTH-1 downto 0); -- abclkdiv (sync in CLKU)
end record synu_type;
constant synu_init : synu_type := (
'0','0', -- rxact_c,_s
'0','0', -- txact_c,_s
'0','0', -- abact_c,_s
'0','0', -- rxok_c,_s
'0','0', -- txok_c,_s
slv(to_unsigned(0,CDWIDTH)), -- abclkdiv_c
slv(to_unsigned(0,CDWIDTH)) -- abclkdiv_s
);
type syns_type is record
enaxon_c : slbit; -- enaxon (capt from CLKU->CLKS)
enaxon_s : slbit; -- enaxon (sync in CLKS)
enaesc_c : slbit; -- enaesc (capt from CLKU->CLKS)
enaesc_s : slbit; -- enaesc (sync in CLKS)
end record syns_type;
constant syns_init : syns_type := (
'0','0', -- enaxon_c,_s
'0','0' -- enaxon_c,_s
);
signal R_SYNU : synu_type := synu_init; -- sync registers (clku)
signal R_SYNS : syns_type := syns_init; -- sync registers (clks)
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal RESET_CLKS : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
signal RXERR_CLKU : slbit := '0';
signal RXOVR_CLKU : slbit := '0';
signal ABDONE_CLKU : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
CDC_RESET : cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => false)
port map (
CLKM => CLKU,
RESET => '0',
CLKS => CLKS,
PIN => RESET,
BUSY => open,
POUT => RESET_CLKS
);
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLKS,
CE_MSEC => CES_MSEC,
RESET => RESET_CLKS,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV,
ABCLKDIV_F => open
);
RESET_INT <= RESET_CLKS or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => R_SYNS.enaxon_s,
ENAESC => R_SYNS.enaesc_s,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKS,
CLKR => CLKU,
RESETW => ABACT, -- clear fifo on abact
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXFIFO_SIZEW,
SIZER => open
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKU,
CLKR => CLKS,
RESETW => RESET,
RESETR => ABACT, -- clear fifo on abact
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
-- receive back pressure
-- on if fifo more than 3/4 full (less than 1/4 free)
-- off if fifo less than 1/2 full (more than 1/2 free)
proc_rxok: process (CLKS)
constant rxsize_rxok_off : slv2 := "01";
constant rxsize_rxok_on : slv2 := "10";
variable rxsize_msb : slv2 := "00";
begin
if rising_edge(CLKS) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2);
if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
proc_synu: process (CLKU)
begin
if rising_edge(CLKU) then
R_SYNU.rxact_c <= RXACT;
R_SYNU.rxact_s <= R_SYNU.rxact_c;
R_SYNU.txact_c <= UART_TXBUSY;
R_SYNU.txact_s <= R_SYNU.txact_c;
R_SYNU.abact_c <= ABACT;
R_SYNU.abact_s <= R_SYNU.abact_c;
R_SYNU.rxok_c <= RXOK;
R_SYNU.rxok_s <= R_SYNU.rxok_c;
R_SYNU.txok_c <= TXOK;
R_SYNU.txok_s <= R_SYNU.txok_c;
R_SYNU.abclkdiv_c <= ABCLKDIV;
R_SYNU.abclkdiv_s <= R_SYNU.abclkdiv_c;
end if;
end process proc_synu;
proc_syns: process (CLKS)
begin
if rising_edge(CLKS) then
R_SYNS.enaxon_c <= ENAXON;
R_SYNS.enaxon_s <= R_SYNS.enaxon_c;
R_SYNS.enaesc_c <= ENAESC;
R_SYNS.enaesc_s <= R_SYNS.enaesc_c;
end if;
end process proc_syns;
CDC_RXERR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXERR,
BUSY => open,
POUT => RXERR_CLKU
);
CDC_RXOVR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXOVR,
BUSY => open,
POUT => RXOVR_CLKU
);
CDC_ABDONE : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => ABDONE,
BUSY => open,
POUT => ABDONE_CLKU
);
MONI.rxerr <= RXERR_CLKU;
MONI.rxovr <= RXOVR_CLKU;
MONI.rxact <= R_SYNU.rxact_s;
MONI.txact <= R_SYNU.txact_s;
MONI.abact <= R_SYNU.abact_s;
MONI.abdone <= ABDONE_CLKU;
MONI.rxok <= R_SYNU.rxok_s;
MONI.txok <= R_SYNU.txok_s;
proc_abclkdiv: process (R_SYNU.abclkdiv_s)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(R_SYNU.abclkdiv_s'range) <= R_SYNU.abclkdiv_s;
end process proc_abclkdiv;
-- synthesis translate_off
proc_check: process (CLKS)
begin
if rising_edge(CLKS) then
assert RXOVR = '0'
report "serport_2clock-W: RXOVR = " & slbit'image(RXOVR) &
"; data loss in receive fifo"
severity warning;
assert RXERR = '0'
report "serport_2clock-W: RXERR = " & slbit'image(RXERR) &
"; spurious receive error"
severity warning;
end if;
end process proc_check;
-- synthesis translate_on
end syn;
| gpl-3.0 | e3cdf239a445ae87af4d98e0fdfa69ca | 0.514123 | 3.565488 | false | false | false | false |
sjohann81/hf-risc | riscv/sim/boot_ram.vhd | 2 | 1,728 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity boot_ram is
generic(memory_file : string := "boot.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 12; -- address width
bank: integer := 0); -- memory bank (0,1,2,3)
port(
clk : in std_logic; --clock
addr : in std_logic_vector(address_width - 1 downto 2); --address bus
cs_n : in std_logic; --chip select
we_n : in std_logic; --write enable
data_i: in std_logic_vector(data_width - 1 downto 0); --write data bus
data_o: out std_logic_vector(data_width - 1 downto 0) --read data bus
);
end boot_ram;
architecture memory of boot_ram is
type ram is array(2 ** address_width - 1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal ram1 : ram := (others => (others => '0'));
begin
process(clk)
variable data : std_logic_vector(data_width*4 -1 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is "boot.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
readline(load_file, hex_file_line);
hread(hex_file_line, data);
ram1(conv_integer(index)) <= data(((bank+1)*data_width)-1 downto bank*data_width);
index := index + 1;
end loop;
end if;
if (clk'event and clk = '1') then
if(cs_n = '0') then
if(we_n = '0') then
ram1(conv_integer(addr(address_width -1 downto 2))) <= data_i;
else
data_o <= ram1(conv_integer(addr(address_width -1 downto 2)));
end if;
end if;
end if;
end process;
end memory;
| gpl-2.0 | 229f29ed718ecc91aedf791857c72cb7 | 0.644676 | 2.809756 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01000_bad.vhd | 1 | 3,675 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01000_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of variable name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01000_bad is
generic (
g_Width : positive := 4 -- Data Width
);
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Data : in std_logic_vector(g_Width-1 downto 0); -- Data from which to count ones
o_Nb_One : out std_logic_vector(g_Width-1 downto 0) -- Number of ones in i_Data signal
);
end CNE_01000_bad;
architecture Behavioral of CNE_01000_bad is
-- Function to get the number of ones in a signal
function Get_Ones(data : in std_logic_vector(g_Width-1 downto 0)) return integer is
-- Number of ones in the input signal
variable nb_ones : integer range 0 to g_Width;
begin
nb_ones := 0;
-- Loop on each signal's bit
for i in 0 to g_Width-1 loop
if (data(i)='1') then
nb_ones := nb_ones + 1;
end if;
end loop;
return nb_ones;
end function;
-- Module output
signal Nb_One : std_logic_vector(g_Width-1 downto 0);
begin
-- Counts the number of ones in a signal and register this count.
p_Count_Ones:process(i_Reset_n,i_Clock)
begin
if (i_Reset_n='0') then
Nb_One <= (others => '0');
elsif (rising_edge(i_Clock)) then
Nb_One <= std_logic_vector(to_unsigned(Get_Ones(i_Data),Nb_One'length));
end if;
end process;
o_Nb_One <= Nb_One;
end Behavioral; | gpl-3.0 | 37a871ce4ca562be1e0f7f502482e5d5 | 0.500952 | 4.369798 | false | false | false | false |
wfjm/w11 | rtl/vlib/comlib/crc16.vhd | 1 | 1,789 | -- $Id: crc16.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: crc16 - syn
-- Description: 16bit CRC generator, use CCITT polynomial
-- x^16 + x^12 + x^5 + 1 (0x1021)
--
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-09-27 595 14.7 131013 xc6slx16-2 16 16 - 4
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-27 595 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.comlib.all;
entity crc16 is -- crc-16 generator, checker
generic (
INIT: slv16 := (others=>'0')); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv16 -- crc code
);
end crc16;
architecture syn of crc16 is
signal R_CRC : slv16 := INIT; -- state registers
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_CRC <= INIT;
else
if ENA = '1' then
R_CRC <= crc16_update(R_CRC, DI);
end if;
end if;
end if;
end process proc_regs;
CRC <= R_CRC;
end syn;
| gpl-3.0 | fc45bf685ca763cf15cbf2cf961a9a32 | 0.486305 | 3.65102 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd | 1 | 3,560 | -- $Id: tb_tst_serloop1_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n2 - sim
-- Description: Test bench for sys_tst_serloop1_n2
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop2_n2 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n2
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop1_n2 is
end tb_tst_serloop1_n2;
architecture sim of tb_tst_serloop1_n2 is
signal CLK50 : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50
);
UUT : entity work.sys_tst_serloop1_n2
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FLA_CE_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK50,
CLKH => CLK50,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | 1a1926a89500d0fa24dcd678566937b2 | 0.510674 | 2.979079 | false | false | false | false |
wfjm/w11 | rtl/bplib/issi/is61lv25616al.vhd | 1 | 5,949 | -- $Id: is61lv25616al.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: is61lv25616al - sim
-- Description: ISSI 61LV25612AL SRAM model
-- Currently a truely minimalistic functional model, without
-- any timing checks. It assumes, that addr/data is stable at
-- the trailing edge of we.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted
-- 2007-12-14 101 1.0 Initial version (written on warsaw airport)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Mode WE_N CE_N OE_N LB_N UB_N D(7:0) D(15:8)
-- Not selected X H X X X high-Z high-Z
-- Output disabled H L H X X high-Z high-Z
-- X L X H H high-Z high-Z
-- Read H L L L H D_out high-Z
-- H L L H L high-Z D_out
-- H L L L L D_out D_out
-- Write L L X L H D_in high-Z
-- L L X H L high-Z D_in
-- L L X L L D_in D_in
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity is61lv25616al is -- ISSI 61LV25612AL SRAM model
port (
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
UB_N : in slbit; -- upper byte enable (act.low)
LB_N : in slbit; -- lower byte enable (act.low)
ADDR : in slv18; -- address lines
DATA : inout slv16 -- data lines
);
end is61lv25616al;
architecture sim of is61lv25616al is
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal BE_L : slbit := '0';
signal BE_U : slbit := '0';
component is61lv25616al_bank is -- ISSI 61LV25612AL bank
port (
CE : in slbit; -- chip enable (act.high)
OE : in slbit; -- output enable (act.high)
WE : in slbit; -- write enable (act.high)
BE : in slbit; -- byte enable (act.high)
ADDR : in slv18; -- address lines
DATA : inout slv8 -- data lines
);
end component;
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
BE_L <= not LB_N;
BE_U <= not UB_N;
BANK_L : is61lv25616al_bank port map (
CE => CE,
OE => OE,
WE => WE,
BE => BE_L,
ADDR => ADDR,
DATA => DATA(7 downto 0));
BANK_U : is61lv25616al_bank port map (
CE => CE,
OE => OE,
WE => WE,
BE => BE_U,
ADDR => ADDR,
DATA => DATA(15 downto 8));
end sim;
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity is61lv25616al_bank is -- ISSI 61LV25612AL bank
port (
CE : in slbit; -- chip enable (act.high)
OE : in slbit; -- output enable (act.high)
WE : in slbit; -- write enable (act.high)
BE : in slbit; -- byte enable (act.high)
ADDR : in slv18; -- address lines
DATA : inout slv8 -- data lines
);
end is61lv25616al_bank;
architecture sim of is61lv25616al_bank is
constant T_rc : Delay_length := 10 ns; -- read cycle time (min)
constant T_aa : Delay_length := 10 ns; -- address access time (max)
constant T_oha : Delay_length := 2 ns; -- output hold time (min)
constant T_ace : Delay_length := 10 ns; -- ce access time (max)
constant T_doe : Delay_length := 4 ns; -- oe access time (max)
constant T_hzoe : Delay_length := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : Delay_length := 0 ns; -- oe to low-Z output (min)
constant T_hzce : Delay_length := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : Delay_length := 3 ns; -- ce to low-Z output (min)
constant T_ba : Delay_length := 4 ns; -- lb,ub access time (max)
constant T_hzb : Delay_length := 3 ns; -- lb,ub to high-Z out (min=0,max=3)
constant T_lzb : Delay_length := 0 ns; -- lb,ub low-Z output (min)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
signal WE_EFF : slbit := '0';
begin
WE_EFF <= CE and WE and BE;
proc_sram: process (CE, OE, WE, BE, WE_EFF, ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
if falling_edge(WE_EFF) then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
end if;
if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver
DATA <= ram(to_integer(unsigned(ADDR)));
else
DATA <= (others=>'Z');
end if;
end process proc_sram;
end sim;
| gpl-3.0 | 8b3dbe0282a1e2fdc8384227b3866f41 | 0.488317 | 3.387813 | false | false | false | false |
sjohann81/hf-risc | riscv/platform/spartan3e_nexys2/spartan3e_nexys2.vhd | 1 | 4,864 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 15;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | 34b1b9bdd34874e5d0d31371f2696bda | 0.63014 | 2.615054 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/migui2bram.vhd | 1 | 5,651 | -- $Id: migui2bram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: migui2bram - sim
-- Description: MIG to BRAM adapter
--
-- Dependencies: xlib/s7_cmt_sfs
-- memlib/ram_1swsr_wfirst_gen
-- cdclib/cdc_signal_s1_as
-- Test bench: -
-- Target Devices: 7-Series
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-28 1096 1.0 Initial version
-- 2018-11-10 1067 0.1 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.cdclib.all;
use work.xlib.all;
entity migui2bram is -- MIG to BRAM adapter
generic (
BAWIDTH : positive := 4; -- byte address width
MAWIDTH : positive := 28; -- memory address width
RAWIDTH : positive := 19; -- BRAM memory address width
RDELAY : positive := 5; -- read response delay
CLKMUI_MUL : positive := 6; -- multiplier for MIGUI clock
CLKMUI_DIV : positive := 12; -- divider for MIGUI clock
CLKMSYS_PERIOD : real := 6.000); -- MIG SYS_CLK period
port (
SYS_CLK : in slbit; -- system clock
SYS_RST : in slbit; -- system reset
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_EN : in slbit; -- MIGUI command enable
APP_CMD : in slv3; -- MIGUI command
APP_ADDR : in slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_WDF_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
APP_WDF_MASK : in slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask
APP_WDF_END : in slbit; -- MIGUI write end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RD_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : out slbit -- MIGUI read end
);
end migui2bram;
architecture syn of migui2bram is
constant mwidth : positive := 2**BAWIDTH; -- mask width (8 or 16)
signal CLKFX : slbit := '0';
signal CLK : slbit := '0'; -- local copy of UI_CLK
signal R_RDVAL : slv(RDELAY downto 0) := (others=>'0');
signal LOCKED : slbit := '0'; -- raw from mmcm
signal LOCKED_UICLK : slbit := '0'; -- sync'ed to UI_CLK
begin
assert BAWIDTH = 3 or BAWIDTH = 4
report "assert( BAWIDTH = 3 or 4 )"
severity failure;
GEN_CLKMUI : s7_cmt_sfs -- ui clock ------------
generic map (
VCO_DIVIDE => 1,
VCO_MULTIPLY => CLKMUI_MUL,
OUT_DIVIDE => CLKMUI_DIV,
CLKIN_PERIOD => CLKMSYS_PERIOD,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => "MMCM")
port map (
CLKIN => SYS_CLK,
CLKFX => CLKFX,
LOCKED => LOCKED
);
CLK <= CLKFX; -- !! copy both local CLK and exported
UI_CLK <= CLKFX; -- !! UI_CLK to avoid delta cycle diff
CDC_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_UICLK
);
MARRAY: for col in mwidth-1 downto 0 generate
signal MEM_WE : slbit := '0';
begin
MEM_WE <= APP_WDF_WREN and not APP_WDF_MASK(col); -- WE = not MASK !
MCELL : ram_1swsr_wfirst_gen
generic map (
AWIDTH => RAWIDTH-BAWIDTH,
DWIDTH => 8) -- byte wide
port map (
CLK => CLK,
EN => APP_EN,
WE => MEM_WE,
ADDR => APP_ADDR(RAWIDTH-1 downto BAWIDTH),
DI => APP_WDF_DATA(8*col+7 downto 8*col),
DO => APP_RD_DATA(8*col+7 downto 8*col)
);
end generate MARRAY;
UI_CLK_SYNC_RST <= not LOCKED_UICLK;
INIT_CALIB_COMPLETE <= LOCKED_UICLK;
APP_RDY <= '1';
APP_WDF_RDY <= '1';
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if SYS_RST = '1' then
R_RDVAL <= (others=>'0');
else
R_RDVAL(0) <= APP_EN and not APP_WDF_WREN;
R_RDVAL(RDELAY downto 1) <= R_RDVAL(RDELAY-1 downto 0);
end if;
end if;
end process proc_regs;
APP_RD_DATA_VALID <= R_RDVAL(RDELAY);
APP_RD_DATA_END <= R_RDVAL(RDELAY);
-- synthesis translate_off
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if SYS_RST = '0' then
if APP_EN = '1' then
assert unsigned(APP_ADDR(MAWIDTH-1 downto RAWIDTH)) = 0
report "migui2bram: FAIL: out of memory size access"
severity error;
else
assert APP_WDF_WREN = '0'
report "migui2bram: FAIL: APP_WDF_WREN=1 when APP_EN=0"
severity error;
end if;
assert APP_WDF_WREN = APP_WDF_END
report "migui2bram: FAIL: APP_WDF_WREN /= APP_WDF_END"
severity error;
end if;
end if;
end process proc_moni;
-- synthesis translate_on
end syn;
| gpl-3.0 | 6e9c371cf1f73e1d6eca27f6a2bfc1f7 | 0.525571 | 3.556325 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/memlib.vhd | 1 | 11,652 | -- $Id: memlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: memlib
-- Description: Basic memory components: single/dual port synchronous and
-- asynchronus rams; Fifo's.
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-03 1109 1.1.1 add fifo_simple_dram
-- 2016-03-25 751 1.1 add fifo_2c_dram2
-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0.2 change generic default for BRAM models
-- 2007-12-27 106 1.0.1 add fifo_2c_dram
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package memlib is
component ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
component ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
component ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
generic (
AWIDTH : positive := 10; -- address port width
DWIDTH : positive := 16); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
component ram_1swsr_rfirst_gen is -- RAM, 1 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
component ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
component ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
component ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w port
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
component fifo_simple_dram is -- fifo, CE/WE interface, dram based
generic (
AWIDTH : positive := 6; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
);
end component;
component fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
WE : in slbit; -- write enable
RE : in slbit; -- read enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
EMPTY : out slbit; -- empty flag
FULL : out slbit -- full flag
);
end component;
component fifo_1c_dram is -- fifo, 1 clock, dram based
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZE : out slv(AWIDTH downto 0) -- number of used slots
);
end component;
component fifo_1c_bubble is -- fifo, 1 clock, bubble regs
generic (
NSTAGE : positive := 4; -- number of stages
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component fifo_2c_dram is -- fifo, 2 clock, dram based
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end component;
component fifo_2c_dram2 is -- fifo, 2 clock, dram based (v2)
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end component;
end package memlib;
| gpl-3.0 | a6e93525e0c312cfa8f3f4353680905b | 0.502575 | 3.923232 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_xonrx.vhd | 1 | 4,031 | -- $Id: serport_xonrx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_xonrx - syn
-- Description: serial port: xon/xoff logic rx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0 Initial version
------------------------------------------------------------------------------
-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
-- !!!! appended to the name, has been created in the /tb sub folder.
-- !!!! Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end serport_xonrx;
architecture syn of serport_xonrx is
type regs_type is record
txok : slbit; -- tx channel ok state
escseen : slbit; -- escape seen
rxdata : slv8; -- user rxdata
rxval : slbit; -- user rxval
rxovr : slbit; -- user rxovr
end record regs_type;
constant regs_init : regs_type := (
'1', -- txok (startup default is ok !!)
'0', -- escseen
(others=>'0'), -- rxdata
'0','0' -- rxval,rxovr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if ENAXON = '0' then
n.txok := '1';
end if;
if ENAESC = '0' then
n.escseen := '0';
end if;
n.rxovr := '0'; -- ensure single clock pulse
if UART_RXVAL = '1' then
if ENAXON='1' and UART_RXDATA=c_serport_xon then
n.txok := '1';
elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
n.txok := '0';
elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
n.escseen := '1';
else
if r.escseen = '1' then
n.escseen := '0';
end if;
if r.rxval = '0' then
n.rxval := '1';
if r.escseen = '1' then
n.rxdata := not UART_RXDATA;
else
n.rxdata := UART_RXDATA;
end if;
else
n.rxovr := '1';
end if;
end if;
end if;
if r.rxval='1' and RXHOLD='0' then
n.rxval := '0';
end if;
N_REGS <= n;
RXDATA <= r.rxdata;
RXVAL <= r.rxval;
RXOVR <= r.rxovr;
TXOK <= r.txok;
end process proc_next;
end syn;
| gpl-3.0 | 5cf9ca7c3635d2abf1d49d08c973cbba | 0.491193 | 3.864813 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/serport_xontx.vhd | 1 | 4,600 | -- $Id: serport_xontx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx - syn
-- Description: serial port: xon/xoff logic tx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-10-22 417 0.5 First draft
------------------------------------------------------------------------------
-- Note: for test bench usage a copy of all serport_* entities, with _tb
-- appended to the name, has been created in the /tb sub folder.
-- Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx;
architecture syn of serport_xontx is
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
end syn;
| gpl-3.0 | 335d7025be5be15b4cc7715231338301 | 0.471739 | 3.849372 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_reg70.vhd | 1 | 3,551 | -- $Id: pdp11_reg70.vhd 1279 2022-08-14 08:02:21Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_reg70 - syn
-- Description: pdp11: 11/70 system registers
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-08-14 1279 1.1.3 set sysid to 010123
-- 2015-04-30 670 1.1.2 rename sys70 -> reg70
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.1 use iblib
-- 2008-04-20 137 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity pdp11_reg70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_reg70;
architecture syn of pdp11_reg70 is
constant ibaddr_mbrk : slv16 := slv(to_unsigned(8#177770#,16));
constant ibaddr_sysid : slv16 := slv(to_unsigned(8#177764#,16));
type regs_type is record -- state registers
ibsel_mbrk : slbit; -- ibus select mbrk
ibsel_sysid : slbit; -- ibus select sysid
mbrk : slv8; -- status of mbrk register
end record regs_type;
constant regs_init : regs_type := (
'0','0', -- ibsel_*
mbrk=>(others=>'0') -- mbrk
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel_mbrk := '0';
n.ibsel_sysid := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr = ibaddr_mbrk(12 downto 1) then
n.ibsel_mbrk := '1';
end if;
if IB_MREQ.addr = ibaddr_sysid(12 downto 1) then
n.ibsel_sysid := '1';
end if;
end if;
-- ibus transactions
if r.ibsel_mbrk = '1' then
idout(r.mbrk'range) := r.mbrk;
end if;
if r.ibsel_sysid = '1' then
idout := slv(to_unsigned(8#010123#,16));
end if;
if r.ibsel_mbrk='1' and ibw0='1' then
n.mbrk := IB_MREQ.din(n.mbrk'range);
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= (r.ibsel_mbrk or r.ibsel_sysid) and ibreq;
IB_SRES.busy <= '0';
end process proc_next;
end syn;
| gpl-3.0 | 10389b820d79d9d0981f1840733a6280 | 0.524641 | 3.306331 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/stack_in_MUX.vhd | 2 | 1,047 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity stack_in_MUX is
port(sel : in std_logic_vector(2 downto 0);
ctl_immediate : in std_logic_vector(31 downto 0);
ALU_result : in std_logic_vector(31 downto 0);
IO_ipins_data : in std_logic_vector(31 downto 0);
IO_iport_data : in std_logic_vector(31 downto 0);
mem_data_out : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end stack_in_MUX;
architecture Behavioral of stack_in_MUX is
begin
main : process(sel, ctl_immediate, ALU_result, IO_ipins_data, IO_iport_data, mem_data_out) is
begin
case (sel) is
when "000" =>
output <= ctl_immediate;
when "001" =>
output <= ALU_result;
when "010" =>
output <= IO_ipins_data;
when "011" =>
output <= IO_iport_data;
when others =>
output <= mem_data_out;
end case;
end process;
end Behavioral;
| mit | bfbfeb84be9c2051c81634258c04262a | 0.635148 | 3.026012 | false | false | false | false |
wfjm/w11 | rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd | 1 | 7,472 | -- $Id: fx2_2fifo_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifo_core - sim
-- Description: Cypress EZ-USB FX2 (2 fifo core model)
--
-- Dependencies: memlib/fifo_2c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.0.1 proc_ifclk: remove clock stop (not needed anymore)
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
use work.fx2lib.all;
use work.memlib.all;
entity fx2_2fifo_core is -- EZ-USB FX2 (2 fifo core model)
port (
CLK : in slbit; -- uplink clock
RESET : in slbit; -- reset
RXDATA : in slv8; -- rx data (ext->fx2)
RXENA : in slbit; -- rx enable
RXBUSY : out slbit; -- rx busy
TXDATA : out slv8; -- tx data (fx2->ext)
TXVAL : out slbit; -- tx valid
IFCLK : out slbit; -- fx2 interface clock
FIFO : in slv2; -- fx2 fifo address
FLAG : out slv4; -- fx2 fifo flags
SLRD_N : in slbit; -- fx2 read enable (act.low)
SLWR_N : in slbit; -- fx2 write enable (act.low)
SLOE_N : in slbit; -- fx2 output enable (act.low)
PKTEND_N : in slbit; -- fx2 packet end (act.low)
DATA : inout slv8 -- fx2 data lines
);
end fx2_2fifo_core;
architecture sim of fx2_2fifo_core is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
constant bufsize : positive := 1024;
constant datzero : slv(DATA'range) := (others=>'0');
type buf_type is array (0 to bufsize-1) of slv(DATA'range);
signal CLK30 : slbit := '0';
signal RXFIFO_DO : slv8 := (others=>'0');
signal RXFIFO_VAL : slbit := '0';
signal RXFIFO_HOLD : slbit := '0';
signal TXFIFO_DI : slv8 := (others=>'0');
signal TXFIFO_ENA : slbit := '0';
signal TXFIFO_BUSY : slbit := '0';
signal R_FLAG : slv4 := (others=>'0');
signal R_DATA : slv8 := (others=>'0');
-- added for debug purposes
signal R_rxbuf_rind : natural := 0;
signal R_rxbuf_wind : natural := 0;
signal R_rxbuf_nbyt : natural := 0;
signal R_txbuf_rind : natural := 0;
signal R_txbuf_wind : natural := 0;
signal R_txbuf_nbyt : natural := 0;
begin
RXFIFO : fifo_2c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => CLK30,
RESETW => '0',
RESETR => '0',
DI => RXDATA,
ENA => RXENA,
BUSY => RXBUSY,
DO => RXFIFO_DO,
VAL => RXFIFO_VAL,
HOLD => RXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
TXFIFO : fifo_2c_dram
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLKW => CLK30,
CLKR => CLK,
RESETW => '0',
RESETR => '0',
DI => TXFIFO_DI,
ENA => TXFIFO_ENA,
BUSY => TXFIFO_BUSY,
DO => TXDATA,
VAL => TXVAL,
HOLD => '0',
SIZEW => open,
SIZER => open
);
proc_ifclk: process
constant offset : Delay_length := 200 ns;
constant halfperiod_7 : Delay_length := 16700 ps;
constant halfperiod_6 : Delay_length := 16600 ps;
begin
CLK30 <= '0';
wait for offset;
loop
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_7;
CLK30 <= '1';
wait for halfperiod_6;
CLK30 <= '0';
wait for halfperiod_7;
CLK30 <= '1';
wait for halfperiod_7;
CLK30 <= '0';
wait for halfperiod_6;
end loop;
end process proc_ifclk;
proc_state: process (CLK30)
variable rxbuf : buf_type := (others=>datzero);
variable rxbuf_rind : natural := 0;
variable rxbuf_wind : natural := 0;
variable rxbuf_nbyt : natural := 0;
variable txbuf : buf_type := (others=>datzero);
variable txbuf_rind : natural := 0;
variable txbuf_wind : natural := 0;
variable txbuf_nbyt : natural := 0;
variable oline : line;
begin
if rising_edge(CLK30) then
RXFIFO_HOLD <= '0';
TXFIFO_ENA <= '0';
-- rxfifo -> rxbuf
if RXFIFO_VAL = '1' then
if rxbuf_nbyt < bufsize then
rxbuf(rxbuf_wind) := RXFIFO_DO;
rxbuf_wind := (rxbuf_wind + 1) mod bufsize;
rxbuf_nbyt := rxbuf_nbyt + 1;
else
RXFIFO_HOLD <= '1';
end if;
end if;
-- txbuf -> txfifo
if txbuf_nbyt>0 and TXFIFO_BUSY='0' then
TXFIFO_DI <= txbuf(txbuf_rind);
TXFIFO_ENA <= '1';
txbuf_rind := (txbuf_rind + 1) mod bufsize;
txbuf_nbyt := txbuf_nbyt - 1;
end if;
-- slrd cycle: rxbuf -> data
if SLRD_N = '0' then
if rxbuf_nbyt > 0 then
rxbuf_rind := (rxbuf_rind + 1) mod bufsize;
rxbuf_nbyt := rxbuf_nbyt - 1;
else
write(oline, string'("fx2_2fifo_core: SLRD_N=0 when rxbuf empty"));
writeline(output, oline);
end if;
end if;
R_DATA <= rxbuf(rxbuf_rind);
-- slwr cycle: data -> txbuf
if SLWR_N = '0' then
if txbuf_nbyt < bufsize then
txbuf(txbuf_wind) := DATA;
txbuf_wind := (txbuf_wind + 1) mod bufsize;
txbuf_nbyt := txbuf_nbyt + 1;
else
write(oline, string'("fx2_2fifo_core: SLWR_N=0 when txbuf full"));
writeline(output, oline);
end if;
end if;
-- prepare flags (note that FLAGs are act.low!)
R_FLAG <= (others=>'1');
-- FLAGA = indexed, PF
-- rx endpoint -> PF 'almost empty' at 3 bytes to go
if FIFO = c_rxfifo then
if rxbuf_nbyt < 4 then
R_FLAG(0) <= '0';
end if;
-- tx endpoint -> PF 'almost full' at 3 bytes to go
elsif FIFO = c_txfifo then
if txbuf_nbyt > bufsize-4 then
R_FLAG(0) <= '0';
end if;
end if;
-- FLAGB = EP6 FF
if txbuf_nbyt = bufsize then
R_FLAG(1) <= '0';
end if;
-- FLAGC = EP4 EF
if rxbuf_nbyt = 0 then
R_FLAG(2) <= '0';
end if;
-- FLAGD = EP8 FF
R_FLAG(3) <= '1';
-- added for debug purposes
R_rxbuf_rind <= rxbuf_rind;
R_rxbuf_wind <= rxbuf_wind;
R_rxbuf_nbyt <= rxbuf_nbyt;
R_txbuf_rind <= txbuf_rind;
R_txbuf_wind <= txbuf_wind;
R_txbuf_nbyt <= txbuf_nbyt;
end if;
end process proc_state;
IFCLK <= CLK30;
FLAG <= R_FLAG;
proc_data: process (SLOE_N, R_DATA)
begin
if SLOE_N = '1' then
DATA <= (others=>'Z');
else
DATA <= R_DATA;
end if;
end process proc_data;
end sim;
| gpl-3.0 | 6728561c75586ce46a6cac50c7d86ede | 0.514722 | 3.511278 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd | 1 | 11,681 | -- $Id: sys_tst_sram_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_n4 - syn
-- Description: test of nexys4 sram and its controller
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_4line_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_sp2c
-- tst_sram
-- bplib/nxcramlib/nx_cram_memctl_as
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_tst_sram_n4
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2018.3; ghdl 0.29-0.35 (ise 14.5-14.7 retired)
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-02-02 1108 2018.3 xc7a100t-1 1042 1550 24 5 530
-- 2019-02-02 1108 2017.2 xc7a100t-1 1043 1642 24 5 564
-- 2017-01-14 844 2016.4 xc7a100t-1 1042 1677 24 5 557 +sysmon
-- 2016-03-29 756 2015.4 xc7a100t-1 918 1207 24 5 428
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.7 use s7_cmt_1ce1ce
-- 2017-01-14 844 1.6 add sysmon_rbus
-- 2016-07-10 785 1.5.1 SWI(1) now XON
-- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support
-- 2016-04-02 758 1.4.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 1.4 use serport_2clock2
-- 2016-03-19 748 1.3.3 define rlink SYSID
-- 2015-04-11 666 1.3.2 rearrange XON handling
-- 2015-02-01 641 1.3.1 separate I_BTNRST_N
-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio
-- 2014-08-28 588 1.2 use new rlink v4 ifaceand 4 bit STAT
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from sys_tst_sram_n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.s3boardlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_n4 is -- top level
-- implements nexys4_cram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end sys_tst_sram_n4;
architecture syn of sys_tst_sram_n4 is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv22 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"05"; -- nexys4
constant sysid_vers : slv8 := x"00";
begin
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => x"ffe8")
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 22)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
MEM_RESET => MEM_RESET,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
CRAMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
SMRB : sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
RB_LAM(0) <= RB_LAM_TST;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
DSP_DP(7 downto 4) <= "0010";
DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
'0' & SER_MONI.abclkdiv_f;
-- setup unused outputs in nexys4
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | f18b7c02f42833fc94acdcea8f7ee937 | 0.498673 | 3.068295 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop2_n4d.vhd | 1 | 3,711 | -- $Id: tb_tst_serloop2_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n4d - sim
-- Description: Test bench for sys_tst_serloop2_n4d
--
-- Dependencies: simlib/simclk
-- xlib/sfs_gsim_core
-- sys_tst_serloop2_n4d [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n4d
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-01-04 838 1.0 Initial version (cloned from tb_tst_serloop2_n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
use work.sys_conf.all;
entity tb_tst_serloop2_n4d is
end tb_tst_serloop2_n4d;
architecture sim of tb_tst_serloop2_n4d is
signal CLK100 : slbit := '0';
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
GEN_CLKSYS : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide)
port map (
CLKIN => CLK100,
CLKFX => CLKH,
LOCKED => open
);
GEN_CLKSER : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLK100,
CLKFX => CLKS,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n4d
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => '1',
O_LED => open,
O_RGBLED0 => open,
O_RGBLED1 => open,
O_ANO_N => open,
O_SEG_N => open
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => RTS_N,
P0_CTS_N => CTS_N,
P1_RXD => open, -- port 1 unused for n4d !
P1_TXD => '0',
P1_RTS_N => '0',
P1_CTS_N => open,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
RTS_N <= O_RTS_N after delay_time;
I_CTS_N <= CTS_N after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | bcffe97c665a101a2104672ae0b15eac | 0.510105 | 3.155612 | false | false | false | false |
wfjm/w11 | rtl/bplib/arty/tb/tb_arty_core.vhd | 1 | 1,663 | -- $Id: tb_arty_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_arty_core - sim
-- Description: Test bench for arty - core device handling
--
-- Dependencies: -
--
-- To test: generic, any arty target
--
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0 Initial version (derived from tb_basys3_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_arty_core is
port (
I_SWI : out slv4; -- arty switches
I_BTN : out slv4 -- arty buttons
);
end tb_arty_core;
architecture sim of tb_arty_core is
signal R_SWI : slv4 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
| gpl-3.0 | d243e2dbe71c28809985395d095f241f | 0.552014 | 3.229126 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/serport_uart_rx_tb.vhd | 1 | 10,073 | -- $Id: serport_uart_rx_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
-- The uart expects CLKDIV+1 wide input bit symbols.
-- This implementation counts the number of 1's in the first CLKDIV clock
-- cycles, and checks in the last cycle of the symbol time whether the
-- number of 1's was > CLKDIV/2. This supresses short glitches nicely,
-- especially for larger clock dividers.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_rx_tb - sim
-- Description: serial port UART - receiver (SIM only!)
--
-- Dependencies: -
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-01-03 724 1.0 Initial version (copied from serport_uart_rx)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_rx_tb is -- serial port uart: receive part
generic (
CDWIDTH : positive := 13); -- clk divider width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end serport_uart_rx_tb;
architecture sim of serport_uart_rx_tb is
type state_type is (
s_idle, -- s_idle: idle
s_colb0, -- s_colb0: collect b0 (start bit)
s_endb0, -- s_endb0: finish b0 (start bit)
s_colbx, -- s_colbx: collect bx
s_endbx, -- s_endbx: finish bx
s_colb9, -- s_colb9: collect bx (stop bit)
s_endb9 -- s_endb9: finish bx (stop bit)
);
type regs_type is record
state : state_type; -- state
ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv(CDWIDTH downto 0); -- data '1' counter
bcnt : slv4; -- bit counter
sreg : slv8; -- input shift register
end record regs_type;
constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
ccntzero, -- ccnt
dcntzero, -- dcnt
(others=>'0'), -- bcnt
(others=>'0') -- sreg
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, CLKDIV, RXSD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable dbit : slbit := '0';
variable ld_ccnt : slbit := '0';
variable tc_ccnt : slbit := '0';
variable tc_bcnt : slbit := '0';
variable ld_dcnt : slbit := '0';
variable ld_bcnt : slbit := '0';
variable ce_bcnt : slbit := '0';
variable iact : slbit := '0';
variable ival : slbit := '0';
variable ierr : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
dbit := '0';
ld_ccnt := '0';
tc_ccnt := '0';
tc_bcnt := '0';
ld_dcnt := '0';
ld_bcnt := '0';
ce_bcnt := '0';
iact := '1';
ival := '0';
ierr := '0';
if unsigned(r.ccnt) = 0 then
tc_ccnt := '1';
end if;
if unsigned(r.bcnt) = 9 then
tc_bcnt := '1';
end if;
if unsigned(r.dcnt) > unsigned("00" & CLKDIV(CDWIDTH-1 downto 1)) then
dbit := '1';
end if;
case r.state is
when s_idle => -- s_idle: idle ----------------------
iact := '0';
ld_dcnt := '1'; -- always keep dcnt in reset
if RXSD = '0' then -- if start bit seen
if tc_ccnt = '1' then
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- start next bit
ce_bcnt := '1';
else
n.state := s_colb0; -- collect b0
end if;
else -- otherwise
ld_ccnt := '1'; -- keep all counters in reset
ld_bcnt := '1';
end if;
when s_colb0 => -- s_colb0: collect b0 (start bit) ---
if tc_ccnt = '1' then -- last cycle of b0 ?
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- "
ce_bcnt := '1';
else -- continue in b0 ?
if dbit='1' and RXSD='1' then -- too many 1's ?
n.state := s_idle; -- abort to idle
ld_dcnt := '1'; -- put counters in reset
ld_ccnt := '1';
ld_bcnt := '1';
end if;
end if;
when s_endb0 => -- s_endb0: finish b0 (start bit) ---
ld_dcnt := '1'; -- start next bit
if dbit = '1' then -- was it a 1 ?
n.state := s_idle; -- abort to idle
ld_ccnt := '1'; -- put counters in reset
ld_bcnt := '1';
else
if tc_ccnt = '1' then -- last cycle of bx ?
n.state := s_endbx; -- finish bx
ld_ccnt := '1';
ce_bcnt := '1';
else -- continue in b0 ?
n.state := s_colbx; -- collect bx
end if;
end if;
when s_colbx => -- s_colbx: collect bx ---------------
if tc_ccnt = '1' then -- last cycle of bx ?
n.state := s_endbx; -- finish bx
ld_ccnt := '1';
ce_bcnt := '1';
end if;
when s_endbx => -- s_endbx: finish bx ---------------
ld_dcnt := '1'; -- start next bit
n.sreg := dbit & r.sreg(7 downto 1);
if tc_ccnt = '1' then -- last cycle of bx ?
if tc_bcnt = '1' then
n.state := s_endb9; -- finish b9
ld_bcnt := '1'; -- and wrap bcnt
else
n.state := s_endbx; -- finish bx
ce_bcnt := '1';
end if;
ld_ccnt := '1';
else -- continue in bx ?
if tc_bcnt = '1' then
n.state := s_colb9; -- collect b9
else
n.state := s_colbx; -- collect bx
end if;
end if;
when s_colb9 => -- s_colb9: collect bx (stop bit) ----
if tc_ccnt = '1' then -- last cycle of b9 ?
n.state := s_endb9; -- finish b9
ld_ccnt := '1'; -- "
ld_bcnt := '1'; -- and wrap bcnt
else -- continue in b9 ?
if dbit='1' and RXSD='1' then -- already enough 1's ?
n.state := s_idle; -- finish to idle
ld_dcnt := '1'; -- put counters in reset
ld_ccnt := '1';
ld_bcnt := '1';
ival := '1';
end if;
end if;
when s_endb9 => -- s_endb9: finish bx (stop bit) ----
ld_dcnt := '1'; -- start next bit
if dbit = '1' then -- was it a valid stop bit ?
ival := '1';
else
ierr := '1';
end if;
if RXSD = '1' then -- line in idle state ?
n.state := s_idle; -- finish to idle state
ld_ccnt := '1'; -- and put counters in reset
ld_bcnt := '1'; -- "
else
if tc_ccnt = '1' then -- last cycle of b9 ?
n.state := s_endb0; -- finish b0
ld_ccnt := '1'; -- "
ce_bcnt := '1';
else -- continue in b0 ?
n.state := s_colb0; -- collect bx
end if;
end if;
when others => null; -- -----------------------------------
end case;
if RESET = '1' then -- RESET seen
ld_ccnt := '1'; -- keep all counters in reset
ld_dcnt := '1';
ld_bcnt := '1';
n.state := s_idle;
end if;
if ld_ccnt = '1' then -- implement ccnt
n.ccnt := CLKDIV;
else
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
if ld_dcnt = '1' then -- implement dcnt
n.dcnt(CDWIDTH downto 1) := (others=>'0');
n.dcnt(0) := RXSD;
else
if RXSD = '1' then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
end if;
if ld_bcnt = '1' then -- implement bcnt
n.bcnt := (others=>'0');
else
if ce_bcnt = '1' then
n.bcnt := slv(unsigned(r.bcnt) + 1);
end if;
end if;
N_REGS <= n;
RXDATA <= r.sreg;
RXACT <= iact;
RXVAL <= ival;
RXERR <= ierr;
end process proc_next;
end sim;
| gpl-3.0 | 7260d9a6f5200d2a5113677f0a64b56e | 0.418942 | 3.950196 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/xlib.vhd | 1 | 11,313 | -- $Id: xlib.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: xlib
-- Description: Xilinx specific components
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.1.2 add bufg_unisim
-- 2018-11-18 1072 1.1.1 add s7_cmt_sfs_3 and s7_cmt_sfs_2
-- 2018-11-03 1064 1.1 add sfs_gsim_core
-- 2016-04-02 758 1.0.11 add usr_access_unisim
-- 2013-10-06 538 1.0.10 add s6_cmt_sfs
-- 2013-09-28 535 1.0.9 add s7_cmt_sfs
-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
-- 2008-05-23 149 1.0.4 add iob_io(_gen)
-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);
-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)
-- 2007-12-16 101 1.0.1 add INIT generic ports
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package xlib is
component iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end component;
component iob_reg_i_gen is -- registered IOB, input, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slv(DWIDTH-1 downto 0); -- input data
PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_reg_o is -- registered IOB, output
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end component;
component iob_reg_o_gen is -- registered IOB, output, vector
generic (
DWIDTH : positive := 16; -- data port width
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slv(DWIDTH-1 downto 0); -- output data
PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_reg_io is -- registered IOB, in/output
generic (
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slbit; -- input data (read from pad)
DO : in slbit; -- output data (write to pad)
PAD : inout slbit -- i/o pad
);
end component;
component iob_reg_io_gen is -- registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_io is -- un-registered IOB, in/output
generic (
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
OE : in slbit; -- output enable
DI : out slbit; -- input data (read from pad)
DO : in slbit; -- output data (write to pad)
PAD : inout slbit -- i/o pad
);
end component;
component iob_oddr2_simple is -- DDR2 output I/O pad
generic (
ALIGN : string := "NONE"; -- ddr_alignment
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO0 : in slbit; -- output data
DO1 : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end component;
component iob_io_gen is -- un-registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component iob_keeper is -- keeper for IOB
port (
PAD : inout slbit -- i/o pad
);
end component;
component iob_keeper_gen is -- keeper for IOB, vector
generic (
DWIDTH : positive := 16); -- data port width
port (
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end component;
component dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 2; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end component;
component s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component s7_cmt_sfs_2 is -- 7-Series CMT for dual freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT0_DIVIDE : positive := 1; -- output 0 divide
OUT1_DIVIDE : positive := 1; -- output 1 divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKOUT0 : out slbit; -- clock output 0
CLKOUT1 : out slbit; -- clock output 1
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component s7_cmt_sfs_3 is -- 7-Series CMT for tripple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT0_DIVIDE : positive := 1; -- output 0 divide
OUT1_DIVIDE : positive := 1; -- output 1 divide
OUT2_DIVIDE : positive := 1; -- output 2 divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKOUT0 : out slbit; -- clock output 0
CLKOUT1 : out slbit; -- clock output 1
CLKOUT2 : out slbit; -- clock output 2
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component sfs_gsim_core is -- frequency synthesis for simulation
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1); -- output divide
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- clkin locked
);
end component;
component usr_access_unisim is -- wrapper for USR_ACCESS family
port (
DATA : out slv32 -- usr_access register value
);
end component;
component bufg_unisim is -- wrapper for bufg
port (
O : out std_ulogic; -- input
I : in std_ulogic -- output
);
end component;
end package xlib;
| gpl-3.0 | c83e606d1c1e862cf43ced1b631327dd | 0.503138 | 3.795035 | false | false | false | false |
abcsds/Micros | RS232Read/hex_7seg.vhd | 2 | 1,530 | library IEEE;
use IEEE.std_logic_1164.all;
entity hex_7seg is
port(
RST : in std_logic;
CLK : in std_logic;
EOR : in std_logic;
Q : in std_logic_vector(3 downto 0);
S : out std_logic_vector(6 downto 0)
);
end hex_7seg;
architecture Tabla of Hex_7seg is
signal Qp, Qn : std_logic_vector(6 downto 0);
begin
SEC: process(RST,CLK,Qn)
begin
if(RST= '1')then
Qp<= (others=>'0');
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process SEC;
COMB: process(Q,EOR)
begin
if(EOR= '1')then
Qn<= Qp;
else
case Q is
when "0000" => Qn <= NOT("1111110");
when "0001" => Qn <= NOT("0110000");
when "0010" => Qn <= NOT("1101101");
when "0011" => Qn <= NOT("1111001");
when "0100" => Qn <= NOT("0110011");
when "0101" => Qn <= NOT("1011011");
when "0110" => Qn <= NOT("1011111");
when "0111" => Qn <= NOT("1110010");
when "1000" => Qn <= NOT("1111111");
when "1001" => Qn <= NOT("1111011");
when "1010" => Qn <= NOT("1110111");
when "1011" => Qn <= NOT("0011111");
when "1100" => Qn <= NOT("1001110");
when "1101" => Qn <= NOT("0111101");
when "1110" => Qn <= NOT("0111101");
when "1111" => Qn <= NOT("1001111");
when others => Qn <= NOT("1000111");
end case;
end if;
end process COMB;
end tabla;
| gpl-3.0 | 5e32c8eb2dd2f70bd205b089cd5d9521 | 0.47451 | 3.276231 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vhd | 1 | 12,889 | -- $Id: sys_tst_sram_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_n4d - syn
-- Description: test of nexys4d ddr and its mig controller
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_4line_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_sp2c
-- tst_sram
-- bplib/nexyx4d/sramif_mig_nexys4d
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_tst_sram_n4d
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1 4408 4197 608 5 1761
-- 2019-08-10 1201 2019.1 xc7a100t-1 4409 4606 656 5 1875
-- 2019-02-02 1108 2018.3 xc7a100t-1 4408 4606 656 5 1895
-- 2019-02-02 1108 2017.2 xc7a100t-1 4403 4900 657 5 1983
-- 2019-01-02 1101 2017.2 xc7a100t-1 4403 4900 640 5 1983
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.1.1 use bufg_unisim
-- 2019-08-10 1201 1.1 use 100 MHz MIG SYS_CLK
-- 2019-01-02 1101 1.0 Initial version
-- 2018-12-30 1099 0.1 First draft (derived from sys_tst_sram_n4/arty)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.s3boardlib.all;
use work.miglib.all;
use work.miglib_nexys4d.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_n4d is -- top level
-- implements nexys4d_mig_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end sys_tst_sram_n4d;
architecture syn of sys_tst_sram_n4d is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG
signal GBL_RESET : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_RESET_RRI : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"08"; -- nexys4d
constant sysid_vers : slv8 := x"00";
begin
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 12, -- vco 1200 MHz
CLK2_OUTDIV => 12, -- mig sys 100.0 MHz (unused)
CLK3_OUTDIV => 6, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => open,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLKMIG_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK100_BUF,
DI => LOCKED,
DO => LOCKED_CLKMIG
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => x"ffe8")
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 18)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
MEM_RESET => MEM_RESET_RRI,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR(17 downto 0), -- ?? FIXME ?? allow AWIDTH=20
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM_ADDR(19 downto 18) <= (others=>'0'); --?? FIXME ?? allow AWIDTH=20
MEM_RESET <= not LOCKED_CLKMIG or MEM_RESET_RRI;
MEMCTL: sramif_mig_nexys4d -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLK100_BUF,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR2_DQ => DDR2_DQ,
DDR2_DQS_P => DDR2_DQS_P,
DDR2_DQS_N => DDR2_DQS_N,
DDR2_ADDR => DDR2_ADDR,
DDR2_BA => DDR2_BA,
DDR2_RAS_N => DDR2_RAS_N,
DDR2_CAS_N => DDR2_CAS_N,
DDR2_WE_N => DDR2_WE_N,
DDR2_CK_P => DDR2_CK_P,
DDR2_CK_N => DDR2_CK_N,
DDR2_CKE => DDR2_CKE,
DDR2_CS_N => DDR2_CS_N,
DDR2_DM => DDR2_DM,
DDR2_ODT => DDR2_ODT
);
SMRB : sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
RB_LAM(0) <= RB_LAM_TST;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
DSP_DP(7 downto 4) <= "0010";
DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
'0' & SER_MONI.abclkdiv_f;
-- setup unused outputs in nexys4
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 91a41be028de60aa7642e31f42845a88 | 0.489177 | 3.112533 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd | 1 | 4,188 | -- $Id: tb_tst_serloop2_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop2_n2 - sim
-- Description: Test bench for sys_tst_serloop2_n2
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop2_n2 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop2_n2
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop2_n2 is
end tb_tst_serloop2_n2;
architecture sim of tb_tst_serloop2_n2 is
signal CLK50 : slbit := '0';
signal CLKS : slbit := '0';
signal CLKH : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
DCM_H : dcm_sfs
generic map (
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 4,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKH,
LOCKED => open
);
UUT : entity work.sys_tst_serloop2_n2
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FLA_CE_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKH,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | b7c9e25cd8b2227c57ca2435693bba71 | 0.504298 | 3.010784 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys3/sys_tst_sram_n3.vhd | 1 | 10,026 | -- $Id: sys_tst_sram_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_n3 - syn
-- Description: test of nexys3 sram and its controller
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio
-- vlib/rlink/rlink_sp1c
-- tst_sram
-- bplib/nxcramlib/nx_cram_memctl_as
--
-- Test bench: tb/tb_tst_sram_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-12-20 614 14.7 131013 xc6slx16-2 922 1574 48 574 t 9.6 ns
-- 2014-08-13 581 14.7 131013 xc6slx16-2 765 1261 32 441 t 9.6 ns
-- 2011-12-21 442 13.4 O40d xc6slx16-2 722 1367 32 506 t 9.6 ns
-- 2011-11-27 433 13.4 O40d xc6slx16-2 699 1194 20 406 t 8.9 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-10 785 1.5.1 SWI(1) now XON; SWI(0) now portsel
-- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support
-- 2016-03-19 748 1.4.2 define rlink SYSID
-- 2015-04-11 666 1.4.1 rearrange XON handling
-- 2014-08-28 588 1.4 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-21 442 1.1.1 use rlink_sp1c
-- 2011-12-03 435 1.1 use int&ext serport and bp_rs232_2l4l_iob
-- 2011-11-27 433 1.0 Initial version (derived from sys_tst_sram_n2)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_sram_n3;
architecture syn of sys_tst_sram_n3 is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv22 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"03"; -- nexys3
constant sysid_vers : slv8 := x"00";
begin
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio
generic map (
BWIDTH => 5)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => x"ffe8")
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 22)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
MEM_RESET => MEM_RESET,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
CRAMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => sys_conf_memctl_read0delay, -- was 2 for 50 MHz
READ1DELAY => sys_conf_memctl_read1delay, -- was 2 "
WRITEDELAY => sys_conf_memctl_writedelay) -- was 3 "
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
RB_SRES <= RB_SRES_TST; -- can be sres_or later...
RB_LAM(0) <= RB_LAM_TST;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
end syn;
| gpl-3.0 | 9daee4ca100d10e6a2bab2d99f17fa2b | 0.490126 | 3.051126 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_02300_bad.vhd | 1 | 2,817 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-15 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_02300_bad.vhd
-- File Creation date : 2015-04-15
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Preservation of clock name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
--CODE
entity CNE_02300_bad is
port (
i_Clk : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_02300_bad;
architecture Behavioral of CNE_02300_bad is
signal Clock_tmp : std_logic;
begin
Clock_tmp <= i_Clk;
DFF1:DFlipFlop
port map (
i_Clock => Clock_tmp,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE | gpl-3.0 | e918b0f655e01346f3deb308802bbacd | 0.475328 | 4.450237 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/tb/tbd_fifo_2c_dram2.vhd | 1 | 2,332 | -- $Id: tbd_fifo_2c_dram2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_fifo_2c_dram2 - syn
-- Description: Wrapper for fifo_2c_dram2 to avoid records & generics. It
-- has a port interface which will not be modified by synthesis
-- (no records, no generic port).
--
-- Dependencies: fifo_2c_dram2
--
-- To test: fifo_2c_dram2
--
-- Target Devices: generic
--
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-28 106 1.0 Initial version (tbd_fifo_2c_dram2)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity tbd_fifo_2c_dram2 is -- fifo, 2 clock, dram based [tb design]
-- generic: AWIDTH=4; DWIDTH=16
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- reset (synchronous with CLKW)
RESETR : in slbit; -- reset (synchronous with CLKR)
DI : in slv16; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZEW : out slv4; -- number slots to write (synch w/ CLKW)
SIZER : out slv4 -- number slots to read (synch w/ CLKR)
);
end tbd_fifo_2c_dram2;
architecture syn of tbd_fifo_2c_dram2 is
begin
FIFO : fifo_2c_dram2
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
end syn;
| gpl-3.0 | 2cc2023214cae865bde08f4435df14eb | 0.477273 | 3.873754 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd | 1 | 6,908 | -- $Id: tst_serloop_hiomap.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.2 rename serport stat->moni port
-- 2011-11-16 426 1.0.1 setup leds and dps
-- 2011-11-05 420 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3): -- unused --
-- (2): -- unused --
-- (1): load enables from SWI(7:4)
-- SWI(7) -> ENAFTDI
-- SWI(6) -> ENATHROTTLE
-- SWI(5) -> ENAESC
-- SWI(4) -> ENAXON
-- (0): reset state [!! decoded by top level design !!]
--
-- SWI(7:4) select display or enable pattern (when BTN(1) pressed)
-- (3) -- unused --
-- (2:1): mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
-- SWI(0) 0 -> main board RS232 port
-- 1 -> Pmod1 RS232 port
--
-- LED(7) enaesc
-- (6) enaxon
-- (5) rxfecnt > 0 (frame error)
-- (4) rxoecnt > 0 (overrun error)
-- (3) rxsecnt > 0 (sequence error)
-- (2) abact (shows ab activity)
-- (1) (not rxok) or (not txok) (shows back pressure)
-- (0) rxact or txact (shows activity)
--
-- DSP data as selected by SWI(7:4)
-- 0000 -> rxfecnt
-- 0001 -> rxoecnt
-- 0010 -> rxsecnt
-- 0100 -> rxcnt.l
-- 0101 -> rxcnt.h
-- 0110 -> txcnt.l
-- 0111 -> txcnt.h
-- 1000 -> rxokcnt
-- 1001 -> txokcnt
-- 1010 -> rxuicnt,rxuidat
-- 1111 -> abclkdiv
--
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back pressure)
-- (0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_serloop_hiomap;
architecture syn of tst_serloop_hiomap is
type regs_type is record
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
dspdat : slv16; -- display data
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- enaxon,enaesc,enathrottle,enaftdi
(others=>'0') -- dspdat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HIO_STAT, SER_MONI, SWI, BTN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
-- handle BTN(1) "load enables" press
if BTN(1) = '1' then
n.enaxon := SWI(4);
n.enaesc := SWI(5);
n.enathrottle := SWI(6);
n.enaftdi := SWI(7);
end if;
-- setup tester controls
icntl.mode := SWI(2 downto 1);
icntl.enaxon := r.enaxon;
icntl.enaesc := r.enaesc;
icntl.enathrottle := r.enathrottle;
icntl.enaftdi := r.enaftdi;
-- setup leds
iled(7) := icntl.enaesc;
iled(6) := icntl.enaxon;
if unsigned(HIO_STAT.rxfecnt) > 0 then iled(5) := '1'; end if;
if unsigned(HIO_STAT.rxoecnt) > 0 then iled(4) := '1'; end if;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(3) := '1'; end if;
iled(2) := SER_MONI.abact;
iled(1) := (not SER_MONI.rxok) or (not SER_MONI.txok);
iled(0) := SER_MONI.rxact or SER_MONI.txact;
-- setup display data
case SWI(7 downto 4) is
when "0000" => idat := HIO_STAT.rxfecnt;
when "0001" => idat := HIO_STAT.rxoecnt;
when "0010" => idat := HIO_STAT.rxsecnt;
when "0100" => idat := HIO_STAT.rxcnt(15 downto 0);
when "0101" => idat := HIO_STAT.rxcnt(31 downto 16);
when "0110" => idat := HIO_STAT.txcnt(15 downto 0);
when "0111" => idat := HIO_STAT.txcnt(31 downto 16);
when "1000" => idat := HIO_STAT.rxokcnt;
when "1001" => idat := HIO_STAT.txokcnt;
when "1010" => idat := HIO_STAT.rxuicnt & HIO_STAT.rxuidat;
when "1111" => idat := SER_MONI.abclkdiv;
when others => null;
end case;
n.dspdat := idat;
-- setup display decimal points
idp(3) := not SER_MONI.txok; -- tx back pressure
idp(2) := SER_MONI.txact; -- tx activity
idp(1) := not SER_MONI.rxok; -- rx back pressure
idp(0) := SER_MONI.rxact; -- rx activity
N_REGS <= n;
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;
| gpl-3.0 | 6f5f3841d13873a5ae88da0e4a569a6d | 0.493631 | 3.586708 | false | false | false | false |
wfjm/w11 | rtl/vlib/comlib/tb/tbd_cdata2byte.vhd | 1 | 2,817 | -- $Id: tbd_cdata2byte.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_cdata2byte - syn
-- Description: Wrapper for cdata2byte + byte2cdata.
--
-- Dependencies: cdata2byte
-- byte2cdata
--
-- To test: cdata2byte
-- byte2cdata
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-10-18 597 14.7 xc6slx16 25 67 0 28 s 3.56
--
-- Tool versions: xst 14.7; ghdl 0.31
-- Revision History:
-- Date Rev Version Comment
-- 2014-10-18 597 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
entity tbd_cdata2byte is -- cdata2byte + byte2cdata [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
C2B_ESCXON : in slbit; -- c2b: enable xon/xoff escaping
C2B_ESCFILL : in slbit; -- c2b: enable fill escaping
C2B_DI : in slv9; -- c2b: input data; bit 8 = comma flag
C2B_ENA : in slbit; -- c2b: input data enable
C2B_BUSY : out slbit; -- c2b: input data busy
C2B_DO : out slv8; -- c2b: output data
C2B_VAL : out slbit; -- c2b: output data valid
B2C_BUSY : out slbit; -- b2c: input data busy
B2C_DO : out slv9; -- b2c: output data; bit 8 = comma flag
B2C_VAL : out slbit; -- b2c: output data valid
B2C_HOLD : in slbit -- b2c: output data hold
);
end tbd_cdata2byte;
architecture syn of tbd_cdata2byte is
signal C2B_DO_L : slv8 := (others=>'0');
signal C2B_VAL_L : slbit := '0';
signal B2C_BUSY_L : slbit := '0';
begin
C2B : cdata2byte
port map (
CLK => CLK,
RESET => RESET,
ESCXON => C2B_ESCXON,
ESCFILL => C2B_ESCFILL,
DI => C2B_DI,
ENA => C2B_ENA,
BUSY => C2B_BUSY,
DO => C2B_DO_L,
VAL => C2B_VAL_L,
HOLD => B2C_BUSY_L
);
B2C : byte2cdata
port map (
CLK => CLK,
RESET => RESET,
DI => C2B_DO_L,
ENA => C2B_VAL_L,
ERR => '0',
BUSY => B2C_BUSY_L,
DO => B2C_DO,
VAL => B2C_VAL,
HOLD => B2C_HOLD
);
C2B_DO <= C2B_DO_L;
C2B_VAL <= C2B_VAL_L;
B2C_BUSY <= B2C_BUSY_L;
end syn;
| gpl-3.0 | c58584830d60fcad9dc5bd28fb688dc0 | 0.482073 | 3.158072 | false | false | false | false |
nsensfel/tabellion | data/test/combinational_processes/invalid.vhd | 1 | 1,533 | library IEEE;
use IEEE.std_logic_1164.all;
entity invalid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of invalid is
signal s0, s1, s2, s3 : std_logic;
begin
-- Missing:
-- - s1 in sensitivity list.
process (s0, s3)
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
-- Missing:
-- - s1 in sensitivity list.
-- - s0 in sensitivity list.
process (ip3)
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
end case;
end process;
-- Missing
-- - op1 not defined when (s1 != '0').
process (s0, s1)
begin
op2 <= '0';
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others=>
op0 <= s1;
op2 <= '1';
end case;
end process;
-- Missing
-- - op0 not defined when ((s1 == '0') && (s2 = '0')).
process (s0, s1, s2)
begin
op2 <= '0';
case s1 is
when '0' =>
if (s2 = '0')
then
op0 <= s0;
else
op1 <= s1;
end if;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
end;
| apache-2.0 | 08867bc0daa2c075fa09b3394f02efa6 | 0.411611 | 3.213836 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/tb/tbd_rlink_sp1c.vhd | 1 | 9,045 | -- $Id: tbd_rlink_sp1c.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_rlink_sp1c - syn
-- Description: Wrapper for rlink_core plus rlink_serport with an interface
-- compatible to the rlink_core only module.
-- NOTE: this implementation is a hack, should be redone
-- using configurations.
--
-- Dependencies: tbu_rlink_sp1c [UUT]
-- serport_uart_tx
-- serport_uart_rx
-- byte2cdata
-- cdata2byte
-- simlib/simclkcnt
--
-- To test: rlink_sp1c
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-08-28 588 4.0 use new rlink v4 iface and 4 bit STAT
-- 2011-12-23 444 3.2 use simclkcnt instead of simbus global
-- 2011-12-22 442 3.1 renamed and retargeted to tbu_rlink_sp1c
-- 2011-11-19 427 3.0.5 now numeric_std clean
-- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0;
-- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_;
-- 2010-12-24 347 3.0.2 rename: CP_*->RL->*
-- 2010-12-22 346 3.0.1 removed proc_moni, use .rlmon cmd in test bench
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas)
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again
-- 2010-04-03 274 2.2 add CE_USEC
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch
-- name to switch core/serport;
-- use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.comlib.all;
use work.serportlib.all;
use work.simlib.all;
use work.simbus.all;
entity tbd_rlink_sp1c is -- rlink_sp1c tb design
-- implements tbd_rlink_gen
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv16; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end entity tbd_rlink_sp1c;
architecture syn of tbd_rlink_sp1c is
constant CDWIDTH : positive := 13;
constant c_cdinit : natural := 0; -- NOTE: change in tbu_rlink_sp1c !!
signal RRI_RXSD : slbit := '0';
signal RRI_TXSD : slbit := '0';
signal RTS_N : slbit := '0';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH));
signal CLK_CYCLE : integer := 0;
component tbu_rlink_sp1c is -- rlink core+serport combo
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv16; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end component;
begin
TBU : tbu_rlink_sp1c
port map (
CLK => CLK,
CE_INT => CE_INT,
CE_USEC => CE_USEC,
CE_MSEC => '1',
RESET => RESET,
RXSD => RRI_RXSD,
TXSD => RRI_TXSD,
CTS_N => '0',
RTS_N => RTS_N,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
UARTRX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RRI_TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => open,
RXACT => RXACT
);
UARTTX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => RRI_RXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
TXRXACT <= RXACT or TXBUSY;
B2CD : byte2cdata -- byte stream -> 9bit comma,data
port map (
CLK => CLK,
RESET => RESET,
DI => RXDATA,
ENA => RXVAL,
ERR => '0',
BUSY => open,
DO => RL_DO,
VAL => RL_VAL,
HOLD => RL_HOLD
);
CD2B : cdata2byte -- 9bit comma,data -> byte stream
port map (
CLK => CLK,
RESET => RESET,
ESCXON => '0',
ESCFILL => '0',
DI => RL_DI,
ENA => RL_ENA,
BUSY => RL_BUSY,
DO => TXDATA,
VAL => TXENA,
HOLD => TXBUSY
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
proc_moni: process
variable oline : line;
variable rts_last : slbit := '0';
variable ncycle : integer := 0;
begin
loop
wait until rising_edge(CLK); -- check at end of clock cycle
if RTS_N /= rts_last then
writetimestamp(oline, CLK_CYCLE, ": rts ");
write(oline, string'(" RTS_N "));
write(oline, rts_last, right, 1);
write(oline, string'(" -> "));
write(oline, RTS_N, right, 1);
write(oline, string'(" after "));
write(oline, ncycle, right, 5);
write(oline, string'(" cycles"));
writeline(output, oline);
rts_last := RTS_N;
ncycle := 0;
end if;
ncycle := ncycle + 1;
end loop;
end process proc_moni;
end syn;
| gpl-3.0 | 4d0fa9715b429b7ea4bd6862a6bf3fbd | 0.505804 | 3.570865 | false | false | false | false |
wfjm/w11 | rtl/bplib/arty/migui_arty_gsim.vhd | 1 | 5,634 | -- $Id: migui_arty_gsim.vhd 1201 2019-08-10 16:51:22Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: migui_arty - sim
-- Description: MIG generated for arty - simple simulator
--
-- Dependencies: bplib/mig/migui_core_gsim
-- Test bench: tb_tst_sram_arty
-- Target Devices: arty board
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-25 1093 1.0 Initial version
-- 2018-11-17 1071 0.1 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.miglib.all;
use work.miglib_arty.all;
entity migui_arty is -- MIG generated for arty
port (
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1; -- dram: on-die termination
APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
APP_CMD : in slv3; -- MIGUI command
APP_EN : in slbit; -- MIGUI command enable
APP_WDF_DATA : in slv(mig_dwidth-1 downto 0);-- MIGUI write data
APP_WDF_END : in slbit; -- MIGUI write end
APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : in slbit; -- MIGUI refresh request
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI inital calibration complete
SYS_CLK_I : in slbit; -- MIGUI system clock
CLK_REF_I : in slbit; -- MIGUI reference clock
DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
SYS_RST : in slbit -- MIGUI system reset
);
end migui_arty;
architecture sim of migui_arty is
begin
-- On Arty we have
-- SYS_CLK_I 166.6 Mhz
-- controller 333.3 MHz
-- UI_CLK 83.3 MHz (4:1)
-- therefore for simulation
-- f_vco 1000 MHz
-- --> mul 6 (f_vco/SYS_CLK)
-- --> div 12 (f_vco/UI_CLK)
MIG_SIM : migui_core_gsim
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth,
SAWIDTH => 24,
CLKMUI_MUL => 6,
CLKMUI_DIV => 12)
port map (
SYS_CLK => SYS_CLK_I,
SYS_RST => SYS_RST,
UI_CLK => UI_CLK,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK
);
DDR3_DQ <= (others=>'Z');
DDR3_DQS_P <= (others=>'Z');
DDR3_DQS_N <= (others=>'Z');
DDR3_ADDR <= (others=>'0');
DDR3_BA <= (others=>'0');
DDR3_RAS_N <= '1';
DDR3_CAS_N <= '1';
DDR3_WE_N <= '1';
DDR3_RESET_N <= '1';
DDR3_CK_P <= (others=>'0');
DDR3_CK_N <= (others=>'1');
DDR3_CKE <= (others=>'0');
DDR3_CS_N <= (others=>'1');
DDR3_DM <= (others=>'0');
DDR3_ODT <= (others=>'0');
APP_SR_ACTIVE <= '0';
end sim;
| gpl-3.0 | e26031ec5379b7f9c651e706a76851cc | 0.49077 | 3.319976 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/UART6_RX.vhdl | 1 | 17,215 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_rx6 is
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_rx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_rx6 - constrained
--
architecture rtl of uart_rx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_rx6
--
-------------------------------------------------------------------------------------------
--
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sample_value : std_logic;
signal sample : std_logic;
signal sample_dly_value : std_logic;
signal sample_dly : std_logic;
signal stop_bit_value : std_logic;
signal stop_bit : std_logic;
signal data_value : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal run_value : std_logic;
signal run : std_logic;
signal start_bit_value : std_logic;
signal start_bit : std_logic;
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal div_carry : std_logic;
signal sample_input_value : std_logic;
signal sample_input : std_logic;
signal buffer_write_value : std_logic;
signal buffer_write : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_rx6_1";
attribute hblknm of pointer3_flop : label is "uart_rx6_1";
attribute hblknm of pointer2_lut : label is "uart_rx6_1";
attribute hblknm of pointer2_flop : label is "uart_rx6_1";
attribute hblknm of pointer01_lut : label is "uart_rx6_1";
attribute hblknm of pointer1_flop : label is "uart_rx6_1";
attribute hblknm of pointer0_flop : label is "uart_rx6_1";
attribute hblknm of data_present_lut : label is "uart_rx6_1";
attribute hblknm of data_present_flop : label is "uart_rx6_1";
--
attribute hblknm of data01_lut : label is "uart_rx6_2";
attribute hblknm of data0_flop : label is "uart_rx6_2";
attribute hblknm of data1_flop : label is "uart_rx6_2";
attribute hblknm of data23_lut : label is "uart_rx6_2";
attribute hblknm of data2_flop : label is "uart_rx6_2";
attribute hblknm of data3_flop : label is "uart_rx6_2";
attribute hblknm of data45_lut : label is "uart_rx6_2";
attribute hblknm of data4_flop : label is "uart_rx6_2";
attribute hblknm of data5_flop : label is "uart_rx6_2";
attribute hblknm of data67_lut : label is "uart_rx6_2";
attribute hblknm of data6_flop : label is "uart_rx6_2";
attribute hblknm of data7_flop : label is "uart_rx6_2";
--
attribute hblknm of div01_lut : label is "uart_rx6_3";
attribute hblknm of div23_lut : label is "uart_rx6_3";
attribute hblknm of div0_flop : label is "uart_rx6_3";
attribute hblknm of div1_flop : label is "uart_rx6_3";
attribute hblknm of div2_flop : label is "uart_rx6_3";
attribute hblknm of div3_flop : label is "uart_rx6_3";
attribute hblknm of sample_input_lut : label is "uart_rx6_3";
attribute hblknm of sample_input_flop : label is "uart_rx6_3";
attribute hblknm of full_lut : label is "uart_rx6_3";
--
attribute hblknm of sample_lut : label is "uart_rx6_4";
attribute hblknm of sample_flop : label is "uart_rx6_4";
attribute hblknm of sample_dly_flop : label is "uart_rx6_4";
attribute hblknm of stop_bit_lut : label is "uart_rx6_4";
attribute hblknm of stop_bit_flop : label is "uart_rx6_4";
attribute hblknm of buffer_write_flop : label is "uart_rx6_4";
attribute hblknm of start_bit_lut : label is "uart_rx6_4";
attribute hblknm of start_bit_flop : label is "uart_rx6_4";
attribute hblknm of run_lut : label is "uart_rx6_4";
attribute hblknm of run_flop : label is "uart_rx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_rx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_rx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
sample_lut: LUT6_2
generic map (INIT => X"CCF00000AACC0000")
port map( I0 => serial_in,
I1 => sample,
I2 => sample_dly,
I3 => en_16_x_baud,
I4 => '1',
I5 => '1',
O5 => sample_value,
O6 => sample_dly_value);
sample_flop: FD
port map ( D => sample_value,
Q => sample,
C => clk);
sample_dly_flop: FD
port map ( D => sample_dly_value,
Q => sample_dly,
C => clk);
stop_bit_lut: LUT6_2
generic map (INIT => X"CAFFCAFF0000C0C0")
port map( I0 => stop_bit,
I1 => sample,
I2 => sample_input,
I3 => run,
I4 => data(0),
I5 => '1',
O5 => buffer_write_value,
O6 => stop_bit_value);
buffer_write_flop: FD
port map ( D => buffer_write_value,
Q => buffer_write,
C => clk);
stop_bit_flop: FD
port map ( D => stop_bit_value,
Q => stop_bit,
C => clk);
data01_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(0),
O6 => data_value(1));
data0_flop: FD
port map ( D => data_value(0),
Q => data(0),
C => clk);
data1_flop: FD
port map ( D => data_value(1),
Q => data(1),
C => clk);
data23_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(2),
I1 => data(3),
I2 => data(4),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(2),
O6 => data_value(3));
data2_flop: FD
port map ( D => data_value(2),
Q => data(2),
C => clk);
data3_flop: FD
port map ( D => data_value(3),
Q => data(3),
C => clk);
data45_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(4),
O6 => data_value(5));
data4_flop: FD
port map ( D => data_value(4),
Q => data(4),
C => clk);
data5_flop: FD
port map ( D => data_value(5),
Q => data(5),
C => clk);
data67_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(6),
I1 => data(7),
I2 => stop_bit,
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(6),
O6 => data_value(7));
data6_flop: FD
port map ( D => data_value(6),
Q => data(6),
C => clk);
data7_flop: FD
port map ( D => data_value(7),
Q => data(7),
C => clk);
run_lut: LUT6
generic map (INIT => X"2F2FAFAF0000FF00")
port map( I0 => data(0),
I1 => start_bit,
I2 => sample_input,
I3 => sample_dly,
I4 => sample,
I5 => run,
O => run_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
start_bit_lut: LUT6
generic map (INIT => X"222200F000000000")
port map( I0 => start_bit,
I1 => sample_input,
I2 => sample_dly,
I3 => sample,
I4 => run,
I5 => '1',
O => start_bit_value);
start_bit_flop: FD
port map ( D => start_bit_value,
Q => start_bit,
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => run,
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"6CCC00005AAA0000")
port map( I0 => div(2),
I1 => div(3),
I2 => div_carry,
I3 => en_16_x_baud,
I4 => run,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
sample_input_lut: LUT6_2
generic map (INIT => X"0080000088888888")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_carry,
O6 => sample_input_value);
sample_input_flop: FD
port map ( D => sample_input_value,
Q => sample_input,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_rx6.vhd
--
-------------------------------------------------------------------------------------------
| apache-2.0 | c2c2babbcdc5ae19d0787ea60367a699 | 0.502062 | 3.801899 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/tb_serport_uart_rx.vhd | 1 | 9,588 | -- $Id: tb_serport_uart_rx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_uart_rx - sim
-- Description: Test bench for serport_uart_rx
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_serport_uart_rx [UUT]
--
-- To test: serport_uart_rx
--
-- Target Devices: generic
--
-- Verified (with tb_serport_uart_rx_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (63488 cl 15.21s)
-- 2007-10-21 91 - 0.26 - - c:ok (63488 cl 7.12s)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-10-22 417 1.0.3 now numeric_std clean
-- 2010-04-24 281 1.0.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serportlib.all;
entity tb_serport_uart_rx is
end tb_serport_uart_rx;
architecture sim of tb_serport_uart_rx is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv5 := slv(to_unsigned(15, 5));
signal RXSD : slbit := '1';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_ERR : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_ERR_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_ERR_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_serport_uart_rx
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_uart_rx_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable irxerr : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable irate : integer := 16;
type bit_10_array_type is array (0 to 9) of slbit;
type int_10_array_type is array (0 to 9) of integer;
variable valpuls : bit_10_array_type := (others=>'0');
variable delpuls : int_10_array_type := (others=>0);
variable npuls : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
idelta := 0;
while RXACT='1' loop -- ensure that uart isn't active
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
read_ea(iline, irate);
wait for 2*clock_period;
CLKDIV <= slv(to_unsigned(irate-1, CLKDIV'length));
wait for 2*clock_period;
when ".xrate" => -- .xrate
read_ea(iline, irate);
when "puls " => -- puls
writetimestamp(oline, CLK_CYCLE, ": puls ");
read_ea(iline, irxval);
read_ea(iline, irxerr);
read_ea(iline, irxdata);
npuls := 0;
for i in valpuls'range loop
testempty(iline, ok);
if ok then
exit;
end if;
read_ea(iline, valpuls(i));
read_ea(iline, delpuls(i));
assert delpuls(i)>0
report "assert puls length > 0" severity failure;
npuls := npuls + 1;
write(oline, valpuls(i), right, 3);
write(oline, delpuls(i), right, 3);
end loop; -- i
writeline(output, oline);
if npuls > 0 then
N_MON_VAL <= irxval;
N_MON_ERR <= irxerr;
N_MON_DAT <= irxdata;
for i in 0 to npuls-1 loop
RXSD <= valpuls(i);
wait for clock_period;
N_MON_VAL <= '0';
wait for (delpuls(i)-1)*clock_period;
end loop; -- i
end if;
when "send " => -- send
read_ea(iline, idelta);
read_ea(iline, itxdata);
RXSD <= '1';
wait for idelta*clock_period;
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
N_MON_VAL <= '1';
N_MON_ERR <= '0';
N_MON_DAT <= itxdata;
RXSD <= '0'; -- start bit
wait for clock_period;
N_MON_VAL <= '0';
wait for (irate-1)*clock_period;
RXSD <= '1';
for i in itxdata'reverse_range loop -- transmit lsb first
RXSD <= itxdata(i); -- data bit
wait for irate*clock_period;
end loop;
RXSD <= '1'; -- stop bit
wait for irate*clock_period;
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
idelta := 0;
while RXACT='1' loop
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 12*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING ERR="));
write(oline, R_MON_ERR_2);
write(oline, string'(" DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_ERR_2 <= R_MON_ERR_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_ERR_1 <= N_MON_ERR;
R_MON_DAT_1 <= N_MON_DAT;
if RXVAL='1' or RXERR='1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_ERR_2 = '0' then
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
else
if RXERR = '1' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, RXERR=1 expected"));
end if;
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | 0945be0217cf4d2698506b9d45b8ed21 | 0.489883 | 3.791222 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_ledmux.vhd | 1 | 1,970 | -- $Id: pdp11_ledmux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ledmux - syn
-- Description: pdp11: hio led mux
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-02-27 652 1.0 Initial version
-- 2015-02-20 649 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_ledmux is -- hio led mux
generic (
LWIDTH : positive := 8); -- led width
port (
SEL : in slbit; -- select (0=stat;1=dr)
STATLEDS : in slv8; -- 8 bit CPU status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
LED : out slv(LWIDTH-1 downto 0) -- hio leds
);
end pdp11_ledmux;
architecture syn of pdp11_ledmux is
begin
assert LWIDTH=8 or LWIDTH=16
report "assert(LWIDTH=8 or LWIDTH=16): unsupported LWIDTH"
severity failure;
proc_mux: process (SEL, STATLEDS, DM_STAT_EXP)
variable iled : slv(LWIDTH-1 downto 0) := (others=>'0');
begin
iled := (others=>'0');
if SEL = '0' then
iled(STATLEDS'range) := STATLEDS;
else
if LWIDTH=8 then
iled := DM_STAT_EXP.dp_dsrc(11 downto 4); --take middle part
else
iled := DM_STAT_EXP.dp_dsrc(iled'range);
end if;
end if;
LED <= iled;
end process proc_mux;
end syn;
| gpl-3.0 | 08c2e4ece29be8ff77c985d13ac6e7e2 | 0.527411 | 3.536804 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd | 1 | 2,496 | -- $Id: ram_2swsr_rfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_rfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-before-write' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 13; -- address port width 11/9 or 13/8
DWIDTH : positive := 8); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_rfirst_gen;
architecture syn of ram_2swsr_rfirst_gen is
begin
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "READ_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
end syn;
| gpl-3.0 | 4b16fa6db92465d17988b66f05f894c9 | 0.522837 | 3.596542 | false | false | false | false |
nsensfel/tabellion | data/test/CNE_01200/invalid.vhd | 1 | 1,729 | library IEEE;
use IEEE.std_logic_1164.all;
entity invalid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of invalid is
type enum_t is (V0, V1, V2, V3);
signal s0, s1, s2, s3: std_logic;
signal st0: enum_t;
signal n0, n1, n2, n3: natural range 0 to 3;
begin
P_s: process (s0, s1)
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
P_P_P_E: process (s0, s1) -- $SOL:1:0$
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
Nope: op0 <= s1;
end case;
end process;
P_P: process (s0, s1)
begin
op2 <= '0';
P_PP:
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
What: with ip0 select
s1 <=
ip1 when '0',
ip2 when '1',
ip3 when others;
with st0 select
s2 <=
ip1 when V0,
ip2 when V1,
ip3 when V2,
s1 when V3;
P_but_maybe_still: with st0 select
s2 <=
ip1 when V0,
ip2 when V1,
ip3 when others;
P_oops: process (s0, s1, s2, s3)
begin
case st0 is
when V3 =>
Cheese: op0 <= s0;
when V2 =>
May: op0 <= s1;
when V1 =>
Be: op0 <= s2;
when V0 =>
Available: op0 <= s3;
end case;
end process;
end;
| apache-2.0 | b03152980de4cb60a7fe24060f460864 | 0.434933 | 2.986183 | false | false | false | false |
mr-kenhoff/Bitmap-VHDL-Package | rtl/vga_bmp_sink.vhd | 1 | 3,146 | -------------------------------------------------------------------------------
-- File : vga_bmp_sink.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Saves a conventional VGA-Standard input into a .bmp File
--
-- Target: Simulator
-- Dependencies: bmp_pkg.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.bmp_pkg.all;
entity vga_bmp_sink is
generic (
FILENAME : string
);
port (
clk_i : in std_logic;
dat_i : in std_logic_vector(23 downto 0);
active_vid_i : in std_logic;
h_sync_i : in std_logic;
v_sync_i : in std_logic
);
end vga_bmp_sink;
architecture Behavioral of vga_bmp_sink is
signal h_sync_dly : std_logic := '0';
signal v_sync_dly : std_logic := '0';
signal eol : std_logic := '0';
signal eof : std_logic := '0';
signal x : natural := 0;
signal y : natural := 0;
signal is_active_line : std_logic := '0';
signal is_active_frame : std_logic := '0';
begin
h_sync_dly <= h_sync_i when rising_edge(clk_i);
v_sync_dly <= v_sync_i when rising_edge(clk_i);
eol_eof_gen_process : process(clk_i)
begin
if rising_edge(clk_i) then
-- EOL
if h_sync_dly = '0' and h_sync_i = '1' then
eol <= '1';
else
eol <= '0';
end if;
-- EOF
if v_sync_dly = '0' and v_sync_i = '1' then
eof <= '1';
else
eof <= '0';
end if;
end if;
end process;
sink_process : process( clk_i )
variable sink_bmp : bmp_ptr;
variable sink_pix : bmp_pix;
variable is_bmp_created : boolean := false;
variable is_bmp_saved : boolean := false;
begin
-- Create bitmap on startup
if is_bmp_created = false then
sink_bmp := new bmp;
is_bmp_created := true;
end if;
if rising_edge( clk_i ) then
if active_vid_i = '1' then
sink_pix.r := dat_i(23 downto 16);
sink_pix.g := dat_i(15 downto 8);
sink_pix.b := dat_i(7 downto 0);
bmp_set_pix( sink_bmp, x, y, sink_pix );
x <= x + 1;
is_active_line <= '1';
is_active_frame <= '1';
else
if eol = '1' then
x <= 0;
if is_active_line = '1' then
y <= y + 1;
end if;
is_active_line <= '0';
end if;
if eof = '1' then
y <= 0;
if is_active_frame = '1' then
bmp_save( sink_bmp, FILENAME );
end if;
is_active_frame <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
| mit | d51945b7b6671dfba0a04dbbb751b54a | 0.410045 | 3.883951 | false | false | false | false |
rongcuid/lots-of-subleq-cpus | Subleq Pipelined/src/mmu.vhd | 1 | 8,546 | ----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date:
-- Design Name:
-- Module Name: MMU
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- This is a 32-bit address, 64-bit data, byte addressable MMU.
-- Multiple devices can be mapped onto the memory. Currently the
-- memory map is as following:
--
-- - 0x00000000 - 0x0FFFFFFF, Main Memory. Maximum size: 256MiB
-- - 0x7F000000 - 0x7FFFFFFF, I/O devices.
-- -
-- -
--
-- Currently, RWXD bits are NOT SUPPORTED (at least, not in this
-- version of the CPU)
--
-- This MMU is dual-port. Port I is for Instruction memory, and
-- Port D is for Data memory. Suffixes i and d are used to distinguish
-- signals.
entity MMU is
generic ( DEPTH_BANK : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
resetb : in std_logic;
-- Instruction Memory
we_i : in std_logic;
en_i : in std_logic;
addr_i : in std_logic_vector(31 downto 3);
ben_i : in std_logic_vector(7 downto 0);
di_i : in std_logic_vector(63 downto 0);
do_i : out std_logic_vector(63 downto 0);
-- Data Memory
we_d : in std_logic;
en_d : in std_logic;
addr_d : in std_logic_vector(31 downto 3);
ben_d : in std_logic_vector(7 downto 0);
di_d : in std_logic_vector(63 downto 0);
do_d : out std_logic_vector(63 downto 0)
);
end MMU;
architecture behavior of MMU is
type byte_array8_t is array (0 to 7) of std_logic_vector(7 downto 0);
-- Memory Bank Control Signals
signal wei_ram, wed_ram, eni_ram, end_ram : std_logic_vector(7 downto 0);
signal dii, did, doi, dod : byte_array8_t;
component BRAM_DP
generic ( WIDTH : integer := 32;
DEPTH : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
awe : in std_logic;
aen : in std_logic;
aaddr : in std_logic_vector(DEPTH_LOG-1 downto 0);
adi : in std_logic_vector(WIDTH-1 downto 0);
ado : out std_logic_vector(WIDTH-1 downto 0);
bwe : in std_logic;
ben : in std_logic;
baddr : in std_logic_vector(DEPTH_LOG-1 downto 0);
bdi : in std_logic_vector(WIDTH-1 downto 0);
bdo : out std_logic_vector(WIDTH-1 downto 0)
);
end component BRAM_DP;
-- -- Memory Bank control signals
-- signal we_ram0, en_ram0 : std_logic;
-- signal we_ram1, en_ram1 : std_logic;
-- signal we_ram2, en_ram2 : std_logic;
-- signal we_ram3, en_ram3 : std_logic;
-- signal we_ram4, en_ram4 : std_logic;
-- signal we_ram5, en_ram5 : std_logic;
-- signal we_ram6, en_ram6 : std_logic;
-- signal we_ram7, en_ram7 : std_logic;
-- -- Memory Bank Data In
-- signal di_ram0, di_ram1, di_ram2, di_ram3, di_ram4, di_ram5, di_ram6, di_ram7 : std_logic_vector(7 downto 0);
-- -- Memory Bank Data Out
-- signal do_ram0, do_ram1, do_ram2, do_ram3, do_ram4, do_ram5, do_ram6, do_ram7 : std_logic_vector(7 downto 0);
-- signal do_ram : std_logic_vector(63 downto 0);
-- component BRAM_SP
-- generic ( WIDTH : integer := 32;
-- DEPTH : integer := 1024;
-- DEPTH_LOG : integer := 10
-- );
-- port (
-- clk : in std_logic;
-- we : in std_logic;
-- en : in std_logic;
-- addr : in std_logic_vector(DEPTH_LOG-1 downto 0);
-- di : in std_logic_vector(WIDTH-1 downto 0);
-- do : out std_logic_vector(WIDTH-1 downto 0)
-- );
-- end component BRAM_SP;
begin
-- The main memory bank.
RAM0 : BRAM_DP
generic map (WIDTH => 8, DEPTH => DEPTH_BANK, DEPTH_LOG => DEPTH_LOG)
port map (
clk=>clk,
awe=>wei_ram(0),aen=>eni_ram(0),
aaddr=>addr_i(DEPTH_LOG+3-1 downto 3),adi=>dii(0),ado=>doi(0),
bwe=>wed_ram(0),ben=>end_ram(0),
baddr=>addr_d(DEPTH_LOG+3-1 downto 3),bdi=>did(0),bdo=>dod(0)
);
RAM1 : BRAM_DP
generic map (WIDTH => 8, DEPTH => DEPTH_BANK, DEPTH_LOG => DEPTH_LOG)
port map (
clk=>clk,
awe=>wei_ram(1),aen=>eni_ram(1),
aaddr=>addr_i(DEPTH_LOG+3-1 downto 3),adi=>dii(1),ado=>doi(1),
bwe=>wed_ram(1),ben=>end_ram(1),
baddr=>addr_d(DEPTH_LOG+3-1 downto 3),bdi=>did(1),bdo=>dod(1)
);
RAM2 : BRAM_DP
generic map (WIDTH => 8, DEPTH => DEPTH_BANK, DEPTH_LOG => DEPTH_LOG)
port map (
clk=>clk,
awe=>wei_ram(2),aen=>eni_ram(2),
aaddr=>addr_i(DEPTH_LOG+3-1 downto 3),adi=>dii(2),ado=>doi(2),
bwe=>wed_ram(2),ben=>end_ram(2),
baddr=>addr_d(DEPTH_LOG+3-1 downto 3),bdi=>did(2),bdo=>dod(2)
);
RAM3 : BRAM_DP
generic map (WIDTH => 8, DEPTH => DEPTH_BANK, DEPTH_LOG => DEPTH_LOG)
port map (
clk=>clk,
awe=>wei_ram(3),aen=>eni_ram(3),
aaddr=>addr_i(DEPTH_LOG+3-1 downto 3),adi=>dii(3),ado=>doi(3),
bwe=>wed_ram(3),ben=>end_ram(3),
baddr=>addr_d(DEPTH_LOG+3-1 downto 3),bdi=>did(3),bdo=>dod(3)
);
RAM4 : BRAM_DP
generic map (WIDTH => 8, DEPTH => DEPTH_BANK, DEPTH_LOG => DEPTH_LOG)
port map (
clk=>clk,
awe=>wei_ram(4),aen=>eni_ram(4),
aaddr=>addr_i(DEPTH_LOG+3-1 downto 3),adi=>dii(4),ado=>doi(4),
bwe=>wed_ram(4),ben=>end_ram(4),
baddr=>addr_d(DEPTH_LOG+3-1 downto 3),bdi=>did(4),bdo=>dod(4)
);
RAM5 : BRAM_DP
generic map (WIDTH => 8, DEPTH => DEPTH_BANK, DEPTH_LOG => DEPTH_LOG)
port map (
clk=>clk,
awe=>wei_ram(5),aen=>eni_ram(5),
aaddr=>addr_i(DEPTH_LOG+3-1 downto 3),adi=>dii(5),ado=>doi(5),
bwe=>wed_ram(5),ben=>end_ram(5),
baddr=>addr_d(DEPTH_LOG+3-1 downto 3),bdi=>did(5),bdo=>dod(5)
);
RAM6 : BRAM_DP
generic map (WIDTH => 8, DEPTH => DEPTH_BANK, DEPTH_LOG => DEPTH_LOG)
port map (
clk=>clk,
awe=>wei_ram(6),aen=>eni_ram(6),
aaddr=>addr_i(DEPTH_LOG+3-1 downto 3),adi=>dii(6),ado=>doi(6),
bwe=>wed_ram(6),ben=>end_ram(6),
baddr=>addr_d(DEPTH_LOG+3-1 downto 3),bdi=>did(6),bdo=>dod(6)
);
RAM7 : BRAM_DP
generic map (WIDTH => 8, DEPTH => DEPTH_BANK, DEPTH_LOG => DEPTH_LOG)
port map (
clk=>clk,
awe=>wei_ram(7),aen=>eni_ram(7),
aaddr=>addr_i(DEPTH_LOG+3-1 downto 3),adi=>dii(7),ado=>doi(7),
bwe=>wed_ram(7),ben=>end_ram(7),
baddr=>addr_d(DEPTH_LOG+3-1 downto 3),bdi=>did(7),bdo=>dod(7)
);
-- The main mux which selects devices
selector : process (we_i, en_i, addr_i, ben_i, di_i, doi,
we_d, en_d, addr_d, ben_d, di_d, dod)
begin
-- Write and Enable are all inactive by default
eni_ram <= "00000000";
wei_ram <= "00000000";
end_ram <= "00000000";
wei_ram <= "00000000";
-- Data is interleaved
for i in 0 to 7 loop
dii(i) <= di_i(7+8*i downto 8*i);
did(i) <= di_d(7+8*i downto 8*i);
end loop;
-- By default, MMU generates invalid data
do_i <= (others => '-');
do_d <= (others => '-');
instruction_mux : if (addr_i(31) = '0') then
-- If address is 0x0XXXXXXX, then selet Main Memory
-- The following section turns on memory bank as needed
-- The memory is in low-level interleaving mode so that
-- we can access 8 bytes in parallel
for i in 0 to 7 loop
do_i(i*8+7 downto i*8) <= doi(i);
if (ben_i(i) = '0') then
wei_ram(i) <= we_i;
eni_ram(i) <= en_i;
end if;
end loop;
else
-- If not main memory. This is not implemented in this project
end if instruction_mux;
data_mux : if (addr_i(31) = '0') then
-- If address is 0x0XXXXXXX, then selet Main Memory
for i in 0 to 7 loop
do_d(i*8+7 downto i*8) <= dod(i);
end loop;
-- The following section turns on memory bank as needed
-- The memory is in low-level interleaving mode so that
-- we can access 8 bytes in parallel
for i in 0 to 7 loop
if (ben_d(i) = '0') then
wed_ram(i) <= we_d;
end_ram(i) <= en_d;
end if;
end loop;
else
-- If not main memory. This is not implemented in this project
end if data_mux;
end process selector;
end behavior;
| gpl-3.0 | e4ec5148add6b039b01d7be1ed1a219c | 0.571027 | 3.034801 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/sim_top.vhd | 1 | 3,132 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity sim_top is
port(clk : in std_logic;
rst : in std_logic);
end sim_top;
architecture Behavioral of sim_top is
component OZ4_top is
port(clk : in std_logic;
rst : in std_logic;
--Basic IO
iport : in std_logic_vector(31 downto 0);
ipins : in std_logic_vector(7 downto 0);
oport : out std_logic_vector(31 downto 0);
opins : out std_logic_vector(7 downto 0);
--Instruction Memory
instruction_in : in std_logic_vector(11 downto 0);
instruction_addr : out std_logic_vector(31 downto 0);
immediate_in : in std_logic_vector(31 downto 0);
immediate_addr : out std_logic_vector(5 downto 0);
--Data Memory
mem_addr : out std_logic_vector(31 downto 0);
mem_write_data : out std_logic_vector(31 downto 0);
mem_read_data : in std_logic_vector(31 downto 0);
mem_we_out : out std_logic;
mem_clk : out std_logic);
end component;
component data_memory is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic);
end component;
component instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_logic_vector(5 downto 0);
immediate_out : out std_logic_vector(31 downto 0));
end component;
signal OZ4_iport, OZ4_oport : std_logic_vector(31 downto 0);
signal OZ4_ipins, OZ4_opins : std_logic_vector(7 downto 0);
signal instruction_mem_out : std_logic_vector(11 downto 0);
signal instruction_addr : std_logic_vector(31 downto 0);
signal immediate_mem_out : std_logic_vector(31 downto 0);
signal immediate_addr : std_logic_vector(5 downto 0);
signal data_mem_addr, data_mem_in, data_mem_out: std_logic_vector(31 downto 0);
signal data_mem_we : std_logic;
begin
OZ4_iport <= x"50505050";
OZ4_ipins <= "01011000";
OZ4 : OZ4_top
port map(clk => clk,
rst => rst,
iport => OZ4_iport,
ipins => OZ4_ipins,
oport => OZ4_oport,
opins => OZ4_opins,
instruction_in => instruction_mem_out,
instruction_addr => instruction_addr,
immediate_in => immediate_mem_out,
immediate_addr => immediate_addr,
mem_addr => data_mem_addr,
mem_write_data => data_mem_in,
mem_read_data => data_mem_out,
mem_we_out => data_mem_we,
mem_clk => open
);
data_mem : data_memory
port map(clk => clk,
rst => rst,
address => data_mem_addr,
data_in => data_mem_in,
data_out => data_mem_out,
we => data_mem_we
);
prog_mem : instruction_memory
port map(address => instruction_addr,
data_out => instruction_mem_out,
immediate_addr => immediate_addr,
immediate_out => immediate_mem_out
);
end Behavioral;
| mit | 45ee984a72efe96c965191a8ec08e041 | 0.628991 | 3.182927 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys2/tb/nexys2_dummy.vhd | 1 | 3,155 | -- $Id: nexys2_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys2_dummy - syn
-- Description: nexys2 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys2
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 use nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-23 294 1.0 Initial version (derived from s3board_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys2_dummy is -- NEXYS 2 dummy (base; loopback)
-- implements nexys2_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end nexys2_dummy;
architecture syn of nexys2_dummy is
begin
O_TXD <= I_RXD; -- loop back
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
| gpl-3.0 | 9c3228c3e4da03756464d43766ccb374 | 0.499208 | 3.249228 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/rlink_mon.vhd | 1 | 6,229 | -- $Id: rlink_mon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon - sim
-- Description: rlink monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2-17.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-11-08 602 4.0.2 annotate clobber commas
-- 2014-10-25 599 4.0.1 use writeoptint()
-- 2014-10-12 596 4.0 adopt to new escaping, better 8 bit output
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-11-19 427 3.0.2 now numeric_std clean
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rlinklib.all;
use work.comlib.all;
entity rlink_mon is -- rlink monitor
generic (
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon;
architecture sim of rlink_mon is
begin
assert DWIDTH=8 or DWIDTH=9
report "assert(DWIDTH=8 or DWIDTH=9)" severity failure;
proc_moni: process
variable oline : line;
variable nbusy : integer := 0;
variable nhold : integer := 0;
variable edatarx : boolean := false;
variable edatatx : boolean := false;
procedure write_val(L: inout line;
data: in slv(DWIDTH-1 downto 0);
nwait: in integer;
txt1: in string(1 to 2);
txt2: in string;
edata: in boolean) is
variable data9 : slv9 := (others=>'0');
variable optxt : string(1 to 8) := ": ??rx ";
begin
if DWIDTH = 9 then
optxt(3 to 4) := "rl";
else
optxt(3 to 4) := "r8";
end if;
optxt(5 to 6) := txt1;
writetimestamp(L, CLK_CYCLE, optxt);
if DWIDTH = 9 then
write(L, data(data'left), right, 1);
else
write(L, string'(" "));
end if;
write(L, data(7 downto 0), right, 9);
writeoptint(L, txt2, nwait);
if DWIDTH=9 and data(data'left)='1' then
-- a copy to data9 needed to allow following case construct
-- using data directly gives a 'subtype is not locally static' error
data9 := (others=>'0');
data9(data'range) := data;
write(L, string'(" comma"));
case data9 is
when c_rlink_dat_sop => write(L, string'(" sop"));
when c_rlink_dat_eop => write(L, string'(" eop"));
when c_rlink_dat_nak => write(L, string'(" nak"));
when c_rlink_dat_attn => write(L, string'(" attn"));
when others => write(L, string'(" clobber|oob"));
end case;
end if;
if DWIDTH = 8 then
if edata then
write(L, string'(" edata"));
if data(c_cdata_edf_pref) /= c_cdata_ed_pref or
(not data(c_cdata_edf_eci)) /= data(c_cdata_edf_ec) then
write(L, string'(" FAIL: bad format"));
else
write(L, string'(" ec="));
write(L, data(c_cdata_edf_ec));
data9 := (others=>'0');
data9(8) := '1';
data9(c_cdata_edf_ec) := data(c_cdata_edf_ec);
case data9 is
when c_rlink_dat_sop => write(L, string'(" (sop)"));
when c_rlink_dat_eop => write(L, string'(" (eop)"));
when c_rlink_dat_nak => write(L, string'(" (nak)"));
when c_rlink_dat_attn => write(L, string'(" (attn)"));
when "100000" & c_cdata_ec_xon => write(L, string'(" (xon)"));
when "100000" & c_cdata_ec_xoff => write(L, string'(" (xoff)"));
when "100000" & c_cdata_ec_fill => write(L, string'(" (fill)"));
when "100000" & c_cdata_ec_esc => write(L, string'(" (esc)"));
when others =>
write(L, string'(" FAIL: bad ec"));
end case;
end if;
end if;
if data = c_cdata_escape then
write(L, string'(" escape"));
end if;
end if;
writeline(output, L);
end procedure write_val;
begin
loop
if ENA='0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RL_ENA = '1' then
if RL_BUSY = '1' then
nbusy := nbusy + 1;
else
write_val(oline, RL_DI, nbusy, "rx", " nbusy=", edatarx);
edatarx := RL_DI=c_cdata_escape;
nbusy := 0;
end if;
else
nbusy := 0;
end if;
if RL_VAL = '1' then
if RL_HOLD = '1' then
nhold := nhold + 1;
else
write_val(oline, RL_DO, nhold, "tx", " nhold=", edatatx);
edatatx := RL_DO=c_cdata_escape;
nhold := 0;
end if;
else
nhold := 0;
end if;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | 86aa6d8a1f87dbad696e67fb005d27fa | 0.500562 | 3.557396 | false | false | false | false |
mr-kenhoff/Bitmap-VHDL-Package | rtl/bmp_source.vhd | 1 | 2,958 | -------------------------------------------------------------------------------
-- File : bmp_source.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Outputs a bitmap image as a data stream
-- Target: Simulator
-- Dependencies: bmp_pkg.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bmp_pkg.all;
entity bmp_source is
generic (
FILENAME : string;
ITERATIONS : natural;
BACKPRESSURE_EN : boolean := false
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
val_o : out std_logic := '0';
dat_o : out std_logic_vector(23 downto 0) := (others => '0');
rdy_i : in std_logic;
eol_o : out std_logic := '0';
eof_o : out std_logic := '0'
);
end entity;
architecture behavioural of bmp_source is
begin
source_process : process( clk_i )
variable source_bmp : bmp_ptr;
variable source_pix : bmp_pix;
variable is_bmp_loaded : boolean := false;
variable iteration : natural := 0;
variable x : natural := 0;
variable y : natural := 0;
begin
if is_bmp_loaded = false then
source_bmp := new bmp;
bmp_open(source_bmp, FILENAME);
is_bmp_loaded := true;
end if;
if rising_edge( clk_i ) then
eol_o <= '0';
eof_o <= '0';
val_o <= '0';
if rst_i = '1' then
iteration := 0;
x := 0;
y := 0;
else
if (BACKPRESSURE_EN and rdy_i = '1') or not BACKPRESSURE_EN then
if iteration < ITERATIONS then
bmp_get_pix( source_bmp, x, y, source_pix );
dat_o(23 downto 16) <= source_pix.r;
dat_o(15 downto 8) <= source_pix.g;
dat_o(7 downto 0) <= source_pix.b;
val_o <= '1';
if x = source_bmp.meta.width-1 then -- EOL
eol_o <= '1';
x := 0;
if y = source_bmp.meta.height-1 then -- EOF
eof_o <= '1';
y := 0;
iteration := iteration + 1;
else -- Not EOF
y := y + 1;
end if;
else -- Not EOL
x := x + 1;
end if;
end if; -- if iteration < ITERATIONS
end if;
end if;
end if;
end process;
end architecture;
| mit | 793361f38a5b702d76cdd89127e818be | 0.378634 | 4.502283 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_sys70.vhd | 1 | 15,552 | -- $Id: pdp11_sys70.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sys70 - syn
-- Description: pdp11: 11/70 system - single core +rbus,debug,cache
--
-- Dependencies: w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- ibus/ibd_ibmon
-- ibus/ibd_ibtst
-- ibus/ib_sres_or_4
-- w11a/pdp11_dmscnt
-- w11a/pdp11_dmcmon
-- w11a/pdp11_dmhpbt
-- w11a/pdp11_dmpcnt
-- rbus/rb_sres_or_4
-- rbus/rb_sres_or_2
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.3.3 use rbaddr_ constants
-- 2019-03-02 1116 1.3.2 add RESET_SYS; fix pdp11_mem70 reset
-- 2019-02-16 1112 1.3.1 add ibd_ibtst
-- 2018-10-13 1055 1.3 drop ITIMER,DM_STAT_DP out ports, use DM_STAT_EXP
-- add PERFEXT in port
-- 2018-10-06 1053 1.2.3 drop DM_STAT_SY; add DM_STAT_CA; use _SE.pcload
-- 2018-09-29 1051 1.2.2 add pdp11_dmpcnt
-- 2017-04-22 884 1.2.1 pdp11_dmcmon: use SNUM and AWIDTH generics
-- 2016-03-22 750 1.2 pdp11_cache now configurable size
-- 2015-11-01 712 1.1.4 use sbcntl_sbf_tmu
-- 2015-07-19 702 1.1.3 use DM_STAT_SE
-- 2015-07-04 697 1.1.2 change DM_STAT_SY setup; add dmcmon, dmhbpt;
-- 2015-06-26 695 1.1.1 add pdp11_dmscnt support
-- 2015-05-09 677 1.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.pdp11.all;
use work.iblib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus request (slave)
RB_SRES : out rb_sres_type; -- rbus response
RB_STAT : out slv4; -- rbus status flags
RB_LAM_CPU : out slbit; -- rbus lam (cpu)
GRESET : out slbit; -- general reset (from rbus)
CRESET : out slbit; -- cpu reset (from cp)
BRESET : out slbit; -- bus reset (from cp or cpu)
CP_STAT : out cp_stat_type; -- console port status
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PERFEXT : in slv8; -- cpu external perf counter signals
IB_MREQ : out ib_mreq_type; -- ibus request (master)
IB_SRES : in ib_sres_type; -- ibus response
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_EXP : out dm_stat_exp_type -- debug and monitor - sys70 exports
);
end pdp11_sys70;
architecture syn of pdp11_sys70 is
signal RB_SRES_CORE : rb_sres_type := rb_sres_init;
signal RB_SRES_DMSCNT : rb_sres_type := rb_sres_init;
signal RB_SRES_DMPCNT : rb_sres_type := rb_sres_init;
signal RB_SRES_DMHBPT : rb_sres_type := rb_sres_init;
signal RB_SRES_DMCMON : rb_sres_type := rb_sres_init;
signal RB_SRES_DM : rb_sres_type := rb_sres_init;
signal RB_SRES_L : rb_sres_type := rb_sres_init;
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT_L : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_ACKM_L : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal GRESET_L : slbit := '0'; -- general reset (from rbus init)
signal CRESET_L : slbit := '0'; -- cpu reset (from -creset command)
signal BRESET_L : slbit := '0'; -- bus reset (RESET inst or -breset)
signal RESET_SYS : slbit := '0'; -- or of RESET (port) and GRESET (rbus)
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal HBPT : slbit := '0';
signal DM_STAT_SE : dm_stat_se_type := dm_stat_se_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_CA : dm_stat_ca_type := dm_stat_ca_init;
signal IB_MREQ_M : ib_mreq_type := ib_mreq_init;
signal IB_SRES_M : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBMON : ib_sres_type := ib_sres_init;
signal IB_SRES_IBTST : ib_sres_type := ib_sres_init;
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx
begin
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus0)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CORE,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_CPU,
GRESET => GRESET_L,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT_L,
CP_DOUT => CP_DOUT
);
RESET_SYS <= RESET or GRESET_L; -- use as reset of w11 sub-system
W11A : pdp11_core
port map (
CLK => CLK,
RESET => RESET_SYS,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT_L,
CP_DOUT => CP_DOUT,
ESUSP_O => open,
ESUSP_I => '0',
HBPT => HBPT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM_L,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
CRESET => CRESET_L,
BRESET => BRESET_L,
IB_MREQ_M => IB_MREQ_M,
IB_SRES_M => IB_SRES_M,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
CACHE: pdp11_cache
generic map (
TWIDTH => sys_conf_cache_twidth)
port map (
CLK => CLK,
GRESET => RESET_SYS,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
FMISS => CACHE_FMISS,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_CA => DM_STAT_CA
);
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => CRESET_L,
HM_ENA => HM_ENA,
HM_VAL => DM_STAT_CA.rdhit,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_MEM70
);
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
IBMON : if sys_conf_ibmon_awidth > 0 generate
begin
I0 : ibd_ibmon
generic map (
IB_ADDR => slv(to_unsigned(8#160000#,16)),
AWIDTH => sys_conf_ibmon_awidth)
port map (
CLK => CLK,
RESET => RESET_SYS,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_IBMON,
IB_SRES_SUM => DM_STAT_VM.ibsres
);
end generate IBMON;
IBTST : if sys_conf_ibtst generate
signal RESET_IBTST : slbit := '0';
begin
RESET_IBTST <= RESET_SYS or BRESET_L;
I0 : ibd_ibtst
generic map (
IB_ADDR => slv(to_unsigned(8#170000#,16)))
port map (
CLK => CLK,
RESET => RESET_IBTST,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_IBTST
);
end generate IBTST;
IB_SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES,
IB_SRES_3 => IB_SRES_IBMON,
IB_SRES_4 => IB_SRES_IBTST,
IB_SRES_OR => IB_SRES_M
);
DMSCNT : if sys_conf_dmscnt generate
begin
I0: pdp11_dmscnt
generic map (
RB_ADDR => rbaddr_dmscnt_off)
port map (
CLK => CLK,
RESET => RESET_SYS,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMSCNT,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_CO => DM_STAT_CO
);
end generate DMSCNT;
DMCMON : if sys_conf_dmcmon_awidth > 0 generate
begin
I0: pdp11_dmcmon
generic map (
RB_ADDR => rbaddr_dmcmon_off,
AWIDTH => sys_conf_dmcmon_awidth,
SNUM => sys_conf_dmscnt)
port map (
CLK => CLK,
RESET => RESET_SYS,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMCMON,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
end generate DMCMON;
DMHBPT : if sys_conf_dmhbpt_nunit > 0 generate
begin
I0: pdp11_dmhbpt
generic map (
RB_ADDR => rbaddr_dmhbpt_off,
NUNIT => sys_conf_dmhbpt_nunit)
port map (
CLK => CLK,
RESET => RESET_SYS,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMHBPT,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
HBPT => HBPT
);
end generate DMHBPT;
DMPCNT : if sys_conf_dmpcnt generate
signal PERFSIG : slv32 := (others=>'0');
begin
proc_sig: process (CP_STAT_L, DM_STAT_SE, DM_STAT_DP, DM_STAT_DP.psw,
DM_STAT_CA, RB_MREQ, RB_SRES_L, EI_ACKM_L,
DM_STAT_VM.ibmreq, DM_STAT_VM.ibsres, PERFEXT)
variable isig : slv32 := (others=>'0');
begin
isig := (others=>'0');
if DM_STAT_SE.cpbusy = '1' then
isig(0) := '1'; -- cpu_cpbusy
elsif CP_STAT_L.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT_L.cpuwait = '1' then
isig(3) := '1'; -- cpu_km_wait
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
isig(2) := '1'; -- cpu_km_pri0
else
isig(1) := '1'; -- cpu_km_prix
end if;
when c_psw_smode =>
isig(4) := '1'; -- cpu_sm
when c_psw_umode =>
isig(5) := '1'; -- cpu_um
when others => null;
end case;
end if;
isig(6) := DM_STAT_SE.idec; -- cpu_idec
isig(7) := DM_STAT_SE.pcload; -- cpu_pcload
isig(8) := DM_STAT_SE.vfetch; -- cpu_vfetch
isig(9) := EI_ACKM_L; -- cpu_irupt (not counting PIRQ!)
isig(10) := DM_STAT_CA.rd; -- ca_rd
isig(11) := DM_STAT_CA.wr; -- ca_wr
isig(12) := DM_STAT_CA.rdhit; -- ca_rdhit
isig(13) := DM_STAT_CA.wrhit; -- ca_wrhit
isig(14) := DM_STAT_CA.rdmem; -- ca_rdmem
isig(15) := DM_STAT_CA.wrmem; -- ca_wrmem
isig(16) := DM_STAT_CA.rdwait; -- ca_rdwait
isig(17) := DM_STAT_CA.wrwait; -- ca_wrwait
if DM_STAT_VM.ibmreq.aval='1' then
if DM_STAT_VM. ibsres.busy='0' then
isig(18) := DM_STAT_VM.ibmreq.re; -- ib_rd
isig(19) := DM_STAT_VM.ibmreq.we; -- ib_wr
else
isig(20) := DM_STAT_VM.ibmreq.re or DM_STAT_VM.ibmreq.we; -- ib_busy
end if;
end if;
-- a hack too, for 1 core systems is addr(15)='0' when CPU addressed
if RB_MREQ.aval='1' and RB_MREQ.addr(15)='0' then
if RB_SRES_L.busy='0' then
isig(21) := RB_MREQ.re; -- rb_rd
isig(22) := RB_MREQ.we; -- rb_wr
else
isig(23) := RB_MREQ.re or RB_MREQ.we; -- rb_busy
end if;
end if;
isig(24) := PERFEXT(0); -- ext_rdrhit
isig(25) := PERFEXT(1); -- ext_wrrhit
isig(26) := PERFEXT(2); -- ext_wrflush
isig(27) := PERFEXT(3); -- ext_rlrxact
isig(28) := PERFEXT(4); -- ext_rlrxback
isig(29) := PERFEXT(5); -- ext_rltxact
isig(30) := PERFEXT(6); -- ext_rltxback
isig(31) := PERFEXT(7); -- ext_usec
PERFSIG <= isig;
end process proc_sig;
I0: pdp11_dmpcnt
generic map (
RB_ADDR => rbaddr_dmpcnt_off, -- rbus address
VERS => slv(to_unsigned(1, 8)), -- counter layout version
-- 33222222222211111111110000000000
-- 10987654321098765432109876543210
CENA => "11111111111111111111111111111111") -- counter enables
port map (
CLK => CLK,
RESET => RESET_SYS,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMPCNT,
PERFSIG => PERFSIG
);
end generate DMPCNT;
RB_SRES_DMOR : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_DMSCNT,
RB_SRES_2 => RB_SRES_DMPCNT,
RB_SRES_3 => RB_SRES_DMHBPT,
RB_SRES_4 => RB_SRES_DMCMON,
RB_SRES_OR => RB_SRES_DM
);
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CORE,
RB_SRES_2 => RB_SRES_DM,
RB_SRES_OR => RB_SRES_L
);
RB_SRES <= RB_SRES_L; -- setup output signals
IB_MREQ <= IB_MREQ_M;
GRESET <= GRESET_L;
CRESET <= CRESET_L;
BRESET <= BRESET_L;
CP_STAT <= CP_STAT_L;
EI_ACKM <= EI_ACKM_L;
DM_STAT_EXP.dp_psw <= DM_STAT_DP.psw;
DM_STAT_EXP.dp_pc <= DM_STAT_DP.pc;
DM_STAT_EXP.dp_dsrc <= DM_STAT_DP.dsrc;
DM_STAT_EXP.se_idec <= DM_STAT_SE.idec;
DM_STAT_EXP.se_itimer <= DM_STAT_SE.itimer;
-- synthesis translate_off
TMU : pdp11_tmu_sb
generic map (
ENAPIN => sbcntl_sbf_tmu)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_CA => DM_STAT_CA
);
-- synthesis translate_on
end syn;
| gpl-3.0 | 7158cbfab07c3450a69d5c8e9f747cfe | 0.502251 | 3.162261 | false | false | false | false |
thelonious/sound_out | sound_out.vhd | 1 | 1,698 | --
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SoundOut is
port(
clock: in std_logic;
audio_left, audio_right: out std_logic
);
end SoundOut;
architecture behavioral of SoundOut is
component Timer
generic(
TIMER_FREQUENCY: positive
);
port(
clock: in std_logic;
reset: in std_logic;
tick: out std_logic
);
end component;
component dac
port(
clk: in std_logic;
reset: in std_logic;
DACin: in std_logic_vector(7 downto 0);
DACout: out std_logic
);
end component;
signal tick: std_logic := '0';
signal wave: std_logic_vector(7 downto 0) := "01110000";
signal tick2: std_logic := '0';
signal wave2: std_logic_vector(7 downto 0) := "01110000";
begin
-- left
fundamental_left: Timer
generic map(
TIMER_FREQUENCY => 880 -- 2x concert A
)
port map(
clock => clock,
reset => '0',
tick => tick
);
sd_left: dac
port map(
clk => clock,
reset => '0',
DACin => wave,
DACout => audio_left
);
toggle_left: process(clock, tick)
begin
if clock'event and clock = '1' then
if tick = '1' then
wave <= 255 - wave;
end if;
end if;
end process;
-- right
fundamental_right: Timer
generic map(
TIMER_FREQUENCY => 875
)
port map(
clock => clock,
reset => '0',
tick => tick2
);
sd_right: dac
port map(
clk => clock,
reset => '0',
DACin => wave2,
DACout => audio_right
);
toggle_right: process(clock, tick2)
begin
if clock'event and clock = '1' then
if tick2 = '1' then
wave2 <= 255 - wave2;
end if;
end if;
end process;
end behavioral;
| bsd-3-clause | a2e4dfedb6ef9ced4dfa87f5ad7daa90 | 0.62662 | 2.806612 | false | false | false | false |
abcsds/Micros | RS232Write_16/FsmWrite.vhd | 4 | 3,940 | library IEEE;
use IEEE.std_logic_1164.all;
entity FsmWrite is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOT : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end FsmWrite;
architecture simple of FsmWrite is
signal Qp, Qn : std_logic_vector(3 downto 0);
begin
COMB: process(Qp,STR,FBaud)
begin
case Qp is
when "0000" =>
CTRL<= "0000"; -- Hold
EOT<= '1';
if(STR= '0')then
Qn<= Qp;
else
Qn<= "0001";
end if;
when "0001" =>
CTRL<= "0000"; -- Hold
EOT<= '0';
if(FBaud= '1')then
Qn<= "0010";
else
Qn<= Qp;
end if;
when "0010" =>
CTRL<= "0001"; -- Start
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0011";
end if;
when "0011" =>
CTRL<= "0010"; -- Bit 0
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0100";
end if;
when "0100" =>
CTRL<= "0011"; -- Bit 1
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0101";
end if;
when "0101" =>
CTRL<= "0100"; -- Bit2
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0110";
end if;
when "0110" =>
CTRL<= "0101"; -- Bit 3
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "0111";
end if;
when "0111" =>
CTRL<= "0110"; -- Bit 4
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1000";
end if;
when "1000" =>
CTRL<= "0111"; -- Bit 5
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1001";
end if;
when "1001" =>
CTRL<= "1000"; -- Bit 6
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1010";
end if;
when "1010" =>
CTRL<= "1001"; -- Bit 7
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1011";
end if;
when "1011" =>
CTRL<= "1010"; -- Stop
EOT<= '0';
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "1100";
end if;
when others =>
CTRL<= "0000";
EOT<= '1';
Qn<= "0000";
end case;
end process COMB;
FF: process(RST,CLK)
begin
if(RST='0')then
Qp<= "0000";
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process;
end simple; | gpl-3.0 | ed4ffc2e712799283cde1ce3e4026ccd | 0.268528 | 4.888337 | false | false | false | false |
abcsds/Micros | RS232Read_DEPRECATED/register_of_displacement.vhd | 2 | 940 | library IEEE;
use IEEE.std_logic_1164.all;
entity register_of_displacement is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
CTRL : in std_logic_vector(1 downto 0);
DATARead : out std_logic_vector(8 downto 0)
);
end register_of_displacement;
architecture simple of register_of_displacement is
signal Qn,Qp:std_logic_vector(8 downto 0);
begin
combinacional: process(CTRL, Qp, Rx)
begin
case( CTRL ) is
when "00" => Qn <= Qp;
when "01" => Qn <= (others => '0');
when others => Qn <= Rx & Qp(7 downto 1);
end case ;
DATARead <= Qp;
end process combinacional;
secuencial: process(RST,CLK)
begin
if (RST='0') then
Qp<=(others=>'0');
elsif (CLK'event and CLK='1') then
Qp<=Qn;
end if;
end process secuencial;
end simple;
| gpl-3.0 | c5eedf0153ed8a551f940f28296332e9 | 0.545745 | 3.700787 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_munit.vhd | 1 | 15,312 | -- $Id: pdp11_munit.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_munit - syn
-- Description: pdp11: mul/div unit for data (munit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-07-12 569 14.7 131013 xc6slx16-2 30 154 0 46 s 6.8
-- 2014-07-11 568 14.7 131013 xc6slx16-2 28 123 0 47 s 5.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.2.5 rename _gpr -> _gr
-- 2014-08-10 581 1.2.4 rename NEXT_ to N_; use c_cc_f_*
-- 2014-08-05 578 1.2.3 fix proc_div sensitivity list
-- 2014-08-03 577 1.2.2 use DTMP_POS rather signed(Q)>0 (xst bug for S-3)
-- 2014-07-26 575 1.2.1 fix proc_omux sensitivity list
-- 2014-07-12 569 1.2 merge DIV_ZERO+DIV_OVFL to DIV_QUIT; add S_DIV_SR
-- BUGFIX: fix divide logic, dr+q max neg issues
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from mbox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GR_DSRC : in slv16; -- 'src' data from GR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state (load dd_low)
S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle)
S_DIV_CR : in slbit; -- s_opg_div_cr state (remainder corr.)
S_DIV_SR : in slbit; -- s_opg_div_sr state (store remainder)
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: remainder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_QUIT : out slbit; -- division: abort (0/ or /0 or V=1)
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end pdp11_munit;
architecture syn of pdp11_munit is
signal R_DD_L : slv16 := (others=>'0'); -- divident, low order part
signal R_DDO_LT : slbit := '0'; -- original sign bit of divident
signal R_MAXFIX : slbit := '0'; -- maxfix flag for division
signal R_QO_LT : slbit := '0'; -- expected q sign for division
signal R_DIV_V : slbit := '0'; -- V flag for division
signal R_SHC : slv6 := (others=>'0'); -- shift counter for div and ash/c
signal R_C1 : slbit := '0'; -- first cycle indicator
signal R_MSBO : slbit := '0'; -- original sign bit for ash/c
signal R_ASH_V : slbit := '0'; -- V flag for ash/c
signal R_ASH_C : slbit := '0'; -- C flag for ash/c
signal N_DD_L : slv16 := (others=>'0');
signal N_DDO_LT : slbit := '0';
signal N_MAXFIX : slbit := '0';
signal N_QO_LT : slbit := '0';
signal N_DIV_V : slbit := '0';
signal N_SHC : slv6 := (others=>'0');
signal N_C1 : slbit := '0';
signal N_MSBO : slbit := '0';
signal N_ASH_V : slbit := '0';
signal N_ASH_C : slbit := '0';
signal SHC_TC_L : slbit := '0';
signal DDST_ZERO : slbit := '0';
signal DDST_NMAX : slbit := '0';
signal DSRC_ZERO : slbit := '0';
signal DSRC_ONES : slbit := '0';
signal DTMP_ZERO : slbit := '0';
signal DTMP_POS : slbit := '0';
signal DOUT_DIV : slv16 := (others=>'0');
signal DOUTE_DIV : slv16 := (others=>'0');
alias DR : slv16 is DDST; -- divisor (in DDST)
alias DD_H : slv16 is DSRC; -- divident, high order part (in DSRC)
alias Q : slv16 is DTMP; -- quotient (accumulated in DTMP)
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_DD_L <= N_DD_L;
R_DDO_LT <= N_DDO_LT;
R_MAXFIX <= N_MAXFIX;
R_QO_LT <= N_QO_LT;
R_DIV_V <= N_DIV_V;
R_SHC <= N_SHC;
R_C1 <= N_C1;
R_MSBO <= N_MSBO;
R_ASH_V <= N_ASH_V;
R_ASH_C <= N_ASH_C;
end if;
end process proc_regs;
proc_comm: process (DDST, DSRC, DTMP)
begin
DDST_ZERO <= '0';
DDST_NMAX <= '0';
DSRC_ZERO <= '0';
DSRC_ONES <= '0';
DTMP_ZERO <= '0';
DTMP_POS <= '0';
if unsigned(DDST) = 0 then
DDST_ZERO <= '1';
end if;
if DDST = "1000000000000000" then
DDST_NMAX <= '1';
end if;
if unsigned(DSRC) = 0 then
DSRC_ZERO <= '1';
end if;
if signed(DSRC) = -1 then
DSRC_ONES <= '1';
end if;
if unsigned(DTMP) = 0 then
DTMP_ZERO <= '1';
end if;
if signed(DTMP) > 0 then
DTMP_POS <= '1';
end if;
end process proc_comm;
proc_shc: process (DDST, R_SHC, R_C1,
S_DIV, S_DIV_CN, S_ASH, S_ASH_CN, S_ASHC, S_ASHC_CN)
begin
N_SHC <= R_SHC;
N_C1 <= R_C1;
if S_ASH='1' or S_ASHC='1' then
N_SHC <= DDST(5 downto 0);
N_C1 <= '1';
end if;
if S_DIV = '1' then
N_SHC <= "001111";
N_C1 <= '1';
end if;
if S_DIV_CN='1' or S_ASH_CN='1' or S_ASHC_CN='1' then
if R_SHC(5) = '0' then
N_SHC <= slv(unsigned(R_SHC) - 1);
else
N_SHC <= slv(unsigned(R_SHC) + 1);
end if;
N_C1 <= '0';
end if;
SHC_TC_L <= '0';
if unsigned(R_SHC) = 0 then
SHC_TC_L <= '1';
end if;
end process proc_shc;
proc_div: process (DDST, DSRC, DTMP, GR_DSRC, DR, DD_H, Q,
R_DD_L, R_DDO_LT, R_MAXFIX, R_QO_LT, R_DIV_V, R_SHC, R_C1,
S_DIV, S_DIV_CN, S_DIV_CR, S_DIV_SR,
DDST_ZERO, DDST_NMAX, DSRC_ZERO, DTMP_ZERO, DTMP_POS)
variable div_zero : slbit := '0';
variable div_ovfl : slbit := '0';
variable shftdd : slbit := '0';
variable subadd : slbit := '0';
variable dd_le : slbit := '0';
variable dd_ge : slbit := '0';
variable dd_gt : slbit := '0';
variable qbit : slbit := '0';
variable qbit_1 : slbit := '0';
variable qbit_n : slbit := '0';
variable dd_h_old : slv16 := (others=>'0'); -- dd_h before add/sub
variable dd_h_new : slv16 := (others=>'0'); -- dd_h after add/sub
begin
N_DD_L <= R_DD_L;
N_DDO_LT <= R_DDO_LT;
N_MAXFIX <= R_MAXFIX;
N_QO_LT <= R_QO_LT;
N_DIV_V <= R_DIV_V;
div_zero := '0';
div_ovfl := '0';
qbit_1 := not (DR(15) xor DD_H(15)); -- !(dr<0 ^ dd_h<0)
shftdd := not S_DIV_CR;
if shftdd = '1' then
dd_h_old := DD_H(14 downto 0) & R_DD_L(15);
else
dd_h_old := DD_H(15 downto 0);
end if;
if R_C1 = '1' then
subadd := qbit_1;
else
subadd := Q(0);
end if;
if subadd = '0' then
dd_h_new := slv(signed(dd_h_old) + signed(DR));
else
dd_h_new := slv(signed(dd_h_old) - signed(DR));
end if;
dd_le := '0';
if signed(dd_h_new) <= 0 then
dd_le := '1'; -- set if dd_new_h <= 0
end if;
dd_ge := '0';
if signed(dd_h_new) >= -1 then
dd_ge := '1'; -- set if dd_new_h >= -1
end if;
dd_gt := '0';
if dd_h_new(15) = '0' and
(unsigned(dd_h_new(14 downto 0))/=0 or
unsigned(R_DD_L(14 downto 0))/=0)
then
dd_gt := '1'; -- set if dd_new > 0
end if;
if R_DDO_LT = '0' then
qbit_n := DR(15) xor not dd_h_new(15); -- b_dr_lt ^ !b_dd_lt
else
if R_MAXFIX = '0' then
qbit_n := DR(15) xor dd_gt; -- b_dr_lt ^ b_dd_gt
else
qbit_n := dd_h_new(15); -- b_dd_lt
end if;
end if;
if S_DIV = '1' then
N_DDO_LT <= DD_H(15);
N_DD_L <= GR_DSRC;
N_MAXFIX <= '0';
if DDST_NMAX = '1' and GR_DSRC = "0000000000000000" then
N_MAXFIX <= '1'; -- b_dr_nmax && (ddi_l == 0)
end if;
N_QO_LT <= DD_H(15) xor DR(15); -- b_di_lt ^ b_dr_lt
end if;
if R_C1 = '1' then
div_zero := DDST_ZERO or
(DSRC_ZERO and DTMP_ZERO); -- note: DTMP here still dd_low !
if DDST_NMAX='0' and (DD_H(15) xor DD_H(14)) = '1' then
div_ovfl := '1'; -- !b_dr_nmax && (b_di_31 != b_di_30)
end if;
if R_DDO_LT = '0' then -- if (!b_di_lt)
if R_QO_LT = '0' then -- if (!b_qo_lt)
if dd_h_new(15) = '0' then -- if (!b_dd_lt)
div_ovfl := '1';
end if;
else -- else
if dd_le = '0' then -- if (!b_dd_le)
div_ovfl := '1';
end if;
end if;
else
if R_QO_LT = '0' then -- if (!b_qo_lt)
if dd_gt = '0' then -- if (!b_dd_gt)
div_ovfl := '1';
end if;
else -- else
if dd_ge = '0' then -- if (!b_dd_ge)
div_ovfl := '1';
end if;
end if;
end if;
N_DIV_V <= div_ovfl;
elsif S_DIV_SR = '1' then
if R_QO_LT='1' and DTMP_POS='1' then
div_ovfl := '1';
end if;
N_DIV_V <= div_ovfl;
end if;
if S_DIV_CN = '1' then
N_DD_L <= R_DD_L(14 downto 0) & '0';
end if;
if S_DIV_CN = '1' then
qbit := qbit_n;
else
qbit := qbit_1;
end if;
DIV_QUIT <= div_zero or div_ovfl;
DIV_CR <= R_MAXFIX or -- b_maxfix | (!(b_ddo_lt ^ (b_dr_lt ^ b_qbit)))
(not (R_DDO_LT xor (DR(15) xor Q(0))));
DIV_CQ <= R_MAXFIX or -- b_maxfix | (b_ddo_lt ^ b_dr_lt)
(R_DDO_LT xor DR(15));
DOUT_DIV <= dd_h_new;
DOUTE_DIV <= Q(14 downto 0) & qbit;
end process proc_div;
proc_ash: process (R_MSBO, R_ASH_V, R_ASH_C, R_SHC, DSRC, DTMP, FUNC,
S_ASH, S_ASH_CN, S_ASHC, S_ASHC_CN, SHC_TC_L)
begin
N_MSBO <= R_MSBO;
N_ASH_V <= R_ASH_V;
N_ASH_C <= R_ASH_C;
if S_ASH='1' or S_ASHC='1' then
N_MSBO <= DSRC(15);
N_ASH_V <= '0';
N_ASH_C <= '0';
end if;
if (S_ASH_CN='1' or S_ASHC_CN='1') and SHC_TC_L='0' then
if R_SHC(5) = '0' then -- left shift
if (R_MSBO xor DSRC(14))='1' then
N_ASH_V <= '1';
end if;
N_ASH_C <= DSRC(15);
else -- right shift
if FUNC = c_munit_func_ash then
N_ASH_C <= DSRC(0);
else
N_ASH_C <= DTMP(0);
end if;
end if;
end if;
end process proc_ash;
proc_omux: process (DSRC, DDST, DTMP, FUNC,
R_ASH_V, R_ASH_C, R_SHC, R_DIV_V, R_QO_LT,
DOUT_DIV, DOUTE_DIV,
DSRC_ZERO, DSRC_ONES, DTMP_ZERO, DDST_ZERO)
variable prod : slv32 := (others=>'0');
variable omux_sel : slv2 := "00";
variable ash_dout0 : slbit := '0';
variable mul_c : slbit := '0';
begin
prod := slv(signed(DSRC) * signed(DDST));
case FUNC is
when c_munit_func_mul =>
omux_sel := "00";
when c_munit_func_div =>
omux_sel := "01";
when c_munit_func_ash |c_munit_func_ashc =>
if R_SHC(5) = '0' then
omux_sel := "10";
else
omux_sel := "11";
end if;
when others => null;
end case;
if FUNC = c_munit_func_ash then
ash_dout0 := '0';
else
ash_dout0 := DTMP(15);
end if;
case omux_sel is
when "00" => -- MUL
DOUT <= prod(31 downto 16);
DOUTE <= prod(15 downto 0);
when "01" => -- DIV
DOUT <= DOUT_DIV;
DOUTE <= DOUTE_DIV;
when "10" => -- shift left
DOUT <= DSRC(14 downto 0) & ash_dout0;
DOUTE <= DTMP(14 downto 0) & "0";
when "11" => -- shift right
DOUT <= DSRC(15) & DSRC(15 downto 1);
DOUTE <= DSRC(0) & DTMP(15 downto 1);
when others => null;
end case;
mul_c := '0'; -- MUL C codes is set if
if DSRC(15) = '0' then
if DSRC_ZERO='0' or DTMP(15)='1' then -- for positive results when
mul_c := '1'; -- product > 2^15-1
end if;
else -- for negative results when
if DSRC_ONES='0' or DTMP(15)='0' then
mul_c := '1'; -- product < -2^15
end if;
end if;
case FUNC is
when c_munit_func_mul =>
CCOUT(c_cc_f_n) <= DSRC(15); -- N
CCOUT(c_cc_f_z) <= DSRC_ZERO and DTMP_ZERO; -- Z
CCOUT(c_cc_f_v) <= '0'; -- V=0
CCOUT(c_cc_f_c) <= mul_c; -- C
when c_munit_func_div =>
if DDST_ZERO = '1' then
CCOUT(c_cc_f_n) <= '0'; -- N=0 if div/0
CCOUT(c_cc_f_z) <= '1'; -- Z=1 if div/0
elsif R_DIV_V = '1' then
CCOUT(c_cc_f_n) <= R_QO_LT; -- N (send expected sign)
CCOUT(c_cc_f_z) <= '0'; -- Z (from unchanged reg) ??? veri
else
CCOUT(c_cc_f_n) <= DTMP(15); -- N (from Q (DTMP))
CCOUT(c_cc_f_z) <= DTMP_ZERO; -- Z (from Q (DTMP)) ??? verify
end if;
CCOUT(c_cc_f_v) <= R_DIV_V or DDST_ZERO; -- V
CCOUT(c_cc_f_c) <= DDST_ZERO; -- C (dst=0)
when c_munit_func_ash =>
CCOUT(c_cc_f_n) <= DSRC(15); -- N
CCOUT(c_cc_f_z) <= DSRC_ZERO; -- Z
CCOUT(c_cc_f_v) <= R_ASH_V; -- V
CCOUT(c_cc_f_c) <= R_ASH_C; -- C
when c_munit_func_ashc =>
CCOUT(c_cc_f_n) <= DSRC(15); -- N
CCOUT(c_cc_f_z) <= DSRC_ZERO and DTMP_ZERO;-- Z
CCOUT(c_cc_f_v) <= R_ASH_V; -- V
CCOUT(c_cc_f_c) <= R_ASH_C; -- C
when others => null;
end case;
end process proc_omux;
SHC_TC <= SHC_TC_L;
end syn;
| gpl-3.0 | 7c4dd3867bc3794215e791cb180566c5 | 0.449778 | 3.04353 | false | false | false | false |
wfjm/w11 | rtl/bplib/issi/tb/tb_is61wv5128bll.vhd | 1 | 5,217 | -- $Id: tb_is61wv5128bll.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_is61wv5128bll - sim
-- Description: Test bench for is61wv5128bll memory model
--
-- Dependencies: is61wv5128bll [UUT]
--
-- To test: is61wv5128bll
--
-- Verified (with tb_is61wv5128bll_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2017-06-04 906 - 0.34 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version (derived from tb_is61lv25616al)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_is61wv5128bll is
end tb_is61wv5128bll;
architecture sim of tb_is61wv5128bll is
signal CE_N : slbit := '1';
signal OE_N : slbit := '1';
signal WE_N : slbit := '1';
signal ADDR : slv19 := (others=>'0');
signal DATA : slv8 := (others=>'0');
begin
UUT : entity work.is61wv5128bll
port map (
CE_N => CE_N,
OE_N => OE_N,
WE_N => WE_N,
ADDR => ADDR,
DATA => DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_is61wv5128bll_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idtime : Delay_length := 0 ns;
variable imatch : boolean := false;
variable ival : slbit := '0';
variable ival8 : slv8 := (others=>'0');
variable ival19 : slv19 := (others=>'0');
variable ice : slbit := '0';
variable ioe : slbit := '0';
variable iwe : slbit := '0';
variable iaddr : slv19 := (others=>'0');
variable idata : slv8 := (others=>'0');
variable ide : slbit := '0';
variable idchk : slv8 := (others=>'0');
begin
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wdo " => -- wdo
read_ea(iline, idtime);
wait for idtime;
readtagval_ea(iline, "ce", imatch, ival);
if imatch then ice := ival; end if;
readtagval_ea(iline, "oe", imatch, ival);
if imatch then ioe := ival; end if;
readtagval_ea(iline, "we", imatch, ival);
if imatch then iwe := ival; end if;
readtagval_ea(iline, "a", imatch, ival19, 16);
if imatch then iaddr := ival19; end if;
readtagval_ea(iline, "de", imatch, ival);
if imatch then ide := ival; end if;
readtagval_ea(iline, "d", imatch, ival8, 16);
if imatch then idata := ival8; end if;
CE_N <= not ice;
OE_N <= not ioe;
WE_N <= not iwe;
ADDR <= iaddr;
if ide = '1' then
DATA <= idata;
else
DATA <= (others=>'Z');
end if;
write(oline, now, right, 12);
write(oline, string'(": wdo "));
write(oline, string'(" ce="));
write(oline, ice);
write(oline, string'(" oe="));
write(oline, ioe);
write(oline, string'(" we="));
write(oline, iwe);
write(oline, string'(" a="));
writegen(oline, iaddr, right, 5, 16);
write(oline, string'(" de="));
write(oline, ide);
if ide = '1' then
write(oline, string'(" d="));
writegen(oline, idata, right, 4, 16);
end if;
readtagval_ea(iline, "D", imatch, idchk, 16);
if imatch then
write(oline, string'(" D="));
writegen(oline, DATA, right, 4, 16);
write(oline, string'(" CHECK"));
if DATA = idchk then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL exp="));
writegen(oline, idchk, right, 4, 16);
end if;
end if;
writeline(output, oline);
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop;
write(oline, now, right, 12);
write(oline, string'(": DONE"));
writeline(output, oline);
wait; -- suspend proc_stim forever
-- no clock, sim will end
end process proc_stim;
end sim;
| gpl-3.0 | 19664b53dd51ff0d735a2471f37f625b | 0.492045 | 3.988532 | false | false | false | false |
wfjm/w11 | rtl/bplib/sysmon/sysmonx_rbus_arty.vhd | 1 | 8,459 | -- $Id: sysmonx_rbus_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sysmonx_rbus_arty - syn
-- Description: 7series XADC interface to rbus (arty pwrmon version)
--
-- Dependencies: sysmon_rbus_core
--
-- Test bench: -
--
-- Target Devices: 7series
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers: see sysmon_rbus_core and XADC user guide
--
-- XADC usage:
-- - build-in sensors: temp, Vccint, Vccaux, Vccbram
-- - arty power monitoring:
-- VAUX( 1) VPWR(0) <- 1/5.99 of JPR5V0 (main 5 V line)
-- VAUX( 2) VPWR(1) <- 1/16 of VU (external power jack)
-- VAUX( 9) VPWR(2) <- 250mV/A from shunt on JPR5V0 (main 5 V line)
-- VAUX(10) VPWR(3) <- 500mV/A from shunt on VCC0V95 (FPGA core)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
-- ----------------------------------------------------------------------------
entity sysmonx_rbus_arty is -- XADC interface to rbus (for arty)
generic (
INIT_OT_LIMIT : real := 125.0; -- INIT_53
INIT_OT_RESET : real := 70.0; -- INIT_57
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types)
INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12; -- xadc: die temp
VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon)
VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon)
);
end sysmonx_rbus_arty;
architecture syn of sysmonx_rbus_arty is
constant vpwrmap_0 : integer := 1; -- map vpwr(0) -> xadc vaux
constant vpwrmap_1 : integer := 2; -- map vpwr(1) -> xadc vaux
constant vpwrmap_2 : integer := 9; -- map vpwr(2) -> xadc vaux
constant vpwrmap_3 : integer := 10; -- map vpwr(3) -> xadc vaux
constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio
constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16)));
constant init_49 : bv16 := (vpwrmap_0 => '1', -- seq #1: (enable pwrmon)
vpwrmap_1 => '1',
vpwrmap_2 => '1',
vpwrmap_3 => '1',
others => '0');
signal VAUXN : slv16 := (others=>'0');
signal VAUXP : slv16 := (others=>'0');
signal SM_DEN : slbit := '0';
signal SM_DWE : slbit := '0';
signal SM_DADDR : slv7 := (others=>'0');
signal SM_DI : slv16 := (others=>'0');
signal SM_DO : slv16 := (others=>'0');
signal SM_DRDY : slbit := '0';
signal SM_EOS : slbit := '0';
signal SM_EOC : slbit := '0';
signal SM_RESET : slbit := '0';
signal SM_CHAN : slv5 := (others=>'0');
signal SM_ALM : slv8 := (others=>'0');
signal SM_OT : slbit := '0';
signal SM_JTAGLOCKED : slbit := '0';
signal SM_JTAGMODIFIED : slbit := '0';
signal SM_JTAGBUSY : slbit := '0';
begin
SM : XADC
generic map (
INIT_40 => xadc_init_40_default, -- conf #0
INIT_41 => xadc_init_41_default, -- conf #1
INIT_42 => init_42,
INIT_43 => x"0000", -- test #0 - don't use, stay 0
INIT_44 => x"0000", -- test #1 - "
INIT_45 => x"0000", -- test #2 - "
INIT_46 => x"0000", -- test #3 - "
INIT_47 => x"0000", -- test #4 - "
INIT_48 => xadc_init_48_default, -- seq #0: sel 0
INIT_49 => init_49, -- seq #1: sel 1 (enable pwrmon)
INIT_4A => xadc_init_4a_default, -- seq #2: avr 0
INIT_4B => x"0000", -- seq #3: avr 1: "
INIT_4C => x"0000", -- seq #4: mode 0: unipolar
INIT_4D => x"0000", -- seq #5: mode 1: "
INIT_4E => x"0000", -- seq #6: time 0: fast
INIT_4F => x"0000", -- seq #7: time 1: "
INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0)
INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1)
INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2)
INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT
INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0)
INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1)
INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2)
INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT
INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3)
INIT_59 => x"0000", -- alm #09: ccpint up (4)
INIT_5A => x"0000", -- alm #10: ccpaux up (5)
INIT_5B => x"0000", -- alm #11: ccdram up (6)
INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3)
INIT_5D => x"0000", -- alm #13: ccpint low (4)
INIT_5E => x"0000", -- alm #14: ccpaux low (5)
INIT_5F => x"0000", -- alm #15: ccdram low (6)
-- IS_CONVSTCLK_INVERTED => '0',
-- IS_DCLK_INVERTED => '0',
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "sysmon_stim")
port map (
DCLK => CLK,
DEN => SM_DEN,
DWE => SM_DWE,
DADDR => SM_DADDR,
DI => SM_DI,
DO => SM_DO,
DRDY => SM_DRDY,
EOC => SM_EOC, -- connected for tb usage
EOS => SM_EOS,
BUSY => open,
RESET => SM_RESET,
CHANNEL => SM_CHAN, -- connected for tb usage
MUXADDR => open,
ALM => SM_ALM,
OT => SM_OT,
CONVST => '0',
CONVSTCLK => '0',
JTAGBUSY => SM_JTAGBUSY,
JTAGLOCKED => SM_JTAGLOCKED,
JTAGMODIFIED => SM_JTAGMODIFIED,
VAUXN => VAUXN,
VAUXP => VAUXP,
VN => '0',
VP => '0'
);
VAUXN <= (vpwrmap_0 => VPWRN(0),
vpwrmap_1 => VPWRN(1),
vpwrmap_2 => VPWRN(2),
vpwrmap_3 => VPWRN(3),
others=>'0');
VAUXP <= (vpwrmap_0 => VPWRP(0),
vpwrmap_1 => VPWRP(1),
vpwrmap_2 => VPWRP(2),
vpwrmap_3 => VPWRP(3),
others=>'0');
SMRB : sysmon_rbus_core
generic map (
DAWIDTH => 7,
ALWIDTH => 8,
TEWIDTH => 12,
IBASE => x"78",
RB_ADDR => RB_ADDR)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
SM_DEN => SM_DEN,
SM_DWE => SM_DWE,
SM_DADDR => SM_DADDR,
SM_DI => SM_DI,
SM_DO => SM_DO,
SM_DRDY => SM_DRDY,
SM_EOS => SM_EOS,
SM_RESET => SM_RESET,
SM_ALM => SM_ALM,
SM_OT => SM_OT,
SM_JTAGBUSY => SM_JTAGBUSY,
SM_JTAGLOCKED => SM_JTAGLOCKED,
SM_JTAGMODIFIED => SM_JTAGMODIFIED,
TEMP => TEMP
);
ALM <= SM_ALM;
OT <= SM_OT;
end syn;
| gpl-3.0 | 9e2580766afa4165cb0ae4920648cbfe | 0.475352 | 3.184864 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/tbd_serport_uart_rx.vhd | 1 | 2,363 | -- $Id: tbd_serport_uart_rx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_uart_rx - syn
-- Description: Wrapper for serport_uart_rx to avoid records. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: serport_uart_rx
--
-- To test: serport_uart_rx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 26 67 0 - t 8.17
-- 2007-10-27 92 9.1 J30 xc3s1000-4 26 67 0 - t 8.25
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 29 90 0 47 s 8.45
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 31 92 0 - s 8.25
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity tbd_serport_uart_rx is -- serial port uart rx [tb design]
-- generic: CDWIDTH=5
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv5; -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit -- receiver active
);
end tbd_serport_uart_rx;
architecture syn of tbd_serport_uart_rx is
begin
UART : serport_uart_rx
generic map (
CDWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
end syn;
| gpl-3.0 | 508752ae49cfc5dfaf760738da674e51 | 0.506559 | 3.585736 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibd_iist.vhd | 1 | 28,642 | -- $Id: ibd_iist.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_iist - syn
-- Description: ibus dev(loc): IIST
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 112 510 0 291 s 15.8
-- 2010-10-17 314 12.1 M53d xc3s1000-4 111 504 0 290 s 15.6
-- 2009-06-01 223 10.1.03 K39 xc3s1000-4 111 439 0 256 s 9.8
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 111 449 0 258 s 13.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 0.8.2 don't init N_REGS (vivado fix for fsm inference)
-- 2011-11-18 427 0.8.1 now numeric_std clean
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im
-- also for dcf_dcf and exc_rte; add iist_mreq and
-- iist_sreq, boot and lock interfaces
-- 2009-06-05 223 0.6 level interrupt, parity logic, exc.ui logic
-- st logic modified (partially tested)
-- 2009-06-01 221 0.5 Initial version (untested, lock&boot missing)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibd_iist is -- ibus dev(loc): IIST
-- fixed address: 177500
generic (
SID : slv2 := "00"); -- self id
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit; -- interrupt acknowledge
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's)
IIST_OUT : out iist_line_type; -- iist output
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests
IIST_SRES : in iist_sres_type -- cpu->iist responses
);
end ibd_iist;
architecture syn of ibd_iist is
constant ibaddr_iist : slv16 := slv(to_unsigned(8#177500#,16));
constant tdlysnd : natural := 150; -- send delay timer
constant ibaddr_acr : slv1 := "0"; -- acr address offset
constant ibaddr_adr : slv1 := "1"; -- adr address offset
constant acr_ibf_clr : integer := 15; -- clear flag
subtype acr_ibf_sid is integer range 9 downto 8; -- self id
subtype acr_ibf_ac is integer range 3 downto 0; -- ac code
constant ac_pge : slv4 := "0000"; -- 0 program generated enables
constant ac_pgc : slv4 := "0001"; -- 1 program generated control/status
constant ac_ste : slv4 := "0010"; -- 2 sanity timer enables
constant ac_stc : slv4 := "0011"; -- 3 sanity timer control/status
constant ac_msk : slv4 := "0100"; -- 4 input masks
constant ac_pgf : slv4 := "0101"; -- 5 program generated flags
constant ac_stf : slv4 := "0110"; -- 6 sanity timer flags
constant ac_dcf : slv4 := "0111"; -- 7 disconnect flags
constant ac_exc : slv4 := "1000"; -- 10 exceptions
constant ac_mtc : slv4 := "1101"; -- 15 maintenance control
subtype pge_ibf_pbe is integer range 11 downto 8; -- pg boot ena
subtype pge_ibf_pie is integer range 3 downto 0; -- pg int ena
constant pgc_ibf_err : integer := 15; -- error
constant pgc_ibf_grj : integer := 14; -- go reject
constant pgc_ibf_pgrmr : integer := 13; -- pg req refused
constant pgc_ibf_strmr : integer := 12; -- st req refused
constant pgc_ibf_rdy : integer := 11; -- ready flag
subtype pgc_ibf_sid is integer range 9 downto 8; -- self id
constant pgc_ibf_ip : integer := 3; -- int pending
constant pgc_ibf_ie : integer := 2; -- int enable
constant pgc_ibf_ptp : integer := 1; -- pg parity
constant pgc_ibf_go : integer := 0; -- go flag
subtype ste_ibf_sbe is integer range 11 downto 8; -- st boot enable
subtype ste_ibf_sie is integer range 3 downto 0; -- st int enable
subtype stc_ibf_count is integer range 15 downto 8; -- count
constant stc_ibf_tmo : integer := 3; -- timeout
constant stc_ibf_lke : integer := 2; -- lockup enable
constant stc_ibf_stp : integer := 1; -- st parity
constant stc_ibf_enb : integer := 0; -- enable
subtype msk_ibf_bm is integer range 11 downto 8; -- boot mask
subtype msk_ibf_im is integer range 3 downto 0; -- int mask
subtype pgf_ibf_pbf is integer range 11 downto 8; -- boot flags
subtype pgf_ibf_pif is integer range 3 downto 0; -- int flags
subtype stf_ibf_sbf is integer range 11 downto 8; -- boot flags
subtype stf_ibf_sif is integer range 3 downto 0; -- int flags
subtype dcf_ibf_brk is integer range 11 downto 8; -- break flags
subtype dcf_ibf_dcf is integer range 3 downto 0; -- disconnect flags
subtype exc_ibf_ui is integer range 11 downto 8; -- unexpected int
subtype exc_ibf_rte is integer range 3 downto 0; -- transm. error
constant mtc_ibf_mttp : integer := 11; -- maint. type
constant mtc_ibf_mfrm : integer := 10; -- maint. frame err
subtype mtc_ibf_mid is integer range 9 downto 8; -- maint. id
constant mtc_ibf_dsbt : integer := 3; -- disable boot
constant mtc_ibf_enmxd : integer := 2; -- enable maint mux
constant mtc_ibf_enmlp : integer := 1; -- enable maint loop
constant mtc_ibf_dsdrv : integer := 0; -- disable driver
type state_type is (
s_idle, -- idle state
s_clear, -- handle acr clr
s_stsnd, -- handle st transmit
s_pgsnd -- handle pg transmit
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
acr_ac : slv4; -- acr: ac
pge_pbe : slv4; -- pge: pg boot ena
pge_pie : slv4; -- pge: pg int ena
pgc_grj : slbit; -- pgc: go reject
pgc_pgrmr : slbit; -- pgc: pg req refused
pgc_strmr : slbit; -- pgc: st req refused
pgc_ie : slbit; -- pgc: int enable
pgc_ptp : slbit; -- pgc: pg parity
ste_sbe : slv4; -- ste: st boot enable
ste_sie : slv4; -- ste: st int enable
stc_count : slv8; -- stc: count
stc_tmo : slbit; -- stc: timeout
stc_lke : slbit; -- stc: lockup enable
stc_stp : slbit; -- stc: st parity
stc_enb : slbit; -- stc: enable
msk_bm : slv4; -- msk: boot mask
msk_im : slv4; -- msk: int mask
pgf_pbf : slv4; -- pgf: boot flags
pgf_pif : slv4; -- pgf: int flags
stf_sbf : slv4; -- stf: boot flags
stf_sif : slv4; -- stf: int flags
dcf_brk : slv4; -- dcf: break flags
dcf_dcf : slv4; -- dcf: disconnect flags
exc_ui : slv4; -- exc: unexpected int
exc_rte : slv4; -- exc: transm. error
mtc_mttp : slbit; -- mtc: maint. type
mtc_mfrm : slbit; -- mtc: maint. frame err
mtc_mid : slv2; -- mtc: maint. id
mtc_dsbt : slbit; -- mtc: disable boot
mtc_enmxd : slbit; -- mtc: enable maint mux
mtc_enmlp : slbit; -- mtc: enable maint loop
mtc_dsdrv : slbit; -- mtc: disable driver
state : state_type; -- state
req_clear : slbit; -- request clear
req_stsnd : slbit; -- request sanity timer transmit
req_pgsnd : slbit; -- request prog. gen. transmit
tcnt256 : slv8; -- usec clock divider for st clock
tcntsnd : slv8; -- timer for transmit delay
req_lock : slbit; -- cpu lock request
req_boot : slbit; -- cpu boot request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"0000", -- acr_ac
"0000","0000", -- pge_pbe, pge_pie
'0', -- pgc_grj
'0','0', -- pgc_pgrmr, pgc_strmr
'0','0', -- pgc_ie, pgc_ptp
"0000","0000", -- ste_sbe, ste_sie
(others=>'0'), -- stc_count
'0','0', -- stc_tmo, stc_lke
'0','0', -- stc_stp, stc_enb
"0000","0000", -- msk_bm, msk_im
"0000","0000", -- pgf_pbf, pgf_pif
"0000","0000", -- stf_sbf, stf_sif
"0000","0000", -- dcf_brk, dcf_dcf
"0000","0000", -- exc_ui, exc_rte
'0','0', -- mtc_mttp, mtc_mfrm
"00", -- mtc_mid
'0','0', -- mtc_dsbt, mtc_enmxd
'0','0', -- mtc_enmlp, mtc_dsdrv
s_idle, -- state
'0', -- req_clear
'0','0', -- req_stsnd, req_pgsnd
(others=>'0'), -- tcnt256
(others=>'0'), -- tcntsnd
'0','0' -- req_lock, req_boot
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' or -- BRESET is 1 for system and ibus reset
R_REGS.req_clear='1' then
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.pgf_pbf <= N_REGS.pgf_pbf; -- don't reset pg boot flags
R_REGS.stf_sbf <= N_REGS.stf_sbf; -- don't reset st boot flags
R_REGS.tcnt256 <= N_REGS.tcnt256; -- don't reset st clock divider
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_USEC, IB_MREQ,
IIST_BUS(0), IIST_BUS(1), IIST_BUS(2), IIST_BUS(3),
IIST_SRES)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable int_or : slbit := '0';
variable tcnt256_end : slbit := '0';
variable tcntsnd_end : slbit := '0';
variable eff_id : slv2 := "00";
variable eff_bus : iist_bus_type := iist_bus_init;
variable par_err : slbit := '0';
variable act_ibit : slbit := '0';
variable act_bbit : slbit := '0';
variable iout : iist_line_type := iist_line_init;
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
int_or := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr;
for i in r.dcf_dcf'range loop
int_or := int_or or r.dcf_dcf(i) or
r.exc_rte(i) or
r.pgf_pif(i) or
r.stf_sif(i);
end loop; -- i
tcnt256_end := '0';
if CE_USEC='1' and r.stc_enb='1'then -- if st enabled on every usec
n.tcnt256 := slv(unsigned(r.tcnt256) + 1); -- advance 8 bit counter
if unsigned(r.tcnt256) = 255 then -- if wrap
tcnt256_end := '1'; -- signal 256 usec passed
end if;
end if;
tcntsnd_end := '0';
n.tcntsnd := slv(unsigned(r.tcntsnd) + 1); -- advance send timer counter
if unsigned(r.tcntsnd) = tdlysnd-1 then -- if delay time reached
tcntsnd_end := '1'; -- signal end
end if;
eff_id := SID; -- effective self-id, normally SID
if r.mtc_enmxd = '1' then -- if maint. mux enabled
eff_id := r.mtc_mid; -- use maint. id
end if;
eff_bus := IIST_BUS;
par_err := '0';
act_ibit := '0';
act_bbit := '0';
iout := iist_line_init; -- default state of out line
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_iist(12 downto 2) then
n.ibsel := '1';
end if;
-- internal state machine
case r.state is
when s_idle => -- idle state
n.tcntsnd := (others=>'0'); -- keep send delay timer zero
if r.req_stsnd = '1' then -- sanity timer request pending
n.state := s_stsnd;
elsif r.req_pgsnd = '1' then -- prog. gen. request pending
n.state := s_pgsnd;
end if;
when s_clear => -- handle acr clr
ibhold := r.ibsel; -- keep req pending if selected
-- r.req_clear is set when in this state and cause a reset in prog_regs
-- --> n.req_clear := '0';
-- --> n.state := s_idle;
when s_stsnd => -- handle st transmit
if tcntsnd_end = '1' then -- send delay expired
n.req_stsnd := '0'; -- clear st transmit request
iout.req := '1'; -- do transmit
iout.stf := '1'; -- signal type = st
iout.imask := r.ste_sie; -- int enables
iout.bmask := r.ste_sbe; -- boot enables
iout.par := not r.stc_stp; -- send parity (odd incl. stf!)
iout.frm := '0'; -- frame always ok
n.state := s_idle;
end if;
when s_pgsnd => -- handle pg transmit
if tcntsnd_end = '1' then -- send delay expired
n.req_pgsnd := '0'; -- clear pg transmit request
iout.req := '1'; -- do transmit
iout.stf := '0'; -- signal type = pg
iout.imask := r.pge_pie; -- int enables
iout.bmask := r.pge_pbe; -- boot enables
iout.par := r.pgc_ptp; -- send parity
iout.frm := '0'; -- frame always ok
n.state := s_idle;
end if;
when others => null;
end case;
if r.mtc_enmxd = '1' then -- if maintenance mux enabled
iout.stf := r.mtc_mttp; -- force type from mtc_mttp
iout.frm := r.mtc_mfrm; -- force frame from mtc_mfrm
end if;
-- ibus transactions
if r.ibsel = '1' and ibhold='0' then
if IB_MREQ.addr(1 downto 1) = "0" then -- ACR -- access control reg -----
idout(acr_ibf_sid) := SID;
idout(acr_ibf_ac) := r.acr_ac;
if ibw1 = '1' then
if IB_MREQ.din(acr_ibf_clr) = '1' then
n.req_clear := '1';
n.state := s_clear;
end if;
end if;
if ibw0 = '1' then
n.acr_ac := IB_MREQ.din(acr_ibf_ac);
end if;
else -- ADR -- access data reg --------
case r.acr_ac is
when ac_pge => -- PGE -- program gen enables --------
idout(pge_ibf_pbe) := r.pge_pbe;
idout(pge_ibf_pie) := r.pge_pie;
if IB_MREQ.we = '1' then
if r.req_pgsnd = '0' then -- no pg transmit pending
if ibw1 = '1' then
n.pge_pbe := IB_MREQ.din(pge_ibf_pbe);
end if;
if ibw0 = '1' then
n.pge_pie := IB_MREQ.din(pge_ibf_pie);
end if;
else -- if collision with pg transmit
n.pgc_pgrmr := '1'; -- set pge refused flag
end if;
end if;
when ac_pgc => -- PGC -- program gen control/status -
idout(pgc_ibf_err) := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr;
idout(pgc_ibf_grj) := r.pgc_grj;
idout(pgc_ibf_pgrmr) := r.pgc_pgrmr;
idout(pgc_ibf_strmr) := r.pgc_strmr;
idout(pgc_ibf_rdy) := not r.req_pgsnd;
idout(pgc_ibf_sid) := eff_id;
idout(pgc_ibf_ip) := int_or;
idout(pgc_ibf_ie) := r.pgc_ie;
idout(pgc_ibf_ptp) := r.pgc_ptp;
if ibw1 = '1' then
if IB_MREQ.din(pgc_ibf_err) = '1' then -- '1' written into ERR
n.pgc_grj := '0'; -- clears GRJ
n.pgc_pgrmr := '0'; -- clears PGRMR
n.pgc_strmr := '0'; -- clears STRMR
end if;
end if;
if ibw0 = '1' then
n.pgc_ie := IB_MREQ.din(pgc_ibf_ie);
n.pgc_ptp := IB_MREQ.din(pgc_ibf_ptp);
if IB_MREQ.din(pgc_ibf_go) = '1' then -- GO bit set
if r.req_pgsnd = '0' then -- if ready (no pgsnd pend)
n.req_pgsnd := '1'; -- request pgsnd
else -- if not ready
n.pgc_grj := '1'; -- set go reject flag
end if;
end if;
end if;
when ac_ste => -- STE -- sanity timer enables -------
idout(ste_ibf_sbe) := r.ste_sbe;
idout(ste_ibf_sie) := r.ste_sie;
if IB_MREQ.we = '1' then
if r.req_stsnd = '0' then -- no st transmit pending
if ibw1 = '1' then
n.ste_sbe := IB_MREQ.din(ste_ibf_sbe);
end if;
if ibw0 = '1' then
n.ste_sie := IB_MREQ.din(ste_ibf_sie);
end if;
else -- if collision with st transmit
n.pgc_strmr := '1'; -- set ste refused flag
end if;
end if;
when ac_stc => -- STC -- sanity timer control/status
idout(stc_ibf_count) := r.stc_count;
idout(stc_ibf_tmo) := r.stc_tmo;
idout(stc_ibf_lke) := r.stc_lke;
idout(stc_ibf_stp) := r.stc_stp;
idout(stc_ibf_enb) := r.stc_enb;
if ibw1 = '1' then
n.stc_count := IB_MREQ.din(stc_ibf_count); -- reset st count
n.tcnt256 := (others=>'0'); -- reset usec count
end if;
if ibw0 = '1' then
if IB_MREQ.din(stc_ibf_tmo) = '1' then -- 1 written into TMO
n.stc_tmo := '0';
end if;
n.stc_lke := IB_MREQ.din(stc_ibf_lke);
n.stc_stp := IB_MREQ.din(stc_ibf_stp);
n.stc_enb := IB_MREQ.din(stc_ibf_enb);
end if;
when ac_msk => -- MSK -- input masks ----------------
idout(msk_ibf_bm) := r.msk_bm;
idout(msk_ibf_im) := r.msk_im;
if ibw1 = '1' then
n.msk_bm := IB_MREQ.din(msk_ibf_bm);
end if;
if ibw0 = '1' then
n.msk_im := IB_MREQ.din(msk_ibf_im);
end if;
when ac_pgf => -- PGF -- program generated flags ----
idout(pgf_ibf_pbf) := r.pgf_pbf;
idout(pgf_ibf_pif) := r.pgf_pif;
if ibw1 = '1' then
n.pgf_pbf := r.pgf_pbf and not IB_MREQ.din(pgf_ibf_pbf);
end if;
if ibw0 = '1' then
n.pgf_pif := r.pgf_pif and not IB_MREQ.din(pgf_ibf_pif);
end if;
when ac_stf => -- STF -- sanity timer flags ---------
idout(stf_ibf_sbf) := r.stf_sbf;
idout(stf_ibf_sif) := r.stf_sif;
if ibw1 = '1' then
n.stf_sbf := r.stf_sbf and not IB_MREQ.din(stf_ibf_sbf);
end if;
if ibw0 = '1' then
n.stf_sif := r.stf_sif and not IB_MREQ.din(stf_ibf_sif);
end if;
when ac_dcf => -- DCE -- disconnect flags -----------
idout(dcf_ibf_brk) := r.dcf_brk;
idout(dcf_ibf_dcf) := r.dcf_dcf;
if ibw0 = '1' then
n.dcf_dcf := r.dcf_dcf and not IB_MREQ.din(dcf_ibf_dcf);
end if;
when ac_exc => -- EXC -- exceptions -----------------
idout(exc_ibf_ui) := r.exc_ui;
idout(exc_ibf_rte) := r.exc_rte;
if ibw1 = '1' then
n.exc_ui := r.exc_ui and not IB_MREQ.din(exc_ibf_ui);
end if;
if ibw0 = '1' then
n.exc_rte := r.exc_rte and not IB_MREQ.din(exc_ibf_rte);
end if;
when ac_mtc => -- MTC -- maintenance control --------
idout(mtc_ibf_mttp) := r.mtc_mttp;
idout(mtc_ibf_mfrm) := r.mtc_mfrm;
idout(mtc_ibf_mid) := r.mtc_mid;
idout(mtc_ibf_dsbt) := r.mtc_dsbt;
idout(mtc_ibf_enmxd) := r.mtc_enmxd;
idout(mtc_ibf_enmlp) := r.mtc_enmlp;
idout(mtc_ibf_dsdrv) := r.mtc_dsdrv;
if ibw1 = '1' then
n.mtc_mttp := IB_MREQ.din(mtc_ibf_mttp);
n.mtc_mfrm := IB_MREQ.din(mtc_ibf_mfrm);
n.mtc_mid := IB_MREQ.din(mtc_ibf_mid);
end if;
if ibw0 = '1' then
n.mtc_dsbt := IB_MREQ.din(mtc_ibf_dsbt);
n.mtc_enmxd := IB_MREQ.din(mtc_ibf_enmxd);
n.mtc_enmlp := IB_MREQ.din(mtc_ibf_enmlp);
n.mtc_dsdrv := IB_MREQ.din(mtc_ibf_dsdrv);
end if;
when others => -- access to undefined AC code -------
null;
end case;
if unsigned(r.acr_ac) <= unsigned(ac_exc) then -- if ac 0,..,10
if IB_MREQ.rmw = '0' then -- if not 1st part of rmw
n.acr_ac := slv(unsigned(r.acr_ac) + 1); -- autoincrement
end if;
end if;
end if;
end if;
-- sanity timer
if tcnt256_end = '1' then -- if 256 usec expired (and enabled)
n.stc_count := slv(unsigned(r.stc_count) - 1);
if unsigned(r.stc_count) = 0 then -- if sanity timer expired
n.stc_tmo := '1'; -- set timeout flag
n.req_stsnd := '1'; -- request st transmit
if r.stc_lke = '1' then -- if lockup enabled
n.req_lock := '1'; -- request lockup
end if;
end if;
end if;
-- process iist bus inputs
if r.mtc_enmlp = '1' then -- if mainentance loop
for i in eff_bus'range loop
eff_bus(i) := iout; -- local signal on all input ports
eff_bus(i).dcf := '0'; -- all ports considered connected
end loop; -- i
end if;
for i in eff_bus'range loop
par_err := eff_bus(i).stf xor
eff_bus(i).imask(0) xor eff_bus(i).imask(1) xor
eff_bus(i).imask(2) xor eff_bus(i).imask(3) xor
eff_bus(i).bmask(0) xor eff_bus(i).bmask(1) xor
eff_bus(i).bmask(2) xor eff_bus(i).bmask(3) xor
not eff_bus(i).par;
act_ibit := eff_bus(i).imask(to_integer(unsigned(eff_id)));
act_bbit := eff_bus(i).bmask(to_integer(unsigned(eff_id)));
n.dcf_brk(i) := eff_bus(i).dcf; -- trace dcf state in brk
if eff_bus(i).dcf = '1' then -- if disconnected
if r.msk_im(i) = '0' then -- if not disabled
n.dcf_dcf(i) := '1'; -- set dcf flag
end if;
else -- if connected
if eff_bus(i).req = '1' then -- request received ?
if eff_bus(i).frm='1' or -- frame error seen ?
par_err='1' then -- parity error seen ?
if r.msk_im(i) = '0' then -- if not disabled
n.exc_rte(i) := '1'; -- set rte flag
end if;
else -- here if valid request seen
if act_ibit = '1' then -- interrupt request
if r.msk_im(i) = '1' then -- if disabled
n.exc_ui(i) := '1'; -- set ui flag
else -- if enabled
n.req_lock := '0'; -- release lock
if eff_bus(i).stf = '0' then -- and pg request
n.pgf_pif(i) := '1'; -- set pif flag
else -- and st request
n.stf_sif(i) := '1'; -- set sif flag
end if;
end if;
end if; -- act_ibit='1'
if act_bbit = '1' then -- boot request
if r.msk_bm(i) = '1' then -- if msk disabled
n.exc_ui(i) := '1'; -- set ui flag
else -- if msk enabled
if r.mtc_dsbt = '0' then -- if mtc enabled
n.req_lock := '0'; -- release lock
n.req_boot := '1'; -- request boot
end if;
if eff_bus(i).stf = '0' then -- and pg request
n.pgf_pbf(i) := '1'; -- set pbf flag
else -- and st request
n.stf_sbf(i) := '1'; -- set sbf flag
end if;
end if;
end if; -- act_bbit='1'
end if;
end if;
end if;
end loop;
-- process cpu->iist responses
if IIST_SRES.ack_lock = '1' then
n.req_lock := '0';
end if;
if IIST_SRES.ack_boot = '1' then
n.req_boot := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
EI_REQ <= r.pgc_ie and int_or;
if r.mtc_dsdrv = '1' then -- if driver disconnected
iout.dcf := '1'; -- set dcf flag
iout.req := '0'; -- suppress requests
end if;
IIST_OUT <= iout; -- and finally send it out...
IIST_MREQ.lock <= r.req_lock;
IIST_MREQ.boot <= r.req_boot;
end process proc_next;
end syn;
| gpl-3.0 | 59d14c57ea2c4f81d16fc4ecd02f8aae | 0.444592 | 3.741607 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4d/tb/sys_conf_sim.vhd | 1 | 1,708 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys4d_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | a2ad49ef5e499b8cec52bf400c864dbd | 0.618267 | 3.634043 | false | false | false | false |
wfjm/w11 | rtl/bplib/artys7/tb/tb_artys7_core.vhd | 1 | 1,688 | -- $Id: tb_artys7_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_artys7_core - sim
-- Description: Test bench for artys7 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any artys7 target
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-05 1038 1.0 Initial version (derived from tb_artya7_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_artys7_core is
port (
I_SWI : out slv4; -- artys7 switches
I_BTN : out slv4 -- artys7 buttons
);
end tb_artys7_core;
architecture sim of tb_artys7_core is
signal R_SWI : slv4 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
| gpl-3.0 | 8255ce81f052c4ab618742771148d39a | 0.558057 | 3.19697 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_dmhbpt.vhd | 1 | 3,284 | -- $Id: pdp11_dmhbpt.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmhbpt - syn
-- Description: pdp11: debug&moni: hardware breakpoint
--
-- Dependencies: pdp11_dmhbpt_unit
-- rbus/rb_sres_or_4
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.36
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-07-12 700 14.7 131013 xc6slx16-2 78 133 0 42 s 3.8 (N=2)
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-08-17 1203 1.0.2 fix for ghdl V0.36 -Whide warnings
-- 2019-06-02 1159 1.0.1 use rbaddr_ constants
-- 2015-07-19 702 1.0 Initial version
-- 2015-07-05 698 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dmhbpt is -- debug&moni: hardware breakpoint
generic (
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
NUNIT : natural := 2);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
HBPT : out slbit -- hw break flag
);
end pdp11_dmhbpt;
architecture syn of pdp11_dmhbpt is
type sres_array_type is array (3 downto 0) of rb_sres_type;
signal SRES_ARRAY : sres_array_type:= (others=>rb_sres_init);
signal HBPT_SUM : slv(NUNIT-1 downto 0) := (others=>'0');
constant hbptzero : slv(HBPT_SUM'range) := (others=>'0');
begin
assert NUNIT>=1 and NUNIT<=4
report "assert(NUNIT>=1 and NUNIT<=4): unsupported NUNIT"
severity failure;
GU: for i in NUNIT-1 downto 0 generate
HB : pdp11_dmhbpt_unit
generic map (
RB_ADDR => RB_ADDR,
INDEX => i)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => SRES_ARRAY(i),
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
HBPT => HBPT_SUM(i)
);
end generate GU;
GD: for i in 3 downto NUNIT generate
SRES_ARRAY(i) <= rb_sres_init;
end generate GD;
RB_SRES_OR : rb_sres_or_4
port map (
RB_SRES_1 => SRES_ARRAY(0),
RB_SRES_2 => SRES_ARRAY(1),
RB_SRES_3 => SRES_ARRAY(2),
RB_SRES_4 => SRES_ARRAY(3),
RB_SRES_OR => RB_SRES
);
HBPT <= '1' when HBPT_SUM /= hbptzero else '0';
end syn;
| gpl-3.0 | 32c966b99688d8d974858ee87a397810 | 0.539281 | 3.267662 | false | false | false | false |
abcsds/Micros | RS232Read_16/fsmread.vhd | 4 | 3,088 | -- This module controls reading process
library IEEE;
use IEEE.std_logic_1164.all;
entity FSMRead is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
FBaud : in std_logic;
ENC : out std_logic;
EOR : out std_logic;
LDx : out std_logic
);
end FSMRead;
architecture simple of FSMRead is
signal Qp, Qn : std_logic_vector(4 downto 0);
begin
COMB: process(Qp,Rx,FBaud)
begin
case Qp is
when "00000"=>
if(Rx= '1')then
Qn<= Qp;
else
Qn<= "00001";
end if;
ENC<= '0';
EOR<= '1';
LDx<= '0';
when "00001"=> -- Start
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "00010";
end if;
ENC<= '1'; -- Enable FBaud
EOR<= '0';
LDx<= '0';
when "00010"=>
Qn<= "00011";
ENC<= '1';
EOR<= '0';
LDx<= '1'; -- Load Bit 0
when "00011"=>
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "00100";
end if;
ENC<= '1';
EOR<= '0';
LDx<= '0';
when "00100"=>
Qn<= "00101";
ENC<= '1';
EOR<= '0';
LDx<= '1'; -- Load Bit 1
when "00101"=>
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "00110";
end if;
ENC<= '1';
EOR<= '0';
LDx<= '0';
when "00110"=>
Qn<= "00111";
ENC<= '1';
EOR<= '0';
LDx<= '1'; -- Load Bit 2
when "00111"=>
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "01000";
end if;
ENC<= '1';
EOR<= '0';
LDx<= '0';
when "01000"=>
Qn<= "01001";
ENC<= '1';
EOR<= '0';
LDx<= '1'; -- Load Bit 3
when "01001"=>
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "01010";
end if;
ENC<= '1';
EOR<= '0';
LDx<= '0';
when "01010"=>
Qn<= "01011";
ENC<= '1';
EOR<= '0';
LDx<= '1'; -- Load Bit 4
when "01011"=>
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "01100";
end if;
ENC<= '1';
EOR<= '0';
LDx<= '0';
when "01100"=>
Qn<= "01101";
ENC<= '1';
EOR<= '0';
LDx<= '1'; -- Load Bit 5
when "01101"=>
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "01110";
end if;
ENC<= '1';
EOR<= '0';
LDx<= '0';
when "01110"=>
Qn<= "01111";
ENC<= '1';
EOR<= '0';
LDx<= '1'; -- Load Bit 6
when "01111"=>
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "10000";
end if;
ENC<= '1';
EOR<= '0';
LDx<= '0';
when "10000"=>
Qn<= "10001";
ENC<= '1';
EOR<= '0';
LDx<= '1'; -- Load Bit 7
when "10001"=>
if(FBaud= '0')then
Qn<= Qp;
else
Qn<= "00000";
end if;
ENC<= '1';
EOR<= '0';
LDx<= '0';
when others=>
Qn<= "00000";
ENC<= '0';
EOR<= '0';
LDx<= '0';
end case;
end process COMB;
SEC: process(RST,CLK,Qn)
begin
if(RST= '1')then
Qp<= (others=>'0');
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process SEC;
end simple;
| gpl-3.0 | 89cf2376b657bd1b4c06da2663129607 | 0.409974 | 2.564784 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/tb/clkdivce_tb.vhd | 1 | 2,846 | -- $Id: clkdivce_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: clkdivce_tb - sim
-- Description: Generate usec and msec enable signals (SIM only!)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-10 806 1.0 Initial version (copied from clkdivce)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity clkdivce_tb is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end clkdivce_tb;
architecture sim of clkdivce_tb is
type regs_type is record
ucnt : slv(CDUWIDTH-1 downto 0); -- usec clock divider counter
mcnt : slv10; -- msec clock divider counter
usec : slbit; -- usec pulse
msec : slbit; -- msec pulse
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(USECDIV-1,CDUWIDTH)),
slv(to_unsigned(MSECDIV-1,10)),
'0','0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024
report "assert(USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024): " &
"USECDIV too large for given CDUWIDTH or MSECDIV>1024"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
n.usec := '0';
n.msec := '0';
n.ucnt := slv(unsigned(r.ucnt) - 1);
if unsigned(r.ucnt) = 0 then
n.usec := '1';
n.ucnt := slv(to_unsigned(USECDIV-1,CDUWIDTH));
n.mcnt := slv(unsigned(r.mcnt) - 1);
if unsigned(r.mcnt) = 0 then
n.msec := '1';
n.mcnt := slv(to_unsigned(MSECDIV-1,10));
end if;
end if;
N_REGS <= n;
CE_USEC <= r.usec;
CE_MSEC <= r.msec;
end process proc_next;
end sim;
| gpl-3.0 | 8b0ea5a6ee03c052c576a97437ab1519 | 0.544624 | 3.696104 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd | 1 | 5,062 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n2 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.7.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.7 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.6.5 drop iist
-- 2018-09-22 1050 1.6.4 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.6.3 add sys_conf_ibd_kw11p
-- 2017-04-22 884 1.6.2 use sys_conf_dmcmon_awidth=8 (proper value)
-- 2017-01-29 847 1.6.1 add sys_conf_ibd_deuna
-- 2016-07-16 788 1.6 use cram_*delay functions to determine delays
-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural
-- 2016-03-22 750 1.5 add sys_conf_cache_twidth
-- 2015-06-26 695 1.4.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions
-- 2015-02-07 643 1.3 drop bram and minisys options
-- 2014-12-22 619 1.2.1 add _rbmon_awidth
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-27 433 1.1.1 use /1*1 to skip dcm in sim, _ssim fails with dcm
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-28 295 1.0 Initial version (cloned from _s3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim...
-- constant sys_conf_clkfx_divide : positive := 25;
-- constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- configure memory controller ---------------------------------------------
-- now under derived constants
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 4; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 4; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 5; -- DZ11
constant sys_conf_ibd_pc11 : integer := 4; -- PC11
constant sys_conf_ibd_lp11 : integer := 5; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := false; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | ee62c7d9cf81c62ef4106b4340a32a38 | 0.588107 | 3.411051 | false | true | false | false |
wfjm/w11 | rtl/vlib/serport/serport_2clock2.vhd | 1 | 11,344 | -- $Id: serport_2clock2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_2clock2 - syn
-- Description: serial port: serial port module, 2 clock domain (v2)
--
-- Dependencies: cdclib/cdc_pulse
-- cdclib/cdc_signal_s1
-- cdclib/cdc_vector_s0
-- serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_2c_dram2
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-08 759 1.1 all cdc's via cdc_(pulse|signal|vector)
-- 2016-03-28 755 1.0.1 check assertions only at raising clock
-- 2016-03-25 752 1.0 Initial version (derived from serport_2clock, is
-- exactly same logic, re-written to allow proper
-- usage of vivado constraints)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.cdclib.all;
use work.memlib.all;
entity serport_2clock2 is -- serial port module, 2 clock dom. (v2)
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- U|clock (backend:user)
RESET : in slbit; -- U|reset
CLKS : in slbit; -- S|clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end serport_2clock2;
architecture syn of serport_2clock2 is
subtype cd_range is integer range CDWIDTH-1 downto 0; -- clk div value regs
signal RXACT_U : slbit := '0'; -- rxact in CLKU
signal TXACT_U : slbit := '0'; -- txact in CLKU
signal ABACT_U : slbit := '0'; -- abact in CLKU
signal RXOK_U : slbit := '0'; -- rxok in CLKU
signal TXOK_U : slbit := '0'; -- txok in CLKU
signal ABCLKDIV_U : slv(cd_range) := (others=>'0'); -- abclkdiv
signal ABCLKDIV_F_U: slv3 := (others=>'0'); -- abclkdiv_f
signal ENAXON_S : slbit := '0'; -- enaxon in CLKS
signal ENAESC_S : slbit := '0'; -- enaesc in CLKS
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal RESET_CLKS : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(cd_range) := (others=>'0');
signal ABCLKDIV_F : slv3 := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
signal RXERR_U : slbit := '0';
signal RXOVR_U : slbit := '0';
signal ABDONE_U : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
-- sync CLKU->CLKS
CDC_RESET : cdc_pulse -- provide CLKS side RESET
generic map (
POUT_SINGLE => false,
BUSY_WACK => false)
port map (
CLKM => CLKU,
RESET => '0',
CLKS => CLKS,
PIN => RESET,
BUSY => open,
POUT => RESET_CLKS
);
CDC_ENAXON: cdc_signal_s1
port map (CLKO => CLKS, DI => ENAXON, DO => ENAXON_S);
CDC_ENAESC: cdc_signal_s1
port map (CLKO => CLKS, DI => ENAESC, DO => ENAESC_S);
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLKS,
CE_MSEC => CES_MSEC,
RESET => RESET_CLKS,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV,
ABCLKDIV_F => ABCLKDIV_F
);
RESET_INT <= RESET_CLKS or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => ENAXON_S,
ENAESC => ENAESC_S,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => ENAXON_S,
ENAESC => ENAESC_S,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_2c_dram2 -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKS,
CLKR => CLKU,
RESETW => ABACT, -- clear fifo on abact
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXFIFO_SIZEW,
SIZER => open
);
TXFIFO : fifo_2c_dram2 -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKU,
CLKR => CLKS,
RESETW => RESET,
RESETR => ABACT, -- clear fifo on abact
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
-- receive back pressure
-- on if fifo more than 3/4 full (less than 1/4 free)
-- off if fifo less than 1/2 full (more than 1/2 free)
proc_rxok: process (CLKS)
constant rxsize_rxok_off : slv2 := "01";
constant rxsize_rxok_on : slv2 := "10";
variable rxsize_msb : slv2 := "00";
begin
if rising_edge(CLKS) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2);
if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
-- sync CLKS->CLKU
CDC_RXACT : cdc_signal_s1
port map (CLKO => CLKU, DI => RXACT, DO => RXACT_U);
CDC_TXACT : cdc_signal_s1
port map (CLKO => CLKU, DI => UART_TXBUSY, DO => TXACT_U);
CDC_ABACT : cdc_signal_s1
port map (CLKO => CLKU, DI => ABACT, DO => ABACT_U);
CDC_RXOK : cdc_signal_s1
port map (CLKO => CLKU, DI => RXOK, DO => RXOK_U);
CDC_TXOK : cdc_signal_s1
port map (CLKO => CLKU, DI => TXOK, DO => TXOK_U);
CDC_CDIV : cdc_vector_s0
generic map (
DWIDTH => CDWIDTH)
port map (
CLKO => CLKU,
DI => ABCLKDIV,
DO => ABCLKDIV_U
);
CDC_CDIVF : cdc_vector_s0
generic map (
DWIDTH => 3)
port map (
CLKO => CLKU,
DI => ABCLKDIV_F,
DO => ABCLKDIV_F_U
);
CDC_RXERR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXERR,
BUSY => open,
POUT => RXERR_U
);
CDC_RXOVR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXOVR,
BUSY => open,
POUT => RXOVR_U
);
CDC_ABDONE : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => ABDONE,
BUSY => open,
POUT => ABDONE_U
);
MONI.rxerr <= RXERR_U;
MONI.rxovr <= RXOVR_U;
MONI.rxact <= RXACT_U;
MONI.txact <= TXACT_U;
MONI.abact <= ABACT_U;
MONI.abdone <= ABDONE_U;
MONI.rxok <= RXOK_U;
MONI.txok <= TXOK_U;
proc_abclkdiv: process (ABCLKDIV_U, ABCLKDIV_F_U)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(ABCLKDIV_U'range) <= ABCLKDIV_U;
MONI.abclkdiv_f <= ABCLKDIV_F_U;
end process proc_abclkdiv;
-- synthesis translate_off
proc_check: process (CLKS)
begin
if rising_edge(CLKS) then
assert RXOVR = '0'
report "serport_2clock2-W: RXOVR = " & slbit'image(RXOVR) &
"; data loss in receive fifo"
severity warning;
assert RXERR = '0'
report "serport_2clock2-W: RXERR = " & slbit'image(RXERR) &
"; spurious receive error"
severity warning;
end if;
end process proc_check;
-- synthesis translate_on
end syn;
| gpl-3.0 | f2b95fcffaa746a22eeb5dd1550f6a50 | 0.520187 | 3.611589 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd | 1 | 7,172 | -- $Id: sys_tst_serloop2_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop2_n4d - syn
-- Description: Tester serial link for nexys4d (serport_2clock case)
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bpgen/bp_rs232_4line_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock2
-- tst_serloop
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2022.1; ghdl 0.33-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1 537 482 12 0 238
-- 2019-02-02 1108 2018.3 xc7a100t-1 537 510 16 0 232
-- 2019-02-02 1108 2017.2 xc7a100t-1 537 552 16 0 238
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce
-- 2017-01-04 838 1.0 Initial version (derived from sys_tst_serloop2_n4)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop2_n4d is -- top level
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_serloop2_n4d;
architecture syn of sys_tst_serloop2_n4d is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 8,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => sys_conf_clksys_msecdiv,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => sys_conf_clkser_msecdiv)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
DSP_DP => DSP_DP(3 downto 0)
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
SERPORT : serport_2clock2
generic map (
CDWIDTH => 12,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
-- show autobauder clock divisor on msb of display
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
-- setup unused outputs in nexys4d
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 74f4a91d3b8772e8801b04acb8d01e09 | 0.494144 | 3.280878 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd | 1 | 5,040 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_br_arty (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2015.4-2018.3; ghdl 0.33-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.3.6 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.3.5 add sys_conf_ibd_kw11p
-- 2017-01-29 847 1.3.4 add sys_conf_ibd_deuna
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue)
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth
-- 2016-03-13 742 1.1 add sysmon_bus
-- 2016-02-27 736 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 11;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 5b0020ac41a8ec984d4a438e5758f7f7 | 0.59623 | 3.519553 | false | true | false | false |
wfjm/w11 | rtl/w11a/tb/tbd_pdp11core.vhd | 1 | 8,203 | -- $Id: tbd_pdp11core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_pdp11core - syn
-- Description: Wrapper for pdp11_core to avoid records. It has a port
-- interface which will not be modified by xst synthesis
-- (no records, no generic port).
--
-- Dependencies: genlib/clkdivce
-- pdp11_core
-- pdp11_bram
-- ibus/ibdr_minisys
-- pdp11_tmu_sb [sim only]
--
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2-2018.2; ghdl 0.18-0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-13 305 11.4 L68 xc3s1000-4 601 2504 206 1428 s 18.6
-- 2008-03-01 120 8.2.03 I34 xc3s1000-4 679 2562 206 1465 s 18.5
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 605 2324 164 1297 s 18.7
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 536 2119 119 1184 s 19.3
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 INTERNAL_ERROR -> blog_webpack
-- 2007-10-27 92 9.1 J30 xc3s1000-4 503 2021 119 - t 18.7
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 534 2091 119 1170 s 19.3
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 557 2186 119 - s 18.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.6.4 drop ITIMER from core
-- 2018-10-05 1053 1.6.3 use DM_STAT_CA instead of DM_STAT_SY
-- 2015-11-01 712 1.6.2 use sbcntl_sbf_tmu
-- 2015-07-03 697 1.6.1 adapt to new DM_STAT_(SY|VM)
-- 2015-05-03 674 1.6 start/stop/suspend overhaul
-- 2011-11-18 427 1.5.1 now numeric_std clean
-- 2010-12-30 351 1.5 rename tbd_pdp11_core -> tbd_pdp11core
-- 2010-10-23 335 1.4.2 rename RRI_LAM->RB_LAM;
-- 2010-06-20 307 1.4.1 add CP_ADDR_racc, CP_ADDR_be port
-- 2010-06-13 305 1.4 add CP_ADDR_... in ports; add CP_CNTL_rnum in port
-- 2010-06-11 303 1.3.9 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.3.8 adapt to ibdr_minisys interface changes
-- 2009-05-10 214 1.3.7 use pdp11_tmu_sb instead of pdp11_tmu
-- 2008-08-22 161 1.3.6 use iblib, ibdlib
-- 2008-05-03 143 1.3.5 rename _cpursta->_cpurust
-- 2008-04-27 140 1.3.4 use cpursta interface, remove cpufail
-- 2008-04-19 137 1.3.3 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
-- 2008-04-18 136 1.3.2 add RESET for ibdr_minisys
-- 2008-02-23 118 1.3.1 use sys_conf for bram size
-- 2008-02-17 117 1.3 adapt to em_ core interface; use pdp11_bram
-- 2008-01-20 112 1.2.1 rename clkgen->clkdivce; use ibdr_minisys, BRESET;
-- 2008-01-06 111 1.2 add some external devices: KW11L, DL11, RK11
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
entity tbd_pdp11core is -- full core [no records]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL_req : in slbit; -- console control port
CP_CNTL_func : in slv5; -- console control port
CP_CNTL_rnum : in slv3; -- console control port
CP_ADDR_addr : in slv22_1; -- console address port
CP_ADDR_racc : in slbit; -- console address port
CP_ADDR_be : in slv2; -- console address port
CP_ADDR_ena_22bit : in slbit; -- console address port
CP_ADDR_ena_ubmap : in slbit; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT_cmdbusy : out slbit; -- console status port
CP_STAT_cmdack : out slbit; -- console status port
CP_STAT_cmderr : out slbit; -- console status port
CP_STAT_cmdmerr : out slbit; -- console status port
CP_STAT_cpugo : out slbit; -- console status port
CP_STAT_cpustep : out slbit; -- console status port
CP_STAT_cpuwait : out slbit; -- console status port
CP_STAT_cpususp : out slbit; -- console status port
CP_STAT_cpurust : out slv4; -- console status port
CP_STAT_suspint : out slbit; -- console status port
CP_STAT_suspext : out slbit; -- console status port
CP_DOUT : out slv16 -- console data out
);
end tbd_pdp11core;
architecture syn of tbd_pdp11core is
signal CE_USEC : slbit := '0';
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_STAT : cp_stat_type := cp_stat_init;
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal BRESET : slbit := '0';
signal IB_MREQ_M : ib_mreq_type := ib_mreq_init;
signal IB_SRES_M : ib_sres_type := ib_sres_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_CA : dm_stat_ca_type := dm_stat_ca_init;
begin
CP_CNTL.req <= CP_CNTL_req;
CP_CNTL.func <= CP_CNTL_func;
CP_CNTL.rnum <= CP_CNTL_rnum;
CP_ADDR.addr <= CP_ADDR_addr;
CP_ADDR.racc <= CP_ADDR_racc;
CP_ADDR.be <= CP_ADDR_be;
CP_ADDR.ena_22bit <= CP_ADDR_ena_22bit;
CP_ADDR.ena_ubmap <= CP_ADDR_ena_ubmap;
CP_STAT_cmdbusy <= CP_STAT.cmdbusy;
CP_STAT_cmdack <= CP_STAT.cmdack;
CP_STAT_cmderr <= CP_STAT.cmderr;
CP_STAT_cmdmerr <= CP_STAT.cmdmerr;
CP_STAT_cpugo <= CP_STAT.cpugo;
CP_STAT_cpustep <= CP_STAT.cpustep;
CP_STAT_cpuwait <= CP_STAT.cpuwait;
CP_STAT_cpususp <= CP_STAT.cpususp;
CP_STAT_cpurust <= CP_STAT.cpurust;
CP_STAT_suspint <= CP_STAT.suspint;
CP_STAT_suspext <= CP_STAT.suspext;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => open
);
PDP11 : pdp11_core
port map (
CLK => CLK,
RESET => RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT,
CP_DOUT => CP_DOUT,
ESUSP_O => open, -- not tested
ESUSP_I => '0', -- dito
HBPT => '0', -- dito
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
BRESET => BRESET,
IB_MREQ_M => IB_MREQ_M,
IB_SRES_M => IB_SRES_M,
DM_STAT_SE => open,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
MEM : pdp11_bram
generic map (
AWIDTH => sys_conf_bram_awidth)
port map (
CLK => CLK,
GRESET => RESET,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES
);
IBDR_SYS : ibdr_minisys
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
RESET => RESET,
BRESET => BRESET,
RB_LAM => open,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_M,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => open
);
DM_STAT_CA <= dm_stat_ca_init;
-- synthesis translate_off
TMU : pdp11_tmu_sb
generic map (
ENAPIN => sbcntl_sbf_tmu)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_CA => DM_STAT_CA
);
-- synthesis translate_on
end syn;
| gpl-3.0 | 6c9f1d6e5cd1e0a2a4fb3728733f135b | 0.561624 | 2.977495 | false | false | false | false |
nanomolina/vhdl_examples | flopr_generic/floprgeneric.vhd | 2 | 658 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY floprgeneric IS
GENERIC (N: INTEGER:=32);
PORT (d: IN std_logic_vector(N-1 DOWNTO 0);
clk, reset: IN std_logic;
q: OUT std_logic_vector(N-1 DOWNTO 0));
END floprgeneric;
ARCHITECTURE flopr_est OF floprgeneric IS
BEGIN
PROCESS(clk, reset)
VARIABLE temp: std_logic_vector(q'RANGE);
BEGIN
IF (reset='1') THEN
FOR i IN temp'RANGE LOOP
temp(i) := '0';
END LOOP;
q <= temp;
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END flopr_est;
| gpl-3.0 | 7c261ec665daa60f1182b5346022548f | 0.537994 | 3.615385 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/tb/tbd_fifo_2c_dram.vhd | 1 | 2,502 | -- $Id: tbd_fifo_2c_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_fifo_2c_dram - syn
-- Description: Wrapper for fifo_2c_dram to avoid records & generics. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: fifo_2c_dram
--
-- To test: fifo_2c_dram
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-04-24 281 11.4 L68 xc3s1000-4 36 43 32 52 s 8.34
--
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-28 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity tbd_fifo_2c_dram is -- fifo, 2 clock, dram based [tb design]
-- generic: AWIDTH=4; DWIDTH=16
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- reset (synchronous with CLKW)
RESETR : in slbit; -- reset (synchronous with CLKR)
DI : in slv16; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZEW : out slv4; -- number slots to write (synch w/ CLKW)
SIZER : out slv4 -- number slots to read (synch w/ CLKR)
);
end tbd_fifo_2c_dram;
architecture syn of tbd_fifo_2c_dram is
begin
FIFO : fifo_2c_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
end syn;
| gpl-3.0 | cf6d3f51d67b7d6b5e634a14773f2fd0 | 0.476019 | 3.768072 | false | false | false | false |
wfjm/w11 | rtl/bplib/s3board/s3_sram_memctl.vhd | 1 | 12,478 | -- $Id: s3_sram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s3_sram_memctl - syn
-- Description: s3board: SRAM controller
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- Test bench: tb/tb_s3_sram_memctl
-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-05-23 293 11.4 L68 xc3s1000-4 7 22 0 14 s 8.5
-- 2008-02-16 116 8.2.03 I34 xc3s1000-4 5 30 0 17 s 7.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.0.8 drop superfluous idata_cei=1 in s_write2
-- 2016-07-23 793 1.0.7 drop "KEEP" for data (better for dbg)
-- 2011-11-19 427 1.0.6 now numeric_std clean
-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl
-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface
-- 2008-01-20 113 1.0.2 rename memdrv -> memctl_s3sram
-- 2007-12-15 101 1.0.1 use _N for active low; get ce/we clocking right
-- 2007-12-08 100 1.0 Initial version
--
-- Timing of some signals:
--
-- single read request:
--
-- state |_idle |_read |_idle |
--
-- CLK __|^^^|___|^^^|___|^^^|___|^
--
-- REQ _______|^^^^^|______________
-- WE ____________________________
--
-- IOB_CE __________|^^^^^^^|_________
-- IOB_OE __________|^^^^^^^|_________
--
-- DO oooooooooooooooooo|ddddddd|d
-- BUSY ____________________________
-- ACK_R __________________|^^^^^^^|_
--
-- single write request:
--
-- state |_idle |_write1|_write2|_idle |
--
-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^
--
-- REQ _______|^^^^^|______________
-- WE _______|^^^^^|______________
--
-- IOB_CE __________|^^^^^^^^^^^^^^^|_________
-- IOB_BE __________|^^^^^^^^^^^^^^^|_________
-- IOB_OE ____________________________________
-- IOB_WE ______________|^^^^^^^|_____________
--
-- BUSY __________|^^^^^^^|_________________
-- ACK_W __________________|^^^^^^^|_________
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity s3_sram_memctl is -- SRAM controller for S3BOARD
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv18; -- address
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end s3_sram_memctl;
architecture syn of s3_sram_memctl is
type state_type is (
s_idle, -- s_idle: wait for req
s_read, -- s_read: read cycle
s_write1, -- s_write1: write cycle, 1st half
s_write2, -- s_write2: write cycle, 2nd half
s_bta_r2w, -- s_bta_r2w: bus turn around: r->w
s_bta_w2r -- s_bta_w2r: bus turn around: w->r
);
type regs_type is record
state : state_type; -- state
ackr : slbit; -- signal ack_r
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0' -- ackr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CLK_180 : slbit := '0';
signal MEM_CE_N : slv2 := "00";
signal MEM_BE_N : slv4 := "0000";
signal MEM_WE_N : slbit := '0';
signal MEM_OE_N : slbit := '0';
signal ADDR_CE : slbit := '0';
signal DATA_CEI : slbit := '0';
signal DATA_CEO : slbit := '0';
signal DATA_OE : slbit := '0';
begin
CLK_180 <= not CLK;
IOB_MEM_CE : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => MEM_CE_N,
PAD => O_MEM_CE_N
);
IOB_MEM_BE : iob_reg_o_gen
generic map (
DWIDTH => 4,
INIT => '1')
port map (
CLK => CLK,
CE => ADDR_CE,
DO => MEM_BE_N,
PAD => O_MEM_BE_N
);
IOB_MEM_WE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK_180,
CE => '1',
DO => MEM_WE_N,
PAD => O_MEM_WE_N
);
IOB_MEM_OE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => MEM_OE_N,
PAD => O_MEM_OE_N
);
IOB_MEM_ADDR : iob_reg_o_gen
generic map (
DWIDTH => 18)
port map (
CLK => CLK,
CE => ADDR_CE,
DO => ADDR,
PAD => O_MEM_ADDR
);
IOB_MEM_DATA : iob_reg_io_gen
generic map (
DWIDTH => 32,
PULL => "NONE")
port map (
CLK => CLK,
CEI => DATA_CEI,
CEO => DATA_CEO,
OE => DATA_OE,
DI => DO,
DO => DI,
PAD => IO_MEM_DATA
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, REQ, WE, BE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibusy : slbit := '0';
variable iackw : slbit := '0';
variable iactr : slbit := '0';
variable iactw : slbit := '0';
variable imem_ce : slv2 := "00";
variable imem_be : slv4 := "0000";
variable imem_we : slbit := '0';
variable imem_oe : slbit := '0';
variable iaddr_ce : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
n.ackr := '0';
ibusy := '0';
iackw := '0';
iactr := '0';
iactw := '0';
imem_ce := "00";
imem_be := "1111";
imem_we := '0';
imem_oe := '0';
iaddr_ce := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
case r.state is
when s_idle => -- s_idle: wait for req
if REQ = '1' then -- if IO requested
if WE = '0' then -- if READ requested
iaddr_ce := '1'; -- latch address and be's
imem_ce := "11"; -- ce SRAM next cycle
imem_oe := '1'; -- oe SRAM next cycle
n.state := s_read; -- next: read
else -- if WRITE requested
iaddr_ce := '1'; -- latch address and be's
idata_ceo := '1'; -- latch output data
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := "11"; -- ce SRAM next cycle
imem_be := BE; -- use request BE's
n.state := s_write1; -- next: write 1st part
end if;
end if;
when s_read => -- s_read: read cycle
idata_cei := '1'; -- latch input data
iactr := '1'; -- signal mem read
n.ackr := '1'; -- ACK_R next cycle
if REQ = '1' then -- if IO requested
if WE = '0' then -- if READ requested
iaddr_ce := '1'; -- latch address and be's
imem_ce := "11"; -- ce SRAM next cycle
imem_oe := '1'; -- oe SRAM next cycle
n.state := s_read; -- next: continue read
else -- if WRITE requested
iaddr_ce := '1'; -- latch address and be's
idata_ceo := '1'; -- latch output data
imem_be := BE; -- use request BE's
n.state := s_bta_r2w; -- next: bus turn around cycle
end if;
else
n.state := s_idle; -- next: idle if nothing to do
end if;
when s_write1 => -- s_write1: write cycle, 1st half
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := "11"; -- ce SRAM next cycle
imem_we := '1'; -- we SRAM next shifted cycle
n.state := s_write2; -- next: write cycle, 2nd half
when s_write2 => -- s_write2: write cycle, 2nd half
iactw := '1'; -- signal mem write
iackw := '1'; -- signal write acknowledge
if REQ = '1' then -- if IO requested
if WE = '1' then -- if WRITE requested
iaddr_ce := '1'; -- latch address and be's
idata_ceo := '1'; -- latch output data
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := "11"; -- ce SRAM next cycle
imem_be := BE; -- use request BE's
n.state := s_write1; -- next: continue read
else -- if READ requested
iaddr_ce := '1'; -- latch address and be's
n.state := s_bta_w2r; -- next: bus turn around cycle
end if;
else
n.state := s_idle; -- next: idle if nothing to do
end if;
when s_bta_r2w => -- s_bta_r2w: bus turn around: r->w
ibusy := '1'; -- signal busy, unable to handle req
iactw := '1'; -- signal mem write
imem_ce := "11"; -- ce SRAM next cycle
idata_oe := '1'; -- oe FPGA next cycle
n.state := s_write1; -- next: start write
when s_bta_w2r => -- s_bta_w2r: bus turn around: w->r
ibusy := '1'; -- signal busy, unable to handle req
iactr := '1'; -- signal mem read
imem_ce := "11"; -- ce SRAM next cycle
imem_oe := '1'; -- oe SRAM next cycle
n.state := s_read; -- next: start read
when others => null;
end case;
N_REGS <= n;
MEM_CE_N <= not imem_ce;
MEM_WE_N <= not imem_we;
MEM_BE_N <= not imem_be;
MEM_OE_N <= not imem_oe;
ADDR_CE <= iaddr_ce;
DATA_CEI <= idata_cei;
DATA_CEO <= idata_ceo;
DATA_OE <= idata_oe;
BUSY <= ibusy;
ACK_R <= r.ackr;
ACK_W <= iackw;
ACT_R <= iactr;
ACT_W <= iactw;
end process proc_next;
end syn;
| gpl-3.0 | 4cecbf71df659c5057d675276581a475 | 0.41481 | 3.692809 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_pc11.vhd | 1 | 14,166 | -- $Id: ibdr_pc11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_pc11 - syn
-- Description: ibus dev(rem): PC11
--
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-27 1140 1.4.2 set rbuf.[rp]size0
-- 2019-04-24 1137 1.4.1 add rcsr.ir,ique,iack and pcsr.ir fields (rem)
-- 2019-04-06 1126 1.4 for pc11_buf compat: pbuf.pval in bit 15 and 8;
-- move rbusy reporting from pbuf to rbuf register
-- 2013-05-04 515 1.3 BUGFIX: r.rbuf was immediately cleared ! Was broken
-- since ibus V2 update, never tested afterwards...
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
-- causes interrupt, if enabled; validated with zpcae0
-- 2009-06-01 221 0.9 Initial version (untested)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end ibdr_pc11;
architecture syn of ibdr_pc11 is
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
constant rcsr_ibf_rerr : integer := 15;
constant rcsr_ibf_rbusy : integer := 11;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_rir : integer := 5;
constant rcsr_ibf_ique : integer := 3;
constant rcsr_ibf_iack : integer := 2;
constant rcsr_ibf_renb : integer := 0;
constant rbuf_ibf_rbusy : integer := 15;
constant rbuf_ibf_rsize0: integer := 8;
constant rbuf_ibf_psize0: integer := 0;
subtype rbuf_ibf_data is integer range 7 downto 0;
constant pcsr_ibf_perr : integer := 15;
constant pcsr_ibf_prdy : integer := 7;
constant pcsr_ibf_pie : integer := 6;
constant pcsr_ibf_pir : integer := 5;
constant pbuf_ibf_pval : integer := 15;
constant pbuf_ibf_pval8 : integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rerr : slbit; -- rcsr: reader error
rbusy : slbit; -- rcsr: reader busy
rdone : slbit; -- rcsr: reader done
rie : slbit; -- rcsr: reader interrupt enable
rbuf : slv8; -- rbuf:
rintreq : slbit; -- ptr interrupt request
rique : slbit; -- ptr interrupt queued (req set)
riack : slbit; -- ptr interrupt acknowledged
perr : slbit; -- pcsr: punch error
prdy : slbit; -- pcsr: punch ready
pie : slbit; -- pcsr: punch interrupt enable
pbuf : slv8; -- pbuf:
pintreq : slbit; -- ptp interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- rerr (init=1!)
'0','0','0', -- rbusy,rdone,rie
(others=>'0'), -- rbuf
'0','0','0', -- rintreq,rique,riack
'1', -- perr (init=1!)
'1', -- prdy (init=1!)
'0', -- pie
(others=>'0'), -- pbuf
'0' -- pintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- reader control status -----
idout(rcsr_ibf_rerr) := r.rerr;
idout(rcsr_ibf_rbusy) := r.rbusy;
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rie = '0' and -- IE 0->1 transition
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
(r.rerr='1' or r.rdone='1') then -- but err or done set
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupts
end if;
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
if r.rerr = '0' then -- if not in error state
n.rbusy := '1'; -- set busy
n.rdone := '0'; -- clear done
n.rbuf := (others=>'0'); -- clear buffer
n.rintreq := '0'; -- cancel interrupt
n.rique := '0'; -- and que flag
n.riack := '0'; -- and ack flag
ilam := '1'; -- rri lam
else -- if in error state
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rir) := r.rintreq;
idout(rcsr_ibf_ique) := r.rique;
idout(rcsr_ibf_iack) := r.riack;
if ibw1 = '1' then
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
and r.rerr='0' then
n.rbusy := '0'; -- clear busy
n.rdone := '0'; -- clear done
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- reader data buffer --------
if IB_MREQ.racc = '0' then -- cpu ---------------------
idout(rbuf_ibf_data) := r.rbuf;
if ibreq = '1' then -- !! PC11 is unusual !!
n.rdone := '0'; -- *any* read or write will clear done
n.rbuf := (others=>'0'); -- and the reader buffer
n.rintreq := '0'; -- also interrupt is canceled
end if;
else -- rri ---------------------
idout(rbuf_ibf_rbusy) := r.rbusy;
idout(rbuf_ibf_rsize0) := r.rdone; -- rbuf occupied when rdone=1
idout(rbuf_ibf_psize0) := not r.prdy; -- pbuf empty when prdy=1
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(rbuf_ibf_data);
n.rbusy := '0';
n.rdone := '1';
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
end if;
when ibaddr_pcsr => -- PCSR -- punch control status ------
idout(pcsr_ibf_perr) := r.perr;
idout(pcsr_ibf_prdy) := r.prdy;
idout(pcsr_ibf_pie) := r.pie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.pie := IB_MREQ.din(pcsr_ibf_pie);
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
if r.pie='0' and -- IE 0->1 transition
(r.perr='1' or r.prdy='1') then -- but err or done set
n.pintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.pintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
idout(pcsr_ibf_pir) := r.pintreq;
if ibw1 = '1' then
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
and r.perr='0' then
n.prdy := '1'; -- set ready
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.perr = '0' then -- if not in error state
n.pbuf := IB_MREQ.din(n.pbuf'range);
n.prdy := '0'; -- clear ready
n.pintreq := '0'; -- cancel interrupts
ilam := '1'; -- rri lam
else -- if in error state
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri ---------------------
idout(r.pbuf'range) := r.pbuf;
idout(pbuf_ibf_pval) := not r.prdy;
idout(pbuf_ibf_pval8) := not r.prdy;
if ibrd = '1' then
n.prdy := '1';
if r.pie = '1' then
n.pintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK_PTR = '1' then
n.rintreq := '0';
n.riack := '1';
end if;
if EI_ACK_PTP = '1' then
n.pintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_PTR <= r.rintreq;
EI_REQ_PTP <= r.pintreq;
end process proc_next;
end syn;
| gpl-3.0 | dce074d56f5aa256c2b736738a97120f | 0.426444 | 3.98257 | false | false | false | false |
wfjm/w11 | rtl/bplib/arty/sramif_mig_arty.vhd | 1 | 7,454 | -- $Id: sramif_mig_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sramif_mig_arty - syn
-- Description: SRAM to DDR via MIG for arty
--
-- Dependencies: bplib/mig/sramif2migui_core
-- cdclib/cdc_pulse
-- cdclib/cdc_value
-- migui_arty (generated core)
-- Test bench: tb_tst_sram_arty
-- Target Devices: arty board
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-02 1101 1.0 Initial version
-- 2018-11-17 1071 0.1 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.cdclib.all;
use work.miglib.all;
use work.miglib_arty.all;
entity sramif_mig_arty is -- SRAM to DDR via MIG for arty
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- xadc die temp for mig core
MONI : out sramif2migui_moni_type;-- monitor signals
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sramif_mig_arty;
architecture syn of sramif_mig_arty is
signal MIG_BUSY : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_EN : slbit := '0';
signal APP_CMD : slv3 := (others=>'0');
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_WDF_RDY : slbit := '0';
signal APP_WDF_WREN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal UI_CLK_SYNC_RST : slbit := '0';
signal INIT_CALIB_COMPLETE : slbit := '0';
signal SYS_RST : slbit := '0';
signal SYS_RST_BUSY : slbit := '0';
signal CLKMUI : slbit := '0';
signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI
begin
SR2MIG: sramif2migui_core -- SRAM to MIG iface -----------------
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => MIG_BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
MONI => MONI,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END
);
CDC_SYSRST: cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => true)
port map (
CLKM => CLK,
RESET => '0',
CLKS => CLKMIG,
PIN => RESET,
BUSY => SYS_RST_BUSY,
POUT => SYS_RST
);
CDC_TEMP: cdc_value
generic map (
DWIDTH => TEMP'length)
port map (
CLKI => CLK,
CLKO => CLKMUI,
DI => TEMP,
DO => TEMP_MUI,
UPDT => open
);
MIG_CTL: migui_arty
port map (
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => '0',
APP_REF_REQ => '0',
APP_ZQ_REQ => '0',
APP_SR_ACTIVE => open,
APP_REF_ACK => open,
APP_ZQ_ACK => open,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => TEMP_MUI,
SYS_RST => SYS_RST
);
BUSY <= MIG_BUSY or SYS_RST_BUSY;
end syn;
| gpl-3.0 | c855b4fb1fa9c3fc67105b9dcc00ac35 | 0.463107 | 3.356146 | false | false | false | false |
mr-kenhoff/Bitmap-VHDL-Package | sim/bmp_source_sink_TB.vhd | 1 | 1,386 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bmp_source_sink_TB is
end entity;
architecture behavioural of bmp_source_sink_TB is
constant SOURCE_FILENAME : string := "source.bmp";
constant SINK_FILENAME : string := "sink.bmp";
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal val : std_logic := '0';
signal rdy : std_logic := '0';
signal dat : std_logic_vector(23 downto 0) := (others => '0');
signal eol : std_logic := '0';
signal eof : std_logic := '0';
begin
clk <= not clk after 20 ns;
bmp_source_1 : entity work.bmp_source
generic map (
FILENAME => SOURCE_FILENAME,
ITERATIONS => 1,
BACKPRESSURE_EN => false
)
port map (
clk_i => clk,
rst_i => rst,
val_o => val,
dat_o => dat,
rdy_i => rdy,
eol_o => eol,
eof_o => eof
);
bmp_sink_1 : entity work.bmp_sink
generic map (
FILENAME => SINK_FILENAME
)
port map (
clk_i => clk,
rst_i => rst,
val_i => val,
dat_i => dat,
rdy_o => rdy,
eol_i => eol,
eof_i => eof,
halt_i => '0'
);
end architecture;
| mit | 91b0590c095fc5b635ed4422b8f08a7e | 0.466089 | 3.562982 | false | false | false | false |
jasonpeng/cg3207-proj | MEM_WB_BUFF.vhd | 1 | 2,186 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:30:58 10/31/2013
-- Design Name:
-- Module Name: MEM_WB_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MEM_WB_BUFF is
Port (
IN_MemToReg : in STD_LOGIC;
IN_DataMemory_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_ALU_Result_2 : in STD_LOGIC_VECTOR(31 downto 0);
IN_MUL_DIV : in STD_LOGIC;
IN_REG_WriteAddr : in STD_LOGIC_VECTOR(4 downto 0);
IN_RegWrite : in STD_LOGIC;
OUT_MemToReg : out STD_LOGIC;
OUT_DataMemory_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_ALU_Result : out STD_LOGIC_VECTOR(31 downto 0);
OUT_ALU_Result_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_MUL_DIV : out STD_LOGIC;
OUT_REG_WriteAddr : out STD_LOGIC_VECTOR(4 downto 0);
OUT_RegWrite : out STD_LOGIC;
Clk, Reset : in std_logic
);
end MEM_WB_BUFF;
architecture Behavioral of MEM_WB_BUFF is
begin
process (Clk, Reset)
begin
if (Reset = '1') then
OUT_MemToReg <= '0';
OUT_DataMemory_Result <= (others => '0');
OUT_ALU_Result <= (others => '0');
OUT_ALU_Result_2 <= (others => '0');
OUT_MUL_DIV <= '0';
OUT_REG_WriteAddr <= (others => '0');
OUT_RegWrite <= '0';
elsif rising_edge(CLK) then
OUT_MemToReg <= IN_MemToReg;
OUT_DataMemory_Result <= IN_DataMemory_Result;
OUT_ALU_Result <= IN_ALU_Result;
OUT_ALU_Result_2 <= IN_ALU_Result_2;
OUT_MUL_DIV <= IN_MUL_DIV;
OUT_REG_WriteAddr <= IN_REG_WriteAddr;
OUT_RegWrite <= IN_RegWrite;
end if;
end process;
end Behavioral;
| gpl-2.0 | f9c05239856b2b6e1ac795bde8db0f42 | 0.515554 | 3.480892 | false | false | false | false |
wfjm/w11 | rtl/bplib/fx2lib/fx2lib.vhd | 1 | 7,118 | -- $Id: fx2lib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: fx2lib
-- Description: Cypress ez-usb fx2 support
--
-- Dependencies: -
-- Tool versions: xst 12.1-14.7; ghdl 0.26-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-04-30 888 1.5 add fsm_* monitor lines
-- 2015-01-25 638 1.4 retire fx2_2fifoctl_as
-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size
-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's
-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic
-- 2011-12-25 445 1.1 change pktend iface in fx2_2fifoctl_as
-- 2011-07-17 394 1.0.1 add c_fifo_epx and fx2ctl_moni_type
-- 2011-07-07 389 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package fx2lib is
constant c_fifo_ep2 : slv2 := "00"; -- fifo address: end point 2
constant c_fifo_ep4 : slv2 := "01"; -- fifo address: end point 4
constant c_fifo_ep6 : slv2 := "10"; -- fifo address: end point 6
constant c_fifo_ep8 : slv2 := "11"; -- fifo address: end point 8
type fx2ctl_moni_type is record -- fx2ctl monitor port
fifo_ep4 : slbit; -- fifo 1 (ep4) active;
fifo_ep6 : slbit; -- fifo 2 (ep6) active;
fifo_ep8 : slbit; -- fifo 3 (ep8) active;
flag_ep4_empty : slbit; -- ep4 empty flag (latched);
flag_ep4_almost : slbit; -- ep4 almost empty flag (latched);
flag_ep6_full : slbit; -- ep6 full flag (latched);
flag_ep6_almost : slbit; -- ep6 almost full flag (latched);
flag_ep8_full : slbit; -- ep8 full flag (latched);
flag_ep8_almost : slbit; -- ep8 almost full flag (latched);
slrd : slbit; -- read strobe
slwr : slbit; -- write strobe
pktend : slbit; -- pktend strobe
fsm_idle : slbit; -- fsm: in s_idle
fsm_prep : slbit; -- fsm: in s_*prep*
fsm_disp : slbit; -- fsm: in s_*disp*
fsm_pipe : slbit; -- fsm: in s_rxpipe
fsm_rx : slbit; -- fsm: in s_rx*
fsm_tx : slbit; -- fsm: in s_tx*
fsm_tx2 : slbit; -- fsm: in s_tx2*
end record fx2ctl_moni_type;
constant fx2ctl_moni_init : fx2ctl_moni_type := (
'0','0','0', -- fifo_ep[468]
'0','0', -- flag_ep4_(empty|almost)
'0','0', -- flag_ep6_(full|almost)
'0','0', -- flag_ep8_(full|almost)
'0','0','0', -- slrd, slwr, pktend
'0','0','0','0', -- fsm_(idle|prep|disp|pipe)
'0','0','0' -- fsm_(rx|tx|tx2)
);
-- -------------------------------------
component fx2_2fifoctl_ic is -- EZ-USB FX2 controller(2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component fx2_3fifoctl_ic is -- EZ-USB FX2 controller(3 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit 1 data in
TXENA : in slbit; -- transmit 1 data enable
TXBUSY : out slbit; -- transmit 1 data busy
TXAFULL : out slbit; -- transmit 1 almost full flag
TX2DATA : in slv8; -- transmit 2 data in
TX2ENA : in slbit; -- transmit 2 data enable
TX2BUSY : out slbit; -- transmit 2 data busy
TX2AFULL : out slbit; -- transmit 2 almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package fx2lib;
| gpl-3.0 | 6d1f459220812b60af7e40111729d3f3 | 0.496909 | 3.701508 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_snhumanio/nexys4d/sys_tst_snhumanio_n4d.vhd | 1 | 4,056 | -- $Id: sys_tst_snhumanio_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n4d - syn
-- Description: snhumanio tester design for nexys4d
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2022.1; ghdl 0.31-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1 154 164 0 0 67
-- 2019-02-02 1108 2018.3 xc7a100t-1 154 187 0 0 74
-- 2019-02-02 1108 2017.2 xc7a100t-1 154 185 0 0 68
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 4DDR Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n4d is -- top level
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_snhumanio_n4d;
architecture syn of sys_tst_snhumanio_n4d is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 100,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI(7 downto 0),
I_BTN => I_BTN,
O_LED => O_LED(7 downto 0),
O_ANO_N => O_ANO_N(3 downto 0),
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
O_RTS_N <= I_CTS_N;
O_LED(15 downto 8) <= not I_SWI(15 downto 8);
O_ANO_N(7 downto 4) <= (others=>'1');
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 990ee72fef853f2c0cec1b812fe8894a | 0.463018 | 3.377186 | false | false | false | false |
wfjm/w11 | rtl/ibus/ib_sres_or_mon.vhd | 1 | 3,030 | -- $Id: ib_sres_or_mon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_mon - sim
-- Description: ibus result or monitor
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end ib_sres_or_mon;
architecture sim of ib_sres_or_mon is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
constant dzero : slv16 := (others=>'0');
variable oline : line;
variable nack : integer := 0;
variable nbusy : integer := 0;
variable ndout : integer := 0;
begin
nack := 0;
nbusy := 0;
ndout := 0;
if IB_SRES_1.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_2.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_3.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_4.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
if now > 0 ns and (nack>1 or nbusy>1 or ndout>1) then
write(oline, now, right, 12);
if nack > 1 then
write(oline, string'(" #ack="));
write(oline, nack);
end if;
if nbusy > 1 then
write(oline, string'(" #busy="));
write(oline, nbusy);
end if;
if ndout > 1 then
write(oline, string'(" #dout="));
write(oline, ndout);
end if;
write(oline, string'(" FAIL in "));
write(oline, ib_sres_or_mon'path_name);
writeline(output, oline);
end if;
end process proc_comb;
end sim;
| gpl-3.0 | 5552f3cbcf8bed7392d23ee5be3a5462 | 0.524422 | 3.169456 | false | false | false | false |
sjohann81/hf-risc | devices/peripherals/standard_soc_assoc.vhd | 1 | 26,004 | -- file: standard_soc_assoc.vhd
-- description: standard SoC with peripherals and external blocks
-- date: 09/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- Standard SoC configuration template for prototyping. Dual GPIO ports,
-- a counter, a timer, dual UARTs and dual SPIs are included in this version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity peripherals is
port (
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
sel_i: in std_logic;
wr_i: in std_logic;
irq_o: out std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0);
-- MAC Sync I/O space: 0xe0ff4000 - 0xe0ff43ff
sync_mac_i: in std_logic_vector(31 downto 0);
sync_mac_o: out std_logic_vector(31 downto 0);
sync_mac_en_o: out std_logic;
sync_mac_rst_o: out std_logic;
-- MAC Async I/O space: 0xe0ff4400 - 0xe0ff47ff
async_mac_i: in std_logic_vector(31 downto 0);
async_mac_o: out std_logic_vector(31 downto 0);
async_mac_en_o: out std_logic;
async_mac_rst_o: out std_logic;
-- Delay line I/O space: 0xe0ff4800 - 0xe0ff4bff
de_pause_o: out std_logic_vector(1 downto 0);
de_config_o: out std_logic_vector(4 downto 0);
de_cde_sel_o: out std_logic_vector(3 downto 0);
de_mde_sel_l_o: out std_logic_vector(3 downto 0);
de_mde_sel_b_o: out std_logic_vector(3 downto 0);
de_cde_ctrl_o: out std_logic_vector(15 downto 0)
);
end peripherals;
architecture peripherals_arch of peripherals is
signal segment: std_logic_vector(3 downto 0);
signal class: std_logic_vector(3 downto 0);
signal device: std_logic_vector(5 downto 0);
signal funct: std_logic_vector(3 downto 0);
signal s0cause: std_logic_vector(4 downto 0);
signal gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(15 downto 0);
signal pbddr, pbout, pbin, pbin_inv, pbin_mask: std_logic_vector(15 downto 0);
signal paaltcfg0: std_logic_vector(31 downto 0);
signal paalt: std_logic_vector(15 downto 0);
signal int_gpio, int_timer: std_logic;
signal int_gpioa, int_gpiob, int_timer1_ocr, int_timer1_ctc, tmr1_pulse, tmr1_dly, tmr1_dly2: std_logic;
signal timer0: std_logic_vector(31 downto 0);
signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
signal timer1_pre: std_logic_vector(2 downto 0);
signal timer1_set: std_logic;
signal int_uart: std_logic;
signal uartcause, uartcause_inv, uartmask: std_logic_vector(3 downto 0);
signal uart0_tx, uart0_rx, uart0_enable_w, uart0_enable_r, uart0_write_busy, uart0_data_avail: std_logic;
signal uart0_data_read, uart0_data_write: std_logic_vector(7 downto 0);
signal uart0_divisor: std_logic_vector(15 downto 0);
signal uart1_tx, uart1_rx, uart1_enable_w, uart1_enable_r, uart1_write_busy, uart1_data_avail: std_logic;
signal uart1_data_read, uart1_data_write: std_logic_vector(7 downto 0);
signal uart1_divisor: std_logic_vector(15 downto 0);
signal int_spi: std_logic;
signal spicause, spicause_inv, spimask: std_logic_vector(3 downto 0);
signal spi0_data_write, spi0_data_read: std_logic_vector(7 downto 0);
signal spi0_clk_div: std_logic_vector(8 downto 0);
signal spi0_data_valid, spi0_data_xfer, spi0_ssn, spi0_clk_i, spi0_clk_o, spi0_do, spi0_di: std_logic;
signal spi1_data_write, spi1_data_read: std_logic_vector(7 downto 0);
signal spi1_clk_div: std_logic_vector(8 downto 0);
signal spi1_data_valid, spi1_data_xfer, spi1_ssn, spi1_clk_i, spi1_clk_o, spi1_do, spi1_di: std_logic;
signal async_mac_en_r, async_mac_rst_r, sync_mac_en_r, sync_mac_rst_r: std_logic;
signal async_mac_r, sync_mac_r: std_logic_vector(31 downto 0);
signal de_pause_r: std_logic_vector(1 downto 0);
signal de_config_r: std_logic_vector(4 downto 0);
signal de_cde_sel_r: std_logic_vector(3 downto 0);
signal de_mde_sel_l_r, de_mde_sel_b_r: std_logic_vector(3 downto 0);
signal de_cde_ctrl_r: std_logic_vector(15 downto 0);
signal de_cde_ctrl_we_r: std_logic;
begin
segment <= addr_i(27 downto 24);
class <= addr_i(19 downto 16);
device <= addr_i(15 downto 10);
funct <= addr_i(7 downto 4);
irq_o <= '1' when s0cause /= "00000" else '0';
s0cause <= int_spi & int_uart & int_timer & int_gpio & '0';
int_gpio <= '1' when ((gpiocause xor gpiocause_inv) and gpiomask) /= "0000" else '0';
gpiocause <= "00" & int_gpiob & int_gpioa;
int_gpioa <= '1' when ((pain xor pain_inv) and pain_mask) /= "0000" else '0';
int_gpiob <= '1' when ((pbin xor pbin_inv) and pbin_mask) /= "0000" else '0';
pain <= gpioa_in(15 downto 0);
gpioa_out <= paalt;
gpioa_ddr <= paddr;
pbin <= gpiob_in(15 downto 0);
gpiob_out <= pbout;
gpiob_ddr <= pbddr;
int_timer <= '1' when ((timercause xor timercause_inv) and timermask) /= "0000" else '0';
timercause <= int_timer1_ocr & int_timer1_ctc & timer0(18) & timer0(16);
int_uart <= '1' when ((uartcause xor uartcause_inv) and uartmask) /= "0000" else '0';
uartcause <= uart1_write_busy & uart1_data_avail & uart0_write_busy & uart0_data_avail;
int_spi <= '1' when ((spicause xor spicause_inv) and spimask) /= "0000" else '0';
spicause <= "00" & spi1_data_valid & spi0_data_valid;
-- PORT A alternate config MUXes for outputs
paalt(0) <= int_timer1_ctc when paaltcfg0(1 downto 0) = "01" else int_timer1_ocr when paaltcfg0(1 downto 0) = "10" else paout(0);
paalt(1) <= spi1_clk_o when paaltcfg0(3 downto 2) = "11" else paout(1);
paalt(2) <= uart0_tx when paaltcfg0(5 downto 4) = "01" else spi1_do when paaltcfg0(5 downto 4) = "11" else paout(2);
paalt(3) <= spi1_do when paaltcfg0(7 downto 6) = "11" else paout(3);
paalt(4) <= uart1_tx when paaltcfg0(9 downto 8) = "01" else paout(4);
paalt(5) <= spi0_clk_o when paaltcfg0(11 downto 10) = "10" else paout(5);
paalt(6) <= spi0_do when paaltcfg0(13 downto 12) = "10" else paout(6);
paalt(7) <= spi0_do when paaltcfg0(15 downto 14) = "10" else paout(7);
paalt(8) <= int_timer1_ctc when paaltcfg0(17 downto 16) = "01" else int_timer1_ocr when paaltcfg0(17 downto 16) = "10" else paout(8);
paalt(9) <= spi1_clk_o when paaltcfg0(19 downto 18) = "11" else paout(9);
paalt(10) <= uart0_tx when paaltcfg0(21 downto 20) = "01" else spi1_do when paaltcfg0(21 downto 20) = "11" else paout(10);
paalt(11) <= spi1_do when paaltcfg0(23 downto 22) = "11" else paout(11);
paalt(12) <= uart1_tx when paaltcfg0(25 downto 24) = "01" else paout(12);
paalt(13) <= spi0_clk_o when paaltcfg0(27 downto 26) = "10" else paout(13);
paalt(14) <= spi0_do when paaltcfg0(29 downto 28) = "10" else paout(14);
paalt(15) <= spi0_do when paaltcfg0(31 downto 30) = "10" else paout(15);
-- PORT A alternate config MUXes for inputs
uart0_rx <= pain(3) when paaltcfg0(7 downto 6) = "01" else pain(11) when paaltcfg0(23 downto 22) = "01" else '1';
uart1_rx <= pain(5) when paaltcfg0(11 downto 10) = "01" else pain(13) when paaltcfg0(27 downto 26) = "01" else '1';
spi0_ssn <= pain(4) when paaltcfg0(9 downto 8) = "10" else pain(12) when paaltcfg0(25 downto 24) = "10" else '1';
spi0_clk_i <= pain(5) when paaltcfg0(11 downto 10) = "10" else pain(13) when paaltcfg0(27 downto 26) = "10" else '0';
spi0_di <= pain(6) when paaltcfg0(13 downto 12) = "10" else pain(14) when paaltcfg0(29 downto 28) = "10" else
pain(7) when paaltcfg0(15 downto 14) = "10" else pain(15) when paaltcfg0(31 downto 30) = "10" else '0';
spi1_ssn <= pain(0) when paaltcfg0(1 downto 0) = "11" else pain(8) when paaltcfg0(17 downto 16) = "11" else '1';
spi1_clk_i <= pain(1) when paaltcfg0(3 downto 2) = "11" else pain(9) when paaltcfg0(19 downto 18) = "11" else '0';
spi1_di <= pain(2) when paaltcfg0(5 downto 4) = "11" else pain(10) when paaltcfg0(21 downto 20) = "11" else
pain(3) when paaltcfg0(7 downto 6) = "11" else pain(11) when paaltcfg0(23 downto 22) = "11" else '0';
-- address decoder, read from peripheral registers
process(clk_i, rst_i, segment, class, device, funct)
begin
if rst_i = '1' then
data_o <= (others => '0');
uart0_enable_r <= '0';
uart1_enable_r <= '0';
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' then
case segment is
when "0000" => -- Segment Reserved
case class is
when "1111" =>
case device is
when "010000" => -- MAC Sync I/O space: 0xe0ff4000 - 0xe0ff43ff
case funct is
when "0000" => -- 0xe0ff4000 (RW)
data_o <= sync_mac_r;
when "0001" => -- 0xe0ff4010 (RO)
data_o <= sync_mac_i;
when "0010" => -- 0xe0ff4020 (RW)
data_o <= x"0000000" & "000" & sync_mac_rst_r;
when others =>
end case;
when "010001" => -- MAC Async I/O space: 0xe0ff4400 - 0xe0ff47ff
case funct is
when "0000" => -- 0xe0ff4400 (RW)
data_o <= async_mac_r;
when "0001" => -- 0xe0ff4410 (RO)
data_o <= async_mac_i;
when "0010" => -- 0xe0ff4420 (RW)
data_o <= x"0000000" & "000" & async_mac_rst_r;
when others =>
end case;
when "010010" => -- Delay line I/O space: 0xe0ff4800 - 0xe0ff4bff
case funct is
when "0000" => -- 0xe0ff4800 (RW)
data_o <= x"000000" & "000" & de_config_r;
when "0001" => -- 0xe0ff4810 (RW)
data_o <= x"0000000" & de_cde_sel_r;
when "0010" => -- 0xe0ff4820 (RW)
data_o <= x"0000000" & de_mde_sel_l_r;
when "0011" => -- 0xe0ff4830 (RW)
data_o <= x"0000000" & de_mde_sel_b_r;
when "0100" => -- 0xe0ff4840 (RW)
data_o <= x"0000" & de_cde_ctrl_r;
when "0101" => -- 0xe0ff4850 (RW)
data_o <= x"0000000" & "00" & de_pause_r;
when others =>
end case;
when others =>
end case;
when others =>
end case;
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "000001" => -- S0CAUSE (RO)
data_o <= x"000000" & "000" & s0cause;
when "010000" => -- PAALTCFG0 (RW)
data_o <= paaltcfg0;
when others =>
data_o <= (others => '0');
end case;
when "0001" => -- GPIO
case device is
when "000001" => -- GPIOCAUSE (RO)
data_o <= x"0000000" & gpiocause;
when "000010" => -- GPIOCAUSE_INV (RW)
data_o <= x"0000000" & gpiocause_inv;
when "000011" => -- GPIOMASK (RW)
data_o <= x"0000000" & gpiomask;
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
data_o <= x"0000" & paddr;
when "0001" => -- PAOUT (RW)
data_o <= x"0000" & paout;
when "0010" => -- PAIN (RO)
data_o <= x"0000" & pain;
when "0011" => -- PAIN_INV (RW)
data_o <= x"0000" & pain_inv;
when "0100" => -- PAIN_MASK (RW)
data_o <= x"0000" & pain_mask;
when others =>
data_o <= (others => '0');
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
data_o <= x"0000" & pbddr;
when "0001" => -- PBOUT (RW)
data_o <= x"0000" & pbout;
when "0010" => -- PBIN (RO)
data_o <= x"0000" & pbin;
when "0011" => -- PBIN_INV (RW)
data_o <= x"0000" & pbin_inv;
when "0100" => -- PBIN_MASK (RW)
data_o <= x"0000" & pbin_mask;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0010" => -- timers
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & timercause;
when "000010" => -- TIMERCAUSE_INV (RW)
data_o <= x"0000000" & timercause_inv;
when "000011" => -- TIMERMASK (RW)
data_o <= x"0000000" & timermask;
when "010000" => -- TIMER0 (RO)
data_o <= timer0;
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
data_o <= x"0000" & timer1;
when "0001" => -- TIMER1_PRE (RW)
data_o <= x"0000000" & '0' & timer1_pre;
when "0010" => -- TIMER1_CTC (RW)
data_o <= x"0000" & timer1_ctc;
when "0011" => -- TIMER1_OCR (RW)
data_o <= x"0000" & timer1_ocr;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0011" => -- UARTs
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & uartcause;
when "000010" => -- UARTCAUSE_INV (RW)
data_o <= x"0000000" & uartcause_inv;
when "000011" => -- UARTMASK (RW)
data_o <= x"0000000" & uartmask;
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
data_o <= x"000000" & uart0_data_read;
uart0_enable_r <= '1';
when "0001" => -- UART0DIV (RW)
data_o <= x"0000" & uart0_divisor;
when others =>
end case;
when "010001" => -- UART1
case funct is
when "0000" => -- UART1 (RW)
data_o <= x"000000" & uart1_data_read;
uart1_enable_r <= '1';
when "0001" => -- UART1DIV (RW)
data_o <= x"0000" & uart1_divisor;
when others =>
end case;
when others =>
end case;
when "0100" => -- SPIs
case device is
when "000001" => -- SPICAUSE (RO)
data_o <= x"0000000" & spicause;
when "000010" => -- SPICAUSE_INV (RW)
data_o <= x"0000000" & spicause_inv;
when "000011" => -- SPIMASK (RW)
data_o <= x"0000000" & spimask;
when "010000" => -- SPI0
case funct is
when "0000" => -- SPI0 (RW)
data_o <= x"000000" & spi0_data_read;
when "0001" => -- SPI0CTRL (RW)
data_o <= x"0000" & "0000" & spi0_clk_div & "0" & spi0_data_valid & spi0_data_xfer;
when others =>
end case;
when "010001" => -- SPI1
case funct is
when "0000" => -- SPI1 (RW)
data_o <= x"000000" & spi1_data_read;
when "0001" => -- SPI1CTRL (RW)
data_o <= x"0000" & "0000" & spi1_clk_div & "0" & spi1_data_valid & spi1_data_xfer;
when others =>
end case;
when others =>
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
else
uart0_enable_r <= '0';
uart1_enable_r <= '0';
end if;
end if;
end process;
-- peripheral register logic, write to peripheral registers
process(clk_i, rst_i, segment, class, device, funct, tmr1_pulse)
begin
if rst_i = '1' then
paaltcfg0 <= (others => '0');
gpiocause_inv <= (others => '0');
gpiomask <= (others => '0');
paout <= (others => '0');
pain_inv <= (others => '0');
pain_mask <= (others => '0');
paddr <= (others => '0');
pbout <= (others => '0');
pbin_inv <= (others => '0');
pbin_mask <= (others => '0');
pbddr <= (others => '0');
timercause_inv <= (others => '0');
timermask <= (others => '0');
timer0 <= (others => '0');
timer1 <= (others => '0');
timer1_set <= '0';
timer1_pre <= (others => '0');
timer1_ctc <= (others => '1');
timer1_ocr <= (others => '0');
int_timer1_ctc <= '0';
uartcause_inv <= (others => '0');
uartmask <= (others => '0');
uart0_enable_w <= '0';
uart0_data_write <= (others => '0');
uart0_divisor <= (others => '0');
uart1_enable_w <= '0';
uart1_data_write <= (others => '0');
uart1_divisor <= (others => '0');
spicause_inv <= (others => '0');
spimask <= (others => '0');
spi0_data_write <= (others => '0');
spi0_data_xfer <= '0';
spi0_clk_div <= (others => '0');
spi1_data_write <= (others => '0');
spi1_data_xfer <= '0';
spi1_clk_div <= (others => '0');
sync_mac_en_r <= '0';
sync_mac_rst_r <= '1';
sync_mac_r <= (others => '0');
async_mac_en_r <= '0';
async_mac_rst_r <= '1';
async_mac_r <= (others => '0');
de_pause_r <= (others => '1');
de_config_r <= (others => '0');
de_cde_sel_r <= (others => '1');
de_mde_sel_l_r <= (others => '1');
de_mde_sel_b_r <= (others => '0');
de_cde_ctrl_r <= x"0001";
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' and wr_i = '1' then
case segment is
when "0000" => -- Segment Reserved
case class is
when "1111" =>
case device is
when "010000" => -- MAC Sync I/O space: 0xe0ff4000 - 0xe0ff43ff
case funct is
when "0000" => -- 0xe0ff4000 (RW)
sync_mac_r <= data_i;
sync_mac_en_r <= '1';
-- when "0001" => -- 0xe0ff4010 (RO)
when "0010" => -- 0xe0ff4020 (RW)
sync_mac_rst_r <= data_i(0);
when others =>
end case;
when "010001" => -- MAC Async I/O space: 0xe0ff4400 - 0xe0ff47ff
case funct is
when "0000" => -- 0xe0ff4400 (RW)
async_mac_r <= data_i;
async_mac_en_r <= '1';
-- when "0001" => -- 0xe0ff4410 (RO)
when "0010" => -- 0xe0ff4420 (RW)
async_mac_rst_r <= data_i(0);
when others =>
end case;
when "010010" => -- Delay line I/O space: 0xe0ff4800 - 0xe0ff4bff
case funct is
when "0000" => -- 0xe0ff4800 (RW)
if (de_pause_r = "11") then
de_config_r <= data_i(4 downto 0);
end if;
when "0001" => -- 0xe0ff4810 (RW)
if (de_pause_r(1) = '1') then
de_cde_sel_r <= data_i(3 downto 0);
end if;
when "0010" => -- 0xe0ff4820 (RW)
if (de_pause_r(0) = '1') then
de_mde_sel_l_r <= data_i(3 downto 0);
end if;
when "0011" => -- 0xe0ff4830 (RW)
if (de_pause_r(0) = '1') then
de_mde_sel_b_r <= data_i(3 downto 0);
end if;
when "0100" => -- 0xe0ff4840 (RW)
if (de_pause_r(1) = '1') then
de_cde_ctrl_r <= data_i(15 downto 0);
end if;
when "0101" => -- 0xe0ff4850 (RW)
de_pause_r <= data_i(1 downto 0);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "010000" => -- PAALTCFG0 (RW)
paaltcfg0 <= data_i(31 downto 0);
when others =>
end case;
when "0001" => -- GPIO
case device is
when "000010" => -- GPIOCAUSE_INV (RW)
gpiocause_inv <= data_i(3 downto 0);
when "000011" => -- GPIOMASK (RW)
gpiomask <= data_i(3 downto 0);
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
paddr <= data_i(15 downto 0);
when "0001" => -- PAOUT (RW)
paout <= data_i(15 downto 0);
when "0011" => -- PAIN_INV (RW)
pain_inv <= data_i(15 downto 0);
when "0100" => -- PAIN_MASK (RW)
pain_mask <= data_i(15 downto 0);
when others =>
end case;
when "010001" => -- PORTB
case funct is
when "0000" => -- PBDDR (RW)
pbddr <= data_i(15 downto 0);
when "0001" => -- PBOUT (RW)
pbout <= data_i(15 downto 0);
when "0011" => -- PBIN_INV (RW)
pbin_inv <= data_i(15 downto 0);
when "0100" => -- PBIN_MASK (RW)
pbin_mask <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0010" => -- timers
case device is
when "000010" => -- TIMERCAUSE_INV (RW)
timercause_inv <= data_i(3 downto 0);
when "000011" => -- TIMERMASK (RW)
timermask <= data_i(3 downto 0);
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
if data_i(31) = '1' then
timer1_set <= '1';
end if;
if timer1_set = '1' then
timer1 <= data_i(15 downto 0);
timer1_set <= '0';
end if;
when "0001" => -- TIMER1_PRE (RW)
timer1_pre <= data_i(2 downto 0);
when "0010" => -- TIMER1_CTC (RW)
timer1_ctc <= data_i(15 downto 0);
when "0011" => -- TIMER1_OCR (RW)
timer1_ocr <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0011" => -- UARTs
case device is
when "000010" => -- UARTCAUSE_INV (RW)
uartcause_inv <= data_i(3 downto 0);
when "000011" => -- UARTMASK (RW)
uartmask <= data_i(3 downto 0);
when "010000" => -- UART0
case funct is
when "0000" => -- UART0 (RW)
uart0_data_write <= data_i(7 downto 0);
uart0_enable_w <= '1';
when "0001" => -- UART0DIV (RW)
uart0_divisor <= data_i(15 downto 0);
when others =>
end case;
when "010001" => -- UART1
case funct is
when "0000" => -- UART1 (RW)
uart1_data_write <= data_i(7 downto 0);
uart1_enable_w <= '1';
when "0001" => -- UART1DIV (RW)
uart1_divisor <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when "0100" => -- SPIs
case device is
when "000010" => -- SPICAUSE_INV (RW)
spicause_inv <= data_i(3 downto 0);
when "000011" => -- SPIMASK (RW)
spimask <= data_i(3 downto 0);
when "010000" => -- SPI0
case funct is
when "0000" => -- SPI0 (RW)
spi0_data_write <= data_i(7 downto 0);
spi0_data_xfer <= '1';
when "0001" => -- SPI0CTRL (RW)
spi0_data_xfer <= data_i(0);
spi0_clk_div <= data_i(11 downto 3);
when others =>
end case;
when "010001" => -- SPI1
case funct is
when "0000" => -- SPI1 (RW)
spi1_data_write <= data_i(7 downto 0);
spi1_data_xfer <= '1';
when "0001" => -- SPI1CTRL (RW)
spi1_data_xfer <= data_i(0);
spi1_clk_div <= data_i(11 downto 3);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when others =>
end case;
else
uart0_enable_w <= '0';
uart1_enable_w <= '0';
async_mac_en_r <= '0';
sync_mac_en_r <= '0';
end if;
timer0 <= timer0 + 1;
if tmr1_pulse = '1' then
if (timer1 /= timer1_ctc) then
if timer1_set = '0' then
timer1 <= timer1 + 1;
end if;
else
int_timer1_ctc <= not int_timer1_ctc;
timer1 <= (others => '0');
end if;
end if;
end if;
end process;
process(clk_i, rst_i) -- TIMER1 prescaler
begin
if rst_i = '1' then
tmr1_dly <= '0';
tmr1_dly2 <= '0';
elsif clk_i'event and clk_i = '1' then
case timer1_pre is
when "001" =>
tmr1_dly <= timer0(2); -- /4
when "010" =>
tmr1_dly <= timer0(4); -- /16
when "011" =>
tmr1_dly <= timer0(6); -- /64
when "100" =>
tmr1_dly <= timer0(8); -- /256
when "101" =>
tmr1_dly <= timer0(10); -- /1024
when "110" =>
tmr1_dly <= timer0(12); -- /4096
when "111" =>
tmr1_dly <= timer0(14); -- /16384
when others =>
tmr1_dly <= timer0(0); -- /1
end case;
tmr1_dly2 <= tmr1_dly;
end if;
end process;
tmr1_pulse <= '1' when tmr1_dly /= tmr1_dly2 else '0';
int_timer1_ocr <= '1' when timer1 < timer1_ocr else '0';
uart0: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart0_divisor(11 downto 0),
enable_read => uart0_enable_r,
enable_write => uart0_enable_w,
data_in => uart0_data_write,
data_out => uart0_data_read,
uart_read => uart0_rx,
uart_write => uart0_tx,
busy_write => uart0_write_busy,
data_avail => uart0_data_avail
);
uart1: entity work.uart
port map(
clk => clk_i,
reset => rst_i,
divisor => uart1_divisor(11 downto 0),
enable_read => uart1_enable_r,
enable_write => uart1_enable_w,
data_in => uart1_data_write,
data_out => uart1_data_read,
uart_read => uart1_rx,
uart_write => uart1_tx,
busy_write => uart1_write_busy,
data_avail => uart1_data_avail
);
spi0: entity work.spi_master_slave
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clk_i,
rst_i => rst_i,
data_i => spi0_data_write,
data_o => spi0_data_read,
data_valid_o => spi0_data_valid,
wren_i => spi0_data_xfer,
clk_div_i => spi0_clk_div,
spi_ssn_i => spi0_ssn,
spi_clk_i => spi0_clk_i,
spi_clk_o => spi0_clk_o,
spi_do_o => spi0_do,
spi_di_i => spi0_di
);
spi1: entity work.spi_master_slave
generic map(
BYTE_SIZE => 8
)
port map( clk_i => clk_i,
rst_i => rst_i,
data_i => spi1_data_write,
data_o => spi1_data_read,
data_valid_o => spi1_data_valid,
wren_i => spi1_data_xfer,
clk_div_i => spi1_clk_div,
spi_ssn_i => spi1_ssn,
spi_clk_i => spi1_clk_i,
spi_clk_o => spi1_clk_o,
spi_do_o => spi1_do,
spi_di_i => spi1_di
);
sync_mac_en_o <= sync_mac_en_r;
sync_mac_rst_o <= sync_mac_rst_r;
sync_mac_o <= sync_mac_r;
async_mac_en_o <= async_mac_en_r;
async_mac_rst_o <= async_mac_rst_r;
async_mac_o <= async_mac_r;
de_pause_o <= de_pause_r;
de_config_o <= de_config_r;
de_cde_sel_o <= de_cde_sel_r;
de_mde_sel_l_o <= de_mde_sel_l_r;
de_mde_sel_b_o <= de_mde_sel_b_r;
de_cde_ctrl_o <= de_cde_ctrl_r;
end peripherals_arch;
| gpl-2.0 | 0953033be5eded43f9aad0a78ad35934 | 0.549992 | 2.649414 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys3/sys_conf2.vhd | 1 | 1,151 | -- $Id: sys_conf2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0.1 use with ser=usr=100 MHz
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec (was 150)
constant sys_conf_clksdiv_usecdiv : integer := 100; -- default usec (was 60)
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200
end package sys_conf;
| gpl-3.0 | f4bde433dbeeb2cae3d6e6bbf814b900 | 0.586447 | 3.574534 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/s7_cmt_sfs_gsim.vhd | 1 | 4,995 | -- $Id: s7_cmt_sfs_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_sfs - sim
-- Description: Series-7 CMT for simple frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: xst 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1065 1.2 use sfs_gsim_core
-- 2016-08-18 799 1.1.1 remove 'assert false' from report statements
-- 2016-04-09 760 1.1 BUGFIX: correct mmcm range check boundaries
-- 2013-09-28 535 1.0 Initial version (derived from dcm_sfs_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s7_cmt_sfs;
architecture sim of s7_cmt_sfs is
begin
proc_init : process
-- currently frequency limits taken from Artix-7 speed grade -1
constant f_vcomin_pll : integer := 800;
constant f_vcomax_pll : integer := 1600;
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 450;
constant f_vcomin_mmcm : integer := 600;
constant f_vcomax_mmcm : integer := 1200;
constant f_pdmin_mmcm : integer := 10;
constant f_pdmax_mmcm : integer := 450;
variable t_vco : Delay_length := 0 ns;
variable t_vcomin : Delay_length := 0 ns;
variable t_vcomax : Delay_length := 0 ns;
variable t_pd : Delay_length := 0 ns;
variable t_pdmin : Delay_length := 0 ns;
variable t_pdmax : Delay_length := 0 ns;
begin
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
end if;
if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then
if GEN_TYPE = "PLL" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>56 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
end if; -- GEN_TYPE = "PLL"
if GEN_TYPE = "MMCM" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>106 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
report
"assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_mmcm) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_mmcm) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_mmcm) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_mmcm) + 1 ps;
end if; -- GEN_TYPE = "MMCM"
-- now common check whether VCO and PD frequency is in range
t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
t_vco := t_pd / VCO_MULTIPLY;
if t_vco<t_vcomin or t_vco>t_vcomax then
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
report "assert(PD frequency out of range)"
severity failure;
end if;
end if; -- one factor /= 1
wait;
end process proc_init;
-- generate clock
SFS: sfs_gsim_core
generic map (
VCO_DIVIDE => VCO_DIVIDE,
VCO_MULTIPLY => VCO_MULTIPLY,
OUT_DIVIDE => OUT_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end sim;
| gpl-3.0 | 0a7aab6e08f53161f9d36c1526fa9c63 | 0.558959 | 3.540043 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/nexys4d/tb/sys_conf_sim.vhd | 2 | 2,392 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n4 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2013-09-28 535 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- single clock design, clkser = clksys
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide;
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply;
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide;
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype;
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure further units -------------------------------------------------
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 9151d7e02a75b7d631c45179355e504b | 0.585284 | 3.921311 | false | true | false | false |
sjohann81/hf-risc | riscv/platform/spartan3_starterkit/spartan3.vhd | 1 | 4,864 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | c82741e8a086afb2a613d9e94e518c8f | 0.63014 | 2.615054 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd | 1 | 22,664 | -- $Id: sys_w11a_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n2 - syn
-- Description: w11a test design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/fx2rlink/rlink_sp1c_fx2
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/nxcramlib/nx_cram_memctl_as
-- bplib/fx2rlink/ioleds_sp1c_fx2
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rbus/rb_sres_or_2
--
-- Test bench: tb/tb_sys_w11a_n2
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.26-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2019-05-19 1150 14.7 131013 xc3s1200e-4 3219 8981 638 5796 ok: +dz11 66%
-- 2019-04-27 1140 14.7 131013 xc3s1200e-4 3087 ???? 588 5515 ok: +*buf 63%
-- 2019-03-02 1116 14.7 131013 xc3s1200e-4 3024 8246 526 5322 ok: +ibtst 61%
-- 2019-01-27 1108 14.7 131013 xc3s1200e-4 2976 8101 510 5201 ok: -iist
-- 2018-10-13 1055 14.7 131013 xc3s1200e-4 3097 8484 510 5471 ok: +dmpcnt
-- 2018-09-15 1045 14.7 131013 xc3s1200e-4 2860 7983 446 5098 ok: +KW11P
-- 2017-04-30 888 14.7 131013 xc3s1200e-4 2806 7865 446 5043 ok: +fx2dbg
-- 2017-03-04 858 14.7 131013 xc3s1200e-4 2740 7713 446 4912 ok: +DEUNA
-- 2017-01-29 846 14.7 131013 xc3s1200e-4 2696 7620 446 4857 ok: +int24
-- 2015-06-21 692 14.7 131013 xc3s1200e-4 2312 6716 414 4192 ok: rhrp fixes
-- 2015-06-04 686 14.7 131013 xc3s1200e-4 2311 6725 414 4198 ok: +TM11
-- 2015-05-14 680 14.7 131013 xc3s1200e-4 2232 6547 414 4083 ok: +RHRP
-- 2015-02-21 649 14.7 131013 xc3s1200e-4 1903 5512 382 3483 ok: +RL11
-- 2014-12-22 619 14.7 131013 xc3s1200e-4 1828 5131 366 3263 ok: +rbmon
-- 2014-12-20 614 14.7 131013 xc3s1200e-4 1714 4896 366 3125 ok: -RL11,rlv4
-- 2014-06-08 561 14.7 131013 xc3s1200e-4 1626 4821 360 3052 ok: +RL11
-- 2014-06-01 558 14.7 131013 xc3s1200e-4 1561 4597 334 2901 ok:
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 1541 4598 334 2889 ok: now + FX2 !
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II
-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II
-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II
-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II
-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II
-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II
-- " 306 10.1.02 K39 xc3s1200e-4 1309 4311 242 2665 ok: LP+PC+DL+II
-- " 306 9.2.02 J40 xc3s1200e-4 1316 4259 242 2656 ok: LP+PC+DL+II
-- " 306 9.1 J30 xc3s1200e-4 1311 4260 242 2643 ok: LP+PC+DL+II
-- " 306 8.2.03 I34 xc3s1200e-4 1371 4394 242 2765 ok: LP+PC+DL+II
-- 2010-06-13 305 11.4 L68 xc3s1200e-4 1318 4360 242 2629 ok: LP+PC+DL+II
-- 2010-06-12 304 11.4 L68 xc3s1200e-4 1323 4201 242 2574 ok: LP+PC+DL+II
-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II
-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
-- 2015-04-11 666 1.7.2 rearrange XON handling
-- 2015-02-21 649 1.7.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
-- 2015-02-15 647 1.7 drop bram and minisys options
-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address
-- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon
-- 2014-08-28 588 1.6 use new rlink v4 iface generics and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2013-04-20 509 1.4 added fx2 (cuff) support; ATOWIDTH=7
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-12-18 440 1.2.7 use rlink_sp1c
-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now
-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage
-- 2011-11-19 427 1.2.4 now numeric_std clean
-- 2011-11-17 426 1.2.3 use dcm_sfs now
-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.2.1 use now sn_humanio
-- 2010-12-30 351 1.2 ported to rbv3
-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
-- BUGFIX: resolve rbus address clash hio<->ibr
-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn;
-- rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-13 305 1.1.2 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-12 304 1.1.1 re-do LED driver logic (show cpu modes or cpurust)
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03 300 1.0.2 use default FAWIDTH for rri_core_serport
-- use s3_humanio_rri
-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7
-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)
------------------------------------------------------------------------------
--
-- w11a test design for nexys2
-- w11a + rlink + serport + cuff
--
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:6): select LED display mode
-- 0x w11 sys70 LED display (further controlled by SWI(3))
-- 10 FX2 debug: fx2 fifo states
-- 11 FX2 debug: fx2 fsm states
-- (5:4): select DSP
-- 00 abclkdiv & abclkdiv_f
-- 01 PC
-- 10 DISPREG
-- 11 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1): 1 enable XON
-- (0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LEDs if SWI(7) = 0 and SWI(3) = 1
-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
--
-- LEDs if SWI(7) = 0 and SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- LEDs if SWI(7) = 1
-- (7) fifo_ep4
-- (6) fifo_ep6
-- (5) fsm_rx
-- (4) fsm_tx
-- LEDs if SWI(7) = 1 and SWI(6) = 0
-- (3) flag_ep4_empty
-- (2) flag_ep4_almost
-- (1) flag_ep6_full
-- (0) flag_ep6_almost
-- LEDs if SWI(7) = 1 and SWI(6) = 1
-- (3) fsm_idle
-- (2) fsm_prep
-- (1) fsm_disp
-- (0) fsm_pipe
--
-- DP(3:0) shows IO activity
-- if SWI(2)=0 (serport)
-- (3): not SER_MONI.txok (shows tx back pressure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back pressure)
-- (0): SER_MONI.rxact (shows rx activity)
-- if SWI(2)=1 (fx2-usb)
-- (3): RB_SRES.busy (shows rbus back pressure)
-- (2): RLB_TXBUSY (shows tx back pressure)
-- (1): RLB_TXENA (shows tx activity)
-- (0): RLB_RXVAL (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.fx2lib.all;
use work.fx2rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n2 is -- top level
-- implements nexys2_fusp_cuff_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_w11a_n2;
architecture syn of sys_w11a_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal RLB_MONI : rlb_moni_type := rlb_moni_init;
signal SER_MONI : serport_moni_type := serport_moni_init;
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
signal LED70 : slv8 := (others=>'0');
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"02"; -- nexys2
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs -- clock generator -------------------
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce -- usec/msec clock divider -----------
generic map (
CDUWIDTH => 6,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 -----------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAFX2 => SWI(2),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
FX2_MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact
PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback
PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact
PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => GRESET,
ENAFX2 => SWI(2),
RB_SRES => RB_SRES,
RLB_MONI => RLB_MONI,
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED70,
DSP_DAT => DSP_DAT
);
proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------
variable iled : slv8 := (others=>'0');
begin
iled := (others=>'0');
if SWI(7) = '0' then
iled := LED70;
else
iled(7) := FX2_MONI.fifo_ep4;
iled(6) := FX2_MONI.fifo_ep6;
iled(5) := FX2_MONI.fsm_rx;
iled(4) := FX2_MONI.fsm_tx;
if SWI(6) = '0' then
iled(3) := FX2_MONI.flag_ep4_empty;
iled(2) := FX2_MONI.flag_ep4_almost;
iled(1) := FX2_MONI.flag_ep6_full;
iled(0) := FX2_MONI.flag_ep6_almost;
else
iled(3) := FX2_MONI.fsm_idle;
iled(2) := FX2_MONI.fsm_prep;
iled(1) := FX2_MONI.fsm_disp;
iled(0) := FX2_MONI.fsm_pipe;
end if;
end if;
LED <= iled;
end process proc_fx2leds;
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | 4676f639fface1d9e0299fa7c76a64f7 | 0.508295 | 2.958361 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd | 1 | 9,773 | -- $Id: sys_tst_sram_c7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_c7 - syn
-- Description: test of cmoda7 sram and its controller
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- tst_sram
-- bplib/cmoda7/c7_cram_memctl
-- bplib/bpgen/sn_humanio_eum_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_tst_sram_c7
--
-- Target Devices: generic
-- Tool versions: viv 2017.1-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1 1045 1355 18 5.0 469
-- 2019-02-02 1108 2018.3 xc7a35t-1 1045 1537 24 5.0 490
-- 2019-02-02 1108 2017.2 xc7a35t-1 1042 1541 24 5.0 494
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce
-- 2017-06-11 914 1.0 Initial version
-- 2017-06-11 912 0.5 First draft (derived from sys_tst_sram_n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.cmoda7lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_c7 is -- top level
-- implements cmoda7_sram_aif
port (
I_CLK12 : in slbit; -- 12 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3; -- c7 rgb-led 0
O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv19; -- sram: address lines
IO_MEM_DATA : inout slv8 -- sram: data lines
);
end sys_tst_sram_c7;
architecture syn of sys_tst_sram_c7 is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv17 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"09"; -- cmoda7
constant sysid_vers : slv8 := x"00";
begin
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 83.3,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK12,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => x"ffe8")
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 17)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
MEM_RESET => MEM_RESET,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
SRAMCTL : c7_sram_memctl
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
HIO : sn_humanio_emu_rbus
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3)
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
SMRB : sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
RB_LAM(0) <= RB_LAM_TST;
O_LED(1) <= SER_MONI.txact;
O_LED(0) <= SER_MONI.rxact;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
DSP_DP(7 downto 4) <= "0010";
DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
'0' & SER_MONI.abclkdiv_f;
-- setup unused outputs in cmoda7
O_RGBLED0_N <= (others=>'1');
end syn;
| gpl-3.0 | 991fa4b780bcc36d37e503a0544988e4 | 0.494219 | 3.107472 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_hio70.vhd | 1 | 2,669 | -- $Id: pdp11_hio70.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_hio70 - syn
-- Description: pdp11: hio led and dsp for sys70
--
-- Dependencies: pdp11_statleds
-- pdp11_ledmux
-- pdp11_dspmux
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_hio70 is -- hio led and dsp for sys70
generic (
LWIDTH : positive := 8; -- led width
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
port (
SEL_LED : in slbit; -- led select (0=stat;1=dr)
SEL_DSP : in slv2; -- dsp select
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
ABCLKDIV : in slv16; -- serport clock divider
DISPREG : in slv16; -- display register
LED : out slv(LWIDTH-1 downto 0); -- hio leds
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
end pdp11_hio70;
architecture syn of pdp11_hio70 is
signal STATLEDS : slv8 := (others=>'0');
begin
LED_CPU : pdp11_statleds
port map (
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
STATLEDS => STATLEDS
);
LED_MUX : pdp11_ledmux
generic map (
LWIDTH => LWIDTH)
port map (
SEL => SEL_LED,
STATLEDS => STATLEDS,
DM_STAT_EXP => DM_STAT_EXP,
LED => LED
);
DSP_MUX : pdp11_dspmux
generic map (
DCWIDTH => DCWIDTH)
port map (
SEL => SEL_DSP,
ABCLKDIV => ABCLKDIV,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
DSP_DAT => DSP_DAT
);
end syn;
| gpl-3.0 | 7935947a5a2976b27a052a06b8d7559f | 0.500562 | 3.611637 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd | 1 | 14,366 | -- $Id: sys_w11a_br_as7.vhd 1211 2021-08-28 11:20:34Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_br_as7 - syn
-- Description: w11a test design for as7
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- w11a/pdp11_bram_memctl
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_artys7
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x2mux
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_br_as7
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-05-19 1150 2017.2 xc7s50 2821 6206 273 68.0 1887 +dz11
-- 2019-02-02 1108 2018.3 xc7s50 2568 5811 170 67.5 1799
-- 2019-02-02 1108 2017.2 xc7s50 2556 5503 170 67.5 1666 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7s50 2333 5156 138 67.5 1592 +KW11P
-- 2018-08-11 1038 2018.2 xc7s50 2279 5369 138 67.5 1598
-- 2018-08-11 1038 2018.1 xc7s50 2279 5381 138 67.5 1597
-- 2018-08-11 1038 2017.4 xc7s50 2274 5137 138 67.5 1549
-- 2018-08-11 1038 2017.2 xc7s50 2271 5083 138 67.5 1560
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.2 use s7_cmt_1ce1ce
-- 2018-10-13 1055 1.1 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2018-08-11 1038 1.0 Initial version (derived from sys_w11a_aa7)
------------------------------------------------------------------------------
--
-- w11a test design for artys7 (using BRAM as memory)
-- w11a + rlink + serport
--
-- Usage of Arty S7 switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows bit 7:4, RGB bit 1:0 of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (1) kernel mode, non-wait
-- (0) user or supervisor mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (1:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR( 9:08)
-- RGB_G DR( 5:04)
-- RGB_R DR( 1:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_br_as7 is -- top level
-- implements artys7_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- artys7 switches
I_BTN : in slv4; -- artys7 buttons
O_LED : out slv4; -- artys7 leds
O_RGBLED0 : out slv3; -- artys7 rgb-led 0
O_RGBLED1 : out slv3 -- artys7 rgb-led 1
);
end sys_w11a_br_as7;
architecture syn of sys_w11a_br_as7 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv2 := (others=>'0');
signal RGB_G : slv2 := (others=>'0');
signal RGB_B : slv2 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"0a"; -- artys7
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
BRAM_CTL: pdp11_bram_memctl -- memory controller -----------------
generic map (
MAWIDTH => sys_conf_memctl_mawidth,
NBLOCK => sys_conf_memctl_nblock)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_artys7 -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x2mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | 01a6a30b04f71da97d6f062d0ed7c836 | 0.485452 | 3.267971 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32im_nodiv/int_control.vhd | 1 | 6,056 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity interrupt_controller is
port ( clock: in std_logic;
reset: in std_logic;
stall: in std_logic;
irq_vector_cpu: out std_logic_vector(31 downto 0);
irq_cpu: out std_logic;
irq_ack_cpu: in std_logic;
exception_cpu: in std_logic;
address_cpu: in std_logic_vector(31 downto 0);
data_in_cpu: out std_logic_vector(31 downto 0);
data_out_cpu: in std_logic_vector(31 downto 0);
data_w_cpu: in std_logic_vector(3 downto 0);
data_access_cpu: in std_logic;
addr_mem: out std_logic_vector(31 downto 0);
data_read_mem: in std_logic_vector(31 downto 0);
data_write_mem: out std_logic_vector(31 downto 0);
data_we_mem: out std_logic_vector(3 downto 0);
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0)
);
end interrupt_controller;
architecture arch_interrupt_controller of interrupt_controller is
signal irq_cause, irq_mask_reg, irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
signal periph_data, irq_vector_reg, irq_epc_reg: std_logic_vector(31 downto 0);
signal interrupt, irq: std_logic;
type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done);
signal pulse_state: pulse_state_type;
signal pulse_next_state: pulse_state_type;
signal periph_access, periph_access_dly, periph_access_we: std_logic;
signal data_we_mem_s: std_logic_vector(3 downto 0);
begin
-- address decoder, read from peripheral registers
process(clock, reset, periph_access, address_cpu, irq_vector_reg, irq_cause, irq_mask_reg, irq_status_reg, irq_epc_reg, data_read_mem, extio_in, extio_out_reg)
begin
if reset = '1' then
periph_data <= (others => '0');
elsif clock'event and clock = '1' then
if periph_access = '1' then
case address_cpu(7 downto 4) is
when "0000" => -- IRQ_VECTOR (RW)
periph_data <= irq_vector_reg;
when "0001" => -- IRQ_CAUSE (RO)
periph_data <= irq_cause(7 downto 0) & x"000000";
when "0010" => -- IRQ_MASK (RW)
periph_data <= irq_mask_reg(7 downto 0) & x"000000";
when "0011" => -- IRQ_STATUS (RW)
periph_data <= irq_status_reg & x"000000";
when "0100" => -- IRQ_EPC (RO)
periph_data <= irq_epc_reg(7 downto 0) & irq_epc_reg(15 downto 8) & irq_epc_reg(23 downto 16) & irq_epc_reg(31 downto 24);
when "1000" => -- EXTIO_IN (RO)
periph_data <= extio_in & x"000000";
when "1001" => -- EXTIO_OUT (RW)
periph_data <= extio_out_reg & x"000000";
when others =>
periph_data <= data_read_mem;
end case;
end if;
end if;
end process;
data_in_cpu <= data_read_mem when periph_access_dly = '0' else periph_data;
-- peripheral register logic, write to peripheral registers
process(clock, reset, address_cpu, data_out_cpu, periph_access, periph_access_we, irq_ack_cpu)
begin
if reset = '1' then
irq_vector_reg <= (others => '0');
irq_mask_reg <= (others => '0');
irq_status_reg <= (others => '0');
extio_out_reg <= (others => '0');
elsif clock'event and clock = '1' then
if periph_access = '1' and periph_access_we = '1' then
case address_cpu(7 downto 4) is
when "0000" => -- IRQ_VECTOR
irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
when "0010" => -- IRQ_MASK
irq_mask_reg <= data_out_cpu(31 downto 24);
when "0011" => -- IRQ_STATUS
irq_status_reg <= data_out_cpu(31 downto 24);
when "1001" => -- EXTIO_OUT
extio_out_reg <= data_out_cpu(31 downto 24);
when others =>
end case;
end if;
if irq_ack_cpu = '1' or exception_cpu = '1' then
irq_status_reg(0) <= '0'; -- IRQ_STATUS (clear master int bit on interrupt)
end if;
end if;
end process;
-- EPC register register load on interrupts
process(clock, reset, address_cpu, irq, irq_ack_cpu)
begin
if reset = '1' then
irq_epc_reg <= x"00000000";
elsif clock'event and clock = '1' then
if ((irq = '1' and irq_ack_cpu = '0') or exception_cpu = '1') then
irq_epc_reg <= address_cpu;
end if;
end if;
end process;
-- interrupt state machine
process(clock, reset, pulse_state, interrupt, irq_status_reg, stall)
begin
if reset = '1' then
pulse_state <= irq_idle;
pulse_next_state <= irq_idle;
irq <= '0';
elsif clock'event and clock = '1' then
if stall = '0' then
pulse_state <= pulse_next_state;
case pulse_state is
when irq_idle =>
if interrupt = '1' and irq_status_reg(0) = '1' then
pulse_next_state <= irq_int;
end if;
when irq_int =>
irq <= '1';
pulse_next_state <= irq_req;
when irq_req =>
if irq_ack_cpu = '1' then
irq <= '0';
pulse_next_state <= irq_ackn;
end if;
when irq_ackn =>
pulse_next_state <= irq_done;
when irq_done =>
if irq_status_reg(0) = '1' then
pulse_next_state <= irq_idle;
end if;
when others =>
pulse_next_state <= irq_idle;
end case;
end if;
end if;
end process;
-- data / peripheral access delay
process(clock, reset, irq_ack_cpu, periph_access, stall)
begin
if reset = '1' then
periph_access_dly <= '0';
elsif clock'event and clock = '1' then
if stall = '0' then
periph_access_dly <= periph_access;
end if;
end if;
end process;
periph_access <= '1' when address_cpu(31 downto 27) = "11110" and data_access_cpu = '1' else '0';
periph_access_we <= '1' when periph_access <= '1' and data_w_cpu /= "0000" else '0';
-- memory address / write enable muxes
addr_mem <= address_cpu;
data_write_mem <= data_out_cpu;
data_we_mem_s <= data_w_cpu when data_access_cpu = '1' and periph_access = '0' else "0000";
data_we_mem <= data_we_mem_s;
-- interrupts masking
interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
irq_cause <= extio_in;
irq_cpu <= irq;
irq_vector_cpu <= irq_vector_reg;
extio_out <= extio_out_reg;
end arch_interrupt_controller;
| gpl-2.0 | 5939f43111651fb8c75ed8741c1dd089 | 0.633091 | 2.761514 | false | false | false | false |
wfjm/w11 | rtl/vlib/comlib/tb/tb_cdata2byte.vhd | 1 | 7,923 | -- $Id: tb_cdata2byte.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_cdata2byte - sim
-- Description: Test bench for cdata2byte and byte2cdata
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_cdata2byte [UUT]
--
-- To test: cdata2byte
-- byte2cdata
--
-- Target Devices: generic
--
-- Verified (with tb_cdata2byte_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2014-10-25 599 _ssim 0.31 17.1 sc6slx16 c: ok
-- 2014-10-25 599 - 0.31 - c: ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-10-25 599 1.1.1 use wait_* to control stim and moni timing
-- 2014-10-19 598 1.1 use simfifo with shared variables
-- 2014-10-18 597 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.comlib.all;
entity tb_cdata2byte is
end tb_cdata2byte;
architecture sim of tb_cdata2byte is
constant clk_dsc : clock_dsc := (20 ns, 1 ns, 1 ns);
constant clk_offset : Delay_length := 200 ns;
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal C2B_ESCXON : slbit := '0';
signal C2B_ESCFILL : slbit := '0';
signal C2B_DI : slv9 := (others=>'0');
signal C2B_ENA : slbit := '0';
signal C2B_BUSY : slbit := '0';
signal C2B_DO : slv8 := (others=>'0');
signal C2B_VAL : slbit := '0';
signal B2C_BUSY : slbit := '0';
signal B2C_DO : slv9 := (others=>'0');
signal B2C_VAL : slbit := '0';
signal B2C_HOLD : slbit := '0';
shared variable sv_sff_monc_cnt : natural := 0;
shared variable sv_sff_monc_arr : simfifo_type(0 to 7, 7 downto 0);
shared variable sv_sff_monb_cnt : natural := 0;
shared variable sv_sff_monb_arr : simfifo_type(0 to 7, 8 downto 0);
begin
CLKGEN : simclk
generic map (
PERIOD => clk_dsc.period,
OFFSET => clk_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_cdata2byte
port map (
CLK => CLK,
RESET => RESET,
C2B_ESCXON => C2B_ESCXON,
C2B_ESCFILL => C2B_ESCFILL,
C2B_DI => C2B_DI,
C2B_ENA => C2B_ENA,
C2B_BUSY => C2B_BUSY,
C2B_DO => C2B_DO,
C2B_VAL => C2B_VAL,
B2C_BUSY => B2C_BUSY,
B2C_DO => B2C_DO,
B2C_VAL => B2C_VAL,
B2C_HOLD => B2C_HOLD
);
proc_stim: process
file fstim : text open read_mode is "tb_cdata2byte_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idel : natural := 0;
variable ilen : natural := 0;
variable nbusy : integer := 0;
variable iesc : slbit := '0';
variable itxdata9 : slbit := '0';
variable itxdata : slv8 := (others=>'0');
variable irxdata9 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable dat9 : slv9 := (others=>'0');
begin
wait_nextstim(CLK, clk_dsc);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait_nextstim(CLK, clk_dsc);
RESET <= '0';
wait_nextstim(CLK, clk_dsc);
when ".wait " => -- .wait
read_ea(iline, idel);
wait_nextstim(CLK, clk_dsc, idel);
when "escxon" => -- escxon
read_ea(iline, iesc);
C2B_ESCXON <= iesc;
when "escfil" => -- escfil
read_ea(iline, iesc);
C2B_ESCFILL <= iesc;
when "bhold " => -- bhold
read_ea(iline, idel);
read_ea(iline, ilen);
B2C_HOLD <= '1' after idel*clk_dsc.period,
'0' after (idel+ilen)*clk_dsc.period;
when "data " => -- data
read_ea(iline, itxdata9);
readgen_ea(iline, itxdata);
read_ea(iline, irxdata9);
if irxdata9 = '0' then
simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, itxdata);
else
readgen_ea(iline, irxdata);
simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, c_cdata_escape);
simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, irxdata);
end if;
dat9 := itxdata9 & itxdata;
simfifo_put(sv_sff_monb_cnt, sv_sff_monb_arr, dat9);
C2B_DI <= dat9;
C2B_ENA <= '1';
wait_stim2moni(CLK, clk_dsc);
wait_untilsignal(CLK, clk_dsc, C2B_BUSY, '0', nbusy);
writetimestamp(oline, CLK_CYCLE, ": stim ");
write(oline, itxdata9, right, 2);
write(oline, itxdata, right, 9);
writeoptint(oline, " nbusy=", nbusy);
writeline(output, oline);
wait_nextstim(CLK, clk_dsc);
C2B_ENA <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait_nextstim(CLK, clk_dsc, 12);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_monc: process
variable oline : line;
variable nhold : integer := 0;
begin
loop
wait_nextmoni(CLK, clk_dsc);
if C2B_VAL = '1' then
if B2C_BUSY = '1' then -- c2b_hold = b2c_busy !
nhold := nhold + 1;
else
writetimestamp(oline, CLK_CYCLE, ": monc ");
write(oline, string'(" "));
write(oline, C2B_DO, right, 9);
writeoptint(oline, " nhold=", nhold);
simfifo_writetest(oline, sv_sff_monc_cnt, sv_sff_monc_arr, C2B_DO);
writeline(output, oline);
nhold := 0;
end if;
end if;
end loop;
end process proc_monc;
proc_monb: process
variable oline : line;
variable nhold : integer := 0;
begin
loop
wait_nextmoni(CLK, clk_dsc);
if B2C_VAL = '1' then
if B2C_HOLD = '1' then
nhold := nhold + 1;
else
writetimestamp(oline, CLK_CYCLE, ": monb ");
write(oline, B2C_DO(8), right, 2);
write(oline, B2C_DO(7 downto 0), right, 9);
writeoptint(oline, " nhold=", nhold);
simfifo_writetest(oline, sv_sff_monb_cnt, sv_sff_monb_arr, B2C_DO);
writeline(output, oline);
nhold := 0;
end if;
end if;
end loop;
end process proc_monb;
end sim;
| gpl-3.0 | 43eee8644584c45b0ad44e9d783b9ea5 | 0.508267 | 3.526035 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_conf.vhd | 1 | 1,868 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | 45c4488dbd5be818c9f400e5c62ddb45 | 0.630086 | 3.537879 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/fifo_2c_dram.vhd | 1 | 12,058 | -- $Id: fifo_2c_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram - syn
-- Description: FIFO, two clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: ram_1swar_1ar_gen
-- genlib/gray_cnt_n
-- genlib/gray2bin_gen
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35 !! NOT FOR VIVADO !!
-- Note: for usage with Vivado use fifo_2c_dram2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.1 use capture+sync flops; reset now glitch free
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-12-28 107 1.0.1 VAL=0 in cycle after RESETR=1
-- 2007-12-28 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2011-11-13 Rev 424: ise 13.1 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m LUT.s Flop Slice CLKW CLKR (xst est.)
-- 4 16 41 32 12 38 54 135MHz 115MHz ( 16 words)
-- 5 16 65 64 14 40 80 113MHz 116MHz ( 32 words)
-- - 2007-12-28 Rev 106: ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m Flop CLKW CLKR (xst est.)
-- 4 16 40 32 42 141MHz 165MHz ( 16 words)
-- 5 16 65 64 52 108MHz 108MHz ( 32 words)
-- 6 16 95 128 61 111MHz 113MHz ( 64 words)
-- 7 16 149 256 74 100MHz 96MHz (128 words)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.memlib.all;
entity fifo_2c_dram is -- fifo, 2 clock, dram based
generic (
AWIDTH : positive := 5; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end fifo_2c_dram;
architecture syn of fifo_2c_dram is
type regw_type is record
raddr_c : slv(AWIDTH-1 downto 0); -- read address (capt from CLKR)
raddr_s : slv(AWIDTH-1 downto 0); -- read address (sync in CLKW)
sizew : slv(AWIDTH-1 downto 0); -- slots to write
busy : slbit; -- busy flag
rstw : slbit; -- resetw active
rstw_sc : slbit; -- resetw (sync-capt from CLKR-CLKW)
rstw_ss : slbit; -- resetw (sync-sync from CLKR-CLKW)
rstr_c : slbit; -- resetr (capt from CLKR)
rstr_s : slbit; -- resetr (sync from CLKR)
end record regw_type;
constant regw_init : regw_type := (
slv(to_unsigned(0,AWIDTH)), -- raddr_c
slv(to_unsigned(0,AWIDTH)), -- raddr_s
slv(to_unsigned(0,AWIDTH)), -- sizew
'0', -- busy
'0','0','0', -- rstw,rstw_sc,rstw_ss
'0','0' -- rstr_c,rstr_s
);
type regr_type is record
waddr_c : slv(AWIDTH-1 downto 0); -- write address (capt from CLKW)
waddr_s : slv(AWIDTH-1 downto 0); -- write address (sync in CLKR)
sizer : slv(AWIDTH-1 downto 0); -- slots to read
val : slbit; -- valid flag
rstr : slbit; -- resetr active
rstr_sc : slbit; -- resetr (sync-capt from CLKW-CLKR)
rstr_ss : slbit; -- resetr (sync-sync from CLKW-CLKR)
rstw_c : slbit; -- resetw (capt from CLKW)
rstw_s : slbit; -- resetw (sync from CLKW)
end record regr_type;
constant regr_init : regr_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr_c
slv(to_unsigned(0,AWIDTH)), -- waddr_s
slv(to_unsigned(0,AWIDTH)), -- sizer
'0', -- val
'0','0','0', -- rstr,rstr_sc,rstr_ss
'0','0' -- rstw_c,rstw_s
);
signal R_REGW : regw_type := regw_init; -- write side state registers
signal N_REGW : regw_type := regw_init; -- next values write side
signal R_REGR : regr_type := regr_init; -- read side state registers
signal N_REGR : regr_type := regr_init; -- next values read side
signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal GCW_RST : slbit := '0';
signal GCW_CE : slbit := '0';
signal GCR_RST : slbit := '0';
signal GCR_CE : slbit := '0';
begin
RAM : ram_1swar_1ar_gen -- dual ported memory
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLKW,
WE => GCW_CE,
ADDRA => WADDR,
ADDRB => RADDR,
DI => DI,
DOA => open,
DOB => DO
);
GCW : gray_cnt_gen -- gray counter for write address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKW,
RESET => GCW_RST,
CE => GCW_CE,
DATA => WADDR
);
GCR : gray_cnt_gen -- gray counter for read address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKR,
RESET => GCR_RST,
CE => GCR_CE,
DATA => RADDR
);
G2B_WW : gray2bin_gen -- gray->bin for waddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => WADDR, DO => WADDR_BIN);
G2B_WR : gray2bin_gen -- gray->bin for waddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGR.waddr_s, DO => WADDR_S_BIN);
G2B_RR : gray2bin_gen -- gray->bin for raddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => RADDR, DO => RADDR_BIN);
G2B_RW : gray2bin_gen -- gray->bin for raddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGW.raddr_s, DO => RADDR_S_BIN);
--
-- write side --------------------------------------------------------------
--
proc_regw: process (CLKW)
begin
if rising_edge(CLKW) then
R_REGW <= N_REGW;
end if;
end process proc_regw;
proc_nextw: process (R_REGW, RESETW, ENA, R_REGR,
RADDR, RADDR_S_BIN, WADDR_BIN)
variable r : regw_type := regw_init;
variable n : regw_type := regw_init;
variable ibusy : slbit := '0';
variable igcw_ce : slbit := '0';
variable igcw_rst : slbit := '0';
variable isizew : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGW;
n := R_REGW;
isizew := slv(unsigned(RADDR_S_BIN) + unsigned(not WADDR_BIN));
ibusy := '0';
igcw_ce := '0';
igcw_rst := '0';
if unsigned(isizew) = 0 then -- if no free slots
ibusy := '1'; -- next cycle busy=1
end if;
if ENA='1' and r.busy='0' then -- if ena=1 and this cycle busy=0
igcw_ce := '1'; -- write this value
if unsigned(isizew) = 1 then -- if this last free slot
ibusy := '1'; -- next cycle busy=1
end if;
end if;
if RESETW = '1' then -- reset(write side) request
n.rstw := '1'; -- set RSTW flag
elsif r.rstw_ss = '1' then -- request gone and return seen
n.rstw := '0'; -- clear RSTW flag
end if;
if r.rstw='1' and r.rstw_ss='1' then -- RSTW seen on write and read side
igcw_rst := '1'; -- clear write address counter
end if;
if r.rstr_s = '1' then -- RSTR active
igcw_rst := '1'; -- clear write address counter
end if;
if RESETW='1' or r.rstw='1' or r.rstw_ss='1' or r.rstr_s='1'
then -- RESETW or RESETR active
ibusy := '1'; -- signal write side busy
isizew := (others=>'1');
end if;
n.busy := ibusy;
n.sizew := isizew;
n.raddr_c := RADDR; -- data captuture from CLKR
n.raddr_s := r.raddr_c;
n.rstw_sc := R_REGR.rstw_s;
n.rstw_ss := r.rstw_sc;
n.rstr_c := R_REGR.rstr;
n.rstr_s := r.rstr_c;
N_REGW <= n;
GCW_CE <= igcw_ce;
GCW_RST <= igcw_rst;
BUSY <= r.busy;
SIZEW <= r.sizew;
end process proc_nextw;
--
-- read side ---------------------------------------------------------------
--
proc_regr: process (CLKR)
begin
if rising_edge(CLKR) then
R_REGR <= N_REGR;
end if;
end process proc_regr;
proc_nextr: process (R_REGR, RESETR, HOLD, R_REGW,
WADDR, WADDR_S_BIN, RADDR_BIN)
variable r : regr_type := regr_init;
variable n : regr_type := regr_init;
variable ival : slbit := '0';
variable igcr_ce : slbit := '0';
variable igcr_rst : slbit := '0';
variable isizer : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGR;
n := R_REGR;
isizer := slv(unsigned(WADDR_S_BIN) - unsigned(RADDR_BIN));
ival := '1';
igcr_ce := '0';
igcr_rst := '0';
if unsigned(isizer) = 0 then -- if nothing to read
ival := '0'; -- next cycle val=0
end if;
if r.val='1' and HOLD='0' then -- this cycle val=1 and no hold
igcr_ce := '1'; -- retire this value
if unsigned(isizer) = 1 then -- if this is last one
ival := '0'; -- next cycle val=0
end if;
end if;
if RESETR = '1' then -- reset(read side) request
n.rstr := '1'; -- set RSTR flag
elsif r.rstr_ss = '1' then -- request gone and return seen
n.rstr := '0'; -- clear RSTR flag
end if;
if r.rstr='1' and r.rstr_ss='1' then -- RSTR seen on read and write side
igcr_rst := '1'; -- clear read address counter
end if;
if r.rstw_s = '1' then -- RSTW active
igcr_rst := '1'; -- clear read address counter
end if;
if RESETR='1' or r.rstr='1' or r.rstr_ss='1' or r.rstw_s='1'
then -- RESETR or RESETW active
ival := '0'; -- signal read side empty
isizer := (others=>'0');
end if;
n.val := ival;
n.sizer := isizer;
n.waddr_c := WADDR; -- data captuture from CLKW
n.waddr_s := r.waddr_c;
n.rstr_sc := R_REGW.rstr_s;
n.rstr_ss := r.rstr_sc;
n.rstw_c := R_REGW.rstw;
n.rstw_s := r.rstw_c;
N_REGR <= n;
GCR_CE <= igcr_ce;
GCR_RST <= igcr_rst;
VAL <= r.val;
SIZER <= r.sizer;
end process proc_nextr;
end syn;
| gpl-3.0 | 4a42c30fb6fd8c9fbd60ffabf187ae1b | 0.490546 | 3.52367 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys3/sys_tst_serloop1_n3.vhd | 1 | 7,174 | -- $Id: sys_tst_serloop1_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n3 - syn
-- Description: Tester serial link for nexys3 (serport_1clock case)
--
-- Dependencies: genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop1_n3;
architecture syn of sys_tst_serloop1_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 8,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
| gpl-3.0 | f4b8d5a8efe8358876806103f9df8adb | 0.47477 | 3.263876 | false | false | false | false |
wfjm/w11 | rtl/bplib/s3board/tb/s3board_dummy.vhd | 1 | 2,506 | -- $Id: s3board_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s3board_dummy - syn
-- Description: s3board minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_s3board
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.1.3 rename input pin CLK -> I_CLK50
-- 2010-04-17 278 1.1.2 rename sram_dummy -> s3_sram_dummy
-- 2007-12-16 101 1.1.1 use _N for active low
-- 2007-12-09 100 1.1 add sram memory signals, dummy handle them
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.s3boardlib.all;
entity s3board_dummy is -- S3BOARD dummy (base; loopback)
-- implements s3board_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end s3board_dummy;
architecture syn of s3board_dummy is
begin
O_TXD <= I_RXD;
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
| gpl-3.0 | 3a44bce8a7b6b782be849a9778175d09 | 0.506784 | 3.229381 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd | 1 | 2,472 | -- $Id: ram_2swsr_wfirst_gen_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_wfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-through' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_wfirst_gen;
architecture syn of ram_2swsr_wfirst_gen is
begin
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "WRITE_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
end syn;
| gpl-3.0 | eb10b7b546188a3524b8a619c3646124 | 0.520631 | 3.635294 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4d/tb/nexys4d_dram_dummy.vhd | 1 | 3,583 | -- $Id: nexys4d_dram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys4d_dram_dummy - syn
-- Description: nexys4d target (base; serport loopback, dram project)
--
-- Dependencies: -
-- To test: tb_nexys4d_dram
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version (derived from nexys4_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nexys4d_dram_dummy is -- NEXYS 4DDR dummy (base+dram)
-- implements nexys4d_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end nexys4d_dram_dummy;
architecture syn of nexys4d_dram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
DDR2_DQ <= (others=>'Z');
DDR2_DQS_P <= (others=>'Z');
DDR2_DQS_N <= (others=>'Z');
DDR2_ADDR <= (others=>'0');
DDR2_BA <= (others=>'0');
DDR2_RAS_N <= '1';
DDR2_CAS_N <= '1';
DDR2_WE_N <= '1';
DDR2_CK_P <= (others=>'0');
DDR2_CK_N <= (others=>'1');
DDR2_CKE <= (others=>'0');
DDR2_CS_N <= (others=>'1');
DDR2_DM <= (others=>'0');
DDR2_ODT <= (others=>'0');
end syn;
| gpl-3.0 | 5f7ccdce3d10d75ab6d05702e87d3a7d | 0.478928 | 3.184889 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys2/sys_tst_serloop1_n2.vhd | 1 | 7,054 | -- $Id: sys_tst_serloop1_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n2 - syn
-- Description: Tester serial link for nexys2
--
-- Dependencies: genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-16 439 13.1 O40d xc3s1200e-4 433 634 64 490 t 13.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop1_n2;
architecture syn of sys_tst_serloop1_n2 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
end syn;
| gpl-3.0 | 75a93e52a83bb92d1efb04ac2a9a00c0 | 0.475191 | 3.26423 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_ounit.vhd | 1 | 3,541 | -- $Id: pdp11_ounit.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ounit - syn
-- Description: pdp11: arithmetic unit for addresses (ounit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end pdp11_ounit;
architecture syn of pdp11_ounit is
-- --------------------------------------
begin
process (DSRC, DDST, DTMP, PC, ASEL, AZERO,
IREG8, VMDOUT, CONST, BSEL, OPSUB)
variable ma : slv16 := (others=>'0'); -- effective port a data
variable mb : slv16 := (others=>'0'); -- effective port b data
variable sum : slv16 := (others=>'0'); -- sum
variable nzo : slbit := '0';
begin
if AZERO = '0' then
case ASEL is
when c_ounit_asel_dsrc => ma := DSRC;
when c_ounit_asel_ddst => ma := DDST;
when c_ounit_asel_dtmp => ma := DTMP;
when c_ounit_asel_pc => ma := PC;
when others => null;
end case;
else
ma := (others=>'0');
end if;
case BSEL is
when c_ounit_bsel_ireg6 => mb := "000000000" & IREG8(5 downto 0) & "0";
when c_ounit_bsel_ireg8 => mb := IREG8(7) & IREG8(7) & IREG8(7) &
IREG8(7) & IREG8(7) & IREG8(7) &
IREG8(7) & IREG8 & "0";
when c_ounit_bsel_vmdout => mb := VMDOUT;
when c_ounit_bsel_const => mb := "0000000" & CONST;
when others => null;
end case;
if OPSUB = '0' then
sum := slv(unsigned(ma) + unsigned(mb));
else
sum := slv(unsigned(ma) - unsigned(mb));
end if;
nzo := '0';
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
DOUT <= sum;
NZOUT(1) <= sum(15);
NZOUT(0) <= nzo;
end process;
end syn;
| gpl-3.0 | ae99f3acecca0989bc7c6c9a75e9f0f4 | 0.475572 | 3.688542 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rb_mon_sb.vhd | 1 | 2,601 | -- $Id: rb_mon_sb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_mon_sb - sim
-- Description: simbus wrapper for rbus monitor (for tb's)
--
-- Dependencies: simbus
-- simlib/simclkcnt
-- rb_mon
-- Test bench: -
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-08-28 588 4.0 use new rlink v4 iface and 4 bit STAT
-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global
-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- use sbcntl_sbf_cpmon def
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-12-23 105 1.2 added AP_LAM display
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rblib.all;
entity rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv4 -- rbus: status flags
);
end rb_mon_sb;
architecture sim of rb_mon_sb is
signal ENA : slbit := '0';
signal CLK_CYCLE : integer := 0;
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
ENA <= to_x01(SB_CNTL(ENAPIN));
RBMON : rb_mon
generic map (
DBASE => DBASE)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => ENA,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
end sim;
| gpl-3.0 | e7be2297f5c6ab35e808ac484f3a8069 | 0.535563 | 3.369171 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4d/tb/tb_nexys4d.vhd | 1 | 4,917 | -- $Id: tb_nexys4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d - sim
-- Description: Test bench for nexys4d (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4d_core
-- serport/tb/serport_master_tb
-- nexys4d_aif [UUT]
--
-- To test: generic, any nexys4d_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-01-04 838 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4dlib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4d is
end tb_nexys4d;
architecture sim of tb_nexys4d is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4d_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4d_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | e9d8fad7dcdc83f13c433c872c604e8b | 0.528981 | 3.288963 | false | false | false | false |
nanomolina/vhdl_examples | ALU/test_ALU.vhd | 2 | 1,656 | library ieee;
use ieee.std_logic_1164.all;
entity test_ALU is
end entity;
architecture test_ALU_arq of test_ALU is
component ALU
port (a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
alucontrol: in bit_vector(2 downto 0);
zero: out bit;
result: out std_logic_vector(31 downto 0));
end component;
signal a, b, result: std_logic_vector(31 downto 0);
signal alucontrol: bit_vector(2 downto 0);
signal zero: bit;
begin
u0: ALU port map(a, b, alucontrol, zero, result);
process
begin
alucontrol <= "011";
wait for 5 fs;
alucontrol <= "001";
wait for 8 fs;
alucontrol <= "010";
wait for 5 fs;
alucontrol <= "100";
wait for 2 fs;
alucontrol <= "000";
wait for 15 fs;
alucontrol <= "110";
wait for 30 fs;
alucontrol <= "101";
wait for 5 fs;
alucontrol <= "110";
end process;
process
begin
wait for 15 fs;
a <= x"66271000";
wait for 9 fs;
a <= x"00000001";
wait for 6 fs;
a <= x"22211000";
wait for 20 fs;
a <= x"11118700";
wait for 15 fs;
a <= x"11111111";
wait for 21 fs;
a <= x"00000001";
end process;
process
begin
wait for 30 fs;
b <= x"AA110000";
wait for 15 fs;
b <= x"FFFF0001";
wait for 7 fs;
b <= x"11110001";
wait for 9 fs;
b <= x"CCCD0000";
wait for 9 fs;
b <= x"ABCD0000";
end process;
end architecture;
| gpl-3.0 | 5ab3aab2425309a13663dc5440678058 | 0.51087 | 3.82448 | false | false | false | false |
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