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sjohann81/hf-risc | riscv/sim/hf-riscv_sram_ctl_tb.vhd | 1 | 8,701 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use ieee.numeric_std.all;
entity tb is
generic(
address_width: integer := 13;
memory_file : string := "code.txt";
log_file: string := "out.txt";
uart_support : string := "no"
);
end tb;
architecture tb of tb is
signal clock_in, reset, data, stall, stall_sig: std_logic := '0';
signal uart_read, uart_write: std_logic;
signal boot_enable_n, ram_enable_n, ram_dly: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
signal data_read_sram: std_logic_vector(31 downto 0);
signal data_mode: std_logic_vector(2 downto 0);
signal burst, wr, rd, stall_dly, stall_dly2, stall_sram, spi_cs, spi_clk, spi_mosi, spi_miso, hold_n: std_logic := '0';
begin
process --25Mhz system clock
begin
clock_in <= not clock_in;
wait for 20 ns;
clock_in <= not clock_in;
wait for 20 ns;
end process;
process
begin
wait for 4 ms;
gpio_sig <= not gpio_sig;
wait for 100 us;
gpio_sig <= not gpio_sig;
end process;
gpioa_in <= "0000" & gpio_sig & "000";
process
begin
stall <= not stall;
wait for 123 ns;
stall <= not stall;
wait for 123 ns;
end process;
reset <= '0', '1' after 5 ns, '0' after 500 ns;
ext_irq <= "0000000" & periph_irq;
boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_sig = '0') or reset = '1' else '1';
ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_sig = '0') or reset = '1' else '1';
rd <= '1' when (address(31 downto 28) = "0110" and data_we = "0000" and stall_dly2 = '0') else '0';
wr <= '1' when (address(31 downto 28) = "0110" and data_we /= "0000" and stall_dly2 = '0') else '0';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else
data_read_sram when address(31 downto 28) = "0110" or stall_dly2 = '1' else data_read_ram;
data_w_n_ram <= not data_we;
hold_n <= '1';
burst <= '0';
stall_sig <= stall_sram;
process(clock_in, reset, stall_sram)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
stall_dly <= '0';
stall_dly2 <= '0';
elsif clock_in'event and clock_in = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
stall_dly <= stall_sram;
stall_dly2 <= stall_dly;
end if;
end process;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock_in,
rst_i => reset,
stall_i => stall_sig,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => data_mode,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock_in,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
sram_ctrl_core: entity work.spi_sram_ctrl
port map( clk_i => clock_in,
rst_i => reset,
addr_i => address(23 downto 0),
data_i => data_write,
data_o => data_read_sram,
burst_i => burst,
bmode_i => data_mode(2),
hmode_i => data_mode(1),
wr_i => wr,
rd_i => rd,
data_ack_o => open,
cpu_stall_o => stall_sram,
spi_cs_n_o => spi_cs,
spi_clk_o => spi_clk,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso
);
spi_sram: entity work.M23LC1024
port map( SI_SIO0 => spi_mosi,
SO_SIO1 => spi_miso,
SCK => spi_clk,
CS_N => spi_cs,
SIO2 => open,
HOLD_N_SIO3 => hold_n,
RESET => reset
);
-- boot ROM
boot0lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 0)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(7 downto 0)
);
boot0ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 1)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(15 downto 8)
);
boot1lb: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 2)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(23 downto 16)
);
boot1ub: entity work.boot_ram
generic map ( memory_file => "boot.txt",
data_width => 8,
address_width => 12,
bank => 3)
port map(
clk => clock_in,
addr => address(11 downto 2),
cs_n => boot_enable_n,
we_n => '1',
data_i => (others => '0'),
data_o => data_read_boot(31 downto 24)
);
-- RAM
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock_in,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
-- debug process
debug:
if uart_support = "no" generate
process(clock_in, address)
file store_file : text open write_mode is "debug.txt";
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if clock_in'event and clock_in = '1' then
if address = x"f00000d0" and data = '0' then
data <= '1';
index := conv_integer(data_write(30 downto 24));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
writeline(store_file, hex_file_line);
line_length := 0;
end if;
else
data <= '0';
end if;
end if;
end process;
end generate;
process(clock_in, reset, address)
begin
if reset = '1' then
elsif clock_in'event and clock_in = '0' then
assert address /= x"e0000000" report "end of simulation" severity failure;
assert (address < x"70000000") or (address >= x"e0000000") report "out of memory region" severity failure;
assert address /= x"40000104" report "handling IRQ" severity warning;
end if;
end process;
end tb;
| gpl-2.0 | 113e291c6fdba33fc82a5f23b815ace1 | 0.589817 | 2.686323 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/fifo_2c_dram2.vhd | 1 | 11,981 | -- $Id: fifo_2c_dram2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram2 - syn
-- Description: FIFO, two clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: ram_1swar_1ar_gen
-- genlib/gray_cnt_n
-- genlib/gray2bin_gen
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.3; ghdl 0.33-0.35 !! NOT FOR ISE !!
-- Note: for usage with ISE use fifo_2c_dram
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-24 751 1.0 Initial version (derived from fifo_2c_dram, is
-- exactly same logic, re-written to allow proper
-- usage of vivado constraints)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.memlib.all;
entity fifo_2c_dram2 is -- fifo, 2 clock, dram based (v2)
generic (
AWIDTH : positive := 5; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end fifo_2c_dram2;
architecture syn of fifo_2c_dram2 is
subtype a_range is integer range AWIDTH-1 downto 0; -- addr value regs
signal RW_RADDR_S0 : slv(a_range) := (others=>'0'); -- read addr: CLKR->CLKW
signal RW_RADDR_S1 : slv(a_range) := (others=>'0'); -- read addr: CLKW->CLKW
signal RW_SIZEW : slv(a_range) := (others=>'0'); -- slots to write
signal RW_BUSY : slbit := '0'; -- busy flag
signal RW_RSTW : slbit := '0'; -- resetw active
signal RW_RSTW_E_S0 : slbit := '0'; -- rstw-echo: CLKR->CLKW
signal RW_RSTW_E_S1 : slbit := '0'; -- rstw-echo: CLKW->CLKW
signal RW_RSTR_S0 : slbit := '0'; -- resetr: CLKR->CLKW
signal RW_RSTR_S1 : slbit := '0'; -- resetr: CLKW->CLKW
signal NW_SIZEW : slv(a_range) := (others=>'0'); -- slots to write
signal NW_BUSY : slbit := '0'; -- busy flag
signal NW_RSTW : slbit := '0'; -- resetw active
signal RR_WADDR_S0 : slv(a_range) := (others=>'0'); -- write addr: CLKW->CLKR
signal RR_WADDR_S1 : slv(a_range) := (others=>'0'); -- write addr: CLKR->CLKR
signal RR_SIZER : slv(a_range) := (others=>'0'); -- slots to read
signal RR_VAL: slbit := '0'; -- valid flag
signal RR_RSTR : slbit := '0'; -- resetr active
signal RR_RSTR_E_S0 : slbit := '0'; -- rstr-echo: CLKW->CLKR
signal RR_RSTR_E_S1 : slbit := '0'; -- rstr-echo: CLKR->CLKR
signal RR_RSTW_S0 : slbit := '0'; -- resetw: CLKW->CLKR
signal RR_RSTW_S1 : slbit := '0'; -- resetw: CLKR->CLKR
signal NR_SIZER : slv(a_range) := (others=>'0'); -- slots to read
signal NR_VAL: slbit := '0'; -- valid flag
signal NR_RSTR : slbit := '0'; -- resetr active
signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN_W : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN_R : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN_R : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN_W : slv(AWIDTH-1 downto 0) := (others=>'0');
signal GCW_RST : slbit := '0';
signal GCW_CE : slbit := '0';
signal GCR_RST : slbit := '0';
signal GCR_CE : slbit := '0';
attribute ASYNC_REG: string;
attribute ASYNC_REG of RW_RADDR_S0 : signal is "true";
attribute ASYNC_REG of RW_RADDR_S1 : signal is "true";
attribute ASYNC_REG of RW_RSTW_E_S0 : signal is "true";
attribute ASYNC_REG of RW_RSTW_E_S1 : signal is "true";
attribute ASYNC_REG of RW_RSTR_S0 : signal is "true";
attribute ASYNC_REG of RW_RSTR_S1 : signal is "true";
attribute ASYNC_REG of RR_WADDR_S0 : signal is "true";
attribute ASYNC_REG of RR_WADDR_S1 : signal is "true";
attribute ASYNC_REG of RR_RSTR_E_S0 : signal is "true";
attribute ASYNC_REG of RR_RSTR_E_S1 : signal is "true";
attribute ASYNC_REG of RR_RSTW_S0 : signal is "true";
attribute ASYNC_REG of RR_RSTW_S1 : signal is "true";
begin
RAM : ram_1swar_1ar_gen -- dual ported memory
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLKW,
WE => GCW_CE,
ADDRA => WADDR,
ADDRB => RADDR,
DI => DI,
DOA => open,
DOB => DO
);
GCW : gray_cnt_gen -- gray counter for write address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKW,
RESET => GCW_RST,
CE => GCW_CE,
DATA => WADDR
);
GCR : gray_cnt_gen -- gray counter for read address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKR,
RESET => GCR_RST,
CE => GCR_CE,
DATA => RADDR
);
G2B_WW : gray2bin_gen -- gray->bin for waddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => WADDR, DO => WADDR_BIN_W);
G2B_WR : gray2bin_gen -- gray->bin for waddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => RR_WADDR_S1, DO => WADDR_BIN_R);
G2B_RR : gray2bin_gen -- gray->bin for raddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => RADDR, DO => RADDR_BIN_R);
G2B_RW : gray2bin_gen -- gray->bin for raddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => RW_RADDR_S1, DO => RADDR_BIN_W);
--
-- write side --------------------------------------------------------------
--
proc_regw: process (CLKW)
begin
if rising_edge(CLKW) then
RW_RADDR_S0 <= RADDR; -- sync 0: CLKR->CLKW
RW_RADDR_S1 <= RW_RADDR_S0; -- sync 1: CLKW
RW_SIZEW <= NW_SIZEW;
RW_BUSY <= NW_BUSY;
RW_RSTW <= NW_RSTW;
RW_RSTW_E_S0 <= RR_RSTW_S1; -- sync 0: CLKR->CLKW
RW_RSTW_E_S1 <= RW_RSTW_E_S0; -- sync 1: CLKW
RW_RSTR_S0 <= RR_RSTR; -- sync 0: CLKR->CLKW
RW_RSTR_S1 <= RW_RSTR_S0; -- sync 1: CLKW
end if;
end process proc_regw;
proc_nextw: process (RW_BUSY, RW_SIZEW, RW_RSTW, RW_RSTW_E_S1, RW_RSTR_S1,
ENA, RESETW, RADDR_BIN_W, WADDR_BIN_W)
variable ibusy : slbit := '0';
variable irstw : slbit := '0';
variable igcw_ce : slbit := '0';
variable igcw_rst : slbit := '0';
variable isizew : slv(a_range) := (others=>'0');
begin
isizew := slv(unsigned(RADDR_BIN_W) + unsigned(not WADDR_BIN_W));
ibusy := '0';
igcw_ce := '0';
igcw_rst := '0';
if unsigned(isizew) = 0 then -- if no free slots
ibusy := '1'; -- next cycle busy=1
end if;
if ENA='1' and RW_BUSY='0' then -- if ena=1 and this cycle busy=0
igcw_ce := '1'; -- write this value
if unsigned(isizew) = 1 then -- if this last free slot
ibusy := '1'; -- next cycle busy=1
end if;
end if;
irstw := RW_RSTW;
if RESETW = '1' then -- reset(write side) request
irstw := '1'; -- set RSTW flag
elsif RW_RSTW_E_S1 = '1' then -- request gone and return seen
irstw := '0'; -- clear RSTW flag
end if;
if RW_RSTW='1' and RW_RSTW_E_S1='1' then -- RSTW seen on write and read side
igcw_rst := '1'; -- clear write address counter
end if;
if RW_RSTR_S1 = '1' then -- RSTR active
igcw_rst := '1'; -- clear write address counter
end if;
if RESETW='1' or RW_RSTW='1' or RW_RSTW_E_S1='1' or RW_RSTR_S1='1'
then -- RESETW or RESETR active
ibusy := '1'; -- signal write side busy
isizew := (others=>'1');
end if;
NW_BUSY <= ibusy;
NW_RSTW <= irstw;
NW_SIZEW <= isizew;
GCW_CE <= igcw_ce;
GCW_RST <= igcw_rst;
BUSY <= RW_BUSY;
SIZEW <= RW_SIZEW;
end process proc_nextw;
--
-- read side ---------------------------------------------------------------
--
proc_regr: process (CLKR)
begin
if rising_edge(CLKR) then
RR_WADDR_S0 <= WADDR; -- sync 0: CLKW->CLKR
RR_WADDR_S1 <= RR_WADDR_S0; -- sync 1: CLKW
RR_SIZER <= NR_SIZER;
RR_VAL <= NR_VAL;
RR_RSTR <= NR_RSTR;
RR_RSTR_E_S0 <= RW_RSTR_S1; -- sync 0: CLKW->CLKR
RR_RSTR_E_S1 <= RR_RSTR_E_S0; -- sync 1: CLKW
RR_RSTW_S0 <= RW_RSTW; -- sync 0: CLKW->CLKR
RR_RSTW_S1 <= RR_RSTW_S0; -- sync 1: CLKW
end if;
end process proc_regr;
proc_nextr: process (RR_VAL, RR_SIZER, RR_RSTR, RR_RSTR_E_S1, RR_RSTW_S1,
HOLD, RESETR, RADDR_BIN_R, WADDR_BIN_R)
variable ival : slbit := '0';
variable irstr : slbit := '0';
variable igcr_ce : slbit := '0';
variable igcr_rst : slbit := '0';
variable isizer : slv(a_range) := (others=>'0');
begin
isizer := slv(unsigned(WADDR_BIN_R) - unsigned(RADDR_BIN_R));
ival := '1';
igcr_ce := '0';
igcr_rst := '0';
if unsigned(isizer) = 0 then -- if nothing to read
ival := '0'; -- next cycle val=0
end if;
if RR_VAL='1' and HOLD='0' then -- this cycle val=1 and no hold
igcr_ce := '1'; -- retire this value
if unsigned(isizer) = 1 then -- if this is last one
ival := '0'; -- next cycle val=0
end if;
end if;
irstr := RR_RSTR;
if RESETR = '1' then -- reset(read side) request
irstr := '1'; -- set RSTR flag
elsif RR_RSTR_E_S1 = '1' then -- request gone and return seen
irstr := '0'; -- clear RSTR flag
end if;
if RR_RSTR='1' and RR_RSTR_E_S1='1' then -- RSTR seen on read and write side
igcr_rst := '1'; -- clear read address counter
end if;
if RR_RSTW_S1 = '1' then -- RSTW active
igcr_rst := '1'; -- clear read address counter
end if;
if RESETR='1' or RR_RSTR='1' or RR_RSTR_E_S1='1' or RR_RSTW_S1='1'
then -- RESETR or RESETW active
ival := '0'; -- signal read side empty
isizer := (others=>'0');
end if;
NR_VAL <= ival;
NR_RSTR <= irstr;
NR_SIZER <= isizer;
GCR_CE <= igcr_ce;
GCR_RST <= igcr_rst;
VAL <= RR_VAL;
SIZER <= RR_SIZER;
end process proc_nextr;
end syn;
| gpl-3.0 | 3c6b3f5076bd7ced3cb523b196526864 | 0.499124 | 3.427059 | false | false | false | false |
nanomolina/vhdl_examples | RAM/dmem.vhd | 2 | 1,084 | -- -a --ieee=synopsis -fexplicit -Wc,-m32 -Wa,--32
-- -e -Wa,--32 -Wl,-m32
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dmem is
port (a: in std_logic_vector(31 downto 0);
wd: in std_logic_vector(31 downto 0);
clk, we: in bit;
rd: out std_logic_vector(31 downto 0));
end entity;
architecture arq_dmem of dmem is
type mem is array (0 to 63) of std_logic_vector(31 downto 0);
begin
process(clk)
variable my_mem: mem;
variable address: std_logic_vector(5 downto 0);
variable pos_a: integer;
begin
for pos in 0 to 63 loop --Inicializo mi memoria
my_mem(pos) := std_logic_vector(to_unsigned(pos, 32));
end loop;
if clk'EVENT and clk='1' then
address := a(7 downto 2);
pos_a := to_integer(unsigned(address));
if we='1' then
my_mem(pos_a) := wd;
rd <= wd;
else
rd <= my_mem(pos_a);
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 81bcf2414cd2df9f52c4220b2063b044 | 0.546125 | 3.398119 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd | 1 | 3,393 | -- $Id: ram_2swsr_wfirst_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_wfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-through' semantics (as block RAM).
-- The code is inspired by Xilinx example rams_16.vhd. The
-- 'ram_style' attribute is set to 'block', this will
-- force in XST a synthesis as block RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_wfirst_gen;
architecture syn of ram_2swsr_wfirst_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
shared variable sv_ram : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of sv_ram : variable is "block";
signal R_DOA : slv(DWIDTH-1 downto 0) := datzero;
signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
begin
proc_clka: process (CLKA)
begin
if rising_edge(CLKA) then
if ENA = '1' then
if WEA = '1' then
sv_ram(to_integer(unsigned(ADDRA))) := DIA;
end if;
R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
end if;
end if;
end process proc_clka;
proc_clkb: process (CLKB)
begin
if rising_edge(CLKB) then
if ENB = '1' then
if WEB = '1' then
sv_ram(to_integer(unsigned(ADDRB))) := DIB;
end if;
R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
end if;
end if;
end process proc_clkb;
DOA <= R_DOA;
DOB <= R_DOB;
end syn;
| gpl-3.0 | f47165ff6a170cef1daa083453b33afe | 0.558798 | 3.50879 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/IO Adapter/pb_AddressDecoder.vhdl | 1 | 5,781 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze Generic AddressDecoder Unit
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
use PoC.vectors.all;
use PoC.io.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity PicoBlaze_AddressDecoder is
generic (
DEVICE_NAME : STRING;
BUS_NAME : STRING;
READ_MAPPINGS : T_PB_PORTNUMBER_MAPPING_VECTOR;
WRITE_MAPPINGS : T_PB_PORTNUMBER_MAPPING_VECTOR;
WRITEK_MAPPINGS : T_PB_PORTNUMBER_MAPPING_VECTOR
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
In_WriteStrobe : in STD_LOGIC;
In_WriteStrobe_K : in STD_LOGIC;
In_ReadStrobe : in STD_LOGIC;
In_Address : in T_SLV_8;
In_Data : in T_SLV_8;
Out_WriteStrobe : out STD_LOGIC;
Out_ReadStrobe : out STD_LOGIC;
Out_WriteAddress : out T_SLV_8;
Out_ReadAddress : out T_SLV_8;
Out_Data : out T_SLV_8
);
end entity;
architecture rtl of PicoBlaze_AddressDecoder is
attribute KEEP : BOOLEAN;
signal WriteAddress : T_SLV_8;
signal WriteAddress_K : T_SLV_8;
signal ReadAddress : T_SLV_8;
signal WriteHit : STD_LOGIC;
signal WriteHit_K : STD_LOGIC;
signal ReadHit : STD_LOGIC;
signal Out_WriteStrobe_i : STD_LOGIC := '0';
signal Out_ReadStrobe_i : STD_LOGIC;
signal Out_WriteAddress_i : T_SLV_8 := (others => '0');
signal Out_ReadAddress_i : T_SLV_8;
signal Out_Data_i : T_SLV_8 := (others => '0');
begin
process(In_Address, In_WriteStrobe, In_WriteStrobe_K, In_ReadStrobe)
begin
WriteAddress <= (others => '0');
WriteAddress_K <= (others => '0');
ReadAddress <= (others => '0');
WriteHit <= '0';
WriteHit_K <= '0';
ReadHit <= '0';
assert PB_VERBOSE
report "PicoBlaze_AddressDecoder: Report PortNumber mappings for device " & str_trim(DEVICE_NAME) &
" on bus " & str_trim(BUS_NAME)
severity NOTE;
for i in WRITEK_MAPPINGS'range loop
assert PB_VERBOSE
report " Map PortNumber " & INTEGER'image(WRITEK_MAPPINGS(i).PortNumber) &
" to register number " & INTEGER'image(WRITEK_MAPPINGS(i).RegNumber) &
" as K-writeable"
severity NOTE;
if (In_Address(3 downto 0) = to_slv(WRITEK_MAPPINGS(i).PortNumber, 4)) then
WriteAddress_K <= to_slv(WRITEK_MAPPINGS(i).RegNumber, WriteAddress_K'length);
WriteHit_K <= In_WriteStrobe_K;
end if;
end loop;
for i in WRITE_MAPPINGS'range loop
assert PB_VERBOSE
report " Map PortNumber " & INTEGER'image(WRITE_MAPPINGS(i).PortNumber) &
" to register number " & INTEGER'image(WRITE_MAPPINGS(i).RegNumber) &
" as writeable"
severity NOTE;
if (In_Address = to_slv(WRITE_MAPPINGS(i).PortNumber, In_Address'length)) then
WriteAddress <= to_slv(WRITE_MAPPINGS(i).RegNumber, WriteAddress'length);
WriteHit <= In_WriteStrobe;
end if;
end loop;
for i in READ_MAPPINGS'range loop
assert PB_VERBOSE
report " Map PortNumber " & INTEGER'image(READ_MAPPINGS(i).PortNumber) &
" to register number " & INTEGER'image(READ_MAPPINGS(i).RegNumber) &
" as readable"
severity NOTE;
if (In_Address = to_slv(READ_MAPPINGS(i).PortNumber, In_Address'length)) then
ReadAddress <= to_slv(READ_MAPPINGS(i).RegNumber, ReadAddress'length);
ReadHit <= In_ReadStrobe;
end if;
end loop;
end process;
process(Clock, ReadHit, ReadAddress)
begin
if rising_edge(Clock) then
if (WriteHit_K = '1') then
Out_WriteStrobe_i <= WriteHit_K;
Out_WriteAddress_i <= WriteAddress_K;
else
Out_WriteStrobe_i <= WriteHit;
Out_WriteAddress_i <= WriteAddress;
end if;
Out_Data_i <= In_Data;
end if;
Out_ReadStrobe_i <= ReadHit;
Out_ReadAddress_i <= ReadAddress;
end process;
Out_WriteStrobe <= Out_WriteStrobe_i;
Out_ReadStrobe <= Out_ReadStrobe_i;
Out_WriteAddress <= Out_WriteAddress_i;
Out_ReadAddress <= Out_ReadAddress_i;
Out_Data <= Out_Data_i;
end;
| apache-2.0 | 96515a3c6dfce1db9eb6336038446f5e | 0.560457 | 3.290268 | false | true | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/return_stack.vhd | 1 | 3,023 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity return_stack is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
push : in std_logic;
pop : in std_logic
);
end return_stack;
architecture behavioral of return_stack is
type stack_array is array(15 downto 0) of std_logic_vector(31 downto 0);
signal stg_elements : stack_array; --The storage elements of the stack
signal stg_elements_next : stack_array; --The next values to be taken on in the storage stack
begin
--The process that synchronously writes new values to the elements
sync : process (clk, rst) is
begin
if rst = '1' then
stg_elements <= (others => (others => '0'));
elsif falling_edge(clk) then
stg_elements <= stg_elements_next;
end if;
end process;
--Selects what goes on the stg_elements_next signal, depending on the operation
stg_el_sel : process (rst, stg_elements, push, pop, data_in) is
begin
if rst = '1' then
stg_elements_next <= (others => (others => '0'));
else
if push = '1' then --Pusing a value onto to storage elements from data_in
stg_elements_next(0) <= data_in;
stg_elements_next(1) <= stg_elements(0);
stg_elements_next(2) <= stg_elements(1);
stg_elements_next(3) <= stg_elements(2);
stg_elements_next(4) <= stg_elements(3);
stg_elements_next(5) <= stg_elements(4);
stg_elements_next(6) <= stg_elements(5);
stg_elements_next(7) <= stg_elements(6);
stg_elements_next(8) <= stg_elements(7);
stg_elements_next(9) <= stg_elements(8);
stg_elements_next(10) <= stg_elements(9);
stg_elements_next(11) <= stg_elements(10);
stg_elements_next(12) <= stg_elements(11);
stg_elements_next(13) <= stg_elements(12);
stg_elements_next(14) <= stg_elements(13);
stg_elements_next(15) <= stg_elements(14);
elsif pop = '1' then --Popping a value off the storage elements
stg_elements_next(0) <= stg_elements(1);
stg_elements_next(1) <= stg_elements(2);
stg_elements_next(2) <= stg_elements(3);
stg_elements_next(3) <= stg_elements(4);
stg_elements_next(4) <= stg_elements(5);
stg_elements_next(5) <= stg_elements(6);
stg_elements_next(6) <= stg_elements(7);
stg_elements_next(7) <= stg_elements(8);
stg_elements_next(8) <= stg_elements(9);
stg_elements_next(9) <= stg_elements(10);
stg_elements_next(10) <= stg_elements(11);
stg_elements_next(11) <= stg_elements(12);
stg_elements_next(12) <= stg_elements(13);
stg_elements_next(13) <= stg_elements(14);
stg_elements_next(14) <= stg_elements(15);
stg_elements_next(15) <= (others => '0');
else
stg_elements_next <= stg_elements;
end if;
end if;
end process;
data_out <= stg_elements(0);
end Behavioral;
| mit | 6e132c271e3b10f3efa813c7a35c3698 | 0.6348 | 3.00497 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32i/int_control.vhd | 2 | 6,694 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity interrupt_controller is
port ( clock: in std_logic;
reset: in std_logic;
stall: in std_logic;
stall_cpu: out std_logic;
mwait_cpu: out std_logic;
irq_vector_cpu: out std_logic_vector(31 downto 0);
irq_cpu: out std_logic;
irq_ack_cpu: in std_logic;
exception_cpu: in std_logic;
inst_addr_cpu: in std_logic_vector(31 downto 0);
inst_in_cpu: out std_logic_vector(31 downto 0);
data_addr_cpu: in std_logic_vector(31 downto 0);
data_in_cpu: out std_logic_vector(31 downto 0);
data_out_cpu: in std_logic_vector(31 downto 0);
data_w_cpu: in std_logic_vector(3 downto 0);
data_access_cpu: in std_logic;
addr_mem: out std_logic_vector(31 downto 0);
data_read_mem: in std_logic_vector(31 downto 0);
data_write_mem: out std_logic_vector(31 downto 0);
data_we_mem: out std_logic_vector(3 downto 0);
extio_in: in std_logic_vector(7 downto 0);
extio_out: out std_logic_vector(7 downto 0)
);
end interrupt_controller;
architecture arch_interrupt_controller of interrupt_controller is
signal irq_cause, irq_mask_reg, irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
signal periph_data, irq_vector_reg, irq_epc_reg, inst_reg: std_logic_vector(31 downto 0);
signal interrupt, irq, data_access_cpu_dly: std_logic;
type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done);
signal pulse_state: pulse_state_type;
signal pulse_next_state: pulse_state_type;
signal periph_access, periph_access_dly, periph_access_we: std_logic;
signal data_we_mem_s: std_logic_vector(3 downto 0);
begin
-- address decoder, read from peripheral registers
process(clock, reset, periph_access, data_addr_cpu, irq_vector_reg, irq_cause, irq_mask_reg, irq_status_reg, irq_epc_reg, data_read_mem, extio_in, extio_out_reg)
begin
if reset = '1' then
periph_data <= (others => '0');
elsif clock'event and clock = '1' then
if periph_access = '1' then
case data_addr_cpu(7 downto 4) is
when "0000" => -- IRQ_VECTOR (RW)
periph_data <= irq_vector_reg;
when "0001" => -- IRQ_CAUSE (RO)
periph_data <= irq_cause(7 downto 0) & x"000000";
when "0010" => -- IRQ_MASK (RW)
periph_data <= irq_mask_reg(7 downto 0) & x"000000";
when "0011" => -- IRQ_STATUS (RW)
periph_data <= irq_status_reg & x"000000";
when "0100" => -- IRQ_EPC (RO)
periph_data <= irq_epc_reg(7 downto 0) & irq_epc_reg(15 downto 8) & irq_epc_reg(23 downto 16) & irq_epc_reg(31 downto 24);
when "1000" => -- EXTIO_IN (RO)
periph_data <= extio_in & x"000000";
when "1001" => -- EXTIO_OUT (RW)
periph_data <= extio_out_reg & x"000000";
when others =>
periph_data <= data_read_mem;
end case;
end if;
end if;
end process;
inst_in_cpu <= data_read_mem when data_access_cpu = '0' else inst_reg;
data_in_cpu <= data_read_mem when periph_access_dly = '0' else periph_data;
-- peripheral register logic, write to peripheral registers
process(clock, reset, data_addr_cpu, data_out_cpu, periph_access, periph_access_we, irq_ack_cpu)
begin
if reset = '1' then
irq_vector_reg <= (others => '0');
irq_mask_reg <= (others => '0');
irq_status_reg <= (others => '0');
extio_out_reg <= (others => '0');
elsif clock'event and clock = '1' then
if periph_access = '1' and periph_access_we = '1' then
case data_addr_cpu(7 downto 4) is
when "0000" => -- IRQ_VECTOR
irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
when "0010" => -- IRQ_MASK
irq_mask_reg <= data_out_cpu(31 downto 24);
when "0011" => -- IRQ_STATUS
irq_status_reg <= data_out_cpu(31 downto 24);
when "1001" => -- EXTIO_OUT
extio_out_reg <= data_out_cpu(31 downto 24);
when others =>
end case;
end if;
if irq_ack_cpu = '1' or exception_cpu = '1' then
irq_status_reg(0) <= '0'; -- IRQ_STATUS (clear master int bit on interrupt)
end if;
end if;
end process;
-- EPC register register load on interrupts
process(clock, reset, inst_addr_cpu, irq, irq_ack_cpu)
begin
if reset = '1' then
irq_epc_reg <= x"00000000";
elsif clock'event and clock = '1' then
if ((irq = '1' and irq_ack_cpu = '0') or exception_cpu = '1') then
irq_epc_reg <= inst_addr_cpu;
end if;
end if;
end process;
-- interrupt state machine
process(clock, reset, pulse_state, interrupt, irq_status_reg, stall)
begin
if reset = '1' then
pulse_state <= irq_idle;
pulse_next_state <= irq_idle;
irq <= '0';
elsif clock'event and clock = '1' then
if stall = '0' then
pulse_state <= pulse_next_state;
case pulse_state is
when irq_idle =>
if interrupt = '1' and irq_status_reg(0) = '1' then
pulse_next_state <= irq_int;
end if;
when irq_int =>
irq <= '1';
pulse_next_state <= irq_req;
when irq_req =>
if irq_ack_cpu = '1' then
irq <= '0';
pulse_next_state <= irq_ackn;
end if;
when irq_ackn =>
pulse_next_state <= irq_done;
when irq_done =>
if irq_status_reg(0) = '1' then
pulse_next_state <= irq_idle;
end if;
when others =>
pulse_next_state <= irq_idle;
end case;
end if;
end if;
end process;
-- data / peripheral access delay
process(clock, reset, irq_ack_cpu, periph_access, stall, data_read_mem)
begin
if reset = '1' then
periph_access_dly <= '0';
data_access_cpu_dly <= '0';
inst_reg <= (others => '0');
elsif clock'event and clock = '1' then
if stall = '0' then
periph_access_dly <= periph_access;
data_access_cpu_dly <= data_access_cpu;
if (data_access_cpu = '0') then
inst_reg <= data_read_mem;
end if;
end if;
end if;
end process;
periph_access <= '1' when data_addr_cpu(31 downto 27) = "11110" and data_access_cpu = '1' else '0';
periph_access_we <= '1' when periph_access <= '1' and data_w_cpu /= "0000" else '0';
-- memory address / write enable muxes
addr_mem <= data_addr_cpu when data_access_cpu = '1' else inst_addr_cpu;
data_write_mem <= data_out_cpu;
data_we_mem_s <= data_w_cpu when data_access_cpu = '1' and periph_access = '0' else "0000";
data_we_mem <= data_we_mem_s;
mwait_cpu <= '1' when data_access_cpu = '1' and data_access_cpu_dly = '0' else '0';
stall_cpu <= stall;
-- interrupts masking
interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
irq_cause <= extio_in;
irq_cpu <= irq;
irq_vector_cpu <= irq_vector_reg;
extio_out <= extio_out_reg;
end arch_interrupt_controller;
| gpl-2.0 | 51edecc500c088fd08c9bb7c2614b276 | 0.632805 | 2.730016 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/clkdivce.vhd | 1 | 3,235 | -- $Id: clkdivce.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: clkgen - syn
-- Description: Generate usec and msec enable signals
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
-- Note: for test bench usage a copy of the clkdivce entity, with _tb
-- appended to the name, has been created in the /tb sub folder.
-- Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end clkdivce;
architecture syn of clkdivce is
type regs_type is record
ucnt : slv(CDUWIDTH-1 downto 0); -- usec clock divider counter
mcnt : slv10; -- msec clock divider counter
usec : slbit; -- usec pulse
msec : slbit; -- msec pulse
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(USECDIV-1,CDUWIDTH)),
slv(to_unsigned(MSECDIV-1,10)),
'0','0'
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024
report "assert(USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024): " &
"USECDIV too large for given CDUWIDTH or MSECDIV>1024"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
n.usec := '0';
n.msec := '0';
n.ucnt := slv(unsigned(r.ucnt) - 1);
if unsigned(r.ucnt) = 0 then
n.usec := '1';
n.ucnt := slv(to_unsigned(USECDIV-1,CDUWIDTH));
n.mcnt := slv(unsigned(r.mcnt) - 1);
if unsigned(r.mcnt) = 0 then
n.msec := '1';
n.mcnt := slv(to_unsigned(MSECDIV-1,10));
end if;
end if;
N_REGS <= n;
CE_USEC <= r.usec;
CE_MSEC <= r.msec;
end process proc_next;
end syn;
| gpl-3.0 | 35de6aa2c5801a9c8bb6199fc64ad128 | 0.55796 | 3.618568 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4/tb/tb_nexys4.vhd | 1 | 5,408 | -- $Id: tb_nexys4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4 - sim
-- Description: Test bench for nexys4 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4_core
-- serport/tb/serport_master_tb
-- nexys4_aif [UUT]
--
-- To test: generic, any nexys4_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.3.5 use sfs_gsim_core
-- 2016-09-02 805 1.3.4 tbcore_rlink without CLK_STOP now
-- 2016-02-20 734 1.3.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4 is
end tb_nexys4;
architecture sim of tb_nexys4 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 0a13e3039ea26d3bb7860bf8ae645aff | 0.539571 | 3.224806 | false | false | false | false |
VHDLTool/VHDL_Handbook_CNE | Extras/VHDL/CNE_01700_bad.vhd | 1 | 2,985 | -------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01700_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of rising edge detection signal: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01700_bad is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Signal on which detect edges
o_D : out std_logic -- Rising edge of i_D
);
end CNE_01700_bad;
architecture Behavioral of CNE_01700_bad is
signal D_r1 : std_logic; -- i_D registered 1 time
signal D_r2 : std_logic; -- i_D registered 2 times
begin
-- Rising edge detection process
P_detection: process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D_r1 <= '0';
D_r2 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
D_r2 <= D_r1;
end if;
end process;
o_D <= D_r1 and not D_r2;
end Behavioral;
--CODE | gpl-3.0 | ce533f4bfd19ea1f048ec03a3c83c27e | 0.485427 | 4.38326 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd | 1 | 7,168 | -- $Id: sys_tst_serloop2_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop2_n4 - syn
-- Description: Tester serial link for nexys4 (serport_2clock case)
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bpgen/bp_rs232_4line_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock2
-- tst_serloop
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-02-02 1108 2018.3 xc7a100t-1 537 512 16 0 236
-- 2019-02-02 1108 2017.2 xc7a100t-1 537 549 16 0 238
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce
-- 2016-06-05 722 1.0.1 use CDUWIDTH=7 for CLKS, 120 MHz is natural choice
-- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n4)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop2_n4 is -- top level
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_serloop2_n4;
architecture syn of sys_tst_serloop2_n4 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 8,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => sys_conf_clksys_msecdiv,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => sys_conf_clkser_msecdiv)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
DSP_DP => DSP_DP(3 downto 0)
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
SERPORT : serport_2clock2
generic map (
CDWIDTH => 12,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
-- show autobauder clock divisor on msb of display
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
-- setup unused outputs in nexys4
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 3b85de6f1f7905a7d47c341b06b67a0f | 0.494699 | 3.306273 | false | false | false | false |
jasonpeng/cg3207-proj | RegisterFile.vhd | 1 | 2,501 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity RegisterFile is
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RegWrite : in STD_LOGIC;
RegWriteAddr : in STD_LOGIC_VECTOR(4 downto 0);
RegWriteData : in STD_LOGIC_VECTOR(31 downto 0);
RegAddr_1 : in STD_LOGIC_VECTOR(4 downto 0);
RegAddr_2 : in STD_LOGIC_VECTOR(4 downto 0);
RegData_1 : out STD_LOGIC_VECTOR(31 downto 0);
RegData_2 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_1 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_2 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_3 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_4 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_5 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_6 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_7 : out STD_LOGIC_VECTOR(31 downto 0);
Reg_8 : out STD_LOGIC_VECTOR(31 downto 0)
);
end RegisterFile;
architecture beh of RegisterFile is
TYPE rf is array (0 to 31) of std_logic_vector (31 downto 0);
signal rf_array: rf := (
x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000"
);
begin
Reg_1 <= rf_array(1);
Reg_2 <= rf_array(2);
Reg_3 <= rf_array(3);
Reg_4 <= rf_array(4);
Reg_5 <= rf_array(5);
Reg_6 <= rf_array(6);
Reg_7 <= rf_array(7);
Reg_8 <= rf_array(8);
-- write data at rising_edge
process(Clk,RESET, RegWrite, RegWriteAddr, RegWriteData)
variable index_write : integer range 0 to 31;
begin
if (RESET='1') then
for i in 0 to 31 loop
rf_array(i) <= (others => '0');
end loop;
elsif(Clk'event and Clk = '1') then
index_write := to_integer(unsigned(RegWriteAddr));
if (RegWrite='1' AND index_write /= 0) then
rf_array(index_write) <= RegWriteData;
end if;
end if;
end process;
-- read data at falling_edge
process(RESET, RegAddr_1, RegAddr_2)
variable index_1 : integer range 0 to 31;
variable index_2 : integer range 0 to 31;
begin
if (RESET='1') then
RegData_1 <= (others => 'Z');
RegData_2 <= (others => 'Z');
else
index_1 := to_integer(unsigned(RegAddr_1));
index_2 := to_integer(unsigned(RegAddr_2));
RegData_1 <= rf_array(index_1);
RegData_2 <= rf_array(index_2);
end if;
end process;
end beh;
| gpl-2.0 | e33041bec2a7511997282cfc0d9635b5 | 0.658137 | 2.822799 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/data_stack.vhd | 2 | 5,345 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity data_stack is
port(
clk : in std_logic;
rst : in std_logic;
e0_sel : in std_logic_vector(1 downto 0);
e1_sel : in std_logic_vector(1 downto 0);
e2_sel : in std_logic_vector(1 downto 0);
e0_en : in std_logic;
e1_en : in std_logic;
e2_en : in std_logic;
push : in std_logic;
pop : in std_logic;
pop2 : in std_logic;
data_in : in std_logic_vector(31 downto 0);
e0_out : out std_logic_vector(31 downto 0);
e1_out : out std_logic_vector(31 downto 0)
);
end data_stack;
architecture behavioral of data_stack is
type stack_array is array(12 downto 0) of std_logic_vector(31 downto 0);
signal stg_elements : stack_array; --The storage elements of the stack
signal stg_elements_next : stack_array; --The next values to be taken on in the storage stack
signal e0_r : std_logic_vector(31 downto 0); --The working elements
signal e1_r : std_logic_vector(31 downto 0);
signal e2_r : std_logic_vector(31 downto 0);
signal e0_next : std_logic_vector(31 downto 0); --The values to be taken by the working elements
signal e1_next : std_logic_vector(31 downto 0); --at the next falling edge
signal e2_next : std_logic_vector(31 downto 0);
begin
--The process that synchronously writes new values to the elements
sync : process (clk, rst, e0_r, e1_r) is
begin
if rst = '1' then
stg_elements <= (others => (others => '0'));
e0_r <= (others => '0');
e1_r <= (others => '0');
e2_r <= (others => '0');
elsif falling_edge(clk) then
stg_elements <= stg_elements_next;
if e0_en = '1' then
e0_r <= e0_next;
end if;
if e1_en = '1' then
e1_r <= e1_next;
end if;
if e2_en = '1' then
e2_r <= e2_next;
end if;
end if;
e0_out <= e0_r;
e1_out <= e1_r;
end process;
--Selects what will go on the eX_next signals
wkg_el_mux : process (rst, e0_sel, e1_sel, e2_sel, e0_r, e1_r, e2_r, stg_elements, data_in) is
begin
if rst = '1' then
e0_next <= (others => '0');
e1_next <= (others => '0');
e2_next <= (others => '0');
else
case (e0_sel) is
when "00" =>
e0_next <= data_in;
when "01" =>
e0_next <= e1_r;
when "10" =>
e0_next <= e2_r;
when others =>
e0_next <= (others => '0');
end case;
case (e1_sel) is
when "00" =>
e1_next <= e0_r;
when "01" =>
e1_next <= e2_r;
when "10" =>
e1_next <= stg_elements(0);
when others =>
e1_next <= (others => '0');
end case;
case (e2_sel) is
when "00" =>
e2_next <= e1_r;
when "01" =>
e2_next <= stg_elements(0);
when "10" =>
e2_next <= e0_r;
when others =>
e2_next <= stg_elements(1);
end case;
end if;
end process;
--Selects what goes on the stg_elements_next signal, depending on the operation
stg_el_sel : process (rst, stg_elements, push, pop, pop2, e2_r) is
begin
if rst = '1' then
stg_elements_next <= (others => (others => '0'));
else
if push = '1' then --Pusing a value onto to storage elements from e2
stg_elements_next(0) <= e2_r;
stg_elements_next(1) <= stg_elements(0);
stg_elements_next(2) <= stg_elements(1);
stg_elements_next(3) <= stg_elements(2);
stg_elements_next(4) <= stg_elements(3);
stg_elements_next(5) <= stg_elements(4);
stg_elements_next(6) <= stg_elements(5);
stg_elements_next(7) <= stg_elements(6);
stg_elements_next(8) <= stg_elements(7);
stg_elements_next(9) <= stg_elements(8);
stg_elements_next(10) <= stg_elements(9);
stg_elements_next(11) <= stg_elements(10);
stg_elements_next(12) <= stg_elements(11);
elsif pop = '1' then --Popping a value off the storage elements
stg_elements_next(0) <= stg_elements(1);
stg_elements_next(1) <= stg_elements(2);
stg_elements_next(2) <= stg_elements(3);
stg_elements_next(3) <= stg_elements(4);
stg_elements_next(4) <= stg_elements(5);
stg_elements_next(5) <= stg_elements(6);
stg_elements_next(6) <= stg_elements(7);
stg_elements_next(7) <= stg_elements(8);
stg_elements_next(8) <= stg_elements(9);
stg_elements_next(9) <= stg_elements(10);
stg_elements_next(10) <= stg_elements(11);
stg_elements_next(11) <= stg_elements(12);
stg_elements_next(12) <= (others => '0');
elsif pop2 = '1' then --Popping two values off the storage elements
stg_elements_next(0) <= stg_elements(2);
stg_elements_next(1) <= stg_elements(3);
stg_elements_next(2) <= stg_elements(4);
stg_elements_next(3) <= stg_elements(5);
stg_elements_next(4) <= stg_elements(6);
stg_elements_next(5) <= stg_elements(7);
stg_elements_next(6) <= stg_elements(8);
stg_elements_next(7) <= stg_elements(9);
stg_elements_next(8) <= stg_elements(10);
stg_elements_next(9) <= stg_elements(11);
stg_elements_next(10) <= stg_elements(12);
stg_elements_next(11) <= (others => '0');
stg_elements_next(12) <= (others => '0');
else
stg_elements_next <= stg_elements;
end if;
end if;
end process;
end behavioral; | mit | 03d972e952f3d28d8cec84f8ca599423 | 0.588962 | 2.736815 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf2_sim.vhd | 1 | 2,657 | -- $Id: sys_conf2_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n4d (for test bench)
--
-- Dependencies: -
-- Tool versions: 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to
-- 240 cycles (2 usec). This affects mainly the autobauder. A break will be
-- detected after 128 msec periods, this in simulation after 256 usec or
-- 30720 cycles. This is compatible with bitrates of 115200 baud or higher
-- (115200 <-> 8.68 usec <-> 1040 cycles)
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz
constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clksys_msecdiv : integer := 2; -- shortened !!
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_clkser_msecdiv : integer := 2; -- shortened !!
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure serport ------------------------------------------------------
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 7fae1dee3ec99fb4382da09998ca0483 | 0.582236 | 4.037994 | false | false | false | false |
sjohann81/hf-risc | mips/core_mips/datapath.vhd | 1 | 10,898 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity datapath is
port ( clock: in std_logic;
reset: in std_logic;
stall: in std_logic;
mwait: in std_logic;
irq_vector: in std_logic_vector(31 downto 0);
irq: in std_logic;
irq_ack: out std_logic;
exception: out std_logic;
inst_addr: out std_logic_vector(31 downto 0);
inst_in: in std_logic_vector(31 downto 0);
data_addr: out std_logic_vector(31 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
data_w: out std_logic_vector(3 downto 0);
data_b: out std_logic;
data_h: out std_logic;
data_access: out std_logic
);
end datapath;
architecture arch_datapath of datapath is
-- datapath signals
signal inst_in_s, data_in_s, pc, pc_last, pc_plus4, pc_next, result, branch, jump, ext32, ext32b, ext32h, alu_src: std_logic_vector(31 downto 0);
signal opcode, funct: std_logic_vector(5 downto 0);
signal read_reg1, read_reg2, write_reg: std_logic_vector(4 downto 0);
signal rs, rt, rd, target: std_logic_vector(4 downto 0);
signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
signal imm: std_logic_vector(15 downto 0);
signal wreg, zero, less_than, br_link_ctl, branch_taken, jump_taken, stall_reg: std_logic;
signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
-- control signals
signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;
signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);
signal branch_ctl: std_logic_vector(2 downto 0);
signal alu_op_ctl: std_logic_vector(3 downto 0);
signal reg_dst_ctl_r, reg_write_ctl_r, alu_src_ctl_r, reg_to_mem_ctl_r, mem_to_reg_ctl_r, signed_imm_ctl_r, signed_rd_ctl_r, shift_ctl_r, br_link_ctl_r: std_logic;
signal jump_ctl_r, mem_read_ctl_r, mem_write_ctl_r: std_logic_vector(1 downto 0);
signal branch_ctl_r: std_logic_vector(2 downto 0);
signal alu_op_ctl_r: std_logic_vector(3 downto 0);
signal rs_r, rt_r, rd_r: std_logic_vector(4 downto 0);
signal imm_r: std_logic_vector(15 downto 0);
begin
--
-- FETCH STAGE
--
-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
-- program counter logic
process(clock, reset, stall_reg)
begin
if reset = '1' then
pc <= (others => '0');
pc_last <= (others => '0');
elsif clock'event and clock = '1' then
if stall = '0' then
pc <= pc_next;
pc_last <= pc;
end if;
end if;
end process;
pc_plus4 <= pc + 4;
pc_next <= irq_vector when (irq = '1' and irq_ack_s = '1') else
branch when branch_taken = '1' else
jump when jump_taken = '1' else
pc_last when data_access_s = '1' else
pc_plus4;
-- interrupt acknowledge logic
irq_ack_s <= '1' when irq = '1' and
bds = '0' and branch_taken = '0' and jump_taken = '0' and
reg_to_mem_ctl_r = '0' and mem_to_reg_ctl_r = '0' else '0';
irq_ack <= irq_ack_s_dly;
exception <= '0';
process(clock, reset, irq, irq_ack_s, mem_to_reg_ctl_r, stall, mwait)
begin
if reset = '1' then
irq_ack_s_dly <= '0';
bds <= '0';
data_access_s_dly <= '0';
stall_reg <= '0';
elsif clock'event and clock = '1' then
stall_reg <= stall;
if stall = '0' then
data_access_s_dly <= data_access_s;
if mwait = '0' then
irq_ack_s_dly <= irq_ack_s;
if branch_taken = '1' or jump_taken = '1' then
bds <= '1';
else
bds <= '0';
end if;
end if;
end if;
end if;
end process;
--
-- DECODE STAGE
--
-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and 2nd branch delay slot
-- pipeline bubble insertion on loads/stores, branches and interrupts
inst_in_s <= x"00000000" when data_access_s = '1' or bds = '1' or irq_ack_s = '1' else inst_in;
-- instruction decode
opcode <= inst_in_s(31 downto 26);
rs <= inst_in_s(25 downto 21);
rt <= inst_in_s(20 downto 16);
rd <= "11111" when br_link_ctl = '1' else inst_in_s(15 downto 11); -- FIXME: this will not work for the 'jalr rd, rs' format
funct <= inst_in_s(5 downto 0);
imm <= inst_in_s(15 downto 0);
-- control unit
control_unit: entity work.control
port map( opcode => opcode,
funct => funct,
rtx => rt,
reg_dst => reg_dst_ctl,
reg_write => reg_write_ctl,
alu_src => alu_src_ctl,
alu_op => alu_op_ctl,
jump => jump_ctl,
branch => branch_ctl,
br_link => br_link_ctl,
reg_to_mem => reg_to_mem_ctl,
mem_to_reg => mem_to_reg_ctl,
signed_imm => signed_imm_ctl,
mem_write => mem_write_ctl,
mem_read => mem_read_ctl,
signed_rd => signed_rd_ctl,
shift => shift_ctl
);
process(clock, reset, stall, mwait)
begin
if reset = '1' then
rs_r <= (others => '0');
rt_r <= (others => '0');
rd_r <= (others => '0');
imm_r <= (others => '0');
reg_dst_ctl_r <= '0';
reg_write_ctl_r <= '0';
alu_src_ctl_r <= '0';
alu_op_ctl_r <= (others => '0');
jump_ctl_r <= (others => '0');
branch_ctl_r <= (others => '0');
br_link_ctl_r <= '0';
reg_to_mem_ctl_r <= '0';
mem_to_reg_ctl_r <= '0';
signed_imm_ctl_r <= '0';
mem_write_ctl_r <= "00";
mem_read_ctl_r <= "00";
signed_rd_ctl_r <= '0';
shift_ctl_r <= '0';
elsif clock'event and clock = '1' then
if stall = '0' and mwait = '0' then
rs_r <= rs;
rt_r <= rt;
rd_r <= rd;
imm_r <= imm;
reg_dst_ctl_r <= reg_dst_ctl;
reg_write_ctl_r <= reg_write_ctl;
alu_src_ctl_r <= alu_src_ctl;
alu_op_ctl_r <= alu_op_ctl;
jump_ctl_r <= jump_ctl;
branch_ctl_r <= branch_ctl;
br_link_ctl_r <= br_link_ctl;
reg_to_mem_ctl_r <= reg_to_mem_ctl;
mem_to_reg_ctl_r <= mem_to_reg_ctl;
signed_imm_ctl_r <= signed_imm_ctl;
mem_write_ctl_r <= mem_write_ctl;
mem_read_ctl_r <= mem_read_ctl;
signed_rd_ctl_r <= signed_rd_ctl;
shift_ctl_r <= shift_ctl;
end if;
end if;
end process;
--
-- EXECUTE STAGE
--
-- 3rd stage (a) register file access (read)
-- the register file
register_bank: entity work.reg_bank
port map( clock => clock,
read_reg1 => read_reg1,
read_reg2 => read_reg2,
write_reg => write_reg,
wreg => wreg,
write_data => write_data,
read_data1 => read_data1,
read_data2 => read_data2
);
-- register file read/write selection and write enable
read_reg1 <= rs_r when shift_ctl_r = '0' else rt_r; -- source for shifts or normal operations
read_reg2 <= "00000" when branch_ctl_r > "010" else -- source for branch and link (for zero operations)
rs_r when shift_ctl_r = '1' else rt_r; -- source for register based shifts or normal operations
write_reg <= target when mem_to_reg_ctl_r = '0' else rt_r;
ext32 <= x"0000" & imm_r when (imm_r(15) = '0' or signed_imm_ctl_r = '0') else x"ffff" & imm_r;
target <= rt_r when reg_dst_ctl_r = '0' else rd_r; -- target register selection
wreg <= (reg_write_ctl_r or mem_to_reg_ctl_r) and not mwait and not stall_reg; -- enable the register bank for write back also
-- 3rd stage (b) ALU operation
alu: entity work.alu
port map( op1 => read_data1,
op2 => alu_src,
alu_op => alu_op_ctl_r,
result => result,
zero => zero,
less_than => less_than
);
alu_src <= read_data2 when alu_src_ctl_r = '0' else ext32;
branch <= (ext32(29 downto 0) & "00") + pc_last;
jump <= read_data1 when jump_ctl_r = "10" else pc_last(31 downto 28) & rs_r & rt_r & imm_r & "00";
branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or -- BEQ
(zero = '0' and branch_ctl_r = "010") or -- BNE
((zero = '1' or less_than = '1') and branch_ctl_r = "011") or -- BLEZ
((zero = '0' and less_than = '0') and branch_ctl_r = "100") or -- BGTZ
((zero = '0' and less_than = '1') and branch_ctl_r = "101") or -- BLTZ, BLTZAL
((zero = '1' or less_than = '0') and branch_ctl_r = "110") -- BGEZ, BGEZAL
else '0';
jump_taken <= '1' when jump_ctl_r /= "00" else '0'; -- J, JAL, JR, JALR
inst_addr <= pc;
data_addr <= result;
data_b <= '1' when mem_read_ctl_r = "01" or mem_write_ctl_r = "01" else '0';
data_h <= '1' when mem_read_ctl_r = "10" or mem_write_ctl_r = "10" else '0';
data_access_s <= '1' when reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' else '0';
data_access <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
-- 3rd stage (c) data memory / write back operation, register file access (write)
-- memory access, store operations
process(mem_write_ctl_r, result, read_data2)
begin
case mem_write_ctl_r is
when "11" => -- store word
data_out <= read_data2;
data_w <= "1111";
when "01" => -- store byte
data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);
case result(1 downto 0) is
when "11" => data_w <= "0001";
when "10" => data_w <= "0010";
when "01" => data_w <= "0100";
when others => data_w <= "1000";
end case;
when "10" => -- store half word
data_out <= read_data2(15 downto 0) & read_data2(15 downto 0);
case result(1) is
when '1' => data_w <= "0011";
when others => data_w <= "1100";
end case;
when others => -- WTF??
data_out <= read_data2;
data_w <= "0000";
end case;
end process;
-- memory access, load operations
process(mem_read_ctl_r, result, data_in)
begin
case mem_read_ctl_r is
when "01" => -- load byte
case result(1 downto 0) is
when "11" => data_in_s <= x"000000" & data_in(7 downto 0);
when "10" => data_in_s <= x"000000" & data_in(15 downto 8);
when "01" => data_in_s <= x"000000" & data_in(23 downto 16);
when others => data_in_s <= x"000000" & data_in(31 downto 24);
end case;
when "10" => -- load half word
case result(1) is
when '1' => data_in_s <= x"0000" & data_in(15 downto 0);
when others => data_in_s <= x"0000" & data_in(31 downto 16);
end case;
when others => -- load word
data_in_s <= data_in;
end case;
end process;
-- write back
ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or signed_rd_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);
ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or signed_rd_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);
write_data <= data_in_s when mem_read_ctl_r = "11" else
ext32b when mem_read_ctl_r = "01" else
ext32h when mem_read_ctl_r = "10" else
pc when br_link_ctl_r = '1' else result;
end arch_datapath;
| gpl-2.0 | 35302030c0145e81236ca1cdc4ac2e18 | 0.589099 | 2.612803 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys2/tb/sys_conf2_sim.vhd | 1 | 1,470 | -- $Id: sys_conf2_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkudiv_usecdiv : integer := 20; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
| gpl-3.0 | f91d8800ebed50795e8dd3b2fd0cb676 | 0.607483 | 3.730964 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/arty_bram/pdp11_hio70_arty.vhd | 1 | 6,113 | -- $Id: pdp11_hio70_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_hio70_arty - syn
-- Description: pdp11: hio led and rgb for sys70 for arty
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.2; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP instead of DM_STAT_DP
-- 2016-02-27 737 1.0 Initial version
------------------------------------------------------------------------------
--
-- collects the output for LED and RGB leds
-- MODE = 00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with y=1)
-- (3) kernel mode, non-wait, pri>0
-- (2) kernel mode, non-wait, pri=0
-- (1) supervisor mode
-- (0) user mode
-- RGB_R CPU rust (active cpugo=0, enabled with y=1)
-- (3:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with x=1)
-- (3) MEM_ACT_W
-- (2) MEM_ACT_R
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- MODE = 0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR(11:08)
-- RGB_G DR( 7:04)
-- RGB_R DR( 3:00)
--
-- MODE = 1xyy (show lsb or msb of 16 bit register)
-- LED show upper, RGB_G lower nibble; x=0 shows lsb and x=1 shows msb
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_hio70_arty is -- hio led+rgb for sys70 for arty
port (
CLK : in slbit; -- clock
MODE : in slv4; -- mode select
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
IOLEDS : in slv4; -- serport ioleds
ABCLKDIV : in slv16; -- serport clock divider
LED : out slv4; -- hio leds
RGB_R : out slv4; -- hio rgb leds - red
RGB_G : out slv4; -- hio rgb leds - green
RGB_B : out slv4 -- hio rgb leds - blue
);
end pdp11_hio70_arty;
architecture syn of pdp11_hio70_arty is
signal R_LED : slv4 := (others=>'0');
signal R_RGB_R : slv4 := (others=>'0');
signal R_RGB_G : slv4 := (others=>'0');
signal R_RGB_B : slv4 := (others=>'0');
begin
proc_regs : process (CLK)
variable idat16 : slv16 := (others=>'0');
variable idat8 : slv8 := (others=>'0');
variable iled : slv4 := (others=>'0');
variable irgb_r : slv4 := (others=>'0');
variable irgb_g : slv4 := (others=>'0');
variable irgb_b : slv4 := (others=>'0');
begin
if rising_edge(CLK) then
idat16 := (others=>'0');
case MODE(1 downto 0) is
when "00" => idat16 := ABCLKDIV;
when "01" => idat16 := DM_STAT_EXP.dp_pc;
when "10" => idat16 := DISPREG;
when "11" => idat16 := DM_STAT_EXP.dp_dsrc;
when others => null;
end case;
if MODE(2) = '0' then
idat8 := idat16( 7 downto 0);
else
idat8 := idat16(15 downto 8);
end if;
iled := (others=>'0');
irgb_r := (others=>'0');
irgb_g := (others=>'0');
irgb_b := (others=>'0');
if MODE(3) = '0' then
if MODE(2) = '0' then -- LED shows IO; RGB shows CPU/MEM
iled := IOLEDS;
if MODE(0) = '1' then
if CP_STAT.cpugo = '1' then
case DM_STAT_EXP.dp_psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '0' then
if unsigned(DM_STAT_EXP.dp_psw.pri) = 0 then
irgb_g(2) := '1';
else
irgb_g(3) := '1';
end if;
end if;
when c_psw_smode =>
irgb_g(1) := '1';
when c_psw_umode =>
irgb_g(0) := '1';
when others => null;
end case;
else
irgb_r(3 downto 0) := CP_STAT.cpurust;
end if;
end if; -- MODE(0) = '1'
if MODE(1) = '1' then
irgb_b(3) := MEM_ACT_W;
irgb_b(2) := MEM_ACT_R;
irgb_b(1) := CP_STAT.cmdbusy;
irgb_b(0) := not CP_STAT.cpugo;
end if;
else -- LED+RGB show DR emulation
iled := DM_STAT_EXP.dp_dsrc(15 downto 12);
irgb_b := DM_STAT_EXP.dp_dsrc(11 downto 8);
irgb_g := DM_STAT_EXP.dp_dsrc( 7 downto 4);
irgb_r := DM_STAT_EXP.dp_dsrc( 3 downto 0);
end if; -- MODE(2) = '0'
else -- LED+RGB show one of four regs
iled := idat8(7 downto 4);
irgb_g := idat8(3 downto 0);
end if; -- MODE(3) = '0'
R_LED <= iled;
R_RGB_R <= irgb_r;
R_RGB_G <= irgb_g;
R_RGB_B <= irgb_b;
end if;
end process proc_regs;
LED <= R_LED;
RGB_R <= R_RGB_R;
RGB_G <= R_RGB_G;
RGB_B <= R_RGB_B;
end syn;
| gpl-3.0 | 19c2f10941c181a342d23696d0529d6c | 0.453623 | 3.394225 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32e/datapath.vhd | 1 | 11,917 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity datapath is
port ( clock: in std_logic;
reset: in std_logic;
stall: in std_logic;
mwait: in std_logic;
irq_vector: in std_logic_vector(31 downto 0);
irq: in std_logic;
irq_ack: out std_logic;
exception: out std_logic;
inst_addr: out std_logic_vector(31 downto 0);
inst_in: in std_logic_vector(31 downto 0);
data_addr: out std_logic_vector(31 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
data_w: out std_logic_vector(3 downto 0);
data_b: out std_logic;
data_h: out std_logic;
data_access: out std_logic
);
end datapath;
architecture arch_datapath of datapath is
-- datapath signals
signal inst_in_s, data_in_s, pc, pc_last, pc_last2, pc_plus4, pc_next, result, branch, ext32b, ext32h, alu_src1, alu_src2: std_logic_vector(31 downto 0);
signal ext32: std_logic_vector(31 downto 12);
signal opcode, funct7: std_logic_vector(6 downto 0);
signal funct3: std_logic_vector(2 downto 0);
signal read_reg1, read_reg2, write_reg: std_logic_vector(3 downto 0);
signal rs1, rs2, rd: std_logic_vector(4 downto 0);
signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);
signal imm_u: std_logic_vector(31 downto 12);
signal wreg, zero, less_than, branch_taken, jump_taken, stall_reg: std_logic;
signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
-- control signals
signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;
signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);
signal alu_src2_ctl, branch_ctl: std_logic_vector(2 downto 0);
signal alu_op_ctl: std_logic_vector(3 downto 0);
signal rs1_r, rs2_r, rd_r: std_logic_vector(4 downto 0);
signal imm_i_r, imm_s_r, imm_sb_r, imm_uj_r: std_logic_vector(31 downto 0);
signal imm_u_r: std_logic_vector(31 downto 12);
signal reg_write_ctl_r, alu_src1_ctl_r, sig_read_ctl_r, reg_to_mem_r, mem_to_reg_r: std_logic;
signal jump_ctl_r, mem_write_ctl_r, mem_read_ctl_r: std_logic_vector(1 downto 0);
signal alu_src2_ctl_r, branch_ctl_r: std_logic_vector(2 downto 0);
signal alu_op_ctl_r: std_logic_vector(3 downto 0);
begin
--
-- FETCH STAGE
--
-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
-- program counter logic
process(clock, reset, reg_to_mem_r, mem_to_reg_r, stall, stall_reg)
begin
if reset = '1' then
pc <= (others => '0');
pc_last <= (others => '0');
pc_last2 <= (others => '0');
elsif clock'event and clock = '1' then
if stall = '0' then
pc <= pc_next;
pc_last <= pc;
pc_last2 <= pc_last;
end if;
end if;
end process;
pc_plus4 <= pc + 4;
pc_next <= irq_vector when (irq = '1' and irq_ack_s = '1') or except = '1' else
branch when branch_taken = '1' or jump_taken = '1' else
pc_last when data_access_s = '1' else
pc_plus4;
-- interrupt acknowledge logic
irq_ack_s <= '1' when irq = '1' and
bds = '0' and branch_taken = '0' and jump_taken = '0' and
reg_to_mem_r = '0' and mem_to_reg_r = '0' else '0';
irq_ack <= irq_ack_s_dly;
exception <= '1' when except = '1' else '0';
process(clock, reset, irq, irq_ack_s, mem_to_reg_r, stall, mwait)
begin
if reset = '1' then
irq_ack_s_dly <= '0';
bds <= '0';
data_access_s_dly <= '0';
stall_reg <= '0';
elsif clock'event and clock = '1' then
stall_reg <= stall;
if stall = '0' then
data_access_s_dly <= data_access_s;
if mwait = '0' then
irq_ack_s_dly <= irq_ack_s;
if branch_taken = '1' or jump_taken = '1' then
bds <= '1';
else
bds <= '0';
end if;
end if;
end if;
end if;
end process;
--
-- DECODE STAGE
--
-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and branches
-- pipeline bubble insertion on loads/stores, exceptions, branches and interrupts
inst_in_s <= x"00000000" when data_access_s = '1' or except = '1' or
branch_taken = '1' or jump_taken = '1' or bds = '1' or irq_ack_s = '1' else
inst_in(7 downto 0) & inst_in(15 downto 8) & inst_in(23 downto 16) & inst_in(31 downto 24);
-- instruction decode
opcode <= inst_in_s(6 downto 0);
funct3 <= inst_in_s(14 downto 12);
funct7 <= inst_in_s(31 downto 25);
rd <= inst_in_s(11 downto 7);
rs1 <= inst_in_s(19 downto 15);
rs2 <= inst_in_s(24 downto 20);
imm_i <= ext32(31 downto 12) & inst_in_s(31 downto 20);
imm_s <= ext32(31 downto 12) & inst_in_s(31 downto 25) & inst_in_s(11 downto 7);
imm_sb <= ext32(31 downto 13) & inst_in_s(31) & inst_in_s(7) & inst_in_s(30 downto 25) & inst_in_s(11 downto 8) & '0';
imm_u <= inst_in_s(31 downto 12);
imm_uj <= ext32(31 downto 21) & inst_in_s(31) & inst_in_s(19 downto 12) & inst_in_s(20) & inst_in_s(30 downto 21) & '0';
ext32 <= (others => '1') when inst_in_s(31) = '1' else (others => '0');
-- control unit
control_unit: entity work.control
port map( opcode => opcode,
funct3 => funct3,
funct7 => funct7,
reg_write => reg_write_ctl,
alu_src1 => alu_src1_ctl,
alu_src2 => alu_src2_ctl,
alu_op => alu_op_ctl,
jump => jump_ctl,
branch => branch_ctl,
mem_write => mem_write_ctl,
mem_read => mem_read_ctl,
sig_read => sig_read_ctl
);
reg_to_mem <= '1' when mem_write_ctl /= "00" else '0';
mem_to_reg <= '1' when mem_read_ctl /= "00" else '0';
process(clock, reset, irq_ack_s, bds, stall, mwait)
begin
if reset = '1' then
rd_r <= (others => '0');
rs1_r <= (others => '0');
rs2_r <= (others => '0');
imm_i_r <= (others => '0');
imm_s_r <= (others => '0');
imm_sb_r <= (others => '0');
imm_u_r <= (others => '0');
imm_uj_r <= (others => '0');
reg_write_ctl_r <= '0';
alu_src1_ctl_r <= '0';
alu_src2_ctl_r <= (others => '0');
alu_op_ctl_r <= (others => '0');
jump_ctl_r <= (others => '0');
branch_ctl_r <= (others => '0');
mem_write_ctl_r <= (others => '0');
mem_read_ctl_r <= (others => '0');
sig_read_ctl_r <= '0';
reg_to_mem_r <= '0';
mem_to_reg_r <= '0';
elsif clock'event and clock = '1' then
if stall = '0' and mwait = '0' then
rd_r <= rd;
rs1_r <= rs1;
rs2_r <= rs2;
imm_i_r <= imm_i;
imm_s_r <= imm_s;
imm_sb_r <= imm_sb;
imm_u_r <= imm_u;
imm_uj_r <= imm_uj;
reg_write_ctl_r <= reg_write_ctl;
alu_src1_ctl_r <= alu_src1_ctl;
alu_src2_ctl_r <= alu_src2_ctl;
alu_op_ctl_r <= alu_op_ctl;
jump_ctl_r <= jump_ctl;
branch_ctl_r <= branch_ctl;
mem_write_ctl_r <= mem_write_ctl;
mem_read_ctl_r <= mem_read_ctl;
sig_read_ctl_r <= sig_read_ctl;
reg_to_mem_r <= reg_to_mem;
mem_to_reg_r <= mem_to_reg;
end if;
end if;
end process;
--
-- EXECUTE STAGE
--
-- 3rd stage (a) register file access (read)
-- the register file
register_bank: entity work.reg_bank
port map( clock => clock,
read_reg1 => read_reg1,
read_reg2 => read_reg2,
write_reg => write_reg,
wreg => wreg,
write_data => write_data,
read_data1 => read_data1,
read_data2 => read_data2
);
-- register file read/write selection and write enable
read_reg1 <= rs1_r(3 downto 0);
read_reg2 <= rs2_r(3 downto 0);
write_reg <= rd_r(3 downto 0);
wreg <= (reg_write_ctl_r or mem_to_reg_r) and not mwait and not stall_reg;
-- 3rd stage (b) ALU operation
alu: entity work.alu
port map( op1 => alu_src1,
op2 => alu_src2,
alu_op => alu_op_ctl_r,
result => result,
zero => zero,
less_than => less_than
);
alu_src1 <= read_data1 when alu_src1_ctl_r = '0' else pc_last2;
alu_src2 <= imm_u_r & x"000" when alu_src2_ctl_r = "000" else
imm_i_r when alu_src2_ctl_r = "001" else
imm_s_r when alu_src2_ctl_r = "010" else
pc when alu_src2_ctl_r = "011" else
x"000000" & "000" & rs2_r when alu_src2_ctl_r = "100" else
read_data2;
branch_src1 <= read_data1 when jump_ctl_r = "11" else pc_last2;
branch_src2 <= imm_uj_r when jump_ctl_r = "10" else
imm_i_r when jump_ctl_r = "11" else imm_sb_r;
branch <= branch_src1 + branch_src2;
branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or -- BEQ
(zero = '0' and branch_ctl_r = "010") or -- BNE
(less_than = '1' and branch_ctl_r = "011") or -- BLT
(less_than = '0' and branch_ctl_r = "100") or -- BGE
(less_than = '1' and branch_ctl_r = "101") or -- BLTU
(less_than = '0' and branch_ctl_r = "110") -- BGEU
else '0';
except <= '1' when branch_ctl_r = "111" else '0';
jump_taken <= '1' when jump_ctl_r /= "00" else '0';
inst_addr <= pc;
data_addr <= result;
data_b <= '1' when mem_read_ctl_r = "01" or mem_write_ctl_r = "01" else '0';
data_h <= '1' when mem_read_ctl_r = "10" or mem_write_ctl_r = "10" else '0';
data_access_s <= '1' when reg_to_mem_r = '1' or mem_to_reg_r = '1' else '0';
data_access <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
-- 3rd stage (c) data memory / write back operation, register file access (write)
-- memory access, store operations
process(mem_write_ctl_r, result, read_data2)
begin
case mem_write_ctl_r is
when "11" => -- store word
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);
data_w <= "1111";
when "01" => -- store byte
data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);
case result(1 downto 0) is
when "11" => data_w <= "0001";
when "10" => data_w <= "0010";
when "01" => data_w <= "0100";
when others => data_w <= "1000";
end case;
when "10" => -- store half word
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(7 downto 0) & read_data2(15 downto 8);
case result(1) is
when '1' => data_w <= "0011";
when others => data_w <= "1100";
end case;
when others => -- WTF??
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);
data_w <= "0000";
end case;
end process;
-- memory access, load operations
process(mem_read_ctl_r, result, data_in)
begin
case mem_read_ctl_r is
when "01" => -- load byte
case result(1 downto 0) is
when "11" => data_in_s <= x"000000" & data_in(7 downto 0);
when "10" => data_in_s <= x"000000" & data_in(15 downto 8);
when "01" => data_in_s <= x"000000" & data_in(23 downto 16);
when others => data_in_s <= x"000000" & data_in(31 downto 24);
end case;
when "10" => -- load half word
case result(1) is
when '1' => data_in_s <= x"0000" & data_in(7 downto 0) & data_in(15 downto 8);
when others => data_in_s <= x"0000" & data_in(23 downto 16) & data_in(31 downto 24);
end case;
when others => -- load word
data_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);
end case;
end process;
-- write back
ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or sig_read_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);
ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or sig_read_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);
write_data <= data_in_s when mem_read_ctl_r = "11" else
ext32b when mem_read_ctl_r = "01" else
ext32h when mem_read_ctl_r = "10" else
pc_last when jump_taken = '1' else result;
end arch_datapath;
| gpl-2.0 | 7fa6838c15a2c05861ea46b105a2f3fe | 0.589158 | 2.54148 | false | false | false | false |
Paebbels/PicoBlaze-Library | ROM Templates/Page.Series-7.template.vhdl | 1 | 15,225 | {begin template}
-- Program defined by '{psmname}.{psmext}'.
--
-- Generated by {assembler}: {timestamp}.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UniSim;
use UniSim.vComponents.all;
entity {name} is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end;
architecture page of {name} is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
begin
address_a <= '1' & Address(11 downto 0) & "111";
Instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
we_b <= (others => JTAGLoader_WriteEnable);
address_b <= '1' & JTAGLoader_Address(11 downto 0) & "111";
data_in_b_l <= "000" & JTAGLoader_DataIn(8) & x"000000" & JTAGLoader_DataIn(7 downto 0);
data_in_b_h <= "000" & JTAGLoader_DataIn(17) & x"000000" & JTAGLoader_DataIn(16 downto 9);
JTAGLoader_DataOut <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
rom0 : RAMB36E1
generic map (
READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INIT_40 => X"{[8:0]_INIT_40}",
INIT_41 => X"{[8:0]_INIT_41}",
INIT_42 => X"{[8:0]_INIT_42}",
INIT_43 => X"{[8:0]_INIT_43}",
INIT_44 => X"{[8:0]_INIT_44}",
INIT_45 => X"{[8:0]_INIT_45}",
INIT_46 => X"{[8:0]_INIT_46}",
INIT_47 => X"{[8:0]_INIT_47}",
INIT_48 => X"{[8:0]_INIT_48}",
INIT_49 => X"{[8:0]_INIT_49}",
INIT_4A => X"{[8:0]_INIT_4A}",
INIT_4B => X"{[8:0]_INIT_4B}",
INIT_4C => X"{[8:0]_INIT_4C}",
INIT_4D => X"{[8:0]_INIT_4D}",
INIT_4E => X"{[8:0]_INIT_4E}",
INIT_4F => X"{[8:0]_INIT_4F}",
INIT_50 => X"{[8:0]_INIT_50}",
INIT_51 => X"{[8:0]_INIT_51}",
INIT_52 => X"{[8:0]_INIT_52}",
INIT_53 => X"{[8:0]_INIT_53}",
INIT_54 => X"{[8:0]_INIT_54}",
INIT_55 => X"{[8:0]_INIT_55}",
INIT_56 => X"{[8:0]_INIT_56}",
INIT_57 => X"{[8:0]_INIT_57}",
INIT_58 => X"{[8:0]_INIT_58}",
INIT_59 => X"{[8:0]_INIT_59}",
INIT_5A => X"{[8:0]_INIT_5A}",
INIT_5B => X"{[8:0]_INIT_5B}",
INIT_5C => X"{[8:0]_INIT_5C}",
INIT_5D => X"{[8:0]_INIT_5D}",
INIT_5E => X"{[8:0]_INIT_5E}",
INIT_5F => X"{[8:0]_INIT_5F}",
INIT_60 => X"{[8:0]_INIT_60}",
INIT_61 => X"{[8:0]_INIT_61}",
INIT_62 => X"{[8:0]_INIT_62}",
INIT_63 => X"{[8:0]_INIT_63}",
INIT_64 => X"{[8:0]_INIT_64}",
INIT_65 => X"{[8:0]_INIT_65}",
INIT_66 => X"{[8:0]_INIT_66}",
INIT_67 => X"{[8:0]_INIT_67}",
INIT_68 => X"{[8:0]_INIT_68}",
INIT_69 => X"{[8:0]_INIT_69}",
INIT_6A => X"{[8:0]_INIT_6A}",
INIT_6B => X"{[8:0]_INIT_6B}",
INIT_6C => X"{[8:0]_INIT_6C}",
INIT_6D => X"{[8:0]_INIT_6D}",
INIT_6E => X"{[8:0]_INIT_6E}",
INIT_6F => X"{[8:0]_INIT_6F}",
INIT_70 => X"{[8:0]_INIT_70}",
INIT_71 => X"{[8:0]_INIT_71}",
INIT_72 => X"{[8:0]_INIT_72}",
INIT_73 => X"{[8:0]_INIT_73}",
INIT_74 => X"{[8:0]_INIT_74}",
INIT_75 => X"{[8:0]_INIT_75}",
INIT_76 => X"{[8:0]_INIT_76}",
INIT_77 => X"{[8:0]_INIT_77}",
INIT_78 => X"{[8:0]_INIT_78}",
INIT_79 => X"{[8:0]_INIT_79}",
INIT_7A => X"{[8:0]_INIT_7A}",
INIT_7B => X"{[8:0]_INIT_7B}",
INIT_7C => X"{[8:0]_INIT_7C}",
INIT_7D => X"{[8:0]_INIT_7D}",
INIT_7E => X"{[8:0]_INIT_7E}",
INIT_7F => X"{[8:0]_INIT_7F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}",
INITP_08 => X"{[8:0]_INITP_08}",
INITP_09 => X"{[8:0]_INITP_09}",
INITP_0A => X"{[8:0]_INITP_0A}",
INITP_0B => X"{[8:0]_INITP_0B}",
INITP_0C => X"{[8:0]_INITP_0C}",
INITP_0D => X"{[8:0]_INITP_0D}",
INITP_0E => X"{[8:0]_INITP_0E}",
INITP_0F => X"{[8:0]_INITP_0F}"
)
port map (
ADDRARDADDR => address_a,
ENARDEN => Fetch,
CLKARDCLK => Clock,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => x"00000000",
DIPADIP => x"0",
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => JTAGLoader_Enable,
CLKBWRCLK => JTAGLoader_Clock,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0'
);
--
rom1 : RAMB36E1
generic map (
READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INIT_40 => X"{[17:9]_INIT_40}",
INIT_41 => X"{[17:9]_INIT_41}",
INIT_42 => X"{[17:9]_INIT_42}",
INIT_43 => X"{[17:9]_INIT_43}",
INIT_44 => X"{[17:9]_INIT_44}",
INIT_45 => X"{[17:9]_INIT_45}",
INIT_46 => X"{[17:9]_INIT_46}",
INIT_47 => X"{[17:9]_INIT_47}",
INIT_48 => X"{[17:9]_INIT_48}",
INIT_49 => X"{[17:9]_INIT_49}",
INIT_4A => X"{[17:9]_INIT_4A}",
INIT_4B => X"{[17:9]_INIT_4B}",
INIT_4C => X"{[17:9]_INIT_4C}",
INIT_4D => X"{[17:9]_INIT_4D}",
INIT_4E => X"{[17:9]_INIT_4E}",
INIT_4F => X"{[17:9]_INIT_4F}",
INIT_50 => X"{[17:9]_INIT_50}",
INIT_51 => X"{[17:9]_INIT_51}",
INIT_52 => X"{[17:9]_INIT_52}",
INIT_53 => X"{[17:9]_INIT_53}",
INIT_54 => X"{[17:9]_INIT_54}",
INIT_55 => X"{[17:9]_INIT_55}",
INIT_56 => X"{[17:9]_INIT_56}",
INIT_57 => X"{[17:9]_INIT_57}",
INIT_58 => X"{[17:9]_INIT_58}",
INIT_59 => X"{[17:9]_INIT_59}",
INIT_5A => X"{[17:9]_INIT_5A}",
INIT_5B => X"{[17:9]_INIT_5B}",
INIT_5C => X"{[17:9]_INIT_5C}",
INIT_5D => X"{[17:9]_INIT_5D}",
INIT_5E => X"{[17:9]_INIT_5E}",
INIT_5F => X"{[17:9]_INIT_5F}",
INIT_60 => X"{[17:9]_INIT_60}",
INIT_61 => X"{[17:9]_INIT_61}",
INIT_62 => X"{[17:9]_INIT_62}",
INIT_63 => X"{[17:9]_INIT_63}",
INIT_64 => X"{[17:9]_INIT_64}",
INIT_65 => X"{[17:9]_INIT_65}",
INIT_66 => X"{[17:9]_INIT_66}",
INIT_67 => X"{[17:9]_INIT_67}",
INIT_68 => X"{[17:9]_INIT_68}",
INIT_69 => X"{[17:9]_INIT_69}",
INIT_6A => X"{[17:9]_INIT_6A}",
INIT_6B => X"{[17:9]_INIT_6B}",
INIT_6C => X"{[17:9]_INIT_6C}",
INIT_6D => X"{[17:9]_INIT_6D}",
INIT_6E => X"{[17:9]_INIT_6E}",
INIT_6F => X"{[17:9]_INIT_6F}",
INIT_70 => X"{[17:9]_INIT_70}",
INIT_71 => X"{[17:9]_INIT_71}",
INIT_72 => X"{[17:9]_INIT_72}",
INIT_73 => X"{[17:9]_INIT_73}",
INIT_74 => X"{[17:9]_INIT_74}",
INIT_75 => X"{[17:9]_INIT_75}",
INIT_76 => X"{[17:9]_INIT_76}",
INIT_77 => X"{[17:9]_INIT_77}",
INIT_78 => X"{[17:9]_INIT_78}",
INIT_79 => X"{[17:9]_INIT_79}",
INIT_7A => X"{[17:9]_INIT_7A}",
INIT_7B => X"{[17:9]_INIT_7B}",
INIT_7C => X"{[17:9]_INIT_7C}",
INIT_7D => X"{[17:9]_INIT_7D}",
INIT_7E => X"{[17:9]_INIT_7E}",
INIT_7F => X"{[17:9]_INIT_7F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}",
INITP_08 => X"{[17:9]_INITP_08}",
INITP_09 => X"{[17:9]_INITP_09}",
INITP_0A => X"{[17:9]_INITP_0A}",
INITP_0B => X"{[17:9]_INITP_0B}",
INITP_0C => X"{[17:9]_INITP_0C}",
INITP_0D => X"{[17:9]_INITP_0D}",
INITP_0E => X"{[17:9]_INITP_0E}",
INITP_0F => X"{[17:9]_INITP_0F}"
)
port map (
ADDRARDADDR => address_a,
ENARDEN => Fetch,
CLKARDCLK => Clock,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => x"00000000",
DIPADIP => x"0",
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => JTAGLoader_Enable,
CLKBWRCLK => JTAGLoader_Clock,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0'
);
end page;
| apache-2.0 | c3a5b79c046d6fb33cf59c2ab0500b7f | 0.495304 | 2.25422 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd | 1 | 16,169 | -- $Id: sys_w11a_c7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_c7 - syn
-- Description: w11a test design for Cmod A7
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/cmoda7/c7_cram_memctl
-- w11a/pdp11_bram_memctl
-- bplib/fx2rlink/ioleds_sp1c
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_emu_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
-- vlib/xlib/iob_reg_o_gen
--
-- Test bench: tb/tb_sys_w11a_c7
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1 3411 6189 279 50.0 2021
-- 2019-05-19 1150 2017.2 xc7a35t-1 3369 6994 285 50.0 2099 +dz11
-- 2019-04-27 1140 2017.2 xc7a35t-1 3243 6618 260 50.0 2009 +ibtst
-- 2019-03-02 1116 2017.2 xc7a35t-1 3156 6332 198 50.0 1918 +ibtst
-- 2019-02-02 1108 2018.3 xc7a35t-1 3112 6457 182 50.0 1936
-- 2019-02-02 1108 2017.2 xc7a35t-1 3107 6216 182 50.0 1884
-- 2018-10-13 1055 2017.2 xc7a35t-1 3107 6215 182 50.0 1889 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a35t-1 2883 5891 150 50.0 1826 +KW11P
-- 2017-06-27 918 2017.1 xc7a35t-1 2823 5827 150 50.0 1814 16kB cache
-- 2017-06-25 916 2017.1 xc7a35t-1 2823 5796 150 47.5 1744 +BRAM
-- 2017-06-24 914 2017.1 xc7a35t-1 2708 5668 150 26.0 1787
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.3 use s7_cmt_1ce1ce
-- 2018-10-13 1055 1.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-06-27 918 1.1.1 use 16 kB cache (all BRAM's used up)
-- 2017-06-25 916 1.1 add bram_memctl for 672 kB total memory
-- 2017-06-24 914 1.0 Initial version (derived from sys_w11a_n4)
------------------------------------------------------------------------------
--
-- w11a test design for Cmod A7 (using SRAM+BRAM as memory)
-- w11a + rlink + serport
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.cmoda7lib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_c7 is -- top level
-- implements cmoda7_sram_aif
port (
I_CLK12 : in slbit; -- 12 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3; -- c7 rgb-led 0
O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv19; -- sram: address lines
IO_MEM_DATA : inout slv8 -- sram: data lines
);
end sys_w11a_c7;
architecture syn of sys_w11a_c7 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_REQ_SRAM : slbit := '0';
signal MEM_BUSY_SRAM : slbit := '0';
signal MEM_ACK_R_SRAM : slbit := '0';
signal MEM_ACT_R_SRAM : slbit := '0';
signal MEM_ACT_W_SRAM : slbit := '0';
signal MEM_DO_SRAM : slv32 := (others=>'0');
signal MEM_REQ_BRAM : slbit := '0';
signal MEM_BUSY_BRAM : slbit := '0';
signal MEM_ACK_R_BRAM : slbit := '0';
signal MEM_ACT_R_BRAM : slbit := '0';
signal MEM_ACT_W_BRAM : slbit := '0';
signal MEM_ADDR_BRAM : slv20 := (others=>'0');
signal MEM_DO_BRAM : slv32 := (others=>'0');
signal R_MEM_A17 : slbit := '0';
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal ESWI : slv16 := (others=>'0');
signal EBTN : slv5 := (others=>'0');
signal ELED : slv16 := (others=>'0');
signal EDSP_DAT : slv32 := (others=>'0');
signal EDSP_DP : slv8 := (others=>'0');
signal LED : slv2 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"09"; -- cmoda7
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 83.3,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK12,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
-- logic to distribute/collect request/response to SRAM/BRAM
proc_a17reg: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_MEM_A17 <= '0';
else
if MEM_REQ = '1' then
R_MEM_A17 <= MEM_ADDR(17);
end if;
end if;
end if;
end process proc_a17reg;
proc_a17mux: process (R_MEM_A17, MEM_REQ, MEM_ADDR,
MEM_BUSY_SRAM, MEM_BUSY_BRAM,
MEM_ACK_R_SRAM, MEM_ACK_R_BRAM,
MEM_ACT_R_SRAM, MEM_ACT_R_BRAM,
MEM_ACT_W_SRAM, MEM_ACT_W_BRAM,
MEM_DO_SRAM, MEM_DO_BRAM)
begin
MEM_REQ_SRAM <= MEM_REQ and not MEM_ADDR(17);
MEM_REQ_BRAM <= MEM_REQ and MEM_ADDR(17);
MEM_ADDR_BRAM <= "000" & MEM_ADDR(16 downto 0);
if R_MEM_A17 = '0' then
MEM_BUSY <= MEM_BUSY_SRAM;
MEM_ACK_R <= MEM_ACK_R_SRAM;
MEM_ACT_R <= MEM_ACT_R_SRAM;
MEM_ACT_W <= MEM_ACT_W_SRAM;
MEM_DO <= MEM_DO_SRAM;
else
MEM_BUSY <= MEM_BUSY_BRAM;
MEM_ACK_R <= MEM_ACK_R_BRAM;
MEM_ACT_R <= MEM_ACT_R_BRAM;
MEM_ACT_W <= MEM_ACT_W_BRAM;
MEM_DO <= MEM_DO_BRAM;
end if;
end process proc_a17mux;
SRAM_CTL : c7_sram_memctl -- SRAM memory controller ------------
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ_SRAM,
WE => MEM_WE,
BUSY => MEM_BUSY_SRAM,
ACK_R => MEM_ACK_R_SRAM,
ACK_W => open,
ACT_R => MEM_ACT_R_SRAM,
ACT_W => MEM_ACT_W_SRAM,
ADDR => MEM_ADDR(16 downto 0),
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO_SRAM,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
BRAM_CTL: pdp11_bram_memctl -- BRAM memory controller ------------
generic map (
MAWIDTH => sys_conf_memctl_mawidth,
NBLOCK => sys_conf_memctl_nblock)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ_BRAM,
WE => MEM_WE,
BUSY => MEM_BUSY_BRAM,
ACK_R => MEM_ACK_R_BRAM,
ACK_W => open,
ACT_R => MEM_ACT_R_BRAM,
ACT_W => MEM_ACT_W_BRAM,
ADDR => MEM_ADDR_BRAM,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO_BRAM
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => EDSP_DP(3 downto 0)
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => ELED'length,
DCWIDTH => 3)
port map (
SEL_LED => ESWI(3),
SEL_DSP => ESWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => ELED,
DSP_DAT => EDSP_DAT
);
EHIO : sn_humanio_emu_rbus -- emulated hio ----------------------
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3)
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => ESWI,
BTN => EBTN,
LED => ELED,
DSP_DAT => EDSP_DAT,
DSP_DP => EDSP_DP
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (LP: Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
IOB_LED : iob_reg_o_gen
generic map (DWIDTH => O_LED'length)
port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
LED(1) <= SER_MONI.txact;
LED(0) <= SER_MONI.rxact;
-- setup unused outputs in cmoda7
O_RGBLED0_N <= (others=>'1');
end syn;
| gpl-3.0 | 6084bb11b80bac38d4bf456f19038625 | 0.498114 | 3.106436 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/IO_ctl_TB.vhd | 1 | 4,402 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:35:00 03/08/2011
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/Projects/Personal/Senior Project/OZ-4/OZ-4 FPGA/OZ4/IO_ctl_TB.vhd
-- Project Name: OZ4
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IO_ctl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY IO_ctl_TB IS
END IO_ctl_TB;
ARCHITECTURE behavior OF IO_ctl_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IO_ctl
PORT(
clk : IN std_logic;
rst : IN std_logic;
iport : IN std_logic_vector(31 downto 0);
iport_data : OUT std_logic_vector(31 downto 0);
ipins : IN std_logic_vector(7 downto 0);
ipins_data : OUT std_logic_vector(31 downto 0);
ipins_sel : IN std_logic_vector(2 downto 0);
oport : OUT std_logic_vector(31 downto 0);
oport_data : IN std_logic_vector(31 downto 0);
oport_en : IN std_logic;
opins : OUT std_logic_vector(7 downto 0);
opins_data : IN std_logic_vector(31 downto 0);
opins_sel : IN std_logic_vector(2 downto 0);
opins_en : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal iport : std_logic_vector(31 downto 0) := (others => '0');
signal ipins : std_logic_vector(7 downto 0) := (others => '0');
signal ipins_sel : std_logic_vector(2 downto 0) := (others => '0');
signal oport_data : std_logic_vector(31 downto 0) := (others => '0');
signal oport_en : std_logic := '0';
signal opins_data : std_logic_vector(31 downto 0) := (others => '0');
signal opins_sel : std_logic_vector(2 downto 0) := (others => '0');
signal opins_en : std_logic := '0';
--Outputs
signal iport_data : std_logic_vector(31 downto 0);
signal ipins_data : std_logic_vector(31 downto 0);
signal oport : std_logic_vector(31 downto 0);
signal opins : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IO_ctl PORT MAP (
clk => clk,
rst => rst,
iport => iport,
iport_data => iport_data,
ipins => ipins,
ipins_data => ipins_data,
ipins_sel => ipins_sel,
oport => oport,
oport_data => oport_data,
oport_en => oport_en,
opins => opins,
opins_data => opins_data,
opins_sel => opins_sel,
opins_en => opins_en
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 1000 ns;
rst <= '0';
iport <= x"12345678";
ipins <= x"FA";
ipins_sel <= o"6";
wait for 10 ns;
oport_data <= x"87654321";
oport_en <= '1';
opins_data <= x"00000001";
opins_sel <= o"5";
opins_en <= '1';
wait for 10 ns;
oport_data <= x"00000000";
oport_en <= '0';
opins_data <= x"00000000";
opins_sel <= o"0";
opins_en <= '0';
ipins_sel <= o"0";
wait for 10 ns;
opins_data <= x"00000001";
opins_sel <= o"3";
opins_en <= '1';
wait for 10 ns;
opins_data <= x"00000000";
opins_sel <= o"5";
opins_en <= '1';
wait;
end process;
END;
| mit | 608fca8297346611f60e5bb821b4d9ef | 0.551795 | 3.496426 | false | false | false | false |
wfjm/w11 | rtl/bplib/sysmon/sysmon_rbus_core.vhd | 1 | 12,991 | -- $Id: sysmon_rbus_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sysmon_rbus_core - syn
-- Description: SYSMON interface to rbus (generic)
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic (all with SYSMON or XADC)
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-25 767 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- BUGFIX: use s_init in regs_init (was s_idle)
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
-- - in general 1-to-1 mapping to sysmon/xadc address space
-- --> see function in sysmon/xadc user guide
-- - 8 addresses are implemented on the controller (base is ibase, default x"78")
-- --> see function below
--
-- Addr Bits Name r/w/f Function
-- 000 cntl -/-/f cntl
-- 15 reset -/-/f reset SYSMON
-- 001 stat r/w/- stat
-- 3 jlock r/c/- JTAGLOCKED seen
-- 2 jmod r/c/- JTAGMODIFIED seen
-- 1 jbusy r/c/- JTAGBUSY seen
-- 0 ot r/c/- OT seen
-- 010 almh r/w/- alm history
-- *:00 alm r/c/- ALM(*:0) seen
-- 011 -/-/- <unused>
-- 100 temp r/-/- current temp value
-- 101 alm r/-/- current alm value
-- *:00 alm r/-/- alm(*:0)
-- 110 -/-/- <unused>
-- 111 eos r/-/- eos counter
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
-- ----------------------------------------------------------------------------
entity sysmon_rbus_core is -- SYSMON interface to rbus
generic (
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SM_DEN : out slbit; -- sysmon: drp enable
SM_DWE : out slbit; -- sysmon: drp write enable
SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address
SM_DI : out slv16; -- sysmon: data input
SM_DO : in slv16; -- sysmon: data output
SM_DRDY : in slbit; -- sysmon: data ready
SM_EOS : in slbit; -- sysmon: end of scan
SM_RESET : out slbit; -- sysmon: reset
SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms
SM_OT : in slbit; -- sysmon: overtemperature
SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY
SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED
SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED
TEMP : out slv(TEWIDTH-1 downto 0) -- die temp
);
end sysmon_rbus_core;
architecture syn of sysmon_rbus_core is
type state_type is (
s_init, -- init: wait for jtaglocked down
s_idle, -- idle: dispatch
s_wait, -- wait: wait on drdy
s_twait -- twait: wait on drdy of temp read
);
type regs_type is record
rbsel : slbit; -- rbus select
state : state_type; -- state
eoscnt : slv16; -- eos counter
stat_ot : slbit; -- stat: ot
stat_jlock : slbit; -- stat: jtag locked
stat_jmod : slbit; -- stat: jtag modified
stat_jbusy : slbit; -- stat: jtag busy
almh : slv(ALWIDTH-1 downto 0); -- almh
temp : slv(TEWIDTH-1 downto 0); -- temp value
tpend : slbit; -- temp pending
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
s_init, -- state
(others=>'0'), -- eoscnt
'0','0','0','0', -- stat_ot, stat_j*
slv(to_unsigned(0,ALWIDTH)), -- almh
slv(to_unsigned(0,TEWIDTH)), -- temp
'0' -- tpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
-- only internal regs have names, only 3 LSB in constant
constant rbaddr_cntl: slv3 := "000"; -- 0 -/-/f
constant rbaddr_stat: slv3 := "001"; -- 1 r/w/-
constant rbaddr_almh: slv3 := "010"; -- 2 r/w/-
constant rbaddr_temp: slv3 := "100"; -- 4 r/-/-
constant rbaddr_alm: slv3 := "101"; -- 5 r/-/-
constant rbaddr_eos: slv3 := "111"; -- 7 r/-/-
constant cntl_rbf_reset: integer := 15;
constant stat_rbf_jlock: integer := 3;
constant stat_rbf_jmod: integer := 2;
constant stat_rbf_jbusy: integer := 1;
constant stat_rbf_ot: integer := 0;
begin
assert DAWIDTH=7 or DAWIDTH=8
report "assert(DAWIDTH=7 or DAWIDTH=8): unsupported DAWIDTH"
severity failure;
assert ALWIDTH<=16
report "assert ALWIDTH<16: unsupported ALWIDTH"
severity failure;
assert TEWIDTH=10 or TEWIDTH=12
report "assert(TEWIDTH=10 or TEWIDTH=12): unsupported TEWIDTH"
severity failure;
assert IBASE(2 downto 0) = "000"
report "assert IBASE(2:0) = 000: invalid IBASE"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, SM_DO, SM_DRDY, SM_EOS, SM_ALM, SM_OT,
SM_JTAGLOCKED, SM_JTAGMODIFIED, SM_JTAGBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable irb_addr_ext : slbit := '0';
variable irb_addr_int : slbit := '0';
variable ism_den : slbit := '0';
variable ism_dwe : slbit := '0';
variable ism_daddr : slv(DAWIDTH-1 downto 0) := (others=>'0');
variable ism_reset : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- check for internal rbus controller register window
irb_addr_int := '0';
if RB_MREQ.addr(DAWIDTH-1 downto 3) = IBASE(DAWIDTH-1 downto 3) then
irb_addr_int := '1';
end if;
ism_den := '0';
ism_dwe := '0';
ism_daddr := RB_MREQ.addr(DAWIDTH-1 downto 0); -- default
ism_reset := '0';
-- handle EOS
if SM_EOS = '1' then
n.tpend := '1'; -- queue temp read
n.eoscnt := slv(unsigned(r.eoscnt) + 1); -- and count it
end if;
-- update stat and almh register fields
n.stat_ot := r.stat_ot or SM_OT;
n.stat_jlock := r.stat_jlock or SM_JTAGLOCKED;
n.stat_jmod := r.stat_jmod or SM_JTAGMODIFIED;
n.stat_jbusy := r.stat_jbusy or SM_JTAGBUSY;
n.almh := r.almh or SM_ALM;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 7)=RB_ADDR(15 downto 7) then
n.rbsel := '1';
end if;
irb_ack := r.rbsel and irbena; -- ack all accesses
irb_busy := irb_ack; -- busy is default
-- internal state machine
case r.state is
when s_init => -- init: wait for jtaglocked down ----
if SM_JTAGLOCKED = '0' then
n.stat_jlock := '0'; -- clear status
n.state := s_idle; -- start working
end if;
when s_idle => -- idle: dispatch --------------------
if r.tpend = '1' then -- temp update pending ?
n.tpend := '0'; -- mark done
if SM_JTAGLOCKED = '0' then -- if not jlocked
ism_daddr := "0000000"; -- temp is reg 00h
ism_dwe := '0'; -- do read
ism_den := '1'; -- start drp cycle
n.state := s_twait;
end if;
elsif r.rbsel = '1' then -- rbus access ?
if irb_addr_int ='1' then -- internal controller regs
irb_busy := '0';
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
ism_reset := RB_MREQ.din(cntl_rbf_reset);
end if;
when rbaddr_stat =>
if RB_MREQ.we = '1' then
n.stat_jlock := r.stat_jlock and
not RB_MREQ.din(stat_rbf_jlock);
n.stat_jmod := r.stat_jmod and
not RB_MREQ.din(stat_rbf_jmod);
n.stat_jbusy := r.stat_jbusy and
not RB_MREQ.din(stat_rbf_jbusy);
n.stat_ot := r.stat_ot and
not RB_MREQ.din(stat_rbf_ot);
end if;
when rbaddr_almh =>
if RB_MREQ.we = '1' then
n.almh := r.almh and not RB_MREQ.din(r.almh'range);
end if;
when rbaddr_temp =>
irb_err := RB_MREQ.we;
when rbaddr_alm =>
irb_err := RB_MREQ.we;
when rbaddr_eos =>
irb_err := RB_MREQ.we;
when others =>
irb_err := irbena;
end case;
else -- sysmon reg access
if irbena = '1' then
if SM_JTAGLOCKED = '0' then -- if not jlocked
ism_daddr := RB_MREQ.addr(ism_daddr'range);
ism_dwe := RB_MREQ.we;
ism_den := '1'; -- start drp cycle
n.state := s_wait;
else
irb_err := '1'; -- quit with error if jlocked
end if;
end if;
end if;
end if;
when s_wait => -- wait: wait on drdy ----------------
n.state := s_wait;
if SM_DRDY = '1' then
irb_busy := '0';
n.state := s_idle;
end if;
when s_twait => -- twait: wait on drdy of temp read --
n.state := s_twait;
if SM_DRDY = '1' then
n.temp := SM_DO(15 downto 16-TEWIDTH); -- take msb's
n.state := s_idle;
end if;
when others => null; -- <> ------------------------------
end case; -- case r.state
-- rbus output driver
if r.rbsel = '1' then
if irb_addr_int = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_jlock) := r.stat_jlock;
irb_dout(stat_rbf_jmod) := r.stat_jmod;
irb_dout(stat_rbf_jbusy) := r.stat_jbusy;
irb_dout(stat_rbf_ot) := r.stat_ot;
when rbaddr_almh =>
irb_dout(r.almh'range) := r.almh;
when rbaddr_temp =>
irb_dout(r.temp'range) := r.temp;
when rbaddr_alm =>
irb_dout(SM_ALM'range) := SM_ALM;
when rbaddr_eos =>
irb_dout := r.eoscnt;
when others =>
irb_dout := (others=>'0');
end case;
else
irb_dout := SM_DO;
end if;
end if;
N_REGS <= n;
SM_DEN <= ism_den;
SM_DWE <= ism_dwe;
SM_DADDR <= ism_daddr;
SM_DI <= RB_MREQ.din;
SM_RESET <= ism_reset;
TEMP <= r.temp;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 | 3b8490d8d16bec2fa81c9b7cf30318d0 | 0.465322 | 3.710654 | false | false | false | false |
jasonpeng/cg3207-proj | ALU/AddSub.vhd | 1 | 3,556 | library ieee;
use ieee.std_logic_1164.all;
entity addsub_lookahead is
Port ( Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end addsub_lookahead;
architecture beh_addsub_lookahead of addsub_lookahead is
component adder_lookahead_4
Port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
SUM : out STD_LOGIC_VECTOR (3 downto 0);
Cout: out STD_LOGIC
);
end component;
signal Cin: STD_LOGIC;
signal C: STD_LOGIC_VECTOR(7 downto 0);
signal OP2: STD_LOGIC_VECTOR(31 downto 0);
signal buffer1: STD_LOGIC_VECTOR(31 downto 0);
begin
L0: adder_lookahead_4 port map(Operand1(3 downto 0), OP2(3 downto 0), Cin, buffer1(3 downto 0), C(0));
L1: adder_lookahead_4 port map(Operand1(7 downto 4), OP2(7 downto 4), C(0), buffer1(7 downto 4), C(1));
L2: adder_lookahead_4 port map(Operand1(11 downto 8), OP2(11 downto 8), C(1), buffer1(11 downto 8), C(2));
L3: adder_lookahead_4 port map(Operand1(15 downto 12), OP2(15 downto 12), C(2), buffer1(15 downto 12), C(3));
L4: adder_lookahead_4 port map(Operand1(19 downto 16), OP2(19 downto 16), C(3), buffer1(19 downto 16), C(4));
L5: adder_lookahead_4 port map(Operand1(23 downto 20), OP2(23 downto 20), C(4), buffer1(23 downto 20), C(5));
L6: adder_lookahead_4 port map(Operand1(27 downto 24), OP2(27 downto 24), C(5), buffer1(27 downto 24), C(6));
L7: adder_lookahead_4 port map(Operand1(31 downto 28), OP2(31 downto 28), C(6), buffer1(31 downto 28), C(7));
Result1 <= buffer1;
Result2 <= (others => '0');
process (Control, Operand1, Operand2, C, buffer1)
variable O : STD_LOGIC := '0';
variable operand_same_sign : STD_LOGIC := '0';
variable result_diff_sign : STD_LOGIC := '0';
begin
if (Control(1) = '1') then
Cin <= '1';
OP2 <= NOT Operand2;
else
Cin <= '0';
OP2 <= Operand2;
end if;
if (Control(0) = '0') then
operand_same_sign := NOT (Operand1(31) XOR Operand2(31));
result_diff_sign := Operand1(31) XOR buffer1(31);
O := operand_same_sign and result_diff_sign;
Debug <= X"0000" & "000" & O & C; -- add, sub with overflow trap/flag
else
Debug <= X"00000" & C; --addu, subu
end if;
end process;
end beh_addsub_lookahead;
--- lookahead entity
library ieee;
use ieee.std_logic_1164.all;
entity adder_lookahead_4 is
Port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin: in STD_LOGIC;
SUM : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC
);
end adder_lookahead_4;
architecture beh_adder_lookahead_4 of adder_lookahead_4 is
begin
process (A, B, Cin)
variable G : STD_LOGIC_VECTOR (3 downto 0);
variable P : STD_LOGIC_VECTOR (3 downto 0);
variable C: STD_LOGIC_VECTOR (4 downto 0);
begin
G := A AND B;
P := A OR B;
C(0) := Cin;
C(1) := G(0) OR (P(0) AND C(0));
C(2) := G(1) OR (G(0) AND P(1)) OR (C(0) AND P(0) AND P(1));
C(3) := G(2) OR (G(1) AND P(2)) OR (G(0) AND P(1) AND P(2)) OR (C(0) AND P(0) AND P(1) AND P(2));
C(4) := G(3) OR (G(2) AND P(3)) OR (G(1) AND P(2) AND P(3)) OR (G(0) AND P(1) AND P(2) AND P(3)) OR (C(0) AND P(0) AND P(1) AND P(2) AND P(3));
Sum <= (A(3) xor B(3) xor C(3)) & (A(2) xor B(2) xor C(2)) & (A(1) xor B(1) xor C(1)) & (A(0) xor B(0) xor C(0));
Cout <= C(4);
end process;
end beh_adder_lookahead_4; | gpl-2.0 | 308dc0adf3bad3fc67019f5af1bef1bf | 0.629359 | 2.50599 | false | false | false | false |
jasonpeng/cg3207-proj | Execute.vhd | 1 | 9,287 | -----------------------------
-------- FORWARDING UNIT ----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Forwarding_Unit is
Port(
ID_EX_RS : in STD_LOGIC_VECTOR(4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR(4 downto 0);
EX_MM_RegWrite : in STD_LOGIC;
EX_MM_RD : in STD_LOGIC_VECTOR(4 downto 0);
MM_WB_RegWrite : in STD_LOGIC;
MM_WB_RD : in STD_LOGIC_VECTOR(4 downto 0);
FW_A : out STD_LOGIC_VECTOR(1 downto 0);
FW_B : out STD_LOGIC_VECTOR(1 downto 0)
);
end Forwarding_Unit;
architecture Behavioral of Forwarding_Unit is
begin
process(ID_EX_RS, ID_EX_RT,
EX_MM_RegWrite, EX_MM_RD,
MM_WB_RegWrite, MM_WB_RD )
begin
if ( EX_MM_RegWrite = '1'
AND (EX_MM_RD /= "00000")
AND (EX_MM_RD = ID_EX_RS)
) then
FW_A <= "01";
elsif ( MM_WB_RegWrite = '1'
AND (MM_WB_RD /= "00000")
--AND (NOT (EX_MM_RegWrite = '1' AND (EX_MM_RD /= "00000")))
AND (EX_MM_RD /= ID_EX_RS)
AND (MM_WB_RD = ID_EX_RS)
) then
FW_A <= "10";
else
FW_A <= "00";
end if;
if ( EX_MM_RegWrite = '1'
AND (EX_MM_RD /= "00000")
AND (EX_MM_RD = ID_EX_RT)
) then
FW_B <= "01";
elsif ( MM_WB_RegWrite = '1'
AND (MM_WB_RD /= "00000")
--AND (NOT (EX_MM_RegWrite = '1' AND (EX_MM_RD /= "00000")))
AND (EX_MM_RD /= ID_EX_RT)
AND (MM_WB_RD = ID_EX_RT)
) then
FW_B <= "10";
else
FW_B <= "00";
end if;
end process;
end Behavioral;
-----------------------------
-------- EXECUTE ------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Execute is
Port (
IN_ID_EX_ALUOp : in STD_LOGIC_VECTOR(2 downto 0);
IN_ID_EX_SignExtended : in STD_LOGIC_VECTOR(31 downto 0);
-- extended signed immediate value; also used for ALU opcode
IN_ID_EX_ALUSrc : in STD_LOGIC; -- selects second operand for ALU
IN_ID_EX_Data1 : in STD_LOGIC_VECTOR(31 downto 0); -- data1 from register
IN_ID_EX_Data2 : in STD_LOGIC_VECTOR(31 downto 0); -- data2 from register
IN_ID_EX_MemWrite : in STD_LOGIC;
IN_ID_EX_RegDst : in STD_LOGIC; --selects writeback address
IN_ID_EX_Instr_25_21 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_EX_Instr_20_16 : in STD_LOGIC_VECTOR(4 downto 0);
IN_ID_EX_Instr_15_11 : in STD_LOGIC_VECTOR(4 downto 0);
-- forward unit
IN_EX_MM_RegWrite : in STD_LOGIC;
IN_EX_MM_RD : in STD_LOGIC_VECTOR(4 downto 0);
IN_EX_MM_ALU_Result : in STD_LOGIC_VECTOR(31 downto 0);
IN_MM_WB_RegWrite : in STD_LOGIC;
IN_MM_WB_RD : in STD_LOGIC_VECTOR(4 downto 0);
IN_WB_Reg_Data : in STD_LOGIC_VECTOR(31 downto 0);
-- alu related
OUT_EX_MM_OVF : out STD_LOGIC;
OUT_EX_MM_Zero : out STD_LOGIC;
OUT_EX_MM_ALU_Result_1 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_EX_MM_ALU_Result_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_EX_MM_Data_2 : out STD_LOGIC_VECTOR(31 downto 0);
OUT_EX_MM_MULDIV : out STD_LOGIC; -- asserts for mul/div results
OUT_EX_MM_RegWriteAddr : out STD_LOGIC_VECTOR(4 downto 0) -- register address
);
end Execute;
architecture Behavioral of Execute is
-- Forwarding Unit Component --
component Forwarding_Unit
Port(
ID_EX_RS : in STD_LOGIC_VECTOR(4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR(4 downto 0);
EX_MM_RegWrite : in STD_LOGIC;
EX_MM_RD : in STD_LOGIC_VECTOR(4 downto 0);
MM_WB_RegWrite : in STD_LOGIC;
MM_WB_RD : in STD_LOGIC_VECTOR(4 downto 0);
FW_A : out STD_LOGIC_VECTOR(1 downto 0);
FW_B : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
--
-- Fowarding Unit Signals --
signal FWU_A : STD_LOGIC_VECTOR(1 downto 0);
signal FWU_B : STD_LOGIC_VECTOR(1 downto 0);
--
-- ALU Component --
component ALU
Port (
Control : in STD_LOGIC_VECTOR ( 5 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
--
-- ALU Signals
signal ALU_Ctrl : STD_LOGIC_VECTOR(5 downto 0);
signal ALU_Op1 : STD_LOGIC_VECTOR(31 downto 0);
signal ALU_Op2 : STD_LOGIC_VECTOR(31 downto 0);
signal ALU_R1 : STD_LOGIC_VECTOR(31 downto 0);
signal ALU_R2 : STD_LOGIC_VECTOR(31 downto 0);
signal ALU_Debug: STD_LOGIC_VECTOR(31 downto 0);
--
begin
-- Forwarding Unit Port Map --
FWU : Forwarding_Unit Port Map (
ID_EX_RS => IN_ID_EX_Instr_25_21,
ID_EX_RT => IN_ID_EX_Instr_20_16,
EX_MM_RegWrite => IN_EX_MM_RegWrite,
EX_MM_RD => IN_EX_MM_RD,
MM_WB_RegWrite => IN_MM_WB_RegWrite,
MM_WB_RD => IN_MM_WB_RD,
FW_A => FWU_A,
FW_B => FWU_B
);
ALU1 : ALU Port Map (
Control => ALU_Ctrl,
Operand1 => ALU_Op1,
Operand2 => ALU_Op2,
Result1 => ALU_R1,
Result2 => ALU_R2,
Debug => ALU_Debug
);
--
-- Set MEM_ALU_Result
OUT_EX_MM_ALU_Result_1 <= ALU_R1;
OUT_EX_MM_ALU_Result_2 <= ALU_R2;
-- Set MEM_Zero
OUT_EX_MM_Zero <=
'1' when ALU_R1 = X"00000000"
else '0';
-- Select Register Write Address
OUT_EX_MM_RegWriteAddr <=
IN_ID_EX_Instr_20_16 when IN_ID_EX_RegDst='0'
else IN_ID_EX_Instr_15_11 when IN_ID_EX_RegDst='1'
else "XXXXX";
process(
IN_ID_EX_ALUOp,
IN_ID_EX_SignExtended,
IN_ID_EX_ALUSrc,
IN_ID_EX_Data1,
IN_ID_EX_Data2,
IN_ID_EX_RegDst,
IN_ID_EX_Instr_25_21,
IN_ID_EX_Instr_20_16,
IN_ID_EX_Instr_15_11,
IN_EX_MM_RegWrite,
IN_EX_MM_RD,
IN_EX_MM_ALU_Result,
IN_MM_WB_RegWrite,
IN_MM_WB_RD,
IN_WB_Reg_Data,
FWU_A,
FWU_B
)
variable A : STD_LOGIC_VECTOR(31 downto 0); -- op1 for ALU
variable B0 : STD_LOGIC_VECTOR(31 downto 0);
variable B : STD_LOGIC_VECTOR(31 downto 0); -- op2 for ALU
variable shftamt : STD_LOGIC_VECTOR(31 downto 0); -- shift amount
variable R_funct : STD_LOGIC_VECTOR(5 downto 0); -- ALU R type funct (Instr[5-0])
variable b_sll : boolean;
variable b_sra : boolean;
variable b_srl : boolean;
begin
-- forwarding mux for A and B (op1 and op2)
case FWU_A is
when "00" => A := IN_ID_EX_Data1;
when "01" => A := IN_EX_MM_ALU_Result;
when "10" => A := IN_WB_Reg_Data;
when others => A := (others => 'X');
end case;
if (FWU_B="00") then
B0 := IN_ID_EX_Data2;
elsif (FWU_B="01") then
B0 := IN_EX_MM_ALU_Result;
elsif (FWU_B="10") then
B0 := IN_WB_Reg_Data;
else
B0 := (others => 'X');
end if;
if (IN_ID_EX_ALUSrc='0') then
B := B0;
elsif (IN_ID_EX_ALUSrc='1') then
B := IN_ID_EX_SignExtended;
else
B := (others => 'X');
end if;
-- forwarding for SW
if (IN_EX_MM_RegWrite='1' AND IN_EX_MM_RD /= "00000")
AND (IN_ID_EX_Instr_20_16 = IN_EX_MM_RD)
AND (IN_ID_EX_MemWrite = '1') then
OUT_EX_MM_Data_2 <= IN_EX_MM_ALU_Result;
else
OUT_EX_MM_Data_2 <= IN_ID_EX_Data2;
end if;
shftamt := X"000000" & "000" & IN_ID_EX_SignExtended(10 downto 6);
R_funct := IN_ID_EX_SignExtended(5 downto 0);
b_sll := (IN_ID_EX_ALUOp="100" AND (R_funct="000000" OR R_funct="000100"))
OR (IN_ID_EX_ALUOp="011"); -- sll, sllv, lui
b_sra := IN_ID_EX_ALUOp="100" AND (R_funct="000011" OR R_funct="000111"); -- sra, srav
b_srl := IN_ID_EX_ALUOp="100" AND (R_funct="000010" OR R_funct="000110"); -- srl, srlv
-- set ALU Op1 and Op2
if ( b_sll OR b_sra OR b_srl ) then -- shifts
ALU_Op1 <= B;
else
ALU_Op1 <= A;
end if;
if (IN_ID_EX_ALUOp="100" AND (R_funct="000000" OR R_funct="000011"
OR R_funct="000010") ) then -- sll, sra, srl
ALU_Op2 <= shftamt;
elsif (IN_ID_EX_ALUOp="100" AND (R_funct="000100" OR R_funct="000111"
OR R_funct="000110") ) then -- sllv, srav, srlv
ALU_Op2 <= A;
elsif (IN_ID_EX_ALUOp="011") then -- lui
ALU_Op2 <= X"00000010";
else
ALU_Op2 <= B;
end if;
-- mux for ALUOp
case IN_ID_EX_ALUOp is
when "100" => -- R type
R_funct := IN_ID_EX_SignExtended(5 downto 0);
case R_funct is
when "000000" => -- sll
ALU_Ctrl <= "001000";
when "000100" => -- sllv
ALU_Ctrl <= "001000";
when "000011" => -- sra
ALU_Ctrl <= "001011";
when "000111" => -- srav
ALU_Ctrl <= "001011";
when "000010" => -- srl
ALU_Ctrl <= "001010";
when "000110" => -- srlv
ALU_Ctrl <= "001010";
when "100000" => -- add, with overflow;
ALU_Ctrl <= "010000";
when "100001" => -- addu
ALU_Ctrl <= "010001";
when "100010" => -- sub
ALU_Ctrl <= "010010";
when "100011" => -- subu
ALU_Ctrl <= "010011";
when "011000" => -- mult
ALU_Ctrl <= "011000";
when "011001" => -- multu
ALU_Ctrl <= "011001";
when "011010" => -- div
ALU_Ctrl <= "011010";
when "011011" => -- divu
ALU_Ctrl <= "011011";
when "101010" => -- slt, set less than
ALU_Ctrl <= "010110";
when "100100" => -- logical and
ALU_Ctrl <= "000001";
when "100101" => -- logical or
ALU_Ctrl <= "000010";
when "100111" => -- nor
ALU_Ctrl <= "000100";
when "100110" => -- xor
ALU_Ctrl <= "000011";
when others => -- undefined, nop
ALU_Ctrl <= "000000";
end case;
when "000" => -- nop
ALU_Ctrl <= "000000";
when "001" => -- LW, SW, ADDI, use ALU 'add'
ALU_Ctrl <= "010000";
when "010" => -- SLTI
ALU_Ctrl <= "010110";
when "011" => -- LUI
ALU_Ctrl <= "001000";
when "111" => -- ORI
ALU_Ctrl <= "000010";
when others =>
ALU_Ctrl <= "000000";
end case;
-- MUL or DIV flag
if ( IN_ID_EX_ALUOp = "100"
AND ( R_funct="011000" OR R_funct="011001" OR R_funct="011010" OR R_funct="011011")) then
OUT_EX_MM_MULDIV <= '1';
else
OUT_EX_MM_MULDIV <= '0';
end if;
end process;
end Behavioral;
| gpl-2.0 | 8298870c50846a6cee8044530ee26bca | 0.605901 | 2.512037 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/artys7/sys_w11a_as7.vhd | 1 | 16,582 | -- $Id: sys_w11a_as7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_br_as7 - syn
-- Description: w11a design for as7 (with dram via mig)
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/artys7/sramif_mig_artys7
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_artys7
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x2mux
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_as7
--
-- Target Devices: generic
-- Tool versions: viv 2018.3-2022.1; ghdl 0.35-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7s50 6843 9162 878 17.5 3184
-- 2019-05-19 1150 2018.3 xc7s50 6843 10554 926 17.5 3425 +dz11
-- 2019-01-12 1105 2018.3 xc7s50 6585 9837 806 17.0 3250
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.0.1 use bufg_unisim
-- 2019-01-12 1105 1.0 Initial version (derived from sys_w11a_arty/br_as7)
------------------------------------------------------------------------------
--
-- w11a design for artys7 (using DDR3 memory via MIG)
-- w11a + rlink + serport
--
-- Usage of Arty S7 switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows bit 7:4, RGB bit 1:0 of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (1) kernel mode, non-wait
-- (0) user or supervisor mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (1:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR( 9:08)
-- RGB_G DR( 5:04)
-- RGB_R DR( 1:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib.all;
use work.miglib_artys7.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_as7 is -- top level
-- implements artys7_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- artys7 switches
I_BTN : in slv4; -- artys7 buttons
O_LED : out slv4; -- artys7 leds
O_RGBLED0 : out slv3; -- artys7 rgb-led 0
O_RGBLED1 : out slv3; -- artys7 rgb-led 1
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_w11a_as7;
architecture syn of sys_w11a_as7 is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv2 := (others=>'0');
signal RGB_G : slv2 := (others=>'0');
signal RGB_B : slv2 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"0a"; -- artys7
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 16, -- vco 1600 MHz
CLK2_OUTDIV => 10, -- mig sys 160.0 MHz
CLK3_OUTDIV => 8, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLK_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_CLK
);
GBL_RESET <= not LOCKED_CLK;
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 9, -- 512 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit
PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit
PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEMCTL: sramif_mig_artys7 -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => GBL_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLKMIG,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_artys7 -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x2mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1
);
SMRB : sysmonx_rbus_base -- always instantiated, needed for mig
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | 8541ce15221a723d695b9b5da474cf2b | 0.483416 | 3.256481 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4/tb/tb_nexys4_core.vhd | 1 | 1,961 | -- $Id: tb_nexys4_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_core - sim
-- Description: Test bench for nexys4 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any nexys4 target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_nexys4_core is
port (
I_SWI : out slv16; -- n4 switches
I_BTN : out slv5; -- n4 buttons
I_BTNRST_N : out slbit -- n4 reset button
);
end tb_nexys4_core;
architecture sim of tb_nexys4_core is
signal R_SWI : slv16 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
signal R_BTNRST : slbit := '0';
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
R_BTNRST <= to_x01(SB_DATA(5));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
I_BTNRST_N <= not R_BTNRST;
end sim;
| gpl-3.0 | e53c86da9b91113bf8ada8ed247f1ff3 | 0.554819 | 3.102848 | false | false | false | false |
abcsds/Micros | RS232Read_16/baudraterd.vhd | 4 | 2,064 | -- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end BaudRateRD;
architecture simple of BaudRateRD is
signal NB, Qp, Qn : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,ENC,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1111010000100100000"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(ENC='0')then
Qn<= NB;
FBaud<= '0';
else
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end if;
end process COMB;
FF: process(RST,CLK,Qn)
begin
if(RST='1')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
| gpl-3.0 | ab9098d1701d597e07238923c0485227 | 0.579942 | 3.155963 | false | false | false | false |
boztalay/OZ-4 | OZ4_ASM/instruction_memory.vhd | 1 | 4,300 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity instruction_memory is
port(address : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(11 downto 0);
immediate_addr : in std_logic_vector(5 downto 0);
immediate_out : out std_logic_vector(31 downto 0));
end instruction_memory;
architecture Behavioral of instruction_memory is
type instruction_data_type is array (4095 downto 0) of std_logic_vector(11 downto 0); --4 kB of data memory
signal instruction_data : instruction_data_type;
type immediate_data_type is array (63 downto 0) of std_logic_vector(31 downto 0);
signal immediate_data : immediate_data_type;
signal address_short : std_logic_vector(11 downto 0);
begin
address_short <= address(11 downto 0);
data_out <= instruction_data(conv_integer(unsigned(address_short)));
immediate_out <= immediate_data(conv_integer(unsigned(immediate_addr)));
immediate_data(0) <= x"00000000";
immediate_data(1) <= x"06666668";
immediate_data(2) <= x"08ccccd0";
immediate_data(3) <= x"00000001";
immediate_data(4) <= x"00000010";
immediate_data(5) <= x"00000002";
immediate_data(6) <= x"00000003";
immediate_data(7) <= x"000000ff";
immediate_data(8) <= x"40000000";
immediate_data(9) <= x"00000046";
instruction_data(1) <= "010100000001";
instruction_data(2) <= "010100000000";
instruction_data(3) <= "110001000000";
instruction_data(4) <= "010100000010";
instruction_data(5) <= "010100000011";
instruction_data(6) <= "110001000000";
instruction_data(7) <= "010100000010";
instruction_data(8) <= "010101000000";
instruction_data(9) <= "001011000000";
instruction_data(10) <= "010100000001";
instruction_data(11) <= "010101000000";
instruction_data(12) <= "001011000000";
instruction_data(13) <= "010100000010";
instruction_data(14) <= "010100000010";
instruction_data(15) <= "010100000001";
instruction_data(16) <= "001011000000";
instruction_data(17) <= "000111000000";
instruction_data(18) <= "000001000000";
instruction_data(19) <= "010010000000";
instruction_data(20) <= "010100000011";
instruction_data(21) <= "110000000000";
instruction_data(22) <= "010010000000";
instruction_data(23) <= "000010000000";
instruction_data(24) <= "000001000000";
instruction_data(25) <= "010001000000";
instruction_data(26) <= "010101000000";
instruction_data(27) <= "010101000000";
instruction_data(28) <= "001011000000";
instruction_data(29) <= "010101000000";
instruction_data(30) <= "010100000101";
instruction_data(31) <= "110001000000";
instruction_data(32) <= "010010000000";
instruction_data(33) <= "011010000000";
instruction_data(34) <= "010101000000";
instruction_data(35) <= "001011000000";
instruction_data(36) <= "010101000000";
instruction_data(37) <= "010100000101";
instruction_data(38) <= "110000000000";
instruction_data(39) <= "000001000000";
instruction_data(40) <= "010100000101";
instruction_data(41) <= "110001000000";
instruction_data(42) <= "010010000000";
instruction_data(43) <= "010001000000";
instruction_data(44) <= "010100000011";
instruction_data(45) <= "110000000000";
instruction_data(46) <= "010010000000";
instruction_data(47) <= "010100000110";
instruction_data(48) <= "110000000000";
instruction_data(49) <= "010100000011";
instruction_data(50) <= "000001000000";
instruction_data(51) <= "010100000111";
instruction_data(52) <= "000110000000";
instruction_data(53) <= "010000000000";
instruction_data(54) <= "010100000110";
instruction_data(55) <= "110001000000";
instruction_data(56) <= "010100000101";
instruction_data(57) <= "010100001001";
instruction_data(58) <= "100001000000";
instruction_data(59) <= "010100000101";
instruction_data(60) <= "110000000000";
instruction_data(61) <= "010100001000";
instruction_data(62) <= "000110000000";
instruction_data(63) <= "010000000000";
instruction_data(64) <= "010000000000";
instruction_data(65) <= "010100000110";
instruction_data(66) <= "010100001001";
instruction_data(67) <= "100001000000";
instruction_data(68) <= "010100000100";
instruction_data(69) <= "100000000000";
end Behavioral; | mit | 0b6cf6fa0bcf7e6440c351a9eaa9b652 | 0.694884 | 3.385827 | false | false | false | false |
sjohann81/hf-risc | devices/peripherals/minimal_soc.vhd | 1 | 8,804 | -- file: minimal_soc.vhd
-- description: basic SoC with peripherals
-- date: 01/2019
-- author: Sergio Johann Filho <[email protected]>
--
-- Very simple configuration for a minimal SoC. Only a single GPIO port
-- a counter and timer are included in this version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity peripherals is
port (
clk_i: in std_logic;
rst_i: in std_logic;
addr_i: in std_logic_vector(31 downto 0);
data_i: in std_logic_vector(31 downto 0);
data_o: out std_logic_vector(31 downto 0);
sel_i: in std_logic;
wr_i: in std_logic;
irq_o: out std_logic;
gpioa_in: in std_logic_vector(7 downto 0);
gpioa_out: out std_logic_vector(7 downto 0);
gpioa_ddr: out std_logic_vector(7 downto 0)
);
end peripherals;
architecture peripherals_arch of peripherals is
signal segment: std_logic_vector(3 downto 0);
signal class: std_logic_vector(3 downto 0);
signal device: std_logic_vector(5 downto 0);
signal funct: std_logic_vector(3 downto 0);
signal paaltcfg0, s0cause, gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0);
signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(7 downto 0);
signal timer0: std_logic_vector(31 downto 0);
signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0);
signal timer1_pre: std_logic_vector(2 downto 0);
signal timer1_set: std_logic;
signal int_gpio, int_timer: std_logic;
signal int_gpioa, int_timer1_ocr, int_timer1_ctc, tmr1_pulse, tmr1_dly, tmr1_dly2: std_logic;
signal paalt0: std_logic;
begin
segment <= addr_i(27 downto 24);
class <= addr_i(19 downto 16);
device <= addr_i(15 downto 10);
funct <= addr_i(7 downto 4);
irq_o <= '1' when s0cause /= "0000" else '0';
s0cause <= '0' & int_timer & int_gpio & '0';
int_gpio <= '1' when ((gpiocause xor gpiocause_inv) and gpiomask) /= "0000" else '0';
gpiocause <= "000" & int_gpioa;
int_gpioa <= '1' when ((pain xor pain_inv) and pain_mask) /= "0000" else '0';
int_timer <= '1' when ((timercause xor timercause_inv) and timermask) /= "0000" else '0';
timercause <= int_timer1_ocr & int_timer1_ctc & timer0(18) & timer0(16);
pain <= gpioa_in;
gpioa_out <= paout(7 downto 1) & paalt0;
gpioa_ddr <= paddr;
paalt0 <= int_timer1_ctc when paaltcfg0(1 downto 0) = "01" else int_timer1_ocr when paaltcfg0(1 downto 0) = "10" else paout(0);
-- address decoder, read from peripheral registers
process(clk_i, rst_i, segment, class, device, funct)
begin
if rst_i = '1' then
data_o <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "000001" => -- S0CAUSE (RO)
data_o <= x"0000000" & s0cause;
when "010000" => -- PAALTCFG0 (RW)
data_o <= x"0000000" & paaltcfg0;
when others =>
data_o <= (others => '0');
end case;
when "0001" => -- GPIO
case device is
when "000001" => -- GPIOCAUSE (RO)
data_o <= x"0000000" & gpiocause;
when "000010" => -- GPIOCAUSE_INV (RW)
data_o <= x"0000000" & gpiocause_inv;
when "000011" => -- GPIOMASK (RW)
data_o <= x"0000000" & gpiomask;
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
data_o <= x"000000" & paddr;
when "0001" => -- PAOUT (RW)
data_o <= x"000000" & paout;
when "0010" => -- PAIN (RO)
data_o <= x"000000" & pain;
when "0011" => -- PAIN_INV (RW)
data_o <= x"000000" & pain_inv;
when "0100" => -- PAIN_MASK (RW)
data_o <= x"000000" & pain_mask;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when "0010" => -- timers
case device is
when "000001" => -- TIMERCAUSE (RO)
data_o <= x"0000000" & timercause;
when "000010" => -- TIMERCAUSE_INV (RW)
data_o <= x"0000000" & timercause_inv;
when "000011" => -- TIMERMASK (RW)
data_o <= x"0000000" & timermask;
when "010000" => -- TIMER0 (RO)
data_o <= timer0;
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
data_o <= x"0000" & timer1;
when "0001" => -- TIMER1_PRE (RW)
data_o <= x"0000000" & '0' & timer1_pre;
when "0010" => -- TIMER1_CTC (RW)
data_o <= x"0000" & timer1_ctc;
when "0011" => -- TIMER1_OCR (RW)
data_o <= x"0000" & timer1_ocr;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
when others =>
data_o <= (others => '0');
end case;
end if;
end if;
end process;
-- peripheral register logic, write to peripheral registers
process(clk_i, rst_i, segment, class, device, funct, tmr1_pulse)
begin
if rst_i = '1' then
paaltcfg0 <= (others => '0');
gpiocause_inv <= (others => '0');
gpiomask <= (others => '0');
paout <= (others => '0');
pain_inv <= (others => '0');
pain_mask <= (others => '0');
paddr <= (others => '0');
timercause_inv <= (others => '0');
timermask <= (others => '0');
timer0 <= (others => '0');
timer1 <= (others => '0');
timer1_set <= '0';
timer1_pre <= (others => '0');
timer1_ctc <= (others => '1');
timer1_ocr <= (others => '0');
int_timer1_ctc <= '0';
elsif clk_i'event and clk_i = '1' then
if sel_i = '1' and wr_i = '1' then
case segment is
when "0001" =>
case class is
when "0000" => -- Segment 0
case device is
when "010000" => -- PAALTCFG0 (RW)
paaltcfg0 <= data_i(3 downto 0);
when others =>
end case;
when "0001" => -- GPIO
case device is
when "000010" => -- GPIOCAUSE_INV (RW)
gpiocause_inv <= data_i(3 downto 0);
when "000011" => -- GPIOMASK (RW)
gpiomask <= data_i(3 downto 0);
when "010000" => -- PORTA
case funct is
when "0000" => -- PADDR (RW)
paddr <= data_i(7 downto 0);
when "0001" => -- PAOUT (RW)
paout <= data_i(7 downto 0);
when "0011" => -- PAIN_INV (RW)
pain_inv <= data_i(7 downto 0);
when "0100" => -- PAIN_MASK (RW)
pain_mask <= data_i(7 downto 0);
when others =>
end case;
when others =>
end case;
when "0010" => -- timers
case device is
when "000010" => -- TIMERCAUSE_INV (RW)
timercause_inv <= data_i(3 downto 0);
when "000011" => -- TIMERMASK (RW)
timermask <= data_i(3 downto 0);
when "010001" => -- TIMER1
case funct is
when "0000" => -- TIMER1 (RW)
if data_i(31) = '1' then
timer1_set <= '1';
end if;
if timer1_set = '1' then
timer1 <= data_i(15 downto 0);
timer1_set <= '0';
end if;
when "0001" => -- TIMER1_PRE (RW)
timer1_pre <= data_i(2 downto 0);
when "0010" => -- TIMER1_CTC (RW)
timer1_ctc <= data_i(15 downto 0);
when "0011" => -- TIMER1_OCR (RW)
timer1_ocr <= data_i(15 downto 0);
when others =>
end case;
when others =>
end case;
when others =>
end case;
when others =>
end case;
end if;
timer0 <= timer0 + 1;
if tmr1_pulse = '1' then
if (timer1 /= timer1_ctc) then
if timer1_set = '0' then
timer1 <= timer1 + 1;
end if;
else
int_timer1_ctc <= not int_timer1_ctc;
timer1 <= (others => '0');
end if;
end if;
end if;
end process;
process(clk_i, rst_i) -- TIMER1 prescaler
begin
if rst_i = '1' then
tmr1_dly <= '0';
tmr1_dly2 <= '0';
elsif clk_i'event and clk_i = '1' then
case timer1_pre is
when "001" =>
tmr1_dly <= timer0(2); -- /4
when "010" =>
tmr1_dly <= timer0(4); -- /16
when "011" =>
tmr1_dly <= timer0(6); -- /64
when "100" =>
tmr1_dly <= timer0(8); -- /256
when "101" =>
tmr1_dly <= timer0(10); -- /1024
when "110" =>
tmr1_dly <= timer0(12); -- /4096
when "111" =>
tmr1_dly <= timer0(14); -- /16384
when others =>
tmr1_dly <= timer0(0); -- /1
end case;
tmr1_dly2 <= tmr1_dly;
end if;
end process;
tmr1_pulse <= '1' when tmr1_dly /= tmr1_dly2 else '0';
int_timer1_ocr <= '1' when timer1 < timer1_ocr else '0';
end peripherals_arch;
| gpl-2.0 | ff20ce57fb078d9016235a358bd528af | 0.541686 | 2.814578 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd | 1 | 7,809 | -- $Id: tb_nexys2_fusp.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tbcore/tbcore_rlink
-- tb_nexys2_core
-- serport/tb/serport_master_tb
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.3.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2_fusp is
end tb_nexys2_fusp;
architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back pressure for data flow to tb
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_fusp_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 52e25f068abfb9c1261a0def63d17b64 | 0.524011 | 3.029092 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_Multiplier_Device.vhdl | 1 | 5,619 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Multiplier 8/16/24/32 bit Device for PicoBlaze
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_Multiplier_Device is
generic (
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
BITS : POSITIVE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8
);
end entity;
architecture rtl of pb_Multiplier_Device is
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
constant BYTES : POSITIVE := div_ceil(BITS, 8);
constant BIT_AB : NATURAL := log2ceil(BYTES);
signal Reg_Operand_A : T_SLVV_8(BYTES - 1 downto 0) := (others => (others => '0'));
signal Reg_Operand_B : T_SLVV_8(BYTES - 1 downto 0) := (others => (others => '0'));
signal Reg_Result : T_SLVV_8((2 * BYTES) - 1 downto 0);
begin
assert ((BITS = 8) or (BITS = 16) or (BITS = 24) or (BITS = 32))
report "Multiplier size is not supported. Supported sizes: 8, 16, 24, 32. BITS=" & INTEGER'image(BITS)
severity failure;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Reg_Operand_A <= (others => (others => '0'));
Reg_Operand_B <= (others => (others => '0'));
else
if (AdrDec_we = '1') then
if (AdrDec_WriteAddress(BIT_AB) = '0') then
Reg_Operand_A(to_index(AdrDec_WriteAddress(BIT_AB - 1 downto 0))) <= AdrDec_Data;
else
Reg_Operand_B(to_index(AdrDec_WriteAddress(BIT_AB - 1 downto 0))) <= AdrDec_Data;
end if;
end if;
end if;
end if;
end process;
DataOut <= Reg_Result(to_index(AdrDec_ReadAddress(BIT_AB downto 0)));
Interrupt <= '0';
Message <= x"00";
-- pipelined multiplication
blkMult : block
signal Operand_A : UNSIGNED(BITS - 1 downto 0);
signal Operand_B : UNSIGNED(BITS - 1 downto 0);
signal Result : UNSIGNED((BITS * 2) - 1 downto 0);
signal Result_d1 : STD_LOGIC_VECTOR((BITS * 2) - 1 downto 0);
signal Result_d2 : STD_LOGIC_VECTOR((BITS * 2) - 1 downto 0);
begin
Operand_A <= unsigned(to_slv(Reg_Operand_A));
Operand_B <= unsigned(to_slv(Reg_Operand_B));
process(Clock)
begin
if rising_edge(Clock) then
Result <= Operand_A * Operand_B;
Result_d1 <= std_logic_vector(Result);
Result_d2 <= Result_d1;
end if;
end process;
Reg_Result <= to_slvv_8(Result_d2);
end block;
end;
| apache-2.0 | faf837864cb0a86d62ac50ffb4652616 | 0.531233 | 3.282126 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/s7_cmt_sfs_2_unisim.vhd | 1 | 6,675 | -- $Id: s7_cmt_sfs_2_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s7_cmt_sfs_2 - syn
-- Description: Series-7 CMT for dual frequency synthesis
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Series-7
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-18 1072 1.0 Initial version (derived from s7_cmt_sfs_3_unisim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity s7_cmt_sfs_2 is -- 7-Series CMT for dual freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT0_DIVIDE : positive := 1; -- output divide
OUT1_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKOUT0 : out slbit; -- clock output 0
CLKOUT1 : out slbit; -- clock output 1
LOCKED : out slbit -- pll/mmcm locked
);
end s7_cmt_sfs_2;
architecture syn of s7_cmt_sfs_2 is
begin
assert GEN_TYPE = "PLL" or GEN_TYPE = "MMCM"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
severity failure;
NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
OUT0_DIVIDE=1 and OUT1_DIVIDE=1 generate
CLKOUT0 <= CLKIN;
CLKOUT1 <= CLKIN;
LOCKED <= '1';
end generate NOGEN;
USEPLL: if GEN_TYPE = "PLL" and
not (VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
OUT0_DIVIDE=1 and OUT1_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKFBOUT_BUF : slbit;
signal CLKOUT0_PLL : slbit;
signal CLKOUT1_PLL : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
signal CLKOUT6_UNUSED : slbit;
pure function bool2string (val : boolean) return string is
begin
if val then
return "TRUE";
else
return "FALSE";
end if;
end function bool2string;
begin
PLL : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT => VCO_MULTIPLY,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => OUT0_DIVIDE,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => OUT1_DIVIDE,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => CLKIN_PERIOD,
REF_JITTER1 => CLKIN_JITTER,
STARTUP_WAIT => bool2string(STARTUP_WAIT))
port map (
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLKOUT0_PLL,
CLKOUT1 => CLKOUT1_PLL,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT_BUF,
CLKIN1 => CLKIN,
LOCKED => LOCKED,
PWRDWN => '0',
RST => '0'
);
BUFG_CLKFB : BUFG
port map (
I => CLKFBOUT,
O => CLKFBOUT_BUF
);
BUFG_CLKOUT0 : BUFG
port map (
I => CLKOUT0_PLL,
O => CLKOUT0
);
BUFG_CLKOUT1 : BUFG
port map (
I => CLKOUT1_PLL,
O => CLKOUT1
);
end generate USEPLL;
USEMMCM: if GEN_TYPE = "MMCM" and
not (VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
OUT0_DIVIDE=1 and OUT1_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKFBOUT_BUF : slbit;
signal CLKFBOUTB_UNUSED : slbit;
signal CLKOUT0_MMCM : slbit;
signal CLKOUT0B_UNUSED : slbit;
signal CLKOUT1_MMCM : slbit;
signal CLKOUT1B_UNUSED : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT2B_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT3B_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
signal CLKOUT6_UNUSED : slbit;
begin
MMCM : MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT_F => real(VCO_MULTIPLY),
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE_F => real(OUT0_DIVIDE),
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => OUT1_DIVIDE,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => CLKIN_PERIOD,
REF_JITTER1 => CLKIN_JITTER,
STARTUP_WAIT => STARTUP_WAIT)
port map (
CLKFBOUT => CLKFBOUT,
CLKFBOUTB => CLKFBOUTB_UNUSED,
CLKOUT0 => CLKOUT0_MMCM,
CLKOUT0B => CLKOUT0B_UNUSED,
CLKOUT1 => CLKOUT1_MMCM,
CLKOUT1B => CLKOUT1B_UNUSED,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT2B => CLKOUT2B_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT3B => CLKOUT3B_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT_BUF,
CLKIN1 => CLKIN,
LOCKED => LOCKED,
PWRDWN => '0',
RST => '0'
);
BUFG_CLKFB : BUFG
port map (
I => CLKFBOUT,
O => CLKFBOUT_BUF
);
BUFG_CLKOUT0 : BUFG
port map (
I => CLKOUT0_MMCM,
O => CLKOUT0
);
BUFG_CLKOUT1 : BUFG
port map (
I => CLKOUT1_MMCM,
O => CLKOUT1
);
end generate USEMMCM;
end syn;
| gpl-3.0 | ea192c9dd0f254d3ed5890f07bc2517a | 0.50427 | 3.956728 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4d/tb/tb_nexys4d_core.vhd | 1 | 1,851 | -- $Id: tb_nexys4d_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d_core - sim
-- Description: Test bench for nexys4d - core device handling
--
-- Dependencies: -
--
-- To test: generic, any nexys4d target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 834 1.0 Initial version (derived from tb_nexys4_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_nexys4d_core is
port (
I_SWI : out slv16; -- n4d switches
I_BTN : out slv5; -- n4d buttons
I_BTNRST_N : out slbit -- n4d reset button
);
end tb_nexys4d_core;
architecture sim of tb_nexys4d_core is
signal R_SWI : slv16 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
signal R_BTNRST : slbit := '0';
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
R_BTNRST <= to_x01(SB_DATA(5));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
I_BTNRST_N <= not R_BTNRST;
end sim;
| gpl-3.0 | c35ad770938eb0dd4602075a7601db1e | 0.553755 | 3.13198 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | regBank.vhd | 1 | 1,586 | Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Use work.array32.all;
Entity regBank is
port (
A1, A2, A3: in std_logic_vector(4 downto 0);
clk, rst, we3: in std_logic;
wd3: in std_logic_vector(31 downto 0);
out1, out2 : out std_logic_vector(31 downto 0)
);
end regBank;
architecture rtl of regBank is
signal OregImux: reg_array;
signal Odec, Ien: std_logic_vector(31 downto 0);
COMPONENT reg
generic(
DATA_WIDTH : natural := 8
);
port(
clk, rst, en : in std_logic;
D : in std_logic_vector ((DATA_WIDTH-1) downto 0);
Q : out std_logic_vector ((DATA_WIDTH-1) downto 0)
);
END COMPONENT ;
COMPONENT mux32to1
port(
input: reg_array;
sel: in std_logic_vector(4 downto 0);
output : out std_logic_vector(31 downto 0)
);
END COMPONENT ;
COMPONENT dec5to1
port(
input: in std_logic_vector(4 downto 0);
output : out std_logic_vector(31 downto 0)
);
END COMPONENT ;
begin
G1: FOR i IN 0 TO 31 GENERATE
Ien(i) <= Odec(i) and we3;
end generate;
G2: FOR i IN 0 TO 31 GENERATE
regb: reg GENERIC MAP (DATA_WIDTH => 32) PORT MAP (
clk => clk,
rst => rst,
en => Ien(i),
D => wd3,
Q => OregImux(i)
);
end generate;
outData1: mux32to1 PORT MAP (
input => OregImux,
sel => A1,
output => out1
);
outData2: mux32to1 PORT MAP (
input => OregImux,
sel => A2,
output => out2
);
decWrite: dec5to1 PORT MAP (
input => A3,
output => Odec
);
end rtl; | mit | b46847dacfa6cb969b0780bf3b7a924b | 0.604035 | 2.688136 | false | false | false | false |
wfjm/w11 | rtl/vlib/serport/tb/tbd_serport_uart_rxtx.vhd | 1 | 2,728 | -- $Id: tbd_serport_uart_rxtx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_uart_rxtx - syn
-- Description: Wrapper for serport_uart_rxtx to avoid records. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: serport_uart_rxtx
--
-- To test: serport_uart_rxtx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 69 122 0 - t 9.13
-- 2007-10-27 92 9.1 J30 xc3s1000-4 69 122 0 - t 9.13
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 73 152 0 81 s 9.30
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 73 125 0 - s 9.30
--
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity tbd_serport_uart_rxtx is -- serial port uart [tb design]
-- generic: CDWIDTH=13
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv13; -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end tbd_serport_uart_rxtx;
architecture syn of tbd_serport_uart_rxtx is
begin
UART : serport_uart_rxtx
generic map (
CDWIDTH => 13)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
| gpl-3.0 | c10990674371dce27905cb5f8ffecf98 | 0.506598 | 3.747253 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/spi_master/spi_master.vhd | 1 | 2,899 | -- file: spi_master.vhd
-- description: SPI master interface
-- date: 03/2018
-- author: Sergio Johann Filho <[email protected]>
--
-- This is a simple SPI master interface that works in SPI MODE 0.
-- Chip select logic is not included in this design and should be
-- implemented externally.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity spi_master is
generic (
BYTE_SIZE: integer := 8
);
port ( -- core interface
clk_i: in std_logic;
rst_i: in std_logic;
data_i: in std_logic_vector(BYTE_SIZE-1 downto 0); -- parallel data in (clocked on rising spi_clk after last bit)
data_o: out std_logic_vector(BYTE_SIZE-1 downto 0); -- parallel data output (clocked on rising spi_clk after last bit)
data_valid_o: out std_logic; -- data valid (read / write finished)
wren_i: in std_logic; -- data write enable, starts transmission when interface is idle
-- SPI interface
spi_clk_o: out std_logic; -- spi bus sck
spi_mosi_o: out std_logic; -- spi bus mosi output
spi_miso_i: in std_logic -- spi bus miso input
);
end spi_master;
architecture spi_master_arch of spi_master is
type states is (idle, data1, clock1, data2, clock2, done);
signal state: states;
signal data_reg: std_logic_vector(BYTE_SIZE-1 downto 0);
signal counter: std_logic_vector(BYTE_SIZE-1 downto 0);
begin
process(clk_i, rst_i)
begin
if rst_i = '1' then
data_reg <= (others => '0');
counter <= (others => '0');
data_valid_o <= '0';
spi_clk_o <= '0';
spi_mosi_o <= '0';
elsif clk_i'event and clk_i = '1' then
case state is
when idle =>
counter <= (others => '0');
spi_clk_o <= '0';
spi_mosi_o <= '0';
data_valid_o <= '0';
data_reg <= data_i;
when data1 =>
data_valid_o <= '0';
spi_mosi_o <= data_reg(BYTE_SIZE-1);
when clock1 =>
spi_clk_o <= '1';
when data2 =>
data_reg <= data_reg(BYTE_SIZE-2 downto 0) & spi_miso_i;
when clock2 =>
spi_clk_o <= '0';
counter <= counter + 1;
when done =>
counter <= (others => '0');
data_valid_o <= '1';
spi_mosi_o <= '0';
when others => null;
end case;
end if;
end process;
data_o <= data_reg;
process(clk_i, rst_i, state, counter, wren_i)
begin
if rst_i = '1' then
state <= idle;
elsif clk_i'event and clk_i = '1' then
case state is
when idle =>
if (wren_i = '1') then
state <= data1;
end if;
when data1 =>
state <= clock1;
when clock1 =>
state <= data2;
when data2 =>
state <= clock2;
when clock2 =>
if (counter < BYTE_SIZE-1) then
state <= data1;
else
state <= done;
end if;
when done =>
if (wren_i = '0') then
state <= idle;
end if;
when others => null;
end case;
end if;
end process;
end spi_master_arch;
| gpl-2.0 | a41ed6b3c28ce4ffb48a1aa91a4f1784 | 0.597447 | 2.839373 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rb_sel.vhd | 1 | 1,850 | -- $Id: rb_sel.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_sel - syn
-- Description: rbus: address select logic
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 4.1 streamline code
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
-- 2010-12-26 349 1.0 Initial version (cloned from ibus/ib_sel)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sel is -- rbus address select logic
generic (
RB_ADDR : slv16; -- rbus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- ibus request
SEL : out slbit -- select state bit
);
end rb_sel;
architecture syn of rb_sel is
signal R_SEL : slbit := '0';
begin
assert SAWIDTH<=15 -- at most 32k word devices
report "assert(SAWIDTH<=15)" severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RB_MREQ.aval='1' and
RB_MREQ.addr(15 downto SAWIDTH)=RB_ADDR(15 downto SAWIDTH) then
R_SEL <= '1';
else
R_SEL <= '0';
end if;
end if;
end process proc_regs;
SEL <= R_SEL;
end syn;
| gpl-3.0 | 8c25384795c6a3b25916d4e27f4c6e50 | 0.502162 | 3.714859 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/spi_sram_controller/spi_sram_ctrl_tb.vhd | 1 | 1,411 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
entity tb is
end tb;
architecture tb of tb is
signal clock, reset, burst, bmode, hmode, wr, rd, data_ack, stall, spi_cs, spi_clk, spi_mosi, spi_miso, hold_n: std_logic := '0';
signal addr_in: std_logic_vector(23 downto 0);
signal data_in, data_out: std_logic_vector(31 downto 0);
begin
reset <= '0', '1' after 5 ns, '0' after 500 ns;
process --25Mhz system clock
begin
clock <= not clock;
wait for 20 ns;
clock <= not clock;
wait for 20 ns;
end process;
wr <= '0', '1' after 1000 ns, '0' after 1100 ns;
rd <= '0', '1' after 15000 ns, '0' after 15200 ns;
addr_in <= x"001000";
data_in <= x"aa556699";
burst <= '0';
bmode <= '0';
hmode <= '0';
hold_n <= '1';
sram_ctrl_core: entity work.spi_sram_ctrl
port map( clk_i => clock,
rst_i => reset,
addr_i => addr_in,
data_i => data_in,
data_o => data_out,
burst_i => burst,
bmode_i => bmode,
hmode_i => hmode,
wr_i => wr,
rd_i => rd,
data_ack_o => data_ack,
cpu_stall_o => stall,
spi_cs_n_o => spi_cs,
spi_clk_o => spi_clk,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso
);
spi_sram: entity work.M23LC1024
port map( SI_SIO0 => spi_mosi,
SO_SIO1 => spi_miso,
SCK => spi_clk,
CS_N => spi_cs,
SIO2 => open,
HOLD_N_SIO3 => hold_n,
RESET => reset
);
end tb;
| gpl-2.0 | 796abdd63dcafbb62e9ed86591d54b7f | 0.593905 | 2.424399 | false | false | false | false |
rongcuid/lots-of-subleq-cpus | Subleq Pipelined/src/regfile.vhd | 1 | 5,117 | ----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date:
-- Design Name:
-- Module Name: RegFile
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- This is a register file with generic width and depth.
-- The default depth is 16, which is the numver of architectural
-- registers in the Pipelined Subleq machine.
-- This register file has internal forwarding, one write port and
-- two read ports. It is also implemented using BRAM
entity RegFile is
generic ( WIDTH : integer := 64;
DEPTH : integer := 32;
DEPTH_LOG : integer := 5
);
port (
clk : in std_logic;
resetb : in std_logic;
en : in std_logic;
-- Read rs
rs_a : in std_logic_vector(DEPTH_LOG-1 downto 0);
rs_d : out std_logic_vector(WIDTH-1 downto 0);
-- Read rt
rt_a : in std_logic_vector(DEPTH_LOG-1 downto 0);
rt_d : out std_logic_vector(WIDTH-1 downto 0);
-- Write back
wb_we : in std_logic;
wb_a : in std_logic_vector(DEPTH_LOG-1 downto 0);
wb_d : in std_logic_vector(WIDTH-1 downto 0)
);
end entity RegFile;
architecture syn of RegFile is
component BRAM_DP
generic ( WIDTH : integer := 32;
DEPTH : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
awe : in std_logic;
aen : in std_logic;
aaddr : in std_logic_vector(DEPTH_LOG-1 downto 0);
adi : in std_logic_vector(WIDTH-1 downto 0);
ado : out std_logic_vector(WIDTH-1 downto 0);
bwe : in std_logic;
ben : in std_logic;
baddr : in std_logic_vector(DEPTH_LOG-1 downto 0);
bdi : in std_logic_vector(WIDTH-1 downto 0);
bdo : out std_logic_vector(WIDTH-1 downto 0)
);
end component BRAM_DP;
-- Raw signals from BRAM
signal rs_do, rs_d0, rs_df,
rt_do, rt_d0, rt_df,
wb_do : std_logic_vector(WIDTH-1 downto 0);
signal s2_rs_a, s2_rt_a : std_logic_vector(DEPTH_LOG-1 downto 0);
signal forward1_rs, forward1_rt : std_logic;
signal forward2_rs, forward2_rt : std_logic;
signal zero_rs, zero_rt : std_logic;
constant ZERO : std_logic_vector(DEPTH_LOG-1 downto 0) := (others => '0');
begin
-- The BRAMs have two ports: Port A for reading, and Port B
-- for mirroring data.
RS_RAM : BRAM_DP
generic map (WIDTH=>WIDTH,DEPTH=>DEPTH,DEPTH_LOG=>DEPTH_LOG)
port map (
clk => clk,
awe => '0',
aen => en,
aaddr => rs_a,
adi => (others => '-'),
ado => rs_do,
bwe => wb_we,
ben => en,
baddr => wb_a,
bdi => wb_d,
bdo => wb_do
);
RT_RAM : BRAM_DP
generic map (WIDTH=>WIDTH,DEPTH=>DEPTH,DEPTH_LOG=>DEPTH_LOG)
port map (
clk => clk,
awe => '0',
aen => en,
aaddr => rt_a,
adi => (others => '-'),
ado => rt_do,
bwe => wb_we,
ben => en,
baddr => wb_a,
bdi => wb_d,
bdo => open
);
-- Pipelined forwarding, so:
-- | Input Reg | SRAM
-- Keep a copy of wb_d and give it out if necessary
-- Pipelined zero:
-- If $0 is requested, then 0 will be read on the next clock
Forward_Zero : process (clk, resetb)
begin
if (resetb = '0') then
forward1_rs <= '0';
forward1_rt <= '0';
zero_rs <= '0';
zero_rt <= '0';
elsif (clk'event and clk = '1') then
-- Save the previous addresses
s2_rs_a <= rs_a;
s2_rt_a <= rt_a;
-- If any reads share address with write back,
-- writeback value will be selected
rs_forward : if (wb_we = '1' and rs_a = wb_a) then
forward1_rs <= '1';
elsif (forward1_rs = '1') then
forward1_rs <= '0';
end if rs_forward;
rt_forward : if (wb_we = '1' and rt_a = wb_a) then
forward1_rt <= '1';
elsif (forward1_rt = '1') then
forward1_rt <= '0';
end if rt_forward;
-- Return 0 for $0
rs_zero : if (rs_a = ZERO) then
zero_rs <= '1';
elsif (zero_rs = '1') then
zero_rs <= '0';
end if rs_zero;
rt_zero : if (rt_a = ZERO) then
zero_rt <= '1';
elsif (zero_rt = '1') then
zero_rt <= '0';
end if rt_zero;
end if;
end process Forward_Zero;
-- Muxes to choose from keep register/memory ports
rs_df <= wb_do when forward1_rs = '1' else rs_do;
rt_df <= wb_do when forward1_rt = '1' else rt_do;
rs_d0 <= wb_do when s2_rs_a = wb_a else rs_do;
rt_d0 <= wb_do when s2_rt_a = wb_a else rt_do;
-- Note that $0 always read 0
rs_d <= (others => '0') when zero_rs = '1' else rs_d0;
rt_d <= (others => '0') when zero_rt = '1' else rt_d0;
end architecture syn;
| gpl-3.0 | f4ec90b8066ed2099c4d248b8a761ebe | 0.554036 | 3.318418 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys2/tb/tb_nexys2.vhd | 1 | 6,218 | -- $Id: tb_nexys2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2 - sim
-- Description: Test bench for nexys2 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/dcm_sfs
-- tb_nexys2_core
-- nexys2_aif [UUT]
-- serport/tb/serport_master_tb
--
-- To test: generic, any nexys2_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.2 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.0.2 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.0.1 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.3 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.2 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0.1 use serport_uart_rxtx
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2 is
end tb_nexys2;
architecture sim of tb_nexys2 is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
| gpl-3.0 | 92bf4675328785b2c051492c84e778a5 | 0.532326 | 2.996627 | false | false | false | false |
sjohann81/hf-risc | devices/controllers/xtea/xtea_tb.vhd | 1 | 852 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
entity tb is
end tb;
architecture tb of tb is
signal clock, reset, start, encrypt, ready: std_logic := '0';
signal key: std_logic_vector(127 downto 0);
signal input, output: std_logic_vector(63 downto 0);
begin
reset <= '0', '1' after 5 ns, '0' after 500 ns;
process --25Mhz system clock
begin
clock <= not clock;
wait for 20 ns;
clock <= not clock;
wait for 20 ns;
end process;
start <= '0', '1' after 1000 ns;
encrypt <= '1';
key <= x"f0e1d2c3b4a5968778695a4b3c2d1e0f";
input <= x"1234567890123456";
-- XTEA core
core: entity work.xtea
port map( clock => clock,
reset => reset,
start => start,
encrypt => encrypt,
key => key,
input => input,
output => output,
ready => ready
);
end tb;
| gpl-2.0 | a7002c98406585760e4a934337a9e7e1 | 0.650235 | 2.722045 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_bram_memctl.vhd | 1 | 6,520 | -- $Id: pdp11_bram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_bram_memctl - syn
-- Description: pdp11: BRAM based memctl
--
-- Dependencies: ram_1swsr_wfirst_gen
-- Test bench: -
-- Target Devices: 7-Series
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2016-03-20 749 1.1 use ram_1swsr_wfirst_gen rather BRAM_SINGLE_MACRO
-- 2015-02-08 644 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_bram_memctl is -- BRAM based memctl
generic (
MAWIDTH : positive := 4; -- mux address width
NBLOCK : positive := 11); -- number of 16 kByte blocks
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32 -- data out (memory view)
);
end pdp11_bram_memctl;
architecture syn of pdp11_bram_memctl is
type state_type is (
s_idle, -- s_idle: wait for req
s_read0, -- s_read0
s_read1, -- s_read1
s_write -- s_write
);
type regs_type is record
state : state_type; -- state
muxaddr : slv(MAWIDTH-1 downto 0); -- mux addr buffer
celladdr : slv12; -- cell addr buffer
cellen : slv(2**MAWIDTH-1 downto 0);-- cell enables
cellwe : slv4; -- write enables
dibuf : slv32; -- data in buffer
dobuf : slv32; -- data out buffer
ackr : slbit; -- signal ack_r
end record regs_type;
constant muxaddrzero : slv(MAWIDTH-1 downto 0) := (others=>'0');
constant cellenzero : slv(2**MAWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
muxaddrzero, -- muxaddr
(others=>'0'), -- celladdr
cellenzero, -- cellen
(others=>'0'), -- cellwe
(others=>'0'), -- dibuf
(others=>'0'), -- dobuf
'0' -- ackr
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
type mem_do_type is array (NBLOCK-1 downto 0) of slv32;
signal MEM_DO : mem_do_type := (others=> (others => '0'));
begin
assert MAWIDTH <= 8
report "assert(MAWIDTH <= 8)" severity failure;
assert NBLOCK <= 2**MAWIDTH
report "assert(NBLOCK <= 2**MAWIDTH)" severity failure;
-- generate memory array
-- 4 colums, one for each byte of the 32 bit word
-- NBLOCK rows, as many as one can afford ...
MARRAY: for row in NBLOCK-1 downto 0 generate
MROW: for col in 3 downto 0 generate
begin
MCELL : ram_1swsr_wfirst_gen
generic map (
AWIDTH => 12, -- 4 Kb blocks
DWIDTH => 8) -- byte wide
port map (
CLK => CLK,
EN => R_REGS.cellen(row),
WE => R_REGS.cellwe(col),
ADDR => R_REGS.celladdr,
DI => R_REGS.dibuf(8*col+7 downto 8*col),
DO => MEM_DO(row)(8*col+7 downto 8*col)
);
end generate MROW;
end generate MARRAY;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ADDR, DI, REQ, WE, BE, MEM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibusy : slbit := '0';
variable iackw : slbit := '0';
variable iactr : slbit := '0';
variable iactw : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
n.ackr := '0';
ibusy := '0';
iackw := '0';
iactr := '0';
iactw := '0';
case r.state is
when s_idle => -- s_idle: wait for req
n.cellen := (others=>'0');
n.cellwe := (others=>'0');
if REQ = '1' then
n.muxaddr := ADDR(MAWIDTH-1+12 downto 12);
n.celladdr := ADDR(11 downto 0);
n.dibuf := DI;
n.cellen(to_integer(unsigned(ADDR(MAWIDTH-1+12 downto 12)))) := '1';
if WE = '1' then
n.cellwe := BE;
n.state := s_write;
else
n.state := s_read0;
end if;
end if;
when s_read0 => -- s_read0
ibusy := '1';
iactr := '1';
n.state := s_read1;
when s_read1 => -- s_read1
ibusy := '1';
iactr := '1';
n.dobuf := MEM_DO(to_integer(unsigned(r.muxaddr)));
n.ackr := '1';
n.state := s_idle;
when s_write => -- s_write
ibusy := '1';
iactw := '1';
iackw := '1';
n.cellwe := (others=>'0');
n.state := s_idle;
when others => null;
end case;
N_REGS <= n;
BUSY <= ibusy;
ACK_R <= r.ackr;
ACK_W <= iackw;
ACT_R <= iactr;
ACT_W <= iactw;
DO <= r.dobuf;
end process proc_next;
end syn;
| gpl-3.0 | 203fd6c8c421035076405f6270766efc | 0.46227 | 3.760092 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_sequencer.vhd | 1 | 122,141 | -- $Id: pdp11_sequencer.vhd 1321 2022-11-24 15:06:47Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sequencer - syn
-- Description: pdp11: CPU sequencer
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-11-24 1321 1.6.20 BUGFIX: correct mmu trap handing in s_idecode
-- 2022-11-21 1320 1.6.19 rename some rsv->ser and cpustat_type trap_->treq_;
-- remove vm_cntl_type.trap_done;
-- BUGFIX: correct ysv flow implementation
-- 2022-11-18 1316 1.6.18 BUGFIX: use is_kstackdst1246 also in dstr flow
-- 2022-10-29 1312 1.6.17 rename s_int_* -> s_vec_*, s_trap_* -> s_abort_*
-- 2022-10-25 1309 1.6.16 rename _gpr -> _gr
-- 2022-10-03 1301 1.6.15 finalize fix for I space mode=1 in s_dstr_def
-- 2022-09-08 1296 1.6.14 BUGFIX: use I space for all mode=1,2,3 if reg=pc
-- 2022-08-13 1279 1.6.13 ssr->mmr rename
-- 2019-08-17 1203 1.6.12 fix for ghdl V0.36 -Whide warnings
-- 2018-10-07 1054 1.6.11 drop ITIMER, use DM_STAT_SE.itimer
-- 2018-10-06 1053 1.6.10 add DM_STAT_SE.(cpbusy,idec,pcload)
-- 2017-04-23 885 1.6.9 not sys_conf_dmscnt: set SNUM from state category;
-- change waitsusp logic; add WAIT to idm_idone
-- 2016-12-27 831 1.6.8 CPUERR now cleared with creset
-- 2016-10-03 812 1.6.7 always define DM_STAT_SE.snum
-- 2016-05-26 768 1.6.6 don't init N_REGS (vivado fix for fsm inference)
-- proc_snum conditional (vivado fsm workaround)
-- 2015-08-02 708 1.6.5 BUGFIX: proper trap_mmu and trap_ysv handling
-- 2015-08-01 707 1.6.4 set dm_idone in s_(trap_10|op_trap); add dm_vfetch
-- 2015-07-19 702 1.6.3 add DM_STAT_SE, drop SNUM port
-- 2015-07-10 700 1.6.2 use c_cpurust_hbpt
-- 2015-06-26 695 1.6.1 add SNUM (state number) port
-- 2015-05-10 678 1.6 start/stop/suspend overhaul; reset overhaul
-- 2015-02-07 643 1.5.2 s_op_wait: load R0 in DSRC for DR emulation
-- 2014-07-12 569 1.5.1 rename s_opg_div_zero -> s_opg_div_quit;
-- use DP_STAT.div_quit; set munit_s_div_sr;
-- BUGFIX: s_opg_div_sr: check for late div_quit
-- 2014-04-20 554 1.5 now vivado compatible (add dummy assigns in procs)
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
-- 2010-06-20 307 1.3.1 rename cpacc to cacc in vm_cntl_type
-- 2010-06-13 305 1.3 remove CPDIN_WE, CPDOUT_WE out ports; set
-- CNTL.cpdout_we instead of CPDOUT_WE
-- 2010-06-12 304 1.2.8 signal cpuwait when spinning in s_op_wait
-- 2009-05-30 220 1.2.7 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.2.6 BUGFIX: use is_kstackdst1246, stklim for mode=6
-- 2009-05-02 211 1.2.5 BUGFIX: 11/70 spl semantics again in kernel mode
-- 2009-04-26 209 1.2.4 BUGFIX: give interrupts priority over trap handling
-- 2008-12-14 177 1.2.3 BUGFIX: use is_dstkstack124, fix stklim check bug
-- 2008-12-13 176 1.2.2 BUGFIX: use is_pci in s_dstw_inc if DSTDEF='1'
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc; prevent stale DSRC
-- 2008-08-22 161 1.2 rename ubf_ -> ibf_; use iblib
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust; cp reset sets now
-- c_cpurust_reset; proper c_cpurust_vfail handling
-- 2008-04-27 140 1.1.8 BUGFIX: halt cpu in case of a vector fetch error
-- use cpursta to encode why cpu halts, remove cpufail
-- 2008-04-27 139 1.1.7 BUGFIX: correct bytop handling for address fetches;
-- BUGFIX: redo mtp flow; add fork_dsta fork and ddst
-- reload in s_opa_mtp_pop_w;
-- 2008-04-19 137 1.1.6 BUGFIX: fix loop state in s_rti_getpc_w
-- 2008-03-30 131 1.1.5 BUGFIX: inc/dec by 2 for byte mode -(sp),(sp)+
-- inc/dec by 2 for @(R)+ and @-(R) also for bytop's
-- 2008-03-02 121 1.1.4 remove snoopers; add waitsusp, redo WAIT handling
-- 2008-02-24 119 1.1.3 add lah,rps,wps command; revamp cp memory access
-- change WAIT logic, now also bails out on cp command
-- 2008-01-20 112 1.1.2 rename PRESET->BRESET
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_sequencer is -- CPU sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
INT_ACK : out slbit; -- interrupt acknowledge
CRESET : out slbit; -- cpu reset
BRESET : out slbit; -- bus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
HBPT : in slbit; -- hardware bpt
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_SE : out dm_stat_se_type -- debug and monitor status - sequencer
);
end pdp11_sequencer;
architecture syn of pdp11_sequencer is
constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16));
constant cpuerr_ibf_illhlt : integer := 7;
constant cpuerr_ibf_adderr : integer := 6;
constant cpuerr_ibf_nxm : integer := 5;
constant cpuerr_ibf_iobto : integer := 4;
constant cpuerr_ibf_ysv : integer := 3;
constant cpuerr_ibf_rsv : integer := 2;
type state_type is (
s_idle,
s_cp_regread,
s_cp_rps,
s_cp_memr_w,
s_cp_memw_w,
s_ifetch,
s_ifetch_w,
s_idecode,
s_srcr_def,
s_srcr_def_w,
s_srcr_inc,
s_srcr_inc_w,
s_srcr_dec,
s_srcr_dec1,
s_srcr_ind,
s_srcr_ind1_w,
s_srcr_ind2,
s_srcr_ind2_w,
s_dstr_def,
s_dstr_def_w,
s_dstr_inc,
s_dstr_inc_w,
s_dstr_dec,
s_dstr_dec1,
s_dstr_ind,
s_dstr_ind1_w,
s_dstr_ind2,
s_dstr_ind2_w,
s_dstw_def,
s_dstw_def_w,
s_dstw_inc,
s_dstw_inc_w,
s_dstw_incdef_w,
s_dstw_dec,
s_dstw_dec1,
s_dstw_ind,
s_dstw_ind_w,
s_dstw_def246,
s_dsta_inc,
s_dsta_incdef_w,
s_dsta_dec,
s_dsta_dec1,
s_dsta_ind,
s_dsta_ind_w,
s_op_halt,
s_op_wait,
s_op_trap,
s_op_reset,
s_op_rts,
s_op_rts_pop,
s_op_rts_pop_w,
s_op_spl,
s_op_mcc,
s_op_br,
s_op_mark,
s_op_mark1,
s_op_mark_pop,
s_op_mark_pop_w,
s_op_sob,
s_op_sob1,
s_opg_gen,
s_opg_gen_rmw_w,
s_opg_mul,
s_opg_mul1,
s_opg_div,
s_opg_div_cn,
s_opg_div_cr,
s_opg_div_sq,
s_opg_div_sr,
s_opg_div_quit,
s_opg_ash,
s_opg_ash_cn,
s_opg_ashc,
s_opg_ashc_cn,
s_opg_ashc_wl,
s_opa_jsr,
s_opa_jsr1,
s_opa_jsr_push,
s_opa_jsr_push_w,
s_opa_jsr2,
s_opa_jmp,
s_opa_mtp,
s_opa_mtp_pop_w,
s_opa_mtp_reg,
s_opa_mtp_mem,
s_opa_mtp_mem_w,
s_opa_mfp_reg,
s_opa_mfp_mem,
s_opa_mfp_mem_w,
s_opa_mfp_dec,
s_opa_mfp_push,
s_opa_mfp_push_w,
s_abort_4,
s_abort_10,
s_trap_disp,
s_int_ext,
s_vec_getpc,
s_vec_getpc_w,
s_vec_getps,
s_vec_getps_w,
s_vec_getsp,
s_vec_decsp,
s_vec_pushps,
s_vec_pushps_w,
s_vec_pushpc,
s_vec_pushpc_w,
s_rti_getpc,
s_rti_getpc_w,
s_rti_getps,
s_rti_getps_w,
s_rti_newpc,
s_vmerr,
s_cpufail
);
signal R_STATE : state_type := s_idle;-- state register
signal N_STATE : state_type; -- don't init (vivado fix for fsm infer)
attribute fsm_encoding : string;
attribute fsm_encoding of R_STATE : signal is "one_hot";
signal R_STATUS : cpustat_type := cpustat_init;
signal N_STATUS : cpustat_type := cpustat_init;
signal R_CPUERR : cpuerr_type := cpuerr_init;
signal N_CPUERR : cpuerr_type := cpuerr_init;
signal R_IDSTAT : decode_stat_type := decode_stat_init;
signal N_IDSTAT : decode_stat_type := decode_stat_init;
signal R_VMSTAT : vm_stat_type := vm_stat_init;
signal IBSEL_CPUERR : slbit := '0';
signal VM_CNTL_L : vm_cntl_type := vm_cntl_init;
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_cpuerr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_CPUERR
);
proc_ibres : process (IBSEL_CPUERR, IB_MREQ, R_CPUERR)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_CPUERR = '1' then
idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
idout(cpuerr_ibf_adderr) := R_CPUERR.adderr;
idout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
idout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
idout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
idout(cpuerr_ibf_rsv) := R_CPUERR.rsv;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_CPUERR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_status: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_STATUS <= cpustat_init;
R_IDSTAT <= decode_stat_init;
R_VMSTAT <= vm_stat_init;
else
R_STATUS <= N_STATUS;
R_IDSTAT <= N_IDSTAT;
R_VMSTAT <= VM_STAT;
end if;
end if;
end process proc_status;
-- ensure that CPUERR is reset with GRESET and CRESET
proc_cpuerr: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' or R_STATUS.creset = '1' then
R_CPUERR <= cpuerr_init;
else
R_CPUERR <= N_CPUERR;
end if;
end if;
end process proc_cpuerr;
proc_state: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_STATE <= s_idle;
else
R_STATE <= N_STATE;
end if;
end if;
end process proc_state;
proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL,
ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT,
R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR,
INT_PRI, INT_VECT, ESUSP_I, HBPT)
variable nstate : state_type;
variable nstatus : cpustat_type := cpustat_init;
variable ncpuerr : cpuerr_type := cpuerr_init;
variable ndpcntl : dpath_cntl_type := dpath_cntl_init;
variable nvmcntl : vm_cntl_type := vm_cntl_init;
variable nidstat : decode_stat_type := decode_stat_init;
variable nmmumoni : mmu_moni_type := mmu_moni_init;
variable imemok : boolean;
variable bytop : slbit := '0'; -- local bytop access flag
variable macc : slbit := '0'; -- local modify access flag
variable lvector : slv9_2 := (others=>'0'); -- local trap/interrupt vector
variable brcode : slv4 := (others=>'0'); -- reduced br opcode (15,10-8)
variable brcond : slbit := '0'; -- br condition value
variable is_kmode : slbit := '0'; -- cmode is kernel mode
variable is_kstackdst1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6
variable int_pending : slbit := '0'; -- an interrupt is pending
variable idm_idle : slbit := '0'; -- idle for dm_stat_se
variable idm_cpbusy : slbit := '0'; -- cpbusy for dm_stat_se
variable idm_idec : slbit := '0'; -- idec for dm_stat_se
variable idm_idone : slbit := '0'; -- idone for dm_stat_se
variable idm_pcload : slbit := '0'; -- pcload for dm_stat_se
variable idm_vfetch : slbit := '0'; -- vfetch for dm_stat_se
alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
alias SRCDEF : slbit is IREG(9); -- src register mode defered
alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
alias DSTDEF : slbit is IREG(3); -- dst register mode defered
alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
procedure do_memread_i(pnstate : inout state_type;
pndpcntl : inout dpath_cntl_type;
pnvmcntl : inout vm_cntl_type;
pwstate : in state_type) is
begin
pndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
pnvmcntl.dspace := '0';
pnvmcntl.req := '1';
pndpcntl.gr_pcinc := '1'; -- (pc)++
pnstate := pwstate;
end procedure do_memread_i;
procedure do_memread_d(pnstate : inout state_type;
pnvmcntl : inout vm_cntl_type;
pwstate : in state_type;
pbytop : in slbit := '0';
pmacc : in slbit := '0';
pispace : in slbit := '0';
kstack : in slbit := '0') is
begin
pnvmcntl.dspace := not pispace;
-- bytop := R_IDSTAT.is_bytop and not is_addr;
pnvmcntl.bytop := pbytop;
pnvmcntl.macc := pmacc;
pnvmcntl.kstack := kstack;
pnvmcntl.req := '1';
pnstate := pwstate;
end procedure do_memread_d;
procedure do_memread_srcinc(pnstate : inout state_type;
pndpcntl : inout dpath_cntl_type;
pnvmcntl : inout vm_cntl_type;
pwstate : in state_type;
pnmmumoni : inout mmu_moni_type;
pupdt_sp : in slbit := '0') is
begin
pndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
pndpcntl.ounit_const := "000000010"; -- OUNIT const=2
pndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
pndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
pndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
pndpcntl.dsrc_we := '1'; -- update DSRC
if pupdt_sp = '1' then
pnmmumoni.regmod := '1';
pnmmumoni.isdec := '0';
pndpcntl.gr_adst := c_gr_sp; -- update SP too
pndpcntl.gr_we := '1';
end if;
pndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
pnvmcntl.dspace := '1';
pnvmcntl.req := '1';
pnstate := pwstate;
end procedure do_memread_srcinc;
procedure do_memwrite(pnstate : inout state_type;
pnvmcntl : inout vm_cntl_type;
pwstate : in state_type;
pmacc : in slbit :='0';
pispace : in slbit := '0') is
begin
pnvmcntl.dspace := not pispace;
pnvmcntl.bytop := R_IDSTAT.is_bytop;
pnvmcntl.wacc := '1';
pnvmcntl.macc := pmacc;
pnvmcntl.req := '1';
pnstate := pwstate;
end procedure do_memwrite;
procedure do_memcheck(pnstate : inout state_type;
pnstatus : inout cpustat_type;
pmok : out boolean) is
begin
pnstate := pnstate; -- dummy to add driver (vivado)
pnstatus := pnstatus; -- "
pmok := false;
if VM_STAT.ack = '1' then
pmok := true;
if VM_STAT.trap_mmu = '1' then -- remember trap_mmu, may happen on any
pnstatus.treq_mmu := '1'; -- memory access of an instruction
end if;
if VM_STAT.trap_ysv = '1' then -- remember trap_ysv (on final writes)
if R_STATUS.in_vecysv = '0' then -- trap when not in ysv vector flow
pnstatus.treq_ysv := '1';
end if;
end if;
elsif VM_STAT.err='1' or VM_STAT.fail='1' then
pnstate := s_vmerr;
end if;
end procedure do_memcheck;
procedure do_const_opsize(pndpcntl : inout dpath_cntl_type;
pbytop : in slbit;
pisdef : in slbit;
pregnum : in slv3) is
begin
pndpcntl := pndpcntl; -- dummy to add driver (vivado)
if pbytop='0' or pisdef='1' or
pregnum=c_gr_pc or pregnum=c_gr_sp then
pndpcntl.ounit_const := "000000010";
else
pndpcntl.ounit_const := "000000001";
end if;
end procedure do_const_opsize;
procedure do_fork_dstr(pnstate : inout state_type;
pidstat : in decode_stat_type) is
begin
case pidstat.fork_dstr is
when c_fork_dstr_def => pnstate := s_dstr_def;
when c_fork_dstr_inc => pnstate := s_dstr_inc;
when c_fork_dstr_dec => pnstate := s_dstr_dec;
when c_fork_dstr_ind => pnstate := s_dstr_ind;
when others => pnstate := s_cpufail;
end case;
end procedure do_fork_dstr;
procedure do_fork_opg(pnstate : inout state_type;
pidstat : in decode_stat_type) is
begin
case pidstat.fork_opg is
when c_fork_opg_gen => pnstate := s_opg_gen;
when c_fork_opg_wdef => pnstate := s_dstw_def;
when c_fork_opg_winc => pnstate := s_dstw_inc;
when c_fork_opg_wdec => pnstate := s_dstw_dec;
when c_fork_opg_wind => pnstate := s_dstw_ind;
when c_fork_opg_mul => pnstate := s_opg_mul;
when c_fork_opg_div => pnstate := s_opg_div;
when c_fork_opg_ash => pnstate := s_opg_ash;
when c_fork_opg_ashc => pnstate := s_opg_ashc;
when others => pnstate := s_cpufail;
end case;
end procedure do_fork_opg;
procedure do_fork_opa(pnstate : inout state_type;
pidstat : in decode_stat_type) is
begin
case pidstat.fork_opa is
when c_fork_opa_jmp => pnstate := s_opa_jmp;
when c_fork_opa_jsr => pnstate := s_opa_jsr;
when c_fork_opa_mtp => pnstate := s_opa_mtp_mem;
when c_fork_opa_mfp_reg => pnstate := s_opa_mfp_reg;
when c_fork_opa_mfp_mem => pnstate := s_opa_mfp_mem;
when others => pnstate := s_cpufail;
end case;
end procedure do_fork_opa;
procedure do_fork_next(pnstate : inout state_type;
pnstatus : inout cpustat_type;
pnmmumoni : inout mmu_moni_type) is
begin
pnmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
pnstate := s_idle;
elsif R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or
R_STATUS.treq_ysv='1' or pnstatus.treq_ysv='1' or
PSW.tflag='1' then
pnstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and -- running
R_STATUS.cpususp='0' and -- and not suspended
not R_STATUS.cmdbusy='1' then -- and no cmd pending
pnstate := s_ifetch; -- fetch next
else
pnstate := s_idle; -- otherwise idle
end if;
end procedure do_fork_next;
procedure do_fork_next_pref(pnstate : inout state_type;
pnstatus : inout cpustat_type;
pndpcntl : inout dpath_cntl_type;
pnvmcntl : inout vm_cntl_type;
pnmmumoni : inout mmu_moni_type) is
begin
pndpcntl := pndpcntl; -- dummy to add driver (vivado)
pnvmcntl := pnvmcntl; -- "
pnmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
pnstate := s_idle;
elsif R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or
R_STATUS.treq_ysv='1' or pnstatus.treq_ysv='1' or
PSW.tflag='1' then
pnstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and -- running
R_STATUS.cpususp='0' and -- and not suspended
not R_STATUS.cmdbusy='1' then -- and no cmd pending
pnvmcntl.req := '1'; -- read next instruction
pndpcntl.gr_pcinc := '1' ; -- inc PC
pnmmumoni.istart := '1'; -- signal istart to MMU
pnstate := s_ifetch_w; -- next: wait for fetched instruction
else
pnstate := s_idle; -- otherwise idle
end if;
end procedure do_fork_next_pref;
procedure do_start_vec(pnstate : inout state_type;
pndpcntl : inout dpath_cntl_type;
pvector : in slv9_2) is
begin
pndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
pndpcntl.dtmp_we := '1';
pndpcntl.ounit_azero := '1'; -- OUNIT A = 0
pndpcntl.ounit_const := pvector & "00"; -- vector
pndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(vector)
pndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
pndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
pndpcntl.dsrc_we := '1'; -- DSRC = vector
pnstate := s_vec_getpc;
end procedure do_start_vec;
begin
nstate := R_STATE;
nstatus := R_STATUS;
ncpuerr := R_CPUERR;
nstatus.cpuwait := '0'; -- wait flag 0 unless set in s_op_wait
-- itimer pulse logic:
-- if neither running nor suspended --> free run, set itimer = 1
-- otherwise clear to ensure single cycle pulses generated by
-- s_idecode or s_op_wait
if R_STATUS.cpugo='0' and R_STATUS.cpususp='0' then
nstatus.itimer := '1';
else
nstatus.itimer := '0';
end if;
nstatus.creset := '0'; -- ensure single cycle pulse
nstatus.breset := '0'; -- dito
nstatus.intack := '0'; -- dito
nidstat := R_IDSTAT;
if IBSEL_CPUERR='1' and IB_MREQ.we='1' then -- write to CPUERR clears it !
ncpuerr := cpuerr_init;
end if;
int_pending := '0';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
int_pending := '1';
end if;
nstatus.intpend := int_pending;
idm_idle := '0';
idm_cpbusy := '0';
idm_idec := '0';
idm_idone := '0';
idm_pcload := '0';
idm_vfetch := '0';
imemok := false;
nmmumoni := mmu_moni_init;
nmmumoni.pc := PC;
macc := '0';
bytop := '0';
brcode := IREG(15) & IREG(10 downto 8);
brcond := '1';
is_kmode := '0';
is_kstackdst1246 := '0';
if PSW.cmode = c_psw_kmode then
is_kmode := '1';
if DSTREG = c_gr_sp and
(DSTMODF="001" or DSTMODF="010" or
DSTMODF="100" or DSTMODF="110") then
is_kstackdst1246 := '1';
end if;
end if;
lvector := (others=>'0');
nvmcntl := vm_cntl_init;
nvmcntl.dspace := '1'; -- DEFAULT
nvmcntl.mode := PSW.cmode; -- DEFAULT
nvmcntl.vecser := R_STATUS.in_vecser; -- DEFAULT
ndpcntl := dpath_cntl_init;
ndpcntl.gr_asrc := SRCREG; -- DEFAULT
ndpcntl.gr_adst := DSTREG; -- DEFAULT
ndpcntl.gr_mode := PSW.cmode; -- DEFAULT
ndpcntl.gr_rset := PSW.rset; -- DEFAULT
ndpcntl.gr_we := '0'; -- DEFAULT
ndpcntl.gr_bytop := '0'; -- DEFAULT
ndpcntl.gr_pcinc := '0'; -- DEFAULT
ndpcntl.psr_ccwe := '0'; -- DEFAULT
ndpcntl.psr_we := '0'; -- DEFAULT
ndpcntl.psr_func := "000"; -- DEFAULT
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '0';
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '0';
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '0';
ndpcntl.ounit_asel := c_ounit_asel_ddst;
ndpcntl.ounit_azero := '0'; -- DEFAULT
ndpcntl.ounit_const := (others=>'0'); -- DEFAULT
ndpcntl.ounit_bsel := c_ounit_bsel_const;
ndpcntl.ounit_opsub := '0'; -- DEFAULT
ndpcntl.aunit_srcmod := R_IDSTAT.aunit_srcmod; -- STATIC
ndpcntl.aunit_dstmod := R_IDSTAT.aunit_dstmod; -- STATIC
ndpcntl.aunit_cimod := R_IDSTAT.aunit_cimod; -- STATIC
ndpcntl.aunit_cc1op := R_IDSTAT.aunit_cc1op; -- STATIC
ndpcntl.aunit_ccmode := R_IDSTAT.aunit_ccmode; -- STATIC
ndpcntl.aunit_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.lunit_func := R_IDSTAT.lunit_func; -- STATIC
ndpcntl.lunit_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.munit_func := R_IDSTAT.munit_func; -- STATIC
ndpcntl.ireg_we := '0';
ndpcntl.cres_sel := R_IDSTAT.res_sel; -- DEFAULT
ndpcntl.dres_sel := c_dpath_res_ounit;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc;
if CP_CNTL.req='1' and R_STATUS.cmdbusy='0' then
nstatus.cmdbusy := '1';
nstatus.cpfunc := CP_CNTL.func;
nstatus.cprnum := CP_CNTL.rnum;
end if;
if R_STATUS.cmdack = '1' then
nstatus.cmdack := '0';
nstatus.cmderr := '0';
nstatus.cmdmerr := '0';
end if;
case R_STATE is
-- idle and command port states ---------------------------------------------
when s_idle => -- ------------------------------------
-- Note: s_idle was entered from suspended WAIT when waitsusp='1'
-- --> all exits must check this and either return to s_op_wait
-- or abort the WAIT and set waitsusp='0'
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST (do mux early)
nstatus.cpustep := '0';
idm_idle := '1'; -- signal sequencer idle
if R_STATUS.cmdbusy = '1' then
idm_cpbusy := '1'; -- signal cp busy
case R_STATUS.cpfunc is
when c_cpfunc_noop => -- noop : no operation -------
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_start => -- start : cpu start ---------
nstatus.cmdack := '1';
if R_STATUS.cpugo = '1' then -- if already running
nstatus.cmderr := '1'; -- reject
else -- if not running
nstatus.cpugo := '1'; -- start cpu
nstatus.cpurust := c_cpurust_runs;
nstatus.waitsusp := '0';
end if;
nstate := s_idle;
when c_cpfunc_stop => -- stop : cpu stop -----------
nstatus.cmdack := '1';
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_stop;
nstatus.waitsusp := '0';
nstate := s_idle;
when c_cpfunc_step => -- step : cpu step -----------
nstatus.cmdack := '1';
nstatus.cpustep := '1';
nstatus.cpurust := c_cpurust_step;
nstatus.waitsusp := '0';
if int_pending = '1' then
nstatus.intack := '1';
nstatus.intvect := INT_VECT;
nstate := s_int_ext;
else
nstate := s_ifetch;
end if;
when c_cpfunc_creset => -- creset : cpu reset --------
nstatus.cmdack := '1';
if R_STATUS.cpugo = '1' then -- if already running
nstatus.cmderr := '1'; -- reject
else -- if not running
nstatus.creset := '1'; -- do cpu reset
nstatus.breset := '1'; -- and bus reset !
nstatus.suspint := '0'; -- clear suspend
nstatus.cpurust := c_cpurust_init;
end if;
nstate := s_idle;
when c_cpfunc_breset => -- breset : bus reset --------
nstatus.cmdack := '1';
if R_STATUS.cpugo = '1' then -- if already running
nstatus.cmderr := '1'; -- reject
else -- if not running
nstatus.breset := '1'; -- do bus reset only
end if;
nstate := s_idle;
when c_cpfunc_suspend => -- suspend : cpu suspend -----
nstatus.cmdack := '1';
nstatus.suspint := '1';
nstatus.cpurust := c_cpurust_susp;
nstate := s_idle;
when c_cpfunc_resume => -- resume : cpu resume -------
nstatus.cmdack := '1';
nstatus.suspint := '0';
if R_STATUS.cpugo = '1' then
nstatus.cpurust := c_cpurust_runs;
else
nstatus.cpurust := c_cpurust_stop;
end if;
nstate := s_idle;
when c_cpfunc_rreg => -- rreg : read register ------
ndpcntl.gr_adst := R_STATUS.cprnum;
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_cp_regread;
when c_cpfunc_wreg => -- wreg : write register -----
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.gr_adst := R_STATUS.cprnum;
ndpcntl.gr_we := '1';
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_rpsw => -- rpsw : read psw -----------
ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
ndpcntl.dtmp_we := '1';
nstate := s_cp_rps;
when c_cpfunc_wpsw => -- wpsw : write psw ----------
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.psr_func := c_psr_func_wall; -- write all fields
ndpcntl.psr_we := '1'; -- load new PS
nstatus.cmdack := '1';
nstate := s_idle;
when c_cpfunc_rmem => -- rmem : read memory --------
nvmcntl.cacc := '1';
nvmcntl.req := '1';
nstate := s_cp_memr_w;
when c_cpfunc_wmem => -- wmem : write memory -------
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
nvmcntl.wacc := '1'; -- write mem
nvmcntl.cacc := '1';
nvmcntl.req := '1';
nstate := s_cp_memw_w;
when others =>
nstatus.cmdack := '1';
nstatus.cmderr := '1';
nstate := s_idle;
end case;
elsif R_STATUS.waitsusp = '1' then
nstate := s_op_wait; --waitsusp is cleared in s_op_wait
elsif R_STATUS.cpugo = '1' and -- running
R_STATUS.cpususp='0' then -- and not suspended
if int_pending = '1' then -- interrupt pending
nstatus.intack := '1'; -- acknowledle it
nstatus.intvect := INT_VECT; -- latch vector address
nstate := s_int_ext; -- and handle
else
nstate := s_ifetch; -- otherwise fetch intruction
end if;
end if;
when s_cp_regread => -- -----------------------------------
idm_cpbusy := '1'; -- signal cp busy
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_rps => -- -----------------------------------
idm_cpbusy := '1'; -- signal cp busy
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_memr_w => -- -----------------------------------
idm_cpbusy := '1'; -- signal cp busy
nstate := s_cp_memr_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.treq_ysv := '0'; -- suppress traps on console
nstatus.treq_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
when s_cp_memw_w => -- -----------------------------------
idm_cpbusy := '1'; -- signal cp busy
nstate := s_cp_memw_w;
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.treq_ysv := '0'; -- suppress traps on console
nstatus.treq_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
-- instruction fetch and decode ---------------------------------------------
when s_ifetch => -- -----------------------------------
nmmumoni.istart := '1'; -- do here; memread_i inc PC !
do_memread_i(nstate, ndpcntl, nvmcntl, s_ifetch_w);
when s_ifetch_w => -- -----------------------------------
nstate := s_ifetch_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ireg_we := '1';
nstate := s_idecode;
end if;
when s_idecode => -- -----------------------------------
idm_idec := '1'; -- signal instruction started
nstatus.itimer := '1'; -- itimer counts each decode
nidstat := ID_STAT; -- register decode status
if ID_STAT.force_srcsp = '1' then
ndpcntl.gr_asrc := c_gr_sp;
end if;
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '1';
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nvmcntl.dspace := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
-- The prefetch decision path can be critical (and was on s3).
-- It uses R_STATUS.intpend instead of int_pending, using the status
-- latched at the previous state is OK. It uses R_STATUS.treq_mmu
-- because no MMU trap can occur during this state (only in *_w states).
-- It does not check treq_ysv because pipelined instructions can't
-- trigger ysv traps, in contrast to MMU traps.
if ID_STAT.do_pref_dec='1' and -- prefetch possible
PSW.tflag='0' and -- no tbit traps
R_STATUS.intpend='0' and -- no interrupts
R_STATUS.treq_mmu='0' and -- no MMU trap request
R_STATUS.cpugo='1' and -- CPU on go
R_STATUS.cpususp='0' and -- CPU not suspended
not R_STATUS.cmdbusy='1' -- and no command pending
then -- then go for prefetch
nvmcntl.req := '1';
ndpcntl.gr_pcinc := '1'; -- (pc)++
nmmumoni.istart := '1';
nstatus.prefdone := '1';
end if;
if ID_STAT.do_fork_op = '1' then
case ID_STAT.fork_op is
when c_fork_op_halt => nstate := s_op_halt;
when c_fork_op_wait => nstate := s_op_wait;
when c_fork_op_rtti => nstate := s_rti_getpc;
when c_fork_op_trap => nstate := s_op_trap;
when c_fork_op_reset=> nstate := s_op_reset;
when c_fork_op_rts => nstate := s_op_rts;
when c_fork_op_spl => nstate := s_op_spl;
when c_fork_op_mcc => nstate := s_op_mcc;
when c_fork_op_br => nstate := s_op_br;
when c_fork_op_mark => nstate := s_op_mark;
when c_fork_op_sob => nstate := s_op_sob;
when c_fork_op_mtp => nstate := s_opa_mtp;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_srcr = '1' then
case ID_STAT.fork_srcr is
when c_fork_srcr_def => nstate := s_srcr_def;
when c_fork_srcr_inc => nstate := s_srcr_inc;
when c_fork_srcr_dec => nstate := s_srcr_dec;
when c_fork_srcr_ind => nstate := s_srcr_ind;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, ID_STAT);
elsif ID_STAT.do_fork_dsta = '1' then
case ID_STAT.fork_dsta is -- 2nd dsta fork in s_opa_mtp_pop_w
when c_fork_dsta_def => do_fork_opa(nstate, ID_STAT);
when c_fork_dsta_inc => nstate := s_dsta_inc;
when c_fork_dsta_dec => nstate := s_dsta_dec;
when c_fork_dsta_ind => nstate := s_dsta_ind;
when others => nstate := s_cpufail;
end case;
elsif ID_STAT.do_fork_opg = '1' then
do_fork_opg(nstate, ID_STAT);
elsif ID_STAT.is_res = '1' then
nstate := s_abort_10; -- do vector 10 abort;
else
nstate := s_cpufail; -- catch mistakes here...
end if;
-- source read states -------------------------------------------------------
-- flows:
-- 1 (r) s_srcr_def req (r)
-- s_srcr_def_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 2 (r)+ s_srcr_inc req (r); r+=s
-- s_srcr_inc_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 3 @(r)+ s_srcr_inc req (r); r+=s
-- s_srcr_inc_w get (r)
-- s_srcr_def req @(r)
-- s_srcr_def_w get @(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 4 -(r) s_srcr_dec r-=s
-- s_srcr_dec1 req (r)
-- s_srcr_inc_w get (r)
-- -> do_fork_dstr or do_fork_opg
--
-- 5 @-(r) s_srcr_dec r-=s
-- s_srcr_dec1 req (r)
-- s_srcr_inc_w get (r)
-- s_srcr_def req @(r)
-- s_srcr_def_w get @(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 6 n(r) s_srcr_ind req n
-- s_srcr_ind1_w get n; ea=r+n
-- s_srcr_ind2 req n(r)
-- s_srcr_ind2_w get n(r)
-- -> do_fork_dstr or do_fork_opg
--
-- 7 @n(r) s_srcr_ind req n
-- s_srcr_ind1_w get n; ea=r+n
-- s_srcr_ind2 req n(r)
-- s_srcr_ind2_w get n(r)
-- s_srcr_def req @n(r)
-- s_srcr_def_w get @n(r)
-- -> do_fork_dstr or do_fork_opg
when s_srcr_def => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
do_memread_d(nstate, nvmcntl, s_srcr_def_w,
pbytop=>R_IDSTAT.is_bytop,
pispace=>R_IDSTAT.is_srcpcmode1);
when s_srcr_def_w => -- -----------------------------------
nstate := s_srcr_def_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
when s_srcr_inc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
if DSTREG = SRCREG then -- prevent stale DDST copy
ndpcntl.ddst_we := '1'; -- update DDST
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_inc_w,
pbytop=>bytop, pispace=>R_IDSTAT.is_srcpc);
when s_srcr_inc_w => -- -----------------------------------
nstate := s_srcr_inc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if SRCDEF = '1' then
nstate := s_srcr_def;
else
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
end if;
when s_srcr_dec => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
if DSTREG = SRCREG then -- prevent stale DDST copy
ndpcntl.ddst_we := '1'; -- update DDST
end if;
nstate := s_srcr_dec1;
when s_srcr_dec1 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_inc_w, pbytop=>bytop);
when s_srcr_ind => -- -----------------------------------
do_memread_i(nstate, ndpcntl, nvmcntl, s_srcr_ind1_w);
when s_srcr_ind1_w => -- -----------------------------------
nstate := s_srcr_ind1_w;
if R_IDSTAT.is_srcpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A = DSRC
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout; -- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.ddst_we := '1'; -- update DDST (to reload PC)
nstate := s_srcr_ind2;
end if;
when s_srcr_ind2 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
bytop := R_IDSTAT.is_bytop and not SRCDEF;
do_memread_d(nstate, nvmcntl, s_srcr_ind2_w, pbytop=>bytop);
when s_srcr_ind2_w => -- -----------------------------------
nstate := s_srcr_ind2_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
if SRCDEF = '1' then
nstate := s_srcr_def;
else
if R_IDSTAT.do_fork_dstr = '1' then
do_fork_dstr(nstate, R_IDSTAT);
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
end if;
-- destination read states --------------------------------------------------
-- flows:
-- 1 (r) s_dstr_def req (r) (rmw if rmw op)
-- s_dstr_def_w get (r)
-- -> do_fork_opg
--
-- 2 (r)+ s_dstr_inc req (r); r+=s (rmw if rmw op)
-- s_dstr_inc_w get (r)
-- -> do_fork_opg
--
-- 3 @(r)+ s_dstr_inc req (r); r+=s
-- s_dstr_inc_w get (r)
-- s_dstr_def req @(r) (rmw if rmw op)
-- s_dstr_def_w get @(r)
-- -> do_fork_opg
--
-- 4 -(r) s_dstr_dec r-=s
-- s_dstr_dec1 req (r) (rmw if rmw op)
-- s_dstr_inc_w get (r)
-- -> do_fork_opg
--
-- 5 @-(r) s_dstr_dec r-=s
-- s_dstr_dec1 req (r)
-- s_dstr_inc_w get (r)
-- s_dstr_def req @(r) (rmw if rmw op)
-- s_dstr_def_w get @(r)
-- -> do_fork_opg
--
-- 6 n(r) s_dstr_ind req n
-- s_dstr_ind1_w get n; ea=r+n
-- s_dstr_ind2 req n(r) (rmw if rmw op)
-- s_dstr_ind2_w get n(r)
-- -> do_fork_opg
--
-- 7 @n(r) s_dstr_ind req n
-- s_dstr_ind1_w get n; ea=r+n
-- s_dstr_ind2 req n(r)
-- s_dstr_ind2_w get n(r)
-- s_dstr_def req @n(r) (rmw if rmw op)
-- s_dstr_def_w get @n(r)
-- -> do_fork_opg
when s_dstr_def => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
do_memread_d(nstate, nvmcntl, s_dstr_def_w,
pbytop=>R_IDSTAT.is_bytop, pmacc=>R_IDSTAT.is_rmwop,
pispace=>R_IDSTAT.is_dstpcmode1,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_def_w => -- -----------------------------------
nstate := s_dstr_def_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
do_fork_opg(nstate, R_IDSTAT);
end if;
when s_dstr_inc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
pbytop=>bytop, pmacc=>macc, pispace=>R_IDSTAT.is_dstpc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_inc_w => -- -----------------------------------
nstate := s_dstr_inc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
if DSTDEF = '1' then
nstate := s_dstr_def;
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
when s_dstr_dec => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstr_dec1;
when s_dstr_dec1 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
pbytop=>bytop, pmacc=>macc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_ind => -- -----------------------------------
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w);
when s_dstr_ind1_w => -- -----------------------------------
nstate := s_dstr_ind1_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstr_ind2;
end if;
when s_dstr_ind2 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
macc := R_IDSTAT.is_rmwop and not DSTDEF;
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_ind2_w,
pbytop=>bytop, pmacc=>macc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_ind2_w => -- -----------------------------------
nstate := s_dstr_ind2_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
if DSTDEF = '1' then
nstate := s_dstr_def;
else
do_fork_opg(nstate, R_IDSTAT);
end if;
end if;
-- destination write states -------------------------------------------------
-- flows:
-- 1 (r) s_dstw_def wreq (r) check kstack
-- s_dstw_def_w ack (r)
-- -> do_fork_next
--
-- 2 (r)+ s_dstw_inc wreq (r) check kstack
-- s_dstw_inc_w ack (r); r+=s
-- -> do_fork_next
--
-- 3 @(r)+ s_dstw_inc rreq (r); r+=s
-- s_dstw_incdef_w get (r)
-- s_dstw_def246 wreq @(r)
-- s_dstw_def_w ack @(r)
-- -> do_fork_next
--
-- 4 -(r) s_dstw_dec r-=s
-- s_dstw_dec1 wreq (r) check kstack
-- s_dstw_def_w ack (r)
-- -> do_fork_next
--
-- 5 @-(r) s_dstw_dec r-=s
-- s_dstw_dec1 rreq (r)
-- s_dstw_incdef_w get (r)
-- s_dstw_def246 wreq @(r)
-- s_dstw_def_w ack @(r)
-- -> do_fork_next
--
-- 6 n(r) s_dstw_ind rreq n
-- s_dstw_ind_w get n; ea=r+n
-- s_dstw_dec1 wreq n(r) check kstack
-- s_dstw_def_w ack n(r)
-- -> do_fork_next
--
-- 7 @n(r) s_dstw_ind rreq n
-- s_dstw_ind_w get n; ea=r+n
-- s_dstw_dec1 rreq n(r)
-- s_dstw_incdef_w get n(r)
-- s_dstw_def246 wreq @n(r)
-- s_dstw_def_w ack @n(r)
-- -> do_fork_next
when s_dstw_def => -- -----------------------------------
ndpcntl.psr_ccwe := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
nvmcntl.kstack := is_kstackdst1246;
do_memwrite(nstate, nvmcntl, s_dstw_def_w, pispace=>R_IDSTAT.is_dstpc);
when s_dstw_def_w => -- -----------------------------------
nstate := s_dstw_def_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_dstw_inc => -- -----------------------------------
ndpcntl.psr_ccwe := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST (for else)
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG); --(...)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else)
if DSTDEF = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
nvmcntl.kstack := is_kstackdst1246;
do_memwrite(nstate, nvmcntl, s_dstw_inc_w, pispace=>R_IDSTAT.is_dstpc);
nstatus.do_grwe := '1';
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w,
pispace=>R_IDSTAT.is_dstpc);
end if;
when s_dstw_inc_w => -- -----------------------------------
nstate := s_dstw_inc_w;
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := DSTREG;
if R_STATUS.do_grwe = '1' then
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
nmmumoni.trace_prev := '1'; -- mmr freeze of prev state
ndpcntl.gr_we := '1'; -- update DST reg
end if;
nstatus.do_grwe := '0';
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_dstw_incdef_w => -- -----------------------------------
nstate := s_dstw_incdef_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstw_def246;
end if;
when s_dstw_dec => -- -----------------------------------
ndpcntl.psr_ccwe := '1';
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstw_dec1;
when s_dstw_dec1 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = from idec (for if)
if DSTDEF = '0' then
nvmcntl.kstack := is_kstackdst1246;
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
else
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w);
end if;
when s_dstw_ind => -- -----------------------------------
ndpcntl.psr_ccwe := '1';
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstw_ind_w);
when s_dstw_ind_w => -- -----------------------------------
nstate := s_dstw_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dstw_dec1;
end if;
when s_dstw_def246 => -- -----------------------------------
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
do_memwrite(nstate, nvmcntl, s_dstw_def_w);
-- destination address states -----------------------------------------------
-- flows:
-- 1 (r) -> do_fork_opa
--
-- 2 (r)+ s_dsta_inc r+=2
-- -> do_fork_opa
--
-- 3 @(r)+ s_dsta_inc req (r); r+=s
-- s_dsta_incdef_w get (r)
-- -> do_fork_opa
--
-- 4 -(r) s_dsta_dec r-=s
-- s_dsta_dec1 ?? FIXME ?? what is done here ??
-- -> do_fork_opa
--
-- 5 @-(r) s_dsta_dec r-=s
-- s_dsta_dec1 req (r)
-- s_dsta_incdef_w get (r)
-- -> do_fork_opa
--
-- 6 n(r) s_dsta_ind req n
-- s_dsta_ind_w get n; ea=r+n
-- s_dsta_dec1 ?? FIXME ?? what is done here ??
-- -> do_fork_opa
--
-- 7 @n(r) s_dsta_ind req n
-- s_dsta_ind_w get n; ea=r+n
-- s_dsta_dec1 req n(r)
-- s_dsta_incdef_w get n(r)
-- -> do_fork_opa
when s_dsta_inc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
ndpcntl.dsrc_we := '1'; -- update DSRC
end if;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if DSTDEF = '0' then
do_fork_opa(nstate, R_IDSTAT);
else
do_memread_d(nstate, nvmcntl, s_dsta_incdef_w,
pispace=>R_IDSTAT.is_dstpc);
end if;
when s_dsta_incdef_w => -- -----------------------------------
nstate := s_dsta_incdef_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
do_fork_opa(nstate, R_IDSTAT);
end if;
when s_dsta_dec => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
ndpcntl.dsrc_we := '1'; -- update DSRC
end if;
nstate := s_dsta_dec1;
when s_dsta_dec1 => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if DSTDEF = '0' then -- check here used also by
do_fork_opa(nstate, R_IDSTAT); -- s_dsta_ind flow !!
else
do_memread_d(nstate, nvmcntl, s_dsta_incdef_w);
end if;
when s_dsta_ind => -- -----------------------------------
do_memread_i(nstate, ndpcntl, nvmcntl, s_dsta_ind_w);
when s_dsta_ind_w => -- -----------------------------------
nstate := s_dsta_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- update DDST
nstate := s_dsta_dec1;
end if;
-- instruction operate states -----------------------------------------------
when s_op_halt => -- HALT -------------------------------
idm_idone := '1'; -- instruction done
if is_kmode = '1' then -- if in kernel mode execute
nmmumoni.idone := '1';
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_halt;
nstate := s_idle;
else -- otherwise trap
ncpuerr.illhlt := '1';
nstate := s_abort_4; -- vector 4 abort like 11/70
end if;
when s_op_wait => -- WAIT ------------------------------
-- Note: wait is the only interruptable instruction. The CPU spins
-- in s_op_wait until an interrupt or a control command is seen.
-- In case of a control command R_STATUS.waitsusp is set and
-- control transfered to s_idle. If the control command returns
-- to s_op_wait, waitsusp is cleared here. This ensures that the
-- idm_idone logic (for dmcmon) sees only one WAIT even if it is
-- interrupted by control commands.
ndpcntl.gr_asrc := "000"; -- load R0 in DSRC for DR emulation
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '1';
nstatus.waitsusp := '0'; -- in case of returning from s_idle
-- signal idone in the first cycle of a WAIT instruction to dmcmon
-- ensures that a WAIT is logged once and only once
idm_idone := not (R_STATUS.waitsusp or R_STATUS.cpuwait);
nstate := s_op_wait; -- spin here
if is_kmode = '0' then -- but act as nop if not in kernel
nstate := s_idle;
elsif int_pending = '1' or -- bail out if pending interrupt
R_STATUS.cpustep='1' then -- or the instruction is only stepped
nstate := s_idle;
elsif R_STATUS.cmdbusy = '1' then -- suspend if a cp command is pending
nstatus.waitsusp := '1';
nstate := s_idle;
else
nstatus.cpuwait := '1'; -- if spinning here, signal with cpuwait
nstatus.itimer := '1'; -- itimer will stay 1 during a WAIT
end if;
when s_op_trap => -- traps -----------------------------
idm_idone := '1'; -- instruction done
lvector := "0000" & R_IDSTAT.trap_vec; -- vector
do_start_vec(nstate, ndpcntl, lvector);
when s_op_reset => -- RESET -----------------------------
if is_kmode = '1' then -- if in kernel mode execute
nstatus.breset := '1'; -- issue bus reset
end if;
nstate := s_idle;
when s_op_rts => -- RTS -------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with reg(dst)
idm_pcload := '1'; -- signal flow change
nstate := s_op_rts_pop;
when s_op_rts_pop => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_rts_pop_w,
nmmumoni, pupdt_sp=>'1');
when s_op_rts_pop_w => -- -----------------------------------
nstate := s_op_rts_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gr_adst := DSTREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gr_we := '1'; -- load R with (SP)+
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_op_spl => -- SPL -------------------------------
ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
ndpcntl.psr_func := c_psr_func_wspl;
idm_idone := '1'; -- instruction done
if is_kmode = '1' then -- active only in kernel mode
ndpcntl.psr_we := '1';
nstate := s_ifetch; -- unconditionally fetch next
-- instruction like a 11/70
-- no interrupt recognition !
else
do_fork_next(nstate, nstatus, nmmumoni); -- in non-kernel, noop
end if;
when s_op_mcc => -- CLx/SEx ---------------------------
ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
ndpcntl.psr_func := c_psr_func_wcc;
ndpcntl.psr_we := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_op_br => -- BR --------------------------------
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg8;-- OUNIT B = IREG8
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
-- note: cc are NZVC
case brcode(3 downto 1) is
when "000" => -- BR
brcond := '1';
when "001" => -- BNE/BEQ: if Z = x
brcond := PSW.cc(2);
when "010" => -- BGE/BLT: if N xor V = x
brcond := PSW.cc(3) xor PSW.cc(1);
when "011" => -- BGT/BLE: if Z or (N xor V) = x
brcond := PSW.cc(2) or (PSW.cc(3) xor PSW.cc(1));
when "100" => -- BPL/BMI: if N = x
brcond := PSW.cc(3);
when "101" => -- BHI/BLOS:if C or Z = x
brcond := PSW.cc(2) or PSW.cc(0);
when "110" => -- BVC/BVS: if V = x
brcond := PSW.cc(1);
when "111" => -- BCC/BCS: if C = x
brcond := PSW.cc(0);
when others => null;
end case;
ndpcntl.gr_adst := c_gr_pc;
idm_idone := '1'; -- instruction done
if brcond = brcode(0) then -- this coding creates redundant code
ndpcntl.gr_we := '1'; -- but synthesis optimizes this way !
idm_pcload := '1'; -- signal flow change
do_fork_next(nstate, nstatus, nmmumoni);
else
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_op_mark => -- MARK ------------------------------
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC (with PC+2*nn)
ndpcntl.gr_adst := c_gr_r5; -- fetch r5
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_op_mark1;
when s_op_mark1 => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with r5
idm_pcload := '1'; -- signal flow change
nstate := s_op_mark_pop;
when s_op_mark_pop => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_mark_pop_w,
nmmumoni, pupdt_sp=>'1');
when s_op_mark_pop_w => -- -----------------------------------
nstate := s_op_mark_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gr_adst := c_gr_r5;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gr_we := '1'; -- load R5 with (sp)+
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_op_sob => -- SOB (dec) -------------------------
-- comment fork_next_pref out (blog 2006-10-02) due to synthesis impact
--nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
--ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.dres_sel := R_IDSTAT.res_sel;
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
if DP_STAT.ccout_z = '0' then -- if z=0 branch, if z=1 fall thru
nstate := s_op_sob1;
else
--do_fork_next_pref(nstate, ndpcntl, nvmcntl, nmmumoni);
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_op_sob1 => -- SOB (br) --------------------------
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.ounit_opsub := '1'; -- OUNIT = A - B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1';
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opg_gen => -- -----------------------------------
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.gr_bytop := R_IDSTAT.is_bytop;
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
if R_IDSTAT.op_mov = '1' then -- in case of MOV xx,R
ndpcntl.gr_bytop := '0'; -- no bytop, do sign extend
end if;
ndpcntl.psr_ccwe := '1';
if R_IDSTAT.is_dstw_reg = '1' then
ndpcntl.gr_we := '1';
end if;
if R_IDSTAT.is_rmwop = '1' then
do_memwrite(nstate, nvmcntl, s_opg_gen_rmw_w, pmacc=>'1');
else
idm_idone := '1'; -- instruction done
if R_STATUS.prefdone = '1' then
nstatus.prefdone :='0';
nstate := s_ifetch_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ireg_we := '1';
nstate := s_idecode;
end if;
else
if R_IDSTAT.is_dstw_pc = '1' then
nstate := s_idle;
else
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
end if;
end if;
when s_opg_gen_rmw_w => -- -----------------------------------
nstate := s_opg_gen_rmw_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_opg_mul => -- MUL (oper) ------------------------
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.gr_adst := SRCREG; -- write high order result
ndpcntl.gr_we := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- capture high order part
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.dtmp_we := '1'; -- capture low order part
nstate := s_opg_mul1;
when s_opg_mul1 => -- MUL (write odd reg) ---------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opg_div => -- DIV (load dd_low) -----------------
ndpcntl.munit_s_div := '1';
ndpcntl.gr_asrc := SRCREG(2 downto 1) & "1"; -- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
nstate := s_opg_div_cn;
when s_opg_div_cn => -- DIV (1st...16th cycle) ------------
ndpcntl.munit_s_div_cn := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
nstate := s_opg_div_cn;
if DP_STAT.div_quit = '1' then
nstate := s_opg_div_quit;
else
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
end if;
if DP_STAT.shc_tc = '1' then
nstate := s_opg_div_cr;
end if;
when s_opg_div_cr => -- DIV (remainder correction) --------
ndpcntl.munit_s_div_cr := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
nstate := s_opg_div_sq;
when s_opg_div_sq => -- DIV (correct and store quotient) --
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.gr_we := '1';
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
nstate := s_opg_div_sr;
when s_opg_div_sr => -- DIV (store remainder) -------------
ndpcntl.munit_s_div_sr := '1';
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
if DP_STAT.div_quit = '1' then
nstate := s_opg_div_quit;
else
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_opg_div_quit => -- DIV (0/ or /0 or V=1 aborts) ------
ndpcntl.psr_ccwe := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opg_ash => -- ASH (load shc) --------------------
ndpcntl.munit_s_ash := '1';
nstate := s_opg_ash_cn;
when s_opg_ash_cn => -- ASH (shift cycles) ----------------
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.munit_s_ash_cn := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
nstate := s_opg_ash_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
idm_idone := '1'; -- instruction done
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_opg_ashc => -- ASHC (load low, load shc) ---------
ndpcntl.gr_asrc := SRCREG(2 downto 1) & "1"; -- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
ndpcntl.munit_s_ashc := '1';
nstate := s_opg_ashc_cn;
when s_opg_ashc_cn => -- ASHC (shift cycles) ---------------
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.munit_s_ashc_cn := '1';
nstate := s_opg_ashc_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
nstate := s_opg_ashc_wl;
end if;
when s_opg_ashc_wl => -- ASHC (write low) ------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
-- dsta mode operations -----------------------------------------------------
when s_opa_jsr => -- -----------------------------------
ndpcntl.gr_asrc := c_gr_sp; -- (for else)
ndpcntl.dsrc_sel := c_dpath_dsrc_src; -- DSRC = regfile (for else)
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_abort_10; -- vector 10 abort like 11/70
else
ndpcntl.dsrc_we := '1';
nstate := s_opa_jsr1;
end if;
when s_opa_jsr1 => -- -----------------------------------
ndpcntl.gr_asrc := SRCREG;
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc; -- DTMP = regfile
ndpcntl.dtmp_we := '1';
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DDST = DRES
ndpcntl.dsrc_we := '1'; -- update DDST
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_jsr_push;
when s_opa_jsr_push => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_jsr_push_w;
when s_opa_jsr_push_w => -- -----------------------------------
nstate := s_opa_jsr_push_w;
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := SRCREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gr_we := '1'; -- load R with PC
nstate := s_opa_jsr2;
end if;
when s_opa_jsr2 => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with dsta
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opa_jmp => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_abort_10; -- vector 10 abort like 11/70
else
ndpcntl.gr_we := '1'; -- load PC with dsta
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_opa_mtp => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_opa_mtp_pop_w,
nmmumoni, pupdt_sp=>'1');
when s_opa_mtp_pop_w => -- -----------------------------------
nstate := s_opa_mtp_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dtmp_we := '1'; -- load DTMP
if R_IDSTAT.is_dstmode0 = '1' then -- handle register access
nstate := s_opa_mtp_reg;
else
case R_IDSTAT.fork_dsta is -- 2nd dsta fork in s_idecode
when c_fork_dsta_def => nstate := s_opa_mtp_mem;
when c_fork_dsta_inc => nstate := s_dsta_inc;
when c_fork_dsta_dec => nstate := s_dsta_dec;
when c_fork_dsta_ind => nstate := s_dsta_ind;
when others => nstate := s_cpufail;
end case;
end if;
end if;
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
ndpcntl.ddst_we := '1'; -- update DDST (needed for sp)
when s_opa_mtp_reg => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.gr_mode := PSW.pmode; -- load reg in pmode
ndpcntl.gr_we := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opa_mtp_mem => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst;-- VA = DDST
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
nvmcntl.mode := PSW.pmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_mtp_mem_w;
when s_opa_mtp_mem_w => -- -----------------------------------
nstate := s_opa_mtp_mem_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
when s_opa_mfp_reg => -- -----------------------------------
ndpcntl.gr_mode := PSW.pmode; -- fetch reg in pmode
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = reg(dst)
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
when s_opa_mfp_mem => -- -----------------------------------
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
if PSW.cmode=c_psw_umode and -- if cm=pm=user then
PSW.cmode=c_psw_umode then -- MFPI works like it
nvmcntl.dspace := '1'; -- were MFPD
else
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
end if;
nvmcntl.mode := PSW.pmode;
nvmcntl.req := '1';
nstate := s_opa_mfp_mem_w;
when s_opa_mfp_mem_w => -- -----------------------------------
nstate := s_opa_mfp_mem_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
if imemok then
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
end if;
when s_opa_mfp_dec => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_mfp_push;
when s_opa_mfp_push => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.wacc := '1';
nvmcntl.req := '1';
nstate := s_opa_mfp_push_w;
when s_opa_mfp_push_w => -- -----------------------------------
nstate := s_opa_mfp_push_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
-- trap and interrupt handling states --------------------------------------
when s_abort_4 => -- -----------------------------------
lvector := "0000001"; -- vector (4)
do_start_vec(nstate, ndpcntl, lvector);
when s_abort_10 => -- -----------------------------------
idm_idone := '1'; -- instruction done
lvector := "0000010"; -- vector (10)
do_start_vec(nstate, ndpcntl, lvector);
when s_trap_disp => -- -----------------------------------
if R_STATUS.treq_mmu = '1' then -- mmu trap requested ?
lvector := "0101010"; -- mmu trap: vector (250)
elsif R_STATUS.treq_ysv = '1' then -- ysv trap requested ?
lvector := "0000001"; -- ysv trap: vector (4)
ncpuerr.ysv := '1';
nstatus.in_vecysv := '1'; -- signal start of ysv vector flow
else
lvector := "0000011"; -- trace trap: vector (14)
end if;
nstatus.treq_mmu := '0'; -- clear trap request flags
nstatus.treq_ysv := '0'; --
do_start_vec(nstate, ndpcntl, lvector);
when s_int_ext => -- -----------------------------------
lvector := R_STATUS.intvect; -- external vector
do_start_vec(nstate, ndpcntl, lvector);
-- vector flow states ------------------------------------------------------
when s_vec_getpc => -- -----------------------------------
idm_vfetch := '1'; -- signal vfetch
nvmcntl.mode := c_psw_kmode; -- fetch PC from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_vec_getpc_w, nmmumoni);
when s_vec_getpc_w => -- -----------------------------------
nstate := s_vec_getpc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if VM_STAT.err = '1' then -- in case of vm-err
nstatus.cpugo := '0'; -- non-recoverable error
nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
nstate := s_idle;
end if;
if imemok then
ndpcntl.ddst_we := '1'; -- DDST = new PC
nstate := s_vec_getps;
end if;
when s_vec_getps => -- -----------------------------------
nvmcntl.mode := c_psw_kmode; -- fetch PS from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_vec_getps_w, nmmumoni);
when s_vec_getps_w => -- -----------------------------------
nstate := s_vec_getps_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.psr_func := c_psr_func_wint; -- interupt mode write
do_memcheck(nstate, nstatus, imemok);
if VM_STAT.err = '1' then -- in case of vm-err
nstatus.cpugo := '0'; -- non-recoverable error
nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
nstate := s_idle;
end if;
if imemok then
ndpcntl.psr_we := '1'; -- store new PS
nstate := s_vec_getsp;
end if;
when s_vec_getsp => -- -----------------------------------
ndpcntl.gr_asrc := c_gr_sp;
ndpcntl.dsrc_we := '1'; -- DSRC = SP (in new mode)
nstate := s_vec_decsp;
when s_vec_decsp => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP too
nstate := s_vec_pushps;
when s_vec_pushps => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP (old PS)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.req := '1';
nstate := s_vec_pushps_w;
when s_vec_pushps_w => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.gr_adst := c_gr_sp;
nstate := s_vec_pushps_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gr_we := '1'; -- update SP too
nstate := s_vec_pushpc;
end if;
when s_vec_pushpc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
nvmcntl.req := '1';
nstate := s_vec_pushpc_w;
when s_vec_pushpc_w => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
nstate := s_vec_pushpc_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
nstatus.in_vecser := '0'; -- signal end of ser flow
nstatus.in_vecysv := '0'; -- signal end of ysv flow
ndpcntl.gr_we := '1'; -- load new PC
idm_pcload := '1'; -- signal flow change
do_fork_next(nstate, nstatus, nmmumoni); -- ???
end if;
-- return from trap or interrupt handling states ----------------------------
when s_rti_getpc => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getpc_w,
nmmumoni, pupdt_sp=>'1');
when s_rti_getpc_w => -- -----------------------------------
nstate := s_rti_getpc_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.ddst_we := '1'; -- DDST = new PC
nstate := s_rti_getps;
end if;
when s_rti_getps => -- -----------------------------------
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getps_w,
nmmumoni, pupdt_sp=>'1');
when s_rti_getps_w => -- -----------------------------------
nstate := s_rti_getps_w;
do_memcheck(nstate, nstatus, imemok);
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if is_kmode = '1' then -- if in kernel mode
ndpcntl.psr_func := c_psr_func_wall; -- write all fields
else
ndpcntl.psr_func := c_psr_func_wrti; -- otherwise filter
end if;
if imemok then
ndpcntl.psr_we := '1'; -- load new PS
nstate := s_rti_newpc;
end if;
when s_rti_newpc => -- -----------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load new PC
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
nstate := s_ifetch; -- force fetch
else -- otherwise RTI
do_fork_next(nstate, nstatus, nmmumoni);
end if;
-- exception abort states ---------------------------------------------------
when s_vmerr => -- -----------------------------------
nstate := s_cpufail;
-- setup for R_VMSTAT.err_rsv='1'
ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
ndpcntl.ounit_const := "000000100"; -- emergency stack pointer
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.gr_adst := c_gr_sp;
nstatus.treq_mmu := '0'; -- cancel mmu trap request
nstatus.treq_ysv := '0'; -- cancel ysv trap request
if R_VMSTAT.fail = '1' then -- vmbox failure
nstatus.cpugo := '0'; -- halt cpu
nstatus.cpurust := c_cpurust_vfail;
nstate := s_idle;
elsif R_STATUS.in_vecser = '1' then -- double fatal stack error
nstatus.cpugo := '0'; -- give up, HALT cpu
nstatus.cpurust := c_cpurust_recser;
nstate := s_idle;
elsif R_VMSTAT.err = '1' then -- normal vm errors
if R_VMSTAT.err_rsv = '1' then
nstatus.in_vecser := '1'; -- signal start of ser flow
nstatus.in_vecysv := '0'; -- cancel ysv flow
ndpcntl.gr_we := '1';
if R_VMSTAT.err_odd='1' or R_VMSTAT.err_mmu='1' then
ncpuerr.adderr := '1';
elsif R_VMSTAT.err_nxm = '1' then
ncpuerr.nxm := '1';
elsif R_VMSTAT.err_iobto = '1' then
ncpuerr.iobto := '1';
end if;
ncpuerr.rsv := '1';
nstate := s_abort_4;
elsif R_VMSTAT.err_odd = '1' then
ncpuerr.adderr := '1';
nstate := s_abort_4;
elsif R_VMSTAT.err_nxm = '1' then
ncpuerr.nxm := '1';
nstate := s_abort_4;
elsif R_VMSTAT.err_iobto = '1' then
ncpuerr.iobto := '1';
nstate := s_abort_4;
elsif R_VMSTAT.err_mmu = '1' then
lvector := "0101010"; -- vector (250)
do_start_vec(nstate, ndpcntl, lvector);
end if;
end if;
when s_cpufail => -- -----------------------------------
nstatus.cpugo := '0';
nstatus.cpurust := c_cpurust_sfail;
nstate := s_idle;
when others => -- -----------------------------------
nstate := s_cpufail; --!!! catch undefined states !!!
end case;
if HBPT = '1' then -- handle hardware bpt
nstatus.cpurust := c_cpurust_hbpt;
nstatus.suspint :='1';
end if;
nstatus.suspext := ESUSP_I;
-- handle cpususp transitions
if nstatus.suspint='1' or nstatus.suspext='1' then
nstatus.cpususp := '1';
elsif R_STATUS.suspint='0' and R_STATUS.suspext='0' then
nstatus.cpususp := '0';
end if;
if nstatus.cmdack = '1' then -- cmdack in next cycle ? Yes we test
-- nstatus here !!
nstatus.cmdbusy := '0';
ndpcntl.cpdout_we := '1';
end if;
N_STATE <= nstate;
N_STATUS <= nstatus;
N_CPUERR <= ncpuerr;
N_IDSTAT <= nidstat;
INT_ACK <= R_STATUS.intack;
CRESET <= R_STATUS.creset;
BRESET <= R_STATUS.breset;
ESUSP_O <= R_STATUS.suspint; -- FIXME_code: handle masking later
DP_CNTL <= ndpcntl;
VM_CNTL <= nvmcntl;
VM_CNTL_L <= nvmcntl;
nmmumoni.regnum := ndpcntl.gr_adst;
nmmumoni.delta := ndpcntl.ounit_const(3 downto 0);
MMU_MONI <= nmmumoni;
DM_STAT_SE.idle <= idm_idle;
DM_STAT_SE.cpbusy <= idm_cpbusy;
DM_STAT_SE.istart <= nmmumoni.istart;
DM_STAT_SE.idec <= idm_idec;
DM_STAT_SE.idone <= idm_idone;
DM_STAT_SE.itimer <= R_STATUS.itimer;
DM_STAT_SE.pcload <= idm_pcload;
DM_STAT_SE.vfetch <= idm_vfetch;
end process proc_next;
proc_cpstat : process (R_STATUS)
begin
CP_STAT <= cp_stat_init;
CP_STAT.cmdbusy <= R_STATUS.cmdbusy;
CP_STAT.cmdack <= R_STATUS.cmdack;
CP_STAT.cmderr <= R_STATUS.cmderr;
CP_STAT.cmdmerr <= R_STATUS.cmdmerr;
CP_STAT.cpugo <= R_STATUS.cpugo;
CP_STAT.cpustep <= R_STATUS.cpustep;
CP_STAT.cpuwait <= R_STATUS.cpuwait;
CP_STAT.cpususp <= R_STATUS.cpususp;
CP_STAT.cpurust <= R_STATUS.cpurust;
CP_STAT.suspint <= R_STATUS.suspint;
CP_STAT.suspext <= R_STATUS.suspext;
end process proc_cpstat;
-- SNUM creation logic is conditional due to synthesis impact in vivado.
-- SNUM = 'full state number' only available when dmscnt unit enabled.
SNUM1 : if sys_conf_dmscnt generate
begin
proc_snum : process (R_STATE)
variable isnum : slv8 := (others=>'0');
begin
isnum := (others=>'0');
case R_STATE is
-- STATE2SNUM mapper begin
when s_idle => isnum := x"00";
when s_cp_regread => isnum := x"01";
when s_cp_rps => isnum := x"02";
when s_cp_memr_w => isnum := x"03";
when s_cp_memw_w => isnum := x"04";
when s_ifetch => isnum := x"05";
when s_ifetch_w => isnum := x"06";
when s_idecode => isnum := x"07";
when s_srcr_def => isnum := x"08";
when s_srcr_def_w => isnum := x"09";
when s_srcr_inc => isnum := x"0a";
when s_srcr_inc_w => isnum := x"0b";
when s_srcr_dec => isnum := x"0c";
when s_srcr_dec1 => isnum := x"0d";
when s_srcr_ind => isnum := x"0e";
when s_srcr_ind1_w => isnum := x"0f";
when s_srcr_ind2 => isnum := x"10";
when s_srcr_ind2_w => isnum := x"11";
when s_dstr_def => isnum := x"12";
when s_dstr_def_w => isnum := x"13";
when s_dstr_inc => isnum := x"14";
when s_dstr_inc_w => isnum := x"15";
when s_dstr_dec => isnum := x"16";
when s_dstr_dec1 => isnum := x"17";
when s_dstr_ind => isnum := x"18";
when s_dstr_ind1_w => isnum := x"19";
when s_dstr_ind2 => isnum := x"1a";
when s_dstr_ind2_w => isnum := x"1b";
when s_dstw_def => isnum := x"1c";
when s_dstw_def_w => isnum := x"1d";
when s_dstw_inc => isnum := x"1e";
when s_dstw_inc_w => isnum := x"1f";
when s_dstw_incdef_w => isnum := x"20";
when s_dstw_dec => isnum := x"21";
when s_dstw_dec1 => isnum := x"22";
when s_dstw_ind => isnum := x"23";
when s_dstw_ind_w => isnum := x"24";
when s_dstw_def246 => isnum := x"25";
when s_dsta_inc => isnum := x"26";
when s_dsta_incdef_w => isnum := x"27";
when s_dsta_dec => isnum := x"28";
when s_dsta_dec1 => isnum := x"29";
when s_dsta_ind => isnum := x"2a";
when s_dsta_ind_w => isnum := x"2b";
when s_op_halt => isnum := x"2c";
when s_op_wait => isnum := x"2d";
when s_op_trap => isnum := x"2e";
when s_op_reset => isnum := x"2f";
when s_op_rts => isnum := x"30";
when s_op_rts_pop => isnum := x"31";
when s_op_rts_pop_w => isnum := x"32";
when s_op_spl => isnum := x"33";
when s_op_mcc => isnum := x"34";
when s_op_br => isnum := x"35";
when s_op_mark => isnum := x"36";
when s_op_mark1 => isnum := x"37";
when s_op_mark_pop => isnum := x"38";
when s_op_mark_pop_w => isnum := x"39";
when s_op_sob => isnum := x"3a";
when s_op_sob1 => isnum := x"3b";
when s_opg_gen => isnum := x"3c";
when s_opg_gen_rmw_w => isnum := x"3d";
when s_opg_mul => isnum := x"3e";
when s_opg_mul1 => isnum := x"3f";
when s_opg_div => isnum := x"40";
when s_opg_div_cn => isnum := x"41";
when s_opg_div_cr => isnum := x"42";
when s_opg_div_sq => isnum := x"43";
when s_opg_div_sr => isnum := x"44";
when s_opg_div_quit => isnum := x"45";
when s_opg_ash => isnum := x"46";
when s_opg_ash_cn => isnum := x"47";
when s_opg_ashc => isnum := x"48";
when s_opg_ashc_cn => isnum := x"49";
when s_opg_ashc_wl => isnum := x"4a";
when s_opa_jsr => isnum := x"4b";
when s_opa_jsr1 => isnum := x"4c";
when s_opa_jsr_push => isnum := x"4d";
when s_opa_jsr_push_w => isnum := x"4e";
when s_opa_jsr2 => isnum := x"4f";
when s_opa_jmp => isnum := x"50";
when s_opa_mtp => isnum := x"51";
when s_opa_mtp_pop_w => isnum := x"52";
when s_opa_mtp_reg => isnum := x"53";
when s_opa_mtp_mem => isnum := x"54";
when s_opa_mtp_mem_w => isnum := x"55";
when s_opa_mfp_reg => isnum := x"56";
when s_opa_mfp_mem => isnum := x"57";
when s_opa_mfp_mem_w => isnum := x"58";
when s_opa_mfp_dec => isnum := x"59";
when s_opa_mfp_push => isnum := x"5a";
when s_opa_mfp_push_w => isnum := x"5b";
when s_abort_4 => isnum := x"5c";
when s_abort_10 => isnum := x"5d";
when s_trap_disp => isnum := x"5e";
when s_int_ext => isnum := x"5f";
when s_vec_getpc => isnum := x"60";
when s_vec_getpc_w => isnum := x"61";
when s_vec_getps => isnum := x"62";
when s_vec_getps_w => isnum := x"63";
when s_vec_getsp => isnum := x"64";
when s_vec_decsp => isnum := x"65";
when s_vec_pushps => isnum := x"66";
when s_vec_pushps_w => isnum := x"67";
when s_vec_pushpc => isnum := x"68";
when s_vec_pushpc_w => isnum := x"69";
when s_rti_getpc => isnum := x"6a";
when s_rti_getpc_w => isnum := x"6b";
when s_rti_getps => isnum := x"6c";
when s_rti_getps_w => isnum := x"6d";
when s_rti_newpc => isnum := x"6e";
when s_vmerr => isnum := x"6f";
when s_cpufail => isnum := x"70";
-- STATE2SNUM mapper end
when others => isnum := x"ff";
end case;
DM_STAT_SE.snum <= isnum;
end process proc_snum;
end generate SNUM1;
-- if dmscnt not enable setup SNUM based on state categories (currently 4)
-- and a 'wait' indicator determined from monitoring VM_CNTL and VM_STAT
SNUM0 : if not sys_conf_dmscnt generate
signal R_VMWAIT : slbit := '0'; -- vmwait flag
begin
proc_vmwait: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_VMWAIT <= '0';
else
if VM_CNTL_L.req = '1' then
R_VMWAIT <= '1';
elsif VM_STAT.ack = '1' or VM_STAT.err = '1' or VM_STAT.fail='1' then
R_VMWAIT <= '0';
end if;
end if;
end if;
end process proc_vmwait;
proc_snum : process (R_STATE, R_VMWAIT)
variable isnum_con : slbit := '0';
variable isnum_ins : slbit := '0';
variable isnum_vec : slbit := '0';
variable isnum_err : slbit := '0';
begin
isnum_con := '0';
isnum_ins := '0';
isnum_vec := '0';
isnum_err := '0';
case R_STATE is
when s_idle => null;
when s_cp_regread => isnum_con := '1';
when s_cp_rps => isnum_con := '1';
when s_cp_memr_w => isnum_con := '1';
when s_cp_memw_w => isnum_con := '1';
when s_ifetch => isnum_ins := '1';
when s_ifetch_w => isnum_ins := '1';
when s_idecode => isnum_ins := '1';
when s_srcr_def => isnum_ins := '1';
when s_srcr_def_w => isnum_ins := '1';
when s_srcr_inc => isnum_ins := '1';
when s_srcr_inc_w => isnum_ins := '1';
when s_srcr_dec => isnum_ins := '1';
when s_srcr_dec1 => isnum_ins := '1';
when s_srcr_ind => isnum_ins := '1';
when s_srcr_ind1_w => isnum_ins := '1';
when s_srcr_ind2 => isnum_ins := '1';
when s_srcr_ind2_w => isnum_ins := '1';
when s_dstr_def => isnum_ins := '1';
when s_dstr_def_w => isnum_ins := '1';
when s_dstr_inc => isnum_ins := '1';
when s_dstr_inc_w => isnum_ins := '1';
when s_dstr_dec => isnum_ins := '1';
when s_dstr_dec1 => isnum_ins := '1';
when s_dstr_ind => isnum_ins := '1';
when s_dstr_ind1_w => isnum_ins := '1';
when s_dstr_ind2 => isnum_ins := '1';
when s_dstr_ind2_w => isnum_ins := '1';
when s_dstw_def => isnum_ins := '1';
when s_dstw_def_w => isnum_ins := '1';
when s_dstw_inc => isnum_ins := '1';
when s_dstw_inc_w => isnum_ins := '1';
when s_dstw_incdef_w => isnum_ins := '1';
when s_dstw_dec => isnum_ins := '1';
when s_dstw_dec1 => isnum_ins := '1';
when s_dstw_ind => isnum_ins := '1';
when s_dstw_ind_w => isnum_ins := '1';
when s_dstw_def246 => isnum_ins := '1';
when s_dsta_inc => isnum_ins := '1';
when s_dsta_incdef_w => isnum_ins := '1';
when s_dsta_dec => isnum_ins := '1';
when s_dsta_dec1 => isnum_ins := '1';
when s_dsta_ind => isnum_ins := '1';
when s_dsta_ind_w => isnum_ins := '1';
when s_op_halt => isnum_ins := '1';
when s_op_wait => isnum_ins := '1';
when s_op_trap => isnum_ins := '1';
when s_op_reset => isnum_ins := '1';
when s_op_rts => isnum_ins := '1';
when s_op_rts_pop => isnum_ins := '1';
when s_op_rts_pop_w => isnum_ins := '1';
when s_op_spl => isnum_ins := '1';
when s_op_mcc => isnum_ins := '1';
when s_op_br => isnum_ins := '1';
when s_op_mark => isnum_ins := '1';
when s_op_mark1 => isnum_ins := '1';
when s_op_mark_pop => isnum_ins := '1';
when s_op_mark_pop_w => isnum_ins := '1';
when s_op_sob => isnum_ins := '1';
when s_op_sob1 => isnum_ins := '1';
when s_opg_gen => isnum_ins := '1';
when s_opg_gen_rmw_w => isnum_ins := '1';
when s_opg_mul => isnum_ins := '1';
when s_opg_mul1 => isnum_ins := '1';
when s_opg_div => isnum_ins := '1';
when s_opg_div_cn => isnum_ins := '1';
when s_opg_div_cr => isnum_ins := '1';
when s_opg_div_sq => isnum_ins := '1';
when s_opg_div_sr => isnum_ins := '1';
when s_opg_div_quit => isnum_ins := '1';
when s_opg_ash => isnum_ins := '1';
when s_opg_ash_cn => isnum_ins := '1';
when s_opg_ashc => isnum_ins := '1';
when s_opg_ashc_cn => isnum_ins := '1';
when s_opg_ashc_wl => isnum_ins := '1';
when s_opa_jsr => isnum_ins := '1';
when s_opa_jsr1 => isnum_ins := '1';
when s_opa_jsr_push => isnum_ins := '1';
when s_opa_jsr_push_w => isnum_ins := '1';
when s_opa_jsr2 => isnum_ins := '1';
when s_opa_jmp => isnum_ins := '1';
when s_opa_mtp => isnum_ins := '1';
when s_opa_mtp_pop_w => isnum_ins := '1';
when s_opa_mtp_reg => isnum_ins := '1';
when s_opa_mtp_mem => isnum_ins := '1';
when s_opa_mtp_mem_w => isnum_ins := '1';
when s_opa_mfp_reg => isnum_ins := '1';
when s_opa_mfp_mem => isnum_ins := '1';
when s_opa_mfp_mem_w => isnum_ins := '1';
when s_opa_mfp_dec => isnum_ins := '1';
when s_opa_mfp_push => isnum_ins := '1';
when s_opa_mfp_push_w => isnum_ins := '1';
when s_abort_4 => isnum_ins := '1';
when s_abort_10 => isnum_ins := '1';
when s_trap_disp => isnum_ins := '1';
when s_int_ext => isnum_vec := '1';
when s_vec_getpc => isnum_vec := '1';
when s_vec_getpc_w => isnum_vec := '1';
when s_vec_getps => isnum_vec := '1';
when s_vec_getps_w => isnum_vec := '1';
when s_vec_getsp => isnum_vec := '1';
when s_vec_decsp => isnum_vec := '1';
when s_vec_pushps => isnum_vec := '1';
when s_vec_pushps_w => isnum_vec := '1';
when s_vec_pushpc => isnum_vec := '1';
when s_vec_pushpc_w => isnum_vec := '1';
when s_rti_getpc => isnum_vec := '1';
when s_rti_getpc_w => isnum_vec := '1';
when s_rti_getps => isnum_vec := '1';
when s_rti_getps_w => isnum_vec := '1';
when s_rti_newpc => isnum_vec := '1';
when s_vmerr => isnum_err := '1';
when s_cpufail => isnum_err := '1';
when others => null;
end case;
DM_STAT_SE.snum <= (others=>'0');
DM_STAT_SE.snum(c_snum_f_con) <= isnum_con;
DM_STAT_SE.snum(c_snum_f_ins) <= isnum_ins;
DM_STAT_SE.snum(c_snum_f_vec) <= isnum_vec;
DM_STAT_SE.snum(c_snum_f_err) <= isnum_err;
DM_STAT_SE.snum(c_snum_f_vmw) <= R_VMWAIT;
end process proc_snum;
end generate SNUM0;
end syn;
| gpl-3.0 | d0e7210f46a48b2f6bd72f6f849495e9 | 0.461057 | 3.692068 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd | 1 | 4,267 | -- $Id: s6_cmt_sfs_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s6_cmt_sfs - syn
-- Description: Spartan-6 CMT for simple frequency synthesis
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-05 537 1.0 Initial version (derived from s7_cmt_sfs)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/dcm locked
);
end s6_cmt_sfs;
architecture syn of s6_cmt_sfs is
begin
assert GEN_TYPE = "PLL" or GEN_TYPE = "DCM"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate NOGEN;
USEPLL: if GEN_TYPE = "PLL" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKOUT0 : slbit;
signal CLKOUT1_UNUSED : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
begin
PLL : pll_base
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT => VCO_MULTIPLY,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => OUT_DIVIDE,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => CLKIN_PERIOD,
REF_JITTER => CLKIN_JITTER)
port map (
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1_UNUSED,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT,
CLKIN => CLKIN,
LOCKED => LOCKED,
RST => '0'
);
BUFG_CLKOUT : bufg
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEPLL;
USEDCM: if GEN_TYPE = "DCM" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKOUT0 : slbit;
begin
DCM : dcm_sp
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => VCO_DIVIDE,
CLKFX_MULTIPLY => VCO_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE",
STARTUP_WAIT => STARTUP_WAIT)
port map (
CLKIN => CLKIN,
CLKFX => CLKOUT0,
LOCKED => LOCKED
);
BUFG_CLKOUT : bufg
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEDCM;
end syn;
| gpl-3.0 | 6b95931f3a4047b3ebbc1d94787bed9c | 0.509257 | 3.991581 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd | 1 | 8,989 | -- $Id: sys_tst_rlink_b3.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_b3 - syn
-- Description: rlink tester design for basys3
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_tst_rlink_b3
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1 1039 1492 34 3.0 527
-- 2019-02-02 1108 2018.3 xc7a35t-1 1040 1594 36 3.0 546
-- 2019-02-02 1108 2017.2 xc7a35t-1 1040 1682 36 3.0 587
-- 2016-03-27 753 2015.4 xc7a35t-1 986 1352 36 3.0 473 meminf
-- 2016-03-13 743 2015.4 xc7a35t-1 988 1372 64 4.5 503 +XADC
-- 2015-01-30 636 2014.4 xc7a35t-1 946 1319 64 4.5 476
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.1.3 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-19 748 1.1.2 define rlink SYSID
-- 2016-03-18 745 1.1.1 hardwire XON=1
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2016-02-26 735 1.0.2 use s7_cmt_sfs
-- 2015-04-11 666 1.0.1 rearrange XON handling
-- 2015-01-16 636 1.0 Initial version (derived from sys_tst_rlink_n3)
------------------------------------------------------------------------------
-- Usage of Basys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): -unused-
-- SWI(0): -unused-
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(1): timer 1 busy
-- LED(0): timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_b3 is -- top level
-- implements basys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_rlink_b3;
architecture syn of sys_tst_rlink_b3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"06"; -- basys3
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
HIO : sn_humanio_rbus
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR1 : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(15 downto 8) <= SWI(15 downto 8);
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
| gpl-3.0 | 559d9ebe269c6201d3a00603b9781771 | 0.499833 | 3.159578 | false | false | false | false |
wfjm/w11 | rtl/bplib/artys7/sramif_mig_artys7.vhd | 1 | 7,442 | -- $Id: sramif_mig_artys7.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sramif_mig_artys7 - syn
-- Description: SRAM to DDR via MIG for artys7
--
-- Dependencies: bplib/mig/sramif2migui_core
-- cdclib/cdc_pulse
-- cdclib/cdc_value
-- migui_artys7 (generated core)
-- Test bench: -
-- Target Devices: artys7 board
-- Tool versions: viv 2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-12 1105 1.0 Initial version (cloned from sramif_mig_arty)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.cdclib.all;
use work.miglib.all;
use work.miglib_artys7.all;
entity sramif_mig_artys7 is -- SRAM to DDR via MIG for artys7
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- xadc die temp for mig core
MONI : out sramif2migui_moni_type;-- monitor signals
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sramif_mig_artys7;
architecture syn of sramif_mig_artys7 is
signal MIG_BUSY : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_EN : slbit := '0';
signal APP_CMD : slv3 := (others=>'0');
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_WDF_RDY : slbit := '0';
signal APP_WDF_WREN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal UI_CLK_SYNC_RST : slbit := '0';
signal INIT_CALIB_COMPLETE : slbit := '0';
signal SYS_RST : slbit := '0';
signal SYS_RST_BUSY : slbit := '0';
signal CLKMUI : slbit := '0';
signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI
begin
SR2MIG: sramif2migui_core -- SRAM to MIG iface -----------------
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => MIG_BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
MONI => MONI,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END
);
CDC_SYSRST: cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => true)
port map (
CLKM => CLK,
RESET => '0',
CLKS => CLKMIG,
PIN => RESET,
BUSY => SYS_RST_BUSY,
POUT => SYS_RST
);
CDC_TEMP: cdc_value
generic map (
DWIDTH => TEMP'length)
port map (
CLKI => CLK,
CLKO => CLKMUI,
DI => TEMP,
DO => TEMP_MUI,
UPDT => open
);
MIG_CTL: migui_artys7
port map (
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => '0',
APP_REF_REQ => '0',
APP_ZQ_REQ => '0',
APP_SR_ACTIVE => open,
APP_REF_ACK => open,
APP_ZQ_ACK => open,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => TEMP_MUI,
SYS_RST => SYS_RST
);
BUSY <= MIG_BUSY or SYS_RST_BUSY;
end syn;
| gpl-3.0 | 69d7ab4a764a30a479554197e6920025 | 0.464391 | 3.355275 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/fifo_1c_dram.vhd | 1 | 2,641 | -- $Id: fifo_1c_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_1c_dram - syn
-- Description: FIFO, single clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: fifo_1c_dram_raw
--
-- Test bench: tb/tb_fifo_1c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-06-06 49 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m Flop clock(xst est.)
-- 4 16 31 32 22 153MHz ( 16 words)
-- 5 16 49 64 23 120MHz ( 32 words)
-- 6 16 70 128 23 120MHz ( 64 words)
-- 7 16 111 256 30 120MHz (128 words)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_1c_dram is -- fifo, 1 clock, dram based
generic (
AWIDTH : positive := 7; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZE : out slv(AWIDTH downto 0) -- number of used slots
);
end fifo_1c_dram;
architecture syn of fifo_1c_dram is
signal WE : slbit := '0';
signal RE : slbit := '0';
signal SIZE_L : slv(AWIDTH-1 downto 0) := (others=>'0');
signal EMPTY : slbit := '0';
signal FULL : slbit := '0';
begin
FIFO : fifo_1c_dram_raw
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
RESET => RESET,
WE => WE,
RE => RE,
DI => DI,
DO => DO,
SIZE => SIZE_L,
EMPTY => EMPTY,
FULL => FULL
);
WE <= ENA and (not FULL);
RE <= (not EMPTY) and (not HOLD);
BUSY <= FULL;
VAL <= not EMPTY;
SIZE <= FULL & SIZE_L;
end syn;
| gpl-3.0 | 11a0897a7f13567afa0c2b800fe1c0c4 | 0.496782 | 3.516644 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/tb/tb_tst_serloop1_n4d.vhd | 1 | 3,381 | -- $Id: tb_tst_serloop1_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n4d - sim
-- Description: Test bench for sys_tst_serloop1_n4d
--
-- Dependencies: simlib/simclk
-- xlib/sfs_gsim_core
-- sys_tst_serloop1_n4d [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n4d
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-01-04 838 1.0 Initial version (cloned from tb_tst_serloop1_n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
use work.sys_conf.all;
entity tb_tst_serloop1_n4d is
end tb_tst_serloop1_n4d;
architecture sim of tb_tst_serloop1_n4d is
signal CLK100 : slbit := '0';
signal CLK : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
GEN_CLKSYS : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide)
port map (
CLKIN => CLK100,
CLKFX => CLK,
LOCKED => open
);
UUT : entity work.sys_tst_serloop1_n4d
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => '1',
O_LED => open,
O_RGBLED0 => open,
O_RGBLED1 => open,
O_ANO_N => open,
O_SEG_N => open
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK,
CLKH => CLK,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => RTS_N,
P0_CTS_N => CTS_N,
P1_RXD => open, -- port 1 unused for n4d !
P1_TXD => '0',
P1_RTS_N => '0',
P1_CTS_N => open,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
RTS_N <= O_RTS_N after delay_time;
I_CTS_N <= CTS_N after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | 481d11e2443c4071b4bb0923126cb5b5 | 0.505472 | 3.107537 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd | 1 | 1,259 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants =======================================================
constant sys_conf_clksys : integer := 50000000;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | dcaa090e2d7d5886f76c7a1e2a8e1f95 | 0.55282 | 3.909938 | false | false | false | false |
wfjm/w11 | rtl/vlib/cdclib/cdc_vector_s0.vhd | 1 | 1,681 | -- $Id: cdc_vector_s0.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cdc_vector_s0 - syn
-- Description: clock domain crossing for a vector, 1 stage
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4-2017.2; ghdl 0.33-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-02 1101 1.1 add ENA port
-- 2016-04-08 459 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cdc_vector_s0 is -- cdc for vector (1 stage)
generic (
DWIDTH : positive := 16); -- data port width
port (
CLKO : in slbit; -- O|output clock
ENA : in slbit := '1'; -- O|capture enable
DI : in slv(DWIDTH-1 downto 0); -- I|input data
DO : out slv(DWIDTH-1 downto 0) -- O|output data
);
end entity cdc_vector_s0;
architecture syn of cdc_vector_s0 is
subtype d_range is integer range DWIDTH-1 downto 0;
signal R_DO_S0 : slv(d_range) := (others=>'0');
attribute ASYNC_REG: string;
attribute ASYNC_REG of R_DO_S0 : signal is "true";
begin
proc_regs: process (CLKO)
begin
if rising_edge(CLKO) then
if ENA = '1' then
R_DO_S0 <= DI; -- synch 0: CLKI->CLKO
end if;
end if;
end process proc_regs;
DO <= R_DO_S0;
end syn;
| gpl-3.0 | 1ac9371bbd6fac2b00825645019f4055 | 0.532421 | 3.39596 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11.vhd | 1 | 70,913 | -- $Id: pdp11.vhd 1321 2022-11-24 15:06:47Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: pdp11
-- Description: Definitions for pdp11 components
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2016.2-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-11-24 1321 1.5.17 add cpustat_type intpend
-- 2022-11-21 1320 1.6.16 rename some rsv->ser and cpustat_type trap_->treq_;
-- remove vm_cntl_type.trap_done; add in_vecysv;
-- 2022-10-25 1309 1.6.15 rename _gpr -> _gr
-- 2022-10-03 1301 1.6.14 add decode_stat_type.is_dstpcmode1
-- 2022-08-13 1279 1.6.13 ssr->mmr rename
-- 2019-06-02 1159 1.6.12 add rbaddr_ constants
-- 2019-03-01 1116 1.6.11 define c_init_rbf_greset
-- 2018-10-07 1054 1.6.10 add DM_STAT_EXP; add DM_STAT_SE.itimer
-- 2018-10-05 1053 1.6.9 drop DM_STAT_SY; add DM_STAT_CA, use in pdp11_cache
-- add DM_STAT_SE.pcload
-- 2018-09-29 1051 1.6.8 add pdp11_dmpcnt; add DM_STAT_SE.(cpbusy,idec)
-- 2017-04-22 884 1.6.7 dm_stat_se: add idle; pdp11_dmcmon: add SNUM generic
-- 2016-12-26 829 1.6.6 BUGFIX: psw init with pri=0, as on real 11/70
-- 2015-11-01 712 1.6.5 define sbcntl_sbf_tmu := 12; use for pdp11_tmu_sb
-- 2015-07-19 702 1.6.4 change DM_STAT_(DP|CO); add DM_STAT_SE
-- 2015-07-10 700 1.6.3 define c_cpurust_hbpt;
-- 2015-07-04 697 1.6.2 add pdp11_dm(hbpt|cmon); change DM_STAT_(SY|VM|CO)
-- 2015-06-26 695 1.6.1 add pdp11_dmscnt (add support)
-- 2015-05-09 677 1.6 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 1.5.5 add pdp11_sys70, sys_hio70
-- 2015-04-30 670 1.5.4 rename pdp11_sys70 -> pdp11_reg70
-- 2015-02-20 649 1.5.3 add pdp11_statleds
-- 2015-02-08 644 1.5.2 add pdp11_bram_memctl
-- 2014-08-28 588 1.5.1 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2014-08-10: 581 1.4.10 add c_cc_f_* field defs for condition code array
-- 2014-07-12 569 1.4.9 dpath_stat_type: merge div_zero+div_ovfl to div_quit
-- dpath_cntl_type: add munit_s_div_sr
-- 2011-11-18 427 1.4.8 now numeric_std clean
-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
-- reassign cp command codes and rename: c_cp_func_...
-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
-- reassign rbus adresses and rename: c_rb_addr_...
-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
-- -> c_stat_rbf_...
-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2010-03-21 270 1.2.6 add pdp11_du_drv
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
-- move (and rename) intbus defs to iblib package;
-- move intbus devices to ibdlib package;
-- rename ubf_ --> ibf_;
-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
-- _vmbox,_mmu interface changed
-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
-- mod pdp11_intmap;
-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- add ibdr_kw11l.
-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.rblib.all;
package pdp11 is
-- default rbus base addresses and offsets
constant rbaddr_cpu0_core : slv16 := x"0000"; -- cpu0 core base
constant rbaddr_cpu0_ibus : slv16 := x"4000"; -- cpu0 ibus window base
constant rbaddr_dmscnt_off : slv16 := x"0040"; -- dmscnt offset
constant rbaddr_dmcmon_off : slv16 := x"0048"; -- dmcmon offset
constant rbaddr_dmhbpt_off : slv16 := x"0050"; -- dmhbpt offset
constant rbaddr_dmpcnt_off : slv16 := x"0060"; -- dmpcnt offset
type psw_type is record -- processor status
cmode : slv2; -- current mode
pmode : slv2; -- previous mode
rset : slbit; -- register set
pri : slv3; -- processor priority
tflag : slbit; -- trace flag
cc : slv4; -- condition codes (NZVC).
end record psw_type;
constant c_cc_f_n: integer := 3; -- condition code: n
constant c_cc_f_z: integer := 2; -- condition code: z
constant c_cc_f_v: integer := 1; -- condition code: v
constant c_cc_f_c: integer := 0; -- condition code: c
constant psw_init : psw_type := (
"00","00", -- cmode, pmode (=kernel)
'0',"000",'0', -- rset, pri (=0), tflag
"0000" -- cc NZVC=0
);
constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
constant c_psw_umode : slv2 := "11"; -- processor mode: user
subtype psw_ibf_cmode is integer range 15 downto 14;
subtype psw_ibf_pmode is integer range 13 downto 12;
constant psw_ibf_rset: integer := 11;
subtype psw_ibf_pri is integer range 7 downto 5;
constant psw_ibf_tflag: integer := 4;
subtype psw_ibf_cc is integer range 3 downto 0;
type parpdr_type is record -- combined PAR/PDR MMU status
paf : slv16; -- page address field
plf : slv7; -- page length field
ed : slbit; -- expansion direction
acf : slv3; -- access control field
end record parpdr_type;
constant parpdr_init : parpdr_type := (
(others=>'0'), -- paf
"0000000",'0',"000" -- plf, ed, acf
);
type dpath_cntl_type is record -- data path control
gr_asrc : slv3; -- src register address
gr_adst : slv3; -- dst register address
gr_mode : slv2; -- psw mode for gr access
gr_rset : slbit; -- register set
gr_we : slbit; -- gr write enable
gr_bytop : slbit; -- gr high byte enable
gr_pcinc : slbit; -- pc increment enable
psr_ccwe : slbit; -- enable update cc
psr_we: slbit; -- write enable psw (from DIN)
psr_func : slv3; -- write function psw (from DIN)
dsrc_sel : slbit; -- src data register source select
dsrc_we : slbit; -- src data register write enable
ddst_sel : slbit; -- dst data register source select
ddst_we : slbit; -- dst data register write enable
dtmp_sel : slv2; -- tmp data register source select
dtmp_we : slbit; -- tmp data register write enable
ounit_asel : slv2; -- ounit a port selector
ounit_azero : slbit; -- ounit a port force zero
ounit_const : slv9; -- ounit b port const
ounit_bsel : slv2; -- ounit b port selector
ounit_opsub : slbit; -- ounit operation
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
aunit_bytop : slbit; -- aunit byte operation
lunit_func : slv4; -- lunit function
lunit_bytop : slbit; -- lunit byte operation
munit_func : slv2; -- munit function
munit_s_div : slbit; -- munit s_opg_div state
munit_s_div_cn : slbit; -- munit s_opg_div_cn state
munit_s_div_cr : slbit; -- munit s_opg_div_cr state
munit_s_div_sr : slbit; -- munit s_opg_div_sr state
munit_s_ash : slbit; -- munit s_opg_ash state
munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
munit_s_ashc : slbit; -- munit s_opg_ashc state
munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
ireg_we : slbit; -- ireg register write enable
cres_sel : slv3; -- result bus (cres) select
dres_sel : slv3; -- result bus (dres) select
vmaddr_sel : slv2; -- virtual address select
cpdout_we : slbit; -- capture dres for cpdout
end record dpath_cntl_type;
constant dpath_cntl_init : dpath_cntl_type := (
"000","000","00",'0','0','0','0', -- gr
'0','0',"000", -- psr
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
"00",'0',"000000000","00",'0', -- ounit
"00","00","00",'0',"000",'0', -- aunit
"0000",'0', -- lunit
"00",'0','0','0','0','0','0','0','0',-- munit
'0',"000","000","00",'0' -- rest
);
constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
type dpath_stat_type is record -- data path status
ccout_z : slbit; -- current effective Z cc flag
shc_tc : slbit; -- last shc cycle (shc==0)
div_cr : slbit; -- division: remainder correction needed
div_cq : slbit; -- division: quotient correction needed
div_quit : slbit; -- division: abort (0/ or /0 or V=1)
end record dpath_stat_type;
constant dpath_stat_init : dpath_stat_type := (others=>'0');
type decode_stat_type is record -- decode status
is_dstmode0 : slbit; -- dest. is register mode
is_srcpc : slbit; -- source is pc
is_srcpcmode1 : slbit; -- source is pc and mode=1
is_dstpc : slbit; -- dest. is pc
is_dstpcmode1 : slbit; -- dest. is pc and mode=1
is_dstw_reg : slbit; -- dest. register to be written
is_dstw_pc : slbit; -- pc register to be written
is_rmwop : slbit; -- read-modify-write operation
is_bytop : slbit; -- byte operation
is_res : slbit; -- reserved operation code
op_rtt : slbit; -- RTT instruction
op_mov : slbit; -- MOV instruction
trap_vec : slv3; -- trap vector addr bits 4:2
force_srcsp : slbit; -- force src register to be sp
updt_dstadsrc : slbit; -- update dsrc in dsta flow
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
lunit_func : slv4; -- lunit function
munit_func : slv2; -- munit function
res_sel : slv3; -- result bus (cres/dres) select
fork_op : slv4; -- op fork after idecode state
fork_srcr : slv2; -- src-read fork after idecode state
fork_dstr : slv2; -- dst-read fork after src read state
fork_dsta : slv2; -- dst-addr fork after idecode state
fork_opg : slv4; -- opg fork
fork_opa : slv3; -- opa fork
do_fork_op : slbit; -- execute fork_op
do_fork_srcr : slbit; -- execute fork_srcr
do_fork_dstr : slbit; -- execute fork_dstr
do_fork_dsta : slbit; -- execute fork_dsta
do_fork_opg : slbit; -- execute fork_opg
do_pref_dec : slbit; -- can do prefetch at decode phase
end record decode_stat_type;
constant decode_stat_init : decode_stat_type := (
'0','0','0','0','0','0','0','0','0','0', -- is_
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
"00","00","00",'0',"000", -- aunit_
"0000","00","000", -- lunit_, munit_, res_
"0000","00","00","00","0000","000", -- fork_
'0','0','0','0','0', -- do_fork_
'0' -- do_pref_
);
constant c_fork_op_halt : slv4 := "0000";
constant c_fork_op_wait : slv4 := "0001";
constant c_fork_op_rtti : slv4 := "0010";
constant c_fork_op_trap : slv4 := "0011";
constant c_fork_op_reset: slv4 := "0100";
constant c_fork_op_rts : slv4 := "0101";
constant c_fork_op_spl : slv4 := "0110";
constant c_fork_op_mcc : slv4 := "0111";
constant c_fork_op_br : slv4 := "1000";
constant c_fork_op_mark : slv4 := "1001";
constant c_fork_op_sob : slv4 := "1010";
constant c_fork_op_mtp : slv4 := "1011";
constant c_fork_srcr_def : slv2:= "00";
constant c_fork_srcr_inc : slv2:= "01";
constant c_fork_srcr_dec : slv2:= "10";
constant c_fork_srcr_ind : slv2:= "11";
constant c_fork_dstr_def : slv2:= "00";
constant c_fork_dstr_inc : slv2:= "01";
constant c_fork_dstr_dec : slv2:= "10";
constant c_fork_dstr_ind : slv2:= "11";
constant c_fork_dsta_def : slv2:= "00";
constant c_fork_dsta_inc : slv2:= "01";
constant c_fork_dsta_dec : slv2:= "10";
constant c_fork_dsta_ind : slv2:= "11";
constant c_fork_opg_gen : slv4 := "0000";
constant c_fork_opg_wdef : slv4 := "0001";
constant c_fork_opg_winc : slv4 := "0010";
constant c_fork_opg_wdec : slv4 := "0011";
constant c_fork_opg_wind : slv4 := "0100";
constant c_fork_opg_mul : slv4 := "0101";
constant c_fork_opg_div : slv4 := "0110";
constant c_fork_opg_ash : slv4 := "0111";
constant c_fork_opg_ashc : slv4 := "1000";
constant c_fork_opa_jsr : slv3 := "000";
constant c_fork_opa_jmp : slv3 := "001";
constant c_fork_opa_mtp : slv3 := "010";
constant c_fork_opa_mfp_reg : slv3 := "011";
constant c_fork_opa_mfp_mem : slv3 := "100";
-- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
constant c_cpurust_hbpt : slv4 := "0110"; -- cpu had hardware bpt
constant c_cpurust_runs : slv4 := "0111"; -- cpu running
constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
constant c_cpurust_recser : slv4 := "1001"; -- recursive stack error halt
constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
type cpustat_type is record -- CPU status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpususp : slbit; -- CPU susp flag
cpuwait : slbit; -- CPU wait flag
cpurust : slv4; -- CPU run status
suspint : slbit; -- internal suspend flag
suspext : slbit; -- external suspend flag
cpfunc : slv5; -- current control port function
cprnum : slv3; -- current control port register number
waitsusp : slbit; -- WAIT instruction suspended
itimer : slbit; -- ITIMER pulse
creset : slbit; -- CRESET pulse
breset : slbit; -- BRESET pulse
intack : slbit; -- INT_ACK pulse
intpend : slbit; -- interrupt pending
intvect : slv9_2; -- current interrupt vector
treq_mmu : slbit; -- mmu trap requested
treq_ysv : slbit; -- ysv trap requested
prefdone : slbit; -- prefetch done
do_grwe : slbit; -- pending gr_we
in_vecser : slbit; -- in fatal stack error vector flow
in_vecysv : slbit; -- in ysv trap flow
end record cpustat_type;
constant cpustat_init : cpustat_type := (
'0','0','0','0', -- cmdbusy,cmdack,cmderr,cmdmerr
'0','0','0','0', -- cpugo,cpustep,cpususp,cpuwait
c_cpurust_init, -- cpurust
'0','0', -- suspint,suspext
"00000","000", -- cpfunc, cprnum
'0', -- waitsusp
'0','0','0','0','0', -- itimer,creset,breset,intack,intpend
(others=>'0'), -- intvect
'0','0','0', -- treq_(mmu|ysv), prefdone
'0','0','0' -- do_grwe, in_vec(ser|ysv)
);
type cpuerr_type is record -- CPU error register
illhlt : slbit; -- illegal halt (in non-kernel mode)
adderr : slbit; -- address error (odd, jmp/jsr reg)
nxm : slbit; -- non-existent memory
iobto : slbit; -- I/O bus timeout (non-exist UB)
ysv : slbit; -- yellow stack violation
rsv : slbit; -- red stack violation
end record cpuerr_type;
constant cpuerr_init : cpuerr_type := (others=>'0');
type vm_cntl_type is record -- virt memory control port
req : slbit; -- request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access
bytop : slbit; -- byte operation
dspace : slbit; -- dspace operation
kstack : slbit; -- access through kernel stack
vecser : slbit; -- in fatal stack error vector flow
mode : slv2; -- mode
end record vm_cntl_type;
constant vm_cntl_init : vm_cntl_type := (
'0','0','0','0', -- req, wacc, macc,cacc
'0','0','0', -- bytop, dspace, kstack
'0',"00" -- vecser, mode
);
type vm_stat_type is record -- virt memory status port
ack : slbit; -- acknowledge
err : slbit; -- error (see err_xxx for reason)
fail : slbit; -- failure (machine check)
err_odd : slbit; -- abort: odd address error
err_mmu : slbit; -- abort: mmu reject
err_nxm : slbit; -- abort: non-existing memory
err_iobto : slbit; -- abort: non-existing I/O resource
err_rsv : slbit; -- abort: red stack violation
trap_ysv : slbit; -- trap: yellow stack violation
trap_mmu : slbit; -- trap: mmu trap
end record vm_stat_type;
constant vm_stat_init : vm_stat_type := (others=>'0');
type em_mreq_type is record -- external memory - master request
req : slbit; -- request
we : slbit; -- write enable
be : slv2; -- byte enables
cancel : slbit; -- cancel request
addr : slv22_1; -- address
din : slv16; -- data in (input to memory)
end record em_mreq_type;
constant em_mreq_init : em_mreq_type := (
'0','0',"00",'0', -- req, we, be, cancel
(others=>'0'),(others=>'0') -- addr, din
);
type em_sres_type is record -- external memory - slave response
ack_r : slbit; -- acknowledge read
ack_w : slbit; -- acknowledge write
dout : slv16; -- data out (output from memory)
end record em_sres_type;
constant em_sres_init : em_sres_type := (
'0','0', -- ack_r, ack_w
(others=>'0') -- dout
);
type mmu_cntl_type is record -- mmu control port
req : slbit; -- translate request
wacc : slbit; -- write access
macc : slbit; -- modify access (r-m-w sequence)
cacc : slbit; -- console access (bypass mmu)
dspace : slbit; -- dspace access
mode : slv2; -- processor mode
trap_done : slbit; -- mmu trap taken (set mmr0 bit)
end record mmu_cntl_type;
constant mmu_cntl_init : mmu_cntl_type := (
'0','0','0','0', -- req, wacc, macc, cacc
'0',"00",'0' -- dspace, mode, trap_done
);
type mmu_stat_type is record -- mmu status port
vaok : slbit; -- virtual address valid
trap : slbit; -- mmu trap request
ena_mmu : slbit; -- mmu enable (mmr0 bit 0)
ena_22bit : slbit; -- mmu in 22 bit mode (mmr3 bit 4)
ena_ubmap : slbit; -- ubmap enable (mmr3 bit 5)
end record mmu_stat_type;
constant mmu_stat_init : mmu_stat_type := (others=>'0');
type mmu_moni_type is record -- mmu monitor port
istart : slbit; -- instruction start
idone : slbit; -- instruction done
pc : slv16; -- PC of new instruction
regmod : slbit; -- register modified
regnum : slv3; -- register number
delta : slv4; -- register offset
isdec : slbit; -- offset to be subtracted
trace_prev : slbit; -- use mmr12 trace state of prev. state
end record mmu_moni_type;
constant mmu_moni_init : mmu_moni_type := (
'0','0',(others=>'0'), -- istart, idone, pc
'0',"000","0000", -- regmod, regnum, delta
'0','0' -- isdec, trace_prev
);
type mmu_mmr0_type is record -- MMU mmr0
abo_nonres : slbit; -- abort non resident
abo_length : slbit; -- abort page length
abo_rdonly : slbit; -- abort read-only
trap_mmu : slbit; -- trap management
ena_trap : slbit; -- enable traps
inst_compl : slbit; -- instruction complete
page_mode : slv2; -- page mode
dspace : slbit; -- address space (D=1, I=0)
page_num : slv3; -- page number
ena_mmu : slbit; -- enable memory management
trace_prev : slbit; -- mmr12 trace status in prev. state
end record mmu_mmr0_type;
constant mmu_mmr0_init : mmu_mmr0_type := (
inst_compl=>'0', page_mode=>"00", page_num=>"000",
others=>'0'
);
type mmu_mmr1_type is record -- MMU mmr1
rb_delta : slv5; -- RB: amount change
rb_num : slv3; -- RB: register number
ra_delta : slv5; -- RA: amount change
ra_num : slv3; -- RA: register number
end record mmu_mmr1_type;
constant mmu_mmr1_init : mmu_mmr1_type := (
"00000","000", -- rb_...
"00000","000" -- ra_...
);
type mmu_mmr3_type is record -- MMU mmr3
ena_ubmap : slbit; -- enable unibus mapping
ena_22bit : slbit; -- enable 22 bit mapping
dspace_km : slbit; -- enable dspace kernel
dspace_sm : slbit; -- enable dspace supervisor
dspace_um : slbit; -- enable dspace user
end record mmu_mmr3_type;
constant mmu_mmr3_init : mmu_mmr3_type := (others=>'0');
-- control port definitions --------------------------------------------------
type cp_cntl_type is record -- control port control
req : slbit; -- request
func : slv5; -- function
rnum : slv3; -- register number
end record cp_cntl_type;
constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
constant c_cpfunc_start : slv5 := "00001"; -- sta : cpu start
constant c_cpfunc_stop : slv5 := "00010"; -- sto : cpu stop
constant c_cpfunc_step : slv5 := "00011"; -- cont : cpu step
constant c_cpfunc_creset : slv5 := "00100"; -- step : cpu cpu reset
constant c_cpfunc_breset : slv5 := "00101"; -- rst : cpu bus reset
constant c_cpfunc_suspend : slv5 := "00110"; -- rst : cpu suspend
constant c_cpfunc_resume : slv5 := "00111"; -- rst : cpu resume
constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
type cp_stat_type is record -- control port status
cmdbusy : slbit; -- command busy
cmdack : slbit; -- command acknowledge
cmderr : slbit; -- command error
cmdmerr : slbit; -- command memory access error
cpugo : slbit; -- CPU go state
cpustep : slbit; -- CPU step flag
cpuwait : slbit; -- CPU wait flag
cpususp : slbit; -- CPU susp flag
cpurust : slv4; -- CPU run status
suspint : slbit; -- internal suspend
suspext : slbit; -- external suspend
end record cp_stat_type;
constant cp_stat_init : cp_stat_type := (
'0','0','0','0', -- cmd...
'0','0','0','0', -- cpu...
(others=>'0'), -- cpurust
'0','0' -- susp...
);
type cp_addr_type is record -- control port address
addr : slv22_1; -- address
racc : slbit; -- ibus remote access
be : slv2; -- byte enables
ena_22bit : slbit; -- enable 22 bit mode
ena_ubmap : slbit; -- enable unibus mapper
end record cp_addr_type;
constant cp_addr_init : cp_addr_type := (
(others=>'0'), -- addr
'0',"00", -- racc, be
'0','0' -- ena_...
);
-- debug and monitoring port definitions -------------------------------------
type dm_stat_se_type is record -- debug and monitor status - sequencer
idle : slbit; -- sequencer ideling (for pdp11_dcmon)
cpbusy : slbit; -- in cp states
istart : slbit; -- instruction start
idec : slbit; -- instruction decode (for ibd_kw11p)
idone : slbit; -- instruction done
itimer : slbit; -- instruction timer (for ibdr_rhrp)
pcload : slbit; -- PC loaded (flow change)
vfetch : slbit; -- vector fetch
snum : slv8; -- current state number
end record dm_stat_se_type;
constant dm_stat_se_init : dm_stat_se_type := (
'0','0', -- idle,cpbusy
'0','0','0','0', -- istart,idec,idone,itimer
'0','0', -- pcload,vfetch
(others=>'0') -- snum
);
constant c_snum_f_con: integer := 0; -- control state flag
constant c_snum_f_ins: integer := 1; -- instruction state flag
constant c_snum_f_vec: integer := 2; -- vector state flag
constant c_snum_f_err: integer := 3; -- error state flag
constant c_snum_f_vmw: integer := 7; -- vm wait flag
type dm_stat_dp_type is record -- debug and monitor status - dpath
pc : slv16; -- pc
psw : psw_type; -- psw
psr_we: slbit; -- psr_we
ireg : slv16; -- ireg
ireg_we : slbit; -- ireg we
dsrc : slv16; -- dsrc register
dsrc_we: slbit; -- dsrc we
ddst : slv16; -- ddst register
ddst_we : slbit; -- ddst we
dtmp : slv16; -- dtmp register
dtmp_we : slbit; -- dtmp we
dres : slv16; -- dres bus
cpdout_we : slbit; -- cpdout we
gr_adst : slv3; -- gr dst regsiter
gr_mode : slv2; -- gr mode
gr_bytop : slbit; -- gr bytop
gr_we : slbit; -- gr we
end record dm_stat_dp_type;
constant dm_stat_dp_init : dm_stat_dp_type := (
(others=>'0'), -- pc
psw_init,'0', -- psw,psr_we
(others=>'0'),'0', -- ireg,ireg_we
(others=>'0'),'0', -- dsrc,dsrc_we
(others=>'0'),'0', -- ddst,ddst_we
(others=>'0'),'0', -- dtmp,dtmp_we
(others=>'0'), -- dres
'0', -- cpdout_we
(others=>'0'),(others=>'0'), -- gr_adst, gr_mode
'0','0' -- gr_bytop, gr_we
);
type dm_stat_vm_type is record -- debug and monitor status - vmbox
vmcntl : vm_cntl_type; -- vmbox: control
vmaddr : slv16; -- vmbox: address
vmdin : slv16; -- vmbox: data in
vmstat : vm_stat_type; -- vmbox: status
vmdout : slv16; -- vmbox: data out
ibmreq : ib_mreq_type; -- ibus: request
ibsres : ib_sres_type; -- ibus: response
emmreq : em_mreq_type; -- external memory: request
emsres : em_sres_type; -- external memory: response
end record dm_stat_vm_type;
constant dm_stat_vm_init : dm_stat_vm_type := (
vm_cntl_init, -- vmcntl
(others=>'0'), -- vmaddr
(others=>'0'), -- vmdin
vm_stat_init, -- vmstat
(others=>'0'), -- vmdout
ib_mreq_init, -- ibmreq
ib_sres_init, -- ibsres
em_mreq_init, -- emmreq
em_sres_init -- emsres
);
type dm_stat_co_type is record -- debug and monitor status - core
cpugo : slbit; -- cpugo state flag
cpustep : slbit; -- cpustep state flag
cpususp : slbit; -- cpususp state flag
suspint : slbit; -- suspint state flag
suspext : slbit; -- suspext state flag
end record dm_stat_co_type;
constant dm_stat_co_init : dm_stat_co_type := (
'0','0','0', -- cpu...
'0','0' -- susp...
);
type dm_stat_ca_type is record -- debug and monitor status - cache
rd : slbit; -- read request
wr : slbit; -- write request
rdhit : slbit; -- read hit
wrhit : slbit; -- write hit
rdmem : slbit; -- read memory
wrmem : slbit; -- write memory
rdwait : slbit; -- read wait
wrwait : slbit; -- write wait
end record dm_stat_ca_type;
constant dm_stat_ca_init : dm_stat_ca_type := (
'0','0','0','0', -- rd,wr,rdhit,wrhit
'0','0','0','0' -- rdmem,wrmem,rdwait,wrwait
);
type dm_stat_exp_type is record -- debug and monitor - sys70 export
dp_pc : slv16; -- DM_STAT_DP: pc
dp_psw : psw_type; -- DM_STAT_DP: psw
dp_dsrc : slv16; -- DM_STAT_DP: dsrc register
se_idec : slbit; -- DM_STAT_SE: instruction decode
se_itimer : slbit; -- DM_STAT_SE: instruction timer
end record dm_stat_exp_type;
constant dm_stat_exp_init : dm_stat_exp_type := (
(others=>'0'), -- dp_pc
psw_init, -- dp_psw
(others=>'0'), -- dp_dsrc
'0','0' -- se_idec,se_itimer
);
-- rbus interface definitions ------------------------------------------------
constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gr 0
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gr 1
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gr 2
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gr 3
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gr 4
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gr 5
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gr 6 (sp)
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gr 7 (pc)
constant c_rbaddr_membe: slv5 := "10000"; -- R/W memory write byte enables
constant c_init_rbf_greset: integer := 0;
subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
constant c_stat_rbf_suspext: integer := 9; -- stat field: suspext
constant c_stat_rbf_suspint: integer := 8; -- stat field: suspint
subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
constant c_stat_rbf_cpususp: integer := 3; -- stat field: cpususp
constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
subtype c_membe_rbf_be is integer range 1 downto 0; -- membe: be's
constant c_membe_rbf_stick: integer := 2; -- membe: sticky flag
-- -------------------------------------
component pdp11_gr is -- general registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
ASRC : in slv3; -- source register number
ADST : in slv3; -- destination register number
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
RSET : in slbit; -- register set
WE : in slbit; -- write enable
BYTOP : in slbit; -- byte operation (write low byte only)
PCINC : in slbit; -- increment PC
DSRC : out slv16; -- source register data
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end component;
constant c_gr_r5 : slv3 := "101"; -- register number of r5
constant c_gr_sp : slv3 := "110"; -- register number of SP
constant c_gr_pc : slv3 := "111"; -- register number of PC
component pdp11_psr is -- processor status word register
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
DIN : in slv16; -- input data
CCIN : in slv4; -- cc input
CCWE : in slbit; -- enable update cc
WE : in slbit; -- write enable (from DIN)
FUNC : in slv3; -- write function (from DIN)
PSW : out psw_type; -- current psw
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
constant c_psr_func_wall : slv3 := "100"; -- write all fields
component pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end component;
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
component pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
component pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
component pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GR_DSRC : in slv16; -- 'src' data from GR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state (load dd_low)
S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle)
S_DIV_CR : in slbit; -- s_opg_div_cr state (remainder corr.)
S_DIV_SR : in slbit; -- s_opg_div_sr state (store remainder)
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: remainder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_QUIT : out slbit; -- division: abort (0/ or /0 or V=1)
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end component;
constant c_munit_func_mul : slv2 := "00"; -- MUL
constant c_munit_func_div : slv2 := "01"; -- DIV
constant c_munit_func_ash : slv2 := "10"; -- ASH
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
component pdp11_mmu_padr is -- mmu PAR/PDR register set
port (
CLK : in slbit; -- clock
MODE : in slv2; -- mode
APN : in slv4; -- augmented page number (1+3 bit)
AIB_WE : in slbit; -- update AIB
AIB_SETA : in slbit; -- set access AIB
AIB_SETW : in slbit; -- set write AIB
PARPDR : out parpdr_type; -- combined PAR/PDR
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mmu is -- mmu - memory management unit
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
BRESET : in slbit; -- bus reset
CNTL : in mmu_cntl_type; -- control port
VADDR : in slv16; -- virtual address
MONI : in mmu_moni_type; -- monitor port
STAT : out mmu_stat_type; -- status port
PADDRH : out slv16; -- physical address (upper 16 bit)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_vmbox is -- virtual memory
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
CRESET : in slbit; -- cpu reset
BRESET : in slbit; -- bus reset
CP_ADDR : in cp_addr_type; -- console port address
VM_CNTL : in vm_cntl_type; -- vm control port
VM_ADDR : in slv16; -- vm address
VM_DIN : in slv16; -- vm data in
VM_STAT : out vm_stat_type; -- vm status port
VM_DOUT : out slv16; -- vm data out
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
MMU_MONI : in mmu_moni_type; -- mmu monitor port
IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
);
end component;
component pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status - dpath
);
end component;
component pdp11_decode is -- instruction decoder
port (
IREG : in slv16; -- input instruction word
STAT : out decode_stat_type -- status output
);
end component;
component pdp11_sequencer is -- cpu sequencer
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
CP_CNTL : in cp_cntl_type; -- console port control
VM_STAT : in vm_stat_type; -- virtual memory status port
INT_PRI : in slv3; -- interrupt priority
INT_VECT : in slv9_2; -- interrupt vector
INT_ACK : out slbit; -- interrupt acknowledge
CRESET : out slbit; -- cpu reset
BRESET : out slbit; -- bus reset
MMU_MONI : out mmu_moni_type; -- mmu monitor port
DP_CNTL : out dpath_cntl_type; -- data path control
VM_CNTL : out vm_cntl_type; -- virtual memory control port
CP_STAT : out cp_stat_type; -- console port status
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
HBPT : in slbit; -- hardware bpt
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_SE : out dm_stat_se_type -- debug and monitor status - sequencer
);
end component;
component pdp11_irq is -- interrupt requester
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- bus reset
INT_ACK : in slbit; -- interrupt acknowledge from CPU
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PRI : out slv3; -- interrupt priority
VECT : out slv9_2; -- interrupt vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_reg70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component pdp11_cache is -- cache
generic (
TWIDTH : positive := 9); -- tag width (5 to 9)
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type; -- em response
FMISS : in slbit; -- force miss
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_CA : out dm_stat_ca_type -- debug and monitor status - cache
);
end component;
component pdp11_core is -- full processor core
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL : in cp_cntl_type; -- console control port
CP_ADDR : in cp_addr_type; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT : out cp_stat_type; -- console status port
CP_DOUT : out slv16; -- console data out
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
HBPT : in slbit; -- hardware bpt
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
CRESET : out slbit; -- cpu reset
BRESET : out slbit; -- bus reset
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
DM_STAT_SE : out dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_tmu is -- trace and monitor unit
port (
CLK : in slbit; -- clock
ENA : in slbit := '0'; -- enable trace output
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
);
end component;
-- this definition logically belongs into a 'for test benches' section'
-- it is here for convenience to simplify instantiations.
constant sbcntl_sbf_tmu : integer := 12;
component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := sbcntl_sbf_tmu); -- SB_CNTL for tmu
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
);
end component;
component pdp11_du_drv is -- display unit low level driver
generic (
CDWIDTH : positive := 3); -- clock divider width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
ROW0 : in slv22; -- led row 0 (22 leds, top)
ROW1 : in slv16; -- led row 1 (16 leds)
ROW2 : in slv16; -- led row 2 (16 leds)
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
SWOPT : out slv8; -- option pattern from du
SWOPT_RDY : out slbit; -- marks update of swopt
DU_SCLK : out slbit; -- DU: sclk
DU_SS_N : out slbit; -- DU: ss_n
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
DU_MISO : in slbit -- DU: miso (master in, slave out)
);
end component;
component pdp11_bram is -- BRAM based ext. memory dummy
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end component;
component pdp11_bram_memctl is -- BRAM based memctl
generic (
MAWIDTH : positive := 4; -- mux address width
NBLOCK : positive := 11); -- number of 16 kByte blocks
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32 -- data out (memory view)
);
end component;
component pdp11_statleds is -- status leds
port (
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
STATLEDS : out slv8 -- 8 bit CPU status
);
end component;
component pdp11_ledmux is -- hio led mux
generic (
LWIDTH : positive := 8); -- led width
port (
SEL : in slbit; -- select (0=stat;1=dr)
STATLEDS : in slv8; -- 8 bit CPU status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
LED : out slv(LWIDTH-1 downto 0) -- hio leds
);
end component;
component pdp11_dspmux is -- hio dsp mux
generic (
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
port (
SEL : in slv2; -- select
ABCLKDIV : in slv16; -- serport clock divider
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
DISPREG : in slv16; -- display register
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
end component;
component pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv16 := rbaddr_cpu0_core;
RB_ADDR_IBUS : slv16 := rbaddr_cpu0_ibus);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv4; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
GRESET : out slbit; -- general reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end component;
component pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus request (slave)
RB_SRES : out rb_sres_type; -- rbus response
RB_STAT : out slv4; -- rbus status flags
RB_LAM_CPU : out slbit; -- rbus lam (cpu)
GRESET : out slbit; -- general reset (from rbus)
CRESET : out slbit; -- cpu reset (from cp)
BRESET : out slbit; -- bus reset (from cp or cpu)
CP_STAT : out cp_stat_type; -- console port status
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PERFEXT : in slv8; -- cpu external perf counter signals
IB_MREQ : out ib_mreq_type; -- ibus request (master)
IB_SRES : in ib_sres_type; -- ibus response (from IO system)
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_EXP : out dm_stat_exp_type -- debug and monitor - sys70 exports
);
end component;
component pdp11_hio70 is -- hio led and dsp for sys70
generic (
LWIDTH : positive := 8; -- led width
DCWIDTH : positive := 2); -- digit counter width (2 or 3)
port (
SEL_LED : in slbit; -- led select (0=stat;1=dr)
SEL_DSP : in slv2; -- dsp select
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_EXP : in dm_stat_exp_type; -- debug and monitor - exports
ABCLKDIV : in slv16; -- serport clock divider
DISPREG : in slv16; -- display register
LED : out slv(LWIDTH-1 downto 0); -- hio leds
DSP_DAT : out slv(4*(2**DCWIDTH)-1 downto 0) -- display data
);
end component;
component pdp11_dmscnt is -- debug&moni: state counter
generic (
RB_ADDR : slv16 := rbaddr_dmscnt_off);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_dmcmon is -- debug&moni: cpu monitor
generic (
RB_ADDR : slv16 := rbaddr_dmcmon_off;
AWIDTH : natural := 8;
SNUM : boolean := false);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
);
end component;
component pdp11_dmhbpt is -- debug&moni: hardware breakpoint
generic (
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
NUNIT : natural := 2);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
HBPT : out slbit -- hw break flag
);
end component;
component pdp11_dmhbpt_unit is -- dmhbpt - indivitial unit
generic (
RB_ADDR : slv16 := rbaddr_dmhbpt_off;
INDEX : natural := 0);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
HBPT : out slbit -- hw break flag
);
end component;
component pdp11_dmpcnt is -- debug&moni: performance counters
generic (
RB_ADDR : slv16 := rbaddr_dmpcnt_off; -- rbus address
VERS : slv8 := slv(to_unsigned(0, 8)); -- counter layout version
CENA : slv32 := (others=>'1')); -- counter enables
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
PERFSIG : in slv32 -- signals to count
);
end component;
-- ----- move later to pdp11_conf --------------------------------------------
constant conf_vect_pirq : integer := 8#240#;
constant conf_pri_pirq_1 : integer := 1;
constant conf_pri_pirq_2 : integer := 2;
constant conf_pri_pirq_3 : integer := 3;
constant conf_pri_pirq_4 : integer := 4;
constant conf_pri_pirq_5 : integer := 5;
constant conf_pri_pirq_6 : integer := 6;
constant conf_pri_pirq_7 : integer := 7;
end package pdp11;
| gpl-3.0 | 1a0d3c42751fdcc3e42d1ef209ee57d1 | 0.503617 | 3.799657 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_core.vhd | 1 | 8,419 | -- $Id: pdp11_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_core - syn
-- Description: pdp11: full processor core
--
-- Dependencies: pdp11_vmbox
-- pdp11_dpath
-- pdp11_decode
-- pdp11_sequencer
-- pdp11_irq
-- pdp11_reg70
-- ibus/ib_sres_or_4
--
-- Test bench: tb/tb_pdp11core
-- tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.4.4 drop ITIMER, now routed via DM_STAT_SE.itimer
-- 2016-10-03 812 1.4.3 drop SNUM signal, not used anymore
-- 2015-07-19 702 1.4.2 add DM_STAT_SE port; re-arrange DM_STAT_CO usage
-- 2015-07-05 697 1.4.1 wire istart,istop,cpustep to DM_STAT_CO
-- 2015-06-26 695 1.4.1 connect SNUM (current state number)
-- 2015-05-09 679 1.4 start/stop/suspend overhaul; reset overhaul
-- 2015-04-30 670 1.3.2 rename pdp11_sys70 -> pdp11_reg70
-- 2011-11-18 427 1.3.1 now numeric_std clean
-- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox
-- CP_ADDR now from in port; dpath CP_DIN now from in
-- port; out port CP_DOUT now from _dpath
-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.2.4 rename pdp11_ibres_ -> ib_sres_
-- 2008-04-25 138 1.2.3 BRESET: add for _vmbox, use for _irq
-- 2008-04-19 137 1.2.2 add DM_STAT_(DP|VM|CO) port; added pdp11_sys70
-- 2008-03-02 121 1.2.1 remove snoopers
-- 2008-02-17 117 1.2 add em_(mreq|sres) interface for memory
-- 2008-01-20 112 1.1.3 add BRESET port (intbus reset), rename P->BRESET
-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
-- 2008-01-01 109 1.1.1 _vmbox w/ IB_SRES_(CPU|EXT)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_core is -- full processor core
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CP_CNTL : in cp_cntl_type; -- console control port
CP_ADDR : in cp_addr_type; -- console address port
CP_DIN : in slv16; -- console data in
CP_STAT : out cp_stat_type; -- console status port
CP_DOUT : out slv16; -- console data out
ESUSP_O : out slbit; -- external suspend output
ESUSP_I : in slbit; -- external suspend input
HBPT : in slbit; -- hardware bpt
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
EM_MREQ : out em_mreq_type; -- external memory: request
EM_SRES : in em_sres_type; -- external memory: response
CRESET : out slbit; -- cpu reset
BRESET : out slbit; -- bus reset
IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
DM_STAT_SE : out dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
);
end pdp11_core;
architecture syn of pdp11_core is
signal GRESET : slbit := '0';
signal CRESET_L : slbit := '0';
signal BRESET_L : slbit := '0';
signal VM_CNTL : vm_cntl_type := vm_cntl_init;
signal VM_STAT : vm_stat_type := vm_stat_init;
signal MMU_MONI : mmu_moni_type := mmu_moni_init;
signal DP_CNTL : dpath_cntl_type := dpath_cntl_init;
signal DP_STAT : dpath_stat_type := dpath_stat_init;
signal DP_PSW : psw_type := psw_init;
signal DP_PC : slv16 := (others=>'0');
signal DP_IREG : slv16 := (others=>'0');
signal VM_DIN : slv16 := (others=>'0');
signal VM_ADDR : slv16 := (others=>'0');
signal VM_DOUT : slv16 := (others=>'0');
signal ID_STAT : decode_stat_type := decode_stat_init;
signal INT_PRI : slv3 := (others=>'0');
signal INT_VECT : slv9_2 := (others=>'0');
signal CP_STAT_L : cp_stat_type := cp_stat_init;
signal INT_ACK : slbit := '0';
signal IB_SRES_DP : ib_sres_type := ib_sres_init;
signal IB_SRES_SEQ : ib_sres_type := ib_sres_init;
signal IB_SRES_IRQ : ib_sres_type := ib_sres_init;
signal IB_SRES_SYS : ib_sres_type := ib_sres_init;
signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
begin
GRESET <= RESET;
VMBOX : pdp11_vmbox
port map (
CLK => CLK,
GRESET => GRESET,
CRESET => CRESET_L,
BRESET => BRESET_L,
CP_ADDR => CP_ADDR,
VM_CNTL => VM_CNTL,
VM_ADDR => VM_ADDR,
VM_DIN => VM_DIN,
VM_STAT => VM_STAT,
VM_DOUT => VM_DOUT,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
MMU_MONI => MMU_MONI,
IB_MREQ_M => IB_MREQ,
IB_SRES_CPU => IB_SRES,
IB_SRES_EXT => IB_SRES_M,
DM_STAT_VM => DM_STAT_VM
);
DPATH : pdp11_dpath
port map (
CLK => CLK,
CRESET => CRESET_L,
CNTL => DP_CNTL,
STAT => DP_STAT,
CP_DIN => CP_DIN,
CP_DOUT => CP_DOUT,
PSWOUT => DP_PSW,
PCOUT => DP_PC,
IREG => DP_IREG,
VM_ADDR => VM_ADDR,
VM_DOUT => VM_DOUT,
VM_DIN => VM_DIN,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DP,
DM_STAT_DP => DM_STAT_DP
);
IDEC : pdp11_decode
port map (
IREG => DP_IREG,
STAT => ID_STAT
);
SEQ : pdp11_sequencer
port map (
CLK => CLK,
GRESET => GRESET,
PSW => DP_PSW,
PC => DP_PC,
IREG => DP_IREG,
ID_STAT => ID_STAT,
DP_STAT => DP_STAT,
CP_CNTL => CP_CNTL,
VM_STAT => VM_STAT,
INT_PRI => INT_PRI,
INT_VECT => INT_VECT,
INT_ACK => INT_ACK,
CRESET => CRESET_L,
BRESET => BRESET_L,
MMU_MONI => MMU_MONI,
DP_CNTL => DP_CNTL,
VM_CNTL => VM_CNTL,
CP_STAT => CP_STAT_L,
ESUSP_O => ESUSP_O,
ESUSP_I => ESUSP_I,
HBPT => HBPT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SEQ,
DM_STAT_SE => DM_STAT_SE
);
IRQ : pdp11_irq
port map (
CLK => CLK,
BRESET => BRESET_L,
INT_ACK => INT_ACK,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PRI => INT_PRI,
VECT => INT_VECT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IRQ
);
REG70 : pdp11_reg70
port map (
CLK => CLK,
CRESET => CRESET_L,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SYS
);
IB_SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_DP,
IB_SRES_2 => IB_SRES_SEQ,
IB_SRES_3 => IB_SRES_IRQ,
IB_SRES_4 => IB_SRES_SYS,
IB_SRES_OR => IB_SRES
);
IB_MREQ_M <= IB_MREQ;
CP_STAT <= CP_STAT_L;
CRESET <= CRESET_L;
BRESET <= BRESET_L;
DM_STAT_CO.cpugo <= CP_STAT_L.cpugo;
DM_STAT_CO.cpustep <= CP_STAT_L.cpustep;
DM_STAT_CO.cpususp <= CP_STAT_L.cpususp;
DM_STAT_CO.suspint <= CP_STAT_L.suspint;
DM_STAT_CO.suspext <= CP_STAT_L.suspext;
end syn;
| gpl-3.0 | 9787a79ec4d4399fbf923a3e514e092b | 0.530704 | 3.097498 | false | false | false | false |
wfjm/w11 | rtl/vlib/memlib/tb/tbd_fifo_simple_dram.vhd | 1 | 2,014 | -- $Id: tbd_fifo_simple_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tbd_fifo_simple_dram - syn
-- Description: Wrapper for fifo_simple_dram to avoid records & generics. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: fifo_simple_dram
--
-- To test: fifo_simple_dram
--
-- Target Devices: generic
--
-- Tool versions: xst 14.7; viv 2017.2; ghdl 0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-09 1109 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.memlib.all;
entity tbd_fifo_simple_dram is -- fifo, CE/WE, dram based [tb design]
-- generic: AWIDTH=4; DWIDTH=16
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv16; -- input data
DO : out slv16; -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv4 -- number of used slots
);
end tbd_fifo_simple_dram;
architecture syn of tbd_fifo_simple_dram is
begin
FIFO : fifo_simple_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
WE => WE,
DI => DI,
DO => DO,
EMPTY => EMPTY,
FULL => FULL,
SIZE => SIZE
);
end syn;
| gpl-3.0 | f039665a2e44cd4db7f8d3251d520ccd | 0.478153 | 3.996032 | false | false | false | false |
rongcuid/lots-of-subleq-cpus | Subleq Pipelined/src/BRAM.vhd | 1 | 4,232 | ----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date: 06/29/2017 07:16:10 PM
-- Design Name:
-- Module Name: BRAM
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- This is a single port BRAM
entity BRAM_SP is
generic ( WIDTH : integer := 32;
DEPTH : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(DEPTH_LOG-1 downto 0);
di : in std_logic_vector(WIDTH-1 downto 0);
do : out std_logic_vector(WIDTH-1 downto 0)
);
end BRAM_SP;
-- This is a write first memory which should be inferred as a BRAM
architecture syn of BRAM_SP is
type ram_type is array(DEPTH-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal data: ram_type;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
if we = '1' then
data(to_integer(unsigned(addr))) <= di;
do <= di;
else
do <= data(to_integer(unsigned(addr)));
end if;
end if;
end if;
end process;
end syn;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- This is a dual port BRAM
entity BRAM_DP is
generic ( WIDTH : integer := 32;
DEPTH : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
awe : in std_logic;
aen : in std_logic;
aaddr : in std_logic_vector(DEPTH_LOG-1 downto 0);
adi : in std_logic_vector(WIDTH-1 downto 0);
ado : out std_logic_vector(WIDTH-1 downto 0);
bwe : in std_logic;
ben : in std_logic;
baddr : in std_logic_vector(DEPTH_LOG-1 downto 0);
bdi : in std_logic_vector(WIDTH-1 downto 0);
bdo : out std_logic_vector(WIDTH-1 downto 0)
);
end BRAM_DP;
architecture syn of BRAM_DP is
type ram_type is array(DEPTH-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal RAM: ram_type;
signal read_addra, read_addrb : std_logic_vector(DEPTH_LOG-1 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (aen = '1') then
if (awe = '1') then
RAM(to_integer(unsigned(aaddr))) <= adi;
end if;
read_addra <= aaddr;
end if;
if (ben = '1') then
if (bwe = '1') then
RAM(to_integer(unsigned(baddr))) <= bdi;
end if;
read_addrb <= baddr;
end if;
end if;
end process;
ado <= RAM(to_integer(unsigned(read_addra)));
bdo <= RAM(to_integer(unsigned(read_addrb)));
end architecture syn;
-- architecture syn of BRAM_DP is
-- type ram_type is array(DEPTH-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
-- signal data: ram_type;
-- begin
-- portA : process (clk)
-- begin
-- if clk'event and clk = '1' then
-- if aen = '1' then
-- if awe = '1' then
-- data(to_integer(unsigned(aaddr))) <= adi;
-- ado <= adi;
-- else
-- ado <= data(to_integer(unsigned(aaddr)));
-- end if;
-- end if;
-- end if;
-- end process portA;
-- portB : process (clk)
-- begin
-- if clk'event and clk = '1' then
-- if ben = '1' then
-- if bwe = '1' then
-- data(to_integer(unsigned(baddr))) <= bdi;
-- bdo <= bdi;
-- else
-- bdo <= data(to_integer(unsigned(baddr)));
-- end if;
-- end if;
-- end if;
-- end process portB;
-- end architecture syn;
| gpl-3.0 | 9fec40930bf15444663e29725604ad1f | 0.569707 | 3.503311 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4/tb/nexys4_cram_dummy.vhd | 1 | 3,378 | -- $Id: nexys4_cram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys4_cram_dummy - syn
-- Description: nexys4 target (base; serport loopback, cram protect)
--
-- Dependencies: -
-- To test: tb_nexys4_cram
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys4_cram_dummy is -- NEXYS 4 dummy (base+cram)
-- implements nexys4_cram_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end nexys4_cram_dummy;
architecture syn of nexys4_cram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
| gpl-3.0 | 781033ce2389b74f39da8c45fffa853d | 0.491711 | 3.229446 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop1_n4d.vhd | 1 | 6,751 | -- $Id: sys_tst_serloop1_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n4d - syn
-- Description: Tester serial link for nexys4d (serport_1clock case)
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/bp_rs232_4line_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2022.1; ghdl 0.33-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1 409 421 12 0 189
-- 2019-02-02 1108 2018.3 xc7a100t-1 409 456 16 0 200
-- 2019-02-02 1108 2017.2 xc7a100t-1 409 446 16 0 186
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version (derived from sys_tst_serloop1_n4)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n4d is -- top level
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_serloop1_n4d;
architecture syn of sys_tst_serloop1_n4d is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
GEN_CLKSYS : s7_cmt_sfs -- clock generator -------------------
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => sys_conf_clkdiv_msecdiv)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
DSP_DP => DSP_DP(3 downto 0)
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 12,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
-- show autobauder clock divisor on msb of display
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
-- setup unused outputs in nexys4d
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
| gpl-3.0 | 86f3077aca0c644bfc399d12e1d90f92 | 0.486595 | 3.337123 | false | false | false | false |
rad-/VHDL-Pong | Pong.vhd | 1 | 14,944 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Pong is
Port (
clk : in STD_LOGIC;
hsync_out : out STD_LOGIC;
vsync_out : out STD_LOGIC;
red_out : out STD_LOGIC;
green_out : out STD_LOGIC;
blue_out : out STD_LOGIC;
kb_clk : in STD_LOGIC;
kb_data : in STD_LOGIC
);
end Pong;
architecture Behavioral of Pong is
component KeyboardController is
Port ( Clock : in STD_LOGIC;
KeyboardClock : in STD_LOGIC;
KeyboardData : in STD_LOGIC;
LeftPaddleDirection : out integer;
RightPaddleDirection : out integer
);
end component;
signal screen_process_enable : STD_LOGIC;
signal horizontalPosition : integer range 0 to 800 := 0;
signal verticalPosition : integer range 0 to 521 := 0;
signal hsyncEnable : STD_LOGIC;
signal vsyncEnable : STD_LOGIC;
signal photonX : integer range 0 to 640 := 0;
signal photonY : integer range 0 to 480 := 0;
constant leftPaddleX : integer := 25;
signal leftPaddleY : integer range 0 to 480 := 240;
constant rightPaddleX : integer := 615;
signal rightPaddleY : integer range 0 to 480 := 240;
signal rightPaddleDirection : integer := 0;
signal leftPaddleDirection : integer := 0;
signal paddleHalfHeight : integer range 0 to 50 := 30;
constant paddleHalfWidth : integer := 6;
constant leftPaddleBackX : integer := leftPaddleX-paddleHalfWidth;
constant leftPaddleFrontX : integer := leftPaddleX+paddleHalfWidth;
constant rightPaddleFrontX : integer := rightPaddleX-paddleHalfWidth;
constant rightPaddleBackX : integer := rightPaddleX+paddleHalfWidth;
constant paddleBottomLimit : integer := 474;
constant paddleTopLimit : integer := 4;
signal color : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal ballMovementClockCounter : integer range 0 to 1000000 := 0;
signal ballMovementClock : STD_LOGIC := '0';
signal paddleMovementClockCounter : integer range 0 to 1000000 := 0;
signal paddleMovementClock : STD_LOGIC := '0';
constant ballMaxSpeed : integer := 8;
signal ballX : integer range -100 to 640 := 320;
signal ballY : integer range -100 to 480 := 240;
signal ballSpeedX : integer range -100 to 100 := 1;
signal ballSpeedY : integer range -100 to 100 := 1;
constant maxLeftLifes : integer := 5;
constant maxRightLifes : integer := 5;
signal leftLifes : integer range 0 to 5 := maxLeftLifes;
signal rightLifes : integer range 0 to 5 := maxRightLifes;
signal gameOver : STD_LOGIC := '0';
constant leftLifePosition : integer := 179;
constant rightLifePosition : integer := 359;
constant lifeBarWidth : integer := 100;
constant lifeBarHeight : integer := 3;
signal resetBall : STD_LOGIC := '0';
signal resetCounter : integer range 0 to 101 := 0;
begin
kbController : KeyboardController port map ( clk, kb_clk, kb_data, leftPaddleDirection, rightPaddleDirection );
NW_CLK: process (clk) is
variable divider : integer range 0 to 3;
begin
if rising_edge (clk) then
if divider = 3 then
divider := 0;
screen_process_enable <= '1';
else
divider := divider + 1;
screen_process_enable <= '0';
end if;
end if;
end process NW_CLK;
--------------------MAKE THESE ONE CLOCK?-----------------
ballMovementClockScaler : process(clk)
begin
if rising_edge(clk) then
ballMovementClockCounter <= ballMovementClockCounter + 1;
if (ballMovementClockCounter = 500000) then
ballMovementClock <= not ballMovementClock;
ballMovementClockCounter <= 0;
end if;
end if;
end process ballMovementClockScaler;
paddleMovementClockScaler : process(clk)
begin
if rising_edge(clk) then
paddleMovementClockCounter <= paddleMovementClockCounter + 1;
if (paddleMovementClockCounter = 100000) then
paddleMovementClock <= not paddleMovementClock;
paddleMovementClockCounter <= 0;
end if;
end if;
end process paddleMovementClockScaler;
signalTiming : process(screen_process_enable)
begin
if screen_process_enable'event and screen_process_enable = '1' then
if horizontalPosition = 800 then
horizontalPosition <= 0;
verticalPosition <= verticalPosition + 1;
if verticalPosition = 521 then
verticalPosition <= 0;
else
verticalPosition <= verticalPosition + 1;
end if;
else
horizontalPosition <= horizontalPosition + 1;
end if;
end if;
end process signalTiming;
vgaSync : process(screen_process_enable, horizontalPosition, verticalPosition)
begin
if screen_process_enable'event and screen_process_enable = '1' then
if horizontalPosition > 0 and horizontalPosition < 97 then
hsyncEnable <= '0';
else
hsyncEnable <= '1';
end if;
if verticalPosition > 0 and verticalPosition < 3 then
vsyncEnable <= '0';
else
vsyncEnable <= '1';
end if;
end if;
end process vgaSync;
coordinates : process(horizontalPosition, verticalPosition)
begin
photonX <= horizontalPosition - 144;
photonY <= verticalPosition - 31;
end process coordinates;
finishGame : process(leftLifes, rightLifes)
begin
if leftLifes = 0 or rightLifes = 0 then
gameOver <= '1';
end if;
end process finishGame;
colorSetter : process(photonX, photonY, screen_process_enable)
begin
-- Paddle handling
if gameOver = '1' then
-- G
if photonX >= 20 and photonX <= 80 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 20 and photonX <= 30 and photonY >= 190 and photonY <= 300 then
color <= "100";
elsif photonX >= 20 and photonX <= 80 and photonY >= 290 and photonY <= 300 then
color <= "100";
elsif photonX >= 70 and photonX <= 80 and photonY >= 240 and photonY <= 300 then
color <= "100";
elsif photonX >= 50 and photonX <= 80 and photonY >= 240 and photonY <= 250 then
color <= "100";
-- A
elsif photonX >= 90 and photonX <= 150 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 90 and photonX <= 100 and photonY >= 190 and photonY <= 300 then
color <= "100";
elsif photonX >= 140 and photonX <= 150 and photonY >= 190 and photonY <= 300 then
color <= "100";
elsif photonX >= 90 and photonX <= 150 and photonY >= 240 and photonY <= 250 then
color <= "100";
-- M
elsif ((photonX >= 160 and photonX <= 170 and photonY >= 180 and photonY <= 300) or
(photonX >= 170 and photonX <= 220 and photonY >= 190 and photonY <= 200) or
(photonX >= 210 and photonX <= 220 and photonY >= 190 and photonY <= 300) or
(photonX >= 185 and photonX <= 195 and photonY >= 190 and photonY <= 300)) then
color <= "100";
-- E
elsif photonX >= 230 and photonX <= 290 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 230 and photonX <= 290 and photonY >= 235 and photonY <= 245 then
color <= "100";
elsif photonX >= 230 and photonX <= 290 and photonY >= 290 and photonY <= 300 then
color <= "100";
elsif photonX >= 230 and photonX <= 240 and photonY >= 180 and photonY <= 300 then
color <= "100";
-- O
elsif photonX >= 348 and photonX <= 408 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 348 and photonX <= 358 and photonY >= 190 and photonY <= 290 then
color <= "100";
elsif photonX >= 398 and photonX <= 408 and photonY >= 190 and photonY <= 290 then
color <= "100";
elsif photonX >= 348 and photonX <= 408 and photonY >= 290 and photonY <= 300 then
color <= "100";
-- V
elsif photonX >= 418 and photonX <= 448 and photonY >= 270 and photonY <= 300 then
if (photonX - 418) = (photonY - 270) or
(photonX - 419) = (photonY - 270) or
(photonX - 420) = (photonY - 270) or
(photonX - 421) = (photonY - 270) or
(photonX - 422) = (photonY - 270) or
(photonX - 423) = (photonY - 270) or
(photonX - 424) = (photonY - 270) or
(photonX - 425) = (photonY - 270) or
(photonX - 426) = (photonY - 270) or
(photonX - 427) = (photonY - 270) or
(photonX - 428) = (photonY - 270) then
color <= "100";
else
color <= "000";
end if;
elsif photonX >= 449 and photonX <= 478 and photonY >= 270 and photonY <= 300 then
if (478 - photonX) = (photonY - 270) or
(477 - photonX) = (photonY - 270) or
(476 - photonX) = (photonY - 270) or
(475 - photonX) = (photonY - 270) or
(474 - photonX) = (photonY - 270) or
(473 - photonX) = (photonY - 270) or
(472 - photonX) = (photonY - 270) or
(471 - photonX) = (photonY - 270) or
(470 - photonX) = (photonY - 270) or
(469 - photonX) = (photonY - 270) or
(468 - photonX) = (photonY - 270) then
color <= "100";
else
color <= "000";
end if;
elsif (photonX >= 418 and photonX <= 428 and photonY >= 180 and photonY <= 270) or
(photonX >= 468 and photonX <= 478 and photonY >= 180 and photonY <= 270) then
color <= "100";
-- E
elsif photonX >= 488 and photonX <= 548 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 488 and photonX <= 548 and photonY >= 235 and photonY <= 245 then
color <= "100";
elsif photonX >= 488 and photonX <= 548 and photonY >= 290 and photonY <= 300 then
color <= "100";
elsif photonX >= 488 and photonX <= 498 and photonY >= 180 and photonY <= 300 then
color <= "100";
-- R
elsif photonX >= 558 and photonX <= 618 and photonY >= 180 and photonY <= 190 then
color <= "100";
elsif photonX >= 558 and photonX <= 568 and photonY >= 190 and photonY <= 300 then
color <= "100";
elsif photonX >= 608 and photonX <= 618 and photonY >= 190 and photonY <= 250 then
color <= "100";
elsif photonX >= 558 and photonX <= 618 and photonY >= 245 and photonY <= 255 then
color <= "100";
elsif photonX >= 568 and photonX <= 618 and photonY >= 245 and photonY <= 300 then
if (photonX - 568) = (photonY - 255) or
(photonX - 567) = (photonY - 255) or
(photonX - 566) = (photonY - 255) or
(photonX - 565) = (photonY - 255) or
(photonX - 564) = (photonY - 255) or
(photonX - 563) = (photonY - 255) or
(photonX - 562) = (photonY - 255) or
(photonX - 561) = (photonY - 255) or
(photonX - 569) = (photonY - 255) or
(photonX - 570) = (photonY - 255) or
(photonX - 571) = (photonY - 255) or
(photonX - 572) = (photonY - 255) or
(photonX - 573) = (photonY - 255) or
(photonX - 574) = (photonY - 255) then
color <= "100";
else
color <= "000";
end if;
else
color <= "000";
end if;
elsif ((photonX >= leftPaddleBackX) and (photonX <= leftPaddleFrontX)
and (photonY >= leftPaddleY - paddleHalfHeight) and (photonY <= leftPaddleY + paddleHalfHeight)) or
((photonX >= rightPaddleFrontX) and (photonX <= rightPaddleBackX)
and (photonY >= rightPaddleY - paddleHalfHeight) and (photonY <= rightPaddleY + paddleHalfHeight)) then
color <= "111";
-- Dashed Line
elsif (photonX = 319 and photonY mod 16 <= 10) then
color <= "111";
-- Ball
elsif (photonY >= ballY - 2 and photonY <= ballY + 2) and (photonX >= ballX - 2 and photonX <= ballX + 2) then
color <= "111";
elsif (photonY >= ballY - 3 and photonY <= ballY + 3) and (photonX >= ballX - 1 and photonX <= ballX + 1) then
color <= "111";
elsif (photonY >= ballY - 1 and photonY <= ballY + 1) and (photonX >= ballX - 3 and photonX <= ballX + 3) then
color <= "111";
-- green lifebar
elsif (photonX>=leftLifePosition and photonX<leftLifePosition+(leftLifes*20) and photonY>=30 and photonY<=30+lifeBarHeight) or
(photonX>=rightLifePosition and photonX<rightLifePosition+(rightLifes*20) and photonY>=30 and photonY<=30+lifeBarHeight) then
color <= "010";
-- red lifebar
elsif (photonX >= (leftLifePosition+(leftLifes*20)) and photonX <= (leftLifePosition+(20*maxLeftLifes)) and photonY>=30 and photonY<=(30+lifeBarHeight)) or
(photonX>=(rightLifePosition+(rightLifes*20)) and photonX<= (rightLifePosition+(20*maxRightLifes)) and photonY>=30 and photonY<=(30+lifeBarHeight)) then
color <= "100";
-- background
else
color <= "000";
end if;
end process colorSetter;
leftPaddleMovement : process(paddleMovementClock)
begin
if paddleMovementClock'event and paddleMovementClock = '1' then
if leftPaddleY + leftPaddleDirection < paddleBottomLimit - paddleHalfHeight
and leftPaddleY + leftPaddleDirection > paddleTopLimit + paddleHalfHeight then
leftPaddleY <= leftPaddleY + leftPaddleDirection;
end if;
end if;
end process leftPaddleMovement;
rightPaddleMovement : process(paddleMovementClock)
begin
if paddleMovementClock'event and paddleMovementClock = '1' then
if rightPaddleY + rightPaddleDirection < paddleBottomLimit - paddleHalfHeight
and rightPaddleY + rightPaddleDirection > paddleTopLimit + paddleHalfHeight then
rightPaddleY <= rightPaddleY + rightPaddleDirection;
end if;
end if;
end process rightPaddleMovement;
ballMovement : process(ballMovementClock,gameOver)
begin
if gameOver = '1' then
ballX <= 319;
ballY <= 239;
ballSpeedX <= 0;
ballSpeedY <= 0;
elsif ballMovementClock'event and ballMovementClock='1' then
if resetBall = '1' then
if resetCounter = 100 then
resetCounter <= 0;
ballX <= 319;
ballY <= 239;
resetBall <= '0';
else
resetCounter <= resetCounter + 1;
end if;
else
if ballX+4 > rightPaddleFrontX and ballX < rightPaddleBackX
and ballY+4 > rightPaddleY-paddleHalfHeight and ballY-4 < rightPaddleY+paddleHalfHeight then
ballX <= rightPaddleFrontX - 4;
ballSpeedY <= (ballY - rightPaddleY) / 8;
ballSpeedX <= -ballMaxSpeed + ballSpeedY;
elsif ballX-4 < leftPaddleFrontX and ballX > leftPaddleBackX
and ballY+4 > leftPaddleY-paddleHalfHeight and ballY-4 < leftPaddleY+paddleHalfHeight then
ballX <= leftPaddleFrontX + 4;
ballSpeedY <= ((ballY - leftPaddleY) / 8);
ballSpeedX <= ballMaxSpeed - ballSpeedY;
elsif ballX + ballSpeedX < 4 then
leftLifes <= leftLifes - 1;
ballX <= -20;
ballY <= -20;
resetBall <= '1';
elsif ballX + ballSpeedX > 635 then
rightLifes <= rightLifes - 1;
ballX <= -20;
ballY <= -20;
resetBall <= '1';
else
ballX <= ballX + ballSpeedX;
end if;
if ballY > 470 then
ballY <= 470;
ballSpeedY <= -ballSpeedY;
elsif ballY < 10 then
ballY <= 10;
ballSpeedY <= -ballSpeedY;
else
ballY <= ballY + ballSpeedY;
end if;
end if;
end if;
end process ballMovement;
draw : process(photonX, photonY, screen_process_enable)
begin
if screen_process_enable'event and screen_process_enable = '1' then
hsync_out <= hsyncEnable;
vsync_out <= vsyncEnable;
if (photonX < 640 and photonY < 480) then
red_out <= color(2);
green_out <= color(1);
blue_out <= color(0);
else
red_out <= '0';
green_out <= '0';
blue_out <= '0';
end if;
end if;
end process draw;
end Behavioral;
| mit | 297e2461f89aabd25fedece3dc2f9480 | 0.65538 | 3.720189 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd | 1 | 11,183 | -- $Id: sys_tst_rlink_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_arty - syn
-- Description: rlink tester design for arty board
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- bplib/bpgen/bp_swibtnled
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- bplib/bpgen/rgbdrv_master
-- bplib/bpgen/rgbdrv_analog_rbus
-- bplib/sysmon/sysmonx_rbus_arty
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_tst_rlink_arty
--
-- Target Devices: generic
-- Tool versions: viv 2015.4-2022.1; ghdl 0.33-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1L 1033 1528 34 3.0 543
-- 2019-02-02 1108 2018.3 xc7a35t-1L 1034 1613 36 3.0 550
-- 2019-02-02 1108 2017.2 xc7a35t-1L 1036 1678 36 3.0 557
-- 2017-06-05 907 2016.4 xc7a35t-1L 1033 1658 36 3.0 544
-- 2016-03-27 753 2015.4 xc7a35t-1L 980 1396 36 3.0 494 meminf
-- 2016-03-13 743 2015.4 xc7a35t-1L 980 1390 64 4.5 514 +XADC
-- 2016-02-20 734 2015.4 xc7a35t-1L 941 1352 64 4.5 478
-- 2016-02-14 731 2015.4 xc7a35t-1L 777 1313 64 4.5 399
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.1.5 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-19 748 1.1.4 define rlink SYSID
-- 2016-03-13 743 1.1.3 hardwire XON=1, all SWI now unused
-- 2016-03-12 741 1.1.2 use sysmonx_rbus_arty now
-- 2016-03-06 740 1.1.1 add A_VPWRN/P to baseline config
-- 2016-03-06 738 1.1 add xadc_rbus
-- 2016-02-20 734 1.0.1 add rgbdrv_analog_rbus for four rgb leds
-- 2016-02-14 731 1.0 Initial version (derived from sys_tst_rlink_b3)
------------------------------------------------------------------------------
-- Usage of Arty Switches, Buttons, LEDs:
--
-- SWI(3:2): no function
-- SWI(1): -unused-
-- SWI(0): -unused-
--
-- LED(3): not SER_MONI.txok (shows tx back pressure)
-- LED(2): SER_MONI.txact (shows tx activity)
-- LED(1): not SER_MONI.rxok (shows rx back pressure)
-- LED(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_arty is -- top level
-- implements arty_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRP : in slv4; -- arty pwrmon (pos)
A_VPWRN : in slv4 -- arty pwrmon (neg)
);
end sys_tst_rlink_arty;
architecture syn of sys_tst_rlink_arty is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB0 : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB2 : rb_sres_type := rb_sres_init;
signal RB_SRES_RGB3 : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RGBCNTL : slv3 := (others=>'0');
signal DIMCNTL : slv12 := (others=>'0');
constant rbaddr_rgb0 : slv16 := x"fc00"; -- fe00/0004: 1111 1100 0000 00xx
constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx
constant rbaddr_rgb2 : slv16 := x"fc08"; -- fe08/0004: 1111 1100 0000 10xx
constant rbaddr_rgb3 : slv16 := x"fc0c"; -- fe0c/0004: 1111 1100 0000 11xx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RGBMSTR : rgbdrv_master
generic map (
DWIDTH => DIMCNTL'length)
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL
);
RGB0 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
RB_ADDR => rbaddr_rgb0)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB0,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED0
);
RGB1 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
RB_ADDR => rbaddr_rgb1)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB1,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED1
);
RGB2 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
RB_ADDR => rbaddr_rgb2)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB2,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED2
);
RGB3 : rgbdrv_analog_rbus
generic map (
DWIDTH => DIMCNTL'length,
RB_ADDR => rbaddr_rgb3)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_RGB3,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
O_RGBLED => O_RGBLED3
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_arty
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
end generate SMRB;
RB_SRES_ORRGB : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_RGB0,
RB_SRES_2 => RB_SRES_RGB1,
RB_SRES_3 => RB_SRES_RGB2,
RB_SRES_4 => RB_SRES_RGB3,
RB_SRES_OR => RB_SRES_RGB
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR1 : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_RGB,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
LED(3) <= not SER_MONI.txok;
LED(2) <= SER_MONI.txact;
LED(1) <= not SER_MONI.rxok;
LED(0) <= SER_MONI.rxact;
end syn;
| gpl-3.0 | 64e509c11ba6827d5ff46f89e68395f2 | 0.507109 | 3.197884 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/rlink_rlbmux.vhd | 1 | 2,704 | -- $Id: rlink_rlbmux.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_rlbmux - syn
-- Description: rlink rlb multiplexer
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
entity rlink_rlbmux is -- rlink rlb multiplexer
port (
SEL : in slbit; -- port select (0:RLB<->P0; 1:RLB<->P1)
RLB_DI : out slv8; -- rlb: data in
RLB_ENA : out slbit; -- rlb: data enable
RLB_BUSY : in slbit; -- rlb: data busy
RLB_DO : in slv8; -- rlb: data out
RLB_VAL : in slbit; -- rlb: data valid
RLB_HOLD : out slbit; -- rlb: data hold
P0_RXDATA : in slv8; -- p0: rx data
P0_RXVAL : in slbit; -- p0: rx valid
P0_RXHOLD : out slbit; -- p0: rx hold
P0_TXDATA : out slv8; -- p0: tx data
P0_TXENA : out slbit; -- p0: tx enable
P0_TXBUSY : in slbit; -- p0: tx busy
P1_RXDATA : in slv8; -- p1: rx data
P1_RXVAL : in slbit; -- p1: rx valid
P1_RXHOLD : out slbit; -- p1: rx hold
P1_TXDATA : out slv8; -- p1: tx data
P1_TXENA : out slbit; -- p1: tx enable
P1_TXBUSY : in slbit -- p1: tx busy
);
end rlink_rlbmux;
architecture syn of rlink_rlbmux is
begin
proc_rlmux : process (SEL, RLB_DO, RLB_VAL, RLB_BUSY,
P0_RXDATA, P0_RXVAL, P0_TXBUSY,
P1_RXDATA, P1_RXVAL, P1_TXBUSY)
begin
P0_TXDATA <= RLB_DO;
P1_TXDATA <= RLB_DO;
if SEL = '0' then
RLB_DI <= P0_RXDATA;
RLB_ENA <= P0_RXVAL;
P0_RXHOLD <= RLB_BUSY;
P0_TXENA <= RLB_VAL;
RLB_HOLD <= P0_TXBUSY;
P1_RXHOLD <= '0';
P1_TXENA <= '0';
else
RLB_DI <= P1_RXDATA;
RLB_ENA <= P1_RXVAL;
P1_RXHOLD <= RLB_BUSY;
P1_TXENA <= RLB_VAL;
RLB_HOLD <= P1_TXBUSY;
P0_RXHOLD <= '0';
P0_TXENA <= '0';
end if;
end process proc_rlmux;
end syn;
| gpl-3.0 | 18c9781bfe85158764c0535f5d498636 | 0.472263 | 3.346535 | false | false | false | false |
sjohann81/hf-risc | mips/platform/spartan3e_nexys2/spartan3e_nexys2.vhd | 2 | 4,656 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 14;
memory_file : string := "code.txt"
);
port ( clk_in: in std_logic;
reset_in: in std_logic;
uart_read: in std_logic;
uart_write: out std_logic
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
signal gpioa_in, gpioa_out, gpioa_ddr: std_logic_vector(7 downto 0);
signal gpio_sig: std_logic := '0';
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (reset_in, clk_in, clock)
begin
if reset_in = '1' then
clock <= '0';
else
if clk_in'event and clk_in='1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, reset_in)
begin
if (reset_in = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
gpioa_in(3) <= uart_read;
uart_write <= gpioa_out(2);
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s;
data_write_periph <= data_write;
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
| gpl-2.0 | bf79e54888965a668f3163cc5a88232f | 0.626933 | 2.606943 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_snhumanio/tst_snhumanio.vhd | 1 | 7,104 | -- $Id: tst_snhumanio.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tst_snhumanio - syn
-- Description: simple stand-alone tester for sn_humanio
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-15 416 1.0.2 fix sensitivity list of proc_next
-- 2011-10-08 412 1.0.1 use better rndm init (so that swi=0 is non-const)
-- 2011-09-17 410 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
-- ----------------------------------------------------------------------------
entity tst_snhumanio is -- tester for rlink
generic (
BWIDTH : positive := 4); -- BTN port width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
SWI : in slv8; -- switch settings
BTN : in slv(BWIDTH-1 downto 0); -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_snhumanio;
architecture syn of tst_snhumanio is
constant c_mode_rndm : slv2 := "00";
constant c_mode_cnt : slv2 := "01";
constant c_mode_swi : slv2 := "10";
constant c_mode_btst : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
allon : slbit; -- all LEDs on if set
cnt : slv16; -- counter
tcnt : slv16; -- swi/btn toggle counter
rndm : slv8; -- random number
swi_1 : slv8; -- last SWI state
btn_1 : slv(BWIDTH-1 downto 0); -- last BTN state
led : slv8; -- LED output state
dsp : slv16; -- display data
dp : slv4; -- display decimal points
end record regs_type;
-- the rndm start value is /= 0 because a seed of 0 with a SWI setting of 0
-- will result in a 0-0-0 sequence. The 01010101 start will get trapped in a
-- constant sequence with a 01100011 switch setting, which is rather unlikely.
constant rndminit : slv8 := "01010101";
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
c_mode_rndm, -- mode
'0', -- allon
(others=>'0'), -- cnt
(others=>'0'), -- tcnt
rndminit, -- rndm
(others=>'0'), -- swi_1
btnzero, -- btn_1
(others=>'0'), -- led
(others=>'0'), -- dsp
(others=>'0') -- dp
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN4 : slbit := '0';
begin
assert BWIDTH>=4
report "assert(BWIDTH>=4): at least 4 BTNs available"
severity failure;
B4YES: if BWIDTH > 4 generate
BTN4 <= BTN(4);
end generate B4YES;
B4NO: if BWIDTH = 4 generate
BTN4 <= '0';
end generate B4NO;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, SWI, BTN, BTN4)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable btn03 : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
n.swi_1 := SWI;
n.btn_1 := BTN;
if SWI/=r.swi_1 or BTN/=r.btn_1 then
n.tcnt := slv(unsigned(r.tcnt) + 1);
end if;
btn03 := BTN(3 downto 0);
n.allon := BTN4;
if unsigned(BTN) /= 0 then -- is a button being pressed ?
if r.mode /= c_mode_btst then -- not in btst mode
case btn03 is
when "0001" => -- 0001 single button -> rndm mode
n.mode := c_mode_rndm;
n.rndm := rndminit;
when "0010" => -- 0010 single button -> cnt mode
n.mode := c_mode_cnt;
when "0100" => -- 0100 single button -> swi mode
n.mode := c_mode_swi;
when "1000" => -- 1001 single button -> btst mode
n.mode := c_mode_btst;
n.tcnt := (others=>'0');
when others => -- any 2+ button combo -> led test
n.allon := '1';
end case;
else -- button press in btst mode
case btn03 is
when "1001" => -- 1001 double btn -> rndm mode
n.mode := c_mode_rndm;
when "1010" => -- 1010 double btn -> rndm cnt
n.mode := c_mode_cnt;
when "1100" => -- 1100 double btn -> rndm swi
n.mode := c_mode_swi;
when others => null;
end case;
end if;
else -- no button being pressed
if CE_MSEC = '1' then -- on every usec
n.cnt := slv(unsigned(r.cnt) + 1); -- inc counter
if unsigned(r.cnt(8 downto 0)) = 0 then -- every 1/2 sec (approx.)
n.rndm := crc8_update(r.rndm, SWI); -- update rndm state
end if;
end if;
end if;
if r.allon = '1' then -- if led test selected
n.led := (others=>'1'); -- all led,dsp,dp on
n.dsp := (others=>'1');
n.dp := (others=>'1');
else -- no led test, normal output
case r.mode is
when c_mode_rndm =>
n.led := r.rndm;
n.dsp(7 downto 0) := r.rndm;
n.dsp(15 downto 8) := not r.rndm;
when c_mode_cnt =>
n.led := r.cnt(14 downto 7);
n.dsp := r.cnt;
when c_mode_swi =>
n.led := SWI;
n.dsp(7 downto 0) := SWI;
n.dsp(15 downto 8) := not SWI;
when c_mode_btst =>
n.led := SWI;
n.dsp := r.tcnt;
when others => null;
end case;
n.dp := BTN(3 downto 0);
end if;
N_REGS <= n;
LED <= r.led;
DSP_DAT <= r.dsp;
DSP_DP <= r.dp;
end process proc_next;
end syn;
| gpl-3.0 | 8c1f907e9f4fa6f4e0b15766b7aa609d | 0.450591 | 3.905443 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4/tb/sys_conf_sim.vhd | 1 | 1,727 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys4_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
| gpl-3.0 | 1e4c18d2afc2332c3c32854401ee255d | 0.617834 | 3.582988 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_core_rbus.vhd | 1 | 16,894 | -- $Id: pdp11_core_rbus.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_core_rbus - syn
-- Description: pdp11: core to rbus interface
--
-- Dependencies: -
-- Test bench: tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-12-21 591 14.7 131013 xc6slx16-2 52 118 0 58 s 4.9
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.5.4 use rbaddr_ constants
-- 2019-03-02 1116 1.5.3 rename state field rbinit to greset
-- 2016-05-22 767 1.5.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-07-10 700 1.5.1 add cpuact logic, redefine lam as cpuact 1->0
-- 2015-05-09 677 1.5 start/stop/suspend overhaul; reset overhaul
-- 2014-12-26 621 1.4 use full size 4k word ibus window
-- 2014-12-21 617 1.3.1 use separate RB_STAT bits for cmderr and cmdmerr
-- 2014-09-05 591 1.3 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.2 rb_mreq addr now 16 bit
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3
-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's
-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- add ibrb register and ibr window logic
-- 2010-06-13 305 1.2 add CP_ADDR in port; mostly rewritten for new
-- rri <-> cp mapping
-- 2010-06-03 299 1.1.2 correct rbus init logic (use we, din, RB_ADDR)
-- 2010-05-02 287 1.1.1 rename RP_STAT->RB_STAT; remove unneeded unsigned()
-- 2010-05-01 285 1.1 port to rri V2 interface, add RB_ADDR generic;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2008-05-03 143 1.0.8 rename _cpursta->_cpurust
-- 2008-04-27 140 1.0.7 use cpursta interface, remove cpufail
-- 2008-03-02 121 1.0.6 set RP_ERR when cmderr or cmdmerr status seen
-- 2008-02-24 119 1.0.5 support lah,rps,wps cp commands
-- 2008-01-20 113 1.0.4 use single LAM; change to RRI_LAM interface
-- 2007-10-12 88 1.0.3 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-16 74 1.0.2 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.1 use def's; add stat command; wait for step complete
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
--
-- 00000 conf r/w/- cpu configuration (e.g. cpu type)
-- (currently unused, all bits MBZ)
-- 00001 cntl -/f/- cpu control
-- 3:00 func function code
-- 0000: noop
-- 0001: start
-- 0010: stop
-- 0011: step
-- 0100: creset
-- 0101: breset
-- 0110: suspend
-- 0111: resume
-- 00010 stat r/-/- cpu status
-- 9 suspext r/-/- cp_stat: statext
-- 8 suspint r/-/- cp_stat: statint
-- 7:04 cpurust r/-/- cp_stat: cpurust
-- 3 cpususp r/-/- cp_stat: cpususp
-- 2 cpugo r/-/- cp_stat: cpugo
-- 1 cmdmerr r/-/- cp_stat: cmdmerr
-- 0 cmderr r/-/- cp_stat: cmderr
-- 00011 psw r/w/- processor status word access
-- 00100 al r/w/- address register, low
-- 00101 ah r/w/- address register, high
-- 7 ubm r/w/- ubmap access
-- 6 p22 r/w/- 22bit access
-- 5:00 addr r/w/- addr(21:16)
-- 00110 mem r/w/- memory access
-- 00111 memi r/w/- memory access, inc address
-- 01rrr gr[] r/w/- general regs
-- 10000 membe r/w/- memory write byte enables
-- 3 stick r/w/- sticky flag
-- 1:00 be r/w/- byte enables
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv16 := rbaddr_cpu0_core;
RB_ADDR_IBUS : slv16 := rbaddr_cpu0_ibus);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv4; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
GRESET : out slbit; -- general reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end pdp11_core_rbus;
architecture syn of pdp11_core_rbus is
type state_type is (
s_idle, -- s_idle: wait for rbus access
s_cpwait, -- s_cpwait: wait for cp port ack
s_cpstep -- s_cpstep: wait for cpustep done
);
type regs_type is record
state : state_type; -- state
rbselc : slbit; -- rbus select for core
rbseli : slbit; -- rbus select for ibus
greset : slbit; -- greset from rbus init (1 cycle pulse)
cpreq : slbit; -- cp request flag
cpfunc : slv5; -- cp function
cpuact_1 : slbit; -- prev cycle cpuact
addr : slv22_1; -- address register
ena_22bit : slbit; -- 22bit enable
ena_ubmap : slbit; -- ubmap enable
membe : slv2; -- memory write byte enables
membestick : slbit; -- memory write byte enables sticky
doinc : slbit; -- at cmdack: do addr reg inc
waitstep : slbit; -- at cmdack: wait for cpu step complete
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0','0', -- rbselc,rbseli
'0', -- greset
'0', -- cpreq
(others=>'0'), -- cpfunc
'0', -- cpuact_1
(others=>'0'), -- addr
'0','0', -- ena_22bit, ena_ubmap
"11",'0', -- membe,membestick
'0','0' -- doinc, waitstep
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, CP_STAT, CP_DOUT)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irb_lam : slbit := '0';
variable irbena : slbit := '0';
variable icpuact : slbit := '0';
variable icpreq : slbit := '0';
variable icpaddr : cp_addr_type := cp_addr_init;
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irb_lam := '0';
irbena := RB_MREQ.re or RB_MREQ.we;
icpreq := '0';
-- generate single cycle pulse in case init against rbus base address seen
-- is used to generate some state machine resets via GRESET
n.greset := '0';
if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR_CORE then
n.greset := RB_MREQ.din(c_init_rbf_greset);
end if;
-- rbus address decoder
n.rbseli := '0';
n.rbselc := '0';
if RB_MREQ.aval='1' then
if RB_MREQ.addr(15 downto 5)=RB_ADDR_CORE(15 downto 5) then
n.rbselc := '1';
end if;
if RB_MREQ.addr(15 downto 12)=RB_ADDR_IBUS(15 downto 12) then
n.rbseli := '1';
end if;
end if;
if (r.rbselc='1' or r.rbseli='1') and irbena='1' then
irb_ack := '1'; -- ack all (maybe rejected later)
end if;
case r.state is
when s_idle => -- s_idle: wait for rbus access ------
n.doinc := '0';
n.waitstep := '0';
if r.rbseli = '1' then
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
elsif r.rbselc = '1' then
case RB_MREQ.addr(4 downto 0) is
when c_rbaddr_conf => -- conf -------------------------
null; -- currently no action
when c_rbaddr_cntl => -- cntl -------------------------
if irbena = '1' then
n.cpfunc := RB_MREQ.din(n.cpfunc'range);
end if;
if RB_MREQ.we = '1' then
icpreq := '1';
if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
n.waitstep := '1';
end if;
end if;
when c_rbaddr_stat => -- stat ------------------
irb_dout(c_stat_rbf_suspext) := CP_STAT.suspext;
irb_dout(c_stat_rbf_suspint) := CP_STAT.suspint;
irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
irb_dout(c_stat_rbf_cpususp) := CP_STAT.cpususp;
irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr;
irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr;
when c_rbaddr_psw => -- psw -------------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rpsw;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_al => -- al --------------------
irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
if RB_MREQ.we = '1' then
n.addr := (others=>'0'); -- write to al clears ah !!
n.ena_22bit := '0';
n.ena_ubmap := '0';
n.addr(c_al_rbf_addr) := RB_MREQ.din(c_al_rbf_addr);
end if;
when c_rbaddr_ah => -- ah --------------------
irb_dout(c_ah_rbf_ena_ubmap) := r.ena_ubmap;
irb_dout(c_ah_rbf_ena_22bit) := r.ena_22bit;
irb_dout(c_ah_rbf_addr) := r.addr(21 downto 16);
if RB_MREQ.we = '1' then
n.addr(21 downto 16) := RB_MREQ.din(c_ah_rbf_addr);
n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
end if;
when c_rbaddr_mem => -- mem -------------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_memi => -- memi ------------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
n.doinc := '1';
icpreq := '1';
end if;
when c_rbaddr_r0 | c_rbaddr_r1 |
c_rbaddr_r2 | c_rbaddr_r3 |
c_rbaddr_r4 | c_rbaddr_r5 |
c_rbaddr_sp | c_rbaddr_pc => -- r* -----------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rreg;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_membe => -- membe -----------------
irb_dout(c_membe_rbf_be) := r.membe;
irb_dout(c_membe_rbf_stick) := r.membestick;
if RB_MREQ.we = '1' then
n.membe := RB_MREQ.din(c_membe_rbf_be);
n.membestick := RB_MREQ.din(c_membe_rbf_stick);
end if;
when others =>
irb_ack := '0';
end case;
end if;
if icpreq = '1' then
irb_busy := '1';
n.cpreq := '1';
n.state := s_cpwait;
end if;
when s_cpwait => -- s_cpwait: wait for cp port ack ----
n.cpreq := '0'; -- cpreq only for 1 cycle
if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort
if r.cpfunc = c_cpfunc_wmem and -- if wmem command
r.membestick = '0' then -- and be's not sticky
n.membe := "11"; -- re-enable both bytes
end if;
n.state := s_idle; -- quit
else
irb_dout := CP_DOUT;
irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
if CP_STAT.cmdack = '1' then -- normal cycle end
if r.cpfunc = c_cpfunc_wmem and -- if wmem command
r.membestick = '0' then -- and be's not sticky
n.membe := "11"; -- re-enable both bytes
end if;
if r.doinc = '1' then
n.addr := slv(unsigned(r.addr) + 1);
end if;
if r.waitstep = '1' then
irb_busy := '1';
n.state := s_cpstep;
else
n.state := s_idle;
end if;
else
irb_busy := '1';
end if;
end if;
when s_cpstep => -- s_cpstep: wait for cpustep done ---
n.state := s_cpstep; -- needed to prevent vivado iSTATE
if r.rbselc='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
if CP_STAT.cpustep = '0' then -- cpustep done
n.state := s_idle;
else
irb_busy := '1';
end if;
end if;
when others => null;
end case;
icpaddr := cp_addr_init;
icpaddr.be := r.membe;
if r.rbseli = '0' then -- access via cp
icpaddr.addr := r.addr;
icpaddr.racc := '0';
icpaddr.ena_22bit := r.ena_22bit;
icpaddr.ena_ubmap := r.ena_ubmap;
else -- access via ibus window
icpaddr.addr(15 downto 13) := "111";
icpaddr.addr(12 downto 1) := RB_MREQ.addr(11 downto 0);
icpaddr.racc := '1';
icpaddr.ena_22bit := '0';
icpaddr.ena_ubmap := '0';
end if;
icpuact := CP_STAT.cpugo and not CP_STAT.suspint;
n.cpuact_1 := icpuact; -- delay cpuact
if (r.cpuact_1='1' and icpuact='0') then -- cpuact 1 -> 0
irb_lam := '1';
end if;
N_REGS <= n;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
RB_STAT(3) <= CP_STAT.cmderr;
RB_STAT(2) <= CP_STAT.cmdmerr;
RB_STAT(1) <= CP_STAT.cpususp;
RB_STAT(0) <= CP_STAT.cpugo;
RB_LAM <= irb_lam;
GRESET <= R_REGS.greset;
CP_CNTL.req <= r.cpreq;
CP_CNTL.func <= r.cpfunc;
CP_CNTL.rnum <= RB_MREQ.addr(2 downto 0);
CP_ADDR <= icpaddr;
CP_DIN <= RB_MREQ.din;
end process proc_next;
end syn;
| gpl-3.0 | d1370fa95e63f08ea7446c2a33b799d3 | 0.450693 | 3.638596 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys2/tb/tb_nexys2_core.vhd | 1 | 4,049 | -- $Id: tb_nexys2_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_core - sim
-- Description: Test bench for nexys2 - core device handling
--
-- Dependencies: simlib/simbididly
-- bplib/micron/mt45w8mw16b
--
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-20 791 1.2 use simbididly
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 1.1 update O_FLA_CE_N usage
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
entity tb_nexys2_core is
port (
I_SWI : out slv8; -- n2 switches
I_BTN : out slv4; -- n2 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys2_core;
architecture sim of tb_nexys2_core is
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
constant pcb_delay : Delay_length := 1 ns;
begin
MM_MEM_CE_N <= O_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= O_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= O_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= O_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= O_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= O_MEM_CLK after pcb_delay;
MM_MEM_CRE <= O_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= O_MEM_ADDR after pcb_delay;
I_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => IO_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
| gpl-3.0 | 01a1dab24978bd456df676064ac2c686 | 0.542603 | 2.87571 | false | false | false | false |
wfjm/w11 | rtl/vlib/cdclib/cdclib.vhd | 1 | 3,372 | -- $Id: cdclib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: cdclib
-- Description: clock domain crossing components
--
-- Dependencies: -
-- Tool versions: viv 2016.1-2017.2; ghdl 0.33-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-02 1101 1.0.2 cdc_vector_s0,cdc_pulse interface changed
-- 2016-06-11 774 1.0.1 add cdc_signal_s1_as; add INIT generic
-- 2016-04-02 757 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package cdclib is
component cdc_signal_s1 is -- cdc for signal (2 stage)
generic (
INIT : slbit := '0'); -- initial state
port (
CLKO : in slbit; -- O|output clock
DI : in slbit; -- I|input data
DO : out slbit -- O|output data
);
end component;
component cdc_signal_s1_as is -- cdc for signal (2 stage), asyn input
generic (
INIT : slbit := '0'); -- initial state
port (
CLKO : in slbit; -- O|output clock
DI : in slbit; -- I|input data
DO : out slbit -- O|output data
);
end component;
component cdc_vector_s0 is -- cdc for vector (1 stage)
generic (
DWIDTH : positive := 16); -- data port width
port (
CLKO : in slbit; -- O|output clock
ENA : in slbit := '1'; -- O|capture enable
DI : in slv(DWIDTH-1 downto 0); -- I|input data
DO : out slv(DWIDTH-1 downto 0) -- O|output data
);
end component;
component cdc_vector_s1 is -- cdc for vector (2 stage)
generic (
DWIDTH : positive := 16); -- data port width
port (
CLKO : in slbit; -- O|output clock
DI : in slv(DWIDTH-1 downto 0); -- I|input data
DO : out slv(DWIDTH-1 downto 0) -- O|output data
);
end component;
component cdc_pulse is -- clock domain crossing for a pulse
generic (
POUT_SINGLE : boolean := false; -- if true: single cycle pout
BUSY_WACK : boolean := false; -- if true: busy waits for ack
INIT : slbit := '0'); -- initial state
port (
CLKM : in slbit; -- M|clock master
RESET : in slbit := '0'; -- M|reset
CLKS : in slbit; -- S|clock slave
PIN : in slbit; -- M|pulse in
BUSY : out slbit; -- M|busy
POUT : out slbit -- S|pulse out
);
end component;
component cdc_value is -- cdc for value (slow change)
generic (
DWIDTH : positive := 16); -- data port width
port (
CLKI : in slbit; -- I|input clock
CLKO : in slbit; -- O|output clock
DI : in slv(DWIDTH-1 downto 0); -- I|input data
DO : out slv(DWIDTH-1 downto 0); -- O|output data
UPDT : out slbit -- O|output data updated
);
end component;
end package cdclib;
| gpl-3.0 | d9de12a3dd59574c79f86f01e12dc227 | 0.497924 | 3.880322 | false | false | false | false |
wfjm/w11 | rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd | 1 | 18,814 | -- $Id: fx2_2fifoctl_ic.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2012-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_ic - syn
-- Description: Cypress EZ-USB FX2 controller (2 fifo; int clk)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_2c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-30 888 14.7 131013 xc6slx16-2 145 147 32 75 s 5.5/5.1
-- 2013-01-04 469 13.3 O76x xc3s1200e-4 112 172 64 169 s 7.4/7.4
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 101? 173 64 159 s 8.3/7.4
-- 2012-01-08 451 13.3 O76x xc3s1200e-4 110 166 64 163 s 7.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-04-30 888 1.3 BUGFIX: resolve rx fifo threshold deadlock
-- add fsm_* monitor lines
-- 2013-01-04 469 1.2 BUGFIX: redo rx logic, now properly pipelined
-- 2012-01-15 453 1.1 use aempty/afull logic; collapse tx and pe flows
-- 2012-01-09 451 1.0 Initial version
-- 2012-01-01 448 0.5 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_2fifoctl_ic is -- EZ-USB FX2 controller(2 fifo; int clk)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1); -- threshold for tx afull flag
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_ic;
architecture syn of fx2_2fifoctl_ic is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_idle, -- s_idle: idle state
s_rxprep0, -- s_rxprep0: switch to rx-fifo
s_rxprep1, -- s_rxprep1: fifo addr setup
s_rxprep2, -- s_rxprep2: wait for flags
s_rxdisp, -- s_rxdisp: read, dispatch
s_rxpipe, -- s_rxpipe: read, pipe wait
s_txprep0, -- s_txprep0: switch to tx-fifo
s_txprep1, -- s_txprep1: fifo addr setup
s_txprep2, -- s_txprep2: wait for flags
s_txdisp -- s_txdisp: write, dispatch
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
rxpipe1 : slbit; -- read pipe 1: iob capture stage
rxpipe2 : slbit; -- read pipe 2: fifo write stage
ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (tx) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_idle, -- state
petocnt_init, -- petocnt
'0', -- pepend
'0','0', -- rxpipe1, rxpipe2
ccnt_init, -- ccnt
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
constant rxfifo_thres : natural := 3; -- required free space in rx fifo to
-- start rx pipeline
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init;
signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and
TXAFULL_THRES<=2**TXFAWIDTH-1
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => I_FX2_IFCLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => I_FX2_IFCLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => I_FX2_IFCLK,
CLKR => CLK,
RESETW => '0',
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXSIZE_FX2,
SIZER => RXSIZE_USR
);
TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLK,
CLKR => I_FX2_IFCLK,
RESETW => RESET,
RESETR => '0',
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => TXSIZE_USR,
SIZER => TXSIZE_FX2
);
proc_regs: process (I_FX2_IFCLK)
begin
if rising_edge(I_FX2_IFCLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, FX2_FLAG_N, TXFIFO_VAL, RXSIZE_FX2, TXBUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable slrxok : slbit := '0';
variable sltxok : slbit := '0';
variable pipeok : slbit := '0';
variable rxfifook : slbit := '0';
variable cc_clr : slbit := '0';
variable cc_cnt : slbit := '0';
variable cc_done : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low!
rxfifook := '0';
if unsigned(RXSIZE_FX2)>rxfifo_thres then -- enough space in rx fifo ?
rxfifook := '1';
end if;
cc_clr := '0';
cc_cnt := '0';
if unsigned(r.ccnt) = 0 then
cc_done := '1';
else
cc_done := '0';
end if;
n.rxpipe1 := '0';
case r.state is
when s_idle => -- s_idle:
if slrxok='1' and rxfifook='1' then -- rx data and space in fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
end if;
when s_rxprep0 => -- s_rxprep0: switch to rx-fifo
ififo_ce := '1';
ififo := c_rxfifo;
n.state := s_rxprep1;
when s_rxprep1 => -- s_rxprep1: fifo addr setup
cc_clr := '1';
n.state := s_rxprep2;
when s_rxprep2 => -- s_rxprep2: wait for flags
isloe := '1';
n.state := s_rxdisp;
when s_rxdisp => -- s_rxdisp: read, dispatch
isloe := '1';
-- if chunk done and tx or pe pending and possible
if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_txprep0; -- otherwise switch to tx flow
end if;
-- if more rx to do and possible
elsif slrxok='1' and rxfifook='1' then
islrd := '1';
cc_cnt := '1';
n.rxpipe1 := '1';
if pipeok='1' then
n.state := s_rxdisp; -- 1 cycle read
--n.state := s_rxprep2; -- 2 cycle read
else
n.state := s_rxpipe;
end if;
-- otherwise back to idle
else
if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
n.state := s_rxdisp; -- wait
else
n.state := s_idle; -- to idle
end if;
end if;
when s_rxpipe => -- s_rxpipe: read, pipe wait
isloe := '1';
n.state := s_rxprep2;
when s_txprep0 => -- s_txprep0: switch to tx-fifo
ififo_ce := '1';
ififo := c_txfifo;
n.state := s_txprep1;
when s_txprep1 => -- s_txprep1: fifo addr setup
cc_clr := '1';
n.state := s_txprep2;
when s_txprep2 => -- s_txprep2: wait for flags
n.state := s_txdisp;
when s_txdisp => -- s_txdisp: write, dispatch
-- if chunk done and rx pending and possible
if cc_done='1' and slrxok='1' and rxfifook='1' then
n.state := s_rxprep0;
-- if pktend to do and possible
elsif sltxok = '1' and r.pepend = '1' then
ipktend := '1';
n.pepend := '0';
n.state := s_idle;
-- if more tx to do and possible
elsif sltxok = '1' and TXFIFO_VAL = '1' then
cc_cnt := '1'; -- inc chunk count
n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe)
itxfifo_hold := '0';
idata_ceo := '1';
idata_oe := '1';
islwr := '1';
if pipeok = '1' then -- if not almost full
n.state := s_txdisp; -- stream
else
n.state := s_txprep1; -- wait for full flag
end if;
-- otherwise back to idle
else
n.state := s_idle;
end if;
when others => null;
end case;
-- rx pipe handling
idata_cei := r.rxpipe1;
n.rxpipe2 := r.rxpipe1;
irxfifo_ena := r.rxpipe2;
-- chunk counter handling
if cc_clr = '1' then
n.ccnt := (others=>'1');
elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then
n.ccnt := slv(unsigned(r.ccnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every ifclk cycle
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_rxdisp or r.state = s_rxpipe then
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
elsif r.state = s_txdisp then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
end if;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
end process proc_next;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_MONI_C <= fx2ctl_moni_init;
R_MONI_S <= fx2ctl_moni_init;
else
R_MONI_C <= fx2ctl_moni_init;
R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel;
R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel;
R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef);
R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf;
R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff);
R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf;
R_MONI_C.slrd <= not FX2_SLRD_N;
R_MONI_C.slwr <= not FX2_SLWR_N;
R_MONI_C.pktend <= not FX2_PKTEND_N;
case R_REGS.state is
when s_idle => R_MONI_C.fsm_idle <= '1';
when s_rxprep0 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxprep1 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxprep2 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxdisp => R_MONI_C.fsm_disp <= '1'; R_MONI_C.fsm_rx <= '1';
when s_rxpipe => R_MONI_C.fsm_pipe <= '1'; R_MONI_C.fsm_rx <= '1';
when s_txprep0 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txprep1 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txprep2 => R_MONI_C.fsm_prep <= '1'; R_MONI_C.fsm_tx <= '1';
when s_txdisp => R_MONI_C.fsm_disp <= '1'; R_MONI_C.fsm_tx <= '1';
when others => null;
end case;
R_MONI_S <= R_MONI_C;
end if;
end if;
end process proc_moni;
proc_almost: process (RXSIZE_USR, TXSIZE_USR)
begin
-- rxsize_usr is the number of bytes to read
-- txsize_usr is the number of bytes to write
if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE_USR) <= TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
MONI <= R_MONI_S;
end syn;
| gpl-3.0 | 24cb7b657a51895100eb779c9f56e92b | 0.491124 | 3.300702 | false | false | false | false |
wfjm/w11 | rtl/bplib/mig/tb/sys_conf_ba3_bram.vhd | 1 | 1,343 | -- $Id: sys_conf_ba3_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf_ba4_msim
-- Description: Definitions for tb_sramif2migui_core (bawidth=3;btyp=bram)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-16 1069 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sys_conf is
-- define constants --------------------------------------------------------
constant c_btyp_msim : string := "MSIM";
constant c_btyp_bram : string := "BRAM";
-- configure ---------------------------------------------------------------
constant sys_conf_mawidth : positive := 28;
constant sys_conf_bawidth : positive := 3; -- 64 bit data path
constant sys_conf_sawidth : positive := 19; -- msim memory size
constant sys_conf_rawidth : positive := 19; -- bram memory size
constant sys_conf_rdelay : positive := 1; -- bram read delay
constant sys_conf_btyp : string := c_btyp_bram;
end package sys_conf;
| gpl-3.0 | ade79438f15e2f1f8272bbc69f4f4cae | 0.520477 | 3.870317 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd | 1 | 2,033 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-27 512 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 | d8562e4a7528f0a5f8d00d701f10d407 | 0.62666 | 3.529514 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/nexys4/tb/tb_tst_serloop1_n4.vhd | 1 | 3,508 | -- $Id: tb_tst_serloop1_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n4 - sim
-- Description: Test bench for sys_tst_serloop1_n4
--
-- Dependencies: simlib/simclk
-- xlib/sfs_gsim_core
-- sys_tst_serloop1_n4 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n4
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.2.1 use sfs_gsim_core
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2016-04-09 760 1.1 clock now from cmt and configurable
-- 2015-02-21 438 1.0 Initial version (cloned from tb_tst_serloop1_n3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
use work.sys_conf.all;
entity tb_tst_serloop1_n4 is
end tb_tst_serloop1_n4;
architecture sim of tb_tst_serloop1_n4 is
signal CLK100 : slbit := '0';
signal CLK : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
GEN_CLKSYS : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide)
port map (
CLKIN => CLK100,
CLKFX => CLK,
LOCKED => open
);
UUT : entity work.sys_tst_serloop1_n4
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => '1',
O_LED => open,
O_RGBLED0 => open,
O_RGBLED1 => open,
O_ANO_N => open,
O_SEG_N => open
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK,
CLKH => CLK,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => RTS_N,
P0_CTS_N => CTS_N,
P1_RXD => open, -- port 1 unused for n4 !
P1_TXD => '0',
P1_RTS_N => '0',
P1_CTS_N => open,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
RTS_N <= O_RTS_N after delay_time;
I_CTS_N <= CTS_N after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-3.0 | 76ee1eafcfab07dc2a006b41058565f3 | 0.509977 | 3.123776 | false | false | false | false |
wfjm/w11 | rtl/bplib/s3board/tb/tb_s3_sram_memctl.vhd | 1 | 10,243 | -- $Id: tb_s3_sram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_s3_sram_memctl - sim
-- Description: Test bench for s3_sram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/issi/is61lv25616al
-- s3_sram_memctl [UUT]
--
-- To test: s3_sram_memctl
--
-- Verified (with tb_s3_sram_memctl_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-12-16 101 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-12-16 101 - 0.26 - - c:ok
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-11-21 432 1.0.6 now numeric_std clean
-- 2010-05-23 293 1.0.5 output # busy cycles; change CHK pipeline logic
-- 2010-05-16 291 1.0.4 rename tb_memctl_s3sram->tb_s3_sram_memctl
-- 2008-03-24 129 1.0.3 CLK_CYCLE now 31 bits
-- 2008-02-17 117 1.0.2 use req,we rather req_r,req_w interface
-- 2008-01-20 113 1.0.1 rename memdrv -> memctl_s3sram
-- 2007-12-15 101 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.s3boardlib.all;
use work.simlib.all;
entity tb_s3_sram_memctl is
end tb_s3_sram_memctl;
architecture sim of tb_s3_sram_memctl is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv18 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'0');
signal O_MEM_BE_N : slv4 := (others=>'0');
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADDR : slv18 := (others=>'0');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv18 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv18 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv18 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(1),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(3),
LB_N => O_MEM_BE_N(2),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(31 downto 16)
);
UUT : s3_sram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_s3_sram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv18 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
wait for clock_period;
REQ <= '0';
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 6, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
wait for clock_period;
REQ <= '0';
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" be="));
write(oline, not O_MEM_BE_N, right, 4);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 5, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 8, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
| gpl-3.0 | da8f9563a7488ac21bd71896561243c7 | 0.494386 | 3.404121 | false | false | false | false |
hubertokf/VHDL-MIPS-Pipeline | memInst_inst.vhd | 1 | 165 | --memInst_inst : memInst PORT MAP (
-- address => address_sig,
-- clock => clock_sig,
-- data => data_sig,
-- wren => wren_sig,
-- q => q_sig
-- );
| mit | 3ce9cc78c67699eabdfda79c2d2d6683 | 0.49697 | 2.2 | false | false | false | false |
wfjm/w11 | rtl/vlib/rlink/rlink_mon_sb.vhd | 1 | 2,413 | -- $Id: rlink_mon_sb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon_sb - sim
-- Description: simbus wrapper for rlink monitor
--
-- Dependencies: simbus
-- simlib/simclkcnt
-- rlink_mon
-- Test bench: -
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb
-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def
-- 2007-08-25 75 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rlinklib.all;
entity rlink_mon_sb is -- simbus wrap for rlink monitor
generic (
DWIDTH : positive := 9; -- data port width (8 or 9)
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon_sb;
architecture sim of rlink_mon_sb is
signal ENA : slbit := '0';
signal CLK_CYCLE : integer := 0;
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : rlink_mon
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => ENA,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
end sim;
| gpl-3.0 | ba08a56824eaf03077d19c78100ea339 | 0.527145 | 3.432432 | false | false | false | false |
wfjm/w11 | rtl/w11a/tb/tb_pdp11core.vhd | 1 | 26,386 | -- $Id: tb_pdp11core.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_pdp11core - sim
-- Description: Test bench for pdp11_core
--
-- Dependencies: simlib/simclk
-- tbd_pdp11core [UUT]
-- pdp11_intmap
--
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: ghdl 0.18-2.0.0; ISim 14.7
--
-- Verified (with tb_pdp11core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2014-12-23 620 - 0.31 14.7 131013 - u:ok
-- 2010-12-30 351 - 0.29 - - u:ok
-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
-- 2010-06-20 308 - 0.29 - - u:ok
-- 2009-11-22 252 - 0.26 - - u:ok
-- 2007-12-30 107 - 0.25 - - u:ok
-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!)
-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok
-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok
-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
-- 2007-10-07 88 - 0.26 - - c:ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.5.2 rename _gpr -> _gr
-- 2019-03-17 1123 1.5.1 print header
-- 2015-05-08 675 1.5 start/stop/suspend overhaul
-- 2014-12-26 621 1.4.1 adopt wmembe,ribr,wibr emulation to new 4k window
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-18 427 1.3.2 now numeric_std clean
-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
-- 'sta' behaviour with new 'stapc' command; rename
-- lal,lah -> wal,wah and implement locally; new
-- output format with cpfunc name
-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon
-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_
-- 2009-11-28 253 1.1.12 add hack for ISim 11.3
-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits)
-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust
-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail
-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now
-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for
-- command completion, wtgo waits for CPU to halt.
-- added .cerr,.merr directive, check cmd(m)err state
-- added .sdef as ignored directive
-- 2008-02-24 119 1.1.4 added lah,rps,wps command
-- 2008-01-26 114 1.1.3 add handling of d=val,msk
-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-02 79 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11_sim.all;
use work.pdp11.all;
entity tb_pdp11core is
end tb_pdp11core;
architecture sim of tb_pdp11core is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
signal CP_CNTL_req : slbit := '0';
signal CP_CNTL_func : slv5 := (others=>'0');
signal CP_CNTL_rnum : slv3 := (others=>'0');
signal CP_ADDR_addr : slv22_1 := (others=>'0');
signal CP_ADDR_racc : slbit := '0';
signal CP_ADDR_be : slv2 := "11";
signal CP_ADDR_ena_22bit : slbit := '0';
signal CP_ADDR_ena_ubmap : slbit := '0';
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT_cmdbusy : slbit := '0';
signal CP_STAT_cmdack : slbit := '0';
signal CP_STAT_cmderr : slbit := '0';
signal CP_STAT_cmdmerr : slbit := '0';
signal CP_STAT_cpugo : slbit := '0';
signal CP_STAT_cpustep : slbit := '0';
signal CP_STAT_cpuwait : slbit := '0';
signal CP_STAT_cpususp : slbit := '0';
signal CP_STAT_cpurust : slv4 := (others=>'0');
signal CP_STAT_suspint : slbit := '0';
signal CP_STAT_suspext : slbit := '0';
signal CP_DOUT : slv16 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal R_CHKDAT : slv16 := (others=>'0');
signal R_CHKMSK : slv16 := (others=>'0');
signal R_CHKREQ : slbit := '0';
signal R_WAITCMD : slbit := '0';
signal R_WAITSTEP : slbit := '0';
signal R_WAITGO : slbit := '0';
signal R_WAITOK : slbit := '0';
signal R_CP_STAT : cp_stat_type := cp_stat_init;
signal R_CP_DOUT : slv16 := (others=>'0');
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT: entity work.tbd_pdp11core
port map (
CLK => CLK,
RESET => RESET,
CP_CNTL_req => CP_CNTL_req,
CP_CNTL_func => CP_CNTL_func,
CP_CNTL_rnum => CP_CNTL_rnum,
CP_ADDR_addr => CP_ADDR_addr,
CP_ADDR_racc => CP_ADDR_racc,
CP_ADDR_be => CP_ADDR_be,
CP_ADDR_ena_22bit => CP_ADDR_ena_22bit,
CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap,
CP_DIN => CP_DIN,
CP_STAT_cmdbusy => CP_STAT_cmdbusy,
CP_STAT_cmdack => CP_STAT_cmdack,
CP_STAT_cmderr => CP_STAT_cmderr,
CP_STAT_cmdmerr => CP_STAT_cmdmerr,
CP_STAT_cpugo => CP_STAT_cpugo,
CP_STAT_cpustep => CP_STAT_cpustep,
CP_STAT_cpuwait => CP_STAT_cpuwait,
CP_STAT_cpususp => CP_STAT_cpususp,
CP_STAT_cpurust => CP_STAT_cpurust,
CP_STAT_suspint => CP_STAT_suspint,
CP_STAT_suspext => CP_STAT_suspext,
CP_DOUT => CP_DOUT
);
proc_stim: process
file ifile : text open read_mode is "tb_pdp11core_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable idummy : integer := 0;
variable dcycle : integer := 0;
variable irqline : integer := 0;
variable ireq : boolean := false;
variable ifunc : slv5 := (others=>'0');
variable irnum : slv3 := (others=>'0');
variable idin : slv16 := (others=>'0');
variable imsk : slv16 := (others=>'1');
variable idin3 : slv3 := (others=>'0');
variable ichk : boolean := false;
variable idosta: slbit := '0';
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable rind : integer := 0;
variable nblk : integer := 0;
variable xmicmd : string(1 to 3) := (others=>' ');
variable iwtstp : boolean := false;
variable iwtgo : boolean := false;
variable icerr : integer := 0;
variable imerr : integer := 0;
variable to_cmd : integer := 50;
variable to_stp : integer := 100;
variable to_go : integer := 5000;
variable ien : slbit := '0';
variable ibit : integer := 0;
variable imemi : boolean := false;
variable iaddr : slv16 := (others=>'0');
variable idoibr : boolean := false;
variable r_addr : slv22_1 := (others=>'0');
variable r_ena_22bit : slbit := '0';
variable r_ena_ubmap : slbit := '0';
variable r_membe : slv2 := "11";
variable r_membestick : slbit := '0';
begin
SB_CNTL <= (others=>'L');
wait for clock_offset - setup_time;
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
-- write header
write(oline, string'(" # cycles"));
writeline(output, oline);
write(oline, string'(" | function"));
writeline(output, oline);
write(oline, string'(" | | register"));
writeline(output, oline);
write(oline, string'(" | | | input data"));
writeline(output, oline);
write(oline, string'(" | | | | cmdbusy"));
writeline(output, oline);
write(oline, string'(" | | | | | cmdack"));
writeline(output, oline);
write(oline, string'(" | | | | | | cmderr"));
writeline(output, oline);
write(oline, string'(" | | | | | | | cmdmerr"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | output data"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | cpugo"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |cpustep"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | ||cpuwait"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |||cpususp"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | ||||suspint"));
writeline(output, oline);
write(oline, string'(" | | | | | | | | | |||||suspext"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| cpurust"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| | Check result"));
writeline(output, oline);
write(oline,
string'(" | | | | | | | | | |||||| | |"));
writeline(output, oline);
file_loop: while not endfile(ifile) loop
-- this logic is a quick hack to implement the 'stapc' command
if idosta = '0' then
readline (ifile, iline);
iwtstp := false;
iwtgo := false;
if nblk>0 and -- outstanding [rw]mi lines ?
iline'length>=3 and -- and 3 leading blanks
iline(iline'left to iline'left+2)=" " then
nblk := nblk - 1; -- than fill [rw]mi command in again
iline(iline'left to iline'left+2) := xmicmd;
end if;
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
else
idosta := '0';
dname := "sta ";
ok := true;
end if;
if ok then
case dname is
when "rsp " => dname := "rr6 "; -- rsp -> rr6
when "rpc " => dname := "rr7 "; -- rpc -> rr7
when "wsp " => dname := "wr6 "; -- wsp -> wr6
when "wpc " => dname := "wr7 "; -- wpc -> wr7
when others => null;
end case;
rind := character'pos(dname(3)) - character'pos('0');
if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7]
dname(2)='r' and
(rind>=0 and rind<=7) then
dname(3) := '|'; -- replace with [rw]r|
end if;
if dname(1) = '.' then
case dname is
when ".mode " => -- .mode
readword_ea(iline, dname);
assert dname="pdpcp "
report "assert .mode == pdpcp" severity failure;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".tocmd" => -- .tocmd
read_ea(iline, idelta);
to_cmd := idelta;
when ".tostp" => -- .tostp
read_ea(iline, idelta);
to_stp := idelta;
when ".togo " => -- .togo
read_ea(iline, idelta);
to_go := idelta;
when ".sdef " => -- .sdef (ignore it)
readempty(iline);
when ".cerr " => -- .cerr
read_ea(iline, icerr);
when ".merr " => -- .merr
read_ea(iline, imerr);
when ".anena" => -- .anena (ignore it)
readempty(iline);
when ".rlmon" => -- .rlmon (ignore it)
readempty(iline);
when ".rbmon" => -- .rbmon (ignore it)
readempty(iline);
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
when others => -- bad directive
write(oline, string'("-E: unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
testempty_ea(iline);
next file_loop;
else
ireq := true;
ifunc := c_cpfunc_noop;
irnum := "000";
ichk := false;
idin := (others=>'0');
imsk := (others=>'1');
imemi := false;
idoibr := false;
case dname is
when "brm " => -- brm
read_ea(iline, nblk);
xmicmd := "rmi";
next file_loop;
when "bwm " => -- bwm
read_ea(iline, nblk);
xmicmd := "wmi";
next file_loop;
when "rr| " => -- rr[0-7]
ifunc := c_cpfunc_rreg;
irnum := slv(to_unsigned(rind, 3));
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wr| " => -- wr[0-7]
ifunc := c_cpfunc_wreg;
irnum := slv(to_unsigned(rind, 3));
readoct_ea(iline, idin);
-- Note: there are no field definitions for wal, wah, wmembe because
-- there is no corresponding cp command. Therefore the
-- rbus field definitions are used here
when "wal " => -- wal
readoct_ea(iline, idin);
r_addr := (others=>'0'); -- write to al clears ah !!
r_ena_22bit := '0';
r_ena_ubmap := '0';
r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr);
testempty_ea(iline);
next file_loop;
when "wah " => -- wah
readoct_ea(iline, idin);
r_addr(21 downto 16) := idin(c_ah_rbf_addr);
r_ena_22bit := idin(c_ah_rbf_ena_22bit);
r_ena_ubmap := idin(c_ah_rbf_ena_ubmap);
testempty_ea(iline);
next file_loop;
when "wmembe" => -- wmembe
read_ea(iline, idin3);
r_membestick := idin3(c_membe_rbf_stick);
r_membe := idin3(c_membe_rbf_be);
testempty_ea(iline);
next file_loop;
when "rm " => -- rm
ifunc := c_cpfunc_rmem;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "rmi " => -- rmi
ifunc := c_cpfunc_rmem;
imemi := true;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wm " => -- wm
ifunc := c_cpfunc_wmem;
readoct_ea(iline, idin);
when "wmi " => -- wmi
ifunc := c_cpfunc_wmem;
imemi := true;
readoct_ea(iline, idin);
when "ribr " => -- ribr
ifunc := c_cpfunc_rmem;
idoibr := true;
readoct_ea(iline, iaddr);
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wibr " => -- wibr
ifunc := c_cpfunc_wmem;
idoibr := true;
readoct_ea(iline, iaddr);
readoct_ea(iline, idin);
when "rps " => -- rps
ifunc := c_cpfunc_rpsw;
readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
when "wps " => -- wps
ifunc := c_cpfunc_wpsw;
readoct_ea(iline, idin);
-- Note: in old version 'sta addr' was an atomic operation, loading
-- the pc and starting the cpu. Now this is action is two step
-- first a wpc followed by a 'sta'.
when "stapc " => -- stapc
ifunc := c_cpfunc_wreg;
irnum := c_gr_pc;
readoct_ea(iline, idin);
idosta := '1'; -- request 'sta' to be done next
when "sta " => -- sta
ifunc := c_cpfunc_start;
when "sto " => -- sto
ifunc := c_cpfunc_stop;
when "step " => -- step
ifunc := c_cpfunc_step;
iwtstp := true;
when "cres " => -- cres
ifunc := c_cpfunc_creset;
when "bres " => -- bres
ifunc := c_cpfunc_breset;
when "susp " => -- susp
ifunc := c_cpfunc_suspend;
when "resu " => -- resu
ifunc := c_cpfunc_resume;
when "wtgo " => -- wtgo
iwtgo := true;
ireq := false; -- no cp request !
when "wtlam " => -- wtlam (ignore it)
readempty(iline);
next file_loop;
when others => -- bad directive
write(oline, string'("-E: unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
end if;
testempty_ea(iline);
end if;
CP_ADDR_be <= r_membe;
if idoibr then
CP_ADDR_addr(15 downto 13) <= "111";
CP_ADDR_addr(12 downto 1) <= iaddr(12 downto 1);
CP_ADDR_racc <= '1';
CP_ADDR_ena_22bit <= '0';
CP_ADDR_ena_ubmap <= '0';
else
CP_ADDR_addr <= r_addr;
CP_ADDR_racc <= '0';
CP_ADDR_be <= "11";
CP_ADDR_ena_22bit <= r_ena_22bit;
CP_ADDR_ena_ubmap <= r_ena_ubmap;
end if;
if ireq then
CP_CNTL_req <= '1';
CP_CNTL_func <= ifunc;
CP_CNTL_rnum <= irnum;
end if;
if ichk then
CP_DIN <= (others=>'0');
R_CHKDAT <= idin;
R_CHKMSK <= imsk;
R_CHKREQ <= '1';
else
CP_DIN <= idin;
R_CHKREQ <= '0';
end if;
R_WAITCMD <= '0';
R_WAITSTEP <= '0';
R_WAITGO <= '0';
if iwtgo then
idelta := to_go;
R_WAITGO <= '1';
elsif iwtstp then
idelta := to_stp;
R_WAITSTEP <= '1';
else
idelta := to_cmd;
R_WAITCMD <= '1';
end if;
wait for clock_period;
CP_CNTL_req <= '0';
dcycle := 1;
while idelta>0 and R_WAITOK='0' loop
wait for clock_period;
dcycle := dcycle + 1;
idelta := idelta - 1;
end loop;
if imemi then -- rmi or wmi seen ? then inc ar
r_addr := slv(unsigned(r_addr) + 1);
end if;
if ifunc = c_cpfunc_wmem and -- emulate be sticky logic of rbus iface
r_membestick = '0' then
r_membe := "11";
end if;
write(oline, dcycle, right, 4);
write(oline, string'(" "));
if ireq then
case ifunc is
when c_cpfunc_rreg => write(oline, string'("rreg"));
when c_cpfunc_wreg => write(oline, string'("wreg"));
when c_cpfunc_rpsw => write(oline, string'("rpsw"));
when c_cpfunc_wpsw => write(oline, string'("wpsw"));
when c_cpfunc_rmem =>
if idoibr then
write(oline, string'("ribr"));
else
write(oline, string'("rmem"));
end if;
when c_cpfunc_wmem =>
if idoibr then
write(oline, string'("wibr"));
else
write(oline, string'("wmem"));
end if;
when c_cpfunc_start => write(oline, string'("sta "));
when c_cpfunc_stop => write(oline, string'("sto "));
when c_cpfunc_step => write(oline, string'("step"));
when c_cpfunc_creset => write(oline, string'("cres"));
when c_cpfunc_breset => write(oline, string'("bres"));
when c_cpfunc_suspend => write(oline, string'("susp"));
when c_cpfunc_resume => write(oline, string'("resu"));
when others =>
write(oline, string'("?"));
writeoct(oline, ifunc, right, 2);
write(oline, string'("?"));
end case;
writeoct(oline, irnum, right, 2);
writeoct(oline, idin, right, 8);
else
write(oline, string'("---- - ------"));
end if;
write(oline, R_CP_STAT.cmdbusy, right, 3);
write(oline, R_CP_STAT.cmdack, right, 2);
write(oline, R_CP_STAT.cmderr, right, 2);
write(oline, R_CP_STAT.cmdmerr, right, 2);
writeoct(oline, R_CP_DOUT, right, 8);
write(oline, R_CP_STAT.cpugo, right, 3);
write(oline, R_CP_STAT.cpustep, right, 1);
write(oline, R_CP_STAT.cpuwait, right, 1);
write(oline, R_CP_STAT.cpususp, right, 1);
write(oline, R_CP_STAT.suspint, right, 1);
write(oline, R_CP_STAT.suspext, right, 1);
writeoct(oline, R_CP_STAT.cpurust, right, 3);
if R_WAITOK = '1' then
if R_CP_STAT.cmderr='1' or icerr=1 then
if R_CP_STAT.cmderr='1' and icerr=0 then
write(oline, string'(" FAIL CMDERR"));
elsif R_CP_STAT.cmderr='1' and icerr=1 then
write(oline, string'(" CHECK CMDERR SEEN"));
elsif R_CP_STAT.cmderr='0' and icerr=1 then
write(oline, string'(" FAIL CMDERR EXPECTED,MISSED"));
end if;
elsif R_CP_STAT.cmdmerr='1' or imerr=1 then
if R_CP_STAT.cmdmerr='1' and imerr=0 then
write(oline, string'(" FAIL CMDMERR"));
elsif R_CP_STAT.cmdmerr='1' and imerr=1 then
write(oline, string'(" CHECK CMDMERR SEEN"));
elsif R_CP_STAT.cmdmerr='0' and imerr=1 then
write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED"));
end if;
elsif R_CHKREQ='1' then
if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then
write(oline, string'(" CHECK OK"));
else
write(oline, string'(" CHECK FAILED, d="));
writeoct(oline, R_CHKDAT, right, 7);
if unsigned(R_CHKMSK)/=0 then
write(oline, string'(","));
writeoct(oline, R_CHKMSK, right, 7);
end if;
end if;
end if;
if iwtgo then
write(oline, string'(" WAIT GO OK "));
elsif iwtstp then
write(oline, string'(" WAIT STEP OK"));
end if;
else
write(oline, string'(" WAIT FAILED (will reset)"));
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
end if;
writeline(output, oline);
end loop;
wait for 4*clock_period;
CLK_STOP <= '1';
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
R_WAITOK <= '0';
if R_WAITCMD = '1' then
if CP_STAT_cmdack = '1' then
R_WAITOK <= '1';
end if;
elsif R_WAITGO = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then
R_WAITOK <= '1';
end if;
elsif R_WAITSTEP = '1' then
if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then
R_WAITOK <= '1';
end if;
end if;
R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy;
R_CP_STAT.cmdack <= CP_STAT_cmdack;
R_CP_STAT.cmderr <= CP_STAT_cmderr;
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr;
R_CP_STAT.cpugo <= CP_STAT_cpugo;
R_CP_STAT.cpustep <= CP_STAT_cpustep;
R_CP_STAT.cpuwait <= CP_STAT_cpuwait;
R_CP_STAT.cpususp <= CP_STAT_cpususp;
R_CP_STAT.cpurust <= CP_STAT_cpurust;
R_CP_STAT.suspint <= CP_STAT_suspint;
R_CP_STAT.suspext <= CP_STAT_suspext;
R_CP_DOUT <= CP_DOUT;
end loop;
end process proc_moni;
end sim;
| gpl-3.0 | 2c00b292bc3624bf9371b0d5fa4908bf | 0.481505 | 3.568087 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/rgbdrv_analog.vhd | 1 | 2,593 | -- $Id: rgbdrv_analog.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_analog - syn
-- Description: rgbled driver: analog channel
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4-2016.4; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-05 907 1.1 add ACTLOW generic to invert output polarity
-- 2016-02-20 734 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity rgbdrv_analog is -- rgbled driver: analog channel
generic (
DWIDTH : positive := 8; -- dimmer width
ACTLOW : slbit := '0'); -- invert output polarity
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
DIMR : in slv(DWIDTH-1 downto 0); -- dim red
DIMG : in slv(DWIDTH-1 downto 0); -- dim green
DIMB : in slv(DWIDTH-1 downto 0); -- dim blue
O_RGBLED : out slv3 -- pad-o: rgb led
);
end rgbdrv_analog;
architecture syn of rgbdrv_analog is
signal R_RGB : slv3 := (others=>'0'); -- state registers
signal N_RGB : slv3 := (others=>'0'); -- next value state regs
begin
IOB_RGB : iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => R_RGB, PAD => O_RGBLED);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_RGB <= (others=>'0');
else
R_RGB <= N_RGB;
end if;
end if;
end process proc_regs;
proc_next: process (R_RGB, RGBCNTL, DIMCNTL, DIMR, DIMG, DIMB)
variable irgb : slv3 := (others=>'0');
begin
irgb := (others=>'0');
if unsigned(DIMCNTL) < unsigned(DIMR) then
irgb(0) := RGBCNTL(0);
end if;
if unsigned(DIMCNTL) < unsigned(DIMG) then
irgb(1) := RGBCNTL(1);
end if;
if unsigned(DIMCNTL) < unsigned(DIMB) then
irgb(2) := RGBCNTL(2);
end if;
N_RGB(0) <= ACTLOW xor irgb(0);
N_RGB(1) <= ACTLOW xor irgb(1);
N_RGB(2) <= ACTLOW xor irgb(2);
end process proc_next;
end syn;
| gpl-3.0 | 798d0d590aab53ef0063cde7058cf200 | 0.537601 | 3.485215 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd | 1 | 4,759 | -- $Id: sys_tst_snhumanio_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_n3 - syn
-- Description: snhumanio tester design for nexys3
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-27 433 13.1 O40d xc3s1200e-4 151 195 - 65 t 6.1
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_n3 is -- top level
-- implements nexys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit -- ppcm: ...
);
end sys_tst_snhumanio_n3;
architecture syn of sys_tst_snhumanio_n3 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK100;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 100,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 5)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
| gpl-3.0 | 5d853048410b318f1b41d4387bfa7f37 | 0.461021 | 3.370397 | false | false | false | false |
wfjm/w11 | rtl/bplib/sysmon/sysmonx_rbus_base.vhd | 1 | 6,980 | -- $Id: sysmonx_rbus_base.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sysmonx_rbus_base - syn
-- Description: 7series XADC interface to rbus (basic supply monitor version)
--
-- Dependencies: sysmon_rbus_core
--
-- Test bench: -
--
-- Target Devices: 7series
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-13 742 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers: see sysmon_rbus_core and XADC user guide
--
-- XADC usage:
-- - only build-in sensors: temp, Vccint, Vccaux, Vccbram
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
-- ----------------------------------------------------------------------------
entity sysmonx_rbus_base is -- XADC interface to rbus (basic monitor)
generic (
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types)
INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types)
INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12 -- xadc: die temp
);
end sysmonx_rbus_base;
architecture syn of sysmonx_rbus_base is
constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio
constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16)));
signal SM_DEN : slbit := '0';
signal SM_DWE : slbit := '0';
signal SM_DADDR : slv7 := (others=>'0');
signal SM_DI : slv16 := (others=>'0');
signal SM_DO : slv16 := (others=>'0');
signal SM_DRDY : slbit := '0';
signal SM_EOS : slbit := '0';
signal SM_EOC : slbit := '0';
signal SM_RESET : slbit := '0';
signal SM_CHAN : slv5 := (others=>'0');
signal SM_ALM : slv8 := (others=>'0');
signal SM_OT : slbit := '0';
signal SM_JTAGLOCKED : slbit := '0';
signal SM_JTAGMODIFIED : slbit := '0';
signal SM_JTAGBUSY : slbit := '0';
begin
SM : XADC
generic map (
INIT_40 => xadc_init_40_default, -- conf #0
INIT_41 => xadc_init_41_default, -- conf #1
INIT_42 => init_42,
INIT_43 => x"0000", -- test #0 - don't use, stay 0
INIT_44 => x"0000", -- test #1 - "
INIT_45 => x"0000", -- test #2 - "
INIT_46 => x"0000", -- test #3 - "
INIT_47 => x"0000", -- test #4 - "
INIT_48 => xadc_init_48_default, -- seq #0: sel 0
INIT_49 => x"0000", -- seq #1: sel 1: no aux
INIT_4A => xadc_init_4a_default, -- seq #2: avr 0
INIT_4B => x"0000", -- seq #3: avr 1: "
INIT_4C => x"0000", -- seq #4: mode 0: unipolar
INIT_4D => x"0000", -- seq #5: mode 1: "
INIT_4E => x"0000", -- seq #6: time 0: fast
INIT_4F => x"0000", -- seq #7: time 1: "
INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0)
INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1)
INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2)
INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT
INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0)
INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1)
INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2)
INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT
INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3)
INIT_59 => x"0000", -- alm #09: ccpint up (4)
INIT_5A => x"0000", -- alm #10: ccpaux up (5)
INIT_5B => x"0000", -- alm #11: ccdram up (6)
INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3)
INIT_5D => x"0000", -- alm #13: ccpint low (4)
INIT_5E => x"0000", -- alm #14: ccpaux low (5)
INIT_5F => x"0000", -- alm #15: ccdram low (6)
-- IS_CONVSTCLK_INVERTED => '0',
-- IS_DCLK_INVERTED => '0',
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "sysmon_stim")
port map (
DCLK => CLK,
DEN => SM_DEN,
DWE => SM_DWE,
DADDR => SM_DADDR,
DI => SM_DI,
DO => SM_DO,
DRDY => SM_DRDY,
EOC => SM_EOC, -- connected for tb usage
EOS => SM_EOS,
BUSY => open,
RESET => SM_RESET,
CHANNEL => SM_CHAN, -- connected for tb usage
MUXADDR => open,
ALM => SM_ALM,
OT => SM_OT,
CONVST => '0',
CONVSTCLK => '0',
JTAGBUSY => SM_JTAGBUSY,
JTAGLOCKED => SM_JTAGLOCKED,
JTAGMODIFIED => SM_JTAGMODIFIED,
VAUXN => (others=>'0'),
VAUXP => (others=>'0'),
VN => '0',
VP => '0'
);
SMRB : sysmon_rbus_core
generic map (
DAWIDTH => 7,
ALWIDTH => 8,
TEWIDTH => 12,
IBASE => x"78",
RB_ADDR => RB_ADDR)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
SM_DEN => SM_DEN,
SM_DWE => SM_DWE,
SM_DADDR => SM_DADDR,
SM_DI => SM_DI,
SM_DO => SM_DO,
SM_DRDY => SM_DRDY,
SM_EOS => SM_EOS,
SM_RESET => SM_RESET,
SM_ALM => SM_ALM,
SM_OT => SM_OT,
SM_JTAGBUSY => SM_JTAGBUSY,
SM_JTAGLOCKED => SM_JTAGLOCKED,
SM_JTAGMODIFIED => SM_JTAGMODIFIED,
TEMP => TEMP
);
ALM <= SM_ALM;
OT <= SM_OT;
end syn;
| gpl-3.0 | 9334a62525b7a846c9e9e0bbc4dbf2e9 | 0.475931 | 3.187215 | false | false | false | false |
rongcuid/lots-of-subleq-cpus | Subleq Pipelined/src/cpu_top.vhd | 1 | 8,098 | ----------------------------------------------------------------------------------
-- Company: The Most Awesome Mad Scientist Ever
-- Engineer: Rongcui Dong
--
-- Create Date:
-- Design Name:
-- Module Name: cpu_top
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- This module assembles the CPU core, MMU, register file,
-- plus a very simple bootloader
entity cpu_top is
port(
clk : in std_logic;
resetb : in std_logic;
-- Interface with boot ROM
cpu_rom_addr : out unsigned(31 downto 0);
cpu_rom_data : in std_logic_vector(31 downto 0);
-- Interface with board
boot_done : out std_logic
);
end entity cpu_top;
architecture syn of cpu_top is
component CPUCore
port (
clk : in std_logic;
resetb : in std_logic;
-- Interface with register file
core_rf_en : out std_logic;
core_rf_rs_a : out std_logic_vector(4 downto 0);
core_rf_rs_d : in std_logic_vector(63 downto 0);
core_rf_rt_a : out std_logic_vector(4 downto 0);
core_rf_rt_d : in std_logic_vector(63 downto 0);
core_rf_wb_we : out std_logic;
core_rf_wb_a : out std_logic_vector(4 downto 0);
core_rf_wb_d : out std_logic_vector(63 downto 0);
-- Interface with MMU
---- Instruction Port
core_mmu_we_i : out std_logic;
core_mmu_en_i : out std_logic;
core_mmu_addr_i : out std_logic_vector(31 downto 3);
core_mmu_ben_i : out std_logic_vector(7 downto 0);
core_mmu_di_i : out std_logic_vector(63 downto 0);
core_mmu_do_i : in std_logic_vector(63 downto 0);
---- Data Port
core_mmu_we_d : out std_logic;
core_mmu_en_d : out std_logic;
core_mmu_addr_d : out std_logic_vector(31 downto 3);
core_mmu_ben_d : out std_logic_vector(7 downto 0);
core_mmu_di_d : out std_logic_vector(63 downto 0);
core_mmu_do_d : in std_logic_vector(63 downto 0)
);
end component CPUCore;
component MMU
generic ( DEPTH_BANK : integer := 1024;
DEPTH_LOG : integer := 10
);
port (
clk : in std_logic;
resetb : in std_logic;
-- Instruction Memory
we_i : in std_logic;
en_i : in std_logic;
addr_i : in std_logic_vector(31 downto 3);
ben_i : in std_logic_vector(7 downto 0);
di_i : in std_logic_vector(63 downto 0);
do_i : out std_logic_vector(63 downto 0);
-- Data Memory
we_d : in std_logic;
en_d : in std_logic;
addr_d : in std_logic_vector(31 downto 3);
ben_d : in std_logic_vector(7 downto 0);
di_d : in std_logic_vector(63 downto 0);
do_d : out std_logic_vector(63 downto 0)
);
end component MMU;
component RegFile
generic ( WIDTH : integer := 64;
DEPTH : integer := 32;
DEPTH_LOG : integer := 5
);
port (
clk : in std_logic;
resetb : in std_logic;
en : in std_logic;
-- Read rs
rs_a : in std_logic_vector(DEPTH_LOG-1 downto 0);
rs_d : out std_logic_vector(WIDTH-1 downto 0);
-- Read rt
rt_a : in std_logic_vector(DEPTH_LOG-1 downto 0);
rt_d : out std_logic_vector(WIDTH-1 downto 0);
-- Write back
wb_we : in std_logic;
wb_a : in std_logic_vector(DEPTH_LOG-1 downto 0);
wb_d : in std_logic_vector(WIDTH-1 downto 0)
);
end component RegFile;
signal core_resetb : std_logic;
signal rf_en, rf_wb_we : std_logic;
signal rf_rs_a, rf_rt_a, rf_wb_a : std_logic_vector(4 downto 0);
signal rf_rs_d, rf_rt_d, rf_wb_d : std_logic_vector(63 downto 0);
signal core_mmu_we_i, core_mmu_en_i, core_mmu_we_d, core_mmu_en_d : std_logic;
signal
core_mmu_addr_i, core_mmu_addr_d,
boot_mmu_addr_i, mmu_addr_i, mmu_addr_d : std_logic_vector(31 downto 0);
signal core_mmu_ben_i, core_mmu_ben_d,
boot_mmu_ben_i, mmu_ben_i, mmu_ben_d : std_logic_vector(7 downto 0);
signal core_mmu_di_i, core_mmu_do_i,
core_mmu_di_d, core_mmu_do_d,
boot_mmu_di_i,
mmu_di_i, mmu_di_d, mmu_do_i, mmu_do_d : std_logic_vector(63 downto 0);
signal boot_mmu_we_i, boot_mmu_en_i : std_logic;
signal mmu_we_i, mmu_en_i, mmu_we_d, mmu_en_d : std_logic;
signal boot_possibly_done, boot_done_temp, boot_second_word : std_logic;
signal boot_addr : unsigned(31 downto 0);
signal boot_wait_one_clock : std_logic;
constant ZERO64 : std_logic_vector(63 downto 0) := (others => '0');
begin
core : CPUCore
port map (
clk=>clk, resetb=>core_resetb,
core_rf_en=>rf_en, core_rf_rs_a=>rf_rs_a, core_rf_rs_d=>rf_rs_d,
core_rf_rt_a=>rf_rt_a, core_rf_rt_d=>rf_rt_d,
core_rf_wb_we=>rf_wb_we, core_rf_wb_a=>rf_wb_a, core_rf_wb_d=>rf_wb_d,
core_mmu_we_i=>core_mmu_we_i, core_mmu_en_i=>core_mmu_en_i,
core_mmu_addr_i=>core_mmu_addr_i(31 downto 3),
core_mmu_ben_i=>core_mmu_ben_i,
core_mmu_di_i=>core_mmu_di_i, core_mmu_do_i=>core_mmu_do_i,
core_mmu_we_d=>core_mmu_we_d, core_mmu_en_d=>core_mmu_en_d,
core_mmu_addr_d=>core_mmu_addr_d(31 downto 3),
core_mmu_ben_d=>core_mmu_ben_d,
core_mmu_di_d=>core_mmu_di_d, core_mmu_do_d=>core_mmu_do_d
);
MMU0 : MMU
port map (
clk=>clk, resetb=>resetb,
we_i=>mmu_we_i, en_i=>mmu_en_i, addr_i=>mmu_addr_i(31 downto 3),
ben_i=>mmu_ben_i, di_i=>mmu_di_i, do_i=>mmu_do_i,
we_d=>mmu_we_d, en_d=>mmu_en_d, addr_d=>mmu_addr_d(31 downto 3),
ben_d=>mmu_ben_d, di_d=>mmu_di_d, do_d=>mmu_do_d
);
RegFile0 : Regfile
port map (
clk=>clk, resetb=>resetb, en=>rf_en,
rs_a=>rf_rs_a, rs_d=>rf_rs_d,
rt_a=>rf_rt_a, rt_d=>rf_rt_d,
wb_we=>rf_wb_we, wb_a=>rf_wb_a, wb_d=>rf_wb_d
);
core_mmu_do_i <= mmu_do_i;
core_mmu_do_d <= mmu_do_d;
mmu_addr_i <= core_mmu_addr_i when boot_done_temp = '1' else boot_mmu_addr_i;
mmu_addr_d <= core_mmu_addr_d;
mmu_ben_i <= core_mmu_ben_i when boot_done_temp = '1' else boot_mmu_ben_i;
mmu_ben_d <= core_mmu_ben_d;
mmu_di_i <= core_mmu_di_i when boot_done_temp = '1' else boot_mmu_di_i;
mmu_di_d <= core_mmu_di_d;
core_mmu_do_d <= mmu_do_d;
mmu_we_i <= core_mmu_we_i when boot_done_temp = '1' else boot_mmu_we_i;
mmu_we_d <= core_mmu_we_d;
mmu_en_i <= core_mmu_en_i when boot_done_temp = '1' else boot_mmu_en_i;
mmu_en_d <= core_mmu_en_d;
boot_done <= boot_done_temp;
cpu_rom_addr <= boot_addr;
boot_mmu_en_i <= '0' when boot_done_temp = '1' else '1';
boot_mmu_we_i <= '0' when boot_done_temp = '1' else '1';
-- boot_mmu_addr_i <= std_logic_vector(boot_addr);
boot_loader : process (clk, resetb)
begin
if (resetb = '0') then
core_resetb <= '0';
boot_done_temp <= '0';
boot_second_word <= '0';
boot_addr <= (others => '0');
boot_wait_one_clock <= '0';
boot_possibly_done <= '0';
elsif (clk'event and clk = '1') then
if (boot_done_temp = '0' and boot_wait_one_clock = '0') then
if (boot_mmu_di_i = ZERO64) then
if (boot_possibly_done = '1') then
boot_done_temp <= '1';
boot_wait_one_clock <= '1';
else
boot_possibly_done <= '1';
end if;
else
boot_possibly_done <= '0';
end if;
boot_addr <= boot_addr + 4;
boot_mmu_addr_i <= std_logic_vector(boot_addr);
-- Low word, then high word
if (boot_addr(2) = '1') then
boot_mmu_ben_i <= "00001111";
boot_mmu_di_i(63 downto 32) <= cpu_rom_data;
else
boot_mmu_ben_i <= "11110000";
boot_mmu_di_i(31 downto 0) <= cpu_rom_data;
end if;
elsif (boot_wait_one_clock = '1') then
core_resetb <= '1';
end if;
end if;
end process boot_loader;
end architecture syn;
| gpl-3.0 | 4f02af1fbe1962daa665f303f01027e5 | 0.574339 | 2.835434 | false | false | false | false |
wfjm/w11 | rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vhd | 1 | 11,702 | -- $Id: tb_nx_cram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nx_cram_memctl - sim
-- Description: Test bench for nx_cram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/micron/mt45w8mw16b
-- tbd_nx_cram_memctl [UUT, abstact]
--
-- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as)
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl
-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl
-- 2010-05-23 293 1.0 Initial version (derived from tb_s3_sram_memctl)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_nx_cram_memctl is
end tb_nx_cram_memctl;
architecture sim of tb_nx_cram_memctl is
component tbd_nx_cram_memctl is -- CRAM controller (abstract) [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv22 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slbit := '0';
signal O_MEM_BE_N : slv2 := (others=>'0');
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADV_N : slbit := '0';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'0');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv22 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv22 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv22 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : Delay_length := 20 ns; -- when changed update also
-- READ0DELAY ect delays !!
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 7.5 ns; -- compatible ucf for
constant c2out_time : Delay_length := 12.0 ns; -- tbd_nx_cram_memctl_as
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
UUT : tbd_nx_cram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_nx_cram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv22 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 7, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
wait for clock_period;
REQ <= '0';
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 7, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
wait for clock_period;
REQ <= '0';
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" be="));
write(oline, not O_MEM_BE_N, right, 4);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 6, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 4, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
| gpl-3.0 | fdbe8e3006a584913de9aa443d65f26c | 0.487609 | 3.517283 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibdr_rk11.vhd | 1 | 18,823 | -- $Id: ibdr_rk11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rk11 - syn
-- Description: ibus dev(rem): RK11-A/B
--
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-06-08 561 14.7 131013 xc6slx16-2 44 139 9 60 s 5.6
-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.3.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
-- BUGFIX: sector counter now counts 000,...,013.
-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
-- BUGFIX: re-work the seek complete handling
-- 2008-08-22 161 1.0.6 use iblib
-- 2008-05-30 151 1.0.5 BUGFIX: do control reset locally now, add CRDONE
-- 2008-03-30 131 1.0.4 issue interrupt when IDE bit set with GO=0
-- 2008-02-23 118 1.0.3 remove redundant condition in rkda access code
-- fix bug in control reset logic (we's missing)
-- 2008-01-20 113 1.0.2 Fix busy handling when control reset done
-- 2008-01-20 112 1.0.1 Fix scp handling; use BRESET
-- 2008-01-06 111 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_rk11 is -- ibus dev(rem): RK11
-- fixed address: 177400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_rk11;
architecture syn of ibdr_rk11 is
constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16));
constant ibaddr_rkds : slv3 := "000"; -- rkds address offset
constant ibaddr_rker : slv3 := "001"; -- rker address offset
constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset
constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset
constant ibaddr_rkba : slv3 := "100"; -- rkba address offset
constant ibaddr_rkda : slv3 := "101"; -- rkda address offset
constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset
constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset
subtype rkds_ibf_id is integer range 15 downto 13;
constant rkds_ibf_adry : integer := 6;
constant rkds_ibf_scsa : integer := 4;
subtype rkds_ibf_sc is integer range 3 downto 0;
subtype rker_ibf_he is integer range 15 downto 5;
constant rker_ibf_cse : integer := 1;
constant rker_ibf_wce : integer := 0;
constant rkcs_ibf_err : integer := 15;
constant rkcs_ibf_he : integer := 14;
constant rkcs_ibf_scp : integer := 13;
constant rkcs_ibf_maint : integer := 12;
constant rkcs_ibf_rdy : integer := 7;
constant rkcs_ibf_ide : integer := 6;
subtype rkcs_ibf_mex is integer range 5 downto 4;
subtype rkcs_ibf_func is integer range 3 downto 1;
constant rkcs_ibf_go : integer := 0;
subtype rkda_ibf_drsel is integer range 15 downto 13;
subtype rkmr_ibf_rid is integer range 15 downto 13; -- rem id
constant rkmr_ibf_crdone: integer := 11; -- contr. reset done
constant rkmr_ibf_sbclr : integer := 10; -- clear sbusy's
constant rkmr_ibf_creset: integer := 9; -- control reset
constant rkmr_ibf_fdone : integer := 8; -- func done
subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done
constant func_creset : slv3 := "000"; -- func: control reset
constant func_write : slv3 := "001"; -- func: write
constant func_read : slv3 := "010"; -- func: read
constant func_wchk : slv3 := "011"; -- func: write check
constant func_seek : slv3 := "100"; -- func: seek
constant func_rchk : slv3 := "101"; -- func: read check
constant func_dreset : slv3 := "110"; -- func: drive reset
constant func_wlock : slv3 := "111"; -- func: write lock
type state_type is (
s_idle,
s_init
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
id : slv3; -- rkds: drive id of search done
sc : slv4; -- rkds: sector counter
cse : slbit; -- rker: check sum error
wce : slbit; -- rker: write check error
he : slbit; -- rkcs: hard error
scp : slbit; -- rkcs: seek complete
maint : slbit; -- rkcs: maintenance mode
rdy : slbit; -- rkcs: control ready
ide : slbit; -- rkcs: interrupt on done enable
drsel : slv3; -- rkda: currently selected drive
fireq : slbit; -- func done interrupt request flag
sireq : slv8; -- seek done interrupt request flags
sbusy : slv8; -- seek busy flags
rid : slv3; -- drive id for rem ds reads
icnt : slv3; -- init state counter
creset : slbit; -- control reset flag
crdone : slbit; -- control reset done since last fdone
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
s_init, -- state
(others=>'0'), -- id
(others=>'0'), -- sc
'0','0', -- cse, wce
'0','0','0', -- he, scp, maint
'1', -- rdy (SET TO 1)
'0', -- ide
(others=>'0'), -- drsel
'0', -- fireq
(others=>'0'), -- sireq
(others=>'0'), -- sbusy
(others=>'0'), -- rid
(others=>'0'), -- icnt
'0','1' -- creset, crdone
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';
signal MEM_ADDR : slv4 := (others=>'0');
signal MEM_DIN : slv16 := (others=>'0');
signal MEM_DOUT : slv16 := (others=>'0');
begin
MEM_1 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_1_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte1),
DO => MEM_DOUT(ibf_byte1));
MEM_0 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_0_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte0),
DO => MEM_DOUT(ibf_byte0));
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET='1' or R_REGS.creset='1' then
R_REGS <= regs_init;
if R_REGS.creset = '1' then
R_REGS.sbusy <= N_REGS.sbusy;
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable icrip : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
variable iscval : slbit := '0';
variable iscid : slv3 := (others=>'0');
variable iei_req : slbit := '0';
variable imem_we0 : slbit := '0';
variable imem_we1 : slbit := '0';
variable imem_addr : slv4 := (others=>'0');
variable imem_din : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
icrip := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc or r.maint;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
iscval := '0';
iscid := (others=>'0');
iei_req := '0';
imem_we0 := '0';
imem_we1 := '0';
imem_addr := '0' & IB_MREQ.addr(3 downto 1);
imem_din := IB_MREQ.din;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
n.ibsel := '1';
end if;
-- internal state machine (for control reset)
case r.state is
when s_idle =>
null;
when s_init =>
ibhold := r.ibsel; -- hold ibus when controller busy
icrip := '1';
n.icnt := slv(unsigned(r.icnt) + 1);
if unsigned(r.icnt) = 7 then
n.state := s_idle;
end if;
when others => null;
end case;
-- ibus transactions
if r.ibsel='1' and ibhold='0' then -- selected and not holding
idout := MEM_DOUT;
imem_we0 := ibw0;
imem_we1 := ibw1;
case IB_MREQ.addr(3 downto 1) is
when ibaddr_rkds => -- RKDS -- drive status register ----
if ibrem = '0' then
imem_addr := '1' & r.drsel; -- loc read ds data: drsel as addr.
else
imem_addr := '1' & r.rid; -- rem read ds data: rid as addr.
end if;
idout(rkds_ibf_id) := r.id;
if ibrem = '0' then -- loc ? simulate drive sector monitor
if r.sc = MEM_DOUT(rkds_ibf_sc) then
idout(rkds_ibf_scsa) := '1';
else
idout(rkds_ibf_scsa) := '0';
end if;
idout(rkds_ibf_sc) := r.sc;
end if;
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy
end if;
if ibwrem = '1' then -- rem write ? than update ds data
imem_addr := '1' & IB_MREQ.din(rkds_ibf_id); -- use id field as addr
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rker => -- RKER -- error register ------------
idout(4 downto 2) := (others=>'0'); -- unassigned bits
idout(rker_ibf_cse) := r.cse; -- use state bits (cleared at go !)
idout(rker_ibf_wce) := r.wce;
if ibwrem = '1' then -- rem write ?
if unsigned(IB_MREQ.din(rker_ibf_he)) /= 0 then -- hard errors set ?
n.he := '1';
else
n.he := '0';
end if;
n.cse := IB_MREQ.din(rker_ibf_cse); -- mirror cse bit
n.wce := IB_MREQ.din(rker_ibf_wce); -- mirror wce bit
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rkcs => -- RKCS -- control status register ---
idout(rkcs_ibf_err) := r.he or r.cse or r.wce;
idout(rkcs_ibf_he) := r.he;
idout(rkcs_ibf_scp) := r.scp;
idout(rkcs_ibf_rdy) := r.rdy;
idout(rkcs_ibf_go) := not r.rdy;
if ibw1 = '1' then
n.maint := IB_MREQ.din(rkcs_ibf_maint); -- mirror maint bit
end if;
if ibw0 = '1' then
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit
if n.ide = '0' then -- if IE set to 0
n.fireq := '0'; -- cancel all pending
n.sireq := (others=>'0'); -- interrupt requests
end if;
if IB_MREQ.din(rkcs_ibf_go) = '1' then -- GO=1 ?
if r.rdy = '1' then -- ready and GO ?
n.scp := '0'; -- go clears scp !
n.rdy := '0'; -- mark busy
n.cse := '0'; -- clear soft errors
n.wce := '0';
n.fireq := '0'; -- cancel pend. int
if IB_MREQ.din(rkcs_ibf_func)=func_creset then -- control reset?
n.creset := '1'; -- handle locally
else
ilam := '1'; -- issue lam
end if;
if IB_MREQ.din(rkcs_ibf_func)=func_seek or -- if seek
IB_MREQ.din(rkcs_ibf_func)=func_dreset then -- or drive reset
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- drive busy
if n.ide = '1' then -- if enabled
n.fireq := '1'; -- interrupt !
end if;
end if;
end if;
else -- GO=0
if r.ide='0' and n.ide='1' and -- if IDE 0->1 transition
r.rdy='1' then -- and controller ready
n.fireq := '1'; -- issue interrupt
end if;
end if;
end if;
when ibaddr_rkda => -- RKDA -- disk address register -----
if ibrem = '0' then -- loc access ?
if r.rdy = '0' then -- controller busy ?
imem_we0 := '0'; -- suppress write
imem_we1 := '0';
end if;
end if;
if imem_we1 = '1' then
n.drsel := IB_MREQ.din(rkda_ibf_drsel); -- mirror drsel bits
end if;
when ibaddr_rkmr => -- RKMR -- maintenance register ------
idout := (others=>'0');
idout(rkmr_ibf_rid) := r.rid;
idout(rkmr_ibf_crdone) := r.crdone;
idout(rkmr_ibf_sdone) := r.sbusy;
if ibwrem = '1' then -- rem write ?
n.rid := IB_MREQ.din(rkmr_ibf_rid);
if r.ide='1' and IB_MREQ.din(rkmr_ibf_sbclr)='0' then
n.sireq := r.sireq or (IB_MREQ.din(rkmr_ibf_sdone) and r.sbusy);
end if;
n.sbusy := r.sbusy and not IB_MREQ.din(rkmr_ibf_sdone);
if IB_MREQ.din(rkmr_ibf_fdone) = '1' then -- func completed
n.rdy := '1';
n.crdone := '0';
if r.ide = '1' then
n.fireq := '1';
end if;
end if;
if IB_MREQ.din(rkmr_ibf_creset) = '1' then -- control reset
n.creset := '1';
end if;
end if;
when others => -- all other regs
null;
end case;
end if;
iscval := '1';
if r.sireq(7) = '1' then iscid := "111";
elsif r.sireq(6) = '1' then iscid := "110";
elsif r.sireq(5) = '1' then iscid := "101";
elsif r.sireq(4) = '1' then iscid := "100";
elsif r.sireq(3) = '1' then iscid := "011";
elsif r.sireq(2) = '1' then iscid := "010";
elsif r.sireq(1) = '1' then iscid := "001";
elsif r.sireq(0) = '1' then iscid := "000";
else
iscval := '0';
end if;
if r.ide = '1' then
if r.fireq='1' or iscval='1' then
iei_req := '1';
end if;
end if;
if EI_ACK = '1' then -- interrupt executed
if r.fireq = '1' then
n.scp := '0'; -- clear scp flag, is command end
n.fireq := '0';
elsif iscval = '1' then -- was a seek done
n.scp := '1'; -- signal seek complete interrupt
n.id := iscid; -- load id
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit
end if;
end if;
if icrip = '1' then -- control reset in progress ?
imem_addr := '0' & r.icnt; -- use icnt as addr
imem_din := (others=>'0'); -- force data to zero
imem_we0 := '1'; -- enable writes
imem_we1 := '1';
end if;
if CE_MSEC = '1' then -- advance sector counter every msec
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#)
n.sc := (others=>'0');
else
n.sc := slv(unsigned(r.sc) + 1);
end if;
end if;
N_REGS <= n;
MEM_0_WE <= imem_we0;
MEM_1_WE <= imem_we1;
MEM_ADDR <= imem_addr;
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
end syn;
| gpl-3.0 | 4f7d37a658d7f6e17a64fbe01c85b0c5 | 0.466823 | 3.652115 | false | false | false | false |
boztalay/OZ-4 | OZ-4 FPGA/OZ4/ieee_proposed/fixed_pkg_c.vhd | 3 | 291,386 | ------------------------------------------------------------------------------
-- "fixed_pkg" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_pkg.all;
-- Last Modified: $Date: 2006/05/09 19:21:24 $
-- RCS ID: $Id: fixed_pkg_c.vhd,v 1.1 2006/05/09 19:21:24 sandeepd Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- synthesis translate_off
use std.textio.all;
-- synthesis translate_on
package fixed_pkg is
--%%% Uncomment the Generics
-- new work.fixed_generic_pkg
-- generic map (
-- fixed_round_style => true; -- fixed_round
-- fixed_overflow_style => true; -- fixed_saturate
-- fixed_guard_bits => 3; -- number of guard bits
-- no_warning => false -- show warnings
-- );
--%%% REMOVE THE REST OF THIS FILE.
constant fixed_round_style : BOOLEAN := true; -- round
constant fixed_overflow_style : BOOLEAN := true; -- saturate
constant fixed_guard_bits : NATURAL := 3; -- number of guard bits
constant no_warning : BOOLEAN := false; -- issue warnings
-- Author David Bishop ([email protected])
-- These 5 constants are used as defaults.
-- There is a mechanism to override them in every function
constant fixed_round : BOOLEAN := true; -- Turn on rounding routine
constant fixed_truncate : BOOLEAN := false; -- Trun off rounding routine
constant fixed_saturate : BOOLEAN := true; -- Saturate large numbers
constant fixed_wrap : BOOLEAN := false; -- Wrap large numbers
constant fixedsynth_or_real : BOOLEAN; -- differed constant
-- base Unsigned fixed point type, downto direction assumed
type ufixed is array (INTEGER range <>) of STD_LOGIC;
-- base Signed fixed point type, downto direction assumed
type sfixed is array (INTEGER range <>) of STD_LOGIC;
-----------------------------------------------------------------------------
-- Fixed point type is defined as follows:
-- 0000000000
-- 4321012345
-- 4 0 -5
-- The decimal point is assumed between the "0" and "-1" index
-- Thus "0011010000" = 6.5 and would be written as 00110.10000
-- All types are assumed to be in the "downto" direction.
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Modify the sign of the number, 2's complement
function "abs" (arg : sfixed) return sfixed;
function "-" (arg : sfixed)return sfixed;
-- Convert a signed fixed to an unsigned fixed
function "abs" (arg : sfixed) return ufixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : sfixed) return sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : sfixed) return sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : sfixed) return sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : sfixed) return sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (l, r : sfixed) return sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- Overload routines. In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "+" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "+" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "-" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "-" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : ufixed; r : REAL) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto min(b,0))
function "rem" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto min(d,0))
function "rem" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto min(b,0))
function "mod" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto min(d,0))
function "mod" (l : NATURAL; r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "+" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "+" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "-" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "-" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto min(b,0))
function "rem" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto min(d,0))
function "rem" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto min(b,0))
function "mod" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto min(d,0))
function "mod" (l : INTEGER; r : sfixed) return sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed;
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed;
function scalb (y : ufixed; N : SIGNED) return ufixed;
function scalb (y : sfixed; N : integer) return sfixed;
function scalb (y : sfixed; N : SIGNED) return sfixed;
function Is_Negative (arg : sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : ufixed) return BOOLEAN;
function ">" (l, r : sfixed) return BOOLEAN;
function "<" (l, r : ufixed) return BOOLEAN;
function "<" (l, r : sfixed) return BOOLEAN;
function "<=" (l, r : ufixed) return BOOLEAN;
function "<=" (l, r : sfixed) return BOOLEAN;
function ">=" (l, r : ufixed) return BOOLEAN;
function ">=" (l, r : sfixed) return BOOLEAN;
function "=" (l, r : ufixed) return BOOLEAN;
function "=" (l, r : sfixed) return BOOLEAN;
function "/=" (l, r : ufixed) return BOOLEAN;
function "/=" (l, r : sfixed) return BOOLEAN;
--%%% Uncomment the following (new syntax)
-- function "?=" (L, R : ufixed) return BOOLEAN;
-- function "?=" (L, R : sfixed) return BOOLEAN;
-- --%%% remove the following (old syntax)
function \?=\ (L, R : ufixed) return STD_ULOGIC;
function \?=\ (L, R : sfixed) return STD_ULOGIC;
-- These need to be overloaded for sfixed and ufixed
function \?/=\ (L, R : ufixed) return STD_ULOGIC;
function \?>\ (L, R : ufixed) return STD_ULOGIC;
function \?>=\ (L, R : ufixed) return STD_ULOGIC;
function \?<\ (L, R : ufixed) return STD_ULOGIC;
function \?<=\ (L, R : ufixed) return STD_ULOGIC;
function \?/=\ (L, R : sfixed) return STD_ULOGIC;
function \?>\ (L, R : sfixed) return STD_ULOGIC;
function \?>=\ (L, R : sfixed) return STD_ULOGIC;
function \?<\ (L, R : sfixed) return STD_ULOGIC;
function \?<=\ (L, R : sfixed) return STD_ULOGIC;
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC;
-- function "?/=" (L, R : ufixed) return STD_ULOGIC;
-- function "?>" (L, R : ufixed) return STD_ULOGIC;
-- function "?>=" (L, R : ufixed) return STD_ULOGIC;
-- function "?<" (L, R : ufixed) return STD_ULOGIC;
-- function "?<=" (L, R : ufixed) return STD_ULOGIC;
-- function "?=" (L, R : sfixed) return STD_ULOGIC;
-- function "?/=" (L, R : sfixed) return STD_ULOGIC;
-- function "?>" (L, R : sfixed) return STD_ULOGIC;
-- function "?>=" (L, R : sfixed) return STD_ULOGIC;
-- function "?<" (L, R : sfixed) return STD_ULOGIC;
-- function "?<=" (L, R : sfixed) return STD_ULOGIC;
function std_match (L, R : ufixed) return BOOLEAN;
function std_match (L, R : sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : ufixed) return ufixed;
function minimum (l, r : ufixed) return ufixed;
function maximum (l, r : sfixed) return sfixed;
function minimum (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "max(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : REAL) return BOOLEAN;
function "/=" (l : ufixed; r : REAL) return BOOLEAN;
function ">=" (l : ufixed; r : REAL) return BOOLEAN;
function "<=" (l : ufixed; r : REAL) return BOOLEAN;
function ">" (l : ufixed; r : REAL) return BOOLEAN;
function "<" (l : ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : ufixed) return BOOLEAN;
function "/=" (l : REAL; r : ufixed) return BOOLEAN;
function ">=" (l : REAL; r : ufixed) return BOOLEAN;
function "<=" (l : REAL; r : ufixed) return BOOLEAN;
function ">" (l : REAL; r : ufixed) return BOOLEAN;
function "<" (l : REAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "max(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : sfixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : REAL) return BOOLEAN;
function "/=" (l : sfixed; r : REAL) return BOOLEAN;
function ">=" (l : sfixed; r : REAL) return BOOLEAN;
function "<=" (l : sfixed; r : REAL) return BOOLEAN;
function ">" (l : sfixed; r : REAL) return BOOLEAN;
function "<" (l : sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : sfixed) return BOOLEAN;
function "/=" (l : REAL; r : sfixed) return BOOLEAN;
function ">=" (l : REAL; r : sfixed) return BOOLEAN;
function "<=" (l : REAL; r : sfixed) return BOOLEAN;
function ">" (l : REAL; r : sfixed) return BOOLEAN;
function "<" (l : REAL; r : sfixed) return BOOLEAN;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed;
function "and" (L, R : ufixed) return ufixed;
function "or" (L, R : ufixed) return ufixed;
function "nand" (L, R : ufixed) return ufixed;
function "nor" (L, R : ufixed) return ufixed;
function "xor" (L, R : ufixed) return ufixed;
function "xnor" (L, R : ufixed) return ufixed;
function "not" (L : sfixed) return sfixed;
function "and" (L, R : sfixed) return sfixed;
function "or" (L, R : sfixed) return sfixed;
function "nand" (L, R : sfixed) return sfixed;
function "nor" (L, R : sfixed) return sfixed;
function "xor" (L, R : sfixed) return sfixed;
function "xnor" (L, R : sfixed) return sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed;
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC;
function nand_reduce(arg : ufixed) return STD_ULOGIC;
function or_reduce(arg : ufixed) return STD_ULOGIC;
function nor_reduce(arg : ufixed) return STD_ULOGIC;
function xor_reduce(arg : ufixed) return STD_ULOGIC;
function xnor_reduce(arg : ufixed) return STD_ULOGIC;
function and_reduce(arg : sfixed) return STD_ULOGIC;
function nand_reduce(arg : sfixed) return STD_ULOGIC;
function or_reduce(arg : sfixed) return STD_ULOGIC;
function nor_reduce(arg : sfixed) return STD_ULOGIC;
function xor_reduce(arg : sfixed) return STD_ULOGIC;
function xnor_reduce(arg : sfixed) return STD_ULOGIC;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic;
-- function "nand" ( arg : ufixed ) RETURN std_ulogic;
-- function "or" ( arg : ufixed ) RETURN std_ulogic;
-- function "nor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic;
-- function "and" ( arg : sfixed ) RETURN std_ulogic;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic;
-- function "or" ( arg : sfixed ) RETURN std_ulogic;
-- function "nor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic;
-- returns arg'low-1 if not found
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
-- returns arg'high+1 if not found
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is true, then the result will be rounded. If the MSB
-- of the remainder is a "1" AND the LSB of the unround result is a '1' or
-- the lower bits of the remainder include a '1' then the result will be
-- increased by the smallest representable number for that type.
-- The default is "true" for round_style.
-- "overflow_style" can be "true" (saturate mode) or "false" (wrap mode).
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- "size_res" functions create the size of the output from the length
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
-- Performs a casting. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL;
-- Integer to sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return sfixed;
-- unsigned fixed point to signed fixed point (adds a "0" sign bit)
function add_sign (
arg : ufixed) -- unsigned fixed point
return sfixed;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to real
function to_real (
arg : sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- Maps meta-logical values
function to_01 (
s : ufixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed;
-- maps meta-logical values
function to_01 (
s : sfixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed;
function Is_X (arg : ufixed) return BOOLEAN;
function Is_X (arg : sfixed) return BOOLEAN;
function to_X01 (arg : ufixed) return ufixed;
function to_X01 (arg : sfixed) return sfixed;
function to_X01Z (arg : ufixed) return ufixed;
function to_X01Z (arg : sfixed) return sfixed;
function to_UX01 (arg : ufixed) return ufixed;
function to_UX01 (arg : sfixed) return sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not cast these vectors because of their negative index.
function to_slv (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [ufixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [ufixed return STD_LOGIC_VECTOR];
function to_slv (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [sfixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [sfixed return STD_LOGIC_VECTOR];
function to_sulv (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
function to_sulv (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- rtl_synthesis off
-- synthesis translate_off
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out ufixed);
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out sfixed);
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, ufixed, SIDE, width];
alias bwrite is WRITE [LINE, sfixed, SIDE, width];
alias bread is READ [LINE, ufixed];
alias bread is READ [LINE, ufixed, BOOLEAN];
alias bread is READ [LINE, sfixed];
alias bread is READ [LINE, sfixed, BOOLEAN];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out ufixed);
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out sfixed);
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out ufixed);
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out sfixed);
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [ufixed, SIDE, width return STRING];
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_string (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [sfixed, SIDE, width return STRING];
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed;
alias from_bstring is from_string [STRING, ufixed return ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed;
alias from_bstring is from_string [STRING, sfixed return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed;
alias from_bstring is from_string [STRING return ufixed];
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed;
function from_hstring (
hstring : STRING) -- hex string
return ufixed;
function from_string (
bstring : STRING) -- binary string
return sfixed;
alias from_bstring is from_string [STRING return sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return sfixed;
function from_hstring (
hstring : STRING) -- hex string
return sfixed;
-- synthesis translate_on
-- rtl_synthesis on
-- This type is here for the floating point package.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round to positive
round_neginf, -- Round to negate
round_zero); -- Round towards zero
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
end package fixed_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_textio.all; -- %%% for testing only
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : ufixed (0 downto 1) := (others => '0');
constant NASF : sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
--%%% Can be removed in vhdl-200x, will be implicit.
-- purpose: To find the largest of 2 numbers
function maximum (l, r : INTEGER)
return INTEGER is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
function minimum (l, r : INTEGER)
return INTEGER is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
-- %%% Remove the following function (duplicates of new numeric_std)
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
-- %%% Replace or_reducex with "or", and_reducex with "and", and
-- %%% xor_reducex with "xor", then remove the following 3 functions
-- purpose: OR all of the bits in a vector together
-- This is a copy of the proposed "or_reduce" from 1076.3
function or_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reducex (BUS_int (BUS_int'left downto Half));
Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reducex;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reducex (BUS_int (BUS_int'left downto Half));
Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reducex;
function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reducex (BUS_int (BUS_int'left downto Half));
Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reducex;
--%%% remove the following function and table
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% end remove
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report "FIXED_GENERIC_PKG: Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : sfixed) -- input
return sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : sfixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : ufixed) -- input
return ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : ufixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type cast a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := ufixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := sfixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "ufixed" into an "unsigned", used internally
function to_uns (
arg : ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return UNSIGNED(to_X01(std_logic_vector(slv)));
end function to_uns;
-- Type cast an "sfixed" into a "signed", used internally
function to_s (
arg : sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return SIGNED(to_X01(std_logic_vector(slv)));
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in ufixed;
result : out ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0) :=
(others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in sfixed;
result : out sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reducex (STD_LOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : ufixed;
remainder : ufixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : sfixed;
remainder : sfixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- else
-- result(result'high) := arg(arg'high); -- fix sign bit in wrap
end if;
end if;
return result;
end function round_fixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- casting functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_slv (
arg : ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_slv (
arg : sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_sulv (
arg : ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_sulv (
arg : sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
begin
return to_ufixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
begin
return to_sfixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
function "abs" (arg : sfixed) return ufixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : sfixed(left_index+1 downto right_index);
variable result : ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := ufixed (xarg (left_index downto right_index));
return result;
end function "abs";
-- Addition
function "+" (
l, r : ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
variable result : ufixed (l'high - mine(r'low, r'low)
downto mine (l'low, l'low) - r'high -1);
variable dresult : ufixed (result'high downto result'low -guard_bits);
variable lresize : ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
variable result : sfixed (l'high - mine(r'low, r'low)+1
downto mine (l'low, l'low) - r'high);
variable dresult : sfixed (result'high downto result'low-guard_bits);
variable lresize : sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
constant one : ufixed (0 downto 0) := "1";
begin
return divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
constant one : sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
variable result : ufixed (minimum(l'high, r'high) downto mine(l'low, r'low));
variable dresult : ufixed (r'high downto r'low);
variable lresize : ufixed (maximum(l'high, r'low) downto mins(r'low, r'low));
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rslv := to_uns (cleanvec(r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.rem uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap,
round_style => round_style);
-- result(result'high downto r'low) := dresult(result'high downto r'low);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (minimum(r'high, l'high) downto mine(r'low, l'low));
variable neg_result : sfixed (minimum(r'high, l'high)+1 downto mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
result := sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return modulo (l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return modulo(l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (r'high downto
mine(r'low, l'low));
variable dresult : sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
dresult := "0" & sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed is
variable result : ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : ufixed; N : SIGNED) return ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : sfixed; N : integer) return sfixed is
variable result : sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : sfixed; N : SIGNED) return sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : ufixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
function and_reduce(arg : sfixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : sfixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";
-- function "nand" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- function "and" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC is
function \?=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\(lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : ufixed) return STD_ULOGIC is
function \?/=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : ufixed) return STD_ULOGIC is
function \?>\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : ufixed) return STD_ULOGIC is
function \?>=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : ufixed) return STD_ULOGIC is
function \?<\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : ufixed) return STD_ULOGIC is
function \?<=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- function "?=" (L, R : sfixed) return STD_ULOGIC is
function \?=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : sfixed) return STD_ULOGIC is
function \?/=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : sfixed) return STD_ULOGIC is
function \?>\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : sfixed) return STD_ULOGIC is
function \?>=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : sfixed) return STD_ULOGIC is
function \?<\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : sfixed) return STD_ULOGIC is
function \?<=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- %%% end replace
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
--%%% end remove
-- compare functions
function "=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : ufixed) return ufixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function maximum (l, r : sfixed) return sfixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (l, r : ufixed) return ufixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function minimum (l, r : sfixed) return sfixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable sresult : UNSIGNED (left_index downto 0); -- integer portion
variable bound : NATURAL; -- find the numerical bounds
begin
if (left_index < fw) then
return NAUF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index+1);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if arg >= bound or left_index < 0 then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_UFIXED(NATURAL): vector truncated"
severity warning;
if (overflow_style = fixed_wrap) then -- wrap
if bound = 0 then
argx := 0;
else
argx := arg mod bound;
end if;
else -- saturate
return saturate (result'high, result'low);
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_unsigned (argx, sresult'high+1);
result := resize (arg => ufixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable sresult : SIGNED (left_index+1 downto 0); -- integer portion
variable bound : NATURAL := 0;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if (arg >= bound or arg < -bound or left_index < 0) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_wrap then -- wrap
if bound = 0 then -- negative integer_range trap
argx := 0;
else -- shift off the top bits
argx := arg rem (bound*2);
end if;
else -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_signed (argx, sresult'length);
result := resize (arg => sfixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable Xresult : ufixed (left_index downto fw-guard_bits) := (others => '0');
variable presult : REAL;
variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report "FIXED_GENERIC_PKG.TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_UFIXED(REAL): vector truncated"
severity warning;
overflow_needed := (overflow_style = fixed_saturate);
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable Xresult : sfixed (left_index+1 downto fw-guard_bits) := (others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NAUF;
end if;
result := resize (arg => ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- casted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NASF;
end if;
result := resize (arg => sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- casted version
function to_sfixed (
arg : SIGNED) -- signed
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return sfixed(xarg);
end function to_sfixed;
function add_sign (arg : ufixed) return sfixed is
variable result : sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function add_sign;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
constant sat : ufixed (left_index downto right_index) := (others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable sat : sfixed (left_index downto right_index) := (others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed is
variable result : ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed is
variable result : sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : sfixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : sfixed; -- ufixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := abs(arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (minimum(31, left_index+1) downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (minimum(31, left_index+1) downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : ufixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed is
variable result : ufixed (s'range); -- result
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function to_01 (
s : sfixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed is
variable result : sfixed (s'range);
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function Is_X (
arg : ufixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function Is_X (
arg : sfixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function To_X01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : ufixed (arghigh downto arglow);
variable result : ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reducex(to_slv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style and
or_reducex(to_slv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : sfixed (arghigh downto arglow);
variable result : sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style) then
reduced := or_reducex(to_slv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded functions
function "+" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l +
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l +
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l -
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l -
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l *
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l *
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l /
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l /
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l rem
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l rem
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l mod
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l mod
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
-- Overloaded functions for integers
function "+" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l + to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)); -- rounding not needed
end function "+";
function "+" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l + to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "+";
function "+" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l - to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l - to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l * to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l * to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l / to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l / to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l rem to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l rem to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l mod to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l mod to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
-- overloaded compare functions
function "=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
function "=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l = to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l /= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l >= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l <= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l > to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l < to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
-- rtl_synthesis off
-- synthesis translate_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable s : STRING(1 to value'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
-----------------------------------------------------------------------------
-- %%% Remove the following 3 functions. They are a duplicate needed for
-- testing
-----------------------------------------------------------------------------
-- purpose: Justify a string to the right
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_ostring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_hstring;
-- %%% End remove here
function to_string (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_string (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(pad
& slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)
& lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(pad&slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- purpose: find a dot in a string, return -1 if no dot (internal function)
function finddot (
arg : STRING)
return INTEGER is
alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto
begin
for i in xarg'reverse_range loop
if (xarg(i) = '.') then
return i-1;
end if;
end loop;
return -1;
end function finddot;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed is
variable result : ufixed (bstring'length-2 downto 0);
variable result_nodot : ufixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_ufixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return ufixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return sfixed is
variable result : sfixed (bstring'length-2 downto 0);
variable result_nodot : sfixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_sfixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return sfixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return sfixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_sfixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
-- synthesis translate_on
-- rtl_synthesis on
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdULogicVector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
function to_StdULogicVector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
end package body fixed_pkg;
| mit | ba96965a57453a2f8924744d930672d1 | 0.530077 | 4.029121 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/debounce_gen.vhd | 1 | 3,389 | -- $Id: debounce_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: debounce_gen - syn
-- Description: Generic signal debouncer
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 418 1.0.3 now numeric_std clean
-- 2007-12-26 105 1.0.2 add default for RESET
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-29 61 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end entity debounce_gen;
architecture syn of debounce_gen is
constant cntzero : slv(CWIDTH-1 downto 0) := (others=>'0');
constant datazero : slv(dWIDTH-1 downto 0) := (others=>'0');
type regs_type is record
cecnt : slv(CWIDTH-1 downto 0); -- clock interval counter
dref : slv(DWIDTH-1 downto 0); -- data reference
dchange : slv(DWIDTH-1 downto 0); -- data change flag
dout : slv(DWIDTH-1 downto 0); -- data output
end record regs_type;
constant regs_init : regs_type := (
cntzero,
datazero,
datazero,
datazero
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CEDIV<=2**CWIDTH report "assert(CEDIV<=2**CWIDTH)" severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS.cecnt <= cntzero;
R_REGS.dref <= DI;
R_REGS.dchange <= datazero;
R_REGS.dout <= DI;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, DI)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
for i in DI'range loop
if DI(i) /= r.dref(i) then
n.dchange(i) := '1';
end if;
end loop;
if CE_INT = '1' then
if unsigned(r.cecnt) = 0 then
n.cecnt := slv(to_unsigned(CEDIV-1,CWIDTH));
n.dref := DI;
n.dchange := datazero;
for i in DI'range loop
if r.dchange(i) = '0' then
n.dout(i) := r.dref(i);
end if;
end loop;
else
n.cecnt := slv(unsigned(r.cecnt) - 1);
end if;
end if;
N_REGS <= n;
DO <= r.dout;
end process proc_next;
end syn;
| gpl-3.0 | e4db3aca6bfdf2970ae078f18a618740 | 0.544999 | 3.479466 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/arty/sys_conf.vhd | 1 | 2,006 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_arty (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
| gpl-3.0 | 2af2ccad5859fcfc7b2495b38b39ee77 | 0.616152 | 3.694291 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys4d/sramif_mig_nexys4d.vhd | 1 | 7,391 | -- $Id: sramif_mig_nexys4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sramif_mig_nexys4d - syn
-- Description: SRAM to DDR via MIG for nexys4d
--
-- Dependencies: bplib/mig/sramif2migui_core
-- cdclib/cdc_pulse
-- cdclib/cdc_value
-- migui_nexys4d (generated core)
-- Test bench: tb_tst_sram_nexys4d
-- Target Devices: nexys4 DDRboard
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-02 1101 1.0.1 Initial version
-- 2018-12-30 1099 1.0 First draft (cloned from arty)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.cdclib.all;
use work.miglib.all;
use work.miglib_nexys4d.all;
entity sramif_mig_nexys4d is -- SRAM to DDR via MIG for nexyx4d
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- xadc die temp for mig core
MONI : out sramif2migui_moni_type;-- monitor signals
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end sramif_mig_nexys4d;
architecture syn of sramif_mig_nexys4d is
signal MIG_BUSY : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_EN : slbit := '0';
signal APP_CMD : slv3 := (others=>'0');
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_WDF_RDY : slbit := '0';
signal APP_WDF_WREN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal UI_CLK_SYNC_RST : slbit := '0';
signal INIT_CALIB_COMPLETE : slbit := '0';
signal SYS_RST : slbit := '0';
signal SYS_RST_BUSY : slbit := '0';
signal CLKMUI : slbit := '0';
signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI
begin
SR2MIG: sramif2migui_core -- SRAM to MIG iface -----------------
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => MIG_BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
MONI => MONI,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END
);
CDC_SYSRST: cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => true)
port map (
CLKM => CLK,
RESET => '0',
CLKS => CLKMIG,
PIN => RESET,
BUSY => SYS_RST_BUSY,
POUT => SYS_RST
);
CDC_TEMP: cdc_value
generic map (
DWIDTH => TEMP'length)
port map (
CLKI => CLK,
CLKO => CLKMUI,
DI => TEMP,
DO => TEMP_MUI,
UPDT => open
);
MIG_CTL: migui_nexys4d
port map (
DDR2_DQ => DDR2_DQ,
DDR2_DQS_P => DDR2_DQS_P,
DDR2_DQS_N => DDR2_DQS_N,
DDR2_ADDR => DDR2_ADDR,
DDR2_BA => DDR2_BA,
DDR2_RAS_N => DDR2_RAS_N,
DDR2_CAS_N => DDR2_CAS_N,
DDR2_WE_N => DDR2_WE_N,
DDR2_CK_P => DDR2_CK_P,
DDR2_CK_N => DDR2_CK_N,
DDR2_CKE => DDR2_CKE,
DDR2_CS_N => DDR2_CS_N,
DDR2_DM => DDR2_DM,
DDR2_ODT => DDR2_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => '0',
APP_REF_REQ => '0',
APP_ZQ_REQ => '0',
APP_SR_ACTIVE => open,
APP_REF_ACK => open,
APP_ZQ_ACK => open,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => TEMP_MUI,
SYS_RST => SYS_RST
);
BUSY <= MIG_BUSY or SYS_RST_BUSY;
end syn;
| gpl-3.0 | bdb0f44920d81940c9ef6340dc9ec6c1 | 0.467055 | 3.336795 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rb_sres_or_3.vhd | 1 | 2,252 | -- $Id: rb_sres_or_3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_3 - syn
-- Description: rbus result or, 3 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_3;
architecture syn of rb_sres_or_3 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack or
RB_SRES_3.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy or
RB_SRES_3.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err or
RB_SRES_3.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout or
RB_SRES_3.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => RB_SRES_3,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
| gpl-3.0 | e011980c09dc3b310336325303f74718 | 0.492895 | 3.114799 | false | false | false | false |
wfjm/w11 | rtl/w11a/pdp11_gr.vhd | 1 | 5,186 | -- $Id: pdp11_gr.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_gr - syn
-- Description: pdp11: general registers
--
-- Dependencies: memlib/ram_1swar_1ar_gen
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.0.3 rename _gpr -> _gr
-- 2019-08-17 1203 1.0.2 fix for ghdl V0.36 -Whide warnings
-- 2011-11-18 427 1.0.4 now numeric_std clean
-- 2008-08-22 161 1.0.3 rename ubf_ -> ibf_; use iblib
-- 2007-12-30 108 1.0.2 use ubf_byte[01]
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_gr is -- general registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
ASRC : in slv3; -- source register number
ADST : in slv3; -- destination register number
MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
RSET : in slbit; -- register set
WE : in slbit; -- write enable
BYTOP : in slbit; -- byte operation (write low byte only)
PCINC : in slbit; -- increment PC
DSRC : out slv16; -- source register data
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end pdp11_gr;
architecture syn of pdp11_gr is
-- --------------------------------------
-- the register map determines the internal register file storage address
-- of a register. The mapping is
-- ADDR RNUM SET MODE
-- 0000 000 0 -- R0 set 0
-- 0001 001 0 -- R1 set 0
-- 0010 010 0 -- R2 set 0
-- 0011 011 0 -- R3 set 0
-- 0100 100 0 -- R4 set 0
-- 0101 101 0 -- R5 set 0
-- 0110 110 - 00 SP kernel mode
-- 0111 110 - 01 SP supervisor mode
-- 1000 000 1 -- R0 set 1
-- 1001 001 1 -- R1 set 1
-- 1010 010 1 -- R2 set 1
-- 1011 011 1 -- R3 set 1
-- 1100 100 1 -- R4 set 1
-- 1101 101 1 -- R5 set 1
-- 1110 111 - -- PC
-- 1111 110 - 11 SP user mode
procedure do_regmap (
signal PRNUM : in slv3; -- register number
signal PMODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
signal PRSET : in slbit; -- register set
signal PADDR : out slv4 -- internal address in regfile
) is
begin
if PRNUM = c_gr_pc then
PADDR <= "1110";
elsif PRNUM = c_gr_sp then
PADDR <= PMODE(1) & "11" & PMODE(0);
else
PADDR <= PRSET & PRNUM;
end if;
end procedure do_regmap;
-- --------------------------------------
signal MASRC : slv4 := (others=>'0'); -- mapped source register address
signal MADST : slv4 := (others=>'0'); -- mapped destination register address
signal WE1 : slbit := '0'; -- write enable high byte
signal MEMSRC : slv16 := (others=>'0');-- source reg data from memory
signal MEMDST : slv16 := (others=>'0');-- destination reg data from memory
signal R_PC : slv16 := (others=>'0'); -- PC register
begin
do_regmap(PRNUM => ASRC, PMODE => MODE, PRSET => RSET, PADDR => MASRC);
do_regmap(PRNUM => ADST, PMODE => MODE, PRSET => RSET, PADDR => MADST);
WE1 <= WE and not BYTOP;
GR_LOW : ram_1swar_1ar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => WE,
ADDRA => MADST,
ADDRB => MASRC,
DI => DIN(ibf_byte0),
DOA => MEMDST(ibf_byte0),
DOB => MEMSRC(ibf_byte0));
GR_HIGH : ram_1swar_1ar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => WE1,
ADDRA => MADST,
ADDRB => MASRC,
DI => DIN(ibf_byte1),
DOA => MEMDST(ibf_byte1),
DOB => MEMSRC(ibf_byte1));
proc_pc : process (CLK)
alias R_PC15 : slv15 is R_PC(15 downto 1); -- upper 15 bit of PC
begin
if rising_edge(CLK) then
if WE='1' and ADST=c_gr_pc then
R_PC(ibf_byte0) <= DIN(ibf_byte0);
if BYTOP = '0' then
R_PC(ibf_byte1) <= DIN(ibf_byte1);
end if;
elsif PCINC = '1' then
R_PC15 <= slv(unsigned(R_PC15) + 1);
end if;
end if;
end process proc_pc;
DSRC <= R_PC when ASRC=c_gr_pc else MEMSRC;
DDST <= R_PC when ADST=c_gr_pc else MEMDST;
PC <= R_PC;
end syn;
| gpl-3.0 | 7a17bf0c77ac4a94f3355dc0254ae2b8 | 0.502507 | 3.347966 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_sram/nexys4/sys_conf.vhd | 1 | 2,494 | -- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_n4 (for synthesis)
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-16 788 1.2 use cram_*delay functions to determine delays
-- 2016-06-18 775 1.1.1 use PLL for clkser_gentype
-- 2016-03-29 756 1.1 use serport_2clock2 -> define clkser
-- 2013-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
constant sys_conf_memctl_read0delay : positive :=
cram_read0delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_read1delay : positive :=
cram_read1delay(sys_conf_clksys_mhz);
constant sys_conf_memctl_writedelay : positive :=
cram_writedelay(sys_conf_clksys_mhz);
end package sys_conf;
| gpl-3.0 | 18e2bb852920b5354d4631fd50c5d00a | 0.631917 | 3.502809 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/pb_Devices.pkg.vhdl | 1 | 34,368 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and
-- functions associated to the L_PicoBlaze namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_TEXTIO.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
package pb_Devices is
-- ===========================================================================
-- PicoBlaze bus descriptions
-- ===========================================================================
constant C_PB_BUSSES : T_PB_BUS_VECTOR := (
0 => pb_CreateBus("Any", "Any", ""),
1 => pb_CreateBus("Intern", "Intern", "Any"),
2 => pb_CreateBus("Extern", "Extern", "Any")
);
-- ===========================================================================
-- PicoBlaze device descriptions
-- ===========================================================================
constant PB_DEV_RESET : T_PB_DEVICE;
constant PB_DEV_ROM : T_PB_DEVICE;
constant PB_DEV_INTERRUPT : T_PB_DEVICE;
constant PB_DEV_INTERRUPT8 : T_PB_DEVICE;
constant PB_DEV_INTERRUPT16 : T_PB_DEVICE;
constant PB_DEV_TIMER : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER8 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER16 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER24 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER32 : T_PB_DEVICE;
constant PB_DEV_ACCUMULATOR16 : T_PB_DEVICE;
constant PB_DEV_DIVIDER : T_PB_DEVICE;
constant PB_DEV_DIVIDER8 : T_PB_DEVICE;
constant PB_DEV_DIVIDER16 : T_PB_DEVICE;
constant PB_DEV_DIVIDER24 : T_PB_DEVICE;
constant PB_DEV_DIVIDER32 : T_PB_DEVICE;
-- constant PB_DEV_SCALER16 : T_PB_DEVICE;
-- constant PB_DEV_SCALER32 : T_PB_DEVICE;
constant PB_DEV_SCALER40 : T_PB_DEVICE;
constant PB_DEV_CONVERTER_BCD : T_PB_DEVICE;
constant PB_DEV_CONVERTER_BCD24 : T_PB_DEVICE;
constant PB_DEV_GPIO : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO8 : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO16 : T_PB_DEVICE;
constant PB_DEV_LCDISPLAY : T_PB_DEVICE;
constant PB_DEV_UART : T_PB_DEVICE;
-- constant PB_DEV_UARTSTREAM : T_PB_DEVICE;
constant PB_DEV_IICCONTROLLER : T_PB_DEVICE;
-- constant PB_DEV_MDIOCONTROLLER : T_PB_DEVICE;
constant PB_DEV_DRP : T_PB_DEVICE;
constant PB_DEV_FREQM : T_PB_DEVICE;
constant PB_DEV_BCDCOUNTER : T_PB_DEVICE;
end package;
package body pb_Devices is
-- ===========================================================================
-- PicoBlaze device descriptions
-- ===========================================================================
-- Reset Circuit
-- ---------------------------------------------------------------------------
constant PB_DEV_RESET_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Reset", "Reset", 8)
);
constant PB_DEV_RESET : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Reset Circuit",
DeviceShort => "Reset",
Registers => (
pb_CreateRegisterWK("Reset", 0, PB_DEV_RESET_FIELDS, "Reset", 0)),
RegisterFields => PB_DEV_RESET_FIELDS
);
-- Instruction ROM
-- ---------------------------------------------------------------------------
constant PB_DEV_ROM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("PageNumber", "PageNumber", 3)
);
constant PB_DEV_ROM : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Instruction ROM",
DeviceShort => "InstROM",
Registers => (
pb_CreateRegisterRWK("PageNumber", 0, PB_DEV_ROM_FIELDS, "PageNumber", 5)),
RegisterFields => PB_DEV_ROM_FIELDS
);
-- InterruptController
-- ---------------------------------------------------------------------------
constant PB_DEV_INTERRUPT8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 8) &
pb_CreateWriteOnlyField("Interrupt Disable", "IntDisable", 8) &
pb_CreateReadOnlyField("Interrupt Enable Mask", "IntMask", 8) &
pb_CreateReadOnlyField("Interrupt Source", "IntSource", 8)
);
constant PB_DEV_INTERRUPT16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 16) &
pb_CreateWriteOnlyField("Interrupt Disable", "IntDisable", 16) &
pb_CreateReadOnlyField("Interrupt Enable Mask", "IntMask", 16) &
pb_CreateReadOnlyField("Interrupt Source", "IntSource", 8)
);
constant PB_DEV_INTERRUPT8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Interrupt Controller (8 ports)",
DeviceShort => "IntC8",
Registers => (
pb_CreateRegisterWK("IntEnable0", 0, PB_DEV_INTERRUPT8_FIELDS, "IntEnable", 0) &
pb_CreateRegisterWK("IntDisable0", 1, PB_DEV_INTERRUPT8_FIELDS, "IntDisable", 0) &
pb_CreateRegisterRO("IntMask0", 0, PB_DEV_INTERRUPT8_FIELDS, "IntMask", 0) &
pb_CreateRegisterRO("IntSource", 1, PB_DEV_INTERRUPT8_FIELDS, "IntSource", 0)),
RegisterFields => PB_DEV_INTERRUPT8_FIELDS
);
constant PB_DEV_INTERRUPT16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Interrupt Controller (16 ports)",
DeviceShort => "IntC16",
Registers => (
pb_CreateRegisterWK("IntEnable0", 0, PB_DEV_INTERRUPT16_FIELDS, "IntEnable", 0) &
pb_CreateRegisterWK("IntEnable1", 1, PB_DEV_INTERRUPT16_FIELDS, "IntEnable", 8) &
pb_CreateRegisterWK("IntDisable0", 2, PB_DEV_INTERRUPT16_FIELDS, "IntDisable", 0) &
pb_CreateRegisterWK("IntDisable1", 3, PB_DEV_INTERRUPT16_FIELDS, "IntDisable", 8) &
pb_CreateRegisterRO("IntMask0", 0, PB_DEV_INTERRUPT16_FIELDS, "IntMask", 0) &
pb_CreateRegisterRO("IntMask1", 1, PB_DEV_INTERRUPT16_FIELDS, "IntMask", 8) &
pb_CreateRegisterRO("IntSource", 2, PB_DEV_INTERRUPT16_FIELDS, "IntSource", 0)),
RegisterFields => PB_DEV_INTERRUPT16_FIELDS
);
-- Timer
-- ---------------------------------------------------------------------------
constant PB_DEV_TIMER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Control", "Control", 8) &
pb_CreateWriteOnlyField("Max Value", "MaxValue", 16) &
pb_CreateReadOnlyField("Current Value", "CurValue", 16)
);
constant PB_DEV_TIMER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Timer",
DeviceShort => "Timer",
Registers => (
pb_CreateRegisterWK("Control", 0, PB_DEV_TIMER_FIELDS, "Control", 0) &
pb_CreateRegisterWO("MaxValue0", 2, PB_DEV_TIMER_FIELDS, "MaxValue", 0) &
pb_CreateRegisterWO("MaxValue1", 3, PB_DEV_TIMER_FIELDS, "MaxValue", 8) &
pb_CreateRegisterRO("CurValue0", 2, PB_DEV_TIMER_FIELDS, "CurValue", 0) &
pb_CreateRegisterRO("CurValue1", 3, PB_DEV_TIMER_FIELDS, "CurValue", 8)),
RegisterFields => PB_DEV_TIMER_FIELDS,
CreatesInterrupt => TRUE
);
-- Multiplier (8/16/24/32 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_MULTIPLIER8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 8) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 8) &
pb_CreateReadOnlyField("Result R", "Result", 16)
);
constant PB_DEV_MULTIPLIER16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateReadOnlyField("Result R", "Result", 32)
);
constant PB_DEV_MULTIPLIER24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 24) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 24) &
pb_CreateReadOnlyField("Result R", "Result", 48)
);
constant PB_DEV_MULTIPLIER32_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 32) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 32) &
pb_CreateReadOnlyField("Result R", "Result", 64)
);
constant PB_DEV_MULTIPLIER8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (8 bit)",
DeviceShort => "Mult8",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER8_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_MULTIPLIER8_FIELDS, "OperandB", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER8_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER8_FIELDS, "Result", 8)),
RegisterFields => PB_DEV_MULTIPLIER8_FIELDS
);
constant PB_DEV_MULTIPLIER16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (16 bit)",
DeviceShort => "Mult16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_MULTIPLIER16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_MULTIPLIER16_FIELDS, "OperandB", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER16_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER16_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER16_FIELDS, "Result", 24)),
RegisterFields => PB_DEV_MULTIPLIER16_FIELDS
);
constant PB_DEV_MULTIPLIER24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (24 bit)",
DeviceShort => "Mult24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandB0", 3, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 4, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 5, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER24_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER24_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_MULTIPLIER24_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Result5", 5, PB_DEV_MULTIPLIER24_FIELDS, "Result", 40)),
RegisterFields => PB_DEV_MULTIPLIER24_FIELDS
);
constant PB_DEV_MULTIPLIER32 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (32 bit)",
DeviceShort => "Mult32",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandB0", 4, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 5, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 6, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 16) &
pb_CreateRegisterWO("OperandB3", 7, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 24) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER32_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER32_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER32_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER32_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_MULTIPLIER32_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Result5", 5, PB_DEV_MULTIPLIER32_FIELDS, "Result", 40) &
pb_CreateRegisterRO("Result6", 6, PB_DEV_MULTIPLIER32_FIELDS, "Result", 48) &
pb_CreateRegisterRO("Result7", 7, PB_DEV_MULTIPLIER32_FIELDS, "Result", 56)),
RegisterFields => PB_DEV_MULTIPLIER32_FIELDS
);
-- Accumulator (16 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_ACCUMULATOR16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operation", "Operation", 8) &
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateWriteOnlyField("Operand C", "OperandC", 16) &
pb_CreateReadOnlyField("Result R", "Result", 16)
);
constant PB_DEV_ACCUMULATOR16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Accumulator (16 bit)",
DeviceShort => "Accu16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_ACCUMULATOR16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_ACCUMULATOR16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_ACCUMULATOR16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_ACCUMULATOR16_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandC0", 2, PB_DEV_ACCUMULATOR16_FIELDS, "OperandC", 0) &
pb_CreateRegisterWO("OperandC1", 3, PB_DEV_ACCUMULATOR16_FIELDS, "OperandC", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_ACCUMULATOR16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_ACCUMULATOR16_FIELDS, "Result", 8)),
RegisterFields => PB_DEV_ACCUMULATOR16_FIELDS
);
-- Divider (8/16/24/32 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_DIVIDER8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 8) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 8) &
pb_CreateReadOnlyField("Result R", "Result", 8) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateReadOnlyField("Result R", "Result", 16) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 24) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 24) &
pb_CreateReadOnlyField("Result R", "Result", 24) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER32_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 32) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 32) &
pb_CreateReadOnlyField("Result R", "Result", 32) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (8 bit)",
DeviceShort => "Div8",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER8_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_DIVIDER8_FIELDS, "OperandB", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER8_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Status", 3, PB_DEV_DIVIDER8_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER8_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (16 bit)",
DeviceShort => "Div16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_DIVIDER16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_DIVIDER16_FIELDS, "OperandB", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER16_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Status", 3, PB_DEV_DIVIDER16_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER16_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (24 bit)",
DeviceShort => "Div24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_DIVIDER24_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandB0", 3, PB_DEV_DIVIDER24_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 4, PB_DEV_DIVIDER24_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 5, PB_DEV_DIVIDER24_FIELDS, "OperandB", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_DIVIDER24_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Status", 5, PB_DEV_DIVIDER24_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER24_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER32 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (32 bit)",
DeviceShort => "Div32",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER32_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER32_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_DIVIDER32_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_DIVIDER32_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandB0", 4, PB_DEV_DIVIDER32_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 5, PB_DEV_DIVIDER32_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 6, PB_DEV_DIVIDER32_FIELDS, "OperandB", 16) &
pb_CreateRegisterWO("OperandB3", 7, PB_DEV_DIVIDER32_FIELDS, "OperandB", 24) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER32_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER32_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_DIVIDER32_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_DIVIDER32_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Status", 7, PB_DEV_DIVIDER32_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER32_FIELDS,
CreatesInterrupt => TRUE
);
-- Scaler (40 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_SCALER40_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 40) &
pb_CreateWriteOnlyField("Multiplicator", "Mult", 8) &
pb_CreateWriteOnlyField("Divisor", "Div", 8) &
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Result R", "Result", 40) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_SCALER40 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Scaler (40 bit)",
DeviceShort => "Scaler40",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_SCALER40_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_SCALER40_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_SCALER40_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_SCALER40_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandA4", 4, PB_DEV_SCALER40_FIELDS, "OperandA", 32) &
pb_CreateRegisterWO("Mult", 5, PB_DEV_SCALER40_FIELDS, "Mult", 0) &
pb_CreateRegisterWO("Div", 6, PB_DEV_SCALER40_FIELDS, "Div", 0) &
pb_CreateRegisterWO("Command", 7, PB_DEV_SCALER40_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_SCALER40_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_SCALER40_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_SCALER40_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_SCALER40_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_SCALER40_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Status", 7, PB_DEV_SCALER40_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_SCALER40_FIELDS,
CreatesInterrupt => TRUE
);
-- Converter Bin2BCD (24 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_CONVERTER_BCD24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand", "OperandA", 24) &
pb_CreateReadOnlyField("Result", "Result", 28) &
pb_CreateReadOnlyField("Status", "Status", 4)
);
constant PB_DEV_CONVERTER_BCD24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Converter Bin2BCD (24 bit)",
DeviceShort => "ConvBCD24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 16) &
-- pb_CreateRegisterRO("Result3", 3, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Status", 3, PB_DEV_CONVERTER_BCD24_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_CONVERTER_BCD24_FIELDS,
CreatesInterrupt => TRUE
);
-- General Purpose I/O
-- ---------------------------------------------------------------------------
constant PB_DEV_GPIO_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateRegisterField("GPIO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("GPIO DataIn", "DataIn", 8) &
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 8)
);
constant PB_DEV_GPIO : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "General Purpose I/O",
DeviceShort => "GPIO",
Registers => (
pb_CreateRegisterRWK("DataOut", 0, PB_DEV_GPIO_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_GPIO_FIELDS, "DataIn", 0) &
pb_CreateRegisterWO("IntEnable", 1, PB_DEV_GPIO_FIELDS, "IntEnable", 0)),
RegisterFields => PB_DEV_GPIO_FIELDS,
CreatesInterrupt => TRUE
);
-- Bit Banging I/O (8 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_BIT_BANGING_IO8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("BBIO Set", "Set", 8) &
pb_CreateWriteOnlyField("BBIO Clear", "Clear", 8) &
pb_CreateReadOnlyField("BBIO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("BBIO DataIn", "DataIn", 8)
);
constant PB_DEV_BIT_BANGING_IO8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Bit Banging I/O",
DeviceShort => "BBIO8",
Registers => (
pb_CreateRegisterWK("Set", 0, PB_DEV_BIT_BANGING_IO8_FIELDS, "Set", 0) &
pb_CreateRegisterWK("Clear", 1, PB_DEV_BIT_BANGING_IO8_FIELDS, "Clear", 0) &
pb_CreateRegisterRO("DataOut", 0, PB_DEV_BIT_BANGING_IO8_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_BIT_BANGING_IO8_FIELDS, "DataIn", 0)),
RegisterFields => PB_DEV_BIT_BANGING_IO8_FIELDS
);
-- Bit Banging I/O (16 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_BIT_BANGING_IO16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("BBIO Set", "Set", 16) &
pb_CreateWriteOnlyField("BBIO Clear", "Clear", 16) &
pb_CreateReadOnlyField("BBIO DataOut", "DataOut", 16) &
pb_CreateReadOnlyField("BBIO DataIn", "DataIn", 16)
);
constant PB_DEV_BIT_BANGING_IO16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Bit Banging I/O",
DeviceShort => "BBIO16",
Registers => (
pb_CreateRegisterWK("Set0", 0, PB_DEV_BIT_BANGING_IO16_FIELDS, "Set", 0) &
pb_CreateRegisterWK("Set1", 1, PB_DEV_BIT_BANGING_IO16_FIELDS, "Set", 8) &
pb_CreateRegisterWK("Clear0", 2, PB_DEV_BIT_BANGING_IO16_FIELDS, "Clear", 0) &
pb_CreateRegisterWK("Clear1", 3, PB_DEV_BIT_BANGING_IO16_FIELDS, "Clear", 8) &
pb_CreateRegisterRO("DataOut0", 0, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataOut1", 1, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataOut", 8) &
pb_CreateRegisterRO("DataIn0", 2, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataIn", 0) &
pb_CreateRegisterRO("DataIn1", 3, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataIn", 8)),
RegisterFields => PB_DEV_BIT_BANGING_IO16_FIELDS
);
-- LC-Display
-- ---------------------------------------------------------------------------
constant PB_DEV_LCDISPLAY_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateWriteOnlyField("Data", "Data", 8)
);
constant PB_DEV_LCDISPLAY : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "LC Display Controller",
DeviceShort => "LCD",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_LCDISPLAY_FIELDS, "Command", 0) &
pb_CreateRegisterWO("DataOut", 1, PB_DEV_LCDISPLAY_FIELDS, "Data", 0) &
pb_CreateRegisterKO("DataOut", 1, PB_DEV_LCDISPLAY_FIELDS, "Data", 0)),
RegisterFields => PB_DEV_LCDISPLAY_FIELDS
);
-- UART
-- ---------------------------------------------------------------------------
constant PB_DEV_UART_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateWriteOnlyField("FIFO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("FIFO DataIn", "DataIn", 8)
);
constant PB_DEV_UART : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "UART",
DeviceShort => "UART",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_UART_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_UART_FIELDS, "Status", 0) &
pb_CreateRegisterWO("DataOut", 1, PB_DEV_UART_FIELDS, "DataOut", 0) &
pb_CreateRegisterKO("DataOut", 1, PB_DEV_UART_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_UART_FIELDS, "DataIn", 0)),
RegisterFields => PB_DEV_UART_FIELDS,
CreatesInterrupt => TRUE
);
-- UARTStream
-- ---------------------------------------------------------------------------
constant PB_DEV_UARTSTREAM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Dummy", "Dummy", 8)
);
-- constant PB_DEV_UARTSTREAM : T_PB_DEVICE := pb_CreateDevice(
-- DeviceName => "UARTStream",
-- DeviceShort => "UARTStream",
-- Registers => ((
-- 0 => pb_CreateRegister("Dummy", 0, PB_DEV_UARTSTREAM_FIELDS, "Dummy", 0))
-- ),
-- RegisterFields => PB_DEV_UARTSTREAM_FIELDS,
-- CreatesInterrupt => TRUE
-- );
-- I2C Controller
-- ---------------------------------------------------------------------------
constant PB_DEV_IICCONTROLLER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateRegisterField("Device Address [7:1]", "DeviceAddress", 8) &
pb_CreateRegisterField("RX Length [3:0]", "RXLength", 8) &
pb_CreateWriteOnlyField("TX_FIFO", "TX_FIFO", 8) &
pb_CreateReadOnlyField("RX_FIFO", "RX_FIFO", 8)
);
constant PB_DEV_IICCONTROLLER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "I2C Controller",
DeviceShort => "IICCtrl",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_IICCONTROLLER_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_IICCONTROLLER_FIELDS, "Status", 0) &
pb_CreateRegisterRW("DeviceAddress", 1, PB_DEV_IICCONTROLLER_FIELDS, "DeviceAddress", 0) &
pb_CreateRegisterRW("Length", 2, PB_DEV_IICCONTROLLER_FIELDS, "RXLength", 0) &
pb_CreateRegisterWO("TX_FIFO", 3, PB_DEV_IICCONTROLLER_FIELDS, "TX_FIFO", 0) &
pb_CreateRegisterRO("RX_FIFO", 3, PB_DEV_IICCONTROLLER_FIELDS, "RX_FIFO", 0)),
RegisterFields => PB_DEV_IICCONTROLLER_FIELDS,
CreatesInterrupt => TRUE
);
-- MDIO Controller
-- ---------------------------------------------------------------------------
constant PB_DEV_MDIOCONTROLLER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Dummy", "Dummy", 8)
);
-- constant PB_DEV_MDIOCONTROLLER : T_PB_DEVICE := pb_CreateDevice(
-- DeviceName => "MDIO Controller",
-- DeviceShort => "MDIOCtrl",
-- Registers => ((
-- 0 => pb_CreateRegister("Dummy", 0, PB_DEV_MDIOCONTROLLER_FIELDS, "Dummy", 0))
-- ),
-- RegisterFields => PB_DEV_MDIOCONTROLLER_FIELDS,
-- CreatesInterrupt => FALSE
-- );
-- Dynamic Reconfiguration Port
-- ---------------------------------------------------------------------------
constant PB_DEV_DRP_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateRegisterField("Address", "Address", 8) &
pb_CreateRegisterField("Data", "Data", 16) &
pb_CreateWriteOnlyField("Mask Register Set", "MaskRegSet", 16) &
pb_CreateWriteOnlyField("Mask Register Clear", "MaskRegClr", 16)
);
constant PB_DEV_DRP : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "PicoBlaze to DRP Adapter",
DeviceShort => "DRP",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_DRP_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_DRP_FIELDS, "Status", 0) &
pb_CreateRegisterRW("Address", 1, PB_DEV_DRP_FIELDS, "Address", 0) &
pb_CreateRegisterRW("Data0", 2, PB_DEV_DRP_FIELDS, "Data", 0) &
pb_CreateRegisterRW("Data1", 3, PB_DEV_DRP_FIELDS, "Data", 0) &
pb_CreateRegisterWO("MaskRegSet0", 4, PB_DEV_DRP_FIELDS, "MaskRegSet", 0) &
pb_CreateRegisterWO("MaskRegSet1", 5, PB_DEV_DRP_FIELDS, "MaskRegSet", 0) &
pb_CreateRegisterWO("MaskRegClr0", 6, PB_DEV_DRP_FIELDS, "MaskRegClr", 0) &
pb_CreateRegisterWO("MaskRegClr1", 7, PB_DEV_DRP_FIELDS, "MaskRegClr", 0)),
RegisterFields => PB_DEV_DRP_FIELDS
);
-- Frequency Measurement
-- ---------------------------------------------------------------------------
constant PB_DEV_FREQM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Frequency Counter", "FreqCntValue", 24) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_FREQM : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "FrequencyMeasurement",
DeviceShort => "FreqM",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_FREQM_FIELDS, "Command", 0) &
pb_CreateRegisterRO("FreqCntValue0", 0, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("FreqCntValue1", 1, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("FreqCntValue2", 2, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("Status", 3, PB_DEV_FREQM_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_FREQM_FIELDS
);
-- BCD Counter
-- ---------------------------------------------------------------------------
constant PB_DEV_BCDCOUNTER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Value", "Value", 32)
);
constant PB_DEV_BCDCOUNTER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "BCD Counter",
DeviceShort => "BCDCnt",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_BCDCOUNTER_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Value0", 0, PB_DEV_BCDCOUNTER_FIELDS, "Value", 0) &
pb_CreateRegisterRO("Value1", 1, PB_DEV_BCDCOUNTER_FIELDS, "Value", 8) &
pb_CreateRegisterRO("Value2", 2, PB_DEV_BCDCOUNTER_FIELDS, "Value", 16) &
pb_CreateRegisterRO("Value3", 3, PB_DEV_BCDCOUNTER_FIELDS, "Value", 24)),
RegisterFields => PB_DEV_BCDCOUNTER_FIELDS
);
-- define aliases
constant PB_DEV_INTERRUPT : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_INTERRUPT16, "IntC");
constant PB_DEV_MULTIPLIER : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_MULTIPLIER32, "Mult");
constant PB_DEV_DIVIDER : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_DIVIDER32, "Div");
constant PB_DEV_CONVERTER_BCD : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_CONVERTER_BCD24, "ConvBCD");
constant PB_DEV_BIT_BANGING_IO : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_BIT_BANGING_IO8, "BBIO");
end package body;
| apache-2.0 | 40ce0d09cc9acbc75790321c1c57a376 | 0.614642 | 3.159114 | false | false | false | false |
wfjm/w11 | rtl/vlib/rbus/rb_sres_or_mon.vhd | 1 | 4,350 | -- $Id: rb_sres_or_mon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_mon - sim
-- Description: rbus result or monitor
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: viv 2014.4-2015.4; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-13 743 3.1 now with 6 inputs; add RB_SRES_OR_MON_FAIL marker
-- 2010-12-23 347 3.0 rename rritb_sres_or_mon->rb_sres_or_mon
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
-- 2010-06-26 309 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_mon is -- rbus result or monitor
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_5 : in rb_sres_type := rb_sres_init; -- rb_sres input 5
RB_SRES_6 : in rb_sres_type := rb_sres_init -- rb_sres input 6
);
end rb_sres_or_mon;
architecture sim of rb_sres_or_mon is
signal RB_SRES_OR_MON_FAIL : slbit := '0';
begin
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3, RB_SRES_4)
constant dzero : slv16 := (others=>'0');
variable oline : line;
variable nack : integer := 0;
variable nbusy : integer := 0;
variable nerr : integer := 0;
variable ndout : integer := 0;
begin
nack := 0;
nbusy := 0;
nerr := 0;
ndout := 0;
if RB_SRES_1.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_2.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_3.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_4.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_5.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_6.ack /= '0' then nack := nack + 1; end if;
if RB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_5.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_6.busy /= '0' then nbusy := nbusy + 1; end if;
if RB_SRES_1.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_2.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_3.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_4.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_5.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_6.err /= '0' then nerr := nerr + 1; end if;
if RB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_5.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_6.dout /= dzero then ndout := ndout + 1; end if;
RB_SRES_OR_MON_FAIL <= '0';
if now > 0 ns and (nack>1 or nbusy>1 or nerr>1 or ndout>1) then
RB_SRES_OR_MON_FAIL <= '1';
write(oline, now, right, 12);
if nack > 1 then
write(oline, string'(" #ack="));
write(oline, nack);
end if;
if nbusy > 1 then
write(oline, string'(" #busy="));
write(oline, nbusy);
end if;
if nerr > 1 then
write(oline, string'(" #err="));
write(oline, nerr);
end if;
if ndout > 1 then
write(oline, string'(" #dout="));
write(oline, ndout);
end if;
write(oline, string'(" FAIL in "));
write(oline, rb_sres_or_mon'path_name);
writeline(output, oline);
end if;
end process proc_comb;
end sim;
| gpl-3.0 | 80a3ea1f4c0f419f5f60b0c7d4525665 | 0.526437 | 2.957172 | false | false | false | false |
sjohann81/hf-risc | riscv/core_rv32i/datapath.vhd | 1 | 11,881 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity datapath is
port ( clock: in std_logic;
reset: in std_logic;
stall: in std_logic;
mwait: in std_logic;
irq_vector: in std_logic_vector(31 downto 0);
irq: in std_logic;
irq_ack: out std_logic;
exception: out std_logic;
inst_addr: out std_logic_vector(31 downto 0);
inst_in: in std_logic_vector(31 downto 0);
data_addr: out std_logic_vector(31 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
data_w: out std_logic_vector(3 downto 0);
data_b: out std_logic;
data_h: out std_logic;
data_access: out std_logic
);
end datapath;
architecture arch_datapath of datapath is
-- datapath signals
signal inst_in_s, data_in_s, pc, pc_last, pc_last2, pc_plus4, pc_next, result, branch, ext32b, ext32h, alu_src1, alu_src2: std_logic_vector(31 downto 0);
signal ext32: std_logic_vector(31 downto 12);
signal opcode, funct7: std_logic_vector(6 downto 0);
signal funct3: std_logic_vector(2 downto 0);
signal read_reg1, read_reg2, write_reg: std_logic_vector(4 downto 0);
signal rs1, rs2, rd: std_logic_vector(4 downto 0);
signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
signal imm_i, imm_s, imm_sb, imm_uj, branch_src1, branch_src2: std_logic_vector(31 downto 0);
signal imm_u: std_logic_vector(31 downto 12);
signal wreg, zero, less_than, branch_taken, jump_taken, stall_reg: std_logic;
signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
-- control signals
signal reg_write_ctl, alu_src1_ctl, sig_read_ctl, reg_to_mem, mem_to_reg, except: std_logic;
signal jump_ctl, mem_write_ctl, mem_read_ctl: std_logic_vector(1 downto 0);
signal alu_src2_ctl, branch_ctl: std_logic_vector(2 downto 0);
signal alu_op_ctl: std_logic_vector(3 downto 0);
signal rs1_r, rs2_r, rd_r: std_logic_vector(4 downto 0);
signal imm_i_r, imm_s_r, imm_sb_r, imm_uj_r: std_logic_vector(31 downto 0);
signal imm_u_r: std_logic_vector(31 downto 12);
signal reg_write_ctl_r, alu_src1_ctl_r, sig_read_ctl_r, reg_to_mem_r, mem_to_reg_r: std_logic;
signal jump_ctl_r, mem_write_ctl_r, mem_read_ctl_r: std_logic_vector(1 downto 0);
signal alu_src2_ctl_r, branch_ctl_r: std_logic_vector(2 downto 0);
signal alu_op_ctl_r: std_logic_vector(3 downto 0);
begin
--
-- FETCH STAGE
--
-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
-- program counter logic
process(clock, reset, reg_to_mem_r, mem_to_reg_r, stall, stall_reg)
begin
if reset = '1' then
pc <= (others => '0');
pc_last <= (others => '0');
pc_last2 <= (others => '0');
elsif clock'event and clock = '1' then
if stall = '0' then
pc <= pc_next;
pc_last <= pc;
pc_last2 <= pc_last;
end if;
end if;
end process;
pc_plus4 <= pc + 4;
pc_next <= irq_vector when (irq = '1' and irq_ack_s = '1') or except = '1' else
branch when branch_taken = '1' or jump_taken = '1' else
pc_last when data_access_s = '1' else
pc_plus4;
-- interrupt acknowledge logic
irq_ack_s <= '1' when irq = '1' and
bds = '0' and branch_taken = '0' and jump_taken = '0' and
reg_to_mem_r = '0' and mem_to_reg_r = '0' else '0';
irq_ack <= irq_ack_s_dly;
exception <= '1' when except = '1' else '0';
process(clock, reset, irq, irq_ack_s, mem_to_reg_r, stall, mwait)
begin
if reset = '1' then
irq_ack_s_dly <= '0';
bds <= '0';
data_access_s_dly <= '0';
stall_reg <= '0';
elsif clock'event and clock = '1' then
stall_reg <= stall;
if stall = '0' then
data_access_s_dly <= data_access_s;
if mwait = '0' then
irq_ack_s_dly <= irq_ack_s;
if branch_taken = '1' or jump_taken = '1' then
bds <= '1';
else
bds <= '0';
end if;
end if;
end if;
end if;
end process;
--
-- DECODE STAGE
--
-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and branches
-- pipeline bubble insertion on loads/stores, exceptions, branches and interrupts
inst_in_s <= x"00000000" when data_access_s = '1' or except = '1' or
branch_taken = '1' or jump_taken = '1' or bds = '1' or irq_ack_s = '1' else
inst_in(7 downto 0) & inst_in(15 downto 8) & inst_in(23 downto 16) & inst_in(31 downto 24);
-- instruction decode
opcode <= inst_in_s(6 downto 0);
funct3 <= inst_in_s(14 downto 12);
funct7 <= inst_in_s(31 downto 25);
rd <= inst_in_s(11 downto 7);
rs1 <= inst_in_s(19 downto 15);
rs2 <= inst_in_s(24 downto 20);
imm_i <= ext32(31 downto 12) & inst_in_s(31 downto 20);
imm_s <= ext32(31 downto 12) & inst_in_s(31 downto 25) & inst_in_s(11 downto 7);
imm_sb <= ext32(31 downto 13) & inst_in_s(31) & inst_in_s(7) & inst_in_s(30 downto 25) & inst_in_s(11 downto 8) & '0';
imm_u <= inst_in_s(31 downto 12);
imm_uj <= ext32(31 downto 21) & inst_in_s(31) & inst_in_s(19 downto 12) & inst_in_s(20) & inst_in_s(30 downto 21) & '0';
ext32 <= (others => '1') when inst_in_s(31) = '1' else (others => '0');
-- control unit
control_unit: entity work.control
port map( opcode => opcode,
funct3 => funct3,
funct7 => funct7,
reg_write => reg_write_ctl,
alu_src1 => alu_src1_ctl,
alu_src2 => alu_src2_ctl,
alu_op => alu_op_ctl,
jump => jump_ctl,
branch => branch_ctl,
mem_write => mem_write_ctl,
mem_read => mem_read_ctl,
sig_read => sig_read_ctl
);
reg_to_mem <= '1' when mem_write_ctl /= "00" else '0';
mem_to_reg <= '1' when mem_read_ctl /= "00" else '0';
process(clock, reset, irq_ack_s, bds, stall, mwait)
begin
if reset = '1' then
rd_r <= (others => '0');
rs1_r <= (others => '0');
rs2_r <= (others => '0');
imm_i_r <= (others => '0');
imm_s_r <= (others => '0');
imm_sb_r <= (others => '0');
imm_u_r <= (others => '0');
imm_uj_r <= (others => '0');
reg_write_ctl_r <= '0';
alu_src1_ctl_r <= '0';
alu_src2_ctl_r <= (others => '0');
alu_op_ctl_r <= (others => '0');
jump_ctl_r <= (others => '0');
branch_ctl_r <= (others => '0');
mem_write_ctl_r <= (others => '0');
mem_read_ctl_r <= (others => '0');
sig_read_ctl_r <= '0';
reg_to_mem_r <= '0';
mem_to_reg_r <= '0';
elsif clock'event and clock = '1' then
if stall = '0' and mwait = '0' then
rd_r <= rd;
rs1_r <= rs1;
rs2_r <= rs2;
imm_i_r <= imm_i;
imm_s_r <= imm_s;
imm_sb_r <= imm_sb;
imm_u_r <= imm_u;
imm_uj_r <= imm_uj;
reg_write_ctl_r <= reg_write_ctl;
alu_src1_ctl_r <= alu_src1_ctl;
alu_src2_ctl_r <= alu_src2_ctl;
alu_op_ctl_r <= alu_op_ctl;
jump_ctl_r <= jump_ctl;
branch_ctl_r <= branch_ctl;
mem_write_ctl_r <= mem_write_ctl;
mem_read_ctl_r <= mem_read_ctl;
sig_read_ctl_r <= sig_read_ctl;
reg_to_mem_r <= reg_to_mem;
mem_to_reg_r <= mem_to_reg;
end if;
end if;
end process;
--
-- EXECUTE STAGE
--
-- 3rd stage (a) register file access (read)
-- the register file
register_bank: entity work.reg_bank
port map( clock => clock,
read_reg1 => read_reg1,
read_reg2 => read_reg2,
write_reg => write_reg,
wreg => wreg,
write_data => write_data,
read_data1 => read_data1,
read_data2 => read_data2
);
-- register file read/write selection and write enable
read_reg1 <= rs1_r;
read_reg2 <= rs2_r;
write_reg <= rd_r;
wreg <= (reg_write_ctl_r or mem_to_reg_r) and not mwait and not stall_reg;
-- 3rd stage (b) ALU operation
alu: entity work.alu
port map( op1 => alu_src1,
op2 => alu_src2,
alu_op => alu_op_ctl_r,
result => result,
zero => zero,
less_than => less_than
);
alu_src1 <= read_data1 when alu_src1_ctl_r = '0' else pc_last2;
alu_src2 <= imm_u_r & x"000" when alu_src2_ctl_r = "000" else
imm_i_r when alu_src2_ctl_r = "001" else
imm_s_r when alu_src2_ctl_r = "010" else
pc when alu_src2_ctl_r = "011" else
x"000000" & "000" & rs2_r when alu_src2_ctl_r = "100" else
read_data2;
branch_src1 <= read_data1 when jump_ctl_r = "11" else pc_last2;
branch_src2 <= imm_uj_r when jump_ctl_r = "10" else
imm_i_r when jump_ctl_r = "11" else imm_sb_r;
branch <= branch_src1 + branch_src2;
branch_taken <= '1' when (zero = '1' and branch_ctl_r = "001") or -- BEQ
(zero = '0' and branch_ctl_r = "010") or -- BNE
(less_than = '1' and branch_ctl_r = "011") or -- BLT
(less_than = '0' and branch_ctl_r = "100") or -- BGE
(less_than = '1' and branch_ctl_r = "101") or -- BLTU
(less_than = '0' and branch_ctl_r = "110") -- BGEU
else '0';
except <= '1' when branch_ctl_r = "111" else '0';
jump_taken <= '1' when jump_ctl_r /= "00" else '0';
inst_addr <= pc;
data_addr <= result;
data_b <= '1' when mem_read_ctl_r = "01" or mem_write_ctl_r = "01" else '0';
data_h <= '1' when mem_read_ctl_r = "10" or mem_write_ctl_r = "10" else '0';
data_access_s <= '1' when reg_to_mem_r = '1' or mem_to_reg_r = '1' else '0';
data_access <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
-- 3rd stage (c) data memory / write back operation, register file access (write)
-- memory access, store operations
process(mem_write_ctl_r, result, read_data2)
begin
case mem_write_ctl_r is
when "11" => -- store word
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);
data_w <= "1111";
when "01" => -- store byte
data_out <= read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0) & read_data2(7 downto 0);
case result(1 downto 0) is
when "11" => data_w <= "0001";
when "10" => data_w <= "0010";
when "01" => data_w <= "0100";
when others => data_w <= "1000";
end case;
when "10" => -- store half word
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(7 downto 0) & read_data2(15 downto 8);
case result(1) is
when '1' => data_w <= "0011";
when others => data_w <= "1100";
end case;
when others => -- WTF??
data_out <= read_data2(7 downto 0) & read_data2(15 downto 8) & read_data2(23 downto 16) & read_data2(31 downto 24);
data_w <= "0000";
end case;
end process;
-- memory access, load operations
process(mem_read_ctl_r, result, data_in)
begin
case mem_read_ctl_r is
when "01" => -- load byte
case result(1 downto 0) is
when "11" => data_in_s <= x"000000" & data_in(7 downto 0);
when "10" => data_in_s <= x"000000" & data_in(15 downto 8);
when "01" => data_in_s <= x"000000" & data_in(23 downto 16);
when others => data_in_s <= x"000000" & data_in(31 downto 24);
end case;
when "10" => -- load half word
case result(1) is
when '1' => data_in_s <= x"0000" & data_in(7 downto 0) & data_in(15 downto 8);
when others => data_in_s <= x"0000" & data_in(23 downto 16) & data_in(31 downto 24);
end case;
when others => -- load word
data_in_s <= data_in(7 downto 0) & data_in(15 downto 8) & data_in(23 downto 16) & data_in(31 downto 24);
end case;
end process;
-- write back
ext32b <= x"000000" & data_in_s(7 downto 0) when (data_in_s(7) = '0' or sig_read_ctl_r = '0') else x"ffffff" & data_in_s(7 downto 0);
ext32h <= x"0000" & data_in_s(15 downto 0) when (data_in_s(15) = '0' or sig_read_ctl_r = '0') else x"ffff" & data_in_s(15 downto 0);
write_data <= data_in_s when mem_read_ctl_r = "11" else
ext32b when mem_read_ctl_r = "01" else
ext32h when mem_read_ctl_r = "10" else
pc_last when jump_taken = '1' else result;
end arch_datapath;
| gpl-2.0 | ceb02380047d8e61f8012767d0a74154 | 0.588923 | 2.540304 | false | false | false | false |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_Scaler_Device.vhdl | 1 | 7,455 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Scaler (8/16/24/32/40 bit) Device for PicoBlaze
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_Scaler_Device is
generic (
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
BITS : POSITIVE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8
);
end entity;
architecture rtl of pb_Scaler_Device is
constant REG_RW_A0 : STD_LOGIC_VECTOR(2 downto 0) := "000";
constant REG_RW_A1 : STD_LOGIC_VECTOR(2 downto 0) := "001";
constant REG_RW_A2 : STD_LOGIC_VECTOR(2 downto 0) := "010";
constant REG_RW_A3 : STD_LOGIC_VECTOR(2 downto 0) := "011";
constant REG_RW_A4 : STD_LOGIC_VECTOR(2 downto 0) := "100";
constant REG_WO_MULT : STD_LOGIC_VECTOR(2 downto 0) := "101";
constant REG_WO_DIV : STD_LOGIC_VECTOR(2 downto 0) := "110";
constant REG_RO_STATUS : STD_LOGIC_VECTOR(2 downto 0) := "111";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
constant BYTES : POSITIVE := div_ceil(BITS, 8);
constant BITS_A : NATURAL := log2ceil(BYTES);
signal Reg_Scaler : STD_LOGIC_VECTOR(BITS - 1 downto 0) := x"0000000000";
signal Reg_Mult : T_SLV_8 := x"00";
signal Reg_Div : T_SLV_8 := x"00";
function getVALUES return T_POSVEC is
variable Result : T_POSVEC(0 to 255);
begin
Result(0) := 1;
for i in 1 to Result'high loop
Result(I) := I;
end loop;
return Result;
end function;
constant MULTS : T_POSVEC := getVALUES;
constant DIVS : T_POSVEC := getVALUES;
signal MultDiv_Start : STD_LOGIC;
signal MultDiv_Start_d : STD_LOGIC := '0';
signal MultDiv_Done : STD_LOGIC;
signal MultDiv_Done_d : STD_LOGIC := '0';
signal MultDiv_Done_re : STD_LOGIC;
signal MultDiv_Result : STD_LOGIC_VECTOR(BITS - 1 downto 0);
begin
assert (BITS = 40)
-- assert ((BITS = 8) or (BITS = 16) or (BITS = 24) or (BITS = 32) or (BITS = 40))
report "Multiplier size is not supported. Supported sizes: 8, 16, 24, 32, 40. BITS=" & INTEGER'image(BITS)
severity failure;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Reg_Scaler <= (others => '0');
Reg_Mult <= (others => '0');
Reg_Div <= (others => '0');
else
if (AdrDec_we = '1') then
case AdrDec_WriteAddress(2 downto 0) IS
when REG_WO_MULT => Reg_Mult <= AdrDec_Data;
when REG_WO_DIV => Reg_Div <= AdrDec_Data;
when REG_RW_A0 => Reg_Scaler(7 downto 0) <= AdrDec_Data;
when REG_RW_A1 => Reg_Scaler(15 downto 8) <= AdrDec_Data;
when REG_RW_A2 => Reg_Scaler(23 downto 16) <= AdrDec_Data;
when REG_RW_A3 => Reg_Scaler(31 downto 24) <= AdrDec_Data;
when REG_RW_A4 => Reg_Scaler(39 downto 32) <= AdrDec_Data;
when others => null;
end case;
elsif (MultDiv_Done_re = '1') then
Reg_Scaler <= MultDiv_Result;
end if;
end if;
end if;
end process;
MultDiv_Start <= AdrDec_we and to_sl(AdrDec_WriteAddress(2 downto 0) = REG_WO_DIV);
MultDiv_Start_d <= MultDiv_Start when rising_edge(Clock);
MultDiv_Done_d <= MultDiv_Done when rising_edge(Clock);
MultDiv_Done_re <= not MultDiv_Done_d and MultDiv_Done;
MultDiv : entity PoC.arith_scaler
generic map (
MULS => MULTS, -- The set of multipliers to choose from in scaling operations.
DIVS => DIVS -- The set of divisors to choose from in scaling operations.
)
port map (
clk => Clock,
rst => Reset,
start => MultDiv_Start_d,
arg => Reg_Scaler,
msel => Reg_Mult,
dsel => Reg_Div,
done => MultDiv_Done,
res => MultDiv_Result
);
process(AdrDec_re, AdrDec_ReadAddress, Reg_Scaler, MultDiv_Done_d)
variable Reg_Scaler_slvv : T_SLVV_8(4 downto 0);
begin
Reg_Scaler_slvv := to_slvv_8(Reg_Scaler);
DataOut <= Reg_Scaler_slvv(to_index(AdrDec_ReadAddress(2 downto 0), Reg_Scaler_slvv'length - 1));
if (AdrDec_ReadAddress(2 downto 0) = REG_RO_STATUS) then
DataOut <= "0000000" & MultDiv_Done_d;
end if;
end process;
Interrupt <= MultDiv_Done_re;
Message <= x"00";
end;
| apache-2.0 | cba3bf5b939c73769ef3de68ff5c8e4d | 0.548223 | 3.111436 | false | false | false | false |
wfjm/w11 | rtl/bplib/arty/tb/arty_dram_dummy.vhd | 1 | 3,494 | -- $Id: arty_dram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: arty_dram_dummy - syn
-- Description: arty target (base; serport loopback, dram project)
--
-- Dependencies: -
-- To test: tb_arty_dram
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-28 1063 1.0 Initial version (derived from arty_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity arty_dram_dummy is -- ARTY dummy (base+dram)
-- implements arty_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end arty_dram_dummy;
architecture syn of arty_dram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0
O_RGBLED1 <= (others=>'0');
O_RGBLED2 <= (others=>'0');
O_RGBLED3 <= (others=>'0');
DDR3_DQ <= (others=>'Z');
DDR3_DQS_P <= (others=>'Z');
DDR3_DQS_N <= (others=>'Z');
DDR3_ADDR <= (others=>'0');
DDR3_BA <= (others=>'0');
DDR3_RAS_N <= '1';
DDR3_CAS_N <= '1';
DDR3_WE_N <= '1';
DDR3_RESET_N <= '1';
DDR3_CK_P <= (others=>'0');
DDR3_CK_N <= (others=>'1');
DDR3_CKE <= (others=>'0');
DDR3_CS_N <= (others=>'1');
DDR3_DM <= (others=>'0');
DDR3_ODT <= (others=>'0');
end syn;
| gpl-3.0 | 3d00c150d8e09d66593a5a9fed9512bc | 0.471952 | 3.302457 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd | 1 | 15,815 | -- $Id: sys_w11a_br_arty.vhd 1211 2021-08-28 11:20:34Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_br_arty - syn
-- Description: w11a test design for arty
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- w11a/pdp11_bram_memctl
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_arty
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x4mux
-- bplib/sysmon/sysmonx_rbus_arty
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_br_arty
--
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.3; ghdl 0.33-0.35
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-05-19 1150 2017.2 xc7a35t-1 2829 6226 273 48.0 8150 +dz11
-- 2019-02-02 1108 2018.3 xc7a35t-1 2571 5781 170 47.5 1780
-- 2019-02-02 1108 2017.2 xc7a35t-1 2560 5496 170 47.5 1722
-- 2018-10-13 1055 2017.2 xc7a35t-1 2560 5499 170 47.5 1699 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a35t-1 2337 5188 138 47.5 1611 +KW11P
-- 2018-08-11 1038 2018.2 xc7a35t-1 2283 5190 138 47.5 1602
-- 2018-08-11 1038 2018.1 xc7a35t-1 2283 5193 138 47.5 1616
-- 2018-08-11 1038 2017.4 xc7a35t-1 2278 5130 138 47.5 1541
-- 2018-08-11 1038 2017.2 xc7a35t-1 2275 5104 138 47.5 1581
-- 2018-08-11 1038 2017.1 xc7a35t-1 2275 5104 138 47.5 1581
-- 2017-04-16 881 2016.4 xc7a35t-1 2275 5104 138 47.5 1611 +DEUNA
-- 2017-01-29 846 2016.4 xc7a35t-1 2225 5100 138 47.5 1555 +int24
-- 2016-05-26 768 2016.1 xc7a35t-1 2226 5080 138 47.5 1569 fsm+dsm=0
-- 2016-03-29 756 2015.4 xc7a35t-1 2106 4428 138 48.5 1397 serport2
-- 2016-03-27 753 2015.4 xc7a35t-1 1995 4298 138 48.5 1349 meminf
-- 2016-03-13 742 2015.4 xc7a35t-1 1996 4309 162 48.5 1333 +XADC
-- 2016-02-27 737 2015.4 xc7a35t-1 1952 4246 162 48.5 1316
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.4 use s7_cmt_1ce1ce
-- 2018-10-13 1055 1.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-04-02 758 1.2.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 1.2 use serport_2clock2
-- 2016-03-19 748 1.1.2 define rlink SYSID
-- 2016-03-13 742 1.1.1 add sysmon_rbus
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-02-27 736 1.0 Initial version (derived from sys_w11a_b3)
------------------------------------------------------------------------------
--
-- w11a test design for arty (using BRAM as memory)
-- w11a + rlink + serport
--
-- Usage of Arty switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows upper, RGB low nibble of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (3) kernel mode, non-wait, pri>0
-- (2) kernel mode, non-wait, pri=0
-- (1) supervisor mode
-- (0) user mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (3:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (3) MEM_ACT_W
-- (2) MEM_ACT_R
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR(11:08)
-- RGB_G DR( 7:04)
-- RGB_R DR( 3:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_br_arty is -- top level
-- implements arty_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4 -- arty pwrmon (pos)
);
end sys_w11a_br_arty;
architecture syn of sys_w11a_br_arty is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv4 := (others=>'0');
signal RGB_G : slv4 := (others=>'0');
signal RGB_B : slv4 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
BRAM_CTL: pdp11_bram_memctl -- memory controller -----------------
generic map (
MAWIDTH => sys_conf_memctl_mawidth,
NBLOCK => sys_conf_memctl_nblock)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_arty -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x4mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_RGBLED2 => O_RGBLED2,
O_RGBLED3 => O_RGBLED3
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_arty
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;
| gpl-3.0 | e3326bb0e4b0a2fe755af51222c76bfb | 0.491559 | 3.167434 | false | false | false | false |
wfjm/w11 | rtl/bplib/nexys3/tb/sys_conf_sim.vhd | 1 | 1,300 | -- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys3_fusp_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-25 433 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 4;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 75 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 75 MHz
constant sys_conf_clksys_gentype : string := "DCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
| gpl-3.0 | 4b72287c8be569ac21772bd2092aae61 | 0.593077 | 3.581267 | false | false | false | false |
wfjm/w11 | rtl/vlib/xlib/dcm_sfs_gsim.vhd | 1 | 1,759 | -- $Id: dcm_sfs_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: dcm_sfs - sim
-- Description: DCM for simple frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1065 1.1 use sfs_gsim_core
-- 2011-11-17 426 1.0.1 rename dcm_sp_sfs -> dcm_sfs
-- 2010-11-12 338 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sfs;
architecture sim of dcm_sfs is
begin
-- generate clock
SFS: sfs_gsim_core
generic map (
VCO_DIVIDE => 1,
VCO_MULTIPLY => CLKFX_MULTIPLY,
OUT_DIVIDE => CLKFX_DIVIDE)
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
end sim;
| gpl-3.0 | b59e78bc35cddc799ec53f66c50d11ab | 0.531552 | 3.61191 | false | false | false | false |
wfjm/w11 | rtl/sys_gen/tst_serloop/tst_serlooplib.vhd | 1 | 4,583 | -- $Id: tst_serlooplib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: tst_serlooplib
-- Description: Definitions for tst_serloop records and helpers
--
-- Dependencies: -
-- Tool versions: ise 13.1-14.7; viv 2014.7-2015.4; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-10-14 416 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.serportlib.all;
package tst_serlooplib is
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
type hio_cntl_type is record -- humanio controls
mode : slv2; -- mode (idle,(tx|tx)blast,loop)
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
end record hio_cntl_type;
constant hio_cntl_init : hio_cntl_type := (
c_mode_idle, -- mode
'0','0','0','0' -- enaxon,enaesc,enathrottle,enaftdi
);
type hio_stat_type is record -- humanio status
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
end record hio_stat_type;
constant hio_stat_init : hio_stat_type := (
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0') -- txokcnt
);
-- -------------------------------------
component tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end component;
component tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to display by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end component;
end package tst_serlooplib;
| gpl-3.0 | bdb4d8b48c6aa69e284322a0c5c1affe | 0.489636 | 4.31951 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibd_kw11l.vhd | 1 | 5,887 | -- $Id: ibd_kw11l.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_kw11l - syn
-- Description: ibus dev(loc): KW11-L (line clock)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 9 23 0 14 s 5.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-24 1138 1.2.1 add csr.ir; csr only loc writable;
-- csr.moni can be cleared, but not set by loc write
-- 2015-05-09 676 1.2 add CPUSUSP, freeze timer when cpu suspended
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset
-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list
-- 2008-05-09 144 1.0.3 use intreq flop, use EI_ACK
-- 2008-01-20 112 1.0.2 fix proc_next sensitivity list; use BRESET
-- 2008-01-06 111 1.0.1 Renamed to ibd_kw11l (RRI_REQ not used)
-- 2008-01-05 110 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_kw11l is -- ibus dev(loc): KW11-L (line clock)
-- fixed address: 177546
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
CPUSUSP : in slbit; -- cpu suspended
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibd_kw11l;
architecture syn of ibd_kw11l is
constant ibaddr_kw11l : slv16 := slv(to_unsigned(8#177546#,16));
constant lks_ibf_moni : integer := 7;
constant lks_ibf_ie : integer := 6;
constant lks_ibf_ir : integer := 5;
constant twidth : natural := 5;
constant tdivide : natural := 20;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
ie : slbit; -- interrupt enable
moni : slbit; -- monitor bit
intreq : slbit; -- interrupt request
tcnt : slv(twidth-1 downto 0); -- timer counter
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0', -- ie
'1', -- moni (set on reset !!)
'0', -- intreq
(others=>'0') -- tcnt
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.tcnt <= N_REGS.tcnt; -- don't clear msec tick counter
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, CE_MSEC, CPUSUSP, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then
n.ibsel := '1';
end if;
-- ibus output driver
if r.ibsel = '1' then
idout(lks_ibf_moni) := r.moni;
idout(lks_ibf_ie) := r.ie;
if IB_MREQ.racc = '1' then -- rri ---------------------
idout(lks_ibf_ir) := r.intreq;
end if;
end if;
-- ibus write transactions
if r.ibsel='1' and ibw0='1' then
if IB_MREQ.racc = '0' then -- cpu ---------------------
n.ie := IB_MREQ.din(lks_ibf_ie);
if IB_MREQ.din(lks_ibf_moni) = '0' then -- write 0 to moni
n.moni := '0'; -- clears moni
end if;
if IB_MREQ.din(lks_ibf_ie) = '0' then -- ie set 0
n.intreq := '0'; -- cancel interrupt
end if;
end if;
end if;
-- other state changes
if CE_MSEC='1' and CPUSUSP='0' then -- on msec and not suspended
n.tcnt := slv(unsigned(r.tcnt) + 1);
if unsigned(r.tcnt) = tdivide-1 then
n.tcnt := (others=>'0');
n.moni := '1';
if r.ie = '1' then
n.intreq := '1';
end if;
end if;
end if;
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
EI_REQ <= r.intreq;
end process proc_next;
end syn;
| gpl-3.0 | 54bff9cf4a2902b215db88b0cc4b6d5e | 0.490572 | 3.471108 | false | false | false | false |
wfjm/w11 | rtl/ibus/ibd_ibmon.vhd | 1 | 22,855 | -- $Id: ibd_ibmon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibd_ibmon - syn
-- Description: ibus dev: ibus monitor
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2014.4-2018.3; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-14 873 14.7 131013 xc6slx16-2 121 205 0 77 s 5.5
-- 2015-04-24 668 14.7 131013 xc6slx16-2 112 235 0 83 s 5.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-03-01 1116 2.1.1 track ack properly
-- 2019-02-23 1115 2.1 revised iface, busy 10->8, delay 14->16 bits
-- 2017-04-16 879 2.0 revised interface, add suspend and repeat collapse
-- 2017-03-04 858 1.0.2 BUGFIX: wrap set when go=0 due to wena=0
-- 2015-05-02 672 1.0.1 use natural for AWIDTH to work around a ghdl issue
-- 2015-04-24 668 1.0 Initial version (derived from rbd_rbmon)
------------------------------------------------------------------------------
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/f Control register
-- 08 rcolw r/w/- repeat collapse writes
-- 07 rcolr r/w/- repeat collapse reads
-- 06 wstop r/w/- stop on wrap
-- 05 conena r/w/- con enable
-- 04 remena r/w/- rem enable
-- 03 locena r/w/- loc enable
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start and latch all options
-- 110 sus suspend (noop if not started)
-- 111 res resume (noop if not started)
-- 001 stat r/w/- Status register
-- 15:13 bsize r/-/- buffer size (AWIDTH-9)
-- 02 wrap r/-/- line address wrapped (cleared on start)
-- 01 susp r/-/- suspended
-- 00 run r/-/- running (can be suspended)
-- 010 12:01 hilim r/w/- upper address limit, inclusive (def: 177776)
-- 011 12:01 lolim r/w/- lower address limit, inclusive (def: 160000)
-- 100 addr r/w/- Address register
-- *:02 laddr r/w/- line address
-- 01:00 waddr r/w/- word address
-- 101 data r/w/- Data register
--
-- data format:
-- word 3 15 : burst (2nd re/we in a aval sequence)
-- 14 : tout (busy in last re-we cycle)
-- 13 : nak (no ack in last non-busy cycle)
-- 12 : ack (ack seen)
-- 11 : busy (busy seen)
-- 10 : -- (reserved)
-- 09 : we (write cycle)
-- 08 : rmw (read-modify-write)
-- 07:00 : nbusy (number of busy cycles)
-- word 2 : ndly (delay to previous request)
-- word 1 : data
-- word 0 15 : be1 (byte enable low)
-- 14 : be0 (byte enable high)
-- 13 : racc (remote access)
-- 12:01 : addr (word address)
-- 0 : cacc (console access)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
-- to control the instantiation. ghdl checks even for not instantiated
-- entities the validity of generics, that's why natural needed here ....
entity ibd_ibmon is -- ibus dev: ibus monitor
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16)); -- base address
AWIDTH : natural := 9); -- buffer size
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus: request
IB_SRES : out ib_sres_type; -- ibus: response
IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor)
);
end entity ibd_ibmon;
architecture syn of ibd_ibmon is
constant ibaddr_cntl : slv3 := "000"; -- cntl address offset
constant ibaddr_stat : slv3 := "001"; -- stat address offset
constant ibaddr_hilim : slv3 := "010"; -- hilim address offset
constant ibaddr_lolim : slv3 := "011"; -- lolim address offset
constant ibaddr_addr : slv3 := "100"; -- addr address offset
constant ibaddr_data : slv3 := "101"; -- data address offset
constant cntl_ibf_rcolw : integer := 8;
constant cntl_ibf_rcolr : integer := 7;
constant cntl_ibf_wstop : integer := 6;
constant cntl_ibf_conena : integer := 5;
constant cntl_ibf_remena : integer := 4;
constant cntl_ibf_locena : integer := 3;
subtype cntl_ibf_func is integer range 2 downto 0;
subtype stat_ibf_bsize is integer range 15 downto 13;
constant stat_ibf_wrap : integer := 2;
constant stat_ibf_susp : integer := 1;
constant stat_ibf_run : integer := 0;
subtype addr_ibf_laddr is integer range 2+AWIDTH-1 downto 2;
subtype addr_ibf_waddr is integer range 1 downto 0;
subtype iba_ibf_pref is integer range 15 downto 13;
subtype iba_ibf_addr is integer range 12 downto 1;
constant dat3_ibf_burst : integer := 15;
constant dat3_ibf_tout : integer := 14;
constant dat3_ibf_nak : integer := 13;
constant dat3_ibf_ack : integer := 12;
constant dat3_ibf_busy : integer := 11;
constant dat3_ibf_we : integer := 9;
constant dat3_ibf_rmw : integer := 8;
subtype dat3_ibf_nbusy is integer range 7 downto 0;
constant dat0_ibf_be1 : integer := 15;
constant dat0_ibf_be0 : integer := 14;
constant dat0_ibf_racc : integer := 13;
subtype dat0_ibf_addr is integer range 12 downto 1;
constant dat0_ibf_cacc : integer := 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_sus : slv3 := "110"; -- func: suspend
constant func_res : slv3 := "111"; -- func: resume
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rcolw : slbit; -- rcolw flag (repeat collect writes)
rcolr : slbit; -- rcolr flag (repeat collect reads)
wstop : slbit; -- wstop flag (stop on wrap)
conena : slbit; -- conena flag (record console access)
remena : slbit; -- remena flag (record remote access)
locena : slbit; -- locena flag (record local access)
susp : slbit; -- suspended flag
go : slbit; -- go flag (actively running)
hilim : slv13_1; -- upper address limit
lolim : slv13_1; -- lower address limit
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv2; -- word address
addrsame: slbit; -- curr ib addr equal last ib addr
addrwind: slbit; -- curr ib addr in [lolim,hilim] window
aval_1 : slbit; -- last cycle aval
arm1r : slbit; -- 1st level arm for read
arm2r : slbit; -- 2nd level arm for read
arm1w : slbit; -- 1st level arm for write
arm2w : slbit; -- 2nd level arm for write
rcol : slbit; -- repeat collaps
ibtake_1: slbit; -- ib capture active in last cycle
ibaddr : slv13_1; -- ibus trace: addr
ibwe : slbit; -- ibus trace: we
ibrmw : slbit; -- ibus trace: rmw
ibbe0 : slbit; -- ibus trace: be0
ibbe1 : slbit; -- ibus trace: be1
ibcacc : slbit; -- ibus trace: cacc
ibracc : slbit; -- ibus trace: racc
iback : slbit; -- ibus trace: ack seen
ibbusy : slbit; -- ibus trace: busy seen
ibnak : slbit; -- ibus trace: nak detected
ibtout : slbit; -- ibus trace: tout detected
ibburst : slbit; -- ibus trace: burst detected
ibdata : slv16; -- ibus trace: data
ibnbusy : slv8; -- ibus number of busy cycles
ibndly : slv16; -- ibus delay to prev. access
end record regs_type;
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0', -- rcolw,rcolr,wstop
'1','1','1', -- conena,remena,locena
'0','1', -- susp,go
(others=>'1'), -- hilim (def: 177776)
(others=>'0'), -- lolim (def: 160000)
'0', -- wrap
laddrzero, -- laddr
"00", -- waddr
'0','0','0', -- addrsame,addrwind,aval_1
'0','0','0','0','0', -- arm1r,arm2r,arm1w,arm2w,rcol
'0', -- ibtake_1
(others=>'0'), -- ibaddr (startup: 160000)
'0','0','0','0','0','0', -- ibwe,ibrmw,ibbe0,ibbe1,ibcacc,ibracc
'0','0', -- iback,ibbusy
'0','0','0', -- ibnak,ibtout,ibburst
(others=>'0'), -- ibdata
(others=>'0'), -- ibnbusy
(others=>'0') -- ibndly
);
constant ibnbusylast : slv8 := (others=>'1');
constant ibndlylast : slv16 := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM0_DI : slv32 := (others=>'0');
signal BRAM1_DI : slv32 := (others=>'0');
signal BRAM0_DO : slv32 := (others=>'0');
signal BRAM1_DO : slv32 := (others=>'0');
signal BRAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH"
severity failure;
BRAM1 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => BRAM1_DI,
DO => BRAM1_DO
);
BRAM0 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => BRAM0_DI,
DO => BRAM0_DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, IB_SRES_SUM, BRAM0_DO, BRAM1_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iib_ack : slbit := '0';
variable iib_busy : slbit := '0';
variable iib_dout : slv16 := (others=>'0');
variable iibena : slbit := '0';
variable ibramen : slbit := '0'; -- BRAM enable
variable ibramwe : slbit := '0'; -- BRAN we
variable ibtake : slbit := '0';
variable laddr_inc : slbit := '0';
variable idat0 : slv16 := (others=>'0');
variable idat1 : slv16 := (others=>'0');
variable idat2 : slv16 := (others=>'0');
variable idat3 : slv16 := (others=>'0');
variable iaddrinc : slv(AWIDTH-1 downto 0) := (others=>'0');
variable iaddroff : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
iib_ack := '0';
iib_busy := '0';
iib_dout := (others=>'0');
iibena := IB_MREQ.re or IB_MREQ.we;
ibramen := '0';
ibramwe := '0';
laddr_inc := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto 4)=IB_ADDR(12 downto 4) then
n.ibsel := '1';
ibramen := '1'; -- ensures bram read before ibus read
end if;
-- ibus transactions (react only on rem access; invisible on loc side)
if r.ibsel = '1' and IB_MREQ.racc='1' then
iib_ack := iibena; -- ack all accesses
case IB_MREQ.addr(3 downto 1) is
when ibaddr_cntl => -- cntl ------------------
if IB_MREQ.we = '1' then
case IB_MREQ.din(cntl_ibf_func) is
when func_sto => -- func: stop ------------
n.go := '0';
n.susp := '0';
when func_sta => -- func: start -----------
n.rcolw := IB_MREQ.din(cntl_ibf_rcolw);
n.rcolr := IB_MREQ.din(cntl_ibf_rcolr);
n.wstop := IB_MREQ.din(cntl_ibf_wstop);
n.conena := IB_MREQ.din(cntl_ibf_conena);
n.remena := IB_MREQ.din(cntl_ibf_remena);
n.locena := IB_MREQ.din(cntl_ibf_locena);
n.go := '1';
n.susp := '0';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
when func_sus => -- func: susp ------------
if r.go = '1' then -- noop unless running
n.go := '0';
n.susp := r.go;
end if;
when func_res => -- func: resu ------------
n.go := r.susp;
n.susp := '0';
when others => null; -- <> --------------------
end case;
end if;
when ibaddr_stat => null; -- stat ------------------
when ibaddr_hilim => -- hilim -----------------
if IB_MREQ.we = '1' then
n.hilim := IB_MREQ.din(iba_ibf_addr);
end if;
when ibaddr_lolim => -- lolim -----------------
if IB_MREQ.we = '1' then
n.lolim := IB_MREQ.din(iba_ibf_addr);
end if;
when ibaddr_addr => -- addr ------------------
if IB_MREQ.we = '1' then
if r.go = '0' then -- if not active OK
n.laddr := IB_MREQ.din(addr_ibf_laddr);
n.waddr := IB_MREQ.din(addr_ibf_waddr);
else
iib_ack := '0'; -- otherwise error, do nak
end if;
end if;
when ibaddr_data => -- data ------------------
-- write to data is an error, do nak
if IB_MREQ.we='1' then
iib_ack := '0';
end if;
-- read to data always allowed, addr only incremented when not active
if IB_MREQ.re = '1' and r.go = '0' then
n.waddr := slv(unsigned(r.waddr) + 1);
if r.waddr = "11" then
laddr_inc := '1';
end if;
end if;
when others => -- <> --------------------
iib_ack := '0'; -- error, do nak
end case;
end if;
-- ibus output driver
if r.ibsel = '1' then
case IB_MREQ.addr(3 downto 1) is
when ibaddr_cntl => -- cntl ------------------
iib_dout(cntl_ibf_rcolw) := r.rcolw;
iib_dout(cntl_ibf_rcolr) := r.rcolr;
iib_dout(cntl_ibf_wstop) := r.wstop;
iib_dout(cntl_ibf_conena) := r.conena;
iib_dout(cntl_ibf_remena) := r.remena;
iib_dout(cntl_ibf_locena) := r.locena;
when ibaddr_stat => -- stat ------------------
iib_dout(stat_ibf_bsize) := slv(to_unsigned(AWIDTH-9,3));
iib_dout(stat_ibf_wrap) := r.wrap;
iib_dout(stat_ibf_susp) := r.susp; -- started and suspended
iib_dout(stat_ibf_run) := r.go or r.susp; -- started
when ibaddr_hilim => -- hilim -----------------
iib_dout(iba_ibf_pref) := (others=>'1');
iib_dout(iba_ibf_addr) := r.hilim;
when ibaddr_lolim => -- lolim -----------------
iib_dout(iba_ibf_pref) := (others=>'1');
iib_dout(iba_ibf_addr) := r.lolim;
when ibaddr_addr => -- addr ------------------
iib_dout(addr_ibf_laddr) := r.laddr;
iib_dout(addr_ibf_waddr) := r.waddr;
when ibaddr_data => -- data ------------------
case r.waddr is
when "11" => iib_dout := BRAM1_DO(31 downto 16);
when "10" => iib_dout := BRAM1_DO(15 downto 0);
when "01" => iib_dout := BRAM0_DO(31 downto 16);
when "00" => iib_dout := BRAM0_DO(15 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
-- ibus monitor
-- a ibus transaction are captured if the address is in alim window
-- and the access is not refering to ibd_ibmon itself
-- ibus address monitor
if IB_MREQ.aval='1' and r.aval_1='0' then
n.ibaddr := IB_MREQ.addr;
n.addrsame := '0';
if IB_MREQ.addr = r.ibaddr then
n.addrsame := '1';
end if;
n.addrwind := '0';
if unsigned(IB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(IB_MREQ.addr)<=unsigned(r.hilim) then
n.addrwind := '1';
end if;
end if;
n.aval_1 := IB_MREQ.aval;
-- ibus data monitor
if IB_MREQ.aval='1' and iibena='1' then -- aval and (re or we)
if IB_MREQ.we='1' then -- for write of din
n.ibdata := IB_MREQ.din;
else -- for read of dout
n.ibdata := IB_SRES_SUM.dout;
end if;
end if;
-- track state and decide on storage
ibtake := '0';
if IB_MREQ.aval='1' and iibena='1' then -- aval and (re or we)
if r.addrwind='1' and r.ibsel='0' then -- and in window and not self
if (r.locena='1' and IB_MREQ.cacc='0' and IB_MREQ.racc='0') or
(r.remena='1' and IB_MREQ.racc='1') or
(r.conena='1' and IB_MREQ.cacc='1') then
ibtake := '1';
end if;
end if;
end if;
if ibtake = '1' then -- if capture active
n.ibwe := IB_MREQ.we; -- keep track of some state
n.ibrmw := IB_MREQ.rmw;
n.ibbe0 := IB_MREQ.be0;
n.ibbe1 := IB_MREQ.be1;
n.ibcacc := IB_MREQ.cacc;
n.ibracc := IB_MREQ.racc;
if r.ibtake_1 = '0' then -- if initial cycle of a transaction
n.iback := IB_SRES_SUM.ack;
n.ibbusy := IB_SRES_SUM.busy;
n.ibnbusy := (others=>'0');
else -- if non-initial cycles
n.iback := r.iback or IB_SRES_SUM.ack;
if r.ibnbusy /= ibnbusylast then -- and count
n.ibnbusy := slv(unsigned(r.ibnbusy) + 1);
end if;
end if;
n.ibnak := not IB_SRES_SUM.ack;
n.ibtout := IB_SRES_SUM.busy;
if IB_SRES_SUM.busy = '0' then -- if last cycle of a transaction
n.arm1r := r.rcolr and IB_MREQ.re;
n.arm1w := r.rcolw and IB_MREQ.we;
n.arm2r := r.arm1r and r.addrsame and IB_MREQ.re;
n.arm2w := r.arm1w and r.addrsame and IB_MREQ.we;
n.rcol := ((r.arm2r and IB_MREQ.re) or
(r.arm2w and IB_MREQ.we)) and r.addrsame;
end if;
else -- if capture not active
if r.go='1' and r.ibtake_1='1' then -- active and transaction just ended
ibramen := '1';
ibramwe := '1';
laddr_inc := '1';
n.ibburst := '1'; -- assume burst
end if;
if r.ibtake_1 = '1' then -- ibus transaction just ended
n.ibndly := (others=>'0'); -- clear delay counter
else -- just idle
if r.ibndly /= ibndlylast then -- count cycles
n.ibndly := slv(unsigned(r.ibndly) + 1);
end if;
end if;
end if;
if IB_MREQ.aval = '0' then -- if aval gone
n.ibburst := '0'; -- clear burst flag
end if;
iaddrinc := (others=>'0');
iaddroff := (others=>'0');
iaddrinc(0) := not (r.rcol and r.go);
iaddroff(0) := (r.rcol and r.go);
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + unsigned(iaddrinc));
if r.go='1' and r.laddr=laddrlast then
n.wrap := '1';
if r.wstop = '1' then
n.go := '0';
end if;
end if;
end if;
idat3 := (others=>'0');
idat3(dat3_ibf_burst) := r.ibburst;
idat3(dat3_ibf_tout) := r.ibtout;
idat3(dat3_ibf_nak) := r.ibnak;
idat3(dat3_ibf_ack) := r.iback;
idat3(dat3_ibf_busy) := r.ibbusy;
idat3(dat3_ibf_we) := r.ibwe;
idat3(dat3_ibf_rmw) := r.ibrmw;
idat3(dat3_ibf_nbusy) := r.ibnbusy;
idat2 := r.ibndly;
idat1 := r.ibdata;
idat0(dat0_ibf_be1) := r.ibbe1;
idat0(dat0_ibf_be0) := r.ibbe0;
idat0(dat0_ibf_racc) := r.ibracc;
idat0(dat0_ibf_addr) := r.ibaddr;
idat0(dat0_ibf_cacc) := r.ibcacc;
n.ibtake_1 := ibtake;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_ADDR <= slv(unsigned(R_REGS.laddr) - unsigned(iaddroff));
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
IB_SRES.dout <= iib_dout;
IB_SRES.ack <= iib_ack;
IB_SRES.busy <= iib_busy;
end process proc_next;
end syn;
| gpl-3.0 | 5bb6521eadfce8fd1b9673959997eae6 | 0.471757 | 3.604321 | false | false | false | false |
wfjm/w11 | rtl/vlib/genlib/gray_cnt_gen.vhd | 1 | 1,959 | -- $Id: gray_cnt_gen.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_gen - syn
-- Description: Generic width Gray code counter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
entity gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end entity gray_cnt_gen;
architecture syn of gray_cnt_gen is
begin
assert DWIDTH>=4
report "assert(DWIDTH>=4): only 4 or more bit width supported"
severity failure;
GRAY_4: if DWIDTH=4 generate
begin
CNT : gray_cnt_4
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_4;
GRAY_5: if DWIDTH=5 generate
begin
CNT : gray_cnt_5
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_5;
GRAY_N: if DWIDTH>5 generate
begin
CNT : gray_cnt_n
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_N;
end syn;
| gpl-3.0 | 56248eb1524b4c27bb261fee9145d75f | 0.501787 | 3.696226 | false | false | false | false |
wfjm/w11 | rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd | 1 | 5,111 | -- $Id: rgbdrv_analog_rbus.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_analog_rbus - syn
-- Description: rgb analog from rbus
--
-- Dependencies: bpgen/rgbdrv_analog
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2015.4-2016.4; ghdl 0.31-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-05 907 1.1 add ACTLOW generic to invert output polarity
-- 2016-02-20 724 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 00 red r/w/- red channel
-- 01 green r/w/- green channel
-- 10 blue r/w/- blue channel
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity rgbdrv_analog_rbus is -- rgb analog from rbus
generic (
DWIDTH : positive := 8; -- dimmer width
ACTLOW : slbit := '0'; -- invert output polarity
RB_ADDR : slv16 := x"0000");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
O_RGBLED : out slv3 -- pad-o: rgb led
);
end rgbdrv_analog_rbus;
architecture syn of rgbdrv_analog_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
dimr : slv(DWIDTH-1 downto 0); -- dim red
dimg : slv(DWIDTH-1 downto 0); -- dim green
dimb : slv(DWIDTH-1 downto 0); -- dim blue
end record regs_type;
constant dimzero : slv(DWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
dimzero, -- dimr
dimzero, -- dimg
dimzero -- dimb
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
subtype dim_rbf is integer range DWIDTH-1 downto 0;
constant rbaddr_dimr: slv2 := "00"; -- 0 r/w/-
constant rbaddr_dimg: slv2 := "01"; -- 1 r/w/-
constant rbaddr_dimb: slv2 := "10"; -- 2 r/w/-
begin
assert DWIDTH<=16
report "assert (DWIDTH<=16)"
severity failure;
RGB : rgbdrv_analog
generic map (
DWIDTH => DWIDTH,
ACTLOW => ACTLOW)
port map (
CLK => CLK,
RESET => RESET,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
DIMR => R_REGS.dimr,
DIMG => R_REGS.dimg,
DIMB => R_REGS.dimb,
O_RGBLED => O_RGBLED
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_dimr =>
irb_dout(dim_rbf) := r.dimr;
if RB_MREQ.we = '1' then
n.dimr := RB_MREQ.din(dim_rbf);
end if;
when rbaddr_dimg =>
irb_dout(dim_rbf) := r.dimg;
if RB_MREQ.we = '1' then
n.dimg := RB_MREQ.din(dim_rbf);
end if;
when rbaddr_dimb =>
irb_dout(dim_rbf) := r.dimb;
if RB_MREQ.we = '1' then
n.dimb := RB_MREQ.din(dim_rbf);
end if;
when others =>
irb_ack := '0';
end case;
end if;
N_REGS <= n;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
| gpl-3.0 | b761155480cdc617159a9aaa436b75b0 | 0.490119 | 3.49112 | false | false | false | false |
sjohann81/hf-risc | mips/platform/rams/boot_ram.vhd | 1 | 22,558 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
RAMB16_S9_inst0 : RAMB16_S9
generic map (
INIT_00 => X"0202000c0200020c020200260800000000afafafafafaf3caf270010000c273c",
INIT_01 => X"3ca208262703008f8f8f8f8f8f8fa214a00226248280a01002242406a0162690",
INIT_02 => X"038f028f000c0010afaf2c272400038c3c10308c3c30038c3c0003ac3c14308c",
INIT_03 => X"1424000000040010000824042410000003001400001030001027038fa0028f27",
INIT_04 => X"00008f000c00040004afaf272408000300030014001400000000140000001000",
INIT_05 => X"240824240000afafafafafafaf2727038f0000008f3a000c0024040027038f00",
INIT_06 => X"24240c240c2a12001424142c2424142c24142e24108f10000c02102a00260c00",
INIT_07 => X"001480002732260c001083240cafaf272727038f8f8f8f8f8f028f00142a260c",
INIT_08 => X"08240c27038f8f001480002732260c001083240c27020014afaf2c2727038f8f",
INIT_09 => X"0c26243c001482260c26ac34243c8cac3cacafafafafafafafafafaf243c2702",
INIT_0A => X"3c001482260c26243c001482260c26243c3624242726263c0c3c3c243c148226",
INIT_0B => X"102c26000c000c240c001482260c26243c001482260c26243c001482260c2624",
INIT_0C => X"0c26243c3c3c08ae000c001482260c2624003c0c001482260c022400008c0200",
INIT_0D => X"3c0c001482260c02242608241032260c2610000c24120208a002000c00148226",
INIT_0E => X"0c02243c08001626a202301a000c001482260c2624003c0c001482260c262400",
INIT_0F => X"82260c2426020c3c240c020026002418000c001482260c2624003c0c00148226",
INIT_10 => X"0c001482260c02242608240c0016240c900c022624120012240c900c02240014",
INIT_11 => X"8f08260caf00083c0c001482260c02243c080002001482260c26243c3c00083c",
INIT_12 => X"0c26001482260c263c3c080016020c2416260c2400142c249226001482260c03",
INIT_13 => X"6c6864393531333762666a6e72767a00633834304c3c3c08001482260c24263c",
INIT_14 => X"00646d200a2062200a79696175200a30324a2d647420520a202025780a787470",
INIT_15 => X"0a202928670a740a6520002d2e612020740a7820720a746577200a00666d200a",
INIT_16 => X"000000000000000000000000000000000000000000000000000065610a006565",
INIT_17 => X"0100000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(31 downto 24),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(3));
RAMB16_S9_inst1 : RAMB16_S9
generic map (
INIT_00 => X"a242400060406000402060b500a0c080a0b1bfb0b2b3b415b5bd00000000bd1d",
INIT_01 => X"03820083bde000b0b1b2b3b4b5bf046045021042054460800262024062208362",
INIT_02 => X"e0b000bf0000a060bfb063bdc300e042024042620342e0420200e04402404262",
INIT_03 => X"e042a40500a00040050002a00340a400e004a0440560a300a0bde0b0a000bfbd",
INIT_04 => X"6210bf000000a00080bfb0bd030000e0e0e080c0056003e38500408500006003",
INIT_05 => X"150014130000b1bfb0b2b3b4b5bdbde0b0506210bf1000000510a104bde0b050",
INIT_06 => X"040400040042404055516063435160634360235154bf53000030404210520040",
INIT_07 => X"00804470a31010000080a40600bfb0a5bdbde0b0b1b2b3b4b500bf1040425200",
INIT_08 => X"000400bde0b0bf00804470a31010000080a40600a5008040bfb082bdbde0b0bf",
INIT_09 => X"001004100080041000106242041062400343b1b2b3b4b5b6b7bebfb00302bd00",
INIT_0A => X"1000800410001004100080041000100410f71213ded6b517001e160415800410",
INIT_0B => X"6043024000000004000080041000100410008004100010041000800410001004",
INIT_0C => X"00100410111000020000008024310031044011000080041000c004004042a202",
INIT_0D => X"11000080041000c00410000460039400944000000480e0006230000000800410",
INIT_0E => X"00c0041000001110023042200000008084940094044014000080243100310440",
INIT_0F => X"2431000431000011040082021402424000000080243100310440110000800410",
INIT_10 => X"000080041000c004310004000033040044003031043200330400440030110080",
INIT_11 => X"a2001000a2400011000080041000c00410000000008024310031041110400010",
INIT_12 => X"00040080243100311110000034200004301000040040428204110080243100c0",
INIT_13 => X"6d696561363232366165696d71757900643935313e4e10000080041000041010",
INIT_14 => X"007565205b006f425b006e6470555b31386120656c6249487c00302025797571",
INIT_15 => X"62203a68746c0a627362002d2e726266697729286561612072205b006965205b",
INIT_16 => X"0000000000000000000000000000000000000000000000000000782064007820",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(23 downto 16),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(2));
RAMB16_S9_inst2 : RAMB16_S9
generic map (
INIT_00 => X"18108800202828002090a00900a09890800000000000000000ff00ff0001ff50",
INIT_01 => X"e100000000001000000000000000ffff001800ff0000000020ff0000ffff0000",
INIT_02 => X"0000100000008000000000ffff000040e1ff0004e1000004e1000040e1ff0004",
INIT_03 => X"ffff38280000380028000000000010000020ff10280000100000000000100000",
INIT_04 => X"1018003000000080000000ff000000001000100028ff18382000001038380018",
INIT_05 => X"00000000908000000000000000ff000000101018000030002800ff2000000010",
INIT_06 => X"0000000000000088ffffff00ffffff00ffff00ff000000000080000081000020",
INIT_07 => X"00ff001000ff00008000000000000000ff0000000000000000100081ff00ff00",
INIT_08 => X"0100000000000000ff001000ff0000800000000000208000000000ff00000000",
INIT_09 => X"000a000000ff0000000a400100004040e1400000000000000000000001e1ff20",
INIT_0A => X"0000ff0000000a000000ff0000000a0000d000000a0a0b000000000000ff0000",
INIT_0B => X"ff00ff80000000000000ff0000000a000000ff0000000a000000ff0000000a00",
INIT_0C => X"000a000040000100000000ff0000000b0080000000ff00000080000000001010",
INIT_0D => X"000000ff000000800000010000030000ffff00000000a0010018800000ff0000",
INIT_0E => X"008000000100ff00008800ff000000ff0000000a0088000000ff0000000a0080",
INIT_0F => X"000000000a2001000000a0110011ffff000000ff0000000a0080000000ff0000",
INIT_10 => X"0000ff00000080000002000000ff0000ff011000000000000000ff01100000ff",
INIT_11 => X"00010000008002000000ff0000008000000100f800ff0000000a000040880100",
INIT_12 => X"000000ff0000000a00000100ff800000ff000000000000ff000000ff00000088",
INIT_13 => X"6e6a6662373331353964686c70747800656136320055000100ff000000000a00",
INIT_14 => X"006d6d5d64006f5d620061206c5d7539206e00726f6f534600003200307a7672",
INIT_15 => X"790000656865006f0079003e0079696f6e613a6873640064695d77006c6d5d66",
INIT_16 => X"0505050505080505050505050505050505050505050505050800292861002928",
INIT_17 => X"0002000605060505050505050505050505050505060507050805050505050505",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(15 downto 8),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(1));
RAMB16_S9_inst3 : RAMB16_S9
generic map (
INIT_00 => X"2123256725252594252525c41725252525182c141c20240028d000ff0021fc00",
INIT_01 => X"0301260230082514181c2024282cfff9012b01ff000000092bff2d17fff20123",
INIT_02 => X"0810251400062508141023e8fe00080003fd0100030108000300080003fd0200",
INIT_03 => X"f8ff2b4000092513407d201d01102b000840fb21420201250718081000251418",
INIT_04 => X"2623142571000d250c1410e8018300082508250342f942252300032b25250a40",
INIT_05 => X"08c70d0a2525182c141c202428d0180810212623140125712301f52318081021",
INIT_06 => X"08203f083f100925e8a9ea1a9fc9ee1abff10ad01a2c1c004b211f1000013f25",
INIT_07 => X"00f9002110ff013f2509100a53343010c8300814181c202428252c02e310ff3f",
INIT_08 => X"0b303f3808303400f9002110ff013f250910105310252514343010c838083034",
INIT_09 => X"3f384a0000fc00013f2000500a00000000101c2024282c3034383c18b203c025",
INIT_0A => X"0000fc00013f5c0a0000fc00013f440a009010081ca81c033f00000a00fc0001",
INIT_0B => X"cf36be254b004b0a3f00fc00013f940a0000fc00013f800a0000fc00013f6c0a",
INIT_0C => X"3fb80a000000500000b200fc00013f0c0a2500b200fc00013f250a0008002180",
INIT_0D => X"00b200fc00013f250a01a62a87ff014bfffb00472dac25ac0021254b00fc0001",
INIT_0E => X"3f250a005000fd010021ff7a00b200fc00013ffc0a2500b200fc00013fe80a25",
INIT_0F => X"00013f20f82504000a3f21001002ff5e00b200fc00013fe80a2500b200fc0001",
INIT_10 => X"b200fc00013f250a010d203f00f7203fff0421012035000b203fff04210100fc",
INIT_11 => X"10a6013f10252500b200fc00013f250a0050000900fc00013fe00a0000259d00",
INIT_12 => X"ef0100fc00013fd000005000a2253f7cf7013f2e00025fe0001000fc00013f25",
INIT_13 => X"6f6b6763383430343863676b6f73770066623733004c005000fc00013f20d800",
INIT_14 => X"00702020200074202c0072626f202c0032200020616f432d0000780038007773",
INIT_15 => X"74000078206e006f00740020002e6e726769006573640061742020006c202020",
INIT_16 => X"3c3c3c3c3c603c3c3c3c3c3c3c3c3c3c3c3c3c3c3c3c3c3cc0003a6874003a68",
INIT_17 => X"030000143c6c3c3c3c3c3c3c3c3c3c3c3c3c3c3cdc3c743c8c3c3c3c3c3c3c3c",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => data_read(7 downto 0),
DOP => open,
ADDR => address(12 downto 2),
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => enable,
SSR => ZERO(0),
WE => write_byte_enable(0));
end; --architecture logic
| gpl-2.0 | f0549dfae77fb31661bc36f6bbfc7c99 | 0.855351 | 4.466046 | false | false | false | false |
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