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Kalugy/Procesadorarquitectura | Segundoprocesador19oct/ALU.vhd | 1 | 3,102 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:19:49 10/04/2017
-- Design Name:
-- Module Name: ALU - ARQALU
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
c: in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0));
end ALU;
architecture ARQALU of ALU is
begin
process(OPER1,OPER2,ALUOP)
begin
case (ALUOP) is
when "000000" => -- add
ALURESULT <= OPER1 + OPER2;
when "000001" =>--AND
ALURESULT <= OPER1 and OPER2;
when "000010" =>--OR
ALURESULT <= OPER1 or OPER2;
when "000011" =>--xor
ALURESULT <= OPER1 xor OPER2;
when "000111" =>--xnor
ALURESULT <= OPER1 xnor OPER2;
when "000100"=>--Sub
ALURESULT <= OPER1 - OPER2;
when "000101"=>--and not
ALURESULT<=OPER1 and not OPER2;
when "000110"=>--nor
ALURESULT<= OPER1 or not OPER2;
when "010000"=>--addcc
ALURESULT <= OPER1 + OPER2;
when "010100"=>--subcc
ALURESULT <= OPER1 - OPER2;
when "010001" =>--andcc
ALURESULT<= OPER1 and OPER2;
when "010101" =>--andncc
ALURESULT<= OPER1 and not OPER2;
when "010010" => --orcc
ALURESULT <= OPER1 or OPER2;
when "010110" =>--orncc
ALURESULT <= OPER1 or not OPER2;
when "001000"=>--addx
ALURESULT <= OPER1 + OPER2 + c;
when "011000" =>--addxcc
ALURESULT <= OPER1 + OPER2 + c;
when "001100" => --subx
ALURESULT <= OPER1- OPER2 - c;
when "011100" => --subxcc
ALURESULT <= OPER1 - OPER2 - c;
when "010011" => --xorcc
ALURESULT <= OPER1 xor OPER2;
when "010111" => --xnorcc
ALURESULT <= OPER1 xor OPER2;
when "100101" => --sll
ALURESULT <= to_stdlogicvector(to_bitvector(OPER1) sll conv_integer(OPER2));
when "100110" => --srl
ALURESULT <= to_stdlogicvector(to_bitvector(OPER1) srl conv_integer(OPER2));
when "111100" => --save
ALURESULT <= OPER1 + OPER2;
when "111101" => --restore
ALURESULT <= OPER1 + OPER2;
when others => --nops
ALURESULT<= x"00000000";
end case;
end process;
end ARQALU;
| gpl-3.0 | a93379a3b580482545f8326abc6b0eb3 | 0.540941 | 3.778319 | false | false | false | false |
nickdesaulniers/Omicron | data_mem/data_mem.vhd | 1 | 5,199 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file data_mem.vhd when simulating
-- the core, data_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY data_mem IS
port (
clka: IN std_logic;
rsta: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(6 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END data_mem;
ARCHITECTURE data_mem_a OF data_mem IS
-- synthesis translate_off
component wrapped_data_mem
port (
clka: IN std_logic;
rsta: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(6 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_data_mem use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "data_mem.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3e",
c_write_depth_b => 128,
c_write_depth_a => 128,
c_has_rstb => 0,
c_has_rsta => 1,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 7,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 7,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 128,
c_read_depth_a => 128,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_data_mem
port map (
clka => clka,
rsta => rsta,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END data_mem_a;
| gpl-3.0 | d932014c70518771f7883ab74dea79d1 | 0.556261 | 3.638209 | false | false | false | false |
Kalugy/Procesadorarquitectura | Primerprocesador17octubre/RF.vhd | 1 | 1,376 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (31 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type;
begin
RAM(0)<= "00000000000000000000000000000000";
process (rst,rd,rs1,rs2,dwr,RAM)
begin
if rst = '1' then
RAM <= (others=>"00000000000000000000000000000000");
crs1 <="00000000000000000000000000000000";
crs2 <="00000000000000000000000000000000";
elsif rd /= "00000" then
RAM(conv_integer(rd)) <= dwr;
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
else
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
end if;
end process;
end Behavioral;
| gpl-3.0 | 17131d0601cf5e030aab8d7179c930fa | 0.522529 | 4.047059 | false | false | false | false |
hhuang25/uwaterloo_ece224 | Lab1Good/ece324_clock_divider.vhd | 2 | 1,578 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ece324_clock_divider is
port ( masterClk : in std_logic;
period : in std_logic_vector(3 downto 0);
clockHR : out std_logic;
clockLR : out std_logic
);
end ece324_clock_divider;
architecture Behavioral of ece324_clock_divider is
signal count1 : std_logic_vector(12 downto 0);
signal count2 : std_logic_vector(3 downto 0);
signal count3 : std_logic_vector(7 downto 0);
signal clk, clk1Hz, clkPeriod : std_logic;
begin
-- 1 HZ Clock
Clock1HZ: process(masterClk)
begin
if(masterClk'EVENT and masterClk = '1') then
if(count1 = "1111111001001") then
count1 <= "0000000000000";
else
count1 <= count1 + 1;
end if;
end if;
end process;
clk1Hz <= count1(12);
-- period based clock
ClockPeriod: process(masterClk)
begin
if(masterClk'EVENT and masterClk = '1') then
if(count2 = period) then
count2 <= "0000";
clkPeriod <= '1';
else
count2 <= count2 + 1;
clkPeriod <= '0';
end if;
end if;
end process;
-- clocked multiplexer
Mux: process(masterClk)
begin
if(masterClk'EVENT and masterClk = '1') then
if(period = "0000") then
clk <= clk1Hz;
else
clk <= clkPeriod;
end if;
end if;
end process;
-- 50% duty cycle outputs
ClockMain: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(count3 = "11111111") then
count3 <= "00000000";
else
count3 <= count3 + 1;
end if;
end if;
end process;
-- assign outputs
clockLR <= count3(7);
clockHR <= count3(1);
end Behavioral; | mit | aff562fadc115e87123eb809947e4a36 | 0.65526 | 2.848375 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd | 1 | 24,930 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_CH1 : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
-- Channel Control --
desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
sof_ftch_desc : in std_logic ;
desc2_flush : in std_logic ; --
ftch2_active : in std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch2_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_tlast : in std_logic ; --
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic ; --
m_axis_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch_tvalid_new : out std_logic ; --
m_axis_ftch_desc_available : out std_logic ;
m_axis2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis2_ftch_tvalid : out std_logic ; --
m_axis2_ftch_tready : in std_logic ; --
m_axis2_ftch_tlast : out std_logic ; --
m_axis2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis2_ftch_tvalid_new : out std_logic ; --
m_axis2_ftch_desc_available : out std_logic ;
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal ftch_tdata_new_64 : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
signal ftch_active_int : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0);
signal queue_wren, queue_rden : std_logic := '0';
signal queue_din : std_logic_vector (32 downto 0);
signal queue_dout : std_logic_vector (32 downto 0);
signal queue_empty, queue_full : std_logic := '0';
signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0';
signal sof_ftch_desc_del1 : std_logic := '0';
signal queue_sinit : std_logic := '0';
signal data_concat_mcdma_nxt : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
queue_sinit <= not m_axi_sg_aresetn;
ftch_active_int <= ftch_active or ftch2_active;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
ftch_tdata_new (96 downto 65) <= current_bd (31 downto 0);
ADDR641 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 <= data_concat_64 & current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate ADDR641;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
NEXT_BD_S2MM : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
data_concat_mcdma_nxt <= (others => '0');
elsif (ftch2_active = '1') then
data_concat_mcdma_nxt <= next_bd;
end if;
end if;
end process NEXT_BD_S2MM;
end generate NXT_BD_MCDMA;
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
current_bd <= (others => '0');
--
-- -- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then
current_bd <= ftch_cmnd_data((C_M_AXI_SG_ADDR_WIDTH-32)+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process WRITE_CURDESC_PROCESS;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch_active;
queue_rden <= not queue_empty
and m_axis_mm2s_cntrl_tready;
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NO_CONTROL_STREAM;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
ftch_tready <= (m_axis_ftch_tready and ftch_active) or
(m_axis2_ftch_tready and ftch2_active);
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active;
m_axis_ftch_desc_available <= data_concat_tlast and ftch_active;
REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate
begin
LATCH_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tvalid_new <= '0';
m_axis2_ftch_desc_available <= '0';
else
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
end if;
end if;
end process LATCH_PROCESS;
LATCH2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tdata_new <= (others => '0');
elsif (data_concat_valid = '1' and ftch2_active = '1') then
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end if;
end if;
end process LATCH2_PROCESS;
end generate REG_FOR_STS_CNTRL;
NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate
begin
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt;
end generate NO_REG_FOR_STS_CNTRL;
m_axis_mm2s_tready <= ftch_tready;
m_axis2_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
Q2_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then
ftch2_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch2_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch2_queue_empty <= '0';
end if;
end if;
end if;
end process Q2_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
ftch2_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc and ftch_active;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| mit | 95c285568294b99d217907bba99ae1e7 | 0.445608 | 4.176579 | false | false | false | false |
Kalugy/Procesadorarquitectura | Primerprocesador17octubre/firstrpart.vhd | 1 | 4,508 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:12 09/26/2017
-- Design Name:
-- Module Name: firstrpart - arqfirstrpart
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity firstrpart is
Port ( Resetext : in STD_LOGIC;
Clkinext : in STD_LOGIC;
Adressext : out STD_LOGIC_VECTOR (31 downto 0));
end firstrpart;
architecture arqfirstrpart of firstrpart is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT NPC
PORT(
inNPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outNPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT PC
PORT(
inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
Address : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
OUTSEU : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MUX32
PORT(
SEUIMM : in STD_LOGIC_VECTOR (31 downto 0);
CRS2 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : out STD_LOGIC_VECTOR (31 downto 0);
Instruction : in STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal aux1,aux2,aux3,aux4,aux6,aux7,aux8,aux9,aux10: std_logic_vector(31 downto 0);
signal aux5: std_logic_vector(5 downto 0);
begin
U0: NPC PORT MAP(
inNPC => aux1,
Reset => Resetext,
Clk => Clkinext,
outNPC => aux2
);
U1: PC PORT MAP(
inPC => aux2,
Reset => Resetext,
Clk => Clkinext,
outPC => aux3
);
U2: Sumador32bit PORT MAP(
Oper1 => aux3,
Result => aux1
);
U3: IM PORT MAP(
Address => aux3,
Reset => Resetext,
Instruction => aux4
);
U4: CU PORT MAP(
Instruction => aux4,
ALUOP => aux5
);
U5: SEU PORT MAP(
Instruction =>aux4,
OUTSEU =>aux6
);
U6: MUX32 PORT MAP(
SEUIMM => aux6,
CRS2 => aux7,
OPER2 => aux9,
Instruction => aux4
);
U7: ALU PORT MAP(
OPER1 => aux8,
OPER2 => aux9,
ALURESULT => aux10,
ALUOP => aux5
);
U8: RF PORT MAP(
rs1 => aux4(18 downto 14),
rs2 => aux4(4 downto 0),
rd => aux4(29 downto 25),
dwr => aux10,
rst => Resetext,
crs1 => aux8,
crs2 => aux7
);
Adressext<=aux10;
end arqfirstrpart;
| gpl-3.0 | b10a93b5e27cf1ba9b33e30716d4187c | 0.521517 | 3.698113 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_axi_dma_0_0/synth/triangle_intersect_axi_dma_0_0.vhd | 1 | 31,790 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1;
USE axi_dma_v7_1.axi_dma;
ENTITY triangle_intersect_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END triangle_intersect_axi_dma_0_0;
ARCHITECTURE triangle_intersect_axi_dma_0_0_arch OF triangle_intersect_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF triangle_intersect_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF triangle_intersect_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF triangle_intersect_axi_dma_0_0_arch : ARCHITECTURE IS "triangle_intersect_axi_dma_0_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF triangle_intersect_axi_dma_0_0_arch: ARCHITECTURE IS "triangle_intersect_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=1,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=23,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 1,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END triangle_intersect_axi_dma_0_0_arch;
| mit | 7942ed2b1b20632ae1dfef76dd3a7593 | 0.682951 | 2.763627 | false | false | false | false |
dhesant/elec4320 | Lab2/ipcore_dir/bram_decoder/simulation/bmg_stim_gen.vhd | 1 | 12,323 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (12 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(12 DOWNTO 0):= hex_to_std_logic_vector("0",13);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (21 downto 0) of std_logic_vector(12 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(12 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"bram_decoder.mif",
DEFAULT_DATA,
13,
22);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>22 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= READ_ADDR_INT AFTER 50 ns;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 22 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 5834542563f5deb561c9c38c5902626e | 0.550353 | 3.688417 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/hdl/triangle_intersect.vhd | 1 | 224,890 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
--Date : Sun May 08 18:17:54 2016
--Host : Win10Desktop running 64-bit major release (build 9200)
--Command : generate_target triangle_intersect.bd
--Design : triangle_intersect
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_YCVYZF is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_YCVYZF;
architecture STRUCTURE of m00_couplers_imp_YCVYZF is
component triangle_intersect_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component triangle_intersect_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(1 downto 0) <= auto_pc_to_m00_couplers_ARID(1 downto 0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(1 downto 0) <= auto_pc_to_m00_couplers_AWID(1 downto 0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(63 downto 0) <= auto_pc_to_m00_couplers_WDATA(63 downto 0);
M_AXI_wid(1 downto 0) <= auto_pc_to_m00_couplers_WID(1 downto 0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_pc_to_m00_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(1 downto 0) <= m00_couplers_to_auto_pc_BID(1 downto 0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(63 downto 0) <= m00_couplers_to_auto_pc_RDATA(63 downto 0);
S_AXI_rid(1 downto 0) <= m00_couplers_to_auto_pc_RID(1 downto 0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(1 downto 0) <= M_AXI_bid(1 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_pc_to_m00_couplers_RID(1 downto 0) <= M_AXI_rid(1 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(1 downto 0) <= S_AXI_arid(1 downto 0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(1 downto 0) <= S_AXI_awid(1 downto 0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(63 downto 0) <= S_AXI_wdata(63 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(7 downto 0) <= S_AXI_wstrb(7 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component triangle_intersect_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(1 downto 0) => auto_pc_to_m00_couplers_ARID(1 downto 0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(1 downto 0) => auto_pc_to_m00_couplers_AWID(1 downto 0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(1 downto 0) => auto_pc_to_m00_couplers_BID(1 downto 0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => auto_pc_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(1 downto 0) => auto_pc_to_m00_couplers_RID(1 downto 0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => auto_pc_to_m00_couplers_WDATA(63 downto 0),
m_axi_wid(1 downto 0) => auto_pc_to_m00_couplers_WID(1 downto 0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_pc_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => m00_couplers_to_auto_pc_ARID(1 downto 0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(1 downto 0) => m00_couplers_to_auto_pc_AWID(1 downto 0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(1 downto 0) => m00_couplers_to_auto_pc_BID(1 downto 0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(63 downto 0) => m00_couplers_to_auto_pc_RDATA(63 downto 0),
s_axi_rid(1 downto 0) => m00_couplers_to_auto_pc_RID(1 downto 0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(63 downto 0) => m00_couplers_to_auto_pc_WDATA(63 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(7 downto 0) => m00_couplers_to_auto_pc_WSTRB(7 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_18SS9VV is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_18SS9VV;
architecture STRUCTURE of s00_couplers_imp_18SS9VV is
component triangle_intersect_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component triangle_intersect_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(9 downto 0) <= auto_pc_to_s00_couplers_ARADDR(9 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(9 downto 0) <= auto_pc_to_s00_couplers_AWADDR(9 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component triangle_intersect_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => NLW_auto_pc_m_axi_wstrb_UNCONNECTED(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1FME12G is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s00_couplers_imp_1FME12G;
architecture STRUCTURE of s00_couplers_imp_1FME12G is
component triangle_intersect_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component triangle_intersect_auto_us_0;
signal GND_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s00_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID;
auto_us_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_us_RREADY <= S_AXI_rready;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
auto_us: component triangle_intersect_auto_us_0
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s00_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s00_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s00_couplers_RLAST,
m_axi_rready => auto_us_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s00_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1(0),
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => GND_1,
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3) => GND_1,
s_axi_arqos(2) => GND_1,
s_axi_arqos(1) => GND_1,
s_axi_arqos(0) => GND_1,
s_axi_arready => s00_couplers_to_auto_us_ARREADY,
s_axi_arregion(3) => GND_1,
s_axi_arregion(2) => GND_1,
s_axi_arregion(1) => GND_1,
s_axi_arregion(0) => GND_1,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s00_couplers_to_auto_us_RLAST,
s_axi_rready => s00_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1G34NP1 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1G34NP1;
architecture STRUCTURE of s01_couplers_imp_1G34NP1 is
component triangle_intersect_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
end component triangle_intersect_auto_us_1;
signal GND_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s01_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s01_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_WVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s01_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_awaddr(31 downto 0) <= auto_us_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s01_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s01_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s01_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s01_couplers_BREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s01_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s01_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s01_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s01_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_awready <= s01_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_auto_us_BVALID;
S_AXI_wready <= s01_couplers_to_auto_us_WREADY;
auto_us_to_s01_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s01_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s01_couplers_to_auto_us_BREADY <= S_AXI_bready;
s01_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s01_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
auto_us: component triangle_intersect_auto_us_1
port map (
m_axi_awaddr(31 downto 0) => auto_us_to_s01_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s01_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s01_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s01_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s01_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s01_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s01_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s01_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s01_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s01_couplers_AWVALID,
m_axi_bready => auto_us_to_s01_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s01_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s01_couplers_BVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s01_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s01_couplers_WLAST,
m_axi_wready => auto_us_to_s01_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s01_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s01_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_aresetn => S_ARESETN_1(0),
s_axi_awaddr(31 downto 0) => s01_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s01_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s01_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s01_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => GND_1,
s_axi_awprot(2 downto 0) => s01_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3) => GND_1,
s_axi_awqos(2) => GND_1,
s_axi_awqos(1) => GND_1,
s_axi_awqos(0) => GND_1,
s_axi_awready => s01_couplers_to_auto_us_AWREADY,
s_axi_awregion(3) => GND_1,
s_axi_awregion(2) => GND_1,
s_axi_awregion(1) => GND_1,
s_axi_awregion(0) => GND_1,
s_axi_awsize(2 downto 0) => s01_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s01_couplers_to_auto_us_AWVALID,
s_axi_bready => s01_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s01_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s01_couplers_to_auto_us_BVALID,
s_axi_wdata(31 downto 0) => s01_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s01_couplers_to_auto_us_WLAST,
s_axi_wready => s01_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s01_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s01_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_1FFYAJ6 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s02_couplers_imp_1FFYAJ6;
architecture STRUCTURE of s02_couplers_imp_1FFYAJ6 is
component triangle_intersect_auto_us_2 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component triangle_intersect_auto_us_2;
signal GND_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s02_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s02_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s02_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s02_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s02_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s02_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s02_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s02_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s02_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s02_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s02_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s02_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s02_couplers_RVALID : STD_LOGIC;
signal auto_us_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_us_to_s02_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s02_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s02_couplers_WVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s02_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_auto_us_RVALID : STD_LOGIC;
signal s02_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s02_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s02_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s02_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s02_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s02_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s02_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s02_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s02_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s02_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s02_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_us_to_s02_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s02_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s02_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s02_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s02_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s02_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s02_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s02_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s02_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s02_couplers_BREADY;
M_AXI_rready <= auto_us_to_s02_couplers_RREADY;
M_AXI_wdata(63 downto 0) <= auto_us_to_s02_couplers_WDATA(63 downto 0);
M_AXI_wlast <= auto_us_to_s02_couplers_WLAST;
M_AXI_wstrb(7 downto 0) <= auto_us_to_s02_couplers_WSTRB(7 downto 0);
M_AXI_wvalid <= auto_us_to_s02_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s02_couplers_to_auto_us_ARREADY;
S_AXI_awready <= s02_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s02_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s02_couplers_to_auto_us_BVALID;
S_AXI_rdata(31 downto 0) <= s02_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s02_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s02_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s02_couplers_to_auto_us_RVALID;
S_AXI_wready <= s02_couplers_to_auto_us_WREADY;
auto_us_to_s02_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s02_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s02_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s02_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_us_to_s02_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s02_couplers_RVALID <= M_AXI_rvalid;
auto_us_to_s02_couplers_WREADY <= M_AXI_wready;
s02_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s02_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s02_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s02_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s02_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s02_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s02_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s02_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s02_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s02_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s02_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s02_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s02_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s02_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s02_couplers_to_auto_us_BREADY <= S_AXI_bready;
s02_couplers_to_auto_us_RREADY <= S_AXI_rready;
s02_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s02_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s02_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s02_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
auto_us: component triangle_intersect_auto_us_2
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s02_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s02_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s02_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s02_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s02_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s02_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s02_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s02_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s02_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s02_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_us_to_s02_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s02_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s02_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s02_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s02_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s02_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s02_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s02_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s02_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s02_couplers_AWVALID,
m_axi_bready => auto_us_to_s02_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s02_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s02_couplers_BVALID,
m_axi_rdata(63 downto 0) => auto_us_to_s02_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_us_to_s02_couplers_RLAST,
m_axi_rready => auto_us_to_s02_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s02_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s02_couplers_RVALID,
m_axi_wdata(63 downto 0) => auto_us_to_s02_couplers_WDATA(63 downto 0),
m_axi_wlast => auto_us_to_s02_couplers_WLAST,
m_axi_wready => auto_us_to_s02_couplers_WREADY,
m_axi_wstrb(7 downto 0) => auto_us_to_s02_couplers_WSTRB(7 downto 0),
m_axi_wvalid => auto_us_to_s02_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s02_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s02_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s02_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1(0),
s_axi_arlen(7 downto 0) => s02_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => GND_1,
s_axi_arprot(2 downto 0) => s02_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3) => GND_1,
s_axi_arqos(2) => GND_1,
s_axi_arqos(1) => GND_1,
s_axi_arqos(0) => GND_1,
s_axi_arready => s02_couplers_to_auto_us_ARREADY,
s_axi_arregion(3) => GND_1,
s_axi_arregion(2) => GND_1,
s_axi_arregion(1) => GND_1,
s_axi_arregion(0) => GND_1,
s_axi_arsize(2 downto 0) => s02_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s02_couplers_to_auto_us_ARVALID,
s_axi_awaddr(31 downto 0) => s02_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s02_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s02_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s02_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => GND_1,
s_axi_awprot(2 downto 0) => s02_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3) => GND_1,
s_axi_awqos(2) => GND_1,
s_axi_awqos(1) => GND_1,
s_axi_awqos(0) => GND_1,
s_axi_awready => s02_couplers_to_auto_us_AWREADY,
s_axi_awregion(3) => GND_1,
s_axi_awregion(2) => GND_1,
s_axi_awregion(1) => GND_1,
s_axi_awregion(0) => GND_1,
s_axi_awsize(2 downto 0) => s02_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s02_couplers_to_auto_us_AWVALID,
s_axi_bready => s02_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s02_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s02_couplers_to_auto_us_BVALID,
s_axi_rdata(31 downto 0) => s02_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s02_couplers_to_auto_us_RLAST,
s_axi_rready => s02_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s02_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s02_couplers_to_auto_us_RVALID,
s_axi_wdata(31 downto 0) => s02_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s02_couplers_to_auto_us_WLAST,
s_axi_wready => s02_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s02_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s02_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity triangle_intersect_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awready : out STD_LOGIC;
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_bready : in STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_wvalid : in STD_LOGIC
);
end triangle_intersect_axi_mem_intercon_0;
architecture STRUCTURE of triangle_intersect_axi_mem_intercon_0 is
component triangle_intersect_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 95 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component triangle_intersect_xbar_0;
signal GND_1 : STD_LOGIC;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S02_ACLK_1 : STD_LOGIC;
signal S02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal VCC_1 : STD_LOGIC;
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s02_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC;
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s02_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s02_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s02_couplers_to_xbar_BREADY : STD_LOGIC;
signal s02_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 191 downto 128 );
signal s02_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RREADY : STD_LOGIC;
signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s02_couplers_to_xbar_WLAST : STD_LOGIC;
signal s02_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 64 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARID(1 downto 0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWID(1 downto 0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(63 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0);
M00_AXI_wid(1 downto 0) <= m00_couplers_to_axi_mem_intercon_WID(1 downto 0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(7 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID;
S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY;
S02_ACLK_1 <= S02_ACLK;
S02_ARESETN_1(0) <= S02_ARESETN(0);
S02_AXI_arready <= axi_mem_intercon_to_s02_couplers_ARREADY;
S02_AXI_awready <= axi_mem_intercon_to_s02_couplers_AWREADY;
S02_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s02_couplers_BRESP(1 downto 0);
S02_AXI_bvalid <= axi_mem_intercon_to_s02_couplers_BVALID;
S02_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0);
S02_AXI_rlast <= axi_mem_intercon_to_s02_couplers_RLAST;
S02_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0);
S02_AXI_rvalid <= axi_mem_intercon_to_s02_couplers_RVALID;
S02_AXI_wready <= axi_mem_intercon_to_s02_couplers_WREADY;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready;
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast;
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid;
axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s02_couplers_ARVALID <= S02_AXI_arvalid;
axi_mem_intercon_to_s02_couplers_AWADDR(31 downto 0) <= S02_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s02_couplers_AWBURST(1 downto 0) <= S02_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s02_couplers_AWCACHE(3 downto 0) <= S02_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s02_couplers_AWLEN(7 downto 0) <= S02_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s02_couplers_AWPROT(2 downto 0) <= S02_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s02_couplers_AWSIZE(2 downto 0) <= S02_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s02_couplers_AWVALID <= S02_AXI_awvalid;
axi_mem_intercon_to_s02_couplers_BREADY <= S02_AXI_bready;
axi_mem_intercon_to_s02_couplers_RREADY <= S02_AXI_rready;
axi_mem_intercon_to_s02_couplers_WDATA(31 downto 0) <= S02_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s02_couplers_WLAST <= S02_AXI_wlast;
axi_mem_intercon_to_s02_couplers_WSTRB(3 downto 0) <= S02_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s02_couplers_WVALID <= S02_AXI_wvalid;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(1 downto 0) <= M00_AXI_bid(1 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0);
m00_couplers_to_axi_mem_intercon_RID(1 downto 0) <= M00_AXI_rid(1 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
m00_couplers: entity work.m00_couplers_imp_YCVYZF
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARID(1 downto 0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWID(1 downto 0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(1 downto 0) => m00_couplers_to_axi_mem_intercon_BID(1 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(63 downto 0),
M_AXI_rid(1 downto 0) => m00_couplers_to_axi_mem_intercon_RID(1 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(63 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(63 downto 0),
M_AXI_wid(1 downto 0) => m00_couplers_to_axi_mem_intercon_WID(1 downto 0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(7 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(7 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(1 downto 0) => xbar_to_m00_couplers_ARID(1 downto 0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(1 downto 0) => xbar_to_m00_couplers_AWID(1 downto 0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(1 downto 0) => xbar_to_m00_couplers_BID(1 downto 0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
S_AXI_rid(1 downto 0) => xbar_to_m00_couplers_RID(1 downto 0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_1FME12G
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID
);
s01_couplers: entity work.s01_couplers_imp_1G34NP1
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s01_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s01_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(63 downto 0) => s01_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s01_couplers_to_xbar_WLAST,
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(7 downto 0) => s01_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID
);
s02_couplers: entity work.s02_couplers_imp_1FFYAJ6
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s02_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s02_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s02_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s02_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s02_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s02_couplers_to_xbar_ARREADY(2),
M_AXI_arsize(2 downto 0) => s02_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s02_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s02_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s02_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s02_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s02_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s02_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s02_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s02_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s02_couplers_to_xbar_AWREADY(2),
M_AXI_awsize(2 downto 0) => s02_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s02_couplers_to_xbar_AWVALID,
M_AXI_bready => s02_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s02_couplers_to_xbar_BRESP(5 downto 4),
M_AXI_bvalid => s02_couplers_to_xbar_BVALID(2),
M_AXI_rdata(63 downto 0) => s02_couplers_to_xbar_RDATA(191 downto 128),
M_AXI_rlast => s02_couplers_to_xbar_RLAST(2),
M_AXI_rready => s02_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4),
M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2),
M_AXI_wdata(63 downto 0) => s02_couplers_to_xbar_WDATA(63 downto 0),
M_AXI_wlast => s02_couplers_to_xbar_WLAST,
M_AXI_wready => s02_couplers_to_xbar_WREADY(2),
M_AXI_wstrb(7 downto 0) => s02_couplers_to_xbar_WSTRB(7 downto 0),
M_AXI_wvalid => s02_couplers_to_xbar_WVALID,
S_ACLK => S02_ACLK_1,
S_ARESETN(0) => S02_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s02_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s02_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s02_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s02_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s02_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s02_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s02_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s02_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s02_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s02_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s02_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s02_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s02_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s02_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s02_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s02_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s02_couplers_WVALID
);
xbar: component triangle_intersect_xbar_0
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(1 downto 0) => xbar_to_m00_couplers_ARID(1 downto 0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(1 downto 0) => xbar_to_m00_couplers_AWID(1 downto 0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(1 downto 0) => xbar_to_m00_couplers_BID(1 downto 0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 0) => xbar_to_m00_couplers_RDATA(63 downto 0),
m_axi_rid(1 downto 0) => xbar_to_m00_couplers_RID(1 downto 0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 0) => xbar_to_m00_couplers_WDATA(63 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 0) => xbar_to_m00_couplers_WSTRB(7 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(63) => GND_1,
s_axi_araddr(62) => GND_1,
s_axi_araddr(61) => GND_1,
s_axi_araddr(60) => GND_1,
s_axi_araddr(59) => GND_1,
s_axi_araddr(58) => GND_1,
s_axi_araddr(57) => GND_1,
s_axi_araddr(56) => GND_1,
s_axi_araddr(55) => GND_1,
s_axi_araddr(54) => GND_1,
s_axi_araddr(53) => GND_1,
s_axi_araddr(52) => GND_1,
s_axi_araddr(51) => GND_1,
s_axi_araddr(50) => GND_1,
s_axi_araddr(49) => GND_1,
s_axi_araddr(48) => GND_1,
s_axi_araddr(47) => GND_1,
s_axi_araddr(46) => GND_1,
s_axi_araddr(45) => GND_1,
s_axi_araddr(44) => GND_1,
s_axi_araddr(43) => GND_1,
s_axi_araddr(42) => GND_1,
s_axi_araddr(41) => GND_1,
s_axi_araddr(40) => GND_1,
s_axi_araddr(39) => GND_1,
s_axi_araddr(38) => GND_1,
s_axi_araddr(37) => GND_1,
s_axi_araddr(36) => GND_1,
s_axi_araddr(35) => GND_1,
s_axi_araddr(34) => GND_1,
s_axi_araddr(33) => GND_1,
s_axi_araddr(32) => GND_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(5 downto 4) => s02_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(3) => GND_1,
s_axi_arburst(2) => GND_1,
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(11 downto 8) => s02_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(7) => GND_1,
s_axi_arcache(6) => GND_1,
s_axi_arcache(5) => GND_1,
s_axi_arcache(4) => GND_1,
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(5) => GND_1,
s_axi_arid(4) => GND_1,
s_axi_arid(3) => GND_1,
s_axi_arid(2) => GND_1,
s_axi_arid(1) => GND_1,
s_axi_arid(0) => GND_1,
s_axi_arlen(23 downto 16) => s02_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(15) => GND_1,
s_axi_arlen(14) => GND_1,
s_axi_arlen(13) => GND_1,
s_axi_arlen(12) => GND_1,
s_axi_arlen(11) => GND_1,
s_axi_arlen(10) => GND_1,
s_axi_arlen(9) => GND_1,
s_axi_arlen(8) => GND_1,
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(2) => s02_couplers_to_xbar_ARLOCK(0),
s_axi_arlock(1) => GND_1,
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(5) => GND_1,
s_axi_arprot(4) => GND_1,
s_axi_arprot(3) => GND_1,
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(11 downto 8) => s02_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arqos(7) => GND_1,
s_axi_arqos(6) => GND_1,
s_axi_arqos(5) => GND_1,
s_axi_arqos(4) => GND_1,
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2),
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(8 downto 6) => s02_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(5) => GND_1,
s_axi_arsize(4) => GND_1,
s_axi_arsize(3) => GND_1,
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID,
s_axi_arvalid(1) => GND_1,
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(95 downto 64) => s02_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31) => GND_1,
s_axi_awaddr(30) => GND_1,
s_axi_awaddr(29) => GND_1,
s_axi_awaddr(28) => GND_1,
s_axi_awaddr(27) => GND_1,
s_axi_awaddr(26) => GND_1,
s_axi_awaddr(25) => GND_1,
s_axi_awaddr(24) => GND_1,
s_axi_awaddr(23) => GND_1,
s_axi_awaddr(22) => GND_1,
s_axi_awaddr(21) => GND_1,
s_axi_awaddr(20) => GND_1,
s_axi_awaddr(19) => GND_1,
s_axi_awaddr(18) => GND_1,
s_axi_awaddr(17) => GND_1,
s_axi_awaddr(16) => GND_1,
s_axi_awaddr(15) => GND_1,
s_axi_awaddr(14) => GND_1,
s_axi_awaddr(13) => GND_1,
s_axi_awaddr(12) => GND_1,
s_axi_awaddr(11) => GND_1,
s_axi_awaddr(10) => GND_1,
s_axi_awaddr(9) => GND_1,
s_axi_awaddr(8) => GND_1,
s_axi_awaddr(7) => GND_1,
s_axi_awaddr(6) => GND_1,
s_axi_awaddr(5) => GND_1,
s_axi_awaddr(4) => GND_1,
s_axi_awaddr(3) => GND_1,
s_axi_awaddr(2) => GND_1,
s_axi_awaddr(1) => GND_1,
s_axi_awaddr(0) => GND_1,
s_axi_awburst(5 downto 4) => s02_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1) => GND_1,
s_axi_awburst(0) => GND_1,
s_axi_awcache(11 downto 8) => s02_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3) => GND_1,
s_axi_awcache(2) => GND_1,
s_axi_awcache(1) => GND_1,
s_axi_awcache(0) => GND_1,
s_axi_awid(5) => GND_1,
s_axi_awid(4) => GND_1,
s_axi_awid(3) => GND_1,
s_axi_awid(2) => GND_1,
s_axi_awid(1) => GND_1,
s_axi_awid(0) => GND_1,
s_axi_awlen(23 downto 16) => s02_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7) => GND_1,
s_axi_awlen(6) => GND_1,
s_axi_awlen(5) => GND_1,
s_axi_awlen(4) => GND_1,
s_axi_awlen(3) => GND_1,
s_axi_awlen(2) => GND_1,
s_axi_awlen(1) => GND_1,
s_axi_awlen(0) => GND_1,
s_axi_awlock(2) => s02_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(1) => s01_couplers_to_xbar_AWLOCK(0),
s_axi_awlock(0) => GND_1,
s_axi_awprot(8 downto 6) => s02_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2) => GND_1,
s_axi_awprot(1) => GND_1,
s_axi_awprot(0) => GND_1,
s_axi_awqos(11 downto 8) => s02_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(7 downto 4) => s01_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awqos(3) => GND_1,
s_axi_awqos(2) => GND_1,
s_axi_awqos(1) => GND_1,
s_axi_awqos(0) => GND_1,
s_axi_awready(2) => s02_couplers_to_xbar_AWREADY(2),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(8 downto 6) => s02_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2) => GND_1,
s_axi_awsize(1) => GND_1,
s_axi_awsize(0) => GND_1,
s_axi_awvalid(2) => s02_couplers_to_xbar_AWVALID,
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => GND_1,
s_axi_bid(5 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(5 downto 0),
s_axi_bready(2) => s02_couplers_to_xbar_BREADY,
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => GND_1,
s_axi_bresp(5 downto 4) => s02_couplers_to_xbar_BRESP(5 downto 4),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(2) => s02_couplers_to_xbar_BVALID(2),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(191 downto 128) => s02_couplers_to_xbar_RDATA(191 downto 128),
s_axi_rdata(127 downto 64) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 64),
s_axi_rdata(63 downto 0) => s00_couplers_to_xbar_RDATA(63 downto 0),
s_axi_rid(5 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(5 downto 0),
s_axi_rlast(2) => s02_couplers_to_xbar_RLAST(2),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(2) => s02_couplers_to_xbar_RREADY,
s_axi_rready(1) => GND_1,
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4),
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(191 downto 128) => s02_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wdata(127 downto 64) => s01_couplers_to_xbar_WDATA(63 downto 0),
s_axi_wdata(63) => GND_1,
s_axi_wdata(62) => GND_1,
s_axi_wdata(61) => GND_1,
s_axi_wdata(60) => GND_1,
s_axi_wdata(59) => GND_1,
s_axi_wdata(58) => GND_1,
s_axi_wdata(57) => GND_1,
s_axi_wdata(56) => GND_1,
s_axi_wdata(55) => GND_1,
s_axi_wdata(54) => GND_1,
s_axi_wdata(53) => GND_1,
s_axi_wdata(52) => GND_1,
s_axi_wdata(51) => GND_1,
s_axi_wdata(50) => GND_1,
s_axi_wdata(49) => GND_1,
s_axi_wdata(48) => GND_1,
s_axi_wdata(47) => GND_1,
s_axi_wdata(46) => GND_1,
s_axi_wdata(45) => GND_1,
s_axi_wdata(44) => GND_1,
s_axi_wdata(43) => GND_1,
s_axi_wdata(42) => GND_1,
s_axi_wdata(41) => GND_1,
s_axi_wdata(40) => GND_1,
s_axi_wdata(39) => GND_1,
s_axi_wdata(38) => GND_1,
s_axi_wdata(37) => GND_1,
s_axi_wdata(36) => GND_1,
s_axi_wdata(35) => GND_1,
s_axi_wdata(34) => GND_1,
s_axi_wdata(33) => GND_1,
s_axi_wdata(32) => GND_1,
s_axi_wdata(31) => GND_1,
s_axi_wdata(30) => GND_1,
s_axi_wdata(29) => GND_1,
s_axi_wdata(28) => GND_1,
s_axi_wdata(27) => GND_1,
s_axi_wdata(26) => GND_1,
s_axi_wdata(25) => GND_1,
s_axi_wdata(24) => GND_1,
s_axi_wdata(23) => GND_1,
s_axi_wdata(22) => GND_1,
s_axi_wdata(21) => GND_1,
s_axi_wdata(20) => GND_1,
s_axi_wdata(19) => GND_1,
s_axi_wdata(18) => GND_1,
s_axi_wdata(17) => GND_1,
s_axi_wdata(16) => GND_1,
s_axi_wdata(15) => GND_1,
s_axi_wdata(14) => GND_1,
s_axi_wdata(13) => GND_1,
s_axi_wdata(12) => GND_1,
s_axi_wdata(11) => GND_1,
s_axi_wdata(10) => GND_1,
s_axi_wdata(9) => GND_1,
s_axi_wdata(8) => GND_1,
s_axi_wdata(7) => GND_1,
s_axi_wdata(6) => GND_1,
s_axi_wdata(5) => GND_1,
s_axi_wdata(4) => GND_1,
s_axi_wdata(3) => GND_1,
s_axi_wdata(2) => GND_1,
s_axi_wdata(1) => GND_1,
s_axi_wdata(0) => GND_1,
s_axi_wlast(2) => s02_couplers_to_xbar_WLAST,
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST,
s_axi_wlast(0) => VCC_1,
s_axi_wready(2) => s02_couplers_to_xbar_WREADY(2),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(23 downto 16) => s02_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wstrb(15 downto 8) => s01_couplers_to_xbar_WSTRB(7 downto 0),
s_axi_wstrb(7) => VCC_1,
s_axi_wstrb(6) => VCC_1,
s_axi_wstrb(5) => VCC_1,
s_axi_wstrb(4) => VCC_1,
s_axi_wstrb(3) => VCC_1,
s_axi_wstrb(2) => VCC_1,
s_axi_wstrb(1) => VCC_1,
s_axi_wstrb(0) => VCC_1,
s_axi_wvalid(2) => s02_couplers_to_xbar_WVALID,
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => GND_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity triangle_intersect_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end triangle_intersect_processing_system7_0_axi_periph_0;
architecture STRUCTURE of triangle_intersect_processing_system7_0_axi_periph_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 9 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 9 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(9 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_ARADDR(9 downto 0);
M00_AXI_arvalid <= s00_couplers_to_processing_system7_0_axi_periph_ARVALID;
M00_AXI_awaddr(9 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_AWADDR(9 downto 0);
M00_AXI_awvalid <= s00_couplers_to_processing_system7_0_axi_periph_AWVALID;
M00_AXI_bready <= s00_couplers_to_processing_system7_0_axi_periph_BREADY;
M00_AXI_rready <= s00_couplers_to_processing_system7_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wvalid <= s00_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
processing_system7_0_axi_periph_ACLK_net <= M00_ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= M00_ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_processing_system7_0_axi_periph_ARREADY <= M00_AXI_arready;
s00_couplers_to_processing_system7_0_axi_periph_AWREADY <= M00_AXI_awready;
s00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_BVALID <= M00_AXI_bvalid;
s00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_RVALID <= M00_AXI_rvalid;
s00_couplers_to_processing_system7_0_axi_periph_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_18SS9VV
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(9 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_ARADDR(9 downto 0),
M_AXI_arready => s00_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => s00_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(9 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_AWADDR(9 downto 0),
M_AXI_awready => s00_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => s00_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => s00_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => s00_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity triangle_intersect is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of triangle_intersect : entity is "triangle_intersect,IP_Integrator,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=triangle_intersect,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=18,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,da_axi4_cnt=4,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of triangle_intersect : entity is "triangle_intersect.hwdef";
end triangle_intersect;
architecture STRUCTURE of triangle_intersect is
component triangle_intersect_processing_system7_0_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component triangle_intersect_processing_system7_0_0;
component triangle_intersect_axi_dma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_sg_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_sg_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_sg_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_sg_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_sg_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_sg_awvalid : out STD_LOGIC;
m_axi_sg_awready : in STD_LOGIC;
m_axi_sg_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_sg_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_sg_wlast : out STD_LOGIC;
m_axi_sg_wvalid : out STD_LOGIC;
m_axi_sg_wready : in STD_LOGIC;
m_axi_sg_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_bvalid : in STD_LOGIC;
m_axi_sg_bready : out STD_LOGIC;
m_axi_sg_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_sg_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_sg_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_sg_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_sg_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_sg_arvalid : out STD_LOGIC;
m_axi_sg_arready : in STD_LOGIC;
m_axi_sg_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_sg_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_sg_rlast : in STD_LOGIC;
m_axi_sg_rvalid : in STD_LOGIC;
m_axi_sg_rready : out STD_LOGIC;
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
mm2s_introut : out STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component triangle_intersect_axi_dma_0_0;
component triangle_intersect_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component triangle_intersect_rst_processing_system7_0_100M_0;
component triangle_intersect_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component triangle_intersect_xlconcat_0_0;
component triangle_intersect_tri_intersect_0_1 is
port (
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
ins_TVALID : in STD_LOGIC;
ins_TREADY : out STD_LOGIC;
ins_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
ins_TDEST : in STD_LOGIC_VECTOR ( 0 to 0 );
ins_TKEEP : in STD_LOGIC_VECTOR ( 3 downto 0 );
ins_TSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
ins_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
ins_TLAST : in STD_LOGIC_VECTOR ( 0 to 0 );
ins_TID : in STD_LOGIC_VECTOR ( 0 to 0 );
outs_TVALID : out STD_LOGIC;
outs_TREADY : in STD_LOGIC;
outs_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
outs_TDEST : out STD_LOGIC_VECTOR ( 0 to 0 );
outs_TKEEP : out STD_LOGIC_VECTOR ( 3 downto 0 );
outs_TSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
outs_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
outs_TLAST : out STD_LOGIC_VECTOR ( 0 to 0 );
outs_TID : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component triangle_intersect_tri_intersect_0_1;
signal GND_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_SG_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_SG_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_SG_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_SG_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_SG_ARREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_SG_ARVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_SG_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_SG_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_SG_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_0_M_AXI_SG_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_SG_AWREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_0_M_AXI_SG_AWVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_BREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_SG_BVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_SG_RLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_RREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_0_M_AXI_SG_RVALID : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_0_M_AXI_SG_WLAST : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_WREADY : STD_LOGIC;
signal axi_dma_0_M_AXI_SG_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_0_M_AXI_SG_WVALID : STD_LOGIC;
signal axi_dma_0_mm2s_introut : STD_LOGIC;
signal axi_dma_0_s2mm_introut : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 9 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 9 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal tri_intersect_0_outs_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal tri_intersect_0_outs_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal tri_intersect_0_outs_TLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal tri_intersect_0_outs_TREADY : STD_LOGIC;
signal tri_intersect_0_outs_TVALID : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_tri_intersect_0_ins_TSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_tri_intersect_0_outs_TDEST_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_tri_intersect_0_outs_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_tri_intersect_0_outs_TSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_tri_intersect_0_outs_TUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_dma_0: component triangle_intersect_axi_dma_0_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_0_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_0_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_0_M_AXI_S2MM_WVALID,
m_axi_sg_aclk => processing_system7_0_FCLK_CLK0,
m_axi_sg_araddr(31 downto 0) => axi_dma_0_M_AXI_SG_ARADDR(31 downto 0),
m_axi_sg_arburst(1 downto 0) => axi_dma_0_M_AXI_SG_ARBURST(1 downto 0),
m_axi_sg_arcache(3 downto 0) => axi_dma_0_M_AXI_SG_ARCACHE(3 downto 0),
m_axi_sg_arlen(7 downto 0) => axi_dma_0_M_AXI_SG_ARLEN(7 downto 0),
m_axi_sg_arprot(2 downto 0) => axi_dma_0_M_AXI_SG_ARPROT(2 downto 0),
m_axi_sg_arready => axi_dma_0_M_AXI_SG_ARREADY,
m_axi_sg_arsize(2 downto 0) => axi_dma_0_M_AXI_SG_ARSIZE(2 downto 0),
m_axi_sg_arvalid => axi_dma_0_M_AXI_SG_ARVALID,
m_axi_sg_awaddr(31 downto 0) => axi_dma_0_M_AXI_SG_AWADDR(31 downto 0),
m_axi_sg_awburst(1 downto 0) => axi_dma_0_M_AXI_SG_AWBURST(1 downto 0),
m_axi_sg_awcache(3 downto 0) => axi_dma_0_M_AXI_SG_AWCACHE(3 downto 0),
m_axi_sg_awlen(7 downto 0) => axi_dma_0_M_AXI_SG_AWLEN(7 downto 0),
m_axi_sg_awprot(2 downto 0) => axi_dma_0_M_AXI_SG_AWPROT(2 downto 0),
m_axi_sg_awready => axi_dma_0_M_AXI_SG_AWREADY,
m_axi_sg_awsize(2 downto 0) => axi_dma_0_M_AXI_SG_AWSIZE(2 downto 0),
m_axi_sg_awvalid => axi_dma_0_M_AXI_SG_AWVALID,
m_axi_sg_bready => axi_dma_0_M_AXI_SG_BREADY,
m_axi_sg_bresp(1 downto 0) => axi_dma_0_M_AXI_SG_BRESP(1 downto 0),
m_axi_sg_bvalid => axi_dma_0_M_AXI_SG_BVALID,
m_axi_sg_rdata(31 downto 0) => axi_dma_0_M_AXI_SG_RDATA(31 downto 0),
m_axi_sg_rlast => axi_dma_0_M_AXI_SG_RLAST,
m_axi_sg_rready => axi_dma_0_M_AXI_SG_RREADY,
m_axi_sg_rresp(1 downto 0) => axi_dma_0_M_AXI_SG_RRESP(1 downto 0),
m_axi_sg_rvalid => axi_dma_0_M_AXI_SG_RVALID,
m_axi_sg_wdata(31 downto 0) => axi_dma_0_M_AXI_SG_WDATA(31 downto 0),
m_axi_sg_wlast => axi_dma_0_M_AXI_SG_WLAST,
m_axi_sg_wready => axi_dma_0_M_AXI_SG_WREADY,
m_axi_sg_wstrb(3 downto 0) => axi_dma_0_M_AXI_SG_WSTRB(3 downto 0),
m_axi_sg_wvalid => axi_dma_0_M_AXI_SG_WVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
m_axis_mm2s_tlast => axi_dma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_dma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_0_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_0_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_0_mm2s_prmry_reset_out_n_UNCONNECTED,
s2mm_introut => axi_dma_0_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_0_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID,
s_axis_s2mm_tdata(31 downto 0) => tri_intersect_0_outs_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => tri_intersect_0_outs_TKEEP(3 downto 0),
s_axis_s2mm_tlast => tri_intersect_0_outs_TLAST(0),
s_axis_s2mm_tready => tri_intersect_0_outs_TREADY,
s_axis_s2mm_tvalid => tri_intersect_0_outs_TVALID
);
axi_mem_intercon: entity work.triangle_intersect_axi_mem_intercon_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(1 downto 0) => axi_mem_intercon_M00_AXI_ARID(1 downto 0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(1 downto 0) => axi_mem_intercon_M00_AXI_AWID(1 downto 0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(1 downto 0) => axi_mem_intercon_M00_AXI_BID(1 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
M00_AXI_rid(1 downto 0) => axi_mem_intercon_M00_AXI_RID(1 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
M00_AXI_wid(1 downto 0) => axi_mem_intercon_M00_AXI_WID(1 downto 0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready => axi_dma_0_M_AXI_MM2S_ARREADY,
S00_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid => axi_dma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast => axi_dma_0_M_AXI_MM2S_RLAST,
S00_AXI_rready => axi_dma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid => axi_dma_0_M_AXI_MM2S_RVALID,
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready => axi_dma_0_M_AXI_S2MM_AWREADY,
S01_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid => axi_dma_0_M_AXI_S2MM_AWVALID,
S01_AXI_bready => axi_dma_0_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid => axi_dma_0_M_AXI_S2MM_BVALID,
S01_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast => axi_dma_0_M_AXI_S2MM_WLAST,
S01_AXI_wready => axi_dma_0_M_AXI_S2MM_WREADY,
S01_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid => axi_dma_0_M_AXI_S2MM_WVALID,
S02_ACLK => processing_system7_0_FCLK_CLK0,
S02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S02_AXI_araddr(31 downto 0) => axi_dma_0_M_AXI_SG_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => axi_dma_0_M_AXI_SG_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => axi_dma_0_M_AXI_SG_ARCACHE(3 downto 0),
S02_AXI_arlen(7 downto 0) => axi_dma_0_M_AXI_SG_ARLEN(7 downto 0),
S02_AXI_arprot(2 downto 0) => axi_dma_0_M_AXI_SG_ARPROT(2 downto 0),
S02_AXI_arready => axi_dma_0_M_AXI_SG_ARREADY,
S02_AXI_arsize(2 downto 0) => axi_dma_0_M_AXI_SG_ARSIZE(2 downto 0),
S02_AXI_arvalid => axi_dma_0_M_AXI_SG_ARVALID,
S02_AXI_awaddr(31 downto 0) => axi_dma_0_M_AXI_SG_AWADDR(31 downto 0),
S02_AXI_awburst(1 downto 0) => axi_dma_0_M_AXI_SG_AWBURST(1 downto 0),
S02_AXI_awcache(3 downto 0) => axi_dma_0_M_AXI_SG_AWCACHE(3 downto 0),
S02_AXI_awlen(7 downto 0) => axi_dma_0_M_AXI_SG_AWLEN(7 downto 0),
S02_AXI_awprot(2 downto 0) => axi_dma_0_M_AXI_SG_AWPROT(2 downto 0),
S02_AXI_awready => axi_dma_0_M_AXI_SG_AWREADY,
S02_AXI_awsize(2 downto 0) => axi_dma_0_M_AXI_SG_AWSIZE(2 downto 0),
S02_AXI_awvalid => axi_dma_0_M_AXI_SG_AWVALID,
S02_AXI_bready => axi_dma_0_M_AXI_SG_BREADY,
S02_AXI_bresp(1 downto 0) => axi_dma_0_M_AXI_SG_BRESP(1 downto 0),
S02_AXI_bvalid => axi_dma_0_M_AXI_SG_BVALID,
S02_AXI_rdata(31 downto 0) => axi_dma_0_M_AXI_SG_RDATA(31 downto 0),
S02_AXI_rlast => axi_dma_0_M_AXI_SG_RLAST,
S02_AXI_rready => axi_dma_0_M_AXI_SG_RREADY,
S02_AXI_rresp(1 downto 0) => axi_dma_0_M_AXI_SG_RRESP(1 downto 0),
S02_AXI_rvalid => axi_dma_0_M_AXI_SG_RVALID,
S02_AXI_wdata(31 downto 0) => axi_dma_0_M_AXI_SG_WDATA(31 downto 0),
S02_AXI_wlast => axi_dma_0_M_AXI_SG_WLAST,
S02_AXI_wready => axi_dma_0_M_AXI_SG_WREADY,
S02_AXI_wstrb(3 downto 0) => axi_dma_0_M_AXI_SG_WSTRB(3 downto 0),
S02_AXI_wvalid => axi_dma_0_M_AXI_SG_WVALID
);
processing_system7_0: component triangle_intersect_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(1 downto 0) => xlconcat_0_dout(1 downto 0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5) => GND_1,
S_AXI_HP0_ARID(4) => GND_1,
S_AXI_HP0_ARID(3) => GND_1,
S_AXI_HP0_ARID(2) => GND_1,
S_AXI_HP0_ARID(1 downto 0) => axi_mem_intercon_M00_AXI_ARID(1 downto 0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5) => GND_1,
S_AXI_HP0_AWID(4) => GND_1,
S_AXI_HP0_AWID(3) => GND_1,
S_AXI_HP0_AWID(2) => GND_1,
S_AXI_HP0_AWID(1 downto 0) => axi_mem_intercon_M00_AXI_AWID(1 downto 0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => axi_mem_intercon_M00_AXI_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => GND_1,
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => axi_mem_intercon_M00_AXI_WDATA(63 downto 0),
S_AXI_HP0_WID(5) => GND_1,
S_AXI_HP0_WID(4) => GND_1,
S_AXI_HP0_WID(3) => GND_1,
S_AXI_HP0_WID(2) => GND_1,
S_AXI_HP0_WID(1 downto 0) => axi_mem_intercon_M00_AXI_WID(1 downto 0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => GND_1,
S_AXI_HP0_WSTRB(7 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(7 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.triangle_intersect_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(9 downto 0),
M00_AXI_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
M00_AXI_awaddr(9 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(9 downto 0),
M00_AXI_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
M00_AXI_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component triangle_intersect_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
tri_intersect_0: component triangle_intersect_tri_intersect_0_1
port map (
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_processing_system7_0_100M_peripheral_aresetn(0),
ins_TDATA(31 downto 0) => axi_dma_0_M_AXIS_MM2S_TDATA(31 downto 0),
ins_TDEST(0) => GND_1,
ins_TID(0) => GND_1,
ins_TKEEP(3 downto 0) => axi_dma_0_M_AXIS_MM2S_TKEEP(3 downto 0),
ins_TLAST(0) => axi_dma_0_M_AXIS_MM2S_TLAST,
ins_TREADY => axi_dma_0_M_AXIS_MM2S_TREADY,
ins_TSTRB(3) => NLW_tri_intersect_0_ins_TSTRB_UNCONNECTED(3),
ins_TSTRB(2) => VCC_1,
ins_TSTRB(1) => VCC_1,
ins_TSTRB(0) => VCC_1,
ins_TUSER(0) => GND_1,
ins_TVALID => axi_dma_0_M_AXIS_MM2S_TVALID,
outs_TDATA(31 downto 0) => tri_intersect_0_outs_TDATA(31 downto 0),
outs_TDEST(0) => NLW_tri_intersect_0_outs_TDEST_UNCONNECTED(0),
outs_TID(0) => NLW_tri_intersect_0_outs_TID_UNCONNECTED(0),
outs_TKEEP(3 downto 0) => tri_intersect_0_outs_TKEEP(3 downto 0),
outs_TLAST(0) => tri_intersect_0_outs_TLAST(0),
outs_TREADY => tri_intersect_0_outs_TREADY,
outs_TSTRB(3 downto 0) => NLW_tri_intersect_0_outs_TSTRB_UNCONNECTED(3 downto 0),
outs_TUSER(0) => NLW_tri_intersect_0_outs_TUSER_UNCONNECTED(0),
outs_TVALID => tri_intersect_0_outs_TVALID
);
xlconcat_0: component triangle_intersect_xlconcat_0_0
port map (
In0(0) => axi_dma_0_mm2s_introut,
In1(0) => axi_dma_0_s2mm_introut,
dout(1 downto 0) => xlconcat_0_dout(1 downto 0)
);
end STRUCTURE;
| mit | 370a6d4726a68e53e9a6c6c9ee7b9ef0 | 0.665694 | 2.771356 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/MuxPC.vhd | 2 | 1,577 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:27:06 10/20/2017
-- Design Name:
-- Module Name: MuxPC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxPC is
Port ( Disp30 : in STD_LOGIC_VECTOR (31 downto 0);
Disp22 : in STD_LOGIC_VECTOR (31 downto 0);
PC1 : in STD_LOGIC_VECTOR (31 downto 0);
Direccion : in STD_LOGIC_VECTOR (31 downto 0);
Selector : in STD_LOGIC_VECTOR (1 downto 0);
Direccion_Out : out STD_LOGIC_VECTOR (31 downto 0));
end MuxPC;
architecture Behavioral of MuxPC is
begin
process(Disp30, Disp22, PC1, Direccion, Selector)
begin
case Selector is
when "00" => Direccion_Out <= Disp30;
when "01" => Direccion_Out <= Disp22;
when "10" => Direccion_Out <= PC1;
when "11" => Direccion_Out <= Direccion;
when others => Direccion_Out <= PC1;
end case;
end process;
end Behavioral;
| gpl-3.0 | 32e784084f38e4eceffefb689d63e340 | 0.596703 | 3.745843 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Decode.vhd | 1 | 7,067 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:32:44 11/09/2017
-- Design Name:
-- Module Name: Decode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decode is
Port ( Instruction : in STD_LOGIC_VECTOR (31 downto 0);
posicionin : in STD_LOGIC_VECTOR (31 downto 0);
Regtomemin : in STD_LOGIC_VECTOR (31 downto 0);
cwpin : in STD_LOGIC;
iccin : in STD_LOGIC_VECTOR (3 downto 0);
Resetext : in STD_LOGIC;
ncwpout : out STD_LOGIC;
callout : out STD_LOGIC_VECTOR (31 downto 0);
ifout : out STD_LOGIC_VECTOR (31 downto 0);
rfsourceout : out STD_LOGIC_VECTOR (1 downto 0);
wrenmen : out STD_LOGIC;
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
pcsource : out STD_LOGIC_VECTOR (1 downto 0);
Cuentrada : out STD_LOGIC_VECTOR (1 downto 0);
aluop : out STD_LOGIC_VECTOR (5 downto 0);
a18 : out STD_LOGIC_VECTOR (31 downto 0);
crs1out : out STD_LOGIC_VECTOR (31 downto 0);
op2out : out STD_LOGIC_VECTOR (31 downto 0));
end Decode;
architecture Behavioral of Decode is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT UnidadControl
PORT(
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
op2 : in STD_LOGIC_VECTOR (2 downto 0);
cond : in STD_LOGIC_VECTOR (3 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
Reset : in STD_LOGIC;
rfDest : out STD_LOGIC;
rfSource : out STD_LOGIC_VECTOR (1 downto 0);
wrEnMem : out STD_LOGIC;
wrEnRF : out STD_LOGIC;
pcSource : out STD_LOGIC_VECTOR (1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
OUTSEU : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MUX32
PORT(
SEUIMM : in STD_LOGIC_VECTOR (31 downto 0);
CRS2 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : out STD_LOGIC_VECTOR (31 downto 0);
Instruction : in STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
wre : in STD_LOGIC;
cRd : out STD_LOGIC_VECTOR (31 downto 0);
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MuxRF
PORT(
Rd : in STD_LOGIC_VECTOR (5 downto 0);
O7 : in STD_LOGIC_VECTOR (5 downto 0);
RFDEST : in STD_LOGIC;
nRD : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT Windowsmanager
PORT(
cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0')
);
END COMPONENT;
COMPONENT SEU_22
PORT(
Imm_22 : in STD_LOGIC_VECTOR (21 downto 0);
Imm_32 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT SEU_30
PORT(
Imm_30 : in STD_LOGIC_VECTOR (29 downto 0);
Imm_32 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a10,a20,a21,a31: std_logic_vector(31 downto 0);
--nrs1,
signal a8,a9,a26,a27: std_logic_vector(5 downto 0);
signal a1: std_logic_vector(1 downto 0);
signal a11,a12: STD_LOGIC;
begin
ints_windowsmanager: Windowsmanager PORT MAP(
cwp =>cwpin,
rs1 =>Instruction(18 downto 14),
rs2 =>Instruction(4 downto 0),
rd =>Instruction(29 downto 25),
op =>Instruction(31 downto 30),
op3 =>Instruction(24 downto 19),
cwpout=> ncwpout,
rs1out=>a9,
rs2out=> a26,
rdout=> a8
);
ints_rf: RF PORT MAP(
rs1 => a9,
rs2 => a26,
rd => RD,
dwr => Regtomemin,
rst => Resetext,
wre => a11,
cRd => a18,
crs1 => crs1out,
crs2 => a20
);
ints_muxrf: MuxRF PORT MAP(
Rd => a8,
O7 => "001111",
RFDEST => a12,
nRD => a27
);
RDout <=a27;
ints_CU: UnidadControl PORT MAP(
op =>Instruction(31 downto 30),
op3 =>Instruction(24 downto 19),
op2 =>Instruction(24 downto 22),
cond =>Instruction(28 downto 25),
icc =>iccin,
Reset =>Resetext,
rfDest =>a12,
rfSource =>rfsourceout,
wrEnMem =>wrenmen,
wrEnRF =>a11,
pcSource =>a1,
AluOp =>aluop
);
Cuentrada<=a1;
pcsource<=a1;
ints_seu: SEU PORT MAP(
Instruction =>Instruction,
OUTSEU =>a21
);
ints_mux32: MUX32 PORT MAP(
SEUIMM => a21,
CRS2 => a20,
OPER2 => op2out,
Instruction => Instruction
);
ints_seu22: SEU_22 PORT MAP(
Imm_22 => Instruction(21 downto 0),
Imm_32 => a10
);
ints_sumdisp22: Sumador32bit PORT MAP(
Oper1 => a10,
Reset => Resetext,
Oper2 => posicionin,
Result => ifout
);
ints_seu30: SEU_30 PORT MAP(
Imm_30 => Instruction(29 downto 0),
Imm_32 => a31
);
ints_sumdisp30: Sumador32bit PORT MAP(
Oper1 => a31,
Reset => Resetext,
Oper2 => posicionin,
Result => callout
);
end Behavioral;
| gpl-3.0 | c6cee34fd0d8265018ef4d31598dab83 | 0.531909 | 3.605612 | false | false | false | false |
alemedeiros/flappy_vhdl | player/nbit_register.vhd | 1 | 948 | -- file: nbit_register.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- Solution to MC613 - Lab06.Q2.A
--
-- A n bit register
library ieee ;
use ieee.std_logic_1164.all ;
entity nbit_register is
generic ( n : integer := 8) ;
port ( x : in std_logic_vector (n-1 downto 0) ; -- Load input
y : out std_logic_vector (n-1 downto 0) ; -- Stored value
ld : in std_logic ; -- Load control bit
clr : in std_logic ; -- Clear control bit
clk : in std_logic -- Clock
) ;
end nbit_register ;
architecture arch of nbit_register is
begin
process (clk, clr)
begin
if clr = '1' -- Assincronous clear
then
y <= (others => '0') ;
elsif clk'event and clk = '1'
then
-- Rising edge
if ld = '1'
then
-- Load
y <= x ;
end if ;
end if ;
end process ;
end arch ;
| bsd-3-clause | 30a72adf316d0e655199a7fa667572e9 | 0.520042 | 3.56391 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/MurmurHash_BinarySearchImplementation.vhd | 1 | 6,867 | library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.numeric_bit.all;
use work.MurmurHashUtils.ALL;
entity BinarySearch_ComparingRow is
generic (
DATA_WIDTH: integer := 32;
ADDR_WIDTH: integer := 10
);
port(
clk : in std_logic;-- un solo reloj para ambos puertos de la BRAM
radio: std_logic_vector( (ADDR_WIDTH-1) downto 0 );
dataToCompare : in std_logic_vector((DATA_WIDTH-1) downto 0);
operationID : in std_logic_vector((DATA_WIDTH-1) downto 0);
previousIndex : in std_logic_vector( (ADDR_WIDTH-1) downto 0 );
compare : in std_logic;--El dato actual se debe comparar
previousResult : in std_logic;--El resultado es encontrado'1' o no
porta_wr : in std_logic;
porta_waddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
porta_din : in std_logic_vector( (DATA_WIDTH-1) downto 0);
--valores de saldia de esta columna
result : out std_logic;--El resultado es encontrado'1' o no
nextIndex : out std_logic_vector( (ADDR_WIDTH-1) downto 0);
compareFinished : out std_logic;--Resultado de una comparacion listo
result_operationID : out std_logic_vector((DATA_WIDTH-1) downto 0);
dataCompared : out std_logic_vector((DATA_WIDTH-1) downto 0);
--DEBUG SIGNALS
valorLeido_dbg : out ieee.numeric_std.unsigned( (DATA_WIDTH-1) downto 0)
);
end entity BinarySearch_ComparingRow;
architecture Normal of BinarySearch_ComparingRow is
signal actualValue : std_logic_vector( (DATA_WIDTH-1) downto 0);
signal porta_rd : std_logic;
signal porta_raddr : std_logic_vector( (ADDR_WIDTH-1) downto 0);
signal portb_rd : std_logic;
signal portb_addr : std_logic_vector( (ADDR_WIDTH-1) downto 0);
signal portb_dout : std_logic_vector( (DATA_WIDTH-1) downto 0);
signal valorAComparar : ieee.numeric_std.unsigned( (DATA_WIDTH-1) downto 0);
signal compareResultTuple : std_logic_vector(1 downto 0);--bit '1' indica mayor, bit '0' indica menor
signal valorLeido : ieee.numeric_std.unsigned( (DATA_WIDTH-1) downto 0);
signal resultado : std_logic;
signal result_temp : std_logic;
signal nextIndex_temp : std_logic_vector( (ADDR_WIDTH-1) downto 0);
signal compareFinished_temp : std_logic;
signal result_operationID_temp : std_logic_vector((DATA_WIDTH-1) downto 0);
signal dataCompared_temp : std_logic_vector((DATA_WIDTH-1) downto 0);
signal valorLeido_dbg_temp : ieee.numeric_std.unsigned( (DATA_WIDTH-1) downto 0);
signal dataToCompare_delayed : std_logic_vector((DATA_WIDTH-1) downto 0);
signal previousResult_delayed : std_logic;
signal previousIndex_delayed : std_logic_vector( (ADDR_WIDTH-1) downto 0 );
type memoryRead is record
operationID : std_logic_vector((DATA_WIDTH-1) downto 0);
compare : boolean;
end record memoryRead;
function boolean_to_std_logic(a: boolean) return std_logic is
begin
if a then
return('1');
else
return('0');
end if;
end function boolean_to_std_logic;
begin
valorLeido_dbg_temp <= valorLeido;
--puerto a es solo de escriitura
porta_rd <= '0';
porta_raddr <= (others => '-');
portb_rd <= compare;
portb_addr <= previousIndex;
--instanciar la memoria
memory: entity work.BinarySearchBRAM
generic map( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH )
port map (
clk => clk,
porta_wr => porta_wr,
porta_waddr => porta_waddr,
porta_din => porta_din,
porta_rd => porta_rd,
porta_raddr => porta_raddr,
porta_dout => open,
portb_rd => portb_rd,
portb_addr => portb_addr,
portb_dout => portb_dout
);
--GENERAR LOS VALORES CORRECTOS DE SALIDA
delay_dataToCompare : process ( clk, compare, dataToCompare ) begin
if rising_edge(clk) then
if(compare = '1') then
dataToCompare_delayed <= dataToCompare;
previousResult_delayed <= previousResult;
previousIndex_delayed <= previousIndex;
end if;
end if;
end process delay_dataToCompare;
valorLeido <= ieee.numeric_std.unsigned(portb_dout);
valorAComparar <= ieee.numeric_std.unsigned(dataToCompare_delayed);
resultado <= boolean_to_std_logic(valorAComparar = valorLeido);
result_temp <= previousResult_delayed or resultado;
compareResultTuple(1) <= boolean_to_std_logic(valorAComparar > valorLeido);
compareResultTuple(0) <= boolean_to_std_logic(valorAComparar < valorLeido);
generarNuevoIndice: process(compareResultTuple, previousIndex_delayed, radio, previousResult_delayed)
variable searchRadio : std_logic_vector( (ADDR_WIDTH-1) downto 0) ;
begin
searchRadio := radio( (ADDR_WIDTH-1) downto 0 );
if ( previousResult_delayed= '1' ) then
nextIndex_temp<= previousIndex_delayed;
else
case compareResultTuple is
when "10" =>
nextIndex_temp<= previousIndex_delayed+searchRadio;
when "01" =>
nextIndex_temp<= previousIndex_delayed-searchRadio;
when others =>
nextIndex_temp<= previousIndex_delayed;
end case;
end if ;
end process generarNuevoIndice;
validarSalida : process ( clk, previousIndex, compare, dataToCompare, operationID ) begin
if rising_edge(clk) then
compareFinished_temp <= compare;
result_operationID_temp <= operationID;
dataCompared_temp <= dataToCompare;
end if;
end process validarSalida;
lastStage : process ( clk, result_temp, nextIndex_temp, compareFinished_temp, result_operationID_temp, dataCompared_temp, valorLeido_dbg_temp) begin
if rising_edge(clk) then
if (compareFinished_temp = '1') then
result <= result_temp;
nextIndex <= nextIndex_temp;
result_operationID <= result_operationID_temp;
dataCompared <= dataCompared_temp;
valorLeido_dbg <= valorLeido_dbg_temp;
end if;
compareFinished <= compareFinished_temp;
end if;
end process lastStage;
end architecture Normal;
| bsd-3-clause | 7ce9efff36c0b2a4de0a54a8d0c3728a | 0.599243 | 4.08264 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/system_stub.vhd | 3 | 5,836 | -------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0)
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0)
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
axi_dispctrl_0_HSYNC_O_pin => axi_dispctrl_0_HSYNC_O_pin,
axi_dispctrl_0_VSYNC_O_pin => axi_dispctrl_0_VSYNC_O_pin,
axi_dispctrl_0_PXL_CLK_O_pin => axi_dispctrl_0_PXL_CLK_O_pin,
axi_dispctrl_0_DE_O_pin => axi_dispctrl_0_DE_O_pin,
axi_dispctrl_0_RED_O_pin => axi_dispctrl_0_RED_O_pin,
axi_dispctrl_0_GREEN_O_pin => axi_dispctrl_0_GREEN_O_pin,
axi_dispctrl_0_BLUE_O_pin => axi_dispctrl_0_BLUE_O_pin
);
end architecture STRUCTURE;
| bsd-3-clause | e398565dd18c679af890de41929261d7 | 0.672892 | 3.006698 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Memory.vhd | 1 | 1,728 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:31:32 11/11/2017
-- Design Name:
-- Module Name: Memory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Memory is
Port ( a18in : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
datatomenout : out STD_LOGIC_VECTOR (31 downto 0);
wrenmenin : in STD_LOGIC;
Resetext : in STD_LOGIC;
aluresultout : out STD_LOGIC_VECTOR (31 downto 0));
end Memory;
architecture Behavioral of Memory is
COMPONENT DataMemory
PORT(
cRD : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
WRENMEM : in STD_LOGIC;
Reset : in STD_LOGIC;
DataMem : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
begin ints_datamemmory: DataMemory PORT MAP(
cRD => a18in,
AluResult => aluresultin,
WRENMEM => wrenmenin,
Reset => Resetext,
DataMem => datatomenout
);
aluresultout<=aluresultin;
end Behavioral;
| gpl-3.0 | e1d5a1a57316de7f71fd3b58d029936c | 0.575231 | 4.173913 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif.vhd | 3 | 5,736 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| bsd-3-clause | d115b8714192dcb9c353f3da8180ebf8 | 0.585251 | 4.02244 | false | false | false | false |
fumyuun/tasty | src/js_generator.vhd | 1 | 1,889 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity js_generator is
port (
clk_i : in std_logic;
rst_i : in std_logic;
pause_i : in std_logic;
pc_o : out std_logic_vector(15 downto 0);
js_o : out snes_js_btn_r
);
end entity js_generator;
architecture behavioral of js_generator is
signal address_s : std_logic_vector(15 downto 0) := x"0000";
signal address_next_s : std_logic_vector(15 downto 0);
signal data_s : std_logic_vector(15 downto 0);
signal received_r : std_logic;
signal received_next_r : std_logic;
begin
rom16_0: entity work.rom16
port map (
clk_i => clk_i,
address_i => address_s,
data_o => data_s
);
pc_o <= address_s;
clock_proc: process (clk_i, rst_i)
begin
if rst_i = '1' then
received_r <= '0';
address_s <= x"0000";
elsif rising_edge(clk_i) then
address_s <= address_next_s;
received_r <= received_next_r;
end if;
end process;
comb_proc: process(pause_i, address_s)
begin
address_next_s <= address_s;
received_next_r <= received_r;
if pause_i = '0' and received_r = '1' then
address_next_s <= std_logic_vector(unsigned(address_s) + 1);
received_next_r <= '0';
elsif pause_i = '1' and received_r = '0' then
received_next_r <= '1';
end if;
end process;
js_o.b <= data_s(0);
js_o.y <= data_s(1);
js_o.sel <= data_s(2);
js_o.start <= data_s(3);
js_o.up <= data_s(4);
js_o.down <= data_s(5);
js_o.left <= data_s(6);
js_o.right <= data_s(7);
js_o.a <= data_s(8);
js_o.x <= data_s(9);
js_o.l <= data_s(10);
js_o.r <= data_s(11);
end architecture;
| mit | 3eb3eff2e56cf6f21a3280b01cd4cab9 | 0.528322 | 2.937792 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/pcores/axi_dispctrl_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 24,604 | --------------------------------------------------------------------------------
--
-- File:
-- user_logic.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author(s):
-- Sam Bobrowicz
-- Karol Gugala <[email protected]>
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_TDATA_WIDTH : integer := 32; --must be 32
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 13;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
COMPONENT mmcme2_drp
GENERIC(
DIV_F : integer
);
PORT(
SEN : IN std_logic;
SCLK : IN std_logic;
RST : IN std_logic;
S1_CLKOUT0 : IN std_logic_vector(35 downto 0);
S1_CLKFBOUT : IN std_logic_vector(35 downto 0);
S1_DIVCLK : IN std_logic_vector(13 downto 0);
S1_LOCK : IN std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : IN std_logic_vector(9 downto 0);
REF_CLK : IN std_logic;
SRDY : OUT std_logic;
PXL_CLK : OUT std_logic;
PXL_CLK_INV : OUT std_logic;
CLKFBOUT_O : OUT std_logic;
CLKFBOUT_I : IN std_logic;
LOCKED_O : OUT std_logic
);
END COMPONENT;
COMPONENT vdma_to_vga
GENERIC(
C_RED_WIDTH : integer;
C_GREEN_WIDTH : integer;
C_BLUE_WIDTH : integer;
C_S_AXIS_TDATA_WIDTH : integer
);
PORT(
LOCKED_I : IN std_logic;
ENABLE_I : IN std_logic;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
USR_WIDTH_I : IN std_logic_vector(11 downto 0);
USR_HEIGHT_I : IN std_logic_vector(11 downto 0);
USR_HPS_I : IN std_logic_vector(11 downto 0);
USR_HPE_I : IN std_logic_vector(11 downto 0);
USR_HPOL_I : IN std_logic;
USR_HMAX_I : IN std_logic_vector(11 downto 0);
USR_VPS_I : IN std_logic_vector(11 downto 0);
USR_VPE_I : IN std_logic_vector(11 downto 0);
USR_VPOL_I : IN std_logic;
USR_VMAX_I : IN std_logic_vector(11 downto 0);
RUNNING_O : OUT std_logic;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR (C_RED_WIDTH-1 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (C_GREEN_WIDTH-1 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (C_BLUE_WIDTH-1 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0)
);
END COMPONENT;
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal mmcm_clk_inv : std_logic;
signal pxl_clk : std_logic;
signal pxl_clk_inv : std_logic;
signal pxl_clk_inv5x : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal vga_running : std_logic;
signal clk_state : CLK_STATE_TYPE := RESET;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal CTRL_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal STAT_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal FRAME_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal HPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM1_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal VPARAM2_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_O_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FB_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FRAC_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_DIV_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_LOCK_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal CLK_FLTR_REG : std_logic_vector(C_SLV_DWIDTH-1 downto 0) := (others => '0');
signal slv_reg_write_sel : std_logic_vector(12 downto 0);
signal slv_reg_read_sel : std_logic_vector(12 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFG_inst: BUFG port map(
O => pxl_clk_inv5x, -- 1-bit output: Clock output port
I => mmcm_clk_inv -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
BUFR_inst_inv : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output port
CE => enable_reg, -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => pxl_clk_inv5x -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
ENABLE_O <= enable_reg;
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
BUFG_inst_inv : BUFG
port map (
O => pxl_clk_inv, -- 1-bit output: Clock output
I => mmcm_clk_inv -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => Bus2IP_Clk,
RST => not(Bus2IP_Resetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
PXL_CLK_INV => mmcm_clk_inv,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
pxl_clk_mux: BUFGMUX
port map (
O => PXL_CLK_O, -- 1-bit output: Clock output
I0 => pxl_clk, -- 1-bit input: Clock input (S=0)
I1 => pxl_clk_inv, -- 1-bit input: Clock input (S=1)
S => CTRL_REG(1) -- 1-bit input: Clock select
);
VDMA_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED => --This state ensures that the initial SRDY pulse doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
GENERIC MAP(
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => pxl_clk,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
DEBUG_O => DEBUG_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
process (Bus2IP_Clk)
begin
if (rising_edge(Bus2IP_Clk)) then
if (Bus2IP_Resetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(12 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(12 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
CTRL_REG <= (others => '0');
--STAT_REG <= (others => '0');
FRAME_REG <= (others => '0');
HPARAM1_REG <= (others => '0');
HPARAM2_REG <= (others => '0');
VPARAM1_REG <= (others => '0');
VPARAM2_REG <= (others => '0');
CLK_O_REG <= (others => '0');
CLK_FB_REG <= (others => '0');
CLK_FRAC_REG <= (others => '0');
CLK_DIV_REG <= (others => '0');
CLK_LOCK_REG <= (others => '0');
CLK_FLTR_REG <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CTRL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--***Status register is read only***
-- when "0100000000000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- STAT_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "0010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
FRAME_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
HPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM1_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
VPARAM2_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_O_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FB_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FRAC_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_DIV_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_LOCK_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "0000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
CLK_FLTR_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, CTRL_REG, STAT_REG, FRAME_REG, HPARAM1_REG, HPARAM2_REG, VPARAM1_REG, VPARAM2_REG, CLK_O_REG, CLK_FB_REG, CLK_FRAC_REG, CLK_DIV_REG, CLK_LOCK_REG, CLK_FLTR_REG ) is
begin
case slv_reg_read_sel is
when "1000000000000" => slv_ip2bus_data <= CTRL_REG;
when "0100000000000" => slv_ip2bus_data <= STAT_REG;
when "0010000000000" => slv_ip2bus_data <= FRAME_REG;
when "0001000000000" => slv_ip2bus_data <= HPARAM1_REG;
when "0000100000000" => slv_ip2bus_data <= HPARAM2_REG;
when "0000010000000" => slv_ip2bus_data <= VPARAM1_REG;
when "0000001000000" => slv_ip2bus_data <= VPARAM2_REG;
when "0000000100000" => slv_ip2bus_data <= CLK_O_REG;
when "0000000010000" => slv_ip2bus_data <= CLK_FB_REG;
when "0000000001000" => slv_ip2bus_data <= CLK_FRAC_REG;
when "0000000000100" => slv_ip2bus_data <= CLK_DIV_REG;
when "0000000000010" => slv_ip2bus_data <= CLK_LOCK_REG;
when "0000000000001" => slv_ip2bus_data <= CLK_FLTR_REG;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| bsd-3-clause | 36c85c6f6fba3ce11cd93769d1bed6b6 | 0.595025 | 2.995738 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif.vhd | 4 | 5,686 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| bsd-3-clause | 2e31fa51eed018688de83c720accca98 | 0.582483 | 4.015537 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_mm2s_mngr.vhd | 1 | 51,891 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
attribute mark_debug of mm2s_cmnd_data : signal is "true";
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
attribute mark_debug of mm2s_interr : signal is "true";
attribute mark_debug of mm2s_slverr : signal is "true";
attribute mark_debug of mm2s_decerr : signal is "true";
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
| mit | 3774657729d61c6fdc6fa43e7a3f16da | 0.407913 | 4.220153 | false | false | false | false |
loetlab-jena/das-atv | hdl/syn/ip/clkctrl.vhd | 1 | 9,846 | -- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
-- ============================================================
-- File Name: clkctrl.vhd
-- Megafunction Name(s):
-- altclkctrl
--
-- Simulation Library Files(s):
-- cycloneive
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone IV E" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="ON" clkselect ena inclk outclk
--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ VERSION_END
LIBRARY cycloneive;
USE cycloneive.all;
--synthesis_resources = clkctrl 1 reg 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clkctrl_altclkctrl_9gi IS
PORT
(
clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
ena : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
outclk : OUT STD_LOGIC
);
END clkctrl_altclkctrl_9gi;
ARCHITECTURE RTL OF clkctrl_altclkctrl_9gi IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
SIGNAL ena_reg : STD_LOGIC
-- synopsys translate_off
:= '1'
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF ena_reg : SIGNAL IS "POWER_UP_LEVEL=HIGH";
SIGNAL wire_ena_reg_w_lg_q6w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL select_reg : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF select_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_select_reg_w_q_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_select_reg_w_q_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_clkctrl1_w_lg_outclk5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_clkctrl1_clkselect : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_clkctrl1_outclk : STD_LOGIC;
SIGNAL wire_w_lg_w_select_enable_wire_range15w20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_clkselect_wire_range13w14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_clkselect_wire_range18w19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL clkselect_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL inclk_wire : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL select_enable_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_clkselect_wire_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_clkselect_wire_range3w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_clkselect_wire_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_select_enable_wire_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT cycloneive_clkctrl
GENERIC
(
clock_type : STRING;
ena_register_mode : STRING := "falling edge";
lpm_type : STRING := "cycloneive_clkctrl"
);
PORT
(
clkselect : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ena : IN STD_LOGIC;
inclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
outclk : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
wire_vcc <= '1';
wire_w_lg_w_select_enable_wire_range15w20w(0) <= wire_w_select_enable_wire_range15w(0) OR wire_w_lg_w_clkselect_wire_range18w19w(0);
wire_w_lg_w_clkselect_wire_range13w14w(0) <= wire_w_clkselect_wire_range13w(0) XOR wire_select_reg_w_q_range12w(0);
wire_w_lg_w_clkselect_wire_range18w19w(0) <= wire_w_clkselect_wire_range18w(0) XOR wire_select_reg_w_q_range17w(0);
clkselect_wire <= ( clkselect);
inclk_wire <= ( inclk);
outclk <= (wire_clkctrl1_outclk AND ena_reg);
select_enable_wire <= ( wire_w_lg_w_select_enable_wire_range15w20w & wire_w_lg_w_clkselect_wire_range13w14w);
wire_w_clkselect_wire_range13w(0) <= clkselect_wire(0);
wire_w_clkselect_wire_range3w <= clkselect_wire(1 DOWNTO 0);
wire_w_clkselect_wire_range18w(0) <= clkselect_wire(1);
wire_w_select_enable_wire_range15w(0) <= select_enable_wire(0);
PROCESS (wire_clkctrl1_outclk)
BEGIN
IF (wire_clkctrl1_outclk = '0' AND wire_clkctrl1_outclk'event) THEN ena_reg <= (ena AND (NOT select_enable_wire(1)));
END IF;
END PROCESS;
PROCESS (wire_clkctrl1_outclk)
BEGIN
IF (wire_clkctrl1_outclk = '0' AND wire_clkctrl1_outclk'event) THEN
IF (ena_reg = '0') THEN select_reg <= wire_w_clkselect_wire_range3w;
END IF;
END IF;
END PROCESS;
wire_select_reg_w_q_range12w(0) <= select_reg(0);
wire_select_reg_w_q_range17w(0) <= select_reg(1);
wire_clkctrl1_w_lg_outclk5w(0) <= NOT wire_clkctrl1_outclk;
wire_clkctrl1_clkselect <= ( select_reg);
clkctrl1 : cycloneive_clkctrl
GENERIC MAP (
clock_type => "Global Clock"
)
PORT MAP (
clkselect => wire_clkctrl1_clkselect,
ena => wire_vcc,
inclk => inclk_wire,
outclk => wire_clkctrl1_outclk
);
END RTL; --clkctrl_altclkctrl_9gi
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clkctrl IS
PORT
(
clkselect : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
inclk0x : IN STD_LOGIC ;
inclk1x : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
END clkctrl;
ARCHITECTURE RTL OF clkctrl IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "altclkctrl";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "ena_register_mode=falling edge;intended_device_family=Cyclone IV E;use_glitch_free_switch_over_implementation=ON;clock_type=Global Clock;";
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7_bv : BIT_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT clkctrl_altclkctrl_9gi
PORT (
clkselect : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ena : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
outclk : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire3_bv(0 DOWNTO 0) <= "0";
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
sub_wire7_bv(1 DOWNTO 0) <= "00";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire6 <= inclk1x;
outclk <= sub_wire0;
sub_wire1 <= clkselect;
sub_wire2 <= sub_wire3(0 DOWNTO 0) & sub_wire1;
sub_wire4 <= inclk0x;
sub_wire5 <= sub_wire7(1 DOWNTO 0) & sub_wire6 & sub_wire4;
clkctrl_altclkctrl_9gi_component : clkctrl_altclkctrl_9gi
PORT MAP (
clkselect => sub_wire2,
ena => ena,
inclk => sub_wire5,
outclk => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "2"
-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "falling edge"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "ON"
-- Retrieval info: CONSTANT: clock_type STRING "Global Clock"
-- Retrieval info: USED_PORT: clkselect 0 0 0 0 INPUT GND "clkselect"
-- Retrieval info: USED_PORT: ena 0 0 0 0 INPUT VCC "ena"
-- Retrieval info: USED_PORT: inclk0x 0 0 0 0 INPUT NODEFVAL "inclk0x"
-- Retrieval info: USED_PORT: inclk1x 0 0 0 0 INPUT NODEFVAL "inclk1x"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @clkselect 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @clkselect 0 0 1 0 clkselect 0 0 0 0
-- Retrieval info: CONNECT: @ena 0 0 0 0 ena 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 2 2 GND 0 0 2 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0x 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1x 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clkctrl_inst.vhd TRUE
-- Retrieval info: LIB_FILE: cycloneive
| gpl-2.0 | a0815b8c65484f3a28e659675dc12834 | 0.68312 | 3.087488 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif.vhd | 4 | 5,686 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| bsd-3-clause | 706151d99f429ebf7385379e6f7d8b3d | 0.582483 | 4.015537 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/example_design/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes.vhd | 3 | 5,073 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes;
architecture xilinx of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-3-clause | 449482868df56652aca62cc8dd791834 | 0.542874 | 4.767857 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/tbexecute.vhd | 1 | 4,515 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:17:37 11/11/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/aaaaaaaaaaa/tbexecute.vhd
-- Project Name: aaaaaaaaaaa
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Execute
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbexecute IS
END tbexecute;
ARCHITECTURE behavior OF tbexecute IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Execute
PORT(
callin : IN std_logic_vector(31 downto 0);
ifin : IN std_logic_vector(31 downto 0);
pcsourcein : IN std_logic_vector(1 downto 0);
aluopin : IN std_logic_vector(5 downto 0);
op1in : IN std_logic_vector(31 downto 0);
op2in : IN std_logic_vector(31 downto 0);
cwp : OUT std_logic;
ncwp : IN std_logic;
icc : OUT std_logic_vector(3 downto 0);
nextpc : OUT std_logic_vector(31 downto 0);
aluresult : OUT std_logic_vector(31 downto 0);
Clkinext : IN std_logic;
Resetext : IN std_logic
);
END COMPONENT;
--Inputs
signal callin : std_logic_vector(31 downto 0) := (others => '0');
signal ifin : std_logic_vector(31 downto 0) := (others => '0');
signal pcsourcein : std_logic_vector(1 downto 0) := (others => '0');
signal aluopin : std_logic_vector(5 downto 0) := (others => '0');
signal op1in : std_logic_vector(31 downto 0) := (others => '0');
signal op2in : std_logic_vector(31 downto 0) := (others => '0');
signal ncwp : std_logic := '0';
signal Clkinext : std_logic := '0';
signal Resetext : std_logic := '0';
--Outputs
signal cwp : std_logic;
signal icc : std_logic_vector(3 downto 0);
signal nextpc : std_logic_vector(31 downto 0);
signal aluresult : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clkinext_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Execute PORT MAP (
callin => callin,
ifin => ifin,
pcsourcein => pcsourcein,
aluopin => aluopin,
op1in => op1in,
op2in => op2in,
cwp => cwp,
ncwp => ncwp,
icc => icc,
nextpc => nextpc,
aluresult => aluresult,
Clkinext => Clkinext,
Resetext => Resetext
);
-- Clock process definitions
Clkinext_process :process
begin
Clkinext <= '0';
wait for Clkinext_period/2;
Clkinext <= '1';
wait for Clkinext_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
callin <= "00000000000000000000000000000101";
ifin <= "00000000000000000000000000000101";
pcsourcein <= "01";
aluopin <= "000010";
op1in <= "00000000000000000000000000000101";
op2in <= "00000000000000000000000000000101";
ncwp <= '0';
Resetext <= '1';
wait for 100 ns;
callin <= "00000000000000000000000000000101";
ifin <= "00000000000000000000000000000101";
pcsourcein <= "01";
aluopin <= "000010";
op1in <= "00000000000000000000000000000101";
op2in <= "00000000000000000000000000000101";
ncwp <= '0';
Resetext <= '0';
wait for 100 ns;
callin <= "00000000000000000000000000000101";
ifin <= "00000000000000000000000000000101";
pcsourcein <= "00";
aluopin <= "000000";
op1in <= "00000000000000000000000000000101";
op2in <= "00000000000000000000000000000101";
ncwp <= '0';
Resetext <= '0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 5dc3b61ef19e54d32cdb1f7f44d1b521 | 0.588483 | 4.23546 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/vhdl/tri_intersect_fdiv_32ns_32ns_32_30.vhd | 4 | 3,373 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity tri_intersect_fdiv_32ns_32ns_32_30 is
generic (
ID : integer := 50;
NUM_STAGE : integer := 30;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of tri_intersect_fdiv_32ns_32ns_32_30 is
--------------------- Component ---------------------
component tri_intersect_ap_fdiv_28_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
tri_intersect_ap_fdiv_28_no_dsp_32_u : component tri_intersect_ap_fdiv_28_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | 95bd3bd51065643b19d7539e7bcd2784 | 0.489179 | 3.502596 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/TB3_No4ByteAligned.vhd | 1 | 11,379 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.11.2013 00:20:28
-- Design Name:
-- Module Name: TestBench1_FourByteAlignedTests - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: Esta prueba solo realzia una unica prueba al modulo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB3_No4ByteAligned is
end TB3_No4ByteAligned;
architecture Behavioral of TB3_No4ByteAligned is
-- Signals to evaluate
--ENTRADAS
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
signal clk : std_logic;
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal dataStepA_dbg : std_logic_vector(31 downto 0);
signal dataStepA_ID_dbg : std_logic_vector(31 downto 0);
signal dataStepB_dbg : std_logic_vector(31 downto 0);
signal dataStepB_ID_dbg : std_logic_vector(31 downto 0);
signal dataStepC_dbg : std_logic_vector(31 downto 0);
signal dataStepC_ID_dbg : std_logic_vector(31 downto 0);
signal dataStepD_dbg : std_logic_vector(31 downto 0);
signal dataStepD_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
type resultReference is array (0 to 13) of std_logic_vector(31 downto 0);
constant resultsBank : resultReference := ( x"6b6cf591", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
constant opsIDs : resultReference := ( x"6b6cf591", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
signal resultsBankCounter : integer := 0;
signal errorDetected : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
--Inicializar el banco de resultados
verification: process (clk, resultReady, result, resultsBankCounter)
begin
if( rising_edge(clk) ) then
--if( resultsBankCounter = resultReference'length ) then
if( resultsBankCounter = 1 ) then
errorDetected <= '0';
else
if (resultReady = '1') then
if( (resultsBank(resultsBankCounter)/=result) or (resultID/=opsIDs(resultsBankCounter)) ) then
errorDetected <= '1';
else
errorDetected <= '0';
end if;
resultsBankCounter <= resultsBankCounter+1;
else
errorDetected <= '0';
end if;
end if;
end if;
end process verification;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
dataStepA_dbg => dataStepA_dbg,
dataStepB_dbg => dataStepB_dbg,
dataStepC_dbg => dataStepC_dbg,
dataStepD_dbg => dataStepD_dbg,
dataStepA_ID_dbg => dataStepA_ID_dbg,
dataStepB_ID_dbg => dataStepB_ID_dbg,
dataStepC_ID_dbg => dataStepC_ID_dbg,
dataStepD_ID_dbg => dataStepD_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
blockLength <= "00";
--operationID <= "0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101";
operationID <= opsIDs(0);
--PRUEBA 1, HASH DEL VECTOR 0
--Se einicializan los datos y
inputBlock <= x"000000de";
start <= '1';
finalBlock <= '1';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
readInput <= '0';
wait for clk_period;
--hacer que realize una lectura de datos
readInput <= '1';
wait for clk_period;
start <= '0';--que ya no lea otro dato
readInput <= '0';
wait for clk_period;
-- --Prueba 2 hash del vector 1
-- blockLength <= "11";
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0001";
-- operationID <= opsIDs(1);
-- finalBlock <= '1';
-- seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- start <= '1';
-- readInput <= '0';
-- wait for clk_period;
-- --hacer que realize una lectura de datos
-- readInput <= '1';
-- wait for clk_period;
-- start <= '0';--que ya no lea otro dato
-- readInput <= '0';
-- wait for clk_period;
-- wait for clk_period;
-- --PROBAR QUE AMBAS SALIDAS CONSECUTIVAS SE REALIZEN DE FORMA CONSECUTIVA
-- start <= '1';
-- finalBlock <= '1';
-- readInput <= '1';
-- seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- --Probando valroes consecutivos
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(2);
-- wait for clk_period;
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0001";
-- operationID <= opsIDs(3);
-- wait for clk_period;
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0010";
-- operationID <= opsIDs(4);
-- wait for clk_period;
-- inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0011";
-- operationID <= opsIDs(5);
-- wait for clk_period;
-- readInput <= '0';
-- wait for clk_period;
-- readInput <= '1';
-- inputBlock <= "1000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(6);
-- wait for clk_period;
-- inputBlock <= "0100"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(7);
-- wait for clk_period;
-- inputBlock <= "1100"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(8);
-- wait for clk_period;
-- inputBlock <= "0010"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
-- operationID <= opsIDs(9);
-- wait for clk_period;
-- inputBlock <= "1111"&"1111"&"1111"&"1111"&"1111"&"1111"&"1111"&"1111";
-- operationID <= opsIDs(10);
-- wait for clk_period;
-- inputBlock <= "1111"&"0000"&"1111"&"0000"&"1111"&"0000"&"1111"&"0000";
-- operationID <= opsIDs(11);
-- wait for clk_period;
-- inputBlock <= "0000"&"1111"&"0000"&"1111"&"0000"&"1111"&"0000"&"1111";
-- operationID <= opsIDs(12);
-- wait for clk_period;
-- inputBlock <= "1100"&"1100"&"1100"&"1100"&"1100"&"1100"&"1100"&"1100";
-- operationID <= opsIDs(13);
-- wait for clk_period;
readInput <= '0';
wait for clk_period;
wait;
end process stim_proc;
end Behavioral;
| bsd-3-clause | f20cebaeb970d7db6b074523a46ab5d4 | 0.539239 | 3.933287 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_mm2s_cmdsts_if.vhd | 1 | 15,453 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
| mit | 2d76a384bf836c9c7b539bce9651e1c7 | 0.443215 | 4.391304 | false | false | false | false |
loetlab-jena/das-atv | hdl/syn/ip/pll.vhd | 1 | 15,669 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
clkswitch : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
inclk1 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
inclk1_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
primary_clock : STRING;
self_reset_on_loss_lock : STRING;
switch_over_type : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
clkswitch : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5 <= inclk1;
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5 & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
inclk1_input_frequency => 37037,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_USED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_USED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
primary_clock => "inclk0",
self_reset_on_loss_lock => "ON",
switch_over_type => "MANUAL",
width_clock => 5
)
PORT MAP (
clkswitch => clkswitch,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "1"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "7"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | d0132dbe7eeac344ecd7bbdd5b0cf191 | 0.698258 | 3.352375 | false | false | false | false |
VisionistInc/advent-of-code-2016 | rawjoe/18/sol_tb.vhdl | 1 | 1,514 | library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
use std.textio.all;
-- A testbench has no ports.
entity sol_tb is
end sol_tb;
architecture behav of sol_tb is
-- Declaration of the component that will be instantiated.
component sol
port ( clk : in std_logic;
rst : in std_logic;
rows : out integer;
safe : out integer);
end component;
-- Specifies which entity is bound with the component.
for sol_0: sol use entity work.sol;
signal clk : std_logic;
signal rst : std_logic;
signal rows : integer;
signal safe : integer;
begin
-- Component instantiation.
sol_0: sol port map (clk => clk, rst => rst, rows => rows, safe => safe);
-- This process does the real job.
process
begin
rst <= '1';
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
rst <= '0';
L1: loop
if rows = 40 then
report "After 40 rows numSafe = " & integer'image(safe);
end if;
if rows = 400000 then
report "After 400000 rows numSafe = " & integer'image(safe);
exit L1;
end if;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end loop;
assert false report "end of test" severity note;
-- Wait forever; this will finish the simulation.
wait;
end process;
end behav;
| mit | 36055472d918a94ed08f39caee36ad62 | 0.537649 | 3.882051 | false | false | false | false |
davewebb8211/ghdl | libraries/vital95/vital_primitives_body.vhdl | 6 | 235,006 | -------------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : VITAL
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #204 - glitch detection prior to OutputMap
-- ----------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
PACKAGE BODY VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Default values for Primitives
-- ------------------------------------------------------------------------
-- default values for delay parameters
CONSTANT VitalDefDelay01 : VitalDelayType01 := VitalZeroDelay01;
CONSTANT VitalDefDelay01Z : VitalDelayType01Z := VitalZeroDelay01Z;
TYPE VitalTimeArray IS ARRAY (NATURAL RANGE <>) OF TIME;
-- default primitive model operation parameters
-- Glitch detection/reporting
TYPE VitalGlitchModeType IS ( MessagePlusX, MessageOnly, XOnly, NoGlitch);
CONSTANT PrimGlitchMode : VitalGlitchModeType := XOnly;
-- ------------------------------------------------------------------------
-- Local Type and Subtype Declarations
-- ------------------------------------------------------------------------
---------------------------------------------------------------------------
-- enumeration value representing the transition or level of the signal.
-- See function 'GetEdge'
---------------------------------------------------------------------------
TYPE EdgeType IS ( 'U', -- Uninitialized level
'X', -- Unknown level
'0', -- low level
'1', -- high level
'\', -- 1 to 0 falling edge
'/', -- 0 to 1 rising edge
'F', -- * to 0 falling edge
'R', -- * to 1 rising edge
'f', -- rising to X edge
'r', -- falling to X edge
'x', -- Unknown edge (ie U->X)
'V' -- Timing violation edge
);
TYPE EdgeArray IS ARRAY ( NATURAL RANGE <> ) OF EdgeType;
TYPE EdgeX1Table IS ARRAY ( EdgeType ) OF EdgeType;
TYPE EdgeX2Table IS ARRAY ( EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX3Table IS ARRAY ( EdgeType, EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX4Table IS ARRAY (EdgeType,EdgeType,EdgeType,EdgeType) OF EdgeType;
TYPE LogicToEdgeT IS ARRAY(std_ulogic, std_ulogic) OF EdgeType;
TYPE LogicToLevelT IS ARRAY(std_ulogic ) OF EdgeType;
TYPE GlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
CurrentValue : std_ulogic;
END RECORD;
TYPE GlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF GlitchDataType;
-- Enumerated type used in selection of output path delays
TYPE SchedType IS
RECORD
inp0 : TIME; -- time (abs) of output change due to input change to 0
inp1 : TIME; -- time (abs) of output change due to input change to 1
InpX : TIME; -- time (abs) of output change due to input change to X
Glch0 : TIME; -- time (abs) of output glitch due to input change to 0
Glch1 : TIME; -- time (abs) of output glitch due to input change to 0
END RECORD;
TYPE SchedArray IS ARRAY ( NATURAL RANGE <> ) OF SchedType;
CONSTANT DefSchedType : SchedType := (TIME'HIGH, TIME'HIGH, 0 ns,0 ns,0 ns);
CONSTANT DefSchedAnd : SchedType := (TIME'HIGH, 0 ns,0 ns, TIME'HIGH,0 ns);
-- Constrained array declarations (common sizes used by primitives)
SUBTYPE SchedArray2 IS SchedArray(1 DOWNTO 0);
SUBTYPE SchedArray3 IS SchedArray(2 DOWNTO 0);
SUBTYPE SchedArray4 IS SchedArray(3 DOWNTO 0);
SUBTYPE SchedArray8 IS SchedArray(7 DOWNTO 0);
SUBTYPE TimeArray2 IS VitalTimeArray(1 DOWNTO 0);
SUBTYPE TimeArray3 IS VitalTimeArray(2 DOWNTO 0);
SUBTYPE TimeArray4 IS VitalTimeArray(3 DOWNTO 0);
SUBTYPE TimeArray8 IS VitalTimeArray(7 DOWNTO 0);
SUBTYPE GlitchArray2 IS GlitchDataArrayType(1 DOWNTO 0);
SUBTYPE GlitchArray3 IS GlitchDataArrayType(2 DOWNTO 0);
SUBTYPE GlitchArray4 IS GlitchDataArrayType(3 DOWNTO 0);
SUBTYPE GlitchArray8 IS GlitchDataArrayType(7 DOWNTO 0);
SUBTYPE EdgeArray2 IS EdgeArray(1 DOWNTO 0);
SUBTYPE EdgeArray3 IS EdgeArray(2 DOWNTO 0);
SUBTYPE EdgeArray4 IS EdgeArray(3 DOWNTO 0);
SUBTYPE EdgeArray8 IS EdgeArray(7 DOWNTO 0);
CONSTANT DefSchedArray2 : SchedArray2 :=
(OTHERS=> (0 ns, 0 ns, 0 ns, 0 ns, 0 ns));
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT InitialEdge : LogicToLevelT := (
'1'|'H' => 'R',
'0'|'L' => 'F',
OTHERS => 'x'
);
CONSTANT LogicToEdge : LogicToEdgeT := ( -- previous, current
-- old \ new: U X 0 1 Z W L H -
'U' => ( 'U', 'x', 'F', 'R', 'x', 'x', 'F', 'R', 'x' ),
'X' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'0' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'1' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'Z' => ( 'x', 'X', 'F', 'R', 'X', 'x', 'F', 'R', 'x' ),
'W' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'L' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'H' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'-' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' )
);
CONSTANT LogicToLevel : LogicToLevelT := (
'1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X'
);
-- -----------------------------------
-- 3-state logic tables
-- -----------------------------------
CONSTANT BufIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT BufIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
TYPE To_StateCharType IS ARRAY (VitalStateSymbolType) OF CHARACTER;
CONSTANT To_StateChar : To_StateCharType :=
( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v',
'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S' );
TYPE To_TruthCharType IS ARRAY (VitalTruthSymbolType) OF CHARACTER;
CONSTANT To_TruthChar : To_TruthCharType :=
( 'X', '0', '1', '-', 'B', 'Z' );
TYPE TruthTableOutMapType IS ARRAY (VitalTruthSymbolType) OF std_ulogic;
CONSTANT TruthTableOutMap : TruthTableOutMapType :=
-- 'X', '0', '1', '-', 'B', 'Z'
( 'X', '0', '1', 'X', '-', 'Z' );
TYPE StateTableOutMapType IS ARRAY (VitalStateSymbolType) OF std_ulogic;
-- does conversion to X01Z or '-' if invalid
CONSTANT StateTableOutMap : StateTableOutMapType :=
-- '/' '\' 'P' 'N' 'r' 'f' 'p' 'n' 'R' 'F' '^' 'v'
-- 'E' 'A' 'D' '*' 'X' '0' '1' '-' 'B' 'Z' 'S'
( '-','-','-','-','-','-','-','-','-','-','-','-',
'-','-','-','-','X','0','1','X','-','Z','W');
-- ------------------------------------------------------------------------
TYPE ValidTruthTableInputType IS ARRAY (VitalTruthSymbolType) OF BOOLEAN;
-- checks if a symbol IS valid for the stimulus portion of a truth table
CONSTANT ValidTruthTableInput : ValidTruthTableInputType :=
-- 'X' '0' '1' '-' 'B' 'Z'
( TRUE, TRUE, TRUE, TRUE, TRUE, FALSE );
TYPE TruthTableMatchType IS ARRAY (X01, VitalTruthSymbolType) OF BOOLEAN;
-- checks if an input matches th corresponding truth table symbol
-- use: TruthTableMatch(input_converted_to_X01, truth_table_stimulus_symbol)
CONSTANT TruthTableMatch : TruthTableMatchType := (
-- X, 0, 1, - B Z
( TRUE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- X
( FALSE, TRUE, FALSE, TRUE, TRUE, FALSE ), -- 0
( FALSE, FALSE, TRUE, TRUE, TRUE, FALSE ) -- 1
);
-- ------------------------------------------------------------------------
TYPE ValidStateTableInputType IS ARRAY (VitalStateSymbolType) OF BOOLEAN;
CONSTANT ValidStateTableInput : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'p', 'n', 'R', 'F', '^', 'v',
TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'E', 'A', 'D', '*',
TRUE, TRUE, TRUE, TRUE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
TRUE );
CONSTANT ValidStateTableState : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'p', 'n', 'R', 'F', '^', 'v',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'E', 'A', 'D', '*',
FALSE, FALSE, FALSE, FALSE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
FALSE );
TYPE StateTableMatchType IS ARRAY (X01,X01,VitalStateSymbolType) OF BOOLEAN;
-- last value, present value, table symbol
CONSTANT StateTableMatch : StateTableMatchType := (
( -- X (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,TRUE, TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, FALSE,TRUE, FALSE,
TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 0 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,TRUE, FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE ),
(TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 1 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,TRUE ,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE )
)
);
TYPE Logic_UX01Z_Table IS ARRAY (std_ulogic) OF UX01Z;
----------------------------------------------------------
-- table name : cvt_to_x01z
-- parameters : std_ulogic -- some logic value
-- returns : UX01Z -- state value of logic value
-- purpose : to convert state-strength to state only
----------------------------------------------------------
CONSTANT cvt_to_ux01z : Logic_UX01Z_Table :=
('U','X','0','1','Z','X','0','1','X' );
TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER;
CONSTANT LogicCvtTable : LogicCvtTableType
:= ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MINIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return smaller of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 < in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 < t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Minimum;
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MAXIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return larger of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 > in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-----------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 > t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Maximum;
-----------------------------------------------------------------------
FUNCTION GlitchMinTime (
CONSTANT Time1, Time2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( Time1 >= NOW ) THEN
IF ( Time2 >= NOW ) THEN
RETURN Minimum ( Time1, Time2);
ELSE
RETURN Time1;
END IF;
ELSE
IF ( Time2 >= NOW ) THEN
RETURN Time2;
ELSE
RETURN 0 ns;
END IF;
END IF;
END;
--------------------------------------------------------------------
-- Error Message Types and Tables
--------------------------------------------------------------------
TYPE VitalErrorType IS (
ErrNegDel,
ErrInpSym,
ErrOutSym,
ErrStaSym,
ErrVctLng,
ErrTabWidSml,
ErrTabWidLrg,
ErrTabResSml,
ErrTabResLrg
);
TYPE VitalErrorSeverityType IS ARRAY (VitalErrorType) OF SEVERITY_LEVEL;
CONSTANT VitalErrorSeverity : VitalErrorSeverityType := (
ErrNegDel => WARNING,
ErrInpSym => ERROR,
ErrOutSym => ERROR,
ErrStaSym => ERROR,
ErrVctLng => ERROR,
ErrTabWidSml => ERROR,
ErrTabWidLrg => WARNING,
ErrTabResSml => WARNING,
ErrTabResLrg => WARNING
);
CONSTANT MsgNegDel : STRING :=
"Negative delay. New output value not scheduled. Output signal is: ";
CONSTANT MsgInpSym : STRING :=
"Illegal symbol in the input portion of a Truth/State table.";
CONSTANT MsgOutSym : STRING :=
"Illegal symbol in the output portion of a Truth/State table.";
CONSTANT MsgStaSym : STRING :=
"Illegal symbol in the state portion of a State table.";
CONSTANT MsgVctLng : STRING :=
"Vector (array) lengths not equal. ";
CONSTANT MsgTabWidSml : STRING :=
"Width of the Truth/State table is too small.";
CONSTANT MsgTabWidLrg : STRING :=
"Width of Truth/State table is too large. Extra elements are ignored.";
CONSTANT MsgTabResSml : STRING :=
"Result of Truth/State table has too many elements.";
CONSTANT MsgTabResLrg : STRING :=
"Result of Truth/State table has too few elements.";
CONSTANT MsgUnknown : STRING :=
"Unknown error message.";
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
FUNCTION VitalMessage (
CONSTANT ErrorId : IN VitalErrorType
) RETURN STRING IS
BEGIN
CASE ErrorId IS
WHEN ErrNegDel => RETURN MsgNegDel;
WHEN ErrInpSym => RETURN MsgInpSym;
WHEN ErrOutSym => RETURN MsgOutSym;
WHEN ErrStaSym => RETURN MsgStaSym;
WHEN ErrVctLng => RETURN MsgVctLng;
WHEN ErrTabWidSml => RETURN MsgTabWidSml;
WHEN ErrTabWidLrg => RETURN MsgTabWidLrg;
WHEN ErrTabResSml => RETURN MsgTabResSml;
WHEN ErrTabResLrg => RETURN MsgTabResLrg;
WHEN OTHERS => RETURN MsgUnknown;
END CASE;
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId)
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN CHARACTER
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
---------------------------------------------------------------------------
PROCEDURE ReportGlitch (
CONSTANT GlitchRoutine : IN STRING;
CONSTANT OutSignalName : IN STRING;
CONSTANT PreemptedTime : IN TIME;
CONSTANT PreemptedValue : IN std_ulogic;
CONSTANT NewTime : IN TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT Index : IN INTEGER := 0;
CONSTANT IsArraySignal : IN BOOLEAN := FALSE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE StrPtr1, StrPtr2, StrPtr3, StrPtr4, StrPtr5 : LINE;
BEGIN
Write (StrPtr1, PreemptedTime );
Write (StrPtr2, NewTime);
Write (StrPtr3, LogicCvtTable(PreemptedValue));
Write (StrPtr4, LogicCvtTable(NewValue));
IF IsArraySignal THEN
Write (StrPtr5, STRING'( "(" ) );
Write (StrPtr5, Index);
Write (StrPtr5, STRING'( ")" ) );
ELSE
Write (StrPtr5, STRING'( " " ) );
END IF;
-- Issue Report only if Preemted value has not been
-- removed from event queue
ASSERT PreemptedTime > NewTime
REPORT GlitchRoutine & ": GLITCH Detected on port " &
OutSignalName & StrPtr5.ALL &
"; Preempted Future Value := " & StrPtr3.ALL &
" @ " & StrPtr1.ALL &
"; Newly Scheduled Value := " & StrPtr4.ALL &
" @ " & StrPtr2.ALL &
";"
SEVERITY MsgSeverity;
DEALLOCATE(StrPtr1);
DEALLOCATE(StrPtr2);
DEALLOCATE(StrPtr3);
DEALLOCATE(StrPtr4);
DEALLOCATE(StrPtr5);
RETURN;
END ReportGlitch;
---------------------------------------------------------------------------
-- Procedure : VitalGlitchOnEvent
-- :
-- Parameters : OutSignal ........ signal being driven
-- : OutSignalName..... name of the driven signal
-- : GlitchData........ internal data required by the procedure
-- : NewValue.......... new value being assigned
-- : NewDelay.......... Delay accompanying the assignment
-- : (Note: for vectors, this is an array)
-- : GlitchMode........ Glitch generation mode
-- : MessagePlusX, MessageOnly,
-- : XOnly, NoGlitch )
-- : GlitchDelay....... if <= 0 ns , then there will be no Glitch
-- : if > NewDelay, then there is no Glitch,
-- : otherwise, this is the time when a FORCED
-- : generation of a glitch will occur.
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataType;
CONSTANT NewValue : IN std_logic;
CONSTANT NewDelay : IN TIME := 0 ns;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN TIME := 0 ns;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
-- ------------------------------------------------------------------------
VARIABLE NoGlitchDet : BOOLEAN := FALSE;
VARIABLE OldGlitch : BOOLEAN := FALSE;
VARIABLE Dly : TIME := NewDelay;
BEGIN
-- If nothing to schedule, just return
IF NewDelay < 0 ns THEN
IF (NewValue /= GlitchData.SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled
IF GlitchData.SchedTime <= NOW THEN
GlitchData.CurrentValue := GlitchData.SchedValue;
IF (GlitchDelay <= 0 ns) THEN
IF (NewValue = GlitchData.SchedValue) THEN RETURN; END IF;
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlitchData.GlitchTime <= NOW THEN
GlitchData.CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlitchData.SchedValue = NewValue) THEN
dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
-- Transaction currently scheduled (no glitch if same value)
ELSIF (GlitchData.SchedValue = NewValue) AND
(GlitchData.SchedTime = GlitchData.GlitchTime) AND
(GlitchDelay <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
GlitchData.SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal <= NewValue AFTER Dly;
ELSIF NoGlitchDet THEN
GlitchData.GlitchTime := NOW+Dly;
OutSignal <= NewValue AFTER Dly;
ELSE -- new glitch
GlitchData.GlitchTime := GlitchMinTime ( GlitchData.GlitchTime,
NOW+GlitchDelay );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlitchData.GlitchTime, GlitchData.SchedValue,
(Dly + NOW), NewValue,
MsgSeverity=>MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
OutSignal <= 'X' AFTER GlitchData.GlitchTime-NOW;
OutSignal <= TRANSPORT NewValue AFTER Dly;
ELSE
OutSignal <= NewValue AFTER Dly;
END IF;
END IF;
GlitchData.SchedValue := NewValue;
END IF;
RETURN;
END;
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataArrayType;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT NewDelay : IN VitalTimeArray;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN VitalTimeArray;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
ALIAS GlDataAlias : GlitchDataArrayType(1 TO GlitchData'LENGTH)
IS GlitchData;
ALIAS NewValAlias : std_logic_vector(1 TO NewValue'LENGTH) IS NewValue;
ALIAS GlDelayAlias : VitalTimeArray(1 TO GlitchDelay'LENGTH)
IS GlitchDelay;
ALIAS NewDelAlias : VitalTimeArray(1 TO NewDelay'LENGTH) IS NewDelay;
VARIABLE Index : INTEGER := OutSignal'LEFT;
VARIABLE Direction : INTEGER;
VARIABLE NoGlitchDet : BOOLEAN;
VARIABLE OldGlitch : BOOLEAN;
VARIABLE Dly, GlDly : TIME;
BEGIN
IF (OutSignal'LEFT > OutSignal'RIGHT) THEN
Direction := -1;
ELSE
Direction := 1;
END IF;
IF ( (OutSignal'LENGTH /= GlitchData'LENGTH) OR
(OutSignal'LENGTH /= NewValue'LENGTH) OR
(OutSignal'LENGTH /= NewDelay'LENGTH) OR
(OutSignal'LENGTH /= GlitchDelay'LENGTH) ) THEN
VitalError ( "VitalGlitchOnEvent", ErrVctLng, OutSignalName );
RETURN;
END IF;
-- a call to the scalar function cannot be made since the actual
-- name associated with a signal parameter must be locally static
FOR n IN 1 TO OutSignal'LENGTH LOOP
NoGlitchDet := FALSE;
OldGlitch := FALSE;
Dly := NewDelAlias(n);
-- If nothing to schedule, just skip to next loop iteration
IF NewDelAlias(n) < 0 ns THEN
IF (NewValAlias(n) /= GlDataAlias(n).SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled (i.e. last scheduled
-- transaction already occurred)
IF GlDataAlias(n).SchedTime <= NOW THEN
GlDataAlias(n).CurrentValue := GlDataAlias(n).SchedValue;
IF (GlDelayAlias(n) <= 0 ns) THEN
-- Next iteration if no change in value
IF (NewValAlias(n) = GlDataAlias(n).SchedValue) THEN
Index := Index + Direction;
NEXT;
END IF;
-- since last transaction already occurred there is no glitch
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlDataAlias(n).GlitchTime <= NOW THEN
GlDataAlias(n).CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlDataAlias(n).SchedValue = NewValAlias(n)) THEN
dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- Transaction currently scheduled
ELSIF (GlDataAlias(n).SchedValue = NewValAlias(n)) AND
(GlDataAlias(n).SchedTime = GlDataAlias(n).GlitchTime) AND
(GlDelayAlias(n) <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- update last scheduled transaction
GlDataAlias(n).SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSIF NoGlitchDet THEN
-- if no glitch then update last glitch time
-- and OutSignal(actual_index)
GlDataAlias(n).GlitchTime := NOW+Dly;
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSE -- new glitch
GlDataAlias(n).GlitchTime := GlitchMinTime (
GlDataAlias(n).GlitchTime,
NOW+GlDelayAlias(n) );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlDataAlias(n).GlitchTime,
GlDataAlias(n).SchedValue,
(Dly + NOW), NewValAlias(n),
Index, TRUE, MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
GlDly := GlDataAlias(n).GlitchTime - NOW;
OutSignal(Index) <= 'X' AFTER GlDly;
OutSignal(Index) <= TRANSPORT NewValAlias(n) AFTER Dly;
ELSE
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
END IF;
END IF; -- glitch / no-glitch
GlDataAlias(n).SchedValue := NewValAlias(n);
END IF; -- NewDelAlias(n) < 0 ns
Index := Index + Direction;
END LOOP;
RETURN;
END;
---------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : TruthOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- X01Zout - output converted to X01Z
-- err - true if illegal character is encountered
--
--
-- DESCRIPTION : converts the output of a truth table to a valid
-- std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE TruthOutputX01Z (
CONSTANT TableOut : IN VitalTruthSymbolType;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := TruthTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalTruthTable", ErrOutSym, To_TruthChar(TableOut));
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : StateOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- prev_out - previous output value
-- X01Zout - output cojnverted to X01Z
-- err - true if illegal character is encountered
--
-- DESCRIPTION : converts the output of a state table to a
-- valid std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE StateOutputX01Z (
CONSTANT TableOut : IN VitalStateSymbolType;
CONSTANT PrevOut : IN std_ulogic;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := StateTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalStateTable", ErrOutSym, To_StateChar(TableOut));
ELSIF (TempOut = 'W') THEN
TempOut := To_X01Z(PrevOut);
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME: StateMatch
--
-- PARAMETERS : symbol - symbol from state table
-- in2 - input from VitalStateTble procedure
-- to state table
-- in2LastValue - previous value of input
-- state - false if the symbol is from the input
-- portion of the table,
-- true if the symbol is from the state
-- portion of the table
-- Err - true if symbol is not a valid input symbol
-- ReturnValue - true if match occurred
--
-- DESCRIPTION : This procedure sets ReturnValue to true if in2 matches
-- symbol (from the state table). If symbol is an edge
-- value edge is set to true and in2 and in2LastValue are
-- checked against symbol. Err is set to true if symbol
-- is an invalid value for the input portion of the state
-- table.
--
-- ------------------------------------------------------------------------
PROCEDURE StateMatch (
CONSTANT Symbol : IN VitalStateSymbolType;
CONSTANT in2 : IN std_ulogic;
CONSTANT in2LastValue : IN std_ulogic;
CONSTANT State : IN BOOLEAN;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
IF (State) THEN
IF (NOT ValidStateTableState(Symbol)) THEN
VitalError ( "VitalStateTable", ErrStaSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
Err := FALSE;
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
END IF;
ELSE
IF (NOT ValidStateTableInput(Symbol) ) THEN
VitalError ( "VitalStateTable", ErrInpSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
Err := FALSE;
END IF;
END IF;
END;
-- -----------------------------------------------------------------------
-- FUNCTION NAME: StateTableLookUp
--
-- PARAMETERS : StateTable - state table
-- PresentDataIn - current inputs
-- PreviousDataIn - previous inputs and states
-- NumStates - number of state variables
-- PresentOutputs - current state and current outputs
--
-- DESCRIPTION : This function is used to find the output of the
-- StateTable corresponding to a given set of inputs.
--
-- ------------------------------------------------------------------------
FUNCTION StateTableLookUp (
CONSTANT StateTable : VitalStateTableType;
CONSTANT PresentDataIn : std_logic_vector;
CONSTANT PreviousDataIn : std_logic_vector;
CONSTANT NumStates : NATURAL;
CONSTANT PresentOutputs : std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := PresentDataIn'LENGTH;
CONSTANT NumInputs : INTEGER := InputSize + NumStates - 1;
CONSTANT TableEntries : INTEGER := StateTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := StateTable'LENGTH(2);
CONSTANT OutSize : INTEGER := TableWidth - InputSize - NumStates;
VARIABLE Inputs : std_logic_vector(0 TO NumInputs);
VARIABLE PrevInputs : std_logic_vector(0 TO NumInputs)
:= (OTHERS => 'X');
VARIABLE ReturnValue : std_logic_vector(0 TO (OutSize-1))
:= (OTHERS => 'X');
VARIABLE Temp : std_ulogic;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalStateTableType(0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= StateTable;
BEGIN
Inputs(0 TO InputSize-1) := PresentDataIn;
Inputs(InputSize TO NumInputs) := PresentOutputs(0 TO NumStates - 1);
PrevInputs(0 TO InputSize - 1) := PreviousDataIn(0 TO InputSize - 1);
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the entry
FOR j IN 0 TO InputSize + NumStates LOOP
IF (j = InputSize + NumStates) THEN -- a match occurred
FOR k IN 0 TO Minimum(OutSize, PresentOutputs'LENGTH)-1 LOOP
StateOutputX01Z (
TableAlias(i, TableWidth - k - 1),
PresentOutputs(PresentOutputs'LENGTH - k - 1),
Temp, Err);
ReturnValue(OutSize - k - 1) := Temp;
IF (Err) THEN
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END IF;
END LOOP;
RETURN ReturnValue;
END IF;
StateMatch ( TableAlias(i,j),
Inputs(j), PrevInputs(j),
j >= InputSize, Err, Match);
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END;
--------------------------------------------------------------------
-- to_ux01z
-------------------------------------------------------------------
FUNCTION To_UX01Z ( s : std_ulogic
) RETURN UX01Z IS
BEGIN
RETURN cvt_to_ux01z (s);
END;
---------------------------------------------------------------------------
-- Function : GetEdge
-- Purpose : Converts transitions on a given input signal into a
-- enumeration value representing the transition or level
-- of the signal.
--
-- previous "value" current "value" := "edge"
-- ---------------------------------------------------------
-- '1' | 'H' '1' | 'H' '1' level, no edge
-- '0' | 'L' '1' | 'H' '/' rising edge
-- others '1' | 'H' 'R' rising from X
--
-- '1' | 'H' '0' | 'L' '\' falling egde
-- '0' | 'L' '0' | 'L' '0' level, no edge
-- others '0' | 'L' 'F' falling from X
--
-- 'X' | 'W' | '-' 'X' | 'W' | '-' 'X' unknown (X) level
-- 'Z' 'Z' 'X' unknown (X) level
-- 'U' 'U' 'U' 'U' level
--
-- '1' | 'H' others 'f' falling to X
-- '0' | 'L' others 'r' rising to X
-- 'X' | 'W' | '-' 'U' | 'Z' 'x' unknown (X) edge
-- 'Z' 'X' | 'W' | '-' | 'U' 'x' unknown (X) edge
-- 'U' 'X' | 'W' | '-' | 'Z' 'x' unknown (X) edge
--
---------------------------------------------------------------------------
FUNCTION GetEdge (
SIGNAL s : IN std_logic
) RETURN EdgeType IS
BEGIN
IF (s'EVENT)
THEN RETURN LogicToEdge ( s'LAST_VALUE, s );
ELSE RETURN LogicToLevel ( s );
END IF;
END;
---------------------------------------------------------------------------
PROCEDURE GetEdge (
SIGNAL s : IN std_logic_vector;
VARIABLE LastS : INOUT std_logic_vector;
VARIABLE Edge : OUT EdgeArray ) IS
ALIAS sAlias : std_logic_vector ( 1 TO s'LENGTH ) IS s;
ALIAS LastSAlias : std_logic_vector ( 1 TO LastS'LENGTH ) IS LastS;
ALIAS EdgeAlias : EdgeArray ( 1 TO Edge'LENGTH ) IS Edge;
BEGIN
IF s'LENGTH /= LastS'LENGTH OR
s'LENGTH /= Edge'LENGTH THEN
VitalError ( "GetEdge", ErrVctLng, "s, LastS, Edge" );
END IF;
FOR n IN 1 TO s'LENGTH LOOP
EdgeAlias(n) := LogicToEdge( LastSAlias(n), sAlias(n) );
LastSAlias(n) := sAlias(n);
END LOOP;
END;
---------------------------------------------------------------------------
FUNCTION ToEdge ( Value : IN std_logic
) RETURN EdgeType IS
BEGIN
RETURN LogicToLevel( Value );
END;
-- Note: This function will likely be replaced by S'DRIVING_VALUE in VHDL'92
----------------------------------------------------------------------------
FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataType
) RETURN std_logic IS
BEGIN
IF NOW >= GlitchData.SchedTime THEN
RETURN GlitchData.SchedValue;
ELSIF NOW >= GlitchData.GlitchTime THEN
RETURN 'X';
ELSE
RETURN GlitchData.CurrentValue;
END IF;
END;
---------------------------------------------------------------------------
FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataArrayType
) RETURN std_logic_vector IS
VARIABLE Result : std_logic_vector(GlitchData'RANGE);
BEGIN
FOR n IN GlitchData'RANGE LOOP
IF NOW >= GlitchData(n).SchedTime THEN
Result(n) := GlitchData(n).SchedValue;
ELSIF NOW >= GlitchData(n).GlitchTime THEN
Result(n) := 'X';
ELSE
Result(n) := GlitchData(n).CurrentValue;
END IF;
END LOOP;
RETURN Result;
END;
---------------------------------------------------------------------------
-- function calculation utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Function : VitalSame
-- Returns : VitalSame compares the state (UX01) of two logic value. A
-- value of 'X' is returned if the values are different. The
-- common value is returned if the values are equal.
-- Purpose : When the result of a logic model may be either of two
-- separate input values (eg. when the select on a MUX is 'X'),
-- VitalSame may be used to determine if the result needs to
-- be 'X'.
-- Arguments : See the declarations below...
---------------------------------------------------------------------------
FUNCTION VitalSame (
CONSTANT a, b : IN std_ulogic
) RETURN std_ulogic IS
BEGIN
IF To_UX01(a) = To_UX01(b)
THEN RETURN To_UX01(a);
ELSE RETURN 'X';
END IF;
END;
---------------------------------------------------------------------------
-- delay selection utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure : BufPath, InvPath
--
-- Purpose : BufPath and InvPath compute output change times, based on
-- a change on an input port. The computed output change times
-- returned in the composite parameter 'schd'.
--
-- BufPath and InpPath are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the input ports of a model are
-- combined by the delay selection functions (VitalAND,
-- VitalOR, ...). The GetSchedDelay procedure converts the
-- combined output changes times to the single delay (delta
-- time) value for scheduling the output change (passed to
-- VitalGlitchOnEvent).
--
-- The values in 'schd' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- The output times are computed from the model INPUT value
-- and not the final value. For this reason, 'BufPath' should
-- be used to compute the output times for a non-inverting
-- delay paths and 'InvPath' should be used to compute the
-- ouput times for inverting delay paths. Delay paths which
-- include both non-inverting and paths require usage of both
-- 'BufPath' and 'InvPath'. (IE this is needed for the
-- select->output path of a MUX -- See the VitalMUX model).
--
--
-- Parameters : schd....... Computed output result times. (INOUT parameter
-- modified only on input edges)
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays from this input
--
---------------------------------------------------------------------------
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr01); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr10); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr01);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr10);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr10); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr01); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr10);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr01);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
---------------------------------------------------------------------------
-- Procedure : BufEnab, InvEnab
--
-- Purpose : BufEnab and InvEnab compute output change times, from a
-- change on an input enable port for a 3-state driver. The
-- computed output change times are returned in the composite
-- parameters 'schd1', 'schd0'.
--
-- BufEnab and InpEnab are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the non-enable input ports of
-- a model (See BufPath, InvPath) are combined using the delay
-- selection functions (VitalAND, VitalOR, ...). The
-- GetSchedDelay procedure combines the output times on the
-- enable path with the output times from the data path(s) and
-- computes the single delay (delta time) value for scheduling
-- the output change (passed to VitalGlitchOnEvent)
--
-- The values in 'schd*' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- 'schd1' contains output times for 1->Z, Z->1 transitions.
-- 'schd0' contains output times for 0->Z, Z->0 transitions.
--
-- 'BufEnab' is used for computing the output times for an
-- high asserted enable (output 'Z' for enable='0').
-- 'InvEnab' is used for computing the output times for an
-- low asserted enable (output 'Z' for enable='1').
--
-- Note: separate 'schd1', 'schd0' parameters are generated
-- so that the combination of the delay paths from
-- multiple enable signals may be combined using the
-- same functions/operators used in combining separate
-- data paths. (See exampe 2 below)
--
--
-- Parameters : schd1...... Computed output result times for 1->Z, Z->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- schd0...... Computed output result times for 0->Z, 0->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays for the enable -> output path.
--
---------------------------------------------------------------------------
PROCEDURE BufEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(trz1);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(trz0);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(tr1z);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(tr0z);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(tr1z);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(tr0z);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(trz1);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(trz0);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
---------------------------------------------------------------------------
-- Procedure : GetSchedDelay
--
-- Purpose : GetSchedDelay computes the final delay (incremental) for
-- for scheduling an output signal. The delay is computed
-- from the absolute output times in the 'NewSched' parameter.
-- (See BufPath, InvPath).
--
-- Computation of the output delay for non-3_state outputs
-- consists of selection the appropriate output time based
-- on the new output value 'NewValue' and subtracting 'NOW'
-- to convert to an incremental delay value.
--
-- The Computation of the output delay for 3_state output
-- also includes combination of the enable path delay with
-- the date path delay.
--
-- Parameters : NewDelay... Returned output delay value.
-- GlchDelay.. Returned output delay for the start of a glitch.
-- NewValue... New output value.
-- CurValue... Current value of the output.
-- NewSched... Composite containing the combined absolute
-- output times from the data inputs.
-- EnSched1... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 1->Z, Z->1)
-- EnSched0... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 0->Z, Z->0)
--
---------------------------------------------------------------------------
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType
) IS
VARIABLE Tim, Glch : TIME;
BEGIN
CASE To_UX01(NewValue) IS
WHEN '0' => Tim := NewSched.inp0;
Glch := NewSched.Glch1;
WHEN '1' => Tim := NewSched.inp1;
Glch := NewSched.Glch0;
WHEN OTHERS => Tim := NewSched.InpX;
Glch := -1 ns;
END CASE;
IF (CurValue /= NewValue)
THEN Glch := -1 ns;
END IF;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT VitalTimeArray;
VARIABLE GlchDelay : OUT VitalTimeArray;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT CurValue : IN std_logic_vector;
CONSTANT NewSched : IN SchedArray
) IS
VARIABLE Tim, Glch : TIME;
ALIAS NewDelayAlias : VitalTimeArray( NewDelay'LENGTH DOWNTO 1)
IS NewDelay;
ALIAS GlchDelayAlias : VitalTimeArray(GlchDelay'LENGTH DOWNTO 1)
IS GlchDelay;
ALIAS NewSchedAlias : SchedArray( NewSched'LENGTH DOWNTO 1)
IS NewSched;
ALIAS NewValueAlias : std_logic_vector ( NewValue'LENGTH DOWNTO 1 )
IS NewValue;
ALIAS CurValueAlias : std_logic_vector ( CurValue'LENGTH DOWNTO 1 )
IS CurValue;
BEGIN
FOR n IN NewDelay'LENGTH DOWNTO 1 LOOP
CASE To_UX01(NewValueAlias(n)) IS
WHEN '0' => Tim := NewSchedAlias(n).inp0;
Glch := NewSchedAlias(n).Glch1;
WHEN '1' => Tim := NewSchedAlias(n).inp1;
Glch := NewSchedAlias(n).Glch0;
WHEN OTHERS => Tim := NewSchedAlias(n).InpX;
Glch := -1 ns;
END CASE;
IF (CurValueAlias(n) /= NewValueAlias(n))
THEN Glch := -1 ns;
END IF;
NewDelayAlias(n) := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelayAlias(n) := Glch;
ELSE GlchDelayAlias(n) := Glch - NOW;
END IF; -- glch < 0 ns
END LOOP;
RETURN;
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType;
CONSTANT EnSched1 : IN SchedType;
CONSTANT EnSched0 : IN SchedType
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE Tim, Glch : TIME;
BEGIN
CASE v2'(To_X01Z(CurValue) & To_X01Z(NewValue)) IS
WHEN "00" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := GlitchMinTime(NewSched.Glch1,EnSched0.Glch0);
WHEN "01" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := EnSched1.Glch0;
WHEN "0Z" => Tim := EnSched0.inp0;
Glch := NewSched.Glch1;
WHEN "0X" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "10" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := EnSched0.Glch0;
WHEN "11" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := GlitchMinTime(NewSched.Glch0,EnSched1.Glch0);
WHEN "1Z" => Tim := EnSched1.inp0;
Glch := NewSched.Glch0;
WHEN "1X" => Tim := Maximum (NewSched.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "Z0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
IF NewSched.Glch0 > NOW
THEN Glch := Maximum(NewSched.Glch1,EnSched1.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "Z1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
IF NewSched.Glch1 > NOW
THEN Glch := Maximum(NewSched.Glch0,EnSched0.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "ZX" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "ZZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "X0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := 0 ns;
WHEN "X1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := 0 ns;
WHEN "XZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN OTHERS => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
END CASE;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
---------------------------------------------------------------------------
-- Operators and Functions for combination (selection) of path delays
-- > These functions support selection of the "appripriate" path delay
-- dependent on the logic function.
-- > These functions only "select" from the possable output times. No
-- calculation (addition) of delays is performed.
-- > See description of 'BufPath', 'InvPath' and 'GetSchedDelay'
-- > See primitive PROCEDURE models for examples.
---------------------------------------------------------------------------
FUNCTION "not" (
CONSTANT a : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := a.inp0 ;
z.inp0 := a.inp1 ;
z.InpX := a.InpX ;
z.Glch1 := a.Glch0;
z.Glch0 := a.Glch1;
RETURN (z);
END;
FUNCTION "and" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp1 , b.inp1 );
z.inp0 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch1, b.Glch1 );
z.Glch0 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
FUNCTION "or" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp0 , b.inp0 );
z.inp1 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch0, b.Glch0 );
z.Glch1 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
FUNCTION "nand" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp1 , b.inp1 );
z.inp1 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch1, b.Glch1 );
z.Glch1 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
FUNCTION "nor" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp0 , b.inp0 );
z.inp0 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch0, b.Glch0 );
z.Glch0 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 2-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) NOR (a NOR b)
z.inp1 := Maximum ( Minimum (ai.inp0 , bi.inp0 ),
Minimum (ab.inp1 , bb.inp1 ) );
z.inp0 := Minimum ( Maximum (ai.inp1 , bi.inp1 ),
Maximum (ab.inp0 , bb.inp0 ) );
z.InpX := Maximum ( Maximum (ai.InpX , bi.InpX ),
Maximum (ab.InpX , bb.InpX ) );
z.Glch1 := Maximum (GlitchMinTime (ai.Glch0, bi.Glch0),
GlitchMinTime (ab.Glch1, bb.Glch1) );
z.Glch0 := GlitchMinTime ( Maximum (ai.Glch1, bi.Glch1),
Maximum (ab.Glch0, bb.Glch0) );
RETURN (z);
END;
FUNCTION VitalXNOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) OR (a NOR b)
z.inp0 := Maximum ( Minimum (ab.inp0 , bb.inp0 ),
Minimum (ai.inp1 , bi.inp1 ) );
z.inp1 := Minimum ( Maximum (ab.inp1 , bb.inp1 ),
Maximum (ai.inp0 , bi.inp0 ) );
z.InpX := Maximum ( Maximum (ab.InpX , bb.InpX ),
Maximum (ai.InpX , bi.InpX ) );
z.Glch0 := Maximum (GlitchMinTime (ab.Glch0, bb.Glch0),
GlitchMinTime (ai.Glch1, bi.Glch1) );
z.Glch1 := GlitchMinTime ( Maximum (ab.Glch1, bb.Glch1),
Maximum (ai.Glch0, bi.Glch0) );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 3-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 (ab,ai, bb,bi),
VitalXOR2 (ai,ab, bi,bb),
cb, ci );
END;
FUNCTION VitalXNOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
cb, ci );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 4-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalXOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
FUNCTION VitalXNOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for N-bit Logical gates.
-- ------------------------------------------------------------------------
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
FUNCTION VitalXOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
FUNCTION VitalXNOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXNOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXNOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT d1, d0 : IN SchedType;
CONSTANT sb, SI : IN SchedType
) RETURN SchedType IS
BEGIN
RETURN (d1 AND sb) OR (d0 AND (NOT SI) );
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN SchedArray4;
CONSTANT sb : IN SchedArray2;
CONSTANT SI : IN SchedArray2
) RETURN SchedType IS
BEGIN
RETURN ( sb(1) AND VitalMUX2(Data(3),Data(2), sb(0), SI(0)) )
OR ( (NOT SI(1)) AND VitalMUX2(Data(1),Data(0), sb(0), SI(0)) );
END;
FUNCTION VitalMUX8 (
CONSTANT Data : IN SchedArray8;
CONSTANT sb : IN SchedArray3;
CONSTANT SI : IN SchedArray3
) RETURN SchedType IS
BEGIN
RETURN ( ( sb(2)) AND VitalMUX4 (Data(7 DOWNTO 4),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) )
OR ( (NOT SI(2)) AND VitalMUX4 (Data(3 DOWNTO 0),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) );
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT sMsb : INTEGER := sb'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
BEGIN
IF sb'LENGTH = 1 THEN
RETURN VitalMUX2( Data(2), Data(1), sb(1), SI(1) );
ELSIF sb'LENGTH = 2 THEN
RETURN VitalMUX4( Data, sb, SI );
ELSIF sb'LENGTH = 3 THEN
RETURN VitalMUX8( Data, sb, SI );
ELSIF sb'LENGTH > 3 THEN
RETURN (( sb(sMsb)) AND VInterMux( Data(dMsbLow DOWNTO 1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ))
OR ((NOT SI(sMsb)) AND VInterMux( Data(dMsbHigh DOWNTO dMsbLow+1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ));
ELSE
RETURN (0 ns, 0 ns, 0 ns, 0 ns, 0 ns); -- dselect'LENGTH < 1
END IF;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT msb : INTEGER := 2**sb'LENGTH;
VARIABLE lDat : SchedArray(msb DOWNTO 1);
ALIAS DataAlias : SchedArray ( Data'LENGTH DOWNTO 1 ) IS Data;
ALIAS sbAlias : SchedArray ( sb'LENGTH DOWNTO 1 ) IS sb;
ALIAS siAlias : SchedArray ( SI'LENGTH DOWNTO 1 ) IS SI;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
FOR i IN msb DOWNTO Data'LENGTH+1 LOOP
lDat(i) := DefSchedAnd;
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
RETURN VInterMux( lDat, sbAlias, siAlias );
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT DataB : IN SchedType;
CONSTANT DataI : IN SchedType;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray2;
BEGIN
Result(1) := Enable AND ( DataB);
Result(0) := Enable AND (NOT DataI);
RETURN Result;
END;
FUNCTION VitalDECODER4 (
CONSTANT DataB : IN SchedArray2;
CONSTANT DataI : IN SchedArray2;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray4;
BEGIN
Result(3) := Enable AND ( DataB(1)) AND ( DataB(0));
Result(2) := Enable AND ( DataB(1)) AND (NOT DataI(0));
Result(1) := Enable AND (NOT DataI(1)) AND ( DataB(0));
Result(0) := Enable AND (NOT DataI(1)) AND (NOT DataI(0));
RETURN Result;
END;
FUNCTION VitalDECODER8 (
CONSTANT DataB : IN SchedArray3;
CONSTANT DataI : IN SchedArray3;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray8;
BEGIN
Result(7):= Enable AND ( DataB(2))AND( DataB(1))AND( DataB(0));
Result(6):= Enable AND ( DataB(2))AND( DataB(1))AND(NOT DataI(0));
Result(5):= Enable AND ( DataB(2))AND(NOT DataI(1))AND( DataB(0));
Result(4):= Enable AND ( DataB(2))AND(NOT DataI(1))AND(NOT DataI(0));
Result(3):= Enable AND (NOT DataI(2))AND( DataB(1))AND( DataB(0));
Result(2):= Enable AND (NOT DataI(2))AND( DataB(1))AND(NOT DataI(0));
Result(1):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND( DataB(0));
Result(0):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND(NOT DataI(0));
RETURN Result;
END;
FUNCTION VitalDECODER (
CONSTANT DataB : IN SchedArray;
CONSTANT DataI : IN SchedArray;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
CONSTANT DMsb : INTEGER := DataB'LENGTH - 1;
ALIAS DataBAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataB;
ALIAS DataIAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataI;
BEGIN
IF DataB'LENGTH = 1 THEN
RETURN VitalDECODER2 ( DataBAlias( 0 ),
DataIAlias( 0 ), Enable );
ELSIF DataB'LENGTH = 2 THEN
RETURN VitalDECODER4 ( DataBAlias(1 DOWNTO 0),
DataIAlias(1 DOWNTO 0), Enable );
ELSIF DataB'LENGTH = 3 THEN
RETURN VitalDECODER8 ( DataBAlias(2 DOWNTO 0),
DataIAlias(2 DOWNTO 0), Enable );
ELSIF DataB'LENGTH > 3 THEN
RETURN VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataBAlias(DMsb)) )
& VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataIAlias(DMsb)) );
ELSE
RETURN DefSchedArray2;
END IF;
END;
-------------------------------------------------------------------------------
-- PRIMITIVES
-------------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b);
END;
--
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b);
END;
--
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b);
END;
--
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NAND b);
END;
--
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NOR b);
END;
--
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b));
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c);
END;
--
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c);
END;
--
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c);
END;
--
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c));
END;
--
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c));
END;
--
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c));
END;
-- ---------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ---------------------------------------------------------------------------
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c AND d);
END;
--
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c OR d);
END;
--
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c XOR d);
END;
--
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c AND d));
END;
--
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c OR d));
END;
--
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c XOR d));
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01(Data));
END;
--
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf0_Table(Enable,Data));
END;
--
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf1_Table(Enable,Data));
END;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01Z(Data));
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT Data);
END;
--
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf0_Table(Enable,Data));
END;
--
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf1_Table(Enable,Data));
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect) IS
WHEN '0' => Result := To_UX01(Data0);
WHEN '1' => Result := To_UX01(Data1);
WHEN OTHERS => Result := VitalSame( Data1, Data0 );
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Slct : std_logic_vector2;
VARIABLE Result : UX01;
BEGIN
Slct := To_X01(dSelect);
CASE Slct IS
WHEN "00" => Result := To_UX01(Data(0));
WHEN "01" => Result := To_UX01(Data(1));
WHEN "10" => Result := To_UX01(Data(2));
WHEN "11" => Result := To_UX01(Data(3));
WHEN "0X" => Result := VitalSame( Data(1), Data(0) );
WHEN "1X" => Result := VitalSame( Data(2), Data(3) );
WHEN "X0" => Result := VitalSame( Data(2), Data(0) );
WHEN "X1" => Result := VitalSame( Data(3), Data(1) );
WHEN OTHERS => Result := VitalSame( VitalSame(Data(3),Data(2)),
VitalSame(Data(1),Data(0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect(2)) IS
WHEN '0' => Result := VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0));
WHEN '1' => Result := VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0));
WHEN OTHERS => Result := VitalSame( VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0)),
VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector
) RETURN std_ulogic IS
CONSTANT sMsb : INTEGER := dSelect'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE Result : UX01;
BEGIN
IF dSelect'LENGTH = 1 THEN
Result := VitalMUX2( DataAlias(2), DataAlias(1), dSelAlias(1) );
ELSIF dSelect'LENGTH = 2 THEN
Result := VitalMUX4( DataAlias, dSelAlias );
ELSIF dSelect'LENGTH > 2 THEN
CASE To_X01(dSelect(sMsb)) IS
WHEN '0' =>
Result := VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN '1' =>
Result := VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN OTHERS =>
Result := VitalSame(
VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) ),
VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) )
);
END CASE;
ELSE
Result := 'X'; -- dselect'LENGTH < 1
END IF;
RETURN Result;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
CONSTANT msb : INTEGER := 2**dSelect'LENGTH;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE lDat : std_logic_vector(msb DOWNTO 1) := (OTHERS=>'X');
VARIABLE Result : UX01;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
Result := VInterMux( lDat, dSelAlias );
RETURN ResultMap(Result);
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2 IS
VARIABLE Result : std_logic_vector2;
BEGIN
Result(1) := ResultMap(Enable AND ( Data));
Result(0) := ResultMap(Enable AND (NOT Data));
RETURN Result;
END;
--
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4 IS
VARIABLE Result : std_logic_vector4;
BEGIN
Result(3) := ResultMap(Enable AND ( Data(1)) AND ( Data(0)));
Result(2) := ResultMap(Enable AND ( Data(1)) AND (NOT Data(0)));
Result(1) := ResultMap(Enable AND (NOT Data(1)) AND ( Data(0)));
Result(0) := ResultMap(Enable AND (NOT Data(1)) AND (NOT Data(0)));
RETURN Result;
END;
--
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8 IS
VARIABLE Result : std_logic_vector8;
BEGIN
Result(7) := ( Data(2)) AND ( Data(1)) AND ( Data(0));
Result(6) := ( Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(5) := ( Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(4) := ( Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(3) := (NOT Data(2)) AND ( Data(1)) AND ( Data(0));
Result(2) := (NOT Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(1) := (NOT Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(0) := (NOT Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(0) := ResultMap ( Enable AND Result(0) );
Result(1) := ResultMap ( Enable AND Result(1) );
Result(2) := ResultMap ( Enable AND Result(2) );
Result(3) := ResultMap ( Enable AND Result(3) );
Result(4) := ResultMap ( Enable AND Result(4) );
Result(5) := ResultMap ( Enable AND Result(5) );
Result(6) := ResultMap ( Enable AND Result(6) );
Result(7) := ResultMap ( Enable AND Result(7) );
RETURN Result;
END;
--
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector IS
CONSTANT DMsb : INTEGER := Data'LENGTH - 1;
ALIAS DataAlias : std_logic_vector ( DMsb DOWNTO 0 ) IS Data;
BEGIN
IF Data'LENGTH = 1 THEN
RETURN VitalDECODER2 (DataAlias( 0 ), Enable, ResultMap );
ELSIF Data'LENGTH = 2 THEN
RETURN VitalDECODER4 (DataAlias(1 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH = 3 THEN
RETURN VitalDECODER8 (DataAlias(2 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH > 3 THEN
RETURN VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataAlias(DMsb)), ResultMap )
& VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataAlias(DMsb)), ResultMap );
ELSE RETURN "X";
END IF;
END;
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( DataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( DataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXOR ( Data );
new_schd := VitalXOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( DataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( DataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXNOR ( Data );
new_schd := VitalXNOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b;
new_schd := a_schd AND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b;
new_schd := a_schd OR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NAND b;
new_schd := a_schd NAND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NOR b;
new_schd := a_schd NOR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b;
new_schd := VitalXOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b);
new_schd := VitalXNOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
--
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c;
new_schd := a_schd AND b_schd AND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c;
new_schd := a_schd OR b_schd OR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND c;
new_schd := (a_schd AND b_schd) NAND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR c;
new_schd := (a_schd OR b_schd) NOR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c;
new_schd := VitalXOR3 ( ab_schd,ai_schd,
bb_schd,bi_schd,
cb_schd,ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c);
new_schd := VitalXNOR3 ( ab_schd, ai_schd,
bb_schd, bi_schd,
cb_schd, ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c AND d;
new_schd := a_schd AND b_schd AND c_schd AND d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c OR d;
new_schd := a_schd OR b_schd OR c_schd OR d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND (c AND d);
new_schd := (a_schd AND b_schd) NAND (c_schd AND d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR (c OR d);
new_schd := (a_schd OR b_schd) NOR (c_schd OR d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c XOR d;
new_schd := VitalXOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c XOR d);
new_schd := VitalXNOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(To_UX01(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := To_UX01(a); -- convert to forcing strengths
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr01);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr10);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF1( Data, Enable );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01Z) THEN
LOOP
q <= ResultMap(To_UX01Z(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
CASE v2'(To_X01Z(NewValue) & To_X01Z(a)) IS
WHEN "00" => Dly := tpd_a_q(tr10);
WHEN "01" => Dly := tpd_a_q(tr01);
WHEN "0Z" => Dly := tpd_a_q(tr0z);
WHEN "0X" => Dly := tpd_a_q(tr01);
WHEN "10" => Dly := tpd_a_q(tr10);
WHEN "11" => Dly := tpd_a_q(tr01);
WHEN "1Z" => Dly := tpd_a_q(tr1z);
WHEN "1X" => Dly := tpd_a_q(tr10);
WHEN "Z0" => Dly := tpd_a_q(trz0);
WHEN "Z1" => Dly := tpd_a_q(trz1);
WHEN "ZZ" => Dly := 0 ns;
WHEN "ZX" => Dly := Minimum (tpd_a_q(trz1), tpd_a_q(trz0));
WHEN "X0" => Dly := tpd_a_q(tr10);
WHEN "X1" => Dly := tpd_a_q(tr01);
WHEN "XZ" => Dly := Minimum (tpd_a_q(tr0z), tpd_a_q(tr1z));
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
NewValue := To_UX01Z(a);
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(NOT a);
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT a;
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr10);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr01);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF1( Data, Enable );
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType := DefSchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE d1_Schd, d0_Schd : SchedType;
VARIABLE dSel_bSchd, dSel_iSchd : SchedType;
VARIABLE d1_Edge, d0_Edge, dSel_Edge : EdgeType;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_d1_q = VitalZeroDelay01)
AND (tpd_d0_q = VitalZeroDelay01)
AND (tpd_dsel_q = VitalZeroDelay01) ) THEN
LOOP
q <= VitalMUX2 ( d1, d0, dSel, ResultMap );
WAIT ON d1, d0, dSel;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d1_Schd, InitialEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, InitialEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, InitialEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, InitialEdge(dSel), tpd_dsel_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d1_Schd, GetEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, GetEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, GetEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, GetEdge(dSel), tpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX2 ( d1, d0, dSel );
new_schd := VitalMUX2 ( d1_Schd, d0_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON d1, d0, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray4;
VARIABLE Data_Edge : EdgeArray4;
VARIABLE dSel_Edge : EdgeArray2;
VARIABLE dSel_bSchd : SchedArray2;
VARIABLE dSel_iSchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX4 ( Data, dSel );
new_schd := VitalMUX4 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray8;
VARIABLE Data_Edge : EdgeArray8;
VARIABLE dSel_Edge : EdgeArray3;
VARIABLE dSel_bSchd : SchedArray3;
VARIABLE dSel_iSchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX8 ( Data, dSel );
new_schd := VitalMUX8 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE dSel_Edge : EdgeArray(dSel'RANGE);
VARIABLE dSel_bSchd : SchedArray(dSel'RANGE);
VARIABLE dSel_iSchd : SchedArray(dSel'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX ( Data, dSel );
new_schd := VitalMUX ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- Caution: If 'ResultMap' defines other than strength mapping, the
-- delay selection is not defined.
-- ------------------------------------------------------------------------
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : std_logic_vector2;
VARIABLE Glitch_Data : GlitchArray2;
VARIABLE new_schd : SchedArray2;
VARIABLE Dly, Glch : TimeArray2;
VARIABLE Enable_Schd : SchedType := DefSchedType;
VARIABLE Data_BSchd, Data_ISchd : SchedType;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q = VitalZeroDelay01) AND (tpd_data_q = VitalZeroDelay01) THEN
LOOP
q <= VitalDECODER2(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( Data_BSchd, InitialEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, InitialEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( Data_BSchd, GetEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, GetEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER2 ( Data, Enable, ResultMap );
new_schd := VitalDECODER2 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; -- SN
END;
--
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector4;
VARIABLE Glitch_Data : GlitchArray4;
VARIABLE new_schd : SchedArray4;
VARIABLE Dly, Glch : TimeArray4;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray2;
VARIABLE Data_BSchd, Data_ISchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER4(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER4 ( Data, Enable, ResultMap );
new_schd := VitalDECODER4 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector8;
VARIABLE Glitch_Data : GlitchArray8;
VARIABLE new_schd : SchedArray8;
VARIABLE Dly, Glch : TimeArray8;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray3;
VARIABLE Data_BSchd, Data_ISchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER8 ( Data, Enable, ResultMap );
new_schd := VitalDECODER8 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector(q'RANGE);
VARIABLE Glitch_Data : GlitchDataArrayType(q'RANGE);
VARIABLE new_schd : SchedArray(q'RANGE);
VARIABLE Dly, Glch : VitalTimeArray(q'RANGE);
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_BSchd, Data_ISchd : SchedArray(Data'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER ( Data, Enable, ResultMap );
new_schd := VitalDECODER ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE ReturnValue : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO InputSize - 1)
:= To_X01(DataIn);
VARIABLE Index : INTEGER;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalTruthTableType(0 TO (TruthTable'LENGTH(1)-1),
0 TO (TruthTable'LENGTH(2)-1))
:= TruthTable;
BEGIN
-- search through each row of the truth table
IF OutSize > 0 THEN
ColLoop:
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each input element of the entry
FOR j IN 0 TO InputSize LOOP
IF (j = InputSize) THEN -- This entry matches
-- Return the Result
Index := 0;
FOR k IN TruthTable'LENGTH(2) - 1 DOWNTO InputSize LOOP
TruthOutputX01Z ( TableAlias(i,k),
ReturnValue(Index), Err);
EXIT WHEN Err;
Index := Index + 1;
END LOOP;
IF Err THEN
ReturnValue := (OTHERS => 'X');
END IF;
RETURN ReturnValue;
END IF;
IF NOT ValidTruthTableInput(TableAlias(i,j)) THEN
VitalError ( "VitalTruthTable", ErrInpSym,
To_TruthChar(TableAlias(i,j)) );
EXIT ColLoop;
END IF;
EXIT RowLoop WHEN NOT ( TruthTableMatch( DataInAlias(j),
TableAlias(i, j)));
END LOOP RowLoop;
END LOOP ColLoop;
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
END IF;
RETURN ReturnValue;
END VitalTruthTable;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE TempResult : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
IF (OutSize > 0) THEN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
RETURN (TempResult(0));
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
RETURN 'X';
END IF;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) IS
CONSTANT ResLeng : INTEGER := Result'LENGTH;
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
CONSTANT FinalResLen : INTEGER := Minimum(ActResLen, ResLeng);
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF (ResLeng > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF (ResLeng < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
TempResult(FinalResLen-1 DOWNTO 0) := TempResult(FinalResLen-1 DOWNTO 0);
Result <= TempResult;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) IS
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
IF (ActResLen > 0) THEN
Result <= TempResult(0);
END IF;
END VitalTruthTable;
-- ------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1)
:= To_X01(DataIn);
VARIABLE PrevDataAlias : std_logic_vector(0 TO PreviousDataIn'LENGTH-1)
:= To_X01(PreviousDataIn);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1)
:= To_X01(Result);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (PreviousDataIn'LENGTH < DataIn'LENGTH) THEN
VitalError ( "VitalStateTable", ErrVctLng, "PreviousDataIn<DataIn");
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSIF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevDataAlias, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias ( Maximum(0, ResLeng - OutSize) TO ResLeng - 1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result := ResultAlias;
PrevDataAlias(0 TO InputSize - 1) := DataInAlias;
PreviousDataIn := PrevDataAlias;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic; -- states
VARIABLE PreviousDataIn : INOUT std_logic_vector; -- previous inputs and states
CONSTANT StateTable : IN VitalStateTableType; -- User's StateTable data
CONSTANT DataIn : IN std_logic_vector -- Inputs
) IS
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
BEGIN
ResultAlias(0) := Result;
VitalStateTable ( StateTable => StateTable,
DataIn => DataIn,
NumStates => 1,
Result => ResultAlias,
PreviousDataIn => PreviousDataIn
);
Result := ResultAlias(0);
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result <= ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
DataInAlias := To_X01(DataIn);
ResultAlias := To_X01(Result);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias(Maximum(0, ResLeng - OutSize) TO ResLeng-1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result <= ResultAlias;
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := StateTable'LENGTH(2) - InputSize-1;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
Result <= 'X';
ELSE
IF ( 1 > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
ResultAlias(0) := To_X01(Result);
DataInAlias := To_X01(DataIn);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, 1, ResultAlias);
Result <= ExpResult(OutSize-1);
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
-- ------------------------------------------------------------------------
-- std_logic resolution primitive
-- ------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
CONSTANT Data : IN std_logic_vector
) IS
VARIABLE uData : std_ulogic_vector(Data'RANGE);
BEGIN
FOR i IN Data'RANGE LOOP
uData(i) := Data(i);
END LOOP;
q <= resolved(uData);
END;
END VITAL_Primitives;
| gpl-2.0 | 224a9a76de0a817688e8b6b1e7b99817 | 0.451252 | 4.99917 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/fetch.vhd | 1 | 2,926 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:40:53 11/09/2017
-- Design Name:
-- Module Name: fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fetch is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
CUentrada : in STD_LOGIC_VECTOR(1 downto 0);
Entradain : in STD_LOGIC_VECTOR (31 downto 0);
Instruccionout : out STD_LOGIC_VECTOR (31 downto 0);
PCout : out STD_LOGIC_VECTOR (31 downto 0));
end fetch;
architecture Behavioral of fetch is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT PC
PORT(
inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
Address : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Mux2
PORT(
Entrada : in STD_LOGIC_VECTOR (31 downto 0);
sumador : in STD_LOGIC_VECTOR (31 downto 0);
Cuentrada : in STD_LOGIC_VECTOR (1 downto 0);
posicion : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a2,a3,a5,a35: std_logic_vector(31 downto 0);
begin
ints_NPC: PC PORT MAP(
inPC => a35,
Reset => Reset,
Clk => Clk,
outPC => a2
);
ints_PC: PC PORT MAP(
inPC => a2,
Reset => Reset,
Clk => Clk,
outPC => a5
);
PCout<=a5;
ints_sum: Sumador32bit PORT MAP(
Oper1 => a5,
Reset => Reset,
Oper2 =>"00000000000000000000000000000001",
Result => a3
);
ints_Mux2: Mux2 PORT MAP(
Entrada => Entradain,
sumador => a3,
Cuentrada => CUentrada,
posicion=> a35
);
ints_IM: IM PORT MAP(
Address => a5,
Reset => Reset,
Instruction =>Instruccionout
);
end Behavioral;
| gpl-3.0 | 2bde9342afec87e5b90e030bb5250940 | 0.536227 | 3.844941 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng.vhd | 4 | 3,998 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| bsd-3-clause | 5f27c313c97c4717af6dcc3eb1135f1b | 0.642071 | 4.26226 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_pkg.vhd | 1 | 23,664 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
package axi_dma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Find minimum required btt width
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer;
-- Return correct hertz paramter value
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer;
-- Return SnF enable or disable
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
--constant NUM_REG_TOTAL : integer := 18;
--constant NUM_REG_TOTAL : integer := 23;
constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers
--constant NUM_REG_PER_CHANNEL : integer := 6;
constant NUM_REG_PER_CHANNEL : integer := 12;
constant NUM_REG_PER_S2MM : integer := 120;
--constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
constant CMD_BASE_WIDTH : integer := 40;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Lite AXI DMA Register Offsets
-------------------------------------------------------------------------------
constant MM2S_DMACR_INDEX : integer := 0;
constant MM2S_DMASR_INDEX : integer := 1;
constant MM2S_CURDESC_LSB_INDEX : integer := 2;
constant MM2S_CURDESC_MSB_INDEX : integer := 3;
constant MM2S_TAILDESC_LSB_INDEX : integer := 4;
constant MM2S_TAILDESC_MSB_INDEX : integer := 5;
constant MM2S_SA_INDEX : integer := 6;
constant MM2S_SA2_INDEX : integer := 7;
constant RESERVED_20_INDEX : integer := 8;
constant RESERVED_24_INDEX : integer := 9;
constant MM2S_LENGTH_INDEX : integer := 10;
constant RESERVED_2C_INDEX : integer := 11;
constant S2MM_DMACR_INDEX : integer := 12;
constant S2MM_DMASR_INDEX : integer := 13;
constant S2MM_CURDESC_LSB_INDEX : integer := 14;
constant S2MM_CURDESC_MSB_INDEX : integer := 15;
constant S2MM_TAILDESC_LSB_INDEX : integer := 16;
constant S2MM_TAILDESC_MSB_INDEX : integer := 17;
constant S2MM_DA_INDEX : integer := 18;
constant S2MM_DA2_INDEX : integer := 19;
constant RESERVED_50_INDEX : integer := 20;
constant RESERVED_54_INDEX : integer := 21;
--constant S2MM_LENGTH_INDEX : integer := 22;
constant S2MM_LENGTH_INDEX : integer := 142;
constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00
constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04
constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08
constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C
constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10
constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14
constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18
constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C
constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20
constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24
constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28
-- Following was reserved, now is used for SG xCache and xUser
constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C
constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30
constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34
constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38
constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C
constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40
constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44
constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034
constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C
constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50
constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54
constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58
-- New registers for S2MM channels
constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70
constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74
constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78
constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C
constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90
constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94
constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98
constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C
constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0
constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4
constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8
constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC
constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0
constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4
constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8
constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC
constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0
constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4
constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8
constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC
constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110
constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114
constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118
constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C
constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130
constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134
constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138
constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C
constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150
constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154
constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158
constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C
constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170
constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174
constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178
constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C
constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190
constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194
constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198
constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C
constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0
constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4
constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8
constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC
constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0
constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4
constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8
constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC
constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0
constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4
constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8
constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC
constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210
constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214
constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218
constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C
constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230
constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234
constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238
constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RS_BIT : integer := 0;
constant DMACR_TAILPEN_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_KH_BIT : integer := 3;
constant CYCLIC_BIT : integer := 4;
--constant DMACR_RESERVED3_BIT : integer := 3;
--constant DMACR_RESERVED4_BIT : integer := 4;
constant DMACR_RESERVED5_BIT : integer := 5;
constant DMACR_RESERVED6_BIT : integer := 6;
constant DMACR_RESERVED7_BIT : integer := 7;
constant DMACR_RESERVED8_BIT : integer := 8;
constant DMACR_RESERVED9_BIT : integer := 9;
constant DMACR_RESERVED10_BIT : integer := 10;
constant DMACR_RESERVED11_BIT : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_CMPLT_BIT : integer := 2;
constant DMASR_ERROR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_RESERVED7_BIT : integer := 7;
constant DMASR_SGINTERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_RESERVED15_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 6;
constant CURDESC_RESERVED_BIT5 : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
constant CURDESC_RESERVED_BIT3 : integer := 3;
constant CURDESC_RESERVED_BIT2 : integer := 2;
constant CURDESC_RESERVED_BIT1 : integer := 1;
constant CURDESC_RESERVED_BIT0 : integer := 0;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 6;
constant TAILDESC_RESERVED_BIT5 : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Control Bits
constant DESC_BLENGTH_LSB_BIT : integer := 0;
constant DESC_BLENGTH_MSB_BIT : integer := 22;
constant DESC_RSVD23_BIT : integer := 23;
constant DESC_RSVD24_BIT : integer := 24;
constant DESC_RSVD25_BIT : integer := 25;
constant DESC_EOF_BIT : integer := 26;
constant DESC_SOF_BIT : integer := 27;
constant DESC_RSVD28_BIT : integer := 28;
constant DESC_RSVD29_BIT : integer := 29;
constant DESC_RSVD30_BIT : integer := 30;
constant DESC_IOC_BIT : integer := 31;
-- Descriptor Status Bits
constant DESC_STS_CMPLTD_BIT : integer := 31;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_RXSOF_BIT : integer := 27;
constant DESC_STS_RXEOF_BIT : integer := 26;
constant DESC_STS_RSVD25_BIT : integer := 25;
constant DESC_STS_RSVD24_BIT : integer := 24;
constant DESC_STS_RSVD23_BIT : integer := 23;
constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22;
constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
end axi_dma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_dma_pkg is
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width ( dwidth : integer;
burst_size: integer;
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width;
-------------------------------------------------------------------------------
-- function to return Frequency Hertz parameter based on inclusion of sg engine
-------------------------------------------------------------------------------
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer is
begin
-- 1 = Scatter Gather Included
-- 0 = Scatter Gather Excluded
if(included = 1)then
return sg_frequency;
else
return lite_frequency;
end if;
end;
-------------------------------------------------------------------------------
-- function to enable store and forward based on data width mismatch
-- or directly enabled
-------------------------------------------------------------------------------
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer is
begin
-- If store and forward enable or data widths do not
-- match then return 1 to enable snf
if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then
return 1;
else
-- coverage off
return 0;
-- coverage on
end if;
end;
end package body axi_dma_pkg;
| mit | 0d20c6bbc8b49575cda9db109b5e69d8 | 0.600406 | 3.737208 | false | false | false | false |
davewebb8211/ghdl | libraries/ieee/math_real.vhdl | 1 | 10,039 | ------------------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be added to this package.
-- This package cannot be sold or distributed for profit.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.1 (Strawman) Jose A. Torres 6/22/92
-- Version 0.2 Jose A. Torres 1/15/93
-- Version 0.3 Jose A. Torres 4/13/93
-- Version 0.4 Jose A. Torres 4/19/93
-- Version 0.5 Jose A. Torres 4/20/93 Added RANDOM()
-- Version 0.6 Jose A. Torres 4/23/93 Renamed RANDOM as
-- UNIFORM. Modified
-- rights banner.
-- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility
-- with package body.
--
-- GHDL history
-- 2005-04-07 Initial version.
-- 2005-09-01 Some PI constants added.
-- 2005-12-20 I. Curtis : significant overhaul to bring closer in line
-- with ieee standard
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
-- IAC: should have a string with copyright notice
-- constant CopyRightNotice: STRING
-- := "GPL";
--
-- commonly used constants
--
constant MATH_E : real := 2.71828_18284_59045_23536; -- e
constant MATH_1_OVER_E : real := 0.36787_94411_71442_32160; -- 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846; -- pi
constant MATH_2_PI : real := 2.0 * MATH_PI; -- 2 * pi
constant MATH_1_OVER_PI : real := 0.31830_98861_83790_67154; -- 1/pi
constant MATH_PI_OVER_2 : real := 1.57079_63267_94896_61923; -- pi / 2
constant MATH_PI_OVER_4 : real := 0.78539_81633_97448_30962; -- pi / 4
constant MATH_LOG_OF_2 : real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- function declarations
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
attribute foreign of ceil : function is "VHPIDIRECT ceil";
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
attribute foreign of floor : function is "VHPIDIRECT floor";
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
attribute foreign of round : function is "VHPIDIRECT round";
-- returns integer FLOOR(X + 0.5) if X > 0;
-- return integer CEIL(X - 0.5) if X < 0
-- IAC: we are missing the function TRUNC
-- IAC: we are missing the function MOD
-- IAC: functions FMAX and FMIN should be renamed REALMAX and REALMIN
function FMAX (X, Y : real ) return real;
attribute foreign of fmax : function is "VHPIDIRECT fmax";
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
attribute foreign of fmin : function is "VHPIDIRECT fmin";
-- returns the algebraically smaller of X and Y
procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real);
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.
-- This random number generator is portable for 32-bit computers, and
-- it has period ~2.30584*(10**18) for each set of seed values.
--
-- For VHDL-1992, the seeds will be global variables, functions to
-- initialize their values (INIT_SEED) will be provided, and the UNIFORM
-- procedure call will be modified accordingly.
-- IAC: functions SRAND, RAND and GET_RAND_MAX should not be visible
function SRAND (seed: in integer ) return integer;
attribute foreign of srand : function is "VHPIDIRECT srand";
--
-- sets value of seed for sequence of
-- pseudo-random numbers.
-- It uses the foreign native C function srand().
function RAND return integer;
attribute foreign of rand : function is "VHPIDIRECT rand";
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the foreign native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
function GET_RAND_MAX return integer;
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent, and
-- it uses foreign native C functions or constants.
-- It may not be available in some platforms.
-- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- pseudo-random number distributed between 0 & 1.
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0
function CBRT (X : real ) return real;
attribute foreign of cbrt : function is "VHPIDIRECT cbrt";
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integer value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integer value
function EXP (X : real ) return real;
attribute foreign of exp : function is "VHPIDIRECT exp";
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (X: in real; BASE: in real) return real;
-- returns logarithm base BASE of X; X > 0
function LOG2 (X : in real ) return real;
-- returns logarithm base 2 of X; X > 0
function LOG10 (X : in real ) return real;
-- returns logarithm base 10 of X; X > 0
function SIN (X : real ) return real;
attribute foreign of sin : function is "VHPIDIRECT sin";
-- returns sin X; X in radians
function COS ( X : real ) return real;
attribute foreign of cos : function is "VHPIDIRECT cos";
-- returns cos X; X in radians
function TAN (X : real ) return real;
attribute foreign of tan : function is "VHPIDIRECT tan";
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
-- IAC: function should be called ARCSIN
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1
-- IAC: function should be called ARCCOS
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1
-- IAC: function should be called ARCTAN
function ATAN (X : real) return real;
attribute foreign of atan : function is "VHPIDIRECT atan";
-- returns -PI/2 < atan X < PI/2
-- IAC: function ATAN2 should not exist
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
attribute foreign of sinh : function is "VHPIDIRECT sinh";
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
attribute foreign of cosh : function is "VHPIDIRECT cosh";
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
attribute foreign of tanh : function is "VHPIDIRECT tanh";
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
-- IAC: function should be called ARCSINH
function ASINH (X : real) return real;
attribute foreign of asinh : function is "VHPIDIRECT asinh";
-- returns ln( X + sqrt( X**2 + 1))
-- IAC: function should be called ARCCOSH
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1
-- IAC: function should be called ARCTANH
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1
end MATH_REAL;
| gpl-2.0 | ede1f583374ca4e879c9583d3246a392 | 0.603945 | 3.707164 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/PSR_Modifier.vhd | 3 | 2,095 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0));
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(aluop,oper1,oper2,aluResult)
begin
if (aluop="010001" or aluop="010101" or aluop="010010" or aluop="010110" or aluop="010011" or aluop="010111") then -- ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<= '0'; --V
conditionalCodes(0)<= '0'; --C
elsif (aluop="010000" or aluop="011000") then --ADDcc, ADDXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and oper2(31) and (not aluResult(31))) or ((not oper1(31)) and (not oper2(31)) and aluResult(31));
conditionalCodes(0)<=(oper1(31) and oper2(31)) or ((not aluResult(31)) and (oper1(31) or oper2(31)));
elsif (aluop="010100" or aluop="011100") then --SUBcc, SUBXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and (not oper2(31)) and (not aluResult(31))) or ((not oper1(31)) and oper2(31) and aluResult(31));
conditionalCodes(0)<=((not oper1(31)) and oper2(31)) or (aluResult(31) and ((not oper1(31)) or oper2(31)));
end if;
end process;
end Behavioral; | gpl-3.0 | ba1490bf26cc4bfe9903b4df69892c38 | 0.626253 | 3.593482 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/Tbfirstpartnew.vhd | 2 | 2,778 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:28:33 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/Tbfirstpartnew.vhd
-- Project Name: secondooooooooo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: firstrpart
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tbfirstpartnew IS
END Tbfirstpartnew;
ARCHITECTURE behavior OF Tbfirstpartnew IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT firstrpart
PORT(
Resetext : IN std_logic;
Clkinext : IN std_logic;
Adressext : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Resetext : std_logic := '0';
signal Clkinext : std_logic := '0';
--Outputs
signal Adressext : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clkinext_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: firstrpart PORT MAP (
Resetext => Resetext,
Clkinext => Clkinext,
Adressext => Adressext
);
-- Clock process definitions
Clkinext_process :process
begin
Clkinext <= '0';
wait for Clkinext_period/2;
Clkinext <= '1';
wait for Clkinext_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Resetext <= '0';
wait for 100 ns;
Resetext <= '1';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
-- insert stimulus here
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 2e551342dadb64318294dd4423e82a0d | 0.588913 | 4.158683 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segundoprocesador19oct/RF.vhd | 1 | 1,377 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (39 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type;
begin
RAM(0)<= "00000000000000000000000000000000";
process (rst,rd,rs1,rs2,dwr,RAM)
begin
if rst = '1' then
RAM <= (others=>"00000000000000000000000000000000");
crs1 <="00000000000000000000000000000000";
crs2 <="00000000000000000000000000000000";
elsif rd /= "000000" then
RAM(conv_integer(rd)) <= dwr;
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
else
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
end if;
end process;
end Behavioral;
| gpl-3.0 | 39758d7add1127af390bb8d54f586a47 | 0.522876 | 4.05 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/MuxRF.vhd | 2 | 1,291 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:51:25 10/20/2017
-- Design Name:
-- Module Name: MuxRF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxRF is
Port ( Rd : in STD_LOGIC_VECTOR (5 downto 0);
O7 : in STD_LOGIC_VECTOR (5 downto 0);
RFDEST : in STD_LOGIC;
nRD : out STD_LOGIC_VECTOR (5 downto 0));
end MuxRF;
architecture Behavioral of MuxRF is
begin
process (Rd,O7,RFDEST) begin
case (RFDEST) is
when '0' =>
nRD <= Rd;
when '1' =>
nRD <= O7;
when others =>
nRD <= Rd;
end case;
end process;
end Behavioral;
| gpl-3.0 | 7a7a1d0b7b10b9a156392b9ee4c7bb0d | 0.567777 | 3.731214 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/synth/tri_intersect_ap_fsub_7_full_dsp_32.vhd | 1 | 12,685 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fsub_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fsub_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fsub_7_full_dsp_32_arch OF tri_intersect_ap_fsub_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fsub_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fsub_7_full_dsp_32_arch;
| mit | e8f5927157a48cedac897b677eda42ce | 0.65203 | 3.023838 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_mm2s_basic_wrap.vhd | 1 | 44,232 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_scc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_datamover_mm2s_basic_wrap;
architecture implementation of axi_datamover_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= "0000";--sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
-- sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
sig_mm2s_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32));
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_data2skid_wvalid ,
mm2s_strm_wready => sig_data2skid_wready ,
mm2s_strm_wdata => sig_data2skid_wdata ,
mm2s_strm_wstrb => sig_data2skid_wstrb ,
mm2s_strm_wlast => sig_data2skid_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_data2skid_wvalid ,
s_ready => sig_data2skid_wready ,
s_data => sig_data2skid_wdata ,
s_strb => sig_data2skid_wstrb ,
s_last => sig_data2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_data2skid_wvalid;
sig_data2skid_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_data2skid_wdata;
mm2s_strm_wstrb <= sig_data2skid_wstrb;
mm2s_strm_wlast <= sig_data2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
| mit | e583dc8453ebe7fabd29e2ba3c2fd2e0 | 0.44877 | 4.145843 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/hdl/system.vhd | 3 | 122,632 | -------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_wrapper is
port (
CAN0_PHY_TX : out std_logic;
CAN0_PHY_RX : in std_logic;
CAN1_PHY_TX : out std_logic;
CAN1_PHY_RX : in std_logic;
ENET0_GMII_TX_EN : out std_logic;
ENET0_GMII_TX_ER : out std_logic;
ENET0_MDIO_MDC : out std_logic;
ENET0_MDIO_O : out std_logic;
ENET0_MDIO_T : out std_logic;
ENET0_PTP_DELAY_REQ_RX : out std_logic;
ENET0_PTP_DELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_REQ_RX : out std_logic;
ENET0_PTP_PDELAY_REQ_TX : out std_logic;
ENET0_PTP_PDELAY_RESP_RX : out std_logic;
ENET0_PTP_PDELAY_RESP_TX : out std_logic;
ENET0_PTP_SYNC_FRAME_RX : out std_logic;
ENET0_PTP_SYNC_FRAME_TX : out std_logic;
ENET0_SOF_RX : out std_logic;
ENET0_SOF_TX : out std_logic;
ENET0_GMII_TXD : out std_logic_vector(7 downto 0);
ENET0_GMII_COL : in std_logic;
ENET0_GMII_CRS : in std_logic;
ENET0_EXT_INTIN : in std_logic;
ENET0_GMII_RX_CLK : in std_logic;
ENET0_GMII_RX_DV : in std_logic;
ENET0_GMII_RX_ER : in std_logic;
ENET0_GMII_TX_CLK : in std_logic;
ENET0_MDIO_I : in std_logic;
ENET0_GMII_RXD : in std_logic_vector(7 downto 0);
ENET1_GMII_TX_EN : out std_logic;
ENET1_GMII_TX_ER : out std_logic;
ENET1_MDIO_MDC : out std_logic;
ENET1_MDIO_O : out std_logic;
ENET1_MDIO_T : out std_logic;
ENET1_PTP_DELAY_REQ_RX : out std_logic;
ENET1_PTP_DELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_REQ_RX : out std_logic;
ENET1_PTP_PDELAY_REQ_TX : out std_logic;
ENET1_PTP_PDELAY_RESP_RX : out std_logic;
ENET1_PTP_PDELAY_RESP_TX : out std_logic;
ENET1_PTP_SYNC_FRAME_RX : out std_logic;
ENET1_PTP_SYNC_FRAME_TX : out std_logic;
ENET1_SOF_RX : out std_logic;
ENET1_SOF_TX : out std_logic;
ENET1_GMII_TXD : out std_logic_vector(7 downto 0);
ENET1_GMII_COL : in std_logic;
ENET1_GMII_CRS : in std_logic;
ENET1_EXT_INTIN : in std_logic;
ENET1_GMII_RX_CLK : in std_logic;
ENET1_GMII_RX_DV : in std_logic;
ENET1_GMII_RX_ER : in std_logic;
ENET1_GMII_TX_CLK : in std_logic;
ENET1_MDIO_I : in std_logic;
ENET1_GMII_RXD : in std_logic_vector(7 downto 0);
GPIO_I : in std_logic_vector(63 downto 0);
GPIO_O : out std_logic_vector(63 downto 0);
GPIO_T : out std_logic_vector(63 downto 0);
I2C0_SDA_I : in std_logic;
I2C0_SDA_O : out std_logic;
I2C0_SDA_T : out std_logic;
I2C0_SCL_I : in std_logic;
I2C0_SCL_O : out std_logic;
I2C0_SCL_T : out std_logic;
I2C1_SDA_I : in std_logic;
I2C1_SDA_O : out std_logic;
I2C1_SDA_T : out std_logic;
I2C1_SCL_I : in std_logic;
I2C1_SCL_O : out std_logic;
I2C1_SCL_T : out std_logic;
PJTAG_TCK : in std_logic;
PJTAG_TMS : in std_logic;
PJTAG_TD_I : in std_logic;
PJTAG_TD_T : out std_logic;
PJTAG_TD_O : out std_logic;
SDIO0_CLK : out std_logic;
SDIO0_CLK_FB : in std_logic;
SDIO0_CMD_O : out std_logic;
SDIO0_CMD_I : in std_logic;
SDIO0_CMD_T : out std_logic;
SDIO0_DATA_I : in std_logic_vector(3 downto 0);
SDIO0_DATA_O : out std_logic_vector(3 downto 0);
SDIO0_DATA_T : out std_logic_vector(3 downto 0);
SDIO0_LED : out std_logic;
SDIO0_CDN : in std_logic;
SDIO0_WP : in std_logic;
SDIO0_BUSPOW : out std_logic;
SDIO0_BUSVOLT : out std_logic_vector(2 downto 0);
SDIO1_CLK : out std_logic;
SDIO1_CLK_FB : in std_logic;
SDIO1_CMD_O : out std_logic;
SDIO1_CMD_I : in std_logic;
SDIO1_CMD_T : out std_logic;
SDIO1_DATA_I : in std_logic_vector(3 downto 0);
SDIO1_DATA_O : out std_logic_vector(3 downto 0);
SDIO1_DATA_T : out std_logic_vector(3 downto 0);
SDIO1_LED : out std_logic;
SDIO1_CDN : in std_logic;
SDIO1_WP : in std_logic;
SDIO1_BUSPOW : out std_logic;
SDIO1_BUSVOLT : out std_logic_vector(2 downto 0);
SPI0_SCLK_I : in std_logic;
SPI0_SCLK_O : out std_logic;
SPI0_SCLK_T : out std_logic;
SPI0_MOSI_I : in std_logic;
SPI0_MOSI_O : out std_logic;
SPI0_MOSI_T : out std_logic;
SPI0_MISO_I : in std_logic;
SPI0_MISO_O : out std_logic;
SPI0_MISO_T : out std_logic;
SPI0_SS_I : in std_logic;
SPI0_SS_O : out std_logic;
SPI0_SS1_O : out std_logic;
SPI0_SS2_O : out std_logic;
SPI0_SS_T : out std_logic;
SPI1_SCLK_I : in std_logic;
SPI1_SCLK_O : out std_logic;
SPI1_SCLK_T : out std_logic;
SPI1_MOSI_I : in std_logic;
SPI1_MOSI_O : out std_logic;
SPI1_MOSI_T : out std_logic;
SPI1_MISO_I : in std_logic;
SPI1_MISO_O : out std_logic;
SPI1_MISO_T : out std_logic;
SPI1_SS_I : in std_logic;
SPI1_SS_O : out std_logic;
SPI1_SS1_O : out std_logic;
SPI1_SS2_O : out std_logic;
SPI1_SS_T : out std_logic;
UART0_DTRN : out std_logic;
UART0_RTSN : out std_logic;
UART0_TX : out std_logic;
UART0_CTSN : in std_logic;
UART0_DCDN : in std_logic;
UART0_DSRN : in std_logic;
UART0_RIN : in std_logic;
UART0_RX : in std_logic;
UART1_DTRN : out std_logic;
UART1_RTSN : out std_logic;
UART1_TX : out std_logic;
UART1_CTSN : in std_logic;
UART1_DCDN : in std_logic;
UART1_DSRN : in std_logic;
UART1_RIN : in std_logic;
UART1_RX : in std_logic;
TTC0_WAVE0_OUT : out std_logic;
TTC0_WAVE1_OUT : out std_logic;
TTC0_WAVE2_OUT : out std_logic;
TTC0_CLK0_IN : in std_logic;
TTC0_CLK1_IN : in std_logic;
TTC0_CLK2_IN : in std_logic;
TTC1_WAVE0_OUT : out std_logic;
TTC1_WAVE1_OUT : out std_logic;
TTC1_WAVE2_OUT : out std_logic;
TTC1_CLK0_IN : in std_logic;
TTC1_CLK1_IN : in std_logic;
TTC1_CLK2_IN : in std_logic;
WDT_CLK_IN : in std_logic;
WDT_RST_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(31 downto 0);
USB0_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB1_PORT_INDCTL : out std_logic_vector(1 downto 0);
USB0_VBUS_PWRSELECT : out std_logic;
USB1_VBUS_PWRSELECT : out std_logic;
USB0_VBUS_PWRFAULT : in std_logic;
USB1_VBUS_PWRFAULT : in std_logic;
SRAM_INTIN : in std_logic;
M_AXI_GP0_ARESETN : out std_logic;
M_AXI_GP0_ARVALID : out std_logic;
M_AXI_GP0_AWVALID : out std_logic;
M_AXI_GP0_BREADY : out std_logic;
M_AXI_GP0_RREADY : out std_logic;
M_AXI_GP0_WLAST : out std_logic;
M_AXI_GP0_WVALID : out std_logic;
M_AXI_GP0_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP0_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP0_WID : out std_logic_vector(11 downto 0);
M_AXI_GP0_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP0_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP0_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP0_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP0_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP0_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP0_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP0_ACLK : in std_logic;
M_AXI_GP0_ARREADY : in std_logic;
M_AXI_GP0_AWREADY : in std_logic;
M_AXI_GP0_BVALID : in std_logic;
M_AXI_GP0_RLAST : in std_logic;
M_AXI_GP0_RVALID : in std_logic;
M_AXI_GP0_WREADY : in std_logic;
M_AXI_GP0_BID : in std_logic_vector(11 downto 0);
M_AXI_GP0_RID : in std_logic_vector(11 downto 0);
M_AXI_GP0_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP0_RDATA : in std_logic_vector(31 downto 0);
M_AXI_GP1_ARESETN : out std_logic;
M_AXI_GP1_ARVALID : out std_logic;
M_AXI_GP1_AWVALID : out std_logic;
M_AXI_GP1_BREADY : out std_logic;
M_AXI_GP1_RREADY : out std_logic;
M_AXI_GP1_WLAST : out std_logic;
M_AXI_GP1_WVALID : out std_logic;
M_AXI_GP1_ARID : out std_logic_vector(11 downto 0);
M_AXI_GP1_AWID : out std_logic_vector(11 downto 0);
M_AXI_GP1_WID : out std_logic_vector(11 downto 0);
M_AXI_GP1_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_GP1_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_GP1_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_GP1_WDATA : out std_logic_vector(31 downto 0);
M_AXI_GP1_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWLEN : out std_logic_vector(3 downto 0);
M_AXI_GP1_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_GP1_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_GP1_ACLK : in std_logic;
M_AXI_GP1_ARREADY : in std_logic;
M_AXI_GP1_AWREADY : in std_logic;
M_AXI_GP1_BVALID : in std_logic;
M_AXI_GP1_RLAST : in std_logic;
M_AXI_GP1_RVALID : in std_logic;
M_AXI_GP1_WREADY : in std_logic;
M_AXI_GP1_BID : in std_logic_vector(11 downto 0);
M_AXI_GP1_RID : in std_logic_vector(11 downto 0);
M_AXI_GP1_BRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RRESP : in std_logic_vector(1 downto 0);
M_AXI_GP1_RDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARESETN : out std_logic;
S_AXI_GP0_ARREADY : out std_logic;
S_AXI_GP0_AWREADY : out std_logic;
S_AXI_GP0_BVALID : out std_logic;
S_AXI_GP0_RLAST : out std_logic;
S_AXI_GP0_RVALID : out std_logic;
S_AXI_GP0_WREADY : out std_logic;
S_AXI_GP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP0_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP0_BID : out std_logic_vector(5 downto 0);
S_AXI_GP0_RID : out std_logic_vector(5 downto 0);
S_AXI_GP0_ACLK : in std_logic;
S_AXI_GP0_ARVALID : in std_logic;
S_AXI_GP0_AWVALID : in std_logic;
S_AXI_GP0_BREADY : in std_logic;
S_AXI_GP0_RREADY : in std_logic;
S_AXI_GP0_WLAST : in std_logic;
S_AXI_GP0_WVALID : in std_logic;
S_AXI_GP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP0_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP0_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP0_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP0_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP0_WID : in std_logic_vector(5 downto 0);
S_AXI_GP1_ARESETN : out std_logic;
S_AXI_GP1_ARREADY : out std_logic;
S_AXI_GP1_AWREADY : out std_logic;
S_AXI_GP1_BVALID : out std_logic;
S_AXI_GP1_RLAST : out std_logic;
S_AXI_GP1_RVALID : out std_logic;
S_AXI_GP1_WREADY : out std_logic;
S_AXI_GP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_GP1_RDATA : out std_logic_vector(31 downto 0);
S_AXI_GP1_BID : out std_logic_vector(5 downto 0);
S_AXI_GP1_RID : out std_logic_vector(5 downto 0);
S_AXI_GP1_ACLK : in std_logic;
S_AXI_GP1_ARVALID : in std_logic;
S_AXI_GP1_AWVALID : in std_logic;
S_AXI_GP1_BREADY : in std_logic;
S_AXI_GP1_RREADY : in std_logic;
S_AXI_GP1_WLAST : in std_logic;
S_AXI_GP1_WVALID : in std_logic;
S_AXI_GP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_GP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_GP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_GP1_WDATA : in std_logic_vector(31 downto 0);
S_AXI_GP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_GP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_GP1_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_GP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_GP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_GP1_WID : in std_logic_vector(5 downto 0);
S_AXI_ACP_ARESETN : out std_logic;
S_AXI_ACP_AWREADY : out std_logic;
S_AXI_ACP_ARREADY : out std_logic;
S_AXI_ACP_BVALID : out std_logic;
S_AXI_ACP_RLAST : out std_logic;
S_AXI_ACP_RVALID : out std_logic;
S_AXI_ACP_WREADY : out std_logic;
S_AXI_ACP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_ACP_BID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RID : out std_logic_vector(2 downto 0);
S_AXI_ACP_RDATA : out std_logic_vector(63 downto 0);
S_AXI_ACP_ACLK : in std_logic;
S_AXI_ACP_ARVALID : in std_logic;
S_AXI_ACP_AWVALID : in std_logic;
S_AXI_ACP_BREADY : in std_logic;
S_AXI_ACP_RREADY : in std_logic;
S_AXI_ACP_WLAST : in std_logic;
S_AXI_ACP_WVALID : in std_logic;
S_AXI_ACP_ARID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWID : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_ACP_WID : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_ACP_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_ACP_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_ACP_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_ACP_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_ACP_ARUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_AWUSER : in std_logic_vector(4 downto 0);
S_AXI_ACP_WDATA : in std_logic_vector(63 downto 0);
S_AXI_ACP_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP0_ARESETN : out std_logic;
S_AXI_HP0_ARREADY : out std_logic;
S_AXI_HP0_AWREADY : out std_logic;
S_AXI_HP0_BVALID : out std_logic;
S_AXI_HP0_RLAST : out std_logic;
S_AXI_HP0_RVALID : out std_logic;
S_AXI_HP0_WREADY : out std_logic;
S_AXI_HP0_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP0_BID : out std_logic_vector(0 to 0);
S_AXI_HP0_RID : out std_logic_vector(0 to 0);
S_AXI_HP0_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP0_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP0_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP0_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP0_ACLK : in std_logic;
S_AXI_HP0_ARVALID : in std_logic;
S_AXI_HP0_AWVALID : in std_logic;
S_AXI_HP0_BREADY : in std_logic;
S_AXI_HP0_RDISSUECAP1_EN : in std_logic;
S_AXI_HP0_RREADY : in std_logic;
S_AXI_HP0_WLAST : in std_logic;
S_AXI_HP0_WRISSUECAP1_EN : in std_logic;
S_AXI_HP0_WVALID : in std_logic;
S_AXI_HP0_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP0_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP0_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP0_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP0_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP0_ARID : in std_logic_vector(0 to 0);
S_AXI_HP0_AWID : in std_logic_vector(0 to 0);
S_AXI_HP0_WID : in std_logic_vector(0 to 0);
S_AXI_HP0_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP0_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP1_ARESETN : out std_logic;
S_AXI_HP1_ARREADY : out std_logic;
S_AXI_HP1_AWREADY : out std_logic;
S_AXI_HP1_BVALID : out std_logic;
S_AXI_HP1_RLAST : out std_logic;
S_AXI_HP1_RVALID : out std_logic;
S_AXI_HP1_WREADY : out std_logic;
S_AXI_HP1_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP1_BID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RID : out std_logic_vector(5 downto 0);
S_AXI_HP1_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP1_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP1_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP1_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP1_ACLK : in std_logic;
S_AXI_HP1_ARVALID : in std_logic;
S_AXI_HP1_AWVALID : in std_logic;
S_AXI_HP1_BREADY : in std_logic;
S_AXI_HP1_RDISSUECAP1_EN : in std_logic;
S_AXI_HP1_RREADY : in std_logic;
S_AXI_HP1_WLAST : in std_logic;
S_AXI_HP1_WRISSUECAP1_EN : in std_logic;
S_AXI_HP1_WVALID : in std_logic;
S_AXI_HP1_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP1_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP1_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP1_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP1_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP1_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP1_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WID : in std_logic_vector(5 downto 0);
S_AXI_HP1_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP1_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP2_ARESETN : out std_logic;
S_AXI_HP2_ARREADY : out std_logic;
S_AXI_HP2_AWREADY : out std_logic;
S_AXI_HP2_BVALID : out std_logic;
S_AXI_HP2_RLAST : out std_logic;
S_AXI_HP2_RVALID : out std_logic;
S_AXI_HP2_WREADY : out std_logic;
S_AXI_HP2_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP2_BID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RID : out std_logic_vector(5 downto 0);
S_AXI_HP2_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP2_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP2_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP2_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP2_ACLK : in std_logic;
S_AXI_HP2_ARVALID : in std_logic;
S_AXI_HP2_AWVALID : in std_logic;
S_AXI_HP2_BREADY : in std_logic;
S_AXI_HP2_RDISSUECAP1_EN : in std_logic;
S_AXI_HP2_RREADY : in std_logic;
S_AXI_HP2_WLAST : in std_logic;
S_AXI_HP2_WRISSUECAP1_EN : in std_logic;
S_AXI_HP2_WVALID : in std_logic;
S_AXI_HP2_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP2_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP2_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP2_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP2_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP2_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP2_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WID : in std_logic_vector(5 downto 0);
S_AXI_HP2_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP2_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_HP3_ARESETN : out std_logic;
S_AXI_HP3_ARREADY : out std_logic;
S_AXI_HP3_AWREADY : out std_logic;
S_AXI_HP3_BVALID : out std_logic;
S_AXI_HP3_RLAST : out std_logic;
S_AXI_HP3_RVALID : out std_logic;
S_AXI_HP3_WREADY : out std_logic;
S_AXI_HP3_BRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_RRESP : out std_logic_vector(1 downto 0);
S_AXI_HP3_BID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RID : out std_logic_vector(5 downto 0);
S_AXI_HP3_RDATA : out std_logic_vector(63 downto 0);
S_AXI_HP3_RCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_WCOUNT : out std_logic_vector(7 downto 0);
S_AXI_HP3_RACOUNT : out std_logic_vector(2 downto 0);
S_AXI_HP3_WACOUNT : out std_logic_vector(5 downto 0);
S_AXI_HP3_ACLK : in std_logic;
S_AXI_HP3_ARVALID : in std_logic;
S_AXI_HP3_AWVALID : in std_logic;
S_AXI_HP3_BREADY : in std_logic;
S_AXI_HP3_RDISSUECAP1_EN : in std_logic;
S_AXI_HP3_RREADY : in std_logic;
S_AXI_HP3_WLAST : in std_logic;
S_AXI_HP3_WRISSUECAP1_EN : in std_logic;
S_AXI_HP3_WVALID : in std_logic;
S_AXI_HP3_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_HP3_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_HP3_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_HP3_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWLEN : in std_logic_vector(3 downto 0);
S_AXI_HP3_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_HP3_ARID : in std_logic_vector(5 downto 0);
S_AXI_HP3_AWID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WID : in std_logic_vector(5 downto 0);
S_AXI_HP3_WDATA : in std_logic_vector(63 downto 0);
S_AXI_HP3_WSTRB : in std_logic_vector(7 downto 0);
DMA0_DATYPE : out std_logic_vector(1 downto 0);
DMA0_DAVALID : out std_logic;
DMA0_DRREADY : out std_logic;
DMA0_RSTN : out std_logic;
DMA0_ACLK : in std_logic;
DMA0_DAREADY : in std_logic;
DMA0_DRLAST : in std_logic;
DMA0_DRVALID : in std_logic;
DMA0_DRTYPE : in std_logic_vector(1 downto 0);
DMA1_DATYPE : out std_logic_vector(1 downto 0);
DMA1_DAVALID : out std_logic;
DMA1_DRREADY : out std_logic;
DMA1_RSTN : out std_logic;
DMA1_ACLK : in std_logic;
DMA1_DAREADY : in std_logic;
DMA1_DRLAST : in std_logic;
DMA1_DRVALID : in std_logic;
DMA1_DRTYPE : in std_logic_vector(1 downto 0);
DMA2_DATYPE : out std_logic_vector(1 downto 0);
DMA2_DAVALID : out std_logic;
DMA2_DRREADY : out std_logic;
DMA2_RSTN : out std_logic;
DMA2_ACLK : in std_logic;
DMA2_DAREADY : in std_logic;
DMA2_DRLAST : in std_logic;
DMA2_DRVALID : in std_logic;
DMA3_DRVALID : in std_logic;
DMA3_DATYPE : out std_logic_vector(1 downto 0);
DMA3_DAVALID : out std_logic;
DMA3_DRREADY : out std_logic;
DMA3_RSTN : out std_logic;
DMA3_ACLK : in std_logic;
DMA3_DAREADY : in std_logic;
DMA3_DRLAST : in std_logic;
DMA2_DRTYPE : in std_logic_vector(1 downto 0);
DMA3_DRTYPE : in std_logic_vector(1 downto 0);
FTMD_TRACEIN_DATA : in std_logic_vector(31 downto 0);
FTMD_TRACEIN_VALID : in std_logic;
FTMD_TRACEIN_CLK : in std_logic;
FTMD_TRACEIN_ATID : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIG : in std_logic_vector(3 downto 0);
FTMT_F2P_TRIGACK : out std_logic_vector(3 downto 0);
FTMT_F2P_DEBUG : in std_logic_vector(31 downto 0);
FTMT_P2F_TRIGACK : in std_logic_vector(3 downto 0);
FTMT_P2F_TRIG : out std_logic_vector(3 downto 0);
FTMT_P2F_DEBUG : out std_logic_vector(31 downto 0);
FCLK_CLK3 : out std_logic;
FCLK_CLK2 : out std_logic;
FCLK_CLK1 : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_CLKTRIG3_N : in std_logic;
FCLK_CLKTRIG2_N : in std_logic;
FCLK_CLKTRIG1_N : in std_logic;
FCLK_CLKTRIG0_N : in std_logic;
FCLK_RESET3_N : out std_logic;
FCLK_RESET2_N : out std_logic;
FCLK_RESET1_N : out std_logic;
FCLK_RESET0_N : out std_logic;
FPGA_IDLE_N : in std_logic;
DDR_ARB : in std_logic_vector(3 downto 0);
IRQ_F2P : in std_logic_vector(1 downto 0);
Core0_nFIQ : in std_logic;
Core0_nIRQ : in std_logic;
Core1_nFIQ : in std_logic;
Core1_nIRQ : in std_logic;
EVENT_EVENTO : out std_logic;
EVENT_STANDBYWFE : out std_logic_vector(1 downto 0);
EVENT_STANDBYWFI : out std_logic_vector(1 downto 0);
EVENT_EVENTI : in std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_Clk : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_CAS_n : inout std_logic;
DDR_WEB : out std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_ODT : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
PS_SRSTB : in std_logic;
PS_CLK : in std_logic;
PS_PORB : in std_logic;
IRQ_P2F_DMAC_ABORT : out std_logic;
IRQ_P2F_DMAC0 : out std_logic;
IRQ_P2F_DMAC1 : out std_logic;
IRQ_P2F_DMAC2 : out std_logic;
IRQ_P2F_DMAC3 : out std_logic;
IRQ_P2F_DMAC4 : out std_logic;
IRQ_P2F_DMAC5 : out std_logic;
IRQ_P2F_DMAC6 : out std_logic;
IRQ_P2F_DMAC7 : out std_logic;
IRQ_P2F_SMC : out std_logic;
IRQ_P2F_QSPI : out std_logic;
IRQ_P2F_CTI : out std_logic;
IRQ_P2F_GPIO : out std_logic;
IRQ_P2F_USB0 : out std_logic;
IRQ_P2F_ENET0 : out std_logic;
IRQ_P2F_ENET_WAKE0 : out std_logic;
IRQ_P2F_SDIO0 : out std_logic;
IRQ_P2F_I2C0 : out std_logic;
IRQ_P2F_SPI0 : out std_logic;
IRQ_P2F_UART0 : out std_logic;
IRQ_P2F_CAN0 : out std_logic;
IRQ_P2F_USB1 : out std_logic;
IRQ_P2F_ENET1 : out std_logic;
IRQ_P2F_ENET_WAKE1 : out std_logic;
IRQ_P2F_SDIO1 : out std_logic;
IRQ_P2F_I2C1 : out std_logic;
IRQ_P2F_SPI1 : out std_logic;
IRQ_P2F_UART1 : out std_logic;
IRQ_P2F_CAN1 : out std_logic
);
end component;
component system_axi_dispctrl_0_wrapper is
port (
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(7 downto 0);
GREEN_O : out std_logic_vector(7 downto 0);
BLUE_O : out std_logic_vector(7 downto 0);
ENABLE_O : out std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TLAST : in std_logic;
S_AXIS_TSTRB : in std_logic_vector(3 downto 0)
);
end component;
component system_axi_interconnect_1_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(1 downto 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(11 downto 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(11 downto 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(11 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(11 downto 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(11 downto 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(1 downto 0);
M_AXI_AWID : out std_logic_vector(23 downto 0);
M_AXI_AWADDR : out std_logic_vector(63 downto 0);
M_AXI_AWLEN : out std_logic_vector(15 downto 0);
M_AXI_AWSIZE : out std_logic_vector(5 downto 0);
M_AXI_AWBURST : out std_logic_vector(3 downto 0);
M_AXI_AWLOCK : out std_logic_vector(3 downto 0);
M_AXI_AWCACHE : out std_logic_vector(7 downto 0);
M_AXI_AWPROT : out std_logic_vector(5 downto 0);
M_AXI_AWREGION : out std_logic_vector(7 downto 0);
M_AXI_AWQOS : out std_logic_vector(7 downto 0);
M_AXI_AWUSER : out std_logic_vector(1 downto 0);
M_AXI_AWVALID : out std_logic_vector(1 downto 0);
M_AXI_AWREADY : in std_logic_vector(1 downto 0);
M_AXI_WID : out std_logic_vector(23 downto 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(1 downto 0);
M_AXI_WUSER : out std_logic_vector(1 downto 0);
M_AXI_WVALID : out std_logic_vector(1 downto 0);
M_AXI_WREADY : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(23 downto 0);
M_AXI_BRESP : in std_logic_vector(3 downto 0);
M_AXI_BUSER : in std_logic_vector(1 downto 0);
M_AXI_BVALID : in std_logic_vector(1 downto 0);
M_AXI_BREADY : out std_logic_vector(1 downto 0);
M_AXI_ARID : out std_logic_vector(23 downto 0);
M_AXI_ARADDR : out std_logic_vector(63 downto 0);
M_AXI_ARLEN : out std_logic_vector(15 downto 0);
M_AXI_ARSIZE : out std_logic_vector(5 downto 0);
M_AXI_ARBURST : out std_logic_vector(3 downto 0);
M_AXI_ARLOCK : out std_logic_vector(3 downto 0);
M_AXI_ARCACHE : out std_logic_vector(7 downto 0);
M_AXI_ARPROT : out std_logic_vector(5 downto 0);
M_AXI_ARREGION : out std_logic_vector(7 downto 0);
M_AXI_ARQOS : out std_logic_vector(7 downto 0);
M_AXI_ARUSER : out std_logic_vector(1 downto 0);
M_AXI_ARVALID : out std_logic_vector(1 downto 0);
M_AXI_ARREADY : in std_logic_vector(1 downto 0);
M_AXI_RID : in std_logic_vector(23 downto 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(3 downto 0);
M_AXI_RLAST : in std_logic_vector(1 downto 0);
M_AXI_RUSER : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic_vector(1 downto 0);
M_AXI_RREADY : out std_logic_vector(1 downto 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(15 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(15 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(34 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(15 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(16 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
component system_axi_interconnect_2_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(0 to 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(0 to 0);
S_AXI_WDATA : in std_logic_vector(63 downto 0);
S_AXI_WSTRB : in std_logic_vector(7 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(0 to 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(0 to 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(0 to 0);
S_AXI_RDATA : out std_logic_vector(63 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(0 to 0);
M_AXI_AWID : out std_logic_vector(0 to 0);
M_AXI_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWREGION : out std_logic_vector(3 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(0 to 0);
M_AXI_AWVALID : out std_logic_vector(0 to 0);
M_AXI_AWREADY : in std_logic_vector(0 to 0);
M_AXI_WID : out std_logic_vector(0 to 0);
M_AXI_WDATA : out std_logic_vector(63 downto 0);
M_AXI_WSTRB : out std_logic_vector(7 downto 0);
M_AXI_WLAST : out std_logic_vector(0 to 0);
M_AXI_WUSER : out std_logic_vector(0 to 0);
M_AXI_WVALID : out std_logic_vector(0 to 0);
M_AXI_WREADY : in std_logic_vector(0 to 0);
M_AXI_BID : in std_logic_vector(0 to 0);
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BUSER : in std_logic_vector(0 to 0);
M_AXI_BVALID : in std_logic_vector(0 to 0);
M_AXI_BREADY : out std_logic_vector(0 to 0);
M_AXI_ARID : out std_logic_vector(0 to 0);
M_AXI_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARREGION : out std_logic_vector(3 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARUSER : out std_logic_vector(0 to 0);
M_AXI_ARVALID : out std_logic_vector(0 to 0);
M_AXI_ARREADY : in std_logic_vector(0 to 0);
M_AXI_RID : in std_logic_vector(0 to 0);
M_AXI_RDATA : in std_logic_vector(63 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic_vector(0 to 0);
M_AXI_RUSER : in std_logic_vector(0 to 0);
M_AXI_RVALID : in std_logic_vector(0 to 0);
M_AXI_RREADY : out std_logic_vector(0 to 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(63 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(63 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(10 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(63 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(10 downto 0)
);
end component;
component IOBUF is
port (
I : in std_logic;
IO : inout std_logic;
O : out std_logic;
T : in std_logic
);
end component;
-- Internal signals
signal axi_dispctrl_0_BLUE_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_DE_O : std_logic;
signal axi_dispctrl_0_ENABLE_O : std_logic;
signal axi_dispctrl_0_FSYNC_O : std_logic;
signal axi_dispctrl_0_GREEN_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_HSYNC_O : std_logic;
signal axi_dispctrl_0_PXL_CLK_O : std_logic;
signal axi_dispctrl_0_RED_O : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_VDMA_CLK_O : std_logic;
signal axi_dispctrl_0_VSYNC_O : std_logic;
signal axi_interconnect_1_M_ARADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_ARESETN : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_ARVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWADDR : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_AWREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_AWVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_BRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_BVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_RREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_RRESP : std_logic_vector(3 downto 0);
signal axi_interconnect_1_M_RVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_1_M_WREADY : std_logic_vector(1 downto 0);
signal axi_interconnect_1_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_1_M_WVALID : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_1_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_1_S_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_RID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_1_S_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WDATA : std_logic_vector(31 downto 0);
signal axi_interconnect_1_S_WID : std_logic_vector(11 downto 0);
signal axi_interconnect_1_S_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_1_S_WSTRB : std_logic_vector(3 downto 0);
signal axi_interconnect_1_S_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_M_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_ARID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_ARLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_ARQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_M_AWBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_AWCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_AWID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_AWLOCK : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_AWPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_AWQOS : std_logic_vector(3 downto 0);
signal axi_interconnect_2_M_AWREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_AWSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_M_AWVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_BRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_BVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_M_RID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_M_RVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_M_WID : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_M_WSTRB : std_logic_vector(7 downto 0);
signal axi_interconnect_2_M_WVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_ARADDR : std_logic_vector(31 downto 0);
signal axi_interconnect_2_S_ARBURST : std_logic_vector(1 downto 0);
signal axi_interconnect_2_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi_interconnect_2_S_ARLEN : std_logic_vector(7 downto 0);
signal axi_interconnect_2_S_ARPROT : std_logic_vector(2 downto 0);
signal axi_interconnect_2_S_ARREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi_interconnect_2_S_ARVALID : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RDATA : std_logic_vector(63 downto 0);
signal axi_interconnect_2_S_RLAST : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RREADY : std_logic_vector(0 to 0);
signal axi_interconnect_2_S_RRESP : std_logic_vector(1 downto 0);
signal axi_interconnect_2_S_RVALID : std_logic_vector(0 to 0);
signal axi_vdma_0_M_AXIS_MM2S_TKEEP : std_logic_vector(3 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tdata : std_logic_vector(31 downto 0);
signal axi_vdma_0_M_AXIS_MM2S_tlast : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tready : std_logic;
signal axi_vdma_0_M_AXIS_MM2S_tvalid : std_logic;
signal axi_vdma_0_mm2s_introut : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(2 downto 0);
signal net_gnd4 : std_logic_vector(3 downto 0);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd6 : std_logic_vector(5 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd12 : std_logic_vector(11 downto 0);
signal net_gnd24 : std_logic_vector(23 downto 0);
signal net_gnd32 : std_logic_vector(31 downto 0);
signal net_gnd64 : std_logic_vector(63 downto 0);
signal net_vcc0 : std_logic;
signal net_vcc4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(1 downto 0);
signal pgassign2 : std_logic_vector(1 downto 0);
signal processing_system7_0_DDR_WEB : std_logic;
signal processing_system7_0_FCLK_CLK0 : std_logic_vector(0 to 0);
signal processing_system7_0_FCLK_RESET0_N : std_logic;
signal processing_system7_0_I2C0_INT_N : std_logic;
signal processing_system7_0_I2C0_SCL_I : std_logic;
signal processing_system7_0_I2C0_SCL_O : std_logic;
signal processing_system7_0_I2C0_SCL_T : std_logic;
signal processing_system7_0_I2C0_SDA_I : std_logic;
signal processing_system7_0_I2C0_SDA_O : std_logic;
signal processing_system7_0_I2C0_SDA_T : std_logic;
signal processing_system7_0_PS_CLK : std_logic;
signal processing_system7_0_PS_PORB : std_logic;
signal processing_system7_0_PS_SRSTB : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_processing_system7_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_dispctrl_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_vdma_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi_interconnect_2_wrapper : component is "user_black_box";
begin
-- Internal assignments
processing_system7_0_PS_SRSTB <= processing_system7_0_PS_SRSTB_pin;
processing_system7_0_PS_CLK <= processing_system7_0_PS_CLK_pin;
processing_system7_0_PS_PORB <= processing_system7_0_PS_PORB_pin;
processing_system7_0_DDR_WEB_pin <= processing_system7_0_DDR_WEB;
axi_dispctrl_0_HSYNC_O_pin <= axi_dispctrl_0_HSYNC_O;
axi_dispctrl_0_VSYNC_O_pin <= axi_dispctrl_0_VSYNC_O;
axi_dispctrl_0_PXL_CLK_O_pin <= axi_dispctrl_0_PXL_CLK_O;
axi_dispctrl_0_DE_O_pin <= axi_dispctrl_0_DE_O;
axi_dispctrl_0_RED_O_pin <= axi_dispctrl_0_RED_O;
axi_dispctrl_0_GREEN_O_pin <= axi_dispctrl_0_GREEN_O;
axi_dispctrl_0_BLUE_O_pin <= axi_dispctrl_0_BLUE_O;
axi_dispctrl_0_ENABLE_O_pin <= axi_dispctrl_0_ENABLE_O;
processing_system7_0_I2C0_INT_N <= processing_system7_0_I2C0_INT_N_pin;
processing_system7_0_FCLK_CLK0_pin <= processing_system7_0_FCLK_CLK0(0);
pgassign1(1) <= axi_vdma_0_mm2s_introut;
pgassign1(0) <= processing_system7_0_I2C0_INT_N;
pgassign2(1 downto 1) <= processing_system7_0_FCLK_CLK0(0 to 0);
pgassign2(0 downto 0) <= processing_system7_0_FCLK_CLK0(0 to 0);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd12(11 downto 0) <= B"000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd24(23 downto 0) <= B"000000000000000000000000";
net_gnd3(2 downto 0) <= B"000";
net_gnd32(31 downto 0) <= B"00000000000000000000000000000000";
net_gnd4(3 downto 0) <= B"0000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd6(5 downto 0) <= B"000000";
net_gnd64(63 downto 0) <= B"0000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(7 downto 0) <= B"00000000";
net_vcc0 <= '1';
net_vcc4(3 downto 0) <= B"1111";
processing_system7_0 : system_processing_system7_0_wrapper
port map (
CAN0_PHY_TX => open,
CAN0_PHY_RX => net_gnd0,
CAN1_PHY_TX => open,
CAN1_PHY_RX => net_gnd0,
ENET0_GMII_TX_EN => open,
ENET0_GMII_TX_ER => open,
ENET0_MDIO_MDC => open,
ENET0_MDIO_O => open,
ENET0_MDIO_T => open,
ENET0_PTP_DELAY_REQ_RX => open,
ENET0_PTP_DELAY_REQ_TX => open,
ENET0_PTP_PDELAY_REQ_RX => open,
ENET0_PTP_PDELAY_REQ_TX => open,
ENET0_PTP_PDELAY_RESP_RX => open,
ENET0_PTP_PDELAY_RESP_TX => open,
ENET0_PTP_SYNC_FRAME_RX => open,
ENET0_PTP_SYNC_FRAME_TX => open,
ENET0_SOF_RX => open,
ENET0_SOF_TX => open,
ENET0_GMII_TXD => open,
ENET0_GMII_COL => net_gnd0,
ENET0_GMII_CRS => net_gnd0,
ENET0_EXT_INTIN => net_gnd0,
ENET0_GMII_RX_CLK => net_gnd0,
ENET0_GMII_RX_DV => net_gnd0,
ENET0_GMII_RX_ER => net_gnd0,
ENET0_GMII_TX_CLK => net_gnd0,
ENET0_MDIO_I => net_gnd0,
ENET0_GMII_RXD => net_gnd8,
ENET1_GMII_TX_EN => open,
ENET1_GMII_TX_ER => open,
ENET1_MDIO_MDC => open,
ENET1_MDIO_O => open,
ENET1_MDIO_T => open,
ENET1_PTP_DELAY_REQ_RX => open,
ENET1_PTP_DELAY_REQ_TX => open,
ENET1_PTP_PDELAY_REQ_RX => open,
ENET1_PTP_PDELAY_REQ_TX => open,
ENET1_PTP_PDELAY_RESP_RX => open,
ENET1_PTP_PDELAY_RESP_TX => open,
ENET1_PTP_SYNC_FRAME_RX => open,
ENET1_PTP_SYNC_FRAME_TX => open,
ENET1_SOF_RX => open,
ENET1_SOF_TX => open,
ENET1_GMII_TXD => open,
ENET1_GMII_COL => net_gnd0,
ENET1_GMII_CRS => net_gnd0,
ENET1_EXT_INTIN => net_gnd0,
ENET1_GMII_RX_CLK => net_gnd0,
ENET1_GMII_RX_DV => net_gnd0,
ENET1_GMII_RX_ER => net_gnd0,
ENET1_GMII_TX_CLK => net_gnd0,
ENET1_MDIO_I => net_gnd0,
ENET1_GMII_RXD => net_gnd8,
GPIO_I => net_gnd64,
GPIO_O => open,
GPIO_T => open,
I2C0_SDA_I => processing_system7_0_I2C0_SDA_I,
I2C0_SDA_O => processing_system7_0_I2C0_SDA_O,
I2C0_SDA_T => processing_system7_0_I2C0_SDA_T,
I2C0_SCL_I => processing_system7_0_I2C0_SCL_I,
I2C0_SCL_O => processing_system7_0_I2C0_SCL_O,
I2C0_SCL_T => processing_system7_0_I2C0_SCL_T,
I2C1_SDA_I => net_gnd0,
I2C1_SDA_O => open,
I2C1_SDA_T => open,
I2C1_SCL_I => net_gnd0,
I2C1_SCL_O => open,
I2C1_SCL_T => open,
PJTAG_TCK => net_gnd0,
PJTAG_TMS => net_gnd0,
PJTAG_TD_I => net_gnd0,
PJTAG_TD_T => open,
PJTAG_TD_O => open,
SDIO0_CLK => open,
SDIO0_CLK_FB => net_gnd0,
SDIO0_CMD_O => open,
SDIO0_CMD_I => net_gnd0,
SDIO0_CMD_T => open,
SDIO0_DATA_I => net_gnd4,
SDIO0_DATA_O => open,
SDIO0_DATA_T => open,
SDIO0_LED => open,
SDIO0_CDN => net_gnd0,
SDIO0_WP => net_gnd0,
SDIO0_BUSPOW => open,
SDIO0_BUSVOLT => open,
SDIO1_CLK => open,
SDIO1_CLK_FB => net_gnd0,
SDIO1_CMD_O => open,
SDIO1_CMD_I => net_gnd0,
SDIO1_CMD_T => open,
SDIO1_DATA_I => net_gnd4,
SDIO1_DATA_O => open,
SDIO1_DATA_T => open,
SDIO1_LED => open,
SDIO1_CDN => net_gnd0,
SDIO1_WP => net_gnd0,
SDIO1_BUSPOW => open,
SDIO1_BUSVOLT => open,
SPI0_SCLK_I => net_gnd0,
SPI0_SCLK_O => open,
SPI0_SCLK_T => open,
SPI0_MOSI_I => net_gnd0,
SPI0_MOSI_O => open,
SPI0_MOSI_T => open,
SPI0_MISO_I => net_gnd0,
SPI0_MISO_O => open,
SPI0_MISO_T => open,
SPI0_SS_I => net_gnd0,
SPI0_SS_O => open,
SPI0_SS1_O => open,
SPI0_SS2_O => open,
SPI0_SS_T => open,
SPI1_SCLK_I => net_gnd0,
SPI1_SCLK_O => open,
SPI1_SCLK_T => open,
SPI1_MOSI_I => net_gnd0,
SPI1_MOSI_O => open,
SPI1_MOSI_T => open,
SPI1_MISO_I => net_gnd0,
SPI1_MISO_O => open,
SPI1_MISO_T => open,
SPI1_SS_I => net_gnd0,
SPI1_SS_O => open,
SPI1_SS1_O => open,
SPI1_SS2_O => open,
SPI1_SS_T => open,
UART0_DTRN => open,
UART0_RTSN => open,
UART0_TX => open,
UART0_CTSN => net_gnd0,
UART0_DCDN => net_gnd0,
UART0_DSRN => net_gnd0,
UART0_RIN => net_gnd0,
UART0_RX => net_gnd0,
UART1_DTRN => open,
UART1_RTSN => open,
UART1_TX => open,
UART1_CTSN => net_gnd0,
UART1_DCDN => net_gnd0,
UART1_DSRN => net_gnd0,
UART1_RIN => net_gnd0,
UART1_RX => net_gnd0,
TTC0_WAVE0_OUT => open,
TTC0_WAVE1_OUT => open,
TTC0_WAVE2_OUT => open,
TTC0_CLK0_IN => net_gnd0,
TTC0_CLK1_IN => net_gnd0,
TTC0_CLK2_IN => net_gnd0,
TTC1_WAVE0_OUT => open,
TTC1_WAVE1_OUT => open,
TTC1_WAVE2_OUT => open,
TTC1_CLK0_IN => net_gnd0,
TTC1_CLK1_IN => net_gnd0,
TTC1_CLK2_IN => net_gnd0,
WDT_CLK_IN => net_gnd0,
WDT_RST_OUT => open,
TRACE_CLK => net_gnd0,
TRACE_CTL => open,
TRACE_DATA => open,
USB0_PORT_INDCTL => open,
USB1_PORT_INDCTL => open,
USB0_VBUS_PWRSELECT => open,
USB1_VBUS_PWRSELECT => open,
USB0_VBUS_PWRFAULT => net_gnd0,
USB1_VBUS_PWRFAULT => net_gnd0,
SRAM_INTIN => net_gnd0,
M_AXI_GP0_ARESETN => open,
M_AXI_GP0_ARVALID => axi_interconnect_1_S_ARVALID(0),
M_AXI_GP0_AWVALID => axi_interconnect_1_S_AWVALID(0),
M_AXI_GP0_BREADY => axi_interconnect_1_S_BREADY(0),
M_AXI_GP0_RREADY => axi_interconnect_1_S_RREADY(0),
M_AXI_GP0_WLAST => axi_interconnect_1_S_WLAST(0),
M_AXI_GP0_WVALID => axi_interconnect_1_S_WVALID(0),
M_AXI_GP0_ARID => axi_interconnect_1_S_ARID,
M_AXI_GP0_AWID => axi_interconnect_1_S_AWID,
M_AXI_GP0_WID => axi_interconnect_1_S_WID,
M_AXI_GP0_ARBURST => axi_interconnect_1_S_ARBURST,
M_AXI_GP0_ARLOCK => axi_interconnect_1_S_ARLOCK,
M_AXI_GP0_ARSIZE => axi_interconnect_1_S_ARSIZE,
M_AXI_GP0_AWBURST => axi_interconnect_1_S_AWBURST,
M_AXI_GP0_AWLOCK => axi_interconnect_1_S_AWLOCK,
M_AXI_GP0_AWSIZE => axi_interconnect_1_S_AWSIZE,
M_AXI_GP0_ARPROT => axi_interconnect_1_S_ARPROT,
M_AXI_GP0_AWPROT => axi_interconnect_1_S_AWPROT,
M_AXI_GP0_ARADDR => axi_interconnect_1_S_ARADDR,
M_AXI_GP0_AWADDR => axi_interconnect_1_S_AWADDR,
M_AXI_GP0_WDATA => axi_interconnect_1_S_WDATA,
M_AXI_GP0_ARCACHE => axi_interconnect_1_S_ARCACHE,
M_AXI_GP0_ARLEN => axi_interconnect_1_S_ARLEN(3 downto 0),
M_AXI_GP0_ARQOS => axi_interconnect_1_S_ARQOS,
M_AXI_GP0_AWCACHE => axi_interconnect_1_S_AWCACHE,
M_AXI_GP0_AWLEN => axi_interconnect_1_S_AWLEN(3 downto 0),
M_AXI_GP0_AWQOS => axi_interconnect_1_S_AWQOS,
M_AXI_GP0_WSTRB => axi_interconnect_1_S_WSTRB,
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0(0),
M_AXI_GP0_ARREADY => axi_interconnect_1_S_ARREADY(0),
M_AXI_GP0_AWREADY => axi_interconnect_1_S_AWREADY(0),
M_AXI_GP0_BVALID => axi_interconnect_1_S_BVALID(0),
M_AXI_GP0_RLAST => axi_interconnect_1_S_RLAST(0),
M_AXI_GP0_RVALID => axi_interconnect_1_S_RVALID(0),
M_AXI_GP0_WREADY => axi_interconnect_1_S_WREADY(0),
M_AXI_GP0_BID => axi_interconnect_1_S_BID,
M_AXI_GP0_RID => axi_interconnect_1_S_RID,
M_AXI_GP0_BRESP => axi_interconnect_1_S_BRESP,
M_AXI_GP0_RRESP => axi_interconnect_1_S_RRESP,
M_AXI_GP0_RDATA => axi_interconnect_1_S_RDATA,
M_AXI_GP1_ARESETN => open,
M_AXI_GP1_ARVALID => open,
M_AXI_GP1_AWVALID => open,
M_AXI_GP1_BREADY => open,
M_AXI_GP1_RREADY => open,
M_AXI_GP1_WLAST => open,
M_AXI_GP1_WVALID => open,
M_AXI_GP1_ARID => open,
M_AXI_GP1_AWID => open,
M_AXI_GP1_WID => open,
M_AXI_GP1_ARBURST => open,
M_AXI_GP1_ARLOCK => open,
M_AXI_GP1_ARSIZE => open,
M_AXI_GP1_AWBURST => open,
M_AXI_GP1_AWLOCK => open,
M_AXI_GP1_AWSIZE => open,
M_AXI_GP1_ARPROT => open,
M_AXI_GP1_AWPROT => open,
M_AXI_GP1_ARADDR => open,
M_AXI_GP1_AWADDR => open,
M_AXI_GP1_WDATA => open,
M_AXI_GP1_ARCACHE => open,
M_AXI_GP1_ARLEN => open,
M_AXI_GP1_ARQOS => open,
M_AXI_GP1_AWCACHE => open,
M_AXI_GP1_AWLEN => open,
M_AXI_GP1_AWQOS => open,
M_AXI_GP1_WSTRB => open,
M_AXI_GP1_ACLK => net_gnd0,
M_AXI_GP1_ARREADY => net_gnd0,
M_AXI_GP1_AWREADY => net_gnd0,
M_AXI_GP1_BVALID => net_gnd0,
M_AXI_GP1_RLAST => net_gnd0,
M_AXI_GP1_RVALID => net_gnd0,
M_AXI_GP1_WREADY => net_gnd0,
M_AXI_GP1_BID => net_gnd12,
M_AXI_GP1_RID => net_gnd12,
M_AXI_GP1_BRESP => net_gnd2,
M_AXI_GP1_RRESP => net_gnd2,
M_AXI_GP1_RDATA => net_gnd32,
S_AXI_GP0_ARESETN => open,
S_AXI_GP0_ARREADY => open,
S_AXI_GP0_AWREADY => open,
S_AXI_GP0_BVALID => open,
S_AXI_GP0_RLAST => open,
S_AXI_GP0_RVALID => open,
S_AXI_GP0_WREADY => open,
S_AXI_GP0_BRESP => open,
S_AXI_GP0_RRESP => open,
S_AXI_GP0_RDATA => open,
S_AXI_GP0_BID => open,
S_AXI_GP0_RID => open,
S_AXI_GP0_ACLK => net_gnd0,
S_AXI_GP0_ARVALID => net_gnd0,
S_AXI_GP0_AWVALID => net_gnd0,
S_AXI_GP0_BREADY => net_gnd0,
S_AXI_GP0_RREADY => net_gnd0,
S_AXI_GP0_WLAST => net_gnd0,
S_AXI_GP0_WVALID => net_gnd0,
S_AXI_GP0_ARBURST => net_gnd2,
S_AXI_GP0_ARLOCK => net_gnd2,
S_AXI_GP0_ARSIZE => net_gnd3,
S_AXI_GP0_AWBURST => net_gnd2,
S_AXI_GP0_AWLOCK => net_gnd2,
S_AXI_GP0_AWSIZE => net_gnd3,
S_AXI_GP0_ARPROT => net_gnd3,
S_AXI_GP0_AWPROT => net_gnd3,
S_AXI_GP0_ARADDR => net_gnd32,
S_AXI_GP0_AWADDR => net_gnd32,
S_AXI_GP0_WDATA => net_gnd32,
S_AXI_GP0_ARCACHE => net_gnd4,
S_AXI_GP0_ARLEN => net_gnd4,
S_AXI_GP0_ARQOS => net_gnd4,
S_AXI_GP0_AWCACHE => net_gnd4,
S_AXI_GP0_AWLEN => net_gnd4,
S_AXI_GP0_AWQOS => net_gnd4,
S_AXI_GP0_WSTRB => net_gnd4,
S_AXI_GP0_ARID => net_gnd6,
S_AXI_GP0_AWID => net_gnd6,
S_AXI_GP0_WID => net_gnd6,
S_AXI_GP1_ARESETN => open,
S_AXI_GP1_ARREADY => open,
S_AXI_GP1_AWREADY => open,
S_AXI_GP1_BVALID => open,
S_AXI_GP1_RLAST => open,
S_AXI_GP1_RVALID => open,
S_AXI_GP1_WREADY => open,
S_AXI_GP1_BRESP => open,
S_AXI_GP1_RRESP => open,
S_AXI_GP1_RDATA => open,
S_AXI_GP1_BID => open,
S_AXI_GP1_RID => open,
S_AXI_GP1_ACLK => net_gnd0,
S_AXI_GP1_ARVALID => net_gnd0,
S_AXI_GP1_AWVALID => net_gnd0,
S_AXI_GP1_BREADY => net_gnd0,
S_AXI_GP1_RREADY => net_gnd0,
S_AXI_GP1_WLAST => net_gnd0,
S_AXI_GP1_WVALID => net_gnd0,
S_AXI_GP1_ARBURST => net_gnd2,
S_AXI_GP1_ARLOCK => net_gnd2,
S_AXI_GP1_ARSIZE => net_gnd3,
S_AXI_GP1_AWBURST => net_gnd2,
S_AXI_GP1_AWLOCK => net_gnd2,
S_AXI_GP1_AWSIZE => net_gnd3,
S_AXI_GP1_ARPROT => net_gnd3,
S_AXI_GP1_AWPROT => net_gnd3,
S_AXI_GP1_ARADDR => net_gnd32,
S_AXI_GP1_AWADDR => net_gnd32,
S_AXI_GP1_WDATA => net_gnd32,
S_AXI_GP1_ARCACHE => net_gnd4,
S_AXI_GP1_ARLEN => net_gnd4,
S_AXI_GP1_ARQOS => net_gnd4,
S_AXI_GP1_AWCACHE => net_gnd4,
S_AXI_GP1_AWLEN => net_gnd4,
S_AXI_GP1_AWQOS => net_gnd4,
S_AXI_GP1_WSTRB => net_gnd4,
S_AXI_GP1_ARID => net_gnd6,
S_AXI_GP1_AWID => net_gnd6,
S_AXI_GP1_WID => net_gnd6,
S_AXI_ACP_ARESETN => open,
S_AXI_ACP_AWREADY => open,
S_AXI_ACP_ARREADY => open,
S_AXI_ACP_BVALID => open,
S_AXI_ACP_RLAST => open,
S_AXI_ACP_RVALID => open,
S_AXI_ACP_WREADY => open,
S_AXI_ACP_BRESP => open,
S_AXI_ACP_RRESP => open,
S_AXI_ACP_BID => open,
S_AXI_ACP_RID => open,
S_AXI_ACP_RDATA => open,
S_AXI_ACP_ACLK => net_gnd0,
S_AXI_ACP_ARVALID => net_gnd0,
S_AXI_ACP_AWVALID => net_gnd0,
S_AXI_ACP_BREADY => net_gnd0,
S_AXI_ACP_RREADY => net_gnd0,
S_AXI_ACP_WLAST => net_gnd0,
S_AXI_ACP_WVALID => net_gnd0,
S_AXI_ACP_ARID => net_gnd3,
S_AXI_ACP_ARPROT => net_gnd3,
S_AXI_ACP_AWID => net_gnd3,
S_AXI_ACP_AWPROT => net_gnd3,
S_AXI_ACP_WID => net_gnd3,
S_AXI_ACP_ARADDR => net_gnd32,
S_AXI_ACP_AWADDR => net_gnd32,
S_AXI_ACP_ARCACHE => net_gnd4,
S_AXI_ACP_ARLEN => net_gnd4,
S_AXI_ACP_ARQOS => net_gnd4,
S_AXI_ACP_AWCACHE => net_gnd4,
S_AXI_ACP_AWLEN => net_gnd4,
S_AXI_ACP_AWQOS => net_gnd4,
S_AXI_ACP_ARBURST => net_gnd2,
S_AXI_ACP_ARLOCK => net_gnd2,
S_AXI_ACP_ARSIZE => net_gnd3,
S_AXI_ACP_AWBURST => net_gnd2,
S_AXI_ACP_AWLOCK => net_gnd2,
S_AXI_ACP_AWSIZE => net_gnd3,
S_AXI_ACP_ARUSER => net_gnd5,
S_AXI_ACP_AWUSER => net_gnd5,
S_AXI_ACP_WDATA => net_gnd64,
S_AXI_ACP_WSTRB => net_gnd8,
S_AXI_HP0_ARESETN => open,
S_AXI_HP0_ARREADY => axi_interconnect_2_M_ARREADY(0),
S_AXI_HP0_AWREADY => axi_interconnect_2_M_AWREADY(0),
S_AXI_HP0_BVALID => axi_interconnect_2_M_BVALID(0),
S_AXI_HP0_RLAST => axi_interconnect_2_M_RLAST(0),
S_AXI_HP0_RVALID => axi_interconnect_2_M_RVALID(0),
S_AXI_HP0_WREADY => axi_interconnect_2_M_WREADY(0),
S_AXI_HP0_BRESP => axi_interconnect_2_M_BRESP,
S_AXI_HP0_RRESP => axi_interconnect_2_M_RRESP,
S_AXI_HP0_BID => axi_interconnect_2_M_BID(0 to 0),
S_AXI_HP0_RID => axi_interconnect_2_M_RID(0 to 0),
S_AXI_HP0_RDATA => axi_interconnect_2_M_RDATA,
S_AXI_HP0_RCOUNT => open,
S_AXI_HP0_WCOUNT => open,
S_AXI_HP0_RACOUNT => open,
S_AXI_HP0_WACOUNT => open,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_HP0_ARVALID => axi_interconnect_2_M_ARVALID(0),
S_AXI_HP0_AWVALID => axi_interconnect_2_M_AWVALID(0),
S_AXI_HP0_BREADY => axi_interconnect_2_M_BREADY(0),
S_AXI_HP0_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP0_RREADY => axi_interconnect_2_M_RREADY(0),
S_AXI_HP0_WLAST => axi_interconnect_2_M_WLAST(0),
S_AXI_HP0_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP0_WVALID => axi_interconnect_2_M_WVALID(0),
S_AXI_HP0_ARBURST => axi_interconnect_2_M_ARBURST,
S_AXI_HP0_ARLOCK => axi_interconnect_2_M_ARLOCK,
S_AXI_HP0_ARSIZE => axi_interconnect_2_M_ARSIZE,
S_AXI_HP0_AWBURST => axi_interconnect_2_M_AWBURST,
S_AXI_HP0_AWLOCK => axi_interconnect_2_M_AWLOCK,
S_AXI_HP0_AWSIZE => axi_interconnect_2_M_AWSIZE,
S_AXI_HP0_ARPROT => axi_interconnect_2_M_ARPROT,
S_AXI_HP0_AWPROT => axi_interconnect_2_M_AWPROT,
S_AXI_HP0_ARADDR => axi_interconnect_2_M_ARADDR,
S_AXI_HP0_AWADDR => axi_interconnect_2_M_AWADDR,
S_AXI_HP0_ARCACHE => axi_interconnect_2_M_ARCACHE,
S_AXI_HP0_ARLEN => axi_interconnect_2_M_ARLEN(3 downto 0),
S_AXI_HP0_ARQOS => axi_interconnect_2_M_ARQOS,
S_AXI_HP0_AWCACHE => axi_interconnect_2_M_AWCACHE,
S_AXI_HP0_AWLEN => axi_interconnect_2_M_AWLEN(3 downto 0),
S_AXI_HP0_AWQOS => axi_interconnect_2_M_AWQOS,
S_AXI_HP0_ARID => axi_interconnect_2_M_ARID(0 to 0),
S_AXI_HP0_AWID => axi_interconnect_2_M_AWID(0 to 0),
S_AXI_HP0_WID => axi_interconnect_2_M_WID(0 to 0),
S_AXI_HP0_WDATA => axi_interconnect_2_M_WDATA,
S_AXI_HP0_WSTRB => axi_interconnect_2_M_WSTRB,
S_AXI_HP1_ARESETN => open,
S_AXI_HP1_ARREADY => open,
S_AXI_HP1_AWREADY => open,
S_AXI_HP1_BVALID => open,
S_AXI_HP1_RLAST => open,
S_AXI_HP1_RVALID => open,
S_AXI_HP1_WREADY => open,
S_AXI_HP1_BRESP => open,
S_AXI_HP1_RRESP => open,
S_AXI_HP1_BID => open,
S_AXI_HP1_RID => open,
S_AXI_HP1_RDATA => open,
S_AXI_HP1_RCOUNT => open,
S_AXI_HP1_WCOUNT => open,
S_AXI_HP1_RACOUNT => open,
S_AXI_HP1_WACOUNT => open,
S_AXI_HP1_ACLK => net_gnd0,
S_AXI_HP1_ARVALID => net_gnd0,
S_AXI_HP1_AWVALID => net_gnd0,
S_AXI_HP1_BREADY => net_gnd0,
S_AXI_HP1_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP1_RREADY => net_gnd0,
S_AXI_HP1_WLAST => net_gnd0,
S_AXI_HP1_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP1_WVALID => net_gnd0,
S_AXI_HP1_ARBURST => net_gnd2,
S_AXI_HP1_ARLOCK => net_gnd2,
S_AXI_HP1_ARSIZE => net_gnd3,
S_AXI_HP1_AWBURST => net_gnd2,
S_AXI_HP1_AWLOCK => net_gnd2,
S_AXI_HP1_AWSIZE => net_gnd3,
S_AXI_HP1_ARPROT => net_gnd3,
S_AXI_HP1_AWPROT => net_gnd3,
S_AXI_HP1_ARADDR => net_gnd32,
S_AXI_HP1_AWADDR => net_gnd32,
S_AXI_HP1_ARCACHE => net_gnd4,
S_AXI_HP1_ARLEN => net_gnd4,
S_AXI_HP1_ARQOS => net_gnd4,
S_AXI_HP1_AWCACHE => net_gnd4,
S_AXI_HP1_AWLEN => net_gnd4,
S_AXI_HP1_AWQOS => net_gnd4,
S_AXI_HP1_ARID => net_gnd6,
S_AXI_HP1_AWID => net_gnd6,
S_AXI_HP1_WID => net_gnd6,
S_AXI_HP1_WDATA => net_gnd64,
S_AXI_HP1_WSTRB => net_gnd8,
S_AXI_HP2_ARESETN => open,
S_AXI_HP2_ARREADY => open,
S_AXI_HP2_AWREADY => open,
S_AXI_HP2_BVALID => open,
S_AXI_HP2_RLAST => open,
S_AXI_HP2_RVALID => open,
S_AXI_HP2_WREADY => open,
S_AXI_HP2_BRESP => open,
S_AXI_HP2_RRESP => open,
S_AXI_HP2_BID => open,
S_AXI_HP2_RID => open,
S_AXI_HP2_RDATA => open,
S_AXI_HP2_RCOUNT => open,
S_AXI_HP2_WCOUNT => open,
S_AXI_HP2_RACOUNT => open,
S_AXI_HP2_WACOUNT => open,
S_AXI_HP2_ACLK => net_gnd0,
S_AXI_HP2_ARVALID => net_gnd0,
S_AXI_HP2_AWVALID => net_gnd0,
S_AXI_HP2_BREADY => net_gnd0,
S_AXI_HP2_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP2_RREADY => net_gnd0,
S_AXI_HP2_WLAST => net_gnd0,
S_AXI_HP2_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP2_WVALID => net_gnd0,
S_AXI_HP2_ARBURST => net_gnd2,
S_AXI_HP2_ARLOCK => net_gnd2,
S_AXI_HP2_ARSIZE => net_gnd3,
S_AXI_HP2_AWBURST => net_gnd2,
S_AXI_HP2_AWLOCK => net_gnd2,
S_AXI_HP2_AWSIZE => net_gnd3,
S_AXI_HP2_ARPROT => net_gnd3,
S_AXI_HP2_AWPROT => net_gnd3,
S_AXI_HP2_ARADDR => net_gnd32,
S_AXI_HP2_AWADDR => net_gnd32,
S_AXI_HP2_ARCACHE => net_gnd4,
S_AXI_HP2_ARLEN => net_gnd4,
S_AXI_HP2_ARQOS => net_gnd4,
S_AXI_HP2_AWCACHE => net_gnd4,
S_AXI_HP2_AWLEN => net_gnd4,
S_AXI_HP2_AWQOS => net_gnd4,
S_AXI_HP2_ARID => net_gnd6,
S_AXI_HP2_AWID => net_gnd6,
S_AXI_HP2_WID => net_gnd6,
S_AXI_HP2_WDATA => net_gnd64,
S_AXI_HP2_WSTRB => net_gnd8,
S_AXI_HP3_ARESETN => open,
S_AXI_HP3_ARREADY => open,
S_AXI_HP3_AWREADY => open,
S_AXI_HP3_BVALID => open,
S_AXI_HP3_RLAST => open,
S_AXI_HP3_RVALID => open,
S_AXI_HP3_WREADY => open,
S_AXI_HP3_BRESP => open,
S_AXI_HP3_RRESP => open,
S_AXI_HP3_BID => open,
S_AXI_HP3_RID => open,
S_AXI_HP3_RDATA => open,
S_AXI_HP3_RCOUNT => open,
S_AXI_HP3_WCOUNT => open,
S_AXI_HP3_RACOUNT => open,
S_AXI_HP3_WACOUNT => open,
S_AXI_HP3_ACLK => net_gnd0,
S_AXI_HP3_ARVALID => net_gnd0,
S_AXI_HP3_AWVALID => net_gnd0,
S_AXI_HP3_BREADY => net_gnd0,
S_AXI_HP3_RDISSUECAP1_EN => net_gnd0,
S_AXI_HP3_RREADY => net_gnd0,
S_AXI_HP3_WLAST => net_gnd0,
S_AXI_HP3_WRISSUECAP1_EN => net_gnd0,
S_AXI_HP3_WVALID => net_gnd0,
S_AXI_HP3_ARBURST => net_gnd2,
S_AXI_HP3_ARLOCK => net_gnd2,
S_AXI_HP3_ARSIZE => net_gnd3,
S_AXI_HP3_AWBURST => net_gnd2,
S_AXI_HP3_AWLOCK => net_gnd2,
S_AXI_HP3_AWSIZE => net_gnd3,
S_AXI_HP3_ARPROT => net_gnd3,
S_AXI_HP3_AWPROT => net_gnd3,
S_AXI_HP3_ARADDR => net_gnd32,
S_AXI_HP3_AWADDR => net_gnd32,
S_AXI_HP3_ARCACHE => net_gnd4,
S_AXI_HP3_ARLEN => net_gnd4,
S_AXI_HP3_ARQOS => net_gnd4,
S_AXI_HP3_AWCACHE => net_gnd4,
S_AXI_HP3_AWLEN => net_gnd4,
S_AXI_HP3_AWQOS => net_gnd4,
S_AXI_HP3_ARID => net_gnd6,
S_AXI_HP3_AWID => net_gnd6,
S_AXI_HP3_WID => net_gnd6,
S_AXI_HP3_WDATA => net_gnd64,
S_AXI_HP3_WSTRB => net_gnd8,
DMA0_DATYPE => open,
DMA0_DAVALID => open,
DMA0_DRREADY => open,
DMA0_RSTN => open,
DMA0_ACLK => net_gnd0,
DMA0_DAREADY => net_gnd0,
DMA0_DRLAST => net_gnd0,
DMA0_DRVALID => net_gnd0,
DMA0_DRTYPE => net_gnd2,
DMA1_DATYPE => open,
DMA1_DAVALID => open,
DMA1_DRREADY => open,
DMA1_RSTN => open,
DMA1_ACLK => net_gnd0,
DMA1_DAREADY => net_gnd0,
DMA1_DRLAST => net_gnd0,
DMA1_DRVALID => net_gnd0,
DMA1_DRTYPE => net_gnd2,
DMA2_DATYPE => open,
DMA2_DAVALID => open,
DMA2_DRREADY => open,
DMA2_RSTN => open,
DMA2_ACLK => net_gnd0,
DMA2_DAREADY => net_gnd0,
DMA2_DRLAST => net_gnd0,
DMA2_DRVALID => net_gnd0,
DMA3_DRVALID => net_gnd0,
DMA3_DATYPE => open,
DMA3_DAVALID => open,
DMA3_DRREADY => open,
DMA3_RSTN => open,
DMA3_ACLK => net_gnd0,
DMA3_DAREADY => net_gnd0,
DMA3_DRLAST => net_gnd0,
DMA2_DRTYPE => net_gnd2,
DMA3_DRTYPE => net_gnd2,
FTMD_TRACEIN_DATA => net_gnd32,
FTMD_TRACEIN_VALID => net_gnd0,
FTMD_TRACEIN_CLK => net_gnd0,
FTMD_TRACEIN_ATID => net_gnd4,
FTMT_F2P_TRIG => net_gnd4,
FTMT_F2P_TRIGACK => open,
FTMT_F2P_DEBUG => net_gnd32,
FTMT_P2F_TRIGACK => net_gnd4,
FTMT_P2F_TRIG => open,
FTMT_P2F_DEBUG => open,
FCLK_CLK3 => open,
FCLK_CLK2 => open,
FCLK_CLK1 => open,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0(0),
FCLK_CLKTRIG3_N => net_gnd0,
FCLK_CLKTRIG2_N => net_gnd0,
FCLK_CLKTRIG1_N => net_gnd0,
FCLK_CLKTRIG0_N => net_gnd0,
FCLK_RESET3_N => open,
FCLK_RESET2_N => open,
FCLK_RESET1_N => open,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
FPGA_IDLE_N => net_gnd0,
DDR_ARB => net_gnd4,
IRQ_F2P => pgassign1,
Core0_nFIQ => net_gnd0,
Core0_nIRQ => net_gnd0,
Core1_nFIQ => net_gnd0,
Core1_nIRQ => net_gnd0,
EVENT_EVENTO => open,
EVENT_STANDBYWFE => open,
EVENT_STANDBYWFI => open,
EVENT_EVENTI => net_gnd0,
MIO => processing_system7_0_MIO,
DDR_Clk => processing_system7_0_DDR_Clk,
DDR_Clk_n => processing_system7_0_DDR_Clk_n,
DDR_CKE => processing_system7_0_DDR_CKE,
DDR_CS_n => processing_system7_0_DDR_CS_n,
DDR_RAS_n => processing_system7_0_DDR_RAS_n,
DDR_CAS_n => processing_system7_0_DDR_CAS_n,
DDR_WEB => processing_system7_0_DDR_WEB,
DDR_BankAddr => processing_system7_0_DDR_BankAddr,
DDR_Addr => processing_system7_0_DDR_Addr,
DDR_ODT => processing_system7_0_DDR_ODT,
DDR_DRSTB => processing_system7_0_DDR_DRSTB,
DDR_DQ => processing_system7_0_DDR_DQ,
DDR_DM => processing_system7_0_DDR_DM,
DDR_DQS => processing_system7_0_DDR_DQS,
DDR_DQS_n => processing_system7_0_DDR_DQS_n,
DDR_VRN => processing_system7_0_DDR_VRN,
DDR_VRP => processing_system7_0_DDR_VRP,
PS_SRSTB => processing_system7_0_PS_SRSTB,
PS_CLK => processing_system7_0_PS_CLK,
PS_PORB => processing_system7_0_PS_PORB,
IRQ_P2F_DMAC_ABORT => open,
IRQ_P2F_DMAC0 => open,
IRQ_P2F_DMAC1 => open,
IRQ_P2F_DMAC2 => open,
IRQ_P2F_DMAC3 => open,
IRQ_P2F_DMAC4 => open,
IRQ_P2F_DMAC5 => open,
IRQ_P2F_DMAC6 => open,
IRQ_P2F_DMAC7 => open,
IRQ_P2F_SMC => open,
IRQ_P2F_QSPI => open,
IRQ_P2F_CTI => open,
IRQ_P2F_GPIO => open,
IRQ_P2F_USB0 => open,
IRQ_P2F_ENET0 => open,
IRQ_P2F_ENET_WAKE0 => open,
IRQ_P2F_SDIO0 => open,
IRQ_P2F_I2C0 => open,
IRQ_P2F_SPI0 => open,
IRQ_P2F_UART0 => open,
IRQ_P2F_CAN0 => open,
IRQ_P2F_USB1 => open,
IRQ_P2F_ENET1 => open,
IRQ_P2F_ENET_WAKE1 => open,
IRQ_P2F_SDIO1 => open,
IRQ_P2F_I2C1 => open,
IRQ_P2F_SPI1 => open,
IRQ_P2F_UART1 => open,
IRQ_P2F_CAN1 => open
);
axi_dispctrl_0 : system_axi_dispctrl_0_wrapper
port map (
REF_CLK_I => processing_system7_0_FCLK_CLK0(0),
PXL_CLK_O => axi_dispctrl_0_PXL_CLK_O,
VDMA_CLK_O => axi_dispctrl_0_VDMA_CLK_O,
PXL_CLK_5X_O => open,
LOCKED_O => open,
FSYNC_O => axi_dispctrl_0_FSYNC_O,
HSYNC_O => axi_dispctrl_0_HSYNC_O,
VSYNC_O => axi_dispctrl_0_VSYNC_O,
DE_O => axi_dispctrl_0_DE_O,
RED_O => axi_dispctrl_0_RED_O,
GREEN_O => axi_dispctrl_0_GREEN_O,
BLUE_O => axi_dispctrl_0_BLUE_O,
ENABLE_O => axi_dispctrl_0_ENABLE_O,
DEBUG_O => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0),
S_AXI_ARESETN => axi_interconnect_1_M_ARESETN(0),
S_AXI_AWADDR => axi_interconnect_1_M_AWADDR(31 downto 0),
S_AXI_AWVALID => axi_interconnect_1_M_AWVALID(0),
S_AXI_WDATA => axi_interconnect_1_M_WDATA(31 downto 0),
S_AXI_WSTRB => axi_interconnect_1_M_WSTRB(3 downto 0),
S_AXI_WVALID => axi_interconnect_1_M_WVALID(0),
S_AXI_BREADY => axi_interconnect_1_M_BREADY(0),
S_AXI_ARADDR => axi_interconnect_1_M_ARADDR(31 downto 0),
S_AXI_ARVALID => axi_interconnect_1_M_ARVALID(0),
S_AXI_RREADY => axi_interconnect_1_M_RREADY(0),
S_AXI_ARREADY => axi_interconnect_1_M_ARREADY(0),
S_AXI_RDATA => axi_interconnect_1_M_RDATA(31 downto 0),
S_AXI_RRESP => axi_interconnect_1_M_RRESP(1 downto 0),
S_AXI_RVALID => axi_interconnect_1_M_RVALID(0),
S_AXI_WREADY => axi_interconnect_1_M_WREADY(0),
S_AXI_BRESP => axi_interconnect_1_M_BRESP(1 downto 0),
S_AXI_BVALID => axi_interconnect_1_M_BVALID(0),
S_AXI_AWREADY => axi_interconnect_1_M_AWREADY(0),
S_AXIS_TREADY => axi_vdma_0_M_AXIS_MM2S_tready,
S_AXIS_ACLK => net_gnd0,
S_AXIS_ARESETN => net_vcc0,
S_AXIS_TDATA => axi_vdma_0_M_AXIS_MM2S_tdata,
S_AXIS_TVALID => axi_vdma_0_M_AXIS_MM2S_tvalid,
S_AXIS_TLAST => axi_vdma_0_M_AXIS_MM2S_tlast,
S_AXIS_TSTRB => axi_vdma_0_M_AXIS_MM2S_TKEEP
);
axi_interconnect_1 : system_axi_interconnect_1_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => axi_interconnect_1_M_ARESETN,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => axi_interconnect_1_S_AWID,
S_AXI_AWADDR => axi_interconnect_1_S_AWADDR,
S_AXI_AWLEN => axi_interconnect_1_S_AWLEN,
S_AXI_AWSIZE => axi_interconnect_1_S_AWSIZE,
S_AXI_AWBURST => axi_interconnect_1_S_AWBURST,
S_AXI_AWLOCK => axi_interconnect_1_S_AWLOCK,
S_AXI_AWCACHE => axi_interconnect_1_S_AWCACHE,
S_AXI_AWPROT => axi_interconnect_1_S_AWPROT,
S_AXI_AWQOS => axi_interconnect_1_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi_interconnect_1_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi_interconnect_1_S_AWREADY(0 to 0),
S_AXI_WID => axi_interconnect_1_S_WID,
S_AXI_WDATA => axi_interconnect_1_S_WDATA,
S_AXI_WSTRB => axi_interconnect_1_S_WSTRB,
S_AXI_WLAST => axi_interconnect_1_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi_interconnect_1_S_WVALID(0 to 0),
S_AXI_WREADY => axi_interconnect_1_S_WREADY(0 to 0),
S_AXI_BID => axi_interconnect_1_S_BID,
S_AXI_BRESP => axi_interconnect_1_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi_interconnect_1_S_BVALID(0 to 0),
S_AXI_BREADY => axi_interconnect_1_S_BREADY(0 to 0),
S_AXI_ARID => axi_interconnect_1_S_ARID,
S_AXI_ARADDR => axi_interconnect_1_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_1_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_1_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_1_S_ARBURST,
S_AXI_ARLOCK => axi_interconnect_1_S_ARLOCK,
S_AXI_ARCACHE => axi_interconnect_1_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_1_S_ARPROT,
S_AXI_ARQOS => axi_interconnect_1_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_1_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_1_S_ARREADY(0 to 0),
S_AXI_RID => axi_interconnect_1_S_RID,
S_AXI_RDATA => axi_interconnect_1_S_RDATA,
S_AXI_RRESP => axi_interconnect_1_S_RRESP,
S_AXI_RLAST => axi_interconnect_1_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_1_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_1_S_RREADY(0 to 0),
M_AXI_ACLK => pgassign2,
M_AXI_AWID => open,
M_AXI_AWADDR => axi_interconnect_1_M_AWADDR,
M_AXI_AWLEN => open,
M_AXI_AWSIZE => open,
M_AXI_AWBURST => open,
M_AXI_AWLOCK => open,
M_AXI_AWCACHE => open,
M_AXI_AWPROT => open,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_1_M_AWVALID,
M_AXI_AWREADY => axi_interconnect_1_M_AWREADY,
M_AXI_WID => open,
M_AXI_WDATA => axi_interconnect_1_M_WDATA,
M_AXI_WSTRB => axi_interconnect_1_M_WSTRB,
M_AXI_WLAST => open,
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_1_M_WVALID,
M_AXI_WREADY => axi_interconnect_1_M_WREADY,
M_AXI_BID => net_gnd24,
M_AXI_BRESP => axi_interconnect_1_M_BRESP,
M_AXI_BUSER => net_gnd2,
M_AXI_BVALID => axi_interconnect_1_M_BVALID,
M_AXI_BREADY => axi_interconnect_1_M_BREADY,
M_AXI_ARID => open,
M_AXI_ARADDR => axi_interconnect_1_M_ARADDR,
M_AXI_ARLEN => open,
M_AXI_ARSIZE => open,
M_AXI_ARBURST => open,
M_AXI_ARLOCK => open,
M_AXI_ARCACHE => open,
M_AXI_ARPROT => open,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_1_M_ARVALID,
M_AXI_ARREADY => axi_interconnect_1_M_ARREADY,
M_AXI_RID => net_gnd24,
M_AXI_RDATA => axi_interconnect_1_M_RDATA,
M_AXI_RRESP => axi_interconnect_1_M_RRESP,
M_AXI_RLAST => net_gnd2,
M_AXI_RUSER => net_gnd2,
M_AXI_RVALID => axi_interconnect_1_M_RVALID,
M_AXI_RREADY => axi_interconnect_1_M_RREADY,
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
axi_vdma_0 : system_axi_vdma_0_wrapper
port map (
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_sg_aclk => net_gnd0,
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0(0),
m_axi_s2mm_aclk => net_gnd0,
m_axis_mm2s_aclk => axi_dispctrl_0_VDMA_CLK_O,
s_axis_s2mm_aclk => net_gnd0,
axi_resetn => axi_interconnect_1_M_ARESETN(1),
s_axi_lite_awvalid => axi_interconnect_1_M_AWVALID(1),
s_axi_lite_awready => axi_interconnect_1_M_AWREADY(1),
s_axi_lite_awaddr => axi_interconnect_1_M_AWADDR(40 downto 32),
s_axi_lite_wvalid => axi_interconnect_1_M_WVALID(1),
s_axi_lite_wready => axi_interconnect_1_M_WREADY(1),
s_axi_lite_wdata => axi_interconnect_1_M_WDATA(63 downto 32),
s_axi_lite_bresp => axi_interconnect_1_M_BRESP(3 downto 2),
s_axi_lite_bvalid => axi_interconnect_1_M_BVALID(1),
s_axi_lite_bready => axi_interconnect_1_M_BREADY(1),
s_axi_lite_arvalid => axi_interconnect_1_M_ARVALID(1),
s_axi_lite_arready => axi_interconnect_1_M_ARREADY(1),
s_axi_lite_araddr => axi_interconnect_1_M_ARADDR(40 downto 32),
s_axi_lite_rvalid => axi_interconnect_1_M_RVALID(1),
s_axi_lite_rready => axi_interconnect_1_M_RREADY(1),
s_axi_lite_rdata => axi_interconnect_1_M_RDATA(63 downto 32),
s_axi_lite_rresp => axi_interconnect_1_M_RRESP(3 downto 2),
m_axi_sg_araddr => open,
m_axi_sg_arlen => open,
m_axi_sg_arsize => open,
m_axi_sg_arburst => open,
m_axi_sg_arprot => open,
m_axi_sg_arcache => open,
m_axi_sg_arvalid => open,
m_axi_sg_arready => net_gnd0,
m_axi_sg_rdata => net_gnd32,
m_axi_sg_rresp => net_gnd2,
m_axi_sg_rlast => net_gnd0,
m_axi_sg_rvalid => net_gnd0,
m_axi_sg_rready => open,
m_axi_mm2s_araddr => axi_interconnect_2_S_ARADDR,
m_axi_mm2s_arlen => axi_interconnect_2_S_ARLEN,
m_axi_mm2s_arsize => axi_interconnect_2_S_ARSIZE,
m_axi_mm2s_arburst => axi_interconnect_2_S_ARBURST,
m_axi_mm2s_arprot => axi_interconnect_2_S_ARPROT,
m_axi_mm2s_arcache => axi_interconnect_2_S_ARCACHE,
m_axi_mm2s_arvalid => axi_interconnect_2_S_ARVALID(0),
m_axi_mm2s_arready => axi_interconnect_2_S_ARREADY(0),
m_axi_mm2s_rdata => axi_interconnect_2_S_RDATA,
m_axi_mm2s_rresp => axi_interconnect_2_S_RRESP,
m_axi_mm2s_rlast => axi_interconnect_2_S_RLAST(0),
m_axi_mm2s_rvalid => axi_interconnect_2_S_RVALID(0),
m_axi_mm2s_rready => axi_interconnect_2_S_RREADY(0),
mm2s_prmry_reset_out_n => open,
m_axis_mm2s_tdata => axi_vdma_0_M_AXIS_MM2S_tdata,
m_axis_mm2s_tkeep => axi_vdma_0_M_AXIS_MM2S_TKEEP,
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_tvalid,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_tready,
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_tlast,
m_axis_mm2s_tuser => open,
m_axi_s2mm_awaddr => open,
m_axi_s2mm_awlen => open,
m_axi_s2mm_awsize => open,
m_axi_s2mm_awburst => open,
m_axi_s2mm_awprot => open,
m_axi_s2mm_awcache => open,
m_axi_s2mm_awvalid => open,
m_axi_s2mm_awready => net_gnd0,
m_axi_s2mm_wdata => open,
m_axi_s2mm_wstrb => open,
m_axi_s2mm_wlast => open,
m_axi_s2mm_wvalid => open,
m_axi_s2mm_wready => net_gnd0,
m_axi_s2mm_bresp => net_gnd2,
m_axi_s2mm_bvalid => net_gnd0,
m_axi_s2mm_bready => open,
s2mm_prmry_reset_out_n => open,
s_axis_s2mm_tdata => net_gnd32,
s_axis_s2mm_tkeep => net_vcc4,
s_axis_s2mm_tvalid => net_gnd0,
s_axis_s2mm_tready => open,
s_axis_s2mm_tlast => net_gnd0,
s_axis_s2mm_tuser => net_gnd1(0 to 0),
mm2s_fsync => axi_dispctrl_0_FSYNC_O,
mm2s_frame_ptr_in => net_gnd6,
mm2s_frame_ptr_out => open,
mm2s_fsync_out => open,
mm2s_prmtr_update => open,
mm2s_buffer_empty => open,
mm2s_buffer_almost_empty => open,
s2mm_fsync => net_gnd0,
s2mm_frame_ptr_in => net_gnd6,
s2mm_frame_ptr_out => open,
s2mm_fsync_out => open,
s2mm_buffer_full => open,
s2mm_buffer_almost_full => open,
s2mm_prmtr_update => open,
mm2s_introut => axi_vdma_0_mm2s_introut,
s2mm_introut => open,
axi_vdma_tstvec => open
);
axi_interconnect_2 : system_axi_interconnect_2_wrapper
port map (
INTERCONNECT_ACLK => processing_system7_0_FCLK_CLK0(0),
INTERCONNECT_ARESETN => processing_system7_0_FCLK_RESET0_N,
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => open,
IRQ => open,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
S_AXI_AWID => net_gnd1(0 to 0),
S_AXI_AWADDR => net_gnd32,
S_AXI_AWLEN => net_gnd8,
S_AXI_AWSIZE => net_gnd3,
S_AXI_AWBURST => net_gnd2,
S_AXI_AWLOCK => net_gnd2,
S_AXI_AWCACHE => net_gnd4,
S_AXI_AWPROT => net_gnd3,
S_AXI_AWQOS => net_gnd4,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => net_gnd1(0 to 0),
S_AXI_AWREADY => open,
S_AXI_WID => net_gnd1(0 to 0),
S_AXI_WDATA => net_gnd64,
S_AXI_WSTRB => net_gnd8,
S_AXI_WLAST => net_gnd1(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => net_gnd1(0 to 0),
S_AXI_WREADY => open,
S_AXI_BID => open,
S_AXI_BRESP => open,
S_AXI_BUSER => open,
S_AXI_BVALID => open,
S_AXI_BREADY => net_gnd1(0 to 0),
S_AXI_ARID => net_gnd1(0 to 0),
S_AXI_ARADDR => axi_interconnect_2_S_ARADDR,
S_AXI_ARLEN => axi_interconnect_2_S_ARLEN,
S_AXI_ARSIZE => axi_interconnect_2_S_ARSIZE,
S_AXI_ARBURST => axi_interconnect_2_S_ARBURST,
S_AXI_ARLOCK => net_gnd2,
S_AXI_ARCACHE => axi_interconnect_2_S_ARCACHE,
S_AXI_ARPROT => axi_interconnect_2_S_ARPROT,
S_AXI_ARQOS => net_gnd4,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi_interconnect_2_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi_interconnect_2_S_ARREADY(0 to 0),
S_AXI_RID => open,
S_AXI_RDATA => axi_interconnect_2_S_RDATA,
S_AXI_RRESP => axi_interconnect_2_S_RRESP,
S_AXI_RLAST => axi_interconnect_2_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi_interconnect_2_S_RVALID(0 to 0),
S_AXI_RREADY => axi_interconnect_2_S_RREADY(0 to 0),
M_AXI_ACLK => processing_system7_0_FCLK_CLK0(0 to 0),
M_AXI_AWID => axi_interconnect_2_M_AWID(0 to 0),
M_AXI_AWADDR => axi_interconnect_2_M_AWADDR,
M_AXI_AWLEN => axi_interconnect_2_M_AWLEN,
M_AXI_AWSIZE => axi_interconnect_2_M_AWSIZE,
M_AXI_AWBURST => axi_interconnect_2_M_AWBURST,
M_AXI_AWLOCK => axi_interconnect_2_M_AWLOCK,
M_AXI_AWCACHE => axi_interconnect_2_M_AWCACHE,
M_AXI_AWPROT => axi_interconnect_2_M_AWPROT,
M_AXI_AWREGION => open,
M_AXI_AWQOS => axi_interconnect_2_M_AWQOS,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi_interconnect_2_M_AWVALID(0 to 0),
M_AXI_AWREADY => axi_interconnect_2_M_AWREADY(0 to 0),
M_AXI_WID => axi_interconnect_2_M_WID(0 to 0),
M_AXI_WDATA => axi_interconnect_2_M_WDATA,
M_AXI_WSTRB => axi_interconnect_2_M_WSTRB,
M_AXI_WLAST => axi_interconnect_2_M_WLAST(0 to 0),
M_AXI_WUSER => open,
M_AXI_WVALID => axi_interconnect_2_M_WVALID(0 to 0),
M_AXI_WREADY => axi_interconnect_2_M_WREADY(0 to 0),
M_AXI_BID => axi_interconnect_2_M_BID(0 to 0),
M_AXI_BRESP => axi_interconnect_2_M_BRESP,
M_AXI_BUSER => net_gnd1(0 to 0),
M_AXI_BVALID => axi_interconnect_2_M_BVALID(0 to 0),
M_AXI_BREADY => axi_interconnect_2_M_BREADY(0 to 0),
M_AXI_ARID => axi_interconnect_2_M_ARID(0 to 0),
M_AXI_ARADDR => axi_interconnect_2_M_ARADDR,
M_AXI_ARLEN => axi_interconnect_2_M_ARLEN,
M_AXI_ARSIZE => axi_interconnect_2_M_ARSIZE,
M_AXI_ARBURST => axi_interconnect_2_M_ARBURST,
M_AXI_ARLOCK => axi_interconnect_2_M_ARLOCK,
M_AXI_ARCACHE => axi_interconnect_2_M_ARCACHE,
M_AXI_ARPROT => axi_interconnect_2_M_ARPROT,
M_AXI_ARREGION => open,
M_AXI_ARQOS => axi_interconnect_2_M_ARQOS,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi_interconnect_2_M_ARVALID(0 to 0),
M_AXI_ARREADY => axi_interconnect_2_M_ARREADY(0 to 0),
M_AXI_RID => axi_interconnect_2_M_RID(0 to 0),
M_AXI_RDATA => axi_interconnect_2_M_RDATA,
M_AXI_RRESP => axi_interconnect_2_M_RRESP,
M_AXI_RLAST => axi_interconnect_2_M_RLAST(0 to 0),
M_AXI_RUSER => net_gnd1(0 to 0),
M_AXI_RVALID => axi_interconnect_2_M_RVALID(0 to 0),
M_AXI_RREADY => axi_interconnect_2_M_RREADY(0 to 0),
S_AXI_CTRL_AWADDR => net_gnd32,
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32,
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32,
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
iobuf_0 : IOBUF
port map (
I => processing_system7_0_I2C0_SDA_O,
IO => processing_system7_0_I2C0_SDA_pin,
O => processing_system7_0_I2C0_SDA_I,
T => processing_system7_0_I2C0_SDA_T
);
iobuf_1 : IOBUF
port map (
I => processing_system7_0_I2C0_SCL_O,
IO => processing_system7_0_I2C0_SCL_pin,
O => processing_system7_0_I2C0_SCL_I,
T => processing_system7_0_I2C0_SCL_T
);
end architecture STRUCTURE;
| bsd-3-clause | 5664548d943d440de2b699f93a55cbec | 0.619186 | 2.83785 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segundoprocesador19oct/PSR.vhd | 1 | 660 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
rest : in STD_LOGIC;
c : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
begin
process(clk,nzvc,ncwp,rest)
begin
if(rest = '1') then
cwp <='0';
c <= '0';
elsif rising_edge(clk) then
c<=nzvc(0);
cwp<=ncwp;
end if;
end process;
end Behavioral;
| gpl-3.0 | e190e1adc230bc9b94a98db6858ce257 | 0.439394 | 3.728814 | false | false | false | false |
makestuff/s3b_sdram | try1/memctrl/memctrl.vhdl | 1 | 6,756 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memctrl_pkg.all;
entity memctrl is
generic (
-- This should be overridden by the inferring hardware or testbench!
INIT_COUNT : unsigned(12 downto 0) := "1" & x"FFF"
);
port(
-- Client interface
mcClk_in : in std_logic;
mcRDV_out : out std_logic; -- Read Data Valid flag
-- SDRAM interface
ramRAS_out : out std_logic;
ramCAS_out : out std_logic;
ramWE_out : out std_logic;
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic
);
end entity;
architecture behavioural of memctrl is
type StateType is (
-- Initialisation states
S_INIT_WAIT,
S_INIT_PRE,
S_INIT_REF1,
S_INIT_REF1_WAIT,
S_INIT_REF2,
S_INIT_REF2_WAIT,
S_INIT_LMR,
S_INIT_LMR_WAIT,
-- Activate a row, do some writes
S_WRITE_ACT,
S_WRITE1,
S_WRITE2,
S_WRITE3,
S_WRITE4,
-- Do a read
S_READ1,
S_READ2,
S_READ3,
-- Loop forever
S_IDLE
);
signal cmd : std_logic_vector(2 downto 0);
constant CMD_NOP : std_logic_vector(2 downto 0) := "111";
constant CMD_ACT : std_logic_vector(2 downto 0) := "011";
constant CMD_READ : std_logic_vector(2 downto 0) := "101";
constant CMD_WRITE : std_logic_vector(2 downto 0) := "100";
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "001";
constant CMD_LMR : std_logic_vector(2 downto 0) := "000";
-- Reserved
-- / Write Burst Mode (0=Burst, 1=Single)
-- / / Reserved
-- / / / Latency Mode (CL=2)
-- / / / / Burst Type (0=Sequential, 1=Interleaved)
-- / / / / / Burst Length (1,2,4,8,X,X,X,Full)
-- / / / / / /
-- / / / / / /
constant LMR_VALUE : std_logic_vector(11 downto 0) := "00" & "1" & "00" & "010" & "0" & "000";
signal state : StateType := S_INIT_WAIT;
signal state_next : StateType;
signal count : unsigned(12 downto 0) := INIT_COUNT;
signal count_next : unsigned(12 downto 0);
begin
-- Infer registers for state & count
process(mcClk_in)
begin
if ( rising_edge(mcClk_in) ) then
state <= state_next;
count <= count_next;
end if;
end process;
-- Next state logic
process(state, count)
begin
state_next <= state;
count_next <= count - 1;
cmd <= CMD_NOP;
ramBank_out <= (others => 'Z');
ramAddr_out <= (others => 'Z');
ramData_io <= (others => 'Z');
mcRDV_out <= '0';
case state is
----------------------------------------------------------------------------------------
-- The init sequence: 4800 NOPs, PRE all, 2xREF, & LMR
----------------------------------------------------------------------------------------
-- Issue NOPs until the count hits the threshold
when S_INIT_WAIT =>
if ( count = 0 ) then
state_next <= S_INIT_PRE;
end if;
-- Issue a PRECHARGE command to all banks
when S_INIT_PRE =>
cmd <= CMD_PRE;
ramAddr_out(10) <= '1'; -- A10=1: Precharge all banks
state_next <= S_INIT_REF1;
-- Issue a refresh command. Must wait 63ns (four clocks, conservatively)
when S_INIT_REF1 =>
cmd <= CMD_REF;
count_next <= "0" & x"002";
state_next <= S_INIT_REF1_WAIT;
when S_INIT_REF1_WAIT => -- Three NOPs
if ( count = 0 ) then
state_next <= S_INIT_REF2;
end if;
-- Issue a refresh command. Must wait 63ns (four clocks, conservatively)
when S_INIT_REF2 =>
cmd <= CMD_REF;
count_next <= "0" & x"002";
state_next <= S_INIT_REF2_WAIT;
when S_INIT_REF2_WAIT => -- Three NOPs
if ( count = 0 ) then
state_next <= S_INIT_LMR;
end if;
-- Issue a Load Mode Register command. Must wait tMRD (two clocks).
when S_INIT_LMR =>
cmd <= CMD_LMR;
ramAddr_out <= LMR_VALUE;
state_next <= S_INIT_LMR_WAIT;
when S_INIT_LMR_WAIT =>
state_next <= S_WRITE_ACT;
----------------------------------------------------------------------------------------
-- Now do some hard-coded writes
----------------------------------------------------------------------------------------
-- Do some writes
when S_WRITE_ACT =>
cmd <= CMD_ACT;
ramBank_out <= "00";
ramAddr_out <= x"000";
state_next <= S_WRITE1;
when S_WRITE1 =>
cmd <= CMD_WRITE;
ramData_io <= x"CAFE";
ramAddr_out <= x"010";
state_next <= S_WRITE2;
when S_WRITE2 =>
cmd <= CMD_WRITE;
ramData_io <= x"BABE";
ramAddr_out <= x"011";
state_next <= S_WRITE3;
when S_WRITE3 =>
cmd <= CMD_WRITE;
ramData_io <= x"DEAD";
ramAddr_out <= x"012";
state_next <= S_WRITE4;
when S_WRITE4 =>
cmd <= CMD_WRITE;
ramData_io <= x"F00D";
ramAddr_out <= x"013";
state_next <= S_READ1;
----------------------------------------------------------------------------------------
-- Now do a hard-coded read
----------------------------------------------------------------------------------------
when S_READ1 =>
cmd <= CMD_READ;
ramAddr_out <= x"010";
state_next <= S_READ2;
when S_READ2 =>
state_next <= S_READ3;
when S_READ3 =>
mcRDV_out <= '1';
state_next <= S_IDLE;
when others =>
end case;
end process;
-- Breakout command signals
ramRAS_out <= cmd(2);
ramCAS_out <= cmd(1);
ramWE_out <= cmd(0);
-- Don't mask anything
ramLDQM_out <= '0';
ramUDQM_out <= '0';
end architecture;
| gpl-3.0 | 17d0f37556d19e5549ebd9684a89ae02 | 0.511101 | 3.337945 | false | false | false | false |
alemedeiros/flappy_vhdl | output/ledcon.vhd | 1 | 1,206 | -- file: output/ledcon.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Leds and 7seg display controller -- converts internal signals to led
-- outputs.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library module ;
use module.output.hex2disp ;
entity ledcon is
port (
obst_count : in integer range -2 to 255 ;
pause : in std_logic ;
game_over : in std_logic ;
hex0 : out std_logic_vector(0 to 6) ;
hex1 : out std_logic_vector(0 to 6) ;
hex2 : out std_logic_vector(0 to 6) ;
hex3 : out std_logic_vector(0 to 6) ;
ledr : out std_logic_vector(0 to 9) ;
ledg : out std_logic_vector(0 to 7)
) ;
end ledcon ;
architecture behavior of ledcon is
signal val : std_logic_vector(15 downto 0) ;
begin
val <= std_logic_vector(to_unsigned(obst_count, 16)) ;
hex0 <= (others => '1') ;
disp0: hex2disp port map (val(3 downto 0), hex1) ;
disp1: hex2disp port map (val(7 downto 4), hex2) ;
hex3 <= (others => '1') ;
--ledr <= (others => game_over) ;
--ledg <= (others => pause) ;
end behavior ;
| bsd-3-clause | 59d1b1d59b6787fa2ef4df12db3fa7f5 | 0.626036 | 3.037783 | false | false | false | false |
alemedeiros/flappy_vhdl | player/calculate_position.vhd | 1 | 1,416 | -- file: player/calculate_position.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Calculate current position based on internal register for position and
-- current speed value.
library ieee ;
use ieee.std_logic_1164.all ;
entity calculate_position is
generic (
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
jump : in std_logic ;
gravity : in integer range 0 to V_RES - 1 ;
position : out integer range 0 to V_RES - 1 ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end calculate_position ;
architecture behavior of calculate_position is
--signal y: integer range 0 to V_RES - 1 := V_RES / 2 ;
signal my_speed : integer range - V_RES to V_RES - 1 ;
begin
process (clock, reset)
variable y: integer range 0 to V_RES - 1 := V_RES / 2 ;
begin
if reset = '1' then
y := V_RES / 2 ;
elsif enable = '1' and rising_edge(clock) then
y := y + my_speed ;
end if;
position <= y ;
end process;
process (clock, reset)
variable sp : integer range - V_RES to V_RES - 1 := -5 ;
begin
if reset = '1' then
sp := -5 ;
elsif enable = '1' and rising_edge(clock) then
if jump = '1' then
sp := -5 ;
else
sp := sp + gravity ;
end if ;
end if ;
my_speed <= sp;
end process ;
end behavior;
| bsd-3-clause | a89161cea36c2c036fd290738c58891a | 0.622175 | 3.125828 | false | false | false | false |
louis-bonicel/VHDL | Porte_AND/addN_testbench.vhd | 2 | 1,515 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:30:03 02/06/2015
-- Design Name:
-- Module Name: addN_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addN_tb is
generic( M: integer:=5);
end addN_tb;
architecture archi of addN_tb is
signal entree1, entree2, sortie: std_logic_vector(M-1 downto 0);
component addN
generic(N: integer := 5);
port (a,b: in std_logic_vector ( N-1 downto 0);
s: out std_logic_vector (N-1 downto 0));
end component;
begin
-- de la même manière que l'on fait un port map, on va faire un generic map pour
-- attribuer une valeur au paramètre N de AddN
uut: addN generic map (N => M) port map (a=> entree1, b => entree2, s => sortie);
stimuli_entree1: process
begin
entree1 <= (others => '0');
wait for 50 ns;
loop
entree1 <= entree1 + 1;
wait for 50 ns;
end loop;
end process;
stimuli_entree2: process
begin
entree2<= (others => '0') ;
loop
if entree1=0 then
entree2 <= entree2 + 1;
end if;
wait for 50 ns ;
end loop ;
end process;
end archi;
| gpl-2.0 | 242d81017249520d2de2da07be366581 | 0.543234 | 3.279221 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/MuxDM.vhd | 2 | 1,427 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:33:41 10/20/2017
-- Design Name:
-- Module Name: MuxDM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxDM is
Port ( DataMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
RFSC : in STD_LOGIC_VECTOR (1 downto 0);
DWR : out STD_LOGIC_VECTOR (31 downto 0));
end MuxDM;
architecture Behavioral of MuxDM is
begin
process (DataMem,AluResult,PC,RFSC) begin
case (RFSC) is
when "00" =>
DWR <= DataMem;
when "01" =>
DWR <= AluResult;
when "10" =>
DWR <= PC;
when others =>
DWR <= AluResult;
end case;
end process;
end Behavioral;
| gpl-3.0 | 2344cf8c69aac9f0f28355c27182f826 | 0.580939 | 3.745407 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fadd_7_full_dsp_32/sim/tri_intersect_ap_fadd_7_full_dsp_32.vhd | 1 | 10,725 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fadd_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fadd_7_full_dsp_32_arch OF tri_intersect_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fadd_7_full_dsp_32_arch;
| mit | db884e94870e2994d1b6453c604e7817 | 0.632727 | 3.216857 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd | 1 | 50,345 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0';
-- KAPIL
signal ch_desc_flush : std_logic := '0';
signal m_axis_ch_ftch_tready : std_logic := '0';
signal ch_ftch_queue_empty : std_logic := '0';
signal ch_ftch_queue_full : std_logic := '0';
signal ch_ftch_pause : std_logic := '0';
signal ch_writing_curdesc : std_logic := '0';
signal ch_ftch_tready : std_logic := '0';
signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch_ftch_tvalid : std_logic := '0';
signal m_axis_ch_ftch_tlast : std_logic := '0';
signal data_concat : std_logic_vector (95 downto 0) := (others => '0');
signal data_concat_64 : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_64_cdma : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0');
signal next_bd : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_valid, tvalid_new : std_logic;
attribute mark_debug of data_concat_valid : signal is "true";
attribute mark_debug of tvalid_new : signal is "true";
signal data_concat_tlast, tlast_new : std_logic;
attribute mark_debug of data_concat_tlast : signal is "true";
attribute mark_debug of tlast_new : signal is "true";
signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0);
attribute mark_debug of counter : signal is "true";
signal sof_ftch_desc : std_logic;
signal nxtdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
attribute mark_debug of nxtdesc_int : signal is "true";
signal cyclic_enable : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else
ch2_cyclic;
nxtdesc <= nxtdesc_int;
TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate
-- TLAST is generated when 8th beat is received
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
SOF_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then
sof_ftch_desc <= '0';
elsif(counter (6) = '1'
and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tvalid = '1'
and m_axis_mm2s_tdata(27) = '1' )then
sof_ftch_desc <= '1';
end if;
end if;
end process SOF_CHECK;
end generate TLAST_GEN;
NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate
sof_ftch_desc <= '0';
CDMA : if C_ENABLE_CDMA = 1 generate
-- For CDMA TLAST is generated when 7th beat is received
-- because last one is not needed
tlast_new <= counter (6) and m_axis_mm2s_tvalid;
tvalid_new <=counter (6) and m_axis_mm2s_tvalid;
end generate CDMA;
NOCDMA : if C_ENABLE_CDMA = 0 generate
-- For DMA tlast is generated with 8th beat
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
end generate NOCDMA;
end generate NOTLAST_GEN;
-- Following shift register keeps track of number of data beats
-- of BD that is being read
DATA_BEAT_REG : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then
counter (0) <= '1';
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0');
Elsif (m_axis_mm2s_tvalid = '1') then
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0);
counter (0) <= '0';
end if;
end if;
end process DATA_BEAT_REG;
-- Registering the Buffer address from BD, 3rd beat
-- Common for DMA, CDMA
DATA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (31 downto 0) <= (others => '0');
Elsif (counter (2) = '1') then
data_concat (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1;
ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (31 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1_64;
end generate ADDR_64BIT;
ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG1_64;
data_concat_64 (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate ADDR_64BIT2;
DMA_REG2 : if C_ENABLE_CDMA = 0 generate
begin
-- For DMA, the 7th beat has the control information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (6) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
end generate DMA_REG2;
CDMA_REG2 : if C_ENABLE_CDMA = 1 generate
begin
-- For CDMA, the 5th beat has the DA information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
CDMA_ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (31 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2_64;
end generate CDMA_ADDR_64BIT;
CDMA_ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG2_64;
data_concat_64_cdma (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate CDMA_ADDR_64BIT2;
end generate CDMA_REG2;
NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate
begin
-- Last beat is directly concatenated and passed to FIFO
-- Masking the CMPLT bit with cyclic_enable
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end generate NOFLOP_FOR_QUEUE;
-- In absence of queuing option the last beat needs to be floped
FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate
begin
NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95 downto 64) <= (others => '0');
Elsif (counter (7) = '1') then
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
end if;
end if;
end process DATA_REG3;
end generate NO_FETCH_Q;
FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95) <= '0';
Elsif (counter (7) = '1') then
data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable);
end if;
end if;
end process DATA_REG3;
data_concat (94 downto 64) <= (others => '0');
end generate FETCH_Q;
DATA_CNTRL : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_valid <= '0';
data_concat_tlast <= '0';
Else
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end if;
end if;
end process DATA_CNTRL;
end generate FLOP_FOR_NOQUEUE;
-- Since the McDMA BD has two more fields to be captured
-- following procedures are needed
NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
data_concat_mcdma <= (others => '0');
end generate NOMCDMA_FTECH;
MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
DATA_MCDMA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (31 downto 0) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG1;
DATA_MCDMA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (63 downto 32) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG2;
end generate MCDMA_BD_FETCH;
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then
nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6);
-- BD addresses are always 16 word 32-bit aligned
nxtdesc_int(5 downto 0) <= (others => '0');
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (0) = '1' --etch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_ACTUAL_ADDR = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
GEN_UPPER_MSB_NXTDESC2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
nxtdesc_int (63 downto C_ACTUAL_ADDR) <= (others => '0');
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC2;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1' and (not cyclic_enable);
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_INCLUDE_MM2S => C_INCLUDE_CH1,
C_INCLUDE_S2MM => C_INCLUDE_CH2,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => '0' ,
-- Channel Control
desc1_flush => ch1_desc_flush ,
desc2_flush => ch2_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch1_active => ch1_ftch_active ,
ftch2_active => ch2_ftch_active ,
ftch1_queue_empty => ch1_ftch_queue_empty ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch1_queue_full => ch1_ftch_queue_full ,
ftch2_queue_full => ch2_ftch_queue_full ,
ftch1_pause => ch1_ftch_pause ,
ftch2_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing1_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat_64_cdma => data_concat_64_cdma,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
m_axis1_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk ,
m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch1_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch2_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0');
end generate GEN_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_sg_v4_1.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_CH1 => C_INCLUDE_CH1
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
desc2_flush => ch2_desc_flush ,
ftch2_active => ch2_ftch_active ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch2_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch_desc_available => m_axis_ftch1_desc_available ,
m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis2_ftch_desc_available => m_axis_ftch2_desc_available ,
m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
ch1_ftch_pause <= '0';
ch2_ftch_pause <= '0';
end generate GEN_NO_QUEUE;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
counter(0),
counter(1),
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(counter(0) = '1' or counter(1)='1')then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
| mit | 50e4dd39a8c7c1b962b53d1d46d65c56 | 0.439269 | 4.163152 | false | false | false | false |
hhuang25/uwaterloo_ece224 | Lab1Good/ece324_latency_tracker.vhd | 2 | 2,467 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ece324_latency_tracker is
port( response : in std_logic;
pulse : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
missed : out std_logic_vector(15 downto 0);
latency : out std_logic_vector (15 downto 0)
);
end ece324_latency_tracker;
architecture Behavioral of ece324_latency_tracker is
signal responded, pulsed, enabled : std_logic;
signal respondedReset, pulsedReset : std_logic;
signal count : std_logic_vector(15 downto 0);
signal misses : std_logic_vector(15 downto 0);
signal currentLatency : std_logic_vector(15 downto 0);
begin
-- sync response to the clock
syncResponse: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(response = '1' and respondedReset = '0') then
responded <= '1';
respondedReset <= '1';
elsif(responded = '1') then
responded <= '0';
elsif(response = '0') then
respondedReset <= '0';
end if;
end if;
end process;
-- sync pulse to the clock
syncPulse: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(pulse = '1' and pulsedReset = '0') then
pulsed <= '1';
pulsedReset <= '1';
elsif(pulsed = '1') then
pulsed <= '0';
elsif(pulse = '0') then
pulsedReset <= '0';
end if;
end if;
end process;
-- enable the counter on a pulse
enabler: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(responded = '1' or reset = '1') then
enabled <= '0';
else
enabled <= pulsed or enabled;
end if;
end if;
end process;
-- latency counter
latcount: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(responded = '1' or reset = '1') then
count <= "0000000000000000";
elsif(enabled = '1' and enable = '1') then
count <= count + 1;
end if;
end if;
end process;
-- missed pulses counter
misscount: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(reset = '1') then
misses <= "0000000000000000";
elsif(enabled = '1' and enable = '1' and pulsed = '1') then
misses <= misses + 1;
end if;
end if;
end process;
-- maximum latency register
latregister: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(reset = '1') then
currentLatency <= "0000000000000000";
elsif(count > currentLatency) then
currentLatency <= count;
end if;
end if;
end process;
-- assign our outputs
missed <= misses;
latency <= currentLatency;
end Behavioral; | mit | c38eba554f60918b37e2b98ca511a44b | 0.64775 | 2.950957 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/vhdl/tri_intersect_fsub_32ns_32ns_32_9_full_dsp.vhd | 4 | 3,390 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity tri_intersect_fsub_32ns_32ns_32_9_full_dsp is
generic (
ID : integer := 0;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of tri_intersect_fsub_32ns_32ns_32_9_full_dsp is
--------------------- Component ---------------------
component tri_intersect_ap_fsub_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
tri_intersect_ap_fsub_7_full_dsp_32_u : component tri_intersect_ap_fsub_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | 7a775fe3cb302fa97e7828ef8ee927ac | 0.49056 | 3.491246 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Execute.vhd | 1 | 3,794 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:00:50 11/11/2017
-- Design Name:
-- Module Name: Execute - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Execute is
Port ( callin : in STD_LOGIC_VECTOR (31 downto 0);
ifin : in STD_LOGIC_VECTOR (31 downto 0);
pcsourcein : in STD_LOGIC_VECTOR (1 downto 0);
aluopin : in STD_LOGIC_VECTOR (5 downto 0);
op1in : in STD_LOGIC_VECTOR (31 downto 0);
op2in : in STD_LOGIC_VECTOR (31 downto 0);
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
nextpc : out STD_LOGIC_VECTOR (31 downto 0);
aluresult : out STD_LOGIC_VECTOR (31 downto 0);
Clkinext : in STD_LOGIC;
Resetext : in STD_LOGIC);
end Execute;
architecture Behavioral of Execute is
COMPONENT ALU
PORT(
OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
c :in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT PSR
PORT(
nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC ;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
rest : in STD_LOGIC;
c : out STD_LOGIC
);
END COMPONENT;
COMPONENT PSR_Modifier
PORT(
oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
COMPONENT MuxPC
PORT(
Disp30 : in STD_LOGIC_VECTOR (31 downto 0);
Disp22 : in STD_LOGIC_VECTOR (31 downto 0);
PC1 : in STD_LOGIC_VECTOR (31 downto 0);
Direccion : in STD_LOGIC_VECTOR (31 downto 0);
Selector : in STD_LOGIC_VECTOR (1 downto 0);
Direccion_Out : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a23: std_logic_vector(31 downto 0);
signal a29: STD_LOGIC;
signal a28: std_logic_vector(3 downto 0);
begin
ints_alu: ALU PORT MAP(
OPER1 => op1in,
OPER2 => op2in,
c =>a29,
ALURESULT => a23,
ALUOP => aluopin
);
aluresult<= a23;
ints_psr: PSR PORT MAP(
nzvc => a28,
clk => Clkinext,
cwp => cwp,
rest => Resetext,
ncwp => ncwp,
icc => icc,
c => a29
);
ints_psrmodifier: PSR_Modifier PORT MAP(
oper1 => op1in,
oper2 => op2in,
aluop => aluopin,
aluResult => a23,
conditionalCodes => a28
);
ints_muxPC: MuxPC PORT MAP(
Disp30 => callin,
Disp22 => ifin,
PC1 => "00000000000000000000000000000000",
Direccion => a23,
Selector => pcsourcein,
Direccion_Out => nextpc
);
end Behavioral;
| gpl-3.0 | 23f610c17a36c70094da474b51f19724 | 0.542435 | 3.775124 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_s2mm_sm.vhd | 1 | 50,944 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sm.vhd
-- Description: This entity contains the S2MM DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sm is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1
-- Depth of DataMover command FIFO
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
-- S2MM Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_desc_flush : in std_logic ; --
s2mm_cmnd_idle : out std_logic ; --
s2mm_sts_idle : out std_logic ; --
s2mm_eof_set : out std_logic ; --
s2mm_eof_micro : in std_logic ; --
s2mm_sof_micro : in std_logic ; --
--
-- S2MM Descriptor Fetch Request --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
desc_available : in std_logic ; --
--
-- S2MM Status Stream RX Length --
s2mm_rxlength_valid : in std_logic ; --
s2mm_rxlength_clr : out std_logic ; --
s2mm_rxlength : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
-- DataMover Command --
s2mm_cmnd_wr : out std_logic ; --
s2mm_cmnd_data : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
s2mm_desc_info : in std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant S2MM_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-- Zero buffer length error - compare value
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal s2mm_rxlength_clr_cmb : std_logic := '0';
signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_rxlength_set : std_logic := '0';
signal blength_grtr_rxlength : std_logic := '0';
signal rxlength_fetched : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal desc_fetch_done_d1 : std_logic := '0';
signal zero_length_error : std_logic := '0';
signal s2mm_eof_set_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
signal eof_micro : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
EN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
eof_micro <= s2mm_eof_micro;
end generate EN_MICRO_DMA;
NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
eof_micro <= '0';
end generate NO_MICRO_DMA;
s2mm_eof_set <= s2mm_eof_set_i;
burst_type <= '1' and (not s2mm_keyhole);
-- A 0 s2mm_keyhole means incremental burst
-- a 1 s2mm_keyhole means fixed burst
-------------------------------------------------------------------------------
-- Not using rx length from status stream - (indeterminate length mode)
-------------------------------------------------------------------------------
GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-- For no status stream or not using length in status app field then eof set is
-- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd)
s2mm_eof_set_i <= '0';
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_fetch_done,
desc_update_done,
s2mm_cmnd_pending,
s2mm_stop,
s2mm_desc_flush,
updt_pending
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
-- fetch descriptor if desc available, not stopped and running
-- if (updt_pending = '1') then
-- s2mm_ns <= WAIT_STATUS;
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 1) then
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
else
s2mm_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- wait until fetch complete then execute
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- s2mm_ns <= EXECUTE_XFER;
elsif (s2mm_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
write_cmnd_cmb <= '1';
else
-- coverage off
s2mm_ns <= WAIT_STATUS;
-- coverage on
end if;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- if error exit
-- if(s2mm_stop = '1')then
-- s2mm_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(s2mm_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- s2mm_ns <= IDLE;
-- else
-- s2mm_ns <= WAIT_STATUS;
-- end if;
-- else
-- s2mm_ns <= EXECUTE_XFER;
-- end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- for no Q wait until desc updated
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register State Machine Statues
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register State Machine Signalse
-------------------------------------------------------------------------------
-- SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1';
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For Indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & PAD_VALUE
-- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro --'0' -- For Indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & s2mm_desc_blength;
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro -- For indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-- Drive unused output to zero
s2mm_rxlength_clr <= '0';
end generate GEN_SM_FOR_NO_LENGTH;
-------------------------------------------------------------------------------
-- Generate state machine and support logic for Using RX Length from Status
-- Stream
-------------------------------------------------------------------------------
-- this would not hold good for MCDMA
GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
GET_RXLENGTH,
CMPR_LENGTH,
EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_update_done,
-- desc_fetch_done,
updt_pending,
s2mm_rxlength_valid,
rxlength_fetched,
s2mm_cmnd_pending,
zero_length_error,
s2mm_stop,
s2mm_desc_flush
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
s2mm_rxlength_clr_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_rxlength_set <= '0';
--rxlength_fetched_clr <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE; --FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
desc_fetch_req_cmb <= '0';
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1')then
s2mm_ns <= IDLE;
-- Descriptor fetch complete
else --if(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
-- else
-- desc_fetch_req_cmb <= '1';
end if;
-------------------------------------------------------------------
WHEN GET_RXLENGTH =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- Buffer length zero, do not compare lengths, execute
-- command to force datamover to issue interror
elsif(zero_length_error = '1')then
s2mm_ns <= EXECUTE_XFER;
elsif(s2mm_rxlength_valid = '1')then
s2mm_rxlength_set <= '1';
s2mm_rxlength_clr_cmb <= '1';
s2mm_ns <= CMPR_LENGTH;
else
s2mm_ns <= GET_RXLENGTH;
end if;
-------------------------------------------------------------------
WHEN CMPR_LENGTH =>
s2mm_ns <= EXECUTE_XFER;
-------------------------------------------------------------------
when EXECUTE_XFER =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- write new command if one is not already pending
elsif(s2mm_cmnd_pending = '0')then
write_cmnd_cmb <= '1';
-- If descriptor queuing enabled then
-- do NOT need to wait for status
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
-- No queuing therefore must wait for
-- status before issuing next command
else
s2mm_ns <= WAIT_STATUS;
end if;
else
s2mm_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register state machine signals
-------------------------------------------------------------------------------
SM_SIG_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_req <= '0' ;
s2mm_rxlength_clr <= '0' ;
else
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
desc_fetch_req <= '1';
else
desc_fetch_req <= desc_fetch_req_cmb ;
end if;
s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb;
end if;
end if;
end process SM_SIG_REGISTER;
-------------------------------------------------------------------------------
-- Check for a ZERO value in descriptor buffer length. If there is
-- then flag an error and skip waiting for valid rxlength. cmnd will
-- get written to datamover with BTT=0 and datamover will flag dmaint error
-- which will be logged in desc, reset required to clear error
-------------------------------------------------------------------------------
REG_ALIGN_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_done_d1 <= '0';
else
desc_fetch_done_d1 <= desc_fetch_done;
end if;
end if;
end process REG_ALIGN_DONE;
-------------------------------------------------------------------------------
-- Zero length error detection - for determinate mode, detect early to prevent
-- rxlength calcuation from first taking place. This will force a 0 BTT
-- command to be issued to the datamover causing an internal error.
-------------------------------------------------------------------------------
REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
zero_length_error <= '0';
elsif(desc_fetch_done_d1 = '1'
and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then
zero_length_error <= '1';
end if;
end if;
end process REG_ZERO_LNGTH_ERR;
-------------------------------------------------------------------------------
-- Capture/Hold receive length from status stream. Also decrement length
-- based on if received length is greater than descriptor buffer size. (i.e. is
-- the case where multiple descriptors/buffers are used to describe one packet)
-------------------------------------------------------------------------------
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
rxlength <= (others => '0');
-- If command register rxlength from status stream fifo
elsif(s2mm_rxlength_set = '1')then
rxlength <= s2mm_rxlength;
-- On command write if current desc buffer size not greater
-- than current rxlength then decrement rxlength in preperations
-- for subsequent commands
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0))
- unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0)));
end if;
end if;
end process REG_RXLENGTH;
-------------------------------------------------------------------------------
-- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To'
-- Received Length value
-------------------------------------------------------------------------------
REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
blength_grtr_rxlength <= '0';
elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then
blength_grtr_rxlength <= '1';
else
blength_grtr_rxlength <= '0';
end if;
end if;
end process REG_BLENGTH_GRTR_RXLNGTH;
-------------------------------------------------------------------------------
-- On command assert rxlength fetched flag indicating length grabbed from
-- status stream fifo
-------------------------------------------------------------------------------
RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then
rxlength_fetched <= '0';
elsif(s2mm_rxlength_set = '1')then
rxlength_fetched <= '1';
end if;
end if;
end process RXLENGTH_FTCHED_PROCESS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF=0 to CMD Tag
& '0' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF=1 to CMD Tag
& '1' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- Set EOF=1
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF='0' to CMD Tag
& '0' -- Cat. IOC='0' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF='1' to CMD Tag
& '1' -- Cat. IOC='1' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
end generate GEN_SM_FOR_LENGTH;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for s2mm is Idle.
-------------------------------------------------------------------------------
-- Increment queue count for each command written if not occuring at
-- same time a status from DM being updated to SG engine
count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0'
else '0';
-- Decrement queue count for each status update to SG engine if not occuring
-- at same time as command being written to DM
count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1'
else '0';
-- keep track of number queue commands
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift (0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- indicate idle when no more queued commands
--s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
s2mm_sts_idle <= not cmnds_queued_shift(0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0';
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
| mit | d213b5883c097fe57d9f0813ce5cc4db | 0.375883 | 4.906954 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_tb.vhd | 3 | 6,128 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth
system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth_inst:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 40
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| bsd-3-clause | 48ab2ee68afbcff37fd778f13505afa5 | 0.63267 | 4.050231 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd | 9 | 10,258 | `protect begin_protected
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| mit | 8b5113ec7c14c1287668c528c026c678 | 0.927374 | 1.931827 | false | false | false | false |
alemedeiros/flappy_vhdl | flappy_vhdl.vhd | 1 | 6,269 | -- file: flappy_vhdl.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Developed for Altera's Cyclone II: EP2C20F484C7.
--
-- Top-Level Entity for the project.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.numeric_std.all;
library modules ;
use modules.colision.all ;
use modules.control.all ;
use modules.input.all ;
use modules.obstacles.all ;
use modules.output.all ;
use modules.player.all ;
entity flappy_vhdl is
generic (
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
-- Input keys
key : in std_logic_vector(3 downto 0) ;
sw : in std_logic_vector(9 downto 0) ;
-- LEDs output
hex0 : out std_logic_vector(0 to 6) ;
hex1 : out std_logic_vector(0 to 6) ;
hex2 : out std_logic_vector(0 to 6) ;
hex3 : out std_logic_vector(0 to 6) ;
ledr : out std_logic_vector(9 downto 0) ;
ledg : out std_logic_vector(7 downto 0) ;
-- VGA output
vga_r : out std_logic_vector(3 downto 0) ;
vga_g : out std_logic_vector(3 downto 0) ;
vga_b : out std_logic_vector(3 downto 0) ;
vga_hs : out std_logic ;
vga_vs : out std_logic ;
-- Clock
clock_27 : in std_logic
) ;
end flappy_vhdl ;
architecture behavior of flappy_vhdl is
signal timer : std_logic ;
signal timer2 : std_logic ;
signal draw_en : std_logic ;
signal pos : integer range 31 downto 0;
signal play : integer range 0 to 95 ;
signal gravity : integer range 0 to 95 ;
signal id : integer range 0 to 3 ;
signal low : integer range 0 to 95 ;
signal high : integer range 0 to 95 ;
signal n_low : integer range 0 to 95 ;
signal n_high : integer range 0 to 95 ;
signal first_low : integer range 0 to 95 ;
signal first_high : integer range 0 to 95 ;
signal game_over : std_logic ;
signal reset : std_logic ;
signal pause : std_logic ;
signal jump : std_logic ;
signal obst_rem : std_logic ;
signal new_obst : std_logic ;
signal int_reset : std_logic ;
-- Enable signals for each module.
signal ctl_calculate_speed : std_logic ;
signal ctl_calculate_position : std_logic ;
signal ctl_obst_regbank : std_logic ;
signal ctl_update_obstacles : std_logic ;
signal ctl_colision_detection : std_logic ;
signal ctl_draw_frame : std_logic ;
signal ctl_ledcon : std_logic ;
signal aux_speed : integer range -V_RES to V_RES - 1 ;
signal aux_position : integer range 0 to V_RES - 1 ;
signal obst_count : integer range 0 to 255 ;
signal count_aux : std_logic_vector(15 downto 0) ;
begin
gc: game_control
port map (
game_over => game_over,
reset => reset,
pause => pause,
jump => jump,
clock => clock_27,
obst_rem => '0',
new_obst => open,
timer => timer,
calculate_speed => ctl_calculate_speed,
calculate_position => ctl_calculate_position,
obst_regbank => ctl_obst_regbank,
update_obstacles => ctl_update_obstacles,
colision_detection => ctl_colision_detection,
draw_frame => ctl_draw_frame,
ledcon => ctl_ledcon,
internal_reset => int_reset
) ;
----input: input_parser
----port map (
---- key => key,
---- sw => sw,
---- jump => jump,
---- reset => reset,
---- pause => pause,
---- gravity => gravity
---- ) ;
-- leds controller
----lcon: ledcon
----port map (
---- obst_count => obst_count,
---- pause => '0',--pause,
---- game_over => '1',--game_over,
---- hex0 => hex0,
---- hex1 => hex1,
---- hex2 => hex2,
---- hex3 => hex3,
---- ledr => open,--ledr,
---- ledg => open --ledg
---- ) ;
colisi: colision_detection
port map (
player => play,
position => pos,
obst_low => first_low,
obst_high => first_high,
game_over => game_over,
clock => clock_27,
enable => ctl_colision_detection,
reset => int_reset
) ;
regbank: obst_regbank
port map (
in_low => n_low,
in_high => n_high,
up_clk => timer,
id => id,
low => low,
high => high,
pos => pos,
f_low => first_low,
f_high => first_high,
clock => clock_27,
enable => ctl_obst_regbank,
reset => int_reset,
obst_rem => draw_en
) ;
output: draw_frame
port map (
player => play,
obst_low => low,
obst_high => high,
obst_pos => pos,
obst_id => id,
red => vga_r,
green => vga_g,
blue => vga_b,
hsync => vga_hs,
vsync => vga_vs,
clock => clock_27,
enable => ctl_draw_frame,
reset => int_reset
) ;
-- Simple timer
div: clock_divider
generic map ( RATE => 2000000 )
port map (
clk_in => clock_27,
clk_out => timer,
enable => '1',
reset => int_reset
) ;
-- DEBUG: Gradually changes size of obstacles
iup_obs: update_obstacles
port map (
new_obst => draw_en ,
obst_count => obst_count ,
low_obst => n_low ,
high_obst => n_high ,
obst_rem => open ,
clock => timer ,
enable => ctl_update_obstacles ,
reset => int_reset
) ;
div2: clock_divider
generic map ( RATE => 9000000 )
port map (
clk_in => clock_27,
clk_out => timer2,
enable => '1',
reset => int_reset
) ;
-- calculate position
cp: calculate_position
generic map ( V_RES => V_RES )
port map (
jump => jump,
gravity => 2,
position => play ,
clock => timer2 ,
enable => ctl_calculate_position ,
reset => int_reset
) ;
-- DEBUG
count_aux <= std_logic_vector(to_unsigned(obst_count, 16)) ;
hex0 <= (others => '1') ;
disp0: hex2disp port map (count_aux(3 downto 0), hex1) ;
disp1: hex2disp port map (count_aux(7 downto 4), hex2) ;
hex3 <= (others => '1') ;
reset <= not key(1) ;
pause <= sw(9) ;
jump <= not key(2) ;
ledr(0) <= game_over ;
ledg(0) <= pause ;
end behavior ;
| bsd-3-clause | 17c549b7f1a5d1c3be26571df4d3dd8f | 0.554155 | 3.167761 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fadd_7_full_dsp_32/synth/tri_intersect_ap_fadd_7_full_dsp_32.vhd | 3 | 12,691 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fadd_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fadd_7_full_dsp_32_arch OF tri_intersect_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fadd_7_full_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fadd_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fadd_7_full_dsp_32_arch;
| mit | 2fea375f30f6d5192fd570843614463b | 0.652194 | 3.023827 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fmul_3_max_dsp_32/sim/tri_intersect_ap_fmul_3_max_dsp_32.vhd | 1 | 10,716 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fmul_3_max_dsp_32;
ARCHITECTURE tri_intersect_ap_fmul_3_max_dsp_32_arch OF tri_intersect_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fmul_3_max_dsp_32_arch;
| mit | 505d08ad9f3a3de53292282dba248d2b | 0.632419 | 3.215122 | false | false | false | false |
makestuff/s3b_sdram | try1/sevenseg.vhdl | 1 | 2,509 | --
-- Copyright (C) 2009-2010 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sevenseg is
port(
clk : in std_logic;
data : in std_logic_vector(15 downto 0);
segs : out std_logic_vector(6 downto 0);
anodes : out std_logic_vector(3 downto 0)
);
end sevenseg;
architecture behavioural of sevenseg is
-- Refresh rate 50M/2^18 ~ 190Hz
-- Refresh rate 8M/2^16 ~ 122Hz
constant COUNTER_WIDTH : natural := 18;
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
signal anode_select : std_logic_vector(1 downto 0);
signal nibble : std_logic_vector(3 downto 0);
begin
count_next <= count + 1;
anode_select <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
-- Update counter, drive anodes and select bits to display for each 7-seg
process(clk)
begin
if ( clk'event and clk = '1' ) then
count <= count_next;
case anode_select is
when "00" =>
anodes <= "0111";
nibble <= data(15 downto 12);
when "01" =>
anodes <= "1011";
nibble <= data(11 downto 8);
when "10" =>
anodes <= "1101";
nibble <= data(7 downto 4);
when others =>
anodes <= "1110";
nibble <= data(3 downto 0);
end case;
end if;
end process;
-- Decode selected nibble
with nibble select
segs <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
end behavioural;
| gpl-3.0 | 11f902621dec6f23aada446eecb08cd4 | 0.654045 | 3.301316 | false | false | false | false |
louis-bonicel/VHDL | Porte_AND/add4.vhd | 2 | 1,360 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:48:12 01/15/2015
-- Design Name:
-- Module Name: add4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity add4 is
Port ( r0 : in STD_LOGIC;
a,b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (4 downto 0));
end add4;
architecture archi of add4 is
signal r: std_logic_vector(4 downto 0);
component componant_2
port(a1,b1,rin: in std_logic; s1, rout: out std_logic);
end component;
begin
r(0)<=r0;
s(4)<=r(4);
boucle:for i in 0 to 3 generate
inst: componant_2 port map (rin =>r(i) , a1=> a(i), b1=> b(i), rout=>r(i+1), s1=>s(i));
end generate;
end archi;
| gpl-2.0 | 8913a732fa52a00e0e8e9988efdd6b5c | 0.554412 | 3.37469 | false | false | false | false |
davewebb8211/ghdl | libraries/synopsys/std_logic_misc.vhdl | 4 | 5,966 | --------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
| gpl-2.0 | 792d288dd26fc6f6f61dd982443de3cf | 0.532182 | 4.083504 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fmul_3_max_dsp_32/synth/tri_intersect_ap_fmul_3_max_dsp_32.vhd | 3 | 12,680 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fmul_3_max_dsp_32;
ARCHITECTURE tri_intersect_ap_fmul_3_max_dsp_32_arch OF tri_intersect_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fmul_3_max_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fmul_3_max_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fmul_3_max_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fmul_3_max_dsp_32_arch;
| mit | 6fa13208ddcd5ee4fbd4b22413c861c5 | 0.651893 | 3.021206 | false | false | false | false |
makestuff/s3b_sdram | try1/toplevel.vhdl | 1 | 2,716 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memctrl_pkg.all;
entity toplevel is
port(
-- Reset & 48MHz clock
ifclk_in : in std_logic;
-- SDRAM interface
ramClk_out : out std_logic;
ramRAS_out : out std_logic;
ramCAS_out : out std_logic;
ramWE_out : out std_logic;
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic;
-- Onboard peripherals
sseg_out : out std_logic_vector(7 downto 0);
anode_out : out std_logic_vector(3 downto 0)
);
end entity;
architecture behavioural of toplevel is
signal ssData : std_logic_vector(15 downto 0);
signal ssData_next : std_logic_vector(15 downto 0);
signal mcRDV : std_logic;
begin
-- Infer a 16-bit register for ssData.
--
process(ifclk_in)
begin
if ( rising_edge(ifclk_in) ) then
ssData <= ssData_next;
end if;
end process;
-- Register the data bus when memctrl asserts RDV.
--
ssData_next <=
ramData_io when mcRDV = '1'
else ssData;
-- Drive the SDRAM clock from the 48MHz IFCLK. This should really be driven by a PLL.
--
ramClk_out <= ifclk_in;
-- Infer the memory controller
--
memctrl: entity work.memctrl
generic map(
INIT_COUNT => "1" & x"2C0" -- 100uS @ 48MHz
)
port map(
mcClk_in => ifclk_in,
mcRDV_out => mcRDV, -- Read Data Valid
ramRAS_out => ramRAS_out,
ramCAS_out => ramCAS_out,
ramWE_out => ramWE_out,
ramAddr_out => ramAddr_out,
ramData_io => ramData_io,
ramBank_out => ramBank_out,
ramLDQM_out => ramLDQM_out,
ramUDQM_out => ramUDQM_out
);
-- Display the current value registered in ssSata.
--
sseg_out(7) <= '1'; -- Decimal point off
sevenseg : entity work.sevenseg
port map(
clk => ifclk_in,
data => ssData,
segs => sseg_out(6 downto 0),
anodes => anode_out
);
end architecture;
| gpl-3.0 | 8490f869da2023081dcd13da544f5cef | 0.667158 | 3.172897 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Barra2.vhd | 1 | 3,322 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:58:35 12/03/2017
-- Design Name:
-- Module Name: Barra2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Barra2 is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
ncwpin : in STD_LOGIC;
callin : in STD_LOGIC_VECTOR (31 downto 0);
ifin : in STD_LOGIC_VECTOR (31 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
wrenmenin : in STD_LOGIC;
pcsourcein : in STD_LOGIC_VECTOR (1 downto 0);
aluopin : in STD_LOGIC_VECTOR (5 downto 0);
a18in : in STD_LOGIC_VECTOR (31 downto 0);
crs1outin : in STD_LOGIC_VECTOR (31 downto 0);
op2outin : in STD_LOGIC_VECTOR (31 downto 0);
PCC : in STD_LOGIC_VECTOR (31 downto 0);
PCCout : out STD_LOGIC_VECTOR (31 downto 0);
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
Cuentradain : in STD_LOGIC_VECTOR (1 downto 0);
Cuentradaout : out STD_LOGIC_VECTOR (1 downto 0);
ncwpout : out STD_LOGIC;
callout : out STD_LOGIC_VECTOR (31 downto 0);
ifout : out STD_LOGIC_VECTOR (31 downto 0);
rfsourceout : out STD_LOGIC_VECTOR (1 downto 0);
wrenmen : out STD_LOGIC;
pcsource : out STD_LOGIC_VECTOR (1 downto 0);
aluop : out STD_LOGIC_VECTOR (5 downto 0);
a18 : out STD_LOGIC_VECTOR (31 downto 0);
crs1out : out STD_LOGIC_VECTOR (31 downto 0);
op2out : out STD_LOGIC_VECTOR (31 downto 0));
end Barra2;
architecture Behavioral of Barra2 is
begin
process(Clk,Reset,ncwpin ,callin ,ifin,rfsourcein ,wrenmenin ,pcsourcein ,
aluopin,a18in ,crs1outin ,op2outin,PCC,RD,Cuentradain )
begin
if reset='1' then
ncwpout <= '0';
callout <= "00000000000000000000000000000000";
ifout<= "00000000000000000000000000000000";
rfsourceout <= "00";
wrenmen <= '0';
pcsource <= "00";
Cuentradaout<= "00";
aluop<= "000000";
a18 <= "00000000000000000000000000000000";
crs1out <= "00000000000000000000000000000000";
op2out<= "00000000000000000000000000000000";
PCCout<= "00000000000000000000000000000000";
RDout <= "000000";
elsif(rising_edge(Clk)) then
ncwpout <= ncwpin;
callout <= callin;
ifout<= ifin;
rfsourceout <= rfsourcein;
wrenmen <= wrenmenin;
pcsource <= pcsourcein;
RDout<= RD;
Cuentradaout<= Cuentradain ;
aluop<=aluopin;
a18 <= a18in;
crs1out <= crs1outin;
op2out<= op2outin;
PCCout<=PCC;
end if;
end process;
end Behavioral;
| gpl-3.0 | cd943419655829ccbaaaa4964c703e5b | 0.590307 | 3.836028 | false | false | false | false |
VisionistInc/advent-of-code-2016 | rawjoe/18/sol.vhdl | 1 | 1,733 | library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
entity sol is
port ( clk : in std_logic;
rst : in std_logic;
rows : out integer;
safe : out integer);
end entity sol;
architecture behavioral of sol is
constant input : std_logic_vector(99 downto 0):= "1011101001000011000011110110100011010110110110010100010100101101001000001110101110011000111000100010";
signal row : std_logic_vector(99 downto 0);
signal rowCnt : integer;
signal numSafe : integer;
begin
process (clk, rst)
variable safeInRow : integer;
begin
-- set ouput
rows <= rowCnt;
safe <= numSafe;
if clk'event and clk = '1' then
-- reset state
if rst = '1' then
row <= input;
rowCnt <= 0;
numSafe <= 0;
else
-- determine what state row will take
-- edge cases
row(0) <= row(1);
row(99) <= row(98);
-- every other middle space
for i in 1 to 98 loop
-- the cases simply reduce to this
row(i) <= row(i-1) xor row(i+1);
end loop;
-- count how many are safe
safeInRow := 0;
for i in 0 to 99 loop
if row(i) = '0' then
safeInRow := safeInRow + 1;
end if;
end loop;
numSafe <= numSafe + safeInRow;
-- increment row count
rowCnt <= rowCnt + 1;
end if;
end if;
end process;
end architecture behavioral;
| mit | bb7ee12aeb213df8db6be2a1fe7c518c | 0.484709 | 4.420918 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/TB4_FileBasedTest.vhd | 1 | 8,403 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.01.2014 14:32:21
-- Design Name:
-- Module Name: TB4_FileBasedTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TB4_FileBasedTest is
end TB4_FileBasedTest;
architecture Behavioral of TB4_FileBasedTest is
signal clk : std_logic;
constant clk_period : time := 10 ns;
signal errorDetected : std_logic := '0';
-- Signals to evaluate
--ENTRADAS
signal actualTestTotalLength : std_logic_vector(31 downto 0);
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
signal resultsBankCounterSignal : integer := 0;
begin
seed <= simulationSeed;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
verification: process (clk, resultReady, result, resultsBankCounterSignal)
begin
if( rising_edge(clk) ) then
if( resultsBankCounterSignal = resultsBank'length ) then
errorDetected <= '0';
else
if (resultReady = '1') then
if( (resultsBank(resultsBankCounterSignal)/=result) ) then
errorDetected <= '1';
else
errorDetected <= '0';
end if;
resultsBankCounterSignal <= resultsBankCounterSignal+1;
else
errorDetected <= '0';
end if;
end if;
end if;
end process verification;
Test: process is
variable byteCounter : integer := 0;--contador de bytes en el bloque de datos actual
variable byteInputCounter : integer := 0;-- contador de bytes totales elidos en el testBench
variable resultsBankCounter : integer := 0;
variable actualByte : std_logic_vector(7 downto 0);-- byet actualmetne leido
variable inputBlockCurrentByte : integer :=0;
variable input : std_logic_vector(31 downto 0) := (others => '0') ;
variable startBlock : boolean := false;
variable endBlock : boolean := false;
begin
start <= '0';--que ya no lea otro dato
readInput <= '0';
operationID <= ( others => '0');
wait for clk_period*10;
while (resultsBankCounter < resultsBank'length) loop
start <= '0';--que ya no lea otro dato
readInput <= '0';
inputBlockCurrentByte := 0;
byteCounter:=0;
inputBlockCurrentByte := 0;
wait for clk_period;
start <= '1';
actualTestTotalLength <= entrysLengths(resultsBankCounter);
while(byteCounter<entrysLengths(resultsBankCounter)) loop
actualByte := dataBank(byteInputCounter);
input((inputBlockCurrentByte*8+7) downto (inputBlockCurrentByte*8)) := actualByte;
--input(7 downto 0) := actualByte;
endBlock := ((byteCounter+1)=entrysLengths(resultsBankCounter));
if ( ( (byteCounter mod 4) = 3 ) or (endBlock) ) then
finalBlock<= mh3_boolean_to_std_logic(endBlock);
inputBlock <= input;
readInput <= '1';
blockLength <= std_logic_vector( to_unsigned(byteCounter, 2) );
wait for clk_period;
start <= '0';
input := (others => '0') ;
end if;
if (endBlock) then
readInput <= '0';
wait for clk_period;
end if;
byteCounter := byteCounter+1;
byteInputCounter := byteInputCounter+1;
inputBlockCurrentByte := ( (inputBlockCurrentByte+1) mod 4);
end loop;
resultsBankCounter := resultsBankCounter+1;
--wait for clk_period;
end loop;
wait;-- Que no se repita de forma indefinida
end process Test;
end Behavioral;
| bsd-3-clause | f619cc3b3bc2aaa17426924b4a057522 | 0.551946 | 4.520172 | false | false | false | false |
davewebb8211/ghdl | libraries/vital2000/prmtvs_b.vhdl | 6 | 235,650 | -------------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : VITAL
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #204 - glitch detection prior to OutputMap
-- ----------------------------------------------------------------------------
-- v95.2 | ddl | 09/14/96 | #223 - single input prmtvs use on-detect
-- | | | instead of glitch-on-event behavior
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL
-- v95.4 | ddl | 01/16/97 | #243 - index constraint error in nbit xor/xnor
-- v99.1 | dbb | 03/31/99 | Updated for VHDL 93
-- ----------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
PACKAGE BODY VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Default values for Primitives
-- ------------------------------------------------------------------------
-- default values for delay parameters
CONSTANT VitalDefDelay01 : VitalDelayType01 := VitalZeroDelay01;
CONSTANT VitalDefDelay01Z : VitalDelayType01Z := VitalZeroDelay01Z;
TYPE VitalTimeArray IS ARRAY (NATURAL RANGE <>) OF TIME;
-- default primitive model operation parameters
-- Glitch detection/reporting
TYPE VitalGlitchModeType IS ( MessagePlusX, MessageOnly, XOnly, NoGlitch);
CONSTANT PrimGlitchMode : VitalGlitchModeType := XOnly;
-- ------------------------------------------------------------------------
-- Local Type and Subtype Declarations
-- ------------------------------------------------------------------------
---------------------------------------------------------------------------
-- enumeration value representing the transition or level of the signal.
-- See function 'GetEdge'
---------------------------------------------------------------------------
TYPE EdgeType IS ( 'U', -- Uninitialized level
'X', -- Unknown level
'0', -- low level
'1', -- high level
'\', -- 1 to 0 falling edge
'/', -- 0 to 1 rising edge
'F', -- * to 0 falling edge
'R', -- * to 1 rising edge
'f', -- rising to X edge
'r', -- falling to X edge
'x', -- Unknown edge (ie U->X)
'V' -- Timing violation edge
);
TYPE EdgeArray IS ARRAY ( NATURAL RANGE <> ) OF EdgeType;
TYPE EdgeX1Table IS ARRAY ( EdgeType ) OF EdgeType;
TYPE EdgeX2Table IS ARRAY ( EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX3Table IS ARRAY ( EdgeType, EdgeType, EdgeType ) OF EdgeType;
TYPE EdgeX4Table IS ARRAY (EdgeType,EdgeType,EdgeType,EdgeType) OF EdgeType;
TYPE LogicToEdgeT IS ARRAY(std_ulogic, std_ulogic) OF EdgeType;
TYPE LogicToLevelT IS ARRAY(std_ulogic ) OF EdgeType;
TYPE GlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
CurrentValue : std_ulogic;
END RECORD;
TYPE GlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF GlitchDataType;
-- Enumerated type used in selection of output path delays
TYPE SchedType IS
RECORD
inp0 : TIME; -- time (abs) of output change due to input change to 0
inp1 : TIME; -- time (abs) of output change due to input change to 1
InpX : TIME; -- time (abs) of output change due to input change to X
Glch0 : TIME; -- time (abs) of output glitch due to input change to 0
Glch1 : TIME; -- time (abs) of output glitch due to input change to 0
END RECORD;
TYPE SchedArray IS ARRAY ( NATURAL RANGE <> ) OF SchedType;
CONSTANT DefSchedType : SchedType := (TIME'HIGH, TIME'HIGH, 0 ns,0 ns,0 ns);
CONSTANT DefSchedAnd : SchedType := (TIME'HIGH, 0 ns,0 ns, TIME'HIGH,0 ns);
-- Constrained array declarations (common sizes used by primitives)
SUBTYPE SchedArray2 IS SchedArray(1 DOWNTO 0);
SUBTYPE SchedArray3 IS SchedArray(2 DOWNTO 0);
SUBTYPE SchedArray4 IS SchedArray(3 DOWNTO 0);
SUBTYPE SchedArray8 IS SchedArray(7 DOWNTO 0);
SUBTYPE TimeArray2 IS VitalTimeArray(1 DOWNTO 0);
SUBTYPE TimeArray3 IS VitalTimeArray(2 DOWNTO 0);
SUBTYPE TimeArray4 IS VitalTimeArray(3 DOWNTO 0);
SUBTYPE TimeArray8 IS VitalTimeArray(7 DOWNTO 0);
SUBTYPE GlitchArray2 IS GlitchDataArrayType(1 DOWNTO 0);
SUBTYPE GlitchArray3 IS GlitchDataArrayType(2 DOWNTO 0);
SUBTYPE GlitchArray4 IS GlitchDataArrayType(3 DOWNTO 0);
SUBTYPE GlitchArray8 IS GlitchDataArrayType(7 DOWNTO 0);
SUBTYPE EdgeArray2 IS EdgeArray(1 DOWNTO 0);
SUBTYPE EdgeArray3 IS EdgeArray(2 DOWNTO 0);
SUBTYPE EdgeArray4 IS EdgeArray(3 DOWNTO 0);
SUBTYPE EdgeArray8 IS EdgeArray(7 DOWNTO 0);
CONSTANT DefSchedArray2 : SchedArray2 :=
(OTHERS=> (0 ns, 0 ns, 0 ns, 0 ns, 0 ns));
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT InitialEdge : LogicToLevelT := (
'1'|'H' => 'R',
'0'|'L' => 'F',
OTHERS => 'x'
);
CONSTANT LogicToEdge : LogicToEdgeT := ( -- previous, current
-- old \ new: U X 0 1 Z W L H -
'U' => ( 'U', 'x', 'F', 'R', 'x', 'x', 'F', 'R', 'x' ),
'X' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'0' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'1' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'Z' => ( 'x', 'X', 'F', 'R', 'X', 'x', 'F', 'R', 'x' ),
'W' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' ),
'L' => ( 'r', 'r', '0', '/', 'r', 'r', '0', '/', 'r' ),
'H' => ( 'f', 'f', '\', '1', 'f', 'f', '\', '1', 'f' ),
'-' => ( 'x', 'X', 'F', 'R', 'x', 'X', 'F', 'R', 'X' )
);
CONSTANT LogicToLevel : LogicToLevelT := (
'1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X'
);
-- -----------------------------------
-- 3-state logic tables
-- -----------------------------------
CONSTANT BufIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT BufIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '1',
'0'|'L' => '0',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf0_Table : stdlogic_table :=
-- enable data value
( '1'|'H' => ( OTHERS => 'Z' ),
'0'|'L' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
CONSTANT InvIf1_Table : stdlogic_table :=
-- enable data value
( '0'|'L' => ( OTHERS => 'Z' ),
'1'|'H' => ( '1'|'H' => '0',
'0'|'L' => '1',
'U' => 'U',
OTHERS => 'X' ),
'U' => ( OTHERS => 'U' ),
OTHERS => ( OTHERS => 'X' ) );
TYPE To_StateCharType IS ARRAY (VitalStateSymbolType) OF CHARACTER;
CONSTANT To_StateChar : To_StateCharType :=
( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v',
'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S' );
TYPE To_TruthCharType IS ARRAY (VitalTruthSymbolType) OF CHARACTER;
CONSTANT To_TruthChar : To_TruthCharType :=
( 'X', '0', '1', '-', 'B', 'Z' );
TYPE TruthTableOutMapType IS ARRAY (VitalTruthSymbolType) OF std_ulogic;
CONSTANT TruthTableOutMap : TruthTableOutMapType :=
-- 'X', '0', '1', '-', 'B', 'Z'
( 'X', '0', '1', 'X', '-', 'Z' );
TYPE StateTableOutMapType IS ARRAY (VitalStateSymbolType) OF std_ulogic;
-- does conversion to X01Z or '-' if invalid
CONSTANT StateTableOutMap : StateTableOutMapType :=
-- '/' '\' 'P' 'N' 'r' 'f' 'p' 'n' 'R' 'F' '^' 'v'
-- 'E' 'A' 'D' '*' 'X' '0' '1' '-' 'B' 'Z' 'S'
( '-','-','-','-','-','-','-','-','-','-','-','-',
'-','-','-','-','X','0','1','X','-','Z','W');
-- ------------------------------------------------------------------------
TYPE ValidTruthTableInputType IS ARRAY (VitalTruthSymbolType) OF BOOLEAN;
-- checks if a symbol IS valid for the stimulus portion of a truth table
CONSTANT ValidTruthTableInput : ValidTruthTableInputType :=
-- 'X' '0' '1' '-' 'B' 'Z'
( TRUE, TRUE, TRUE, TRUE, TRUE, FALSE );
TYPE TruthTableMatchType IS ARRAY (X01, VitalTruthSymbolType) OF BOOLEAN;
-- checks if an input matches th corresponding truth table symbol
-- use: TruthTableMatch(input_converted_to_X01, truth_table_stimulus_symbol)
CONSTANT TruthTableMatch : TruthTableMatchType := (
-- X, 0, 1, - B Z
( TRUE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- X
( FALSE, TRUE, FALSE, TRUE, TRUE, FALSE ), -- 0
( FALSE, FALSE, TRUE, TRUE, TRUE, FALSE ) -- 1
);
-- ------------------------------------------------------------------------
TYPE ValidStateTableInputType IS ARRAY (VitalStateSymbolType) OF BOOLEAN;
CONSTANT ValidStateTableInput : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'p', 'n', 'R', 'F', '^', 'v',
TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'E', 'A', 'D', '*',
TRUE, TRUE, TRUE, TRUE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
TRUE );
CONSTANT ValidStateTableState : ValidStateTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'p', 'n', 'R', 'F', '^', 'v',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'E', 'A', 'D', '*',
FALSE, FALSE, FALSE, FALSE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S'
FALSE );
TYPE StateTableMatchType IS ARRAY (X01,X01,VitalStateSymbolType) OF BOOLEAN;
-- last value, present value, table symbol
CONSTANT StateTableMatch : StateTableMatchType := (
( -- X (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,TRUE, TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, FALSE,TRUE, FALSE,
TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 0 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,TRUE, FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE ),
(TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE)
),
(-- 1 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
(FALSE,FALSE,FALSE,FALSE,FALSE,TRUE ,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE),
(FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE),
(FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE )
)
);
TYPE Logic_UX01Z_Table IS ARRAY (std_ulogic) OF UX01Z;
----------------------------------------------------------
-- table name : cvt_to_x01z
-- parameters : std_ulogic -- some logic value
-- returns : UX01Z -- state value of logic value
-- purpose : to convert state-strength to state only
----------------------------------------------------------
CONSTANT cvt_to_ux01z : Logic_UX01Z_Table :=
('U','X','0','1','Z','X','0','1','X' );
TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER;
CONSTANT LogicCvtTable : LogicCvtTableType
:= ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MINIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return smaller of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 < in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-- ------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 < t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Minimum;
-- ------------------------------------------------------------------------
-- FUNCTION NAME : MAXIMUM
--
-- PARAMETERS : in1, in2 - integer, time
--
-- DESCRIPTION : return larger of in1 and in2
-- ------------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT in1, in2 : INTEGER
) RETURN INTEGER IS
BEGIN
IF (in1 > in2) THEN
RETURN in1;
END IF;
RETURN in2;
END;
-----------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT t1,t2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( t1 > t2 ) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Maximum;
-----------------------------------------------------------------------
FUNCTION GlitchMinTime (
CONSTANT Time1, Time2 : IN TIME
) RETURN TIME IS
BEGIN
IF ( Time1 >= NOW ) THEN
IF ( Time2 >= NOW ) THEN
RETURN Minimum ( Time1, Time2);
ELSE
RETURN Time1;
END IF;
ELSE
IF ( Time2 >= NOW ) THEN
RETURN Time2;
ELSE
RETURN 0 ns;
END IF;
END IF;
END;
--------------------------------------------------------------------
-- Error Message Types and Tables
--------------------------------------------------------------------
TYPE VitalErrorType IS (
ErrNegDel,
ErrInpSym,
ErrOutSym,
ErrStaSym,
ErrVctLng,
ErrTabWidSml,
ErrTabWidLrg,
ErrTabResSml,
ErrTabResLrg
);
TYPE VitalErrorSeverityType IS ARRAY (VitalErrorType) OF SEVERITY_LEVEL;
CONSTANT VitalErrorSeverity : VitalErrorSeverityType := (
ErrNegDel => WARNING,
ErrInpSym => ERROR,
ErrOutSym => ERROR,
ErrStaSym => ERROR,
ErrVctLng => ERROR,
ErrTabWidSml => ERROR,
ErrTabWidLrg => WARNING,
ErrTabResSml => WARNING,
ErrTabResLrg => WARNING
);
CONSTANT MsgNegDel : STRING :=
"Negative delay. New output value not scheduled. Output signal is: ";
CONSTANT MsgInpSym : STRING :=
"Illegal symbol in the input portion of a Truth/State table.";
CONSTANT MsgOutSym : STRING :=
"Illegal symbol in the output portion of a Truth/State table.";
CONSTANT MsgStaSym : STRING :=
"Illegal symbol in the state portion of a State table.";
CONSTANT MsgVctLng : STRING :=
"Vector (array) lengths not equal. ";
CONSTANT MsgTabWidSml : STRING :=
"Width of the Truth/State table is too small.";
CONSTANT MsgTabWidLrg : STRING :=
"Width of Truth/State table is too large. Extra elements are ignored.";
CONSTANT MsgTabResSml : STRING :=
"Result of Truth/State table has too many elements.";
CONSTANT MsgTabResLrg : STRING :=
"Result of Truth/State table has too few elements.";
CONSTANT MsgUnknown : STRING :=
"Unknown error message.";
--------------------------------------------------------------------
-- LOCAL Utilities
--------------------------------------------------------------------
FUNCTION VitalMessage (
CONSTANT ErrorId : IN VitalErrorType
) RETURN STRING IS
BEGIN
CASE ErrorId IS
WHEN ErrNegDel => RETURN MsgNegDel;
WHEN ErrInpSym => RETURN MsgInpSym;
WHEN ErrOutSym => RETURN MsgOutSym;
WHEN ErrStaSym => RETURN MsgStaSym;
WHEN ErrVctLng => RETURN MsgVctLng;
WHEN ErrTabWidSml => RETURN MsgTabWidSml;
WHEN ErrTabWidLrg => RETURN MsgTabWidLrg;
WHEN ErrTabResSml => RETURN MsgTabResSml;
WHEN ErrTabResLrg => RETURN MsgTabResLrg;
WHEN OTHERS => RETURN MsgUnknown;
END CASE;
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId)
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
PROCEDURE VitalError (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalErrorType;
CONSTANT Info : IN CHARACTER
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & VitalMessage(ErrorId) & Info
SEVERITY VitalErrorSeverity(ErrorId);
END;
---------------------------------------------------------------------------
PROCEDURE ReportGlitch (
CONSTANT GlitchRoutine : IN STRING;
CONSTANT OutSignalName : IN STRING;
CONSTANT PreemptedTime : IN TIME;
CONSTANT PreemptedValue : IN std_ulogic;
CONSTANT NewTime : IN TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT Index : IN INTEGER := 0;
CONSTANT IsArraySignal : IN BOOLEAN := FALSE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE StrPtr1, StrPtr2, StrPtr3, StrPtr4, StrPtr5 : LINE;
BEGIN
Write (StrPtr1, PreemptedTime );
Write (StrPtr2, NewTime);
Write (StrPtr3, LogicCvtTable(PreemptedValue));
Write (StrPtr4, LogicCvtTable(NewValue));
IF IsArraySignal THEN
Write (StrPtr5, STRING'( "(" ) );
Write (StrPtr5, Index);
Write (StrPtr5, STRING'( ")" ) );
ELSE
Write (StrPtr5, STRING'( " " ) );
END IF;
-- Issue Report only if Preemted value has not been
-- removed from event queue
ASSERT PreemptedTime > NewTime
REPORT GlitchRoutine & ": GLITCH Detected on port " &
OutSignalName & StrPtr5.ALL &
"; Preempted Future Value := " & StrPtr3.ALL &
" @ " & StrPtr1.ALL &
"; Newly Scheduled Value := " & StrPtr4.ALL &
" @ " & StrPtr2.ALL &
";"
SEVERITY MsgSeverity;
DEALLOCATE(StrPtr1);
DEALLOCATE(StrPtr2);
DEALLOCATE(StrPtr3);
DEALLOCATE(StrPtr4);
DEALLOCATE(StrPtr5);
RETURN;
END ReportGlitch;
---------------------------------------------------------------------------
-- Procedure : VitalGlitchOnEvent
-- :
-- Parameters : OutSignal ........ signal being driven
-- : OutSignalName..... name of the driven signal
-- : GlitchData........ internal data required by the procedure
-- : NewValue.......... new value being assigned
-- : NewDelay.......... Delay accompanying the assignment
-- : (Note: for vectors, this is an array)
-- : GlitchMode........ Glitch generation mode
-- : MessagePlusX, MessageOnly,
-- : XOnly, NoGlitch )
-- : GlitchDelay....... if <= 0 ns , then there will be no Glitch
-- : if > NewDelay, then there is no Glitch,
-- : otherwise, this is the time when a FORCED
-- : generation of a glitch will occur.
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataType;
CONSTANT NewValue : IN std_logic;
CONSTANT NewDelay : IN TIME := 0 ns;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN TIME := -1 ns; -- IR#223
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
-- ------------------------------------------------------------------------
VARIABLE NoGlitchDet : BOOLEAN := FALSE;
VARIABLE OldGlitch : BOOLEAN := FALSE;
VARIABLE Dly : TIME := NewDelay;
BEGIN
-- If nothing to schedule, just return
IF NewDelay < 0 ns THEN
IF (NewValue /= GlitchData.SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled
IF GlitchData.SchedTime <= NOW THEN
GlitchData.CurrentValue := GlitchData.SchedValue;
IF (GlitchDelay <= 0 ns) THEN
IF (NewValue = GlitchData.SchedValue) THEN RETURN; END IF;
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlitchData.GlitchTime <= NOW THEN
GlitchData.CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlitchData.SchedValue = NewValue) THEN
dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
-- Transaction currently scheduled (no glitch if same value)
ELSIF (GlitchData.SchedValue = NewValue) AND
(GlitchData.SchedTime = GlitchData.GlitchTime) AND
(GlitchDelay <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlitchData.SchedTime-NOW, NewDelay );
END IF;
GlitchData.SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal <= NewValue AFTER Dly;
ELSIF NoGlitchDet THEN
GlitchData.GlitchTime := NOW+Dly;
OutSignal <= NewValue AFTER Dly;
ELSE -- new glitch
GlitchData.GlitchTime := GlitchMinTime ( GlitchData.GlitchTime,
NOW+GlitchDelay );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlitchData.GlitchTime, GlitchData.SchedValue,
(Dly + NOW), NewValue,
MsgSeverity=>MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
OutSignal <= 'X' AFTER GlitchData.GlitchTime-NOW;
OutSignal <= TRANSPORT NewValue AFTER Dly;
ELSE
OutSignal <= NewValue AFTER Dly;
END IF;
END IF;
GlitchData.SchedValue := NewValue;
END IF;
RETURN;
END;
----------------------------------------------------------------------------
PROCEDURE VitalGlitchOnEvent (
SIGNAL OutSignal : OUT std_logic_vector;
CONSTANT OutSignalName : IN STRING;
VARIABLE GlitchData : INOUT GlitchDataArrayType;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT NewDelay : IN VitalTimeArray;
CONSTANT GlitchMode : IN VitalGlitchModeType := MessagePlusX;
CONSTANT GlitchDelay : IN VitalTimeArray;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
ALIAS GlDataAlias : GlitchDataArrayType(1 TO GlitchData'LENGTH)
IS GlitchData;
ALIAS NewValAlias : std_logic_vector(1 TO NewValue'LENGTH) IS NewValue;
ALIAS GlDelayAlias : VitalTimeArray(1 TO GlitchDelay'LENGTH)
IS GlitchDelay;
ALIAS NewDelAlias : VitalTimeArray(1 TO NewDelay'LENGTH) IS NewDelay;
VARIABLE Index : INTEGER := OutSignal'LEFT;
VARIABLE Direction : INTEGER;
VARIABLE NoGlitchDet : BOOLEAN;
VARIABLE OldGlitch : BOOLEAN;
VARIABLE Dly, GlDly : TIME;
BEGIN
IF (OutSignal'LEFT > OutSignal'RIGHT) THEN
Direction := -1;
ELSE
Direction := 1;
END IF;
IF ( (OutSignal'LENGTH /= GlitchData'LENGTH) OR
(OutSignal'LENGTH /= NewValue'LENGTH) OR
(OutSignal'LENGTH /= NewDelay'LENGTH) OR
(OutSignal'LENGTH /= GlitchDelay'LENGTH) ) THEN
VitalError ( "VitalGlitchOnEvent", ErrVctLng, OutSignalName );
RETURN;
END IF;
-- a call to the scalar function cannot be made since the actual
-- name associated with a signal parameter must be locally static
FOR n IN 1 TO OutSignal'LENGTH LOOP
NoGlitchDet := FALSE;
OldGlitch := FALSE;
Dly := NewDelAlias(n);
-- If nothing to schedule, just skip to next loop iteration
IF NewDelAlias(n) < 0 ns THEN
IF (NewValAlias(n) /= GlDataAlias(n).SchedValue) THEN
VitalError ( "VitalGlitchOnEvent", ErrNegDel, OutSignalName );
END IF;
ELSE
-- If nothing currently scheduled (i.e. last scheduled
-- transaction already occurred)
IF GlDataAlias(n).SchedTime <= NOW THEN
GlDataAlias(n).CurrentValue := GlDataAlias(n).SchedValue;
IF (GlDelayAlias(n) <= 0 ns) THEN
-- Next iteration if no change in value
IF (NewValAlias(n) = GlDataAlias(n).SchedValue) THEN
Index := Index + Direction;
NEXT;
END IF;
-- since last transaction already occurred there is no glitch
NoGlitchDet := TRUE;
END IF;
-- Transaction currently scheduled - if glitch already happened
ELSIF GlDataAlias(n).GlitchTime <= NOW THEN
GlDataAlias(n).CurrentValue := 'X';
OldGlitch := TRUE;
IF (GlDataAlias(n).SchedValue = NewValAlias(n)) THEN
dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- Transaction currently scheduled
ELSIF (GlDataAlias(n).SchedValue = NewValAlias(n)) AND
(GlDataAlias(n).SchedTime = GlDataAlias(n).GlitchTime) AND
(GlDelayAlias(n) <= 0 ns) THEN
NoGlitchDet := TRUE;
Dly := Minimum( GlDataAlias(n).SchedTime-NOW,
NewDelAlias(n) );
END IF;
-- update last scheduled transaction
GlDataAlias(n).SchedTime := NOW+Dly;
IF OldGlitch THEN
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSIF NoGlitchDet THEN
-- if no glitch then update last glitch time
-- and OutSignal(actual_index)
GlDataAlias(n).GlitchTime := NOW+Dly;
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
ELSE -- new glitch
GlDataAlias(n).GlitchTime := GlitchMinTime (
GlDataAlias(n).GlitchTime,
NOW+GlDelayAlias(n) );
IF (GlitchMode = MessagePlusX) OR
(GlitchMode = MessageOnly) THEN
ReportGlitch ( "VitalGlitchOnEvent", OutSignalName,
GlDataAlias(n).GlitchTime,
GlDataAlias(n).SchedValue,
(Dly + NOW), NewValAlias(n),
Index, TRUE, MsgSeverity );
END IF;
IF (GlitchMode = MessagePlusX) OR (GlitchMode = XOnly) THEN
GlDly := GlDataAlias(n).GlitchTime - NOW;
OutSignal(Index) <= 'X' AFTER GlDly;
OutSignal(Index) <= TRANSPORT NewValAlias(n) AFTER Dly;
ELSE
OutSignal(Index) <= NewValAlias(n) AFTER Dly;
END IF;
END IF; -- glitch / no-glitch
GlDataAlias(n).SchedValue := NewValAlias(n);
END IF; -- NewDelAlias(n) < 0 ns
Index := Index + Direction;
END LOOP;
RETURN;
END;
---------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : TruthOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- X01Zout - output converted to X01Z
-- err - true if illegal character is encountered
--
--
-- DESCRIPTION : converts the output of a truth table to a valid
-- std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE TruthOutputX01Z (
CONSTANT TableOut : IN VitalTruthSymbolType;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := TruthTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalTruthTable", ErrOutSym, To_TruthChar(TableOut));
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME : StateOutputX01Z
--
-- PARAMETERS : table_out - output of table
-- prev_out - previous output value
-- X01Zout - output cojnverted to X01Z
-- err - true if illegal character is encountered
--
-- DESCRIPTION : converts the output of a state table to a
-- valid std_ulogic
-- ------------------------------------------------------------------------
PROCEDURE StateOutputX01Z (
CONSTANT TableOut : IN VitalStateSymbolType;
CONSTANT PrevOut : IN std_ulogic;
VARIABLE X01Zout : OUT std_ulogic;
VARIABLE Err : OUT BOOLEAN
) IS
VARIABLE TempOut : std_ulogic;
BEGIN
Err := FALSE;
TempOut := StateTableOutMap(TableOut);
IF (TempOut = '-') THEN
Err := TRUE;
TempOut := 'X';
VitalError ( "VitalStateTable", ErrOutSym, To_StateChar(TableOut));
ELSIF (TempOut = 'W') THEN
TempOut := To_X01Z(PrevOut);
END IF;
X01Zout := TempOut;
END;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME: StateMatch
--
-- PARAMETERS : symbol - symbol from state table
-- in2 - input from VitalStateTble procedure
-- to state table
-- in2LastValue - previous value of input
-- state - false if the symbol is from the input
-- portion of the table,
-- true if the symbol is from the state
-- portion of the table
-- Err - true if symbol is not a valid input symbol
-- ReturnValue - true if match occurred
--
-- DESCRIPTION : This procedure sets ReturnValue to true if in2 matches
-- symbol (from the state table). If symbol is an edge
-- value edge is set to true and in2 and in2LastValue are
-- checked against symbol. Err is set to true if symbol
-- is an invalid value for the input portion of the state
-- table.
--
-- ------------------------------------------------------------------------
PROCEDURE StateMatch (
CONSTANT Symbol : IN VitalStateSymbolType;
CONSTANT in2 : IN std_ulogic;
CONSTANT in2LastValue : IN std_ulogic;
CONSTANT State : IN BOOLEAN;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
IF (State) THEN
IF (NOT ValidStateTableState(Symbol)) THEN
VitalError ( "VitalStateTable", ErrStaSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
Err := FALSE;
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
END IF;
ELSE
IF (NOT ValidStateTableInput(Symbol) ) THEN
VitalError ( "VitalStateTable", ErrInpSym, To_StateChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
ReturnValue := StateTableMatch(in2LastValue, in2, Symbol);
Err := FALSE;
END IF;
END IF;
END;
-- -----------------------------------------------------------------------
-- FUNCTION NAME: StateTableLookUp
--
-- PARAMETERS : StateTable - state table
-- PresentDataIn - current inputs
-- PreviousDataIn - previous inputs and states
-- NumStates - number of state variables
-- PresentOutputs - current state and current outputs
--
-- DESCRIPTION : This function is used to find the output of the
-- StateTable corresponding to a given set of inputs.
--
-- ------------------------------------------------------------------------
FUNCTION StateTableLookUp (
CONSTANT StateTable : VitalStateTableType;
CONSTANT PresentDataIn : std_logic_vector;
CONSTANT PreviousDataIn : std_logic_vector;
CONSTANT NumStates : NATURAL;
CONSTANT PresentOutputs : std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := PresentDataIn'LENGTH;
CONSTANT NumInputs : INTEGER := InputSize + NumStates - 1;
CONSTANT TableEntries : INTEGER := StateTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := StateTable'LENGTH(2);
CONSTANT OutSize : INTEGER := TableWidth - InputSize - NumStates;
VARIABLE Inputs : std_logic_vector(0 TO NumInputs);
VARIABLE PrevInputs : std_logic_vector(0 TO NumInputs)
:= (OTHERS => 'X');
VARIABLE ReturnValue : std_logic_vector(0 TO (OutSize-1))
:= (OTHERS => 'X');
VARIABLE Temp : std_ulogic;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalStateTableType(0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= StateTable;
BEGIN
Inputs(0 TO InputSize-1) := PresentDataIn;
Inputs(InputSize TO NumInputs) := PresentOutputs(0 TO NumStates - 1);
PrevInputs(0 TO InputSize - 1) := PreviousDataIn(0 TO InputSize - 1);
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the entry
FOR j IN 0 TO InputSize + NumStates LOOP
IF (j = InputSize + NumStates) THEN -- a match occurred
FOR k IN 0 TO Minimum(OutSize, PresentOutputs'LENGTH)-1 LOOP
StateOutputX01Z (
TableAlias(i, TableWidth - k - 1),
PresentOutputs(PresentOutputs'LENGTH - k - 1),
Temp, Err);
ReturnValue(OutSize - k - 1) := Temp;
IF (Err) THEN
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END IF;
END LOOP;
RETURN ReturnValue;
END IF;
StateMatch ( TableAlias(i,j),
Inputs(j), PrevInputs(j),
j >= InputSize, Err, Match);
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
ReturnValue := (OTHERS => 'X');
RETURN ReturnValue;
END;
--------------------------------------------------------------------
-- to_ux01z
-------------------------------------------------------------------
FUNCTION To_UX01Z ( s : std_ulogic
) RETURN UX01Z IS
BEGIN
RETURN cvt_to_ux01z (s);
END;
---------------------------------------------------------------------------
-- Function : GetEdge
-- Purpose : Converts transitions on a given input signal into a
-- enumeration value representing the transition or level
-- of the signal.
--
-- previous "value" current "value" := "edge"
-- ---------------------------------------------------------
-- '1' | 'H' '1' | 'H' '1' level, no edge
-- '0' | 'L' '1' | 'H' '/' rising edge
-- others '1' | 'H' 'R' rising from X
--
-- '1' | 'H' '0' | 'L' '\' falling egde
-- '0' | 'L' '0' | 'L' '0' level, no edge
-- others '0' | 'L' 'F' falling from X
--
-- 'X' | 'W' | '-' 'X' | 'W' | '-' 'X' unknown (X) level
-- 'Z' 'Z' 'X' unknown (X) level
-- 'U' 'U' 'U' 'U' level
--
-- '1' | 'H' others 'f' falling to X
-- '0' | 'L' others 'r' rising to X
-- 'X' | 'W' | '-' 'U' | 'Z' 'x' unknown (X) edge
-- 'Z' 'X' | 'W' | '-' | 'U' 'x' unknown (X) edge
-- 'U' 'X' | 'W' | '-' | 'Z' 'x' unknown (X) edge
--
---------------------------------------------------------------------------
FUNCTION GetEdge (
SIGNAL s : IN std_logic
) RETURN EdgeType IS
BEGIN
IF (s'EVENT)
THEN RETURN LogicToEdge ( s'LAST_VALUE, s );
ELSE RETURN LogicToLevel ( s );
END IF;
END;
---------------------------------------------------------------------------
PROCEDURE GetEdge (
SIGNAL s : IN std_logic_vector;
VARIABLE LastS : INOUT std_logic_vector;
VARIABLE Edge : OUT EdgeArray ) IS
ALIAS sAlias : std_logic_vector ( 1 TO s'LENGTH ) IS s;
ALIAS LastSAlias : std_logic_vector ( 1 TO LastS'LENGTH ) IS LastS;
ALIAS EdgeAlias : EdgeArray ( 1 TO Edge'LENGTH ) IS Edge;
BEGIN
IF s'LENGTH /= LastS'LENGTH OR
s'LENGTH /= Edge'LENGTH THEN
VitalError ( "GetEdge", ErrVctLng, "s, LastS, Edge" );
END IF;
FOR n IN 1 TO s'LENGTH LOOP
EdgeAlias(n) := LogicToEdge( LastSAlias(n), sAlias(n) );
LastSAlias(n) := sAlias(n);
END LOOP;
END;
---------------------------------------------------------------------------
FUNCTION ToEdge ( Value : IN std_logic
) RETURN EdgeType IS
BEGIN
RETURN LogicToLevel( Value );
END;
-- Note: This function will likely be replaced by S'DRIVING_VALUE in VHDL'92
----------------------------------------------------------------------------
IMPURE FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataType
) RETURN std_logic IS
BEGIN
IF NOW >= GlitchData.SchedTime THEN
RETURN GlitchData.SchedValue;
ELSIF NOW >= GlitchData.GlitchTime THEN
RETURN 'X';
ELSE
RETURN GlitchData.CurrentValue;
END IF;
END;
---------------------------------------------------------------------------
IMPURE FUNCTION CurValue (
CONSTANT GlitchData : IN GlitchDataArrayType
) RETURN std_logic_vector IS
VARIABLE Result : std_logic_vector(GlitchData'RANGE);
BEGIN
FOR n IN GlitchData'RANGE LOOP
IF NOW >= GlitchData(n).SchedTime THEN
Result(n) := GlitchData(n).SchedValue;
ELSIF NOW >= GlitchData(n).GlitchTime THEN
Result(n) := 'X';
ELSE
Result(n) := GlitchData(n).CurrentValue;
END IF;
END LOOP;
RETURN Result;
END;
---------------------------------------------------------------------------
-- function calculation utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Function : VitalSame
-- Returns : VitalSame compares the state (UX01) of two logic value. A
-- value of 'X' is returned if the values are different. The
-- common value is returned if the values are equal.
-- Purpose : When the result of a logic model may be either of two
-- separate input values (eg. when the select on a MUX is 'X'),
-- VitalSame may be used to determine if the result needs to
-- be 'X'.
-- Arguments : See the declarations below...
---------------------------------------------------------------------------
FUNCTION VitalSame (
CONSTANT a, b : IN std_ulogic
) RETURN std_ulogic IS
BEGIN
IF To_UX01(a) = To_UX01(b)
THEN RETURN To_UX01(a);
ELSE RETURN 'X';
END IF;
END;
---------------------------------------------------------------------------
-- delay selection utilities
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure : BufPath, InvPath
--
-- Purpose : BufPath and InvPath compute output change times, based on
-- a change on an input port. The computed output change times
-- returned in the composite parameter 'schd'.
--
-- BufPath and InpPath are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the input ports of a model are
-- combined by the delay selection functions (VitalAND,
-- VitalOR, ...). The GetSchedDelay procedure converts the
-- combined output changes times to the single delay (delta
-- time) value for scheduling the output change (passed to
-- VitalGlitchOnEvent).
--
-- The values in 'schd' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- The output times are computed from the model INPUT value
-- and not the final value. For this reason, 'BufPath' should
-- be used to compute the output times for a non-inverting
-- delay paths and 'InvPath' should be used to compute the
-- ouput times for inverting delay paths. Delay paths which
-- include both non-inverting and paths require usage of both
-- 'BufPath' and 'InvPath'. (IE this is needed for the
-- select->output path of a MUX -- See the VitalMUX model).
--
--
-- Parameters : schd....... Computed output result times. (INOUT parameter
-- modified only on input edges)
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays from this input
--
---------------------------------------------------------------------------
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr01); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr10); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE BufPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr01);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr10);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := NOW + tpd(tr10); Schd.Glch1 := Schd.inp1;
Schd.InpX := Schd.inp1;
WHEN '\'|'F' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := NOW + tpd(tr01); Schd.Glch0 := Schd.inp0;
Schd.InpX := Schd.inp0;
WHEN 'r' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr10);
WHEN 'f' => Schd.inp0 := TIME'HIGH;
Schd.inp1 := TIME'HIGH;
Schd.InpX := NOW + tpd(tr01);
WHEN 'x' => Schd.inp1 := TIME'HIGH;
Schd.inp0 := TIME'HIGH;
-- update for X->X change
Schd.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvPath (
VARIABLE Schd : INOUT SchedArray;
CONSTANT Iedg : IN EdgeArray;
CONSTANT tpd : IN VitalDelayArrayType01
) IS
BEGIN
FOR n IN Schd'RANGE LOOP
CASE Iedg(n) IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := NOW + tpd(n)(tr10);
Schd(n).Glch1 := Schd(n).inp1;
Schd(n).InpX := Schd(n).inp1;
WHEN '\'|'F' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := NOW + tpd(n)(tr01);
Schd(n).Glch0 := Schd(n).inp0;
Schd(n).InpX := Schd(n).inp0;
WHEN 'r' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr10);
WHEN 'f' => Schd(n).inp0 := TIME'HIGH;
Schd(n).inp1 := TIME'HIGH;
Schd(n).InpX := NOW + tpd(n)(tr01);
WHEN 'x' => Schd(n).inp1 := TIME'HIGH;
Schd(n).inp0 := TIME'HIGH;
-- update for X->X change
Schd(n).InpX := NOW + Minimum ( tpd(n)(tr10),
tpd(n)(tr01) );
WHEN OTHERS => NULL; -- no timing change
END CASE;
END LOOP;
END;
---------------------------------------------------------------------------
-- Procedure : BufEnab, InvEnab
--
-- Purpose : BufEnab and InvEnab compute output change times, from a
-- change on an input enable port for a 3-state driver. The
-- computed output change times are returned in the composite
-- parameters 'schd1', 'schd0'.
--
-- BufEnab and InpEnab are used together with the delay path
-- selection functions (GetSchedDelay, VitalAND, VitalOR... )
-- The 'schd' value from each of the non-enable input ports of
-- a model (See BufPath, InvPath) are combined using the delay
-- selection functions (VitalAND, VitalOR, ...). The
-- GetSchedDelay procedure combines the output times on the
-- enable path with the output times from the data path(s) and
-- computes the single delay (delta time) value for scheduling
-- the output change (passed to VitalGlitchOnEvent)
--
-- The values in 'schd*' are: (absolute times)
-- inp0 : time of output change due to input change to 0
-- inp1 : time of output change due to input change to 1
-- inpX : time of output change due to input change to X
-- glch0 : time of output glitch due to input change to 0
-- glch1 : time of output glitch due to input change to 1
--
-- 'schd1' contains output times for 1->Z, Z->1 transitions.
-- 'schd0' contains output times for 0->Z, Z->0 transitions.
--
-- 'BufEnab' is used for computing the output times for an
-- high asserted enable (output 'Z' for enable='0').
-- 'InvEnab' is used for computing the output times for an
-- low asserted enable (output 'Z' for enable='1').
--
-- Note: separate 'schd1', 'schd0' parameters are generated
-- so that the combination of the delay paths from
-- multiple enable signals may be combined using the
-- same functions/operators used in combining separate
-- data paths. (See exampe 2 below)
--
--
-- Parameters : schd1...... Computed output result times for 1->Z, Z->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- schd0...... Computed output result times for 0->Z, 0->1
-- transitions. This parameter is modified only on
-- input edge values (events).
-- Iedg....... Input port edge/level value.
-- tpd....... Propagation delays for the enable -> output path.
--
---------------------------------------------------------------------------
PROCEDURE BufEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(trz1);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(trz0);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(tr1z);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(tr0z);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
PROCEDURE InvEnab (
VARIABLE Schd1 : INOUT SchedType;
VARIABLE Schd0 : INOUT SchedType;
CONSTANT Iedg : IN EdgeType;
CONSTANT tpd : IN VitalDelayType01Z
) IS
BEGIN
CASE Iedg IS
WHEN '0'|'1' => NULL; -- no edge: no timing update
WHEN '/'|'R' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := NOW + tpd(tr1z);
Schd1.Glch1 := Schd1.inp1;
Schd1.InpX := Schd1.inp1;
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := NOW + tpd(tr0z);
Schd0.Glch1 := Schd0.inp1;
Schd0.InpX := Schd0.inp1;
WHEN '\'|'F' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := NOW + tpd(trz1);
Schd1.Glch0 := Schd1.inp0;
Schd1.InpX := Schd1.inp0;
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := NOW + tpd(trz0);
Schd0.Glch0 := Schd0.inp0;
Schd0.InpX := Schd0.inp0;
WHEN 'r' => Schd1.inp1 := TIME'HIGH;
Schd1.inp0 := TIME'HIGH;
Schd1.InpX := NOW + tpd(tr1z);
Schd0.inp1 := TIME'HIGH;
Schd0.inp0 := TIME'HIGH;
Schd0.InpX := NOW + tpd(tr0z);
WHEN 'f' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + tpd(trz1);
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + tpd(trz0);
WHEN 'x' => Schd1.inp0 := TIME'HIGH;
Schd1.inp1 := TIME'HIGH;
Schd1.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
Schd0.inp0 := TIME'HIGH;
Schd0.inp1 := TIME'HIGH;
Schd0.InpX := NOW + Minimum(tpd(tr10),tpd(tr01));
WHEN OTHERS => NULL; -- no timing change
END CASE;
END;
---------------------------------------------------------------------------
-- Procedure : GetSchedDelay
--
-- Purpose : GetSchedDelay computes the final delay (incremental) for
-- for scheduling an output signal. The delay is computed
-- from the absolute output times in the 'NewSched' parameter.
-- (See BufPath, InvPath).
--
-- Computation of the output delay for non-3_state outputs
-- consists of selection the appropriate output time based
-- on the new output value 'NewValue' and subtracting 'NOW'
-- to convert to an incremental delay value.
--
-- The Computation of the output delay for 3_state output
-- also includes combination of the enable path delay with
-- the date path delay.
--
-- Parameters : NewDelay... Returned output delay value.
-- GlchDelay.. Returned output delay for the start of a glitch.
-- NewValue... New output value.
-- CurValue... Current value of the output.
-- NewSched... Composite containing the combined absolute
-- output times from the data inputs.
-- EnSched1... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 1->Z, Z->1)
-- EnSched0... Composite containing the combined absolute
-- output times from the enable input(s).
-- (for a 3_state output transitions 0->Z, Z->0)
--
---------------------------------------------------------------------------
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType
) IS
VARIABLE Tim, Glch : TIME;
BEGIN
CASE To_UX01(NewValue) IS
WHEN '0' => Tim := NewSched.inp0;
Glch := NewSched.Glch1;
WHEN '1' => Tim := NewSched.inp1;
Glch := NewSched.Glch0;
WHEN OTHERS => Tim := NewSched.InpX;
Glch := -1 ns;
END CASE;
IF (CurValue /= NewValue)
THEN Glch := -1 ns;
END IF;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT VitalTimeArray;
VARIABLE GlchDelay : OUT VitalTimeArray;
CONSTANT NewValue : IN std_logic_vector;
CONSTANT CurValue : IN std_logic_vector;
CONSTANT NewSched : IN SchedArray
) IS
VARIABLE Tim, Glch : TIME;
ALIAS NewDelayAlias : VitalTimeArray( NewDelay'LENGTH DOWNTO 1)
IS NewDelay;
ALIAS GlchDelayAlias : VitalTimeArray(GlchDelay'LENGTH DOWNTO 1)
IS GlchDelay;
ALIAS NewSchedAlias : SchedArray( NewSched'LENGTH DOWNTO 1)
IS NewSched;
ALIAS NewValueAlias : std_logic_vector ( NewValue'LENGTH DOWNTO 1 )
IS NewValue;
ALIAS CurValueAlias : std_logic_vector ( CurValue'LENGTH DOWNTO 1 )
IS CurValue;
BEGIN
FOR n IN NewDelay'LENGTH DOWNTO 1 LOOP
CASE To_UX01(NewValueAlias(n)) IS
WHEN '0' => Tim := NewSchedAlias(n).inp0;
Glch := NewSchedAlias(n).Glch1;
WHEN '1' => Tim := NewSchedAlias(n).inp1;
Glch := NewSchedAlias(n).Glch0;
WHEN OTHERS => Tim := NewSchedAlias(n).InpX;
Glch := -1 ns;
END CASE;
IF (CurValueAlias(n) /= NewValueAlias(n))
THEN Glch := -1 ns;
END IF;
NewDelayAlias(n) := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelayAlias(n) := Glch;
ELSE GlchDelayAlias(n) := Glch - NOW;
END IF; -- glch < 0 ns
END LOOP;
RETURN;
END;
PROCEDURE GetSchedDelay (
VARIABLE NewDelay : OUT TIME;
VARIABLE GlchDelay : OUT TIME;
CONSTANT NewValue : IN std_ulogic;
CONSTANT CurValue : IN std_ulogic;
CONSTANT NewSched : IN SchedType;
CONSTANT EnSched1 : IN SchedType;
CONSTANT EnSched0 : IN SchedType
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE Tim, Glch : TIME;
BEGIN
CASE v2'(To_X01Z(CurValue) & To_X01Z(NewValue)) IS
WHEN "00" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := GlitchMinTime(NewSched.Glch1,EnSched0.Glch0);
WHEN "01" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := EnSched1.Glch0;
WHEN "0Z" => Tim := EnSched0.inp0;
Glch := NewSched.Glch1;
WHEN "0X" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "10" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := EnSched0.Glch0;
WHEN "11" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := GlitchMinTime(NewSched.Glch0,EnSched1.Glch0);
WHEN "1Z" => Tim := EnSched1.inp0;
Glch := NewSched.Glch0;
WHEN "1X" => Tim := Maximum (NewSched.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "Z0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
IF NewSched.Glch0 > NOW
THEN Glch := Maximum(NewSched.Glch1,EnSched1.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "Z1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
IF NewSched.Glch1 > NOW
THEN Glch := Maximum(NewSched.Glch0,EnSched0.inp1);
ELSE Glch := 0 ns;
END IF;
WHEN "ZX" => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
WHEN "ZZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN "X0" => Tim := Maximum (NewSched.inp0, EnSched0.inp1);
Glch := 0 ns;
WHEN "X1" => Tim := Maximum (NewSched.inp1, EnSched1.inp1);
Glch := 0 ns;
WHEN "XZ" => Tim := Maximum (EnSched1.InpX, EnSched0.InpX);
Glch := 0 ns;
WHEN OTHERS => Tim := Maximum (NewSched.InpX, EnSched1.InpX);
Glch := 0 ns;
END CASE;
NewDelay := Tim - NOW;
IF Glch < 0 ns
THEN GlchDelay := Glch;
ELSE GlchDelay := Glch - NOW;
END IF; -- glch < 0 ns
END;
---------------------------------------------------------------------------
-- Operators and Functions for combination (selection) of path delays
-- > These functions support selection of the "appripriate" path delay
-- dependent on the logic function.
-- > These functions only "select" from the possable output times. No
-- calculation (addition) of delays is performed.
-- > See description of 'BufPath', 'InvPath' and 'GetSchedDelay'
-- > See primitive PROCEDURE models for examples.
---------------------------------------------------------------------------
FUNCTION "not" (
CONSTANT a : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := a.inp0 ;
z.inp0 := a.inp1 ;
z.InpX := a.InpX ;
z.Glch1 := a.Glch0;
z.Glch0 := a.Glch1;
RETURN (z);
END;
FUNCTION "and" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp1 , b.inp1 );
z.inp0 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch1, b.Glch1 );
z.Glch0 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
FUNCTION "or" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp0 , b.inp0 );
z.inp1 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch0, b.Glch0 );
z.Glch1 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
IMPURE FUNCTION "nand" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp0 := Maximum ( a.inp1 , b.inp1 );
z.inp1 := Minimum ( a.inp0 , b.inp0 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch0 := Maximum ( a.Glch1, b.Glch1 );
z.Glch1 := GlitchMinTime ( a.Glch0, b.Glch0 );
RETURN (z);
END;
IMPURE FUNCTION "nor" (
CONSTANT a, b : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
z.inp1 := Maximum ( a.inp0 , b.inp0 );
z.inp0 := Minimum ( a.inp1 , b.inp1 );
z.InpX := GlitchMinTime ( a.InpX , b.InpX );
z.Glch1 := Maximum ( a.Glch0, b.Glch0 );
z.Glch0 := GlitchMinTime ( a.Glch1, b.Glch1 );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 2-bit Logical gates.
-- ------------------------------------------------------------------------
IMPURE FUNCTION VitalXOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) NOR (a NOR b)
z.inp1 := Maximum ( Minimum (ai.inp0 , bi.inp0 ),
Minimum (ab.inp1 , bb.inp1 ) );
z.inp0 := Minimum ( Maximum (ai.inp1 , bi.inp1 ),
Maximum (ab.inp0 , bb.inp0 ) );
z.InpX := Maximum ( Maximum (ai.InpX , bi.InpX ),
Maximum (ab.InpX , bb.InpX ) );
z.Glch1 := Maximum (GlitchMinTime (ai.Glch0, bi.Glch0),
GlitchMinTime (ab.Glch1, bb.Glch1) );
z.Glch0 := GlitchMinTime ( Maximum (ai.Glch1, bi.Glch1),
Maximum (ab.Glch0, bb.Glch0) );
RETURN (z);
END;
IMPURE FUNCTION VitalXNOR2 (
CONSTANT ab,ai, bb,bi : IN SchedType
) RETURN SchedType IS
VARIABLE z : SchedType;
BEGIN
-- z = (a AND b) OR (a NOR b)
z.inp0 := Maximum ( Minimum (ab.inp0 , bb.inp0 ),
Minimum (ai.inp1 , bi.inp1 ) );
z.inp1 := Minimum ( Maximum (ab.inp1 , bb.inp1 ),
Maximum (ai.inp0 , bi.inp0 ) );
z.InpX := Maximum ( Maximum (ab.InpX , bb.InpX ),
Maximum (ai.InpX , bi.InpX ) );
z.Glch0 := Maximum (GlitchMinTime (ab.Glch0, bb.Glch0),
GlitchMinTime (ai.Glch1, bi.Glch1) );
z.Glch1 := GlitchMinTime ( Maximum (ab.Glch1, bb.Glch1),
Maximum (ai.Glch0, bi.Glch0) );
RETURN (z);
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 3-bit Logical gates.
-- ------------------------------------------------------------------------
IMPURE FUNCTION VitalXOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 (ab,ai, bb,bi),
VitalXOR2 (ai,ab, bi,bb),
cb, ci );
END;
IMPURE FUNCTION VitalXNOR3 (
CONSTANT ab,ai, bb,bi, cb,ci : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
cb, ci );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for 4-bit Logical gates.
-- ------------------------------------------------------------------------
IMPURE FUNCTION VitalXOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
IMPURE FUNCTION VitalXNOR4 (
CONSTANT ab,ai, bb,bi, cb,ci, db,di : IN SchedType )
RETURN SchedType IS
BEGIN
RETURN VitalXNOR2 ( VitalXOR2 ( ab,ai, bb,bi ),
VitalXOR2 ( ai,ab, bi,bb ),
VitalXOR2 ( cb,ci, db,di ),
VitalXOR2 ( ci,cb, di,db ) );
END;
-- ------------------------------------------------------------------------
-- Delay Calculation for N-bit Logical gates.
-- ------------------------------------------------------------------------
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
IMPURE FUNCTION VitalXOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- Note: index range on datab,datai assumed to be 1 TO length.
-- This is enforced by internal only usage of this Function
IMPURE FUNCTION VitalXNOR (
CONSTANT DataB, DataI : IN SchedArray
) RETURN SchedType IS
CONSTANT Leng : INTEGER := DataB'LENGTH;
BEGIN
IF Leng = 2 THEN
RETURN VitalXNOR2 ( DataB(1),DataI(1), DataB(2),DataI(2) );
ELSE
RETURN VitalXNOR2 ( VitalXOR ( DataB(1 TO Leng-1),
DataI(1 TO Leng-1) ),
VitalXOR ( DataI(1 TO Leng-1),
DataB(1 TO Leng-1) ),
DataB(Leng),DataI(Leng) );
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT d1, d0 : IN SchedType;
CONSTANT sb, SI : IN SchedType
) RETURN SchedType IS
BEGIN
RETURN (d1 AND sb) OR (d0 AND (NOT SI) );
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN SchedArray4;
CONSTANT sb : IN SchedArray2;
CONSTANT SI : IN SchedArray2
) RETURN SchedType IS
BEGIN
RETURN ( sb(1) AND VitalMUX2(Data(3),Data(2), sb(0), SI(0)) )
OR ( (NOT SI(1)) AND VitalMUX2(Data(1),Data(0), sb(0), SI(0)) );
END;
FUNCTION VitalMUX8 (
CONSTANT Data : IN SchedArray8;
CONSTANT sb : IN SchedArray3;
CONSTANT SI : IN SchedArray3
) RETURN SchedType IS
BEGIN
RETURN ( ( sb(2)) AND VitalMUX4 (Data(7 DOWNTO 4),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) )
OR ( (NOT SI(2)) AND VitalMUX4 (Data(3 DOWNTO 0),
sb(1 DOWNTO 0), SI(1 DOWNTO 0) ) );
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT sMsb : INTEGER := sb'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
BEGIN
IF sb'LENGTH = 1 THEN
RETURN VitalMUX2( Data(2), Data(1), sb(1), SI(1) );
ELSIF sb'LENGTH = 2 THEN
RETURN VitalMUX4( Data, sb, SI );
ELSIF sb'LENGTH = 3 THEN
RETURN VitalMUX8( Data, sb, SI );
ELSIF sb'LENGTH > 3 THEN
RETURN (( sb(sMsb)) AND VInterMux( Data(dMsbLow DOWNTO 1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ))
OR ((NOT SI(sMsb)) AND VInterMux( Data(dMsbHigh DOWNTO dMsbLow+1),
sb(sMsb-1 DOWNTO 1),
SI(sMsb-1 DOWNTO 1) ));
ELSE
RETURN (0 ns, 0 ns, 0 ns, 0 ns, 0 ns); -- dselect'LENGTH < 1
END IF;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN SchedArray;
CONSTANT sb : IN SchedArray;
CONSTANT SI : IN SchedArray
) RETURN SchedType IS
CONSTANT msb : INTEGER := 2**sb'LENGTH;
VARIABLE lDat : SchedArray(msb DOWNTO 1);
ALIAS DataAlias : SchedArray ( Data'LENGTH DOWNTO 1 ) IS Data;
ALIAS sbAlias : SchedArray ( sb'LENGTH DOWNTO 1 ) IS sb;
ALIAS siAlias : SchedArray ( SI'LENGTH DOWNTO 1 ) IS SI;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
FOR i IN msb DOWNTO Data'LENGTH+1 LOOP
lDat(i) := DefSchedAnd;
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
RETURN VInterMux( lDat, sbAlias, siAlias );
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT DataB : IN SchedType;
CONSTANT DataI : IN SchedType;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray2;
BEGIN
Result(1) := Enable AND ( DataB);
Result(0) := Enable AND (NOT DataI);
RETURN Result;
END;
FUNCTION VitalDECODER4 (
CONSTANT DataB : IN SchedArray2;
CONSTANT DataI : IN SchedArray2;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray4;
BEGIN
Result(3) := Enable AND ( DataB(1)) AND ( DataB(0));
Result(2) := Enable AND ( DataB(1)) AND (NOT DataI(0));
Result(1) := Enable AND (NOT DataI(1)) AND ( DataB(0));
Result(0) := Enable AND (NOT DataI(1)) AND (NOT DataI(0));
RETURN Result;
END;
FUNCTION VitalDECODER8 (
CONSTANT DataB : IN SchedArray3;
CONSTANT DataI : IN SchedArray3;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
VARIABLE Result : SchedArray8;
BEGIN
Result(7):= Enable AND ( DataB(2))AND( DataB(1))AND( DataB(0));
Result(6):= Enable AND ( DataB(2))AND( DataB(1))AND(NOT DataI(0));
Result(5):= Enable AND ( DataB(2))AND(NOT DataI(1))AND( DataB(0));
Result(4):= Enable AND ( DataB(2))AND(NOT DataI(1))AND(NOT DataI(0));
Result(3):= Enable AND (NOT DataI(2))AND( DataB(1))AND( DataB(0));
Result(2):= Enable AND (NOT DataI(2))AND( DataB(1))AND(NOT DataI(0));
Result(1):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND( DataB(0));
Result(0):= Enable AND (NOT DataI(2))AND(NOT DataI(1))AND(NOT DataI(0));
RETURN Result;
END;
FUNCTION VitalDECODER (
CONSTANT DataB : IN SchedArray;
CONSTANT DataI : IN SchedArray;
CONSTANT Enable : IN SchedType
) RETURN SchedArray IS
CONSTANT DMsb : INTEGER := DataB'LENGTH - 1;
ALIAS DataBAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataB;
ALIAS DataIAlias : SchedArray ( DMsb DOWNTO 0 ) IS DataI;
BEGIN
IF DataB'LENGTH = 1 THEN
RETURN VitalDECODER2 ( DataBAlias( 0 ),
DataIAlias( 0 ), Enable );
ELSIF DataB'LENGTH = 2 THEN
RETURN VitalDECODER4 ( DataBAlias(1 DOWNTO 0),
DataIAlias(1 DOWNTO 0), Enable );
ELSIF DataB'LENGTH = 3 THEN
RETURN VitalDECODER8 ( DataBAlias(2 DOWNTO 0),
DataIAlias(2 DOWNTO 0), Enable );
ELSIF DataB'LENGTH > 3 THEN
RETURN VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataBAlias(DMsb)) )
& VitalDECODER ( DataBAlias(DMsb-1 DOWNTO 0),
DataIAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataIAlias(DMsb)) );
ELSE
RETURN DefSchedArray2;
END IF;
END;
-------------------------------------------------------------------------------
-- PRIMITIVES
-------------------------------------------------------------------------------
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '1';
FOR i IN Data'RANGE LOOP
Result := Result AND Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result OR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
--
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
Result := '0';
FOR i IN Data'RANGE LOOP
Result := Result XOR Data(i);
END LOOP;
RETURN ResultMap(NOT Result);
END;
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b);
END;
--
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b);
END;
--
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b);
END;
--
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NAND b);
END;
--
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a NOR b);
END;
--
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b));
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c);
END;
--
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c);
END;
--
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c);
END;
--
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c));
END;
--
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c));
END;
--
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c));
END;
-- ---------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ---------------------------------------------------------------------------
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a AND b AND c AND d);
END;
--
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a OR b OR c OR d);
END;
--
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(a XOR b XOR c XOR d);
END;
--
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a AND b AND c AND d));
END;
--
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a OR b OR c OR d));
END;
--
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT (a XOR b XOR c XOR d));
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01(Data));
END;
--
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf0_Table(Enable,Data));
END;
--
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(BufIf1_Table(Enable,Data));
END;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(To_UX01Z(Data));
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(NOT Data);
END;
--
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf0_Table(Enable,Data));
END;
--
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic IS
BEGIN
RETURN ResultMap(InvIf1_Table(Enable,Data));
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect) IS
WHEN '0' => Result := To_UX01(Data0);
WHEN '1' => Result := To_UX01(Data1);
WHEN OTHERS => Result := VitalSame( Data1, Data0 );
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Slct : std_logic_vector2;
VARIABLE Result : UX01;
BEGIN
Slct := To_X01(dSelect);
CASE Slct IS
WHEN "00" => Result := To_UX01(Data(0));
WHEN "01" => Result := To_UX01(Data(1));
WHEN "10" => Result := To_UX01(Data(2));
WHEN "11" => Result := To_UX01(Data(3));
WHEN "0X" => Result := VitalSame( Data(1), Data(0) );
WHEN "1X" => Result := VitalSame( Data(2), Data(3) );
WHEN "X0" => Result := VitalSame( Data(2), Data(0) );
WHEN "X1" => Result := VitalSame( Data(3), Data(1) );
WHEN OTHERS => Result := VitalSame( VitalSame(Data(3),Data(2)),
VitalSame(Data(1),Data(0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
VARIABLE Result : UX01;
BEGIN
CASE To_X01(dSelect(2)) IS
WHEN '0' => Result := VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0));
WHEN '1' => Result := VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0));
WHEN OTHERS => Result := VitalSame( VitalMUX4( Data(3 DOWNTO 0),
dSelect(1 DOWNTO 0)),
VitalMUX4( Data(7 DOWNTO 4),
dSelect(1 DOWNTO 0)));
END CASE;
RETURN ResultMap(Result);
END;
--
FUNCTION VInterMux (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector
) RETURN std_ulogic IS
CONSTANT sMsb : INTEGER := dSelect'LENGTH;
CONSTANT dMsbHigh : INTEGER := Data'LENGTH;
CONSTANT dMsbLow : INTEGER := Data'LENGTH/2;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE Result : UX01;
BEGIN
IF dSelect'LENGTH = 1 THEN
Result := VitalMUX2( DataAlias(2), DataAlias(1), dSelAlias(1) );
ELSIF dSelect'LENGTH = 2 THEN
Result := VitalMUX4( DataAlias, dSelAlias );
ELSIF dSelect'LENGTH > 2 THEN
CASE To_X01(dSelect(sMsb)) IS
WHEN '0' =>
Result := VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN '1' =>
Result := VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) );
WHEN OTHERS =>
Result := VitalSame(
VInterMux( DataAlias(dMsbLow DOWNTO 1),
dSelAlias(sMsb-1 DOWNTO 1) ),
VInterMux( DataAlias(dMsbHigh DOWNTO dMsbLow+1),
dSelAlias(sMsb-1 DOWNTO 1) )
);
END CASE;
ELSE
Result := 'X'; -- dselect'LENGTH < 1
END IF;
RETURN Result;
END;
--
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic IS
CONSTANT msb : INTEGER := 2**dSelect'LENGTH;
ALIAS DataAlias : std_logic_vector ( Data'LENGTH DOWNTO 1) IS Data;
ALIAS dSelAlias : std_logic_vector (dSelect'LENGTH DOWNTO 1) IS dSelect;
VARIABLE lDat : std_logic_vector(msb DOWNTO 1) := (OTHERS=>'X');
VARIABLE Result : UX01;
BEGIN
IF Data'LENGTH <= msb THEN
FOR i IN Data'LENGTH DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
ELSE
FOR i IN msb DOWNTO 1 LOOP
lDat(i) := DataAlias(i);
END LOOP;
END IF;
Result := VInterMux( lDat, dSelAlias );
RETURN ResultMap(Result);
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- ------------------------------------------------------------------------
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2 IS
VARIABLE Result : std_logic_vector2;
BEGIN
Result(1) := ResultMap(Enable AND ( Data));
Result(0) := ResultMap(Enable AND (NOT Data));
RETURN Result;
END;
--
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4 IS
VARIABLE Result : std_logic_vector4;
BEGIN
Result(3) := ResultMap(Enable AND ( Data(1)) AND ( Data(0)));
Result(2) := ResultMap(Enable AND ( Data(1)) AND (NOT Data(0)));
Result(1) := ResultMap(Enable AND (NOT Data(1)) AND ( Data(0)));
Result(0) := ResultMap(Enable AND (NOT Data(1)) AND (NOT Data(0)));
RETURN Result;
END;
--
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8 IS
VARIABLE Result : std_logic_vector8;
BEGIN
Result(7) := ( Data(2)) AND ( Data(1)) AND ( Data(0));
Result(6) := ( Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(5) := ( Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(4) := ( Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(3) := (NOT Data(2)) AND ( Data(1)) AND ( Data(0));
Result(2) := (NOT Data(2)) AND ( Data(1)) AND (NOT Data(0));
Result(1) := (NOT Data(2)) AND (NOT Data(1)) AND ( Data(0));
Result(0) := (NOT Data(2)) AND (NOT Data(1)) AND (NOT Data(0));
Result(0) := ResultMap ( Enable AND Result(0) );
Result(1) := ResultMap ( Enable AND Result(1) );
Result(2) := ResultMap ( Enable AND Result(2) );
Result(3) := ResultMap ( Enable AND Result(3) );
Result(4) := ResultMap ( Enable AND Result(4) );
Result(5) := ResultMap ( Enable AND Result(5) );
Result(6) := ResultMap ( Enable AND Result(6) );
Result(7) := ResultMap ( Enable AND Result(7) );
RETURN Result;
END;
--
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector IS
CONSTANT DMsb : INTEGER := Data'LENGTH - 1;
ALIAS DataAlias : std_logic_vector ( DMsb DOWNTO 0 ) IS Data;
BEGIN
IF Data'LENGTH = 1 THEN
RETURN VitalDECODER2 (DataAlias( 0 ), Enable, ResultMap );
ELSIF Data'LENGTH = 2 THEN
RETURN VitalDECODER4 (DataAlias(1 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH = 3 THEN
RETURN VitalDECODER8 (DataAlias(2 DOWNTO 0), Enable, ResultMap );
ELSIF Data'LENGTH > 3 THEN
RETURN VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND ( DataAlias(DMsb)), ResultMap )
& VitalDECODER (DataAlias(DMsb-1 DOWNTO 0),
Enable AND (NOT DataAlias(DMsb)), ResultMap );
ELSE RETURN "X";
END IF;
END;
-- ------------------------------------------------------------------------
-- N-bit wide Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( ADataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( ADataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXOR ( Data );
new_schd := VitalXOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNAND(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '1';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue AND Data(i);
new_schd := new_schd AND Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
InvPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
InvPath ( Data_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := '0';
new_schd := Data_Schd(Data_Schd'LEFT);
FOR i IN Data'RANGE LOOP
NewValue := NewValue OR Data(i);
new_schd := new_schd OR Data_Schd(i);
END LOOP;
NewValue := NOT NewValue;
new_schd := NOT new_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE DataB_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE DataI_Schd : SchedArray(1 TO Data'LENGTH);
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS ADataB_Schd : SchedArray(Data'RANGE) IS DataB_Schd;
ALIAS ADataI_Schd : SchedArray(Data'RANGE) IS DataI_Schd;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalXNOR(Data, ResultMap);
WAIT ON Data;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( ADataB_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( ADataI_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( ADataB_Schd, Data_Edge, Atpd_data_q );
InvPath ( ADataI_Schd, Data_Edge, Atpd_data_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalXNOR ( Data );
new_schd := VitalXNOR ( DataB_Schd, DataI_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data;
END LOOP;
END IF; --SN
END;
--
-- ------------------------------------------------------------------------
-- Commonly used 2-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b;
new_schd := a_schd AND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b;
new_schd := a_schd OR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NAND b;
new_schd := a_schd NAND b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a NOR b;
new_schd := a_schd NOR b_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b;
new_schd := VitalXOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd : SchedType;
VARIABLE ai_schd, bi_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ((tpd_a_q = VitalZeroDelay01) AND (tpd_b_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR2 ( a, b, ResultMap );
WAIT ON a, b;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b);
new_schd := VitalXNOR2 ( ab_schd,ai_schd, bb_schd,bi_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 3-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
--
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c;
new_schd := a_schd AND b_schd AND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c;
new_schd := a_schd OR b_schd OR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND c;
new_schd := (a_schd AND b_schd) NAND c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR c;
new_schd := (a_schd OR b_schd) NOR c_schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c;
new_schd := VitalXOR3 ( ab_schd,ai_schd,
bb_schd,bi_schd,
cb_schd,ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR3 ( a, b, c, ResultMap );
WAIT ON a, b, c;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c);
new_schd := VitalXNOR3 ( ab_schd, ai_schd,
bb_schd, bi_schd,
cb_schd, ci_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Commonly used 4-bit Logical gates.
-- ------------------------------------------------------------------------
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a AND b AND c AND d;
new_schd := a_schd AND b_schd AND c_schd AND d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( a_schd, InitialEdge(a), tpd_a_q );
BufPath ( b_schd, InitialEdge(b), tpd_b_q );
BufPath ( c_schd, InitialEdge(c), tpd_c_q );
BufPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( a_schd, GetEdge(a), tpd_a_q );
BufPath ( b_schd, GetEdge(b), tpd_b_q );
BufPath ( c_schd, GetEdge(c), tpd_c_q );
BufPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a OR b OR c OR d;
new_schd := a_schd OR b_schd OR c_schd OR d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNAND4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a AND b) NAND (c AND d);
new_schd := (a_schd AND b_schd) NAND (c_schd AND d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE a_schd, b_schd, c_schd, d_Schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( a_schd, InitialEdge(a), tpd_a_q );
InvPath ( b_schd, InitialEdge(b), tpd_b_q );
InvPath ( c_schd, InitialEdge(c), tpd_c_q );
InvPath ( d_Schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( a_schd, GetEdge(a), tpd_a_q );
InvPath ( b_schd, GetEdge(b), tpd_b_q );
InvPath ( c_schd, GetEdge(c), tpd_c_q );
InvPath ( d_Schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := (a OR b) NOR (c OR d);
new_schd := (a_schd OR b_schd) NOR (c_schd OR d_Schd);
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := a XOR b XOR c XOR d;
new_schd := VitalXOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
--
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE ab_schd, bb_schd, cb_schd, DB_Schd : SchedType;
VARIABLE ai_schd, bi_schd, ci_schd, di_schd : SchedType;
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_a_q = VitalZeroDelay01)
AND (tpd_b_q = VitalZeroDelay01)
AND (tpd_c_q = VitalZeroDelay01)
AND (tpd_d_q = VitalZeroDelay01)) THEN
LOOP
q <= VitalXNOR4 ( a, b, c, d, ResultMap );
WAIT ON a, b, c, d;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( ab_schd, InitialEdge(a), tpd_a_q );
InvPath ( ai_schd, InitialEdge(a), tpd_a_q );
BufPath ( bb_schd, InitialEdge(b), tpd_b_q );
InvPath ( bi_schd, InitialEdge(b), tpd_b_q );
BufPath ( cb_schd, InitialEdge(c), tpd_c_q );
InvPath ( ci_schd, InitialEdge(c), tpd_c_q );
BufPath ( DB_Schd, InitialEdge(d), tpd_d_q );
InvPath ( di_schd, InitialEdge(d), tpd_d_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( ab_schd, GetEdge(a), tpd_a_q );
InvPath ( ai_schd, GetEdge(a), tpd_a_q );
BufPath ( bb_schd, GetEdge(b), tpd_b_q );
InvPath ( bi_schd, GetEdge(b), tpd_b_q );
BufPath ( cb_schd, GetEdge(c), tpd_c_q );
InvPath ( ci_schd, GetEdge(c), tpd_c_q );
BufPath ( DB_Schd, GetEdge(d), tpd_d_q );
InvPath ( di_schd, GetEdge(d), tpd_d_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT (a XOR b XOR c XOR d);
new_schd := VitalXNOR4 ( ab_schd,ai_schd, bb_schd,bi_schd,
cb_schd,ci_schd, DB_Schd,di_schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON a, b, c, d;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Buffers
-- BUF ....... standard non-inverting buffer
-- BUFIF0 ....... non-inverting buffer Data passes thru if (Enable = '0')
-- BUFIF1 ....... non-inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(To_UX01(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := To_UX01(a); -- convert to forcing strengths
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr01);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr10);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF1( Data, Enable );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalBUFIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalBUFIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
d_Schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
SUBTYPE v2 IS std_logic_vector(0 TO 1);
VARIABLE NewValue : UX01Z;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_a_q = VitalZeroDelay01Z) THEN
LOOP
q <= ResultMap(To_UX01Z(a));
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
CASE v2'(To_X01Z(NewValue) & To_X01Z(a)) IS
WHEN "00" => Dly := tpd_a_q(tr10);
WHEN "01" => Dly := tpd_a_q(tr01);
WHEN "0Z" => Dly := tpd_a_q(tr0z);
WHEN "0X" => Dly := tpd_a_q(tr01);
WHEN "10" => Dly := tpd_a_q(tr10);
WHEN "11" => Dly := tpd_a_q(tr01);
WHEN "1Z" => Dly := tpd_a_q(tr1z);
WHEN "1X" => Dly := tpd_a_q(tr10);
WHEN "Z0" => Dly := tpd_a_q(trz0);
WHEN "Z1" => Dly := tpd_a_q(trz1);
WHEN "ZZ" => Dly := 0 ns;
WHEN "ZX" => Dly := Minimum (tpd_a_q(trz1), tpd_a_q(trz0));
WHEN "X0" => Dly := tpd_a_q(tr10);
WHEN "X1" => Dly := tpd_a_q(tr01);
WHEN "XZ" => Dly := Minimum (tpd_a_q(tr0z), tpd_a_q(tr1z));
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
NewValue := To_UX01Z(a);
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Invertors
-- INV ......... standard inverting buffer
-- INVIF0 ......... inverting buffer Data passes thru if (Enable = '0')
-- INVIF1 ......... inverting buffer Data passes thru if (Enable = '1')
-- ------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic ;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
IF (tpd_a_q = VitalZeroDelay01) THEN
LOOP
q <= ResultMap(NOT a);
WAIT ON a;
END LOOP;
ELSE
LOOP
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := NOT a;
CASE EdgeType'(GetEdge(a)) IS
WHEN '1'|'/'|'R'|'r' => Dly := tpd_a_q(tr10);
WHEN '0'|'\'|'F'|'f' => Dly := tpd_a_q(tr01);
WHEN OTHERS => Dly := Minimum (tpd_a_q(tr01), tpd_a_q(tr10));
END CASE;
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode );
WAIT ON a;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF1( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
BufEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF1( Data, Enable );
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, e1_Schd, e0_Schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) IS
VARIABLE NewValue : UX01Z;
VARIABLE new_schd : SchedType;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE d_Schd, e1_Schd, e0_Schd : SchedType;
VARIABLE ne1_schd, ne0_schd : SchedType := DefSchedType;
VARIABLE Dly, Glch : TIME;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_data_q = VitalZeroDelay01 )
AND (tpd_enable_q = VitalZeroDelay01Z)) THEN
LOOP
q <= VitalINVIF0( Data, Enable, ResultMap );
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
InvPath ( d_Schd, InitialEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
InvPath ( d_Schd, GetEdge(Data), tpd_data_q );
InvEnab ( e1_Schd, e0_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delay
-- ------------------------------------
NewValue := VitalINVIF0( Data, Enable );
ne1_schd := NOT e1_Schd;
ne0_schd := NOT e0_Schd;
new_schd := NOT d_Schd;
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data),
new_schd, ne1_schd, ne0_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
-- Multiplexor
-- MUX .......... result := data(dselect)
-- MUX2 .......... 2-input mux; result := data0 when (dselect = '0'),
-- data1 when (dselect = '1'),
-- 'X' when (dselect = 'X') and (data0 /= data1)
-- MUX4 .......... 4-input mux; result := data(dselect)
-- MUX8 .......... 8-input mux; result := data(dselect)
-- ------------------------------------------------------------------------
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE d1_Schd, d0_Schd : SchedType;
VARIABLE dSel_bSchd, dSel_iSchd : SchedType;
VARIABLE d1_Edge, d0_Edge, dSel_Edge : EdgeType;
BEGIN
-- ------------------------------------------------------------------------
-- For ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF ( (tpd_d1_q = VitalZeroDelay01)
AND (tpd_d0_q = VitalZeroDelay01)
AND (tpd_dsel_q = VitalZeroDelay01) ) THEN
LOOP
q <= VitalMUX2 ( d1, d0, dSel, ResultMap );
WAIT ON d1, d0, dSel;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( d1_Schd, InitialEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, InitialEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, InitialEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, InitialEdge(dSel), tpd_dsel_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( d1_Schd, GetEdge(d1), tpd_d1_q );
BufPath ( d0_Schd, GetEdge(d0), tpd_d0_q );
BufPath ( dSel_bSchd, GetEdge(dSel), tpd_dsel_q );
InvPath ( dSel_iSchd, GetEdge(dSel), tpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX2 ( d1, d0, dSel );
new_schd := VitalMUX2 ( d1_Schd, d0_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON d1, d0, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray4;
VARIABLE Data_Edge : EdgeArray4;
VARIABLE dSel_Edge : EdgeArray2;
VARIABLE dSel_bSchd : SchedArray2;
VARIABLE dSel_iSchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX4 ( Data, dSel );
new_schd := VitalMUX4 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray8;
VARIABLE Data_Edge : EdgeArray8;
VARIABLE dSel_Edge : EdgeArray3;
VARIABLE dSel_bSchd : SchedArray3;
VARIABLE dSel_iSchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX8 ( Data, dSel );
new_schd := VitalMUX8 ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF;
END;
--
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE LastdSel : std_logic_vector(dSel'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : UX01;
VARIABLE Glitch_Data : GlitchDataType;
VARIABLE new_schd : SchedType;
VARIABLE Dly, Glch : TIME;
VARIABLE Data_Schd : SchedArray(Data'RANGE);
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE dSel_Edge : EdgeArray(dSel'RANGE);
VARIABLE dSel_bSchd : SchedArray(dSel'RANGE);
VARIABLE dSel_iSchd : SchedArray(dSel'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
ALIAS Atpd_dsel_q : VitalDelayArrayType01(dSel'RANGE) IS tpd_dsel_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
FOR i IN dSel'RANGE LOOP
IF (Atpd_dsel_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
IF (AllZeroDelay) THEN LOOP
q <= VitalMUX(Data, dSel, ResultMap);
WAIT ON Data, dSel;
END LOOP;
END IF;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_Schd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
FOR n IN dSel'RANGE LOOP
BufPath ( dSel_bSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
InvPath ( dSel_iSchd(n), InitialEdge(dSel(n)), Atpd_dsel_q(n) );
END LOOP;
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_Schd, Data_Edge, Atpd_data_q );
GetEdge ( dSel, LastdSel, dSel_Edge );
BufPath ( dSel_bSchd, dSel_Edge, Atpd_dsel_q );
InvPath ( dSel_iSchd, dSel_Edge, Atpd_dsel_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalMUX ( Data, dSel );
new_schd := VitalMUX ( Data_Schd, dSel_bSchd, dSel_iSchd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, ResultMap(NewValue), Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, dSel;
END LOOP;
END IF; --SN
END;
-- ------------------------------------------------------------------------
-- Decoder
-- General Algorithm :
-- (a) Result(...) := '0' when (enable = '0')
-- (b) Result(data) := '1'; all other subelements = '0'
-- ... Result array is decending (n-1 downto 0)
--
-- DECODERn .......... n:2**n decoder
-- Caution: If 'ResultMap' defines other than strength mapping, the
-- delay selection is not defined.
-- ------------------------------------------------------------------------
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE NewValue : std_logic_vector2;
VARIABLE Glitch_Data : GlitchArray2;
VARIABLE new_schd : SchedArray2;
VARIABLE Dly, Glch : TimeArray2;
VARIABLE Enable_Schd : SchedType := DefSchedType;
VARIABLE Data_BSchd, Data_ISchd : SchedType;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q = VitalZeroDelay01) AND (tpd_data_q = VitalZeroDelay01) THEN
LOOP
q <= VitalDECODER2(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
BufPath ( Data_BSchd, InitialEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, InitialEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
BufPath ( Data_BSchd, GetEdge(Data), tpd_data_q );
InvPath ( Data_ISchd, GetEdge(Data), tpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER2 ( Data, Enable, ResultMap );
new_schd := VitalDECODER2 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; -- SN
END;
--
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector4;
VARIABLE Glitch_Data : GlitchArray4;
VARIABLE new_schd : SchedArray4;
VARIABLE Dly, Glch : TimeArray4;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray2;
VARIABLE Data_BSchd, Data_ISchd : SchedArray2;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER4(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER4 ( Data, Enable, ResultMap );
new_schd := VitalDECODER4 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
--
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector8;
VARIABLE Glitch_Data : GlitchArray8;
VARIABLE new_schd : SchedArray8;
VARIABLE Dly, Glch : TimeArray8;
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray3;
VARIABLE Data_BSchd, Data_ISchd : SchedArray3;
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE; --SN
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER8 ( Data, Enable, ResultMap );
new_schd := VitalDECODER8 ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF; --SN
END;
--
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) IS
VARIABLE LastData : std_logic_vector(Data'RANGE) := (OTHERS=>'U');
VARIABLE NewValue : std_logic_vector(q'RANGE);
VARIABLE Glitch_Data : GlitchDataArrayType(q'RANGE);
VARIABLE new_schd : SchedArray(q'RANGE);
VARIABLE Dly, Glch : VitalTimeArray(q'RANGE);
VARIABLE Enable_Schd : SchedType;
VARIABLE Enable_Edge : EdgeType;
VARIABLE Data_Edge : EdgeArray(Data'RANGE);
VARIABLE Data_BSchd, Data_ISchd : SchedArray(Data'RANGE);
ALIAS Atpd_data_q : VitalDelayArrayType01(Data'RANGE) IS tpd_data_q;
VARIABLE AllZeroDelay : BOOLEAN := TRUE;
BEGIN
-- ------------------------------------------------------------------------
-- Check if ALL zero delay paths, use simple model
-- ( No delay selection, glitch detection required )
-- ------------------------------------------------------------------------
IF (tpd_enable_q /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
ELSE
FOR i IN Data'RANGE LOOP
IF (Atpd_data_q(i) /= VitalZeroDelay01) THEN
AllZeroDelay := FALSE;
EXIT;
END IF;
END LOOP;
END IF;
IF (AllZeroDelay) THEN LOOP
q <= VitalDECODER(Data, Enable, ResultMap);
WAIT ON Data, Enable;
END LOOP;
ELSE
-- --------------------------------------
-- Initialize delay schedules
-- --------------------------------------
FOR n IN Data'RANGE LOOP
BufPath ( Data_BSchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
InvPath ( Data_ISchd(n), InitialEdge(Data(n)), Atpd_data_q(n) );
END LOOP;
BufPath ( Enable_Schd, InitialEdge(Enable), tpd_enable_q );
LOOP
-- --------------------------------------
-- Process input signals
-- get edge values
-- re-evaluate output schedules
-- --------------------------------------
GetEdge ( Data, LastData, Data_Edge );
BufPath ( Data_BSchd, Data_Edge, Atpd_data_q );
InvPath ( Data_ISchd, Data_Edge, Atpd_data_q );
BufPath ( Enable_Schd, GetEdge(Enable), tpd_enable_q );
-- ------------------------------------
-- Compute function and propation delaq
-- ------------------------------------
NewValue := VitalDECODER ( Data, Enable, ResultMap );
new_schd := VitalDECODER ( Data_BSchd, Data_ISchd, Enable_Schd );
-- ------------------------------------------------------
-- Assign Outputs
-- get delays to new value and possable glitch
-- schedule output change with On Event glitch detection
-- ------------------------------------------------------
GetSchedDelay ( Dly, Glch, NewValue, CurValue(Glitch_Data), new_schd );
VitalGlitchOnEvent ( q, "q", Glitch_Data, NewValue, Dly,
PrimGlitchMode, GlitchDelay=>Glch );
WAIT ON Data, Enable;
END LOOP;
END IF;
END;
-- ------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE ReturnValue : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO InputSize - 1)
:= To_X01(DataIn);
VARIABLE Index : INTEGER;
VARIABLE Err : BOOLEAN := FALSE;
-- This needs to be done since the TableLookup arrays must be
-- ascending starting with 0
VARIABLE TableAlias : VitalTruthTableType(0 TO (TruthTable'LENGTH(1)-1),
0 TO (TruthTable'LENGTH(2)-1))
:= TruthTable;
BEGIN
-- search through each row of the truth table
IF OutSize > 0 THEN
ColLoop:
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each input element of the entry
FOR j IN 0 TO InputSize LOOP
IF (j = InputSize) THEN -- This entry matches
-- Return the Result
Index := 0;
FOR k IN TruthTable'LENGTH(2) - 1 DOWNTO InputSize LOOP
TruthOutputX01Z ( TableAlias(i,k),
ReturnValue(Index), Err);
EXIT WHEN Err;
Index := Index + 1;
END LOOP;
IF Err THEN
ReturnValue := (OTHERS => 'X');
END IF;
RETURN ReturnValue;
END IF;
IF NOT ValidTruthTableInput(TableAlias(i,j)) THEN
VitalError ( "VitalTruthTable", ErrInpSym,
To_TruthChar(TableAlias(i,j)) );
EXIT ColLoop;
END IF;
EXIT RowLoop WHEN NOT ( TruthTableMatch( DataInAlias(j),
TableAlias(i, j)));
END LOOP RowLoop;
END LOOP ColLoop;
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
END IF;
RETURN ReturnValue;
END VitalTruthTable;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := TruthTable'LENGTH(2) - InputSize;
VARIABLE TempResult : std_logic_vector(OutSize - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
IF (OutSize > 0) THEN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
RETURN (TempResult(0));
ELSE
VitalError ( "VitalTruthTable", ErrTabWidSml );
RETURN 'X';
END IF;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
) IS
CONSTANT ResLeng : INTEGER := Result'LENGTH;
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
CONSTANT FinalResLen : INTEGER := Minimum(ActResLen, ResLeng);
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF (ResLeng > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF (ResLeng < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
TempResult(FinalResLen-1 DOWNTO 0) := TempResult(FinalResLen-1 DOWNTO 0);
Result <= TempResult;
END VitalTruthTable;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
) IS
CONSTANT ActResLen : INTEGER := TruthTable'LENGTH(2) - DataIn'LENGTH;
VARIABLE TempResult : std_logic_vector(ActResLen - 1 DOWNTO 0)
:= (OTHERS => 'X');
BEGIN
TempResult := VitalTruthTable(TruthTable, DataIn);
IF ( 1 > ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResSml );
ELSIF ( 1 < ActResLen) THEN
VitalError ( "VitalTruthTable", ErrTabResLrg );
END IF;
IF (ActResLen > 0) THEN
Result <= TempResult(0);
END IF;
END VitalTruthTable;
-- ------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1)
:= To_X01(DataIn);
VARIABLE PrevDataAlias : std_logic_vector(0 TO PreviousDataIn'LENGTH-1)
:= To_X01(PreviousDataIn);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1)
:= To_X01(Result);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (PreviousDataIn'LENGTH < DataIn'LENGTH) THEN
VitalError ( "VitalStateTable", ErrVctLng, "PreviousDataIn<DataIn");
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSIF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result := ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevDataAlias, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias ( Maximum(0, ResLeng - OutSize) TO ResLeng - 1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result := ResultAlias;
PrevDataAlias(0 TO InputSize - 1) := DataInAlias;
PreviousDataIn := PrevDataAlias;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic; -- states
VARIABLE PreviousDataIn : INOUT std_logic_vector; -- previous inputs and states
CONSTANT StateTable : IN VitalStateTableType; -- User's StateTable data
CONSTANT DataIn : IN std_logic_vector -- Inputs
) IS
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
BEGIN
ResultAlias(0) := Result;
VitalStateTable ( StateTable => StateTable,
DataIn => DataIn,
NumStates => 1,
Result => ResultAlias,
PreviousDataIn => PreviousDataIn
);
Result := ResultAlias(0);
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER
:= StateTable'LENGTH(2) - InputSize - NumStates;
CONSTANT ResLeng : INTEGER := Result'LENGTH;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO ResLeng-1);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
ResultAlias := (OTHERS => 'X');
Result <= ResultAlias;
ELSE
IF (ResLeng > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF (ResLeng < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
DataInAlias := To_X01(DataIn);
ResultAlias := To_X01(Result);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, NumStates,
ResultAlias);
ResultAlias := (OTHERS => 'X');
ResultAlias(Maximum(0, ResLeng - OutSize) TO ResLeng-1)
:= ExpResult(Maximum(0, OutSize - ResLeng) TO OutSize-1);
Result <= ResultAlias;
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
) IS
CONSTANT InputSize : INTEGER := DataIn'LENGTH;
CONSTANT OutSize : INTEGER := StateTable'LENGTH(2) - InputSize-1;
VARIABLE PrevData : std_logic_vector(0 TO DataIn'LENGTH-1)
:= (OTHERS => 'X');
VARIABLE DataInAlias : std_logic_vector(0 TO DataIn'LENGTH-1);
VARIABLE ResultAlias : std_logic_vector(0 TO 0);
VARIABLE ExpResult : std_logic_vector(0 TO OutSize-1);
BEGIN
IF (OutSize <= 0) THEN
VitalError ( "VitalStateTable", ErrTabWidSml );
Result <= 'X';
ELSE
IF ( 1 > OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResSml );
ELSIF ( 1 < OutSize) THEN
VitalError ( "VitalStateTable", ErrTabResLrg );
END IF;
LOOP
ResultAlias(0) := To_X01(Result);
DataInAlias := To_X01(DataIn);
ExpResult := StateTableLookUp ( StateTable, DataInAlias,
PrevData, 1, ResultAlias);
Result <= ExpResult(OutSize-1);
PrevData := DataInAlias;
WAIT ON DataIn;
END LOOP;
END IF;
END VitalStateTable;
-- ------------------------------------------------------------------------
-- std_logic resolution primitive
-- ------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector --IR236 4/2/98
) IS
VARIABLE uData : std_ulogic_vector(Data'RANGE);
BEGIN
FOR i IN Data'RANGE LOOP
uData(i) := Data(i);
END LOOP;
q <= resolved(uData);
END;
END VITAL_Primitives;
| gpl-2.0 | 8b02dc6f90d9c69ead4c4d68b570f181 | 0.451318 | 4.994066 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/MurmurHash32Generator.vhdl | 1 | 21,731 | -- Murmur Hash Code Generator
-- Author: Raul Gerardo Huertas Paiva
--Copyright (c) 2014, Raul Huertas
--All rights reserved.
----Redistribution and use in source and binary forms, with or without
----modification, are permitted provided that the following conditions are met:
----
----1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
--ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
--WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
--ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
--ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
--(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
--SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--The views and conclusions contained in the software and documentation are those
--of the authors and should not be interpreted as representing official policies,
--either expressed or implied, of the FreeBSD Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
entity MurmurHash32Generator is
generic (
ID_PRESENT: boolean := true;
ID_LENGTH: integer := 31
);
port(
--ENTRADAS
inputBlock : in std_logic_vector(31 downto 0);
readInput : in std_logic;
blockLength : in std_logic_vector(1 downto 0);
finalBlock : in std_logic;
start : in std_logic;
operationID : in std_logic_vector(ID_LENGTH downto 0);
seed : in std_logic_vector(31 downto 0);
--SALIDAS
canAccept : out std_logic;
resultReady : out std_logic;
result : out std_logic_vector(31 downto 0);
resultID : out std_logic_vector(ID_LENGTH downto 0);
--RELOJ
clk : in std_logic;
--Salidas de depuracion
dataStep1_dbg : out std_logic_vector(31 downto 0);
dataStep2_dbg : out std_logic_vector(31 downto 0);
dataStep3_dbg : out std_logic_vector(31 downto 0);
dataStep4_dbg : out std_logic_vector(31 downto 0);
dataStep5_dbg : out std_logic_vector(31 downto 0);
dataStep1_ID_dbg : out std_logic_vector(31 downto 0);
dataStep2_ID_dbg : out std_logic_vector(31 downto 0);
dataStep3_ID_dbg : out std_logic_vector(31 downto 0);
dataStep4_ID_dbg : out std_logic_vector(31 downto 0);
dataStep5_ID_dbg : out std_logic_vector(31 downto 0);
dataStepA_dbg : out std_logic_vector(31 downto 0);
dataStepB_dbg : out std_logic_vector(31 downto 0);
dataStepC_dbg : out std_logic_vector(31 downto 0);
dataStepD_dbg : out std_logic_vector(31 downto 0);
dataStepA_ID_dbg : out std_logic_vector(31 downto 0);
dataStepB_ID_dbg : out std_logic_vector(31 downto 0);
dataStepC_ID_dbg : out std_logic_vector(31 downto 0);
dataStepD_ID_dbg : out std_logic_vector(31 downto 0);
finalStep1_dbg : out std_logic_vector(31 downto 0);
finalStep2_dbg : out std_logic_vector(31 downto 0);
finalStep3_dbg : out std_logic_vector(31 downto 0);
finalStep4_dbg : out std_logic_vector(31 downto 0);
finalStep5_dbg : out std_logic_vector(31 downto 0);
finalStep1_ID_dbg : out std_logic_vector(31 downto 0);
finalStep2_ID_dbg : out std_logic_vector(31 downto 0);
finalStep3_ID_dbg : out std_logic_vector(31 downto 0);
finalStep4_ID_dbg : out std_logic_vector(31 downto 0);
finalStep5_ID_dbg : out std_logic_vector(31 downto 0)
);
end MurmurHash32Generator;
architecture Estructural of MurmurHash32Generator is
signal trabajando : boolean ;
-- Resultados de analizar datos alineados a 4 bytes
signal resultStep1 : Step1_Capture;
signal resultStep2 : Step2_C1Mult;
signal resultStep3 : Step3_R1;
signal resultStep4 : Step4_C2Mult;
signal resultStep5 : Step5_HashResult;
-- Resultados de analizar datos NO alineados a 4 bytes
signal resultStepA : Step1_EndianSwap;
signal resultStepB : Step2_C1Mult;
signal resultStepC : Step3_R1;
signal resultStepD : Step4_C2Mult;
--Combinar ambos resultados
signal mixed : FinalStep;
signal finalStep1 : FinalStep;
signal finalStep2 : FinalStep;
signal finalStep3 : FinalStep;
signal finalStep4 : FinalStep;
signal finalStep5 : FinalStep;
signal finalStep6 : FinalStep;
signal lengthCounter: unsigned(31 downto 0);
signal stepAdata : std_logic_vector(31 downto 0);
signal CompletedDataA : std_logic_vector(31 downto 0);
signal CompletedDataB : std_logic_vector(31 downto 0);
signal CompletedDataC : std_logic_vector(31 downto 0);
signal dataBeatValidQ : boolean;
--balancing FF
signal resultReady_temp : std_logic;
signal result_temp : std_logic_vector(31 downto 0);
signal resultID_temp : std_logic_vector(ID_LENGTH downto 0);
begin
--Conectando las salidas de depuracion
dataStep1_dbg <= resultStep1.data;
dataStep2_dbg <= resultStep2.data;
dataStep3_dbg <= resultStep3.data;
dataStep4_dbg <= resultStep4.data;
dataStep5_dbg <= resultStep5.hash;
dataStepA_dbg <= resultStepA.data;
dataStepA_ID_dbg <= resultStepA.operationID;
dataStepB_dbg <= resultStepB.data;
dataStepB_ID_dbg <= resultStepB.operationID;
dataStepC_dbg <= resultStepC.data;
dataStepC_ID_dbg <= resultStepC.operationID;
dataStepD_dbg <= resultStepD.data;
dataStepD_ID_dbg <= resultStepD.operationID;
dataStep1_ID_dbg <= resultStep1.operationID;
dataStep2_ID_dbg <= resultStep2.operationID;
dataStep3_ID_dbg <= resultStep3.operationID;
dataStep4_ID_dbg <= resultStep4.operationID;
dataStep5_ID_dbg <= resultStep5.operationID;
finalStep1_dbg <= finalStep1.hash;
finalStep2_dbg <= finalStep2.hash;
finalStep3_dbg <= finalStep3.hash;
finalStep4_dbg <= finalStep4.hash;
finalStep5_dbg <= finalStep5.hash;
finalStep1_ID_dbg <= finalStep1.operationID;
finalStep2_ID_dbg <= finalStep2.operationID;
finalStep3_ID_dbg <= finalStep3.operationID;
finalStep4_ID_dbg <= finalStep4.operationID;
finalStep5_ID_dbg <= finalStep5.operationID;
canAccept <= '1';-- Siemrpe se debe poder recibir datos en este core
--Definiendo la captura de datos
CaptureStep: process(clk, inputBlock, readInput, blockLength, finalBlock, start, operationID, seed) begin
if rising_edge(clk) then
if(readInput = '1') then
resultStep1.data <= (inputBlock);
resultStep1.dataLength <= blockLength;
resultStep1.isFirst <= (start='1');
resultStep1.isLast <= (finalBlock='1');
if (start='1') then
resultStep1.operationID <= operationID;
end if;
resultStep1.seed <= seed;
end if;--readInput
resultStep1.dataValid <= (readInput='1');
end if;--clk
end process CaptureStep;
C1MultStep: process(clk, resultStep1)
variable c1MutlResult : std_logic_vector(63 downto 0);
variable dataBeatValidQ : boolean;
begin
c1MutlResult := (resultStep1.data*C1);
dataBeatValidQ := resultStep1.dataValid and (resultStep1.dataLength="11");
if rising_edge(clk) then
if(dataBeatValidQ) then
resultStep2.data <= c1MutlResult(31 downto 0);
resultStep2.dataLength <= resultStep1.dataLength;
resultStep2.isFirst <= resultStep1.isFirst;
resultStep2.isLast <= resultStep1.isLast;
resultStep2.operationID <= resultStep1.operationID;
resultStep2.seed <= resultStep1.seed;
end if;--readInput
resultStep2.dataValid <= dataBeatValidQ;
end if;--clk
end process C1MultStep;
CompletedDataA <= x"00"&x"00"&x"00"&resultStep1.data(7 downto 0);
CompletedDataB <= x"00"&x"00"&resultStep1.data(15 downto 0);
CompletedDataC <= x"00"&resultStep1.data(23 downto 0);
with resultStep1.dataLength select
stepAdata <= CompletedDataA when "00",
CompletedDataB when "01",
CompletedDataC when "10",
(others => '-') when others;
dataBeatValidQ <= (resultStep1.dataValid) and (resultStep1.dataLength/="11");
StepA_EndianSwapProcess: process(clk, resultStep1, stepAdata, dataBeatValidQ)
begin
-- if (resultStep1.dataLength="00") then
-- stepAdata := CompletedDataA;
-- elsif (resultStep1.dataLength="01") then
-- stepAdata := CompletedDataB;
-- elsif (resultStep1.dataLength="10") then
-- stepAdata := CompletedDataC;
-- else
-- stepAdata := (others => '-');
-- end if;
-- case resultStep1.dataLength is
-- when "00" => stepAdata := CompletedDataA;
-- when "01" => stepAdata := CompletedDataB;
-- when "10" => stepAdata := CompletedDataC;
-- when others => stepAdata := (others => '-');
-- end case;
if rising_edge(clk) then
if(dataBeatValidQ) then
resultStepA.data <= stepAdata;
resultStepA.dataLength <= resultStep1.dataLength;
resultStepA.isFirst <= resultStep1.isFirst;
resultStepA.isLast <= resultStep1.isLast;
resultStepA.operationID <= resultStep1.operationID;
resultStepA.seed <= resultStep1.seed;
end if;
resultStepA.dataValid <= dataBeatValidQ;
end if;--clk
end process StepA_EndianSwapProcess;
StepB_C1Mult: process(clk, resultStepA)
variable c1MutlResult : std_logic_vector(63 downto 0);
begin
c1MutlResult := (resultStepA.data*C1);
if rising_edge(clk) then
if(resultStepA.dataValid) then
resultStepB.data <= c1MutlResult(31 downto 0);
resultStepB.dataLength <= resultStepA.dataLength;
resultStepB.isFirst <= resultStepA.isFirst;
resultStepB.isLast <= resultStepA.isLast;
resultStepB.operationID <= resultStepA.operationID;
resultStepB.seed <= resultStepA.seed;
end if;--readInput
resultStepB.dataValid <= resultStepA.dataValid;
end if;--clk
end process StepB_C1Mult;
StepC_R1Rotation: process(clk, resultStepB)
begin
if rising_edge(clk) then
if(resultStepB.dataValid) then
resultStepC.data(31 downto 15) <= resultStepB.data(16 downto 0);
resultStepC.data(14 downto 0) <= resultStepB.data(31 downto 17);
resultStepC.dataLength <= resultStepB.dataLength;
resultStepC.isFirst <= resultStepB.isFirst;
resultStepC.isLast <= resultStepB.isLast;
resultStepC.operationID <= resultStepB.operationID;
resultStepC.seed <= resultStepB.seed;
end if;--readInput
resultStepC.dataValid <= resultStepB.dataValid;
end if;--clk
end process StepC_R1Rotation;
StepD_C2Mult: process(clk, resultStepC)
variable c2MutlResult : std_logic_vector(63 downto 0);
begin
c2MutlResult := (resultStepC.data*C2);
if rising_edge(clk) then
if(resultStepC.dataValid) then
resultStepD.data <= c2MutlResult(31 downto 0);
resultStepD.dataLength <= resultStepC.dataLength;
resultStepD.isFirst <= resultStepC.isFirst;
resultStepD.isLast <= resultStepC.isLast;
resultStepD.operationID <= resultStepC.operationID;
resultStepD.seed <= resultStepC.seed;
end if;--readInput
resultStepD.dataValid <= resultStepC.dataValid;
end if;--clk
end process StepD_C2Mult;
R1Step: process(clk, resultStep2)
begin
if rising_edge(clk) then
if(resultStep2.dataValid) then
resultStep3.data(31 downto 15) <= resultStep2.data(16 downto 0);
resultStep3.data(14 downto 0) <= resultStep2.data(31 downto 17);
resultStep3.dataLength <= resultStep2.dataLength;
resultStep3.isFirst <= resultStep2.isFirst;
resultStep3.isLast <= resultStep2.isLast;
resultStep3.operationID <= resultStep2.operationID;
resultStep3.seed <= resultStep2.seed;
end if;--readInput
resultStep3.dataValid <= resultStep2.dataValid;
end if;--clk
end process R1Step;
C2MultStep: process(clk, resultStep3)
variable c2MutlResult : std_logic_vector(63 downto 0);
begin
c2MutlResult := (resultStep3.data*C2);
if rising_edge(clk) then
if(resultStep3.dataValid) then
resultStep4.data <= c2MutlResult(31 downto 0);
resultStep4.dataLength <= resultStep3.dataLength;
resultStep4.isFirst <= resultStep3.isFirst;
resultStep4.isLast <= resultStep3.isLast;
resultStep4.operationID <= resultStep3.operationID;
resultStep4.seed <= resultStep3.seed;
end if;--readInput
resultStep4.dataValid <= resultStep3.dataValid;
end if;--clk
end process C2MultStep;
UpdateHashStep: process(clk, resultStep4, resultStep5, resultStepD)
variable dataAvailable : boolean;
variable selectOrigin: std_logic_vector( 1 downto 0 );
variable newHash: std_logic_vector( 31 downto 0 );
begin
if rising_edge(clk) then
dataAvailable := resultStep4.dataValid or resultStepD.dataValid;
selectOrigin := mh3_boolean_to_std_logic(resultStep4.dataValid) & mh3_boolean_to_std_logic(resultStepD.dataValid);
if(dataAvailable) then
case selectOrigin is
when "01" =>
if(resultStepD.isFirst)then
newHash := resultStepD.seed xor resultStepD.data;
else
newHash := resultStep5.hash xor resultStepD.data;
end if;
resultStep5.operationID <= resultStepD.operationID;
resultStep5.isFirst <= (resultStepD.isFirst);
resultStep5.isLast <= (resultStepD.isLast);
resultStep5.dataLength <= resultStepD.dataLength;
when "10" =>
if(resultStep4.isFirst)then
newHash :=funcionFinalHashOperation_4B(resultStep4.seed, resultStep4.data);
else
newHash := funcionFinalHashOperation_4B(resultStep5.hash, resultStep4.data);
end if;
resultStep5.operationID <= resultStep4.operationID;
resultStep5.isFirst <= (resultStep4.isFirst);
resultStep5.isLast <= (resultStep4.isLast);
resultStep5.dataLength <= resultStep4.dataLength;
when others =>
newHash := resultStep5.hash;
end case;
resultStep5.hash <= newHash;
end if;--readInput
resultStep5.resultReady <= dataAvailable;
end if;--clk
end process UpdateHashStep;
UpdateMix: process(clk, resultStep5, lengthCounter)
variable sum1 : unsigned(1 downto 0);
variable sum2 : unsigned(2 downto 0);
variable newLen : unsigned(31 downto 0);
begin
if rising_edge(clk) then
if(resultStep5.resultReady ) then
mixed.hash <= resultStep5.hash;
mixed.operationID <= resultStep5.operationID;
--mixed.totalLen <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"1000";
mixed.isFirst <= (resultStep5.isFirst);
mixed.isLast <= (resultStep5.isLast);
if (resultStep5.isFirst) then
sum1 := unsigned(resultStep5.dataLength);
sum2 := ("0"&sum1)+1;
newLen( 2 downto 0) := (sum2);
newLen(lengthCounter'HIGH downto 3) := ( others=> '0');
mixed.totalLen <= std_logic_vector(newLen);
lengthCounter <= newLen;
else
sum1 := unsigned(resultStep5.dataLength);
sum2 := ("0"&sum1)+1;
newLen:= (lengthCounter+sum2);
mixed.totalLen <= std_logic_vector(newLen);
lengthCounter <= newLen;
end if;
end if;--readInput
mixed.resultReady <= resultStep5.resultReady;
end if;--clk
end process UpdateMix;
FinalProc_Step1: process(clk, mixed)
begin
if rising_edge(clk) then
if(mixed.resultReady and mixed.isLast) then
finalStep1.hash <= mixed.hash xor mixed.totalLen;
finalStep1.operationID <= mixed.operationID;
finalStep1.totalLen <= mixed.totalLen;
finalStep1.isFirst <= (mixed.isFirst);
finalStep1.isLast <= (mixed.isLast);
end if;--readInput
finalStep1.resultReady <= mixed.resultReady and mixed.isLast;
end if;--clk
end process FinalProc_Step1;
FinalProc_Step2: process(clk, finalStep1)
begin
if rising_edge(clk) then
if(finalStep1.resultReady) then
finalStep2.hash <= xor_with_shiftRight(finalStep1.hash, FinalShift1);
finalStep2.operationID <= finalStep1.operationID;
finalStep2.totalLen <= finalStep1.totalLen;
finalStep2.isFirst <= finalStep1.isFirst;
finalStep2.isLast <= finalStep1.isLast;
end if;--readInput
finalStep2.resultReady <= finalStep1.resultReady;
end if;--clk
end process FinalProc_Step2;
FinalProc_Step3: process(clk, finalStep2)
variable fullMultResult : std_logic_vector( 63 downto 0);
begin
fullMultResult := finalStep2.hash*FinalC1;
if rising_edge(clk) then
if(finalStep2.resultReady) then
finalStep3.hash <= fullMultResult(31 downto 0);
finalStep3.operationID <= finalStep2.operationID;
finalStep3.isFirst <= (finalStep2.isFirst);
finalStep3.isLast <= (finalStep2.isLast);
finalStep3.totalLen <= finalStep2.totalLen;
end if;--readInput
finalStep3.resultReady <= finalStep2.resultReady;
end if;--clk
end process FinalProc_Step3;
FinalProc_Step4: process(clk, finalStep3)
begin
if rising_edge(clk) then
if(finalStep3.resultReady) then
finalStep4.hash <= xor_with_shiftRight(finalStep3.hash, FinalShift2);
finalStep4.operationID <= finalStep3.operationID;
--finalStep4.resultReady <= finalStep3.resultReady;
finalStep4.isFirst <= (finalStep3.isFirst);
finalStep4.isLast <= (finalStep3.isLast);
finalStep4.totalLen <= finalStep3.totalLen;
end if;--readInput
finalStep4.resultReady <= finalStep3.resultReady;
end if;--clk
end process FinalProc_Step4;
FinalProc_Step5: process(clk, finalStep4)
begin
if rising_edge(clk) then
if(finalStep4.resultReady) then
finalStep5.hash <= ClampedMult(finalStep4.hash , FinalC2);
finalStep5.operationID <= finalStep4.operationID;
finalStep5.totalLen <= finalStep4.totalLen;
finalStep5.isFirst <= (finalStep4.isFirst);
finalStep5.isLast <= (finalStep4.isLast);
end if;--readInput
finalStep5.resultReady <= finalStep4.resultReady;
end if;--clk
end process FinalProc_Step5;
FinalProc_Step6: process(clk, finalStep5)
begin
if rising_edge(clk) then
if(finalStep5.resultReady) then
finalStep6.hash <= xor_with_shiftRight(finalStep5.hash, FinalShift3);
finalStep6.operationID <= finalStep5.operationID;
finalStep6.totalLen <= finalStep5.totalLen;
finalStep6.isFirst <= (finalStep5.isFirst);
finalStep6.isLast <= (finalStep5.isLast);
end if;--readInput
finalStep6.resultReady <= finalStep5.resultReady and finalStep5.isLast;
end if;--clk
end process FinalProc_Step6;
--Conectando las salidas a este ultimo paso
resultReady_temp <= mh3_boolean_to_std_logic(finalStep6.resultReady);
result_temp <= finalStep6.hash;
resultID_temp <= finalStep6.operationID;
FinalStage: process(clk, resultReady_temp, result_temp, resultID_temp) begin
if rising_edge(clk) then
resultReady <= resultReady_temp;
result <= result_temp;
resultID <= resultID_temp;
end if;--clk
end process FinalStage;
end architecture Estructural;
| bsd-3-clause | a4d12dea1e3e93b90be38887a81fd32a | 0.627169 | 4.219612 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_tri_intersect_0_1/synth/triangle_intersect_tri_intersect_0_1.vhd | 1 | 8,024 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:hls:tri_intersect:1.0
-- IP Revision: 1605081815
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY triangle_intersect_tri_intersect_0_1 IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ins_TVALID : IN STD_LOGIC;
ins_TREADY : OUT STD_LOGIC;
ins_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ins_TDEST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TKEEP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ins_TSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ins_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TVALID : OUT STD_LOGIC;
outs_TREADY : IN STD_LOGIC;
outs_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
outs_TDEST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outs_TSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outs_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END triangle_intersect_tri_intersect_0_1;
ARCHITECTURE triangle_intersect_tri_intersect_0_1_arch OF triangle_intersect_tri_intersect_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF triangle_intersect_tri_intersect_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT tri_intersect IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ins_TVALID : IN STD_LOGIC;
ins_TREADY : OUT STD_LOGIC;
ins_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ins_TDEST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TKEEP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ins_TSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ins_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TVALID : OUT STD_LOGIC;
outs_TREADY : IN STD_LOGIC;
outs_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
outs_TDEST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outs_TSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outs_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT tri_intersect;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF triangle_intersect_tri_intersect_0_1_arch: ARCHITECTURE IS "tri_intersect,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF triangle_intersect_tri_intersect_0_1_arch : ARCHITECTURE IS "triangle_intersect_tri_intersect_0_1,tri_intersect,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF triangle_intersect_tri_intersect_0_1_arch: ARCHITECTURE IS "triangle_intersect_tri_intersect_0_1,tri_intersect,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=tri_intersect,x_ipVersion=1.0,x_ipCoreRevision=1605081815,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF ins_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ins_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TREADY";
ATTRIBUTE X_INTERFACE_INFO OF ins_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ins_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TDEST";
ATTRIBUTE X_INTERFACE_INFO OF ins_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF ins_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF ins_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TUSER";
ATTRIBUTE X_INTERFACE_INFO OF ins_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TLAST";
ATTRIBUTE X_INTERFACE_INFO OF ins_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TID";
ATTRIBUTE X_INTERFACE_INFO OF outs_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outs_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outs_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outs_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outs_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outs_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outs_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outs_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outs_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TID";
BEGIN
U0 : tri_intersect
PORT MAP (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
ins_TVALID => ins_TVALID,
ins_TREADY => ins_TREADY,
ins_TDATA => ins_TDATA,
ins_TDEST => ins_TDEST,
ins_TKEEP => ins_TKEEP,
ins_TSTRB => ins_TSTRB,
ins_TUSER => ins_TUSER,
ins_TLAST => ins_TLAST,
ins_TID => ins_TID,
outs_TVALID => outs_TVALID,
outs_TREADY => outs_TREADY,
outs_TDATA => outs_TDATA,
outs_TDEST => outs_TDEST,
outs_TKEEP => outs_TKEEP,
outs_TSTRB => outs_TSTRB,
outs_TUSER => outs_TUSER,
outs_TLAST => outs_TLAST,
outs_TID => outs_TID
);
END triangle_intersect_tri_intersect_0_1_arch;
| mit | cf2ec72a06adbddfe1615fa257e60636 | 0.717473 | 3.574165 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Union.vhd | 1 | 10,918 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:44:52 11/11/2017
-- Design Name:
-- Module Name: Union - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Union is
Port ( Clk : in STD_LOGIC;
reset : in STD_LOGIC;
Salidaunion :out STD_LOGIC_VECTOR(31 downto 0)
);
end Union;
architecture Behavioral of Union is
COMPONENT fetch
PORT(
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
CUentrada : in STD_LOGIC_VECTOR(1 downto 0);
Entradain : in STD_LOGIC_VECTOR (31 downto 0);
Instruccionout : out STD_LOGIC_VECTOR (31 downto 0);
PCout : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Barra1
PORT(
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
instrutin : in STD_LOGIC_VECTOR (31 downto 0);
PCin : in STD_LOGIC_VECTOR (31 downto 0);
instrutout : out STD_LOGIC_VECTOR (31 downto 0);
PCout : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Decode
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
posicionin : in STD_LOGIC_VECTOR (31 downto 0);
Regtomemin : in STD_LOGIC_VECTOR (31 downto 0);
cwpin : in STD_LOGIC;
iccin : in STD_LOGIC_VECTOR (3 downto 0);
Resetext : in STD_LOGIC;
ncwpout : out STD_LOGIC;
callout : out STD_LOGIC_VECTOR (31 downto 0);
ifout : out STD_LOGIC_VECTOR (31 downto 0);
rfsourceout : out STD_LOGIC_VECTOR (1 downto 0);
wrenmen : out STD_LOGIC;
pcsource : out STD_LOGIC_VECTOR (1 downto 0);
Cuentrada : out STD_LOGIC_VECTOR (1 downto 0);
aluop : out STD_LOGIC_VECTOR (5 downto 0);
a18 : out STD_LOGIC_VECTOR (31 downto 0);
crs1out : out STD_LOGIC_VECTOR (31 downto 0);
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
op2out : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Barra2
PORT(
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
ncwpin : in STD_LOGIC;
callin : in STD_LOGIC_VECTOR (31 downto 0);
ifin : in STD_LOGIC_VECTOR (31 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
wrenmenin : in STD_LOGIC;
pcsourcein : in STD_LOGIC_VECTOR (1 downto 0);
aluopin : in STD_LOGIC_VECTOR (5 downto 0);
a18in : in STD_LOGIC_VECTOR (31 downto 0);
crs1outin : in STD_LOGIC_VECTOR (31 downto 0);
op2outin : in STD_LOGIC_VECTOR (31 downto 0);
PCC : in STD_LOGIC_VECTOR (31 downto 0);
PCCout : out STD_LOGIC_VECTOR (31 downto 0);
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
Cuentradain : in STD_LOGIC_VECTOR (1 downto 0);
Cuentradaout : out STD_LOGIC_VECTOR (1 downto 0);
ncwpout : out STD_LOGIC;
callout : out STD_LOGIC_VECTOR (31 downto 0);
ifout : out STD_LOGIC_VECTOR (31 downto 0);
rfsourceout : out STD_LOGIC_VECTOR (1 downto 0);
wrenmen : out STD_LOGIC;
pcsource : out STD_LOGIC_VECTOR (1 downto 0);
aluop : out STD_LOGIC_VECTOR (5 downto 0);
a18 : out STD_LOGIC_VECTOR (31 downto 0);
crs1out : out STD_LOGIC_VECTOR (31 downto 0);
op2out : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Execute
PORT(
callin : in STD_LOGIC_VECTOR (31 downto 0);
ifin : in STD_LOGIC_VECTOR (31 downto 0);
pcsourcein : in STD_LOGIC_VECTOR (1 downto 0);
aluopin : in STD_LOGIC_VECTOR (5 downto 0);
op1in : in STD_LOGIC_VECTOR (31 downto 0);
op2in : in STD_LOGIC_VECTOR (31 downto 0);
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
nextpc : out STD_LOGIC_VECTOR (31 downto 0);
aluresult : out STD_LOGIC_VECTOR (31 downto 0);
Clkinext : in STD_LOGIC;
Resetext : in STD_LOGIC
);
END COMPONENT;
COMPONENT Barra3
PORT(
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
a18in : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
wrenmenin : in STD_LOGIC;
PCCin : in STD_LOGIC_VECTOR (31 downto 0);
PCCout : out STD_LOGIC_VECTOR (31 downto 0);
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
rfsource : in STD_LOGIC_VECTOR (1 downto 0);
a18inout : out STD_LOGIC_VECTOR (31 downto 0);
aluresultout : out STD_LOGIC_VECTOR (31 downto 0);
wrenmeninout : out STD_LOGIC;
rfsourceout : out STD_LOGIC_VECTOR (1 downto 0)
);
END COMPONENT;
COMPONENT Memory
PORT(
a18in : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
datatomenout : out STD_LOGIC_VECTOR (31 downto 0);
wrenmenin : in STD_LOGIC;
Resetext : in STD_LOGIC;
aluresultout : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Barra4
PORT(
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
datatomenin : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
pcin : in STD_LOGIC_VECTOR (31 downto 0);
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
rfsource : out STD_LOGIC_VECTOR (1 downto 0);
datatomenout : out STD_LOGIC_VECTOR (31 downto 0);
aluresultout : out STD_LOGIC_VECTOR (31 downto 0);
pcout : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT Writeback
PORT(
datatomenin : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
pc : in STD_LOGIC_VECTOR (31 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
datatoreg : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a1,a2,a5,a9,a10,a18n,a16,a17,a20,a21,a22,a23,a60: std_logic_vector(31 downto 0);
signal a4,a13,a15, a117,a118,a130,a139,a140a,a555: std_logic_vector(1 downto 0);
signal a8: std_logic_vector(3 downto 0);
signal a11,a126,a183,a184,a185,a186: std_logic_vector(5 downto 0);
signal a6,a7,a14,a115,a116,a129: std_logic;
signal a111,a112,a120,a121,a122,a123,a124,a125,a127,a128: std_logic_vector(31 downto 0);
signal a131,a132,a133,a138,a160,a180,a181,a182,a191,a668: std_logic_vector(31 downto 0);
begin ints_fetch: fetch PORT MAP(
Clk =>Clk,
Reset =>reset,
CUentrada =>a555,
Entradain =>a60,
Instruccionout =>a2,
PCout =>a1
);
ints_barra1: Barra1 PORT MAP(
Clk =>Clk,
Reset =>reset,
instrutin =>a2,
PCin =>a1,
instrutout =>a112,
PCout =>a111
);
ints_decode: Decode PORT MAP(
Instruction =>a112,
posicionin =>a111,
Regtomemin =>a23,
cwpin =>a6,
iccin =>a8,
Resetext =>reset,
ncwpout =>a7,
callout =>a17,
ifout =>a16,
rfsourceout =>a15,
wrenmen =>a14,
pcsource =>a13,
Cuentrada =>a4,
aluop =>a11,
a18 =>a18n,
crs1out =>a10,
RD =>a186,
RDout =>a183,
op2out =>a9
);
ints_barra2: Barra2 PORT MAP(
Clk =>Clk,
Reset =>reset,
ncwpin =>a7,
callin =>a17,
ifin =>a16,
rfsourcein =>a15,
wrenmenin =>a14,
pcsourcein =>a13,
aluopin =>a11,
a18in =>a18n,
crs1outin =>a10,
op2outin =>a9,
PCC =>a111,
PCCout =>a180,
RD =>a183,
RDout =>a184,
Cuentradain =>a13,
Cuentradaout =>a555,
ncwpout =>a115,
callout =>a120,
ifout =>a121,
rfsourceout =>a117,
wrenmen =>a116,
pcsource =>a118,
aluop =>a126,
a18 =>a122,
crs1out =>a123,
op2out =>a124
);
ints_execute: Execute PORT MAP(
callin =>a120,
ifin =>a121,
pcsourcein =>a118,
aluopin =>a126,
op1in =>a123,
op2in =>a124,
cwp =>a6,
ncwp =>a7,
icc =>a8,
nextpc =>a60,
aluresult =>a20,
Clkinext =>Clk,
Resetext =>reset
);
ints_Barra3: Barra3 PORT MAP(
Clk =>Clk,
Reset =>reset,
a18in=> a122,
aluresultin =>a20,
wrenmenin =>a116,
rfsource =>a117,
PCCin =>a180,
PCCout =>a181,
RD =>a184,
RDout =>a185,
a18inout =>a127,
aluresultout =>a668,
wrenmeninout =>a129,
rfsourceout =>a130
);
ints_memory: Memory PORT MAP(
Resetext =>reset,
a18in=>a127,
aluresultin =>a668,
wrenmenin =>a129,
datatomenout =>a21,
aluresultout =>a128
);
ints_Barra4: Barra4 PORT MAP(
Clk =>Clk,
Reset =>reset,
datatomenin =>a21,
aluresultin =>a128,
pcin =>a181,
rfsourcein =>a130,
RD =>a185,
RDout =>a186,
datatomenout =>a191,
aluresultout =>a133,
pcout=>a132,
rfsource =>a139
);
ints_writeback: Writeback PORT MAP(
pc =>a132,
datatomenin =>a191,
aluresultin =>a133,
rfsourcein =>a139,
datatoreg =>a23
);
Salidaunion<=a23;
end Behavioral;
| gpl-3.0 | 4bda05dfc6b1b7f38a7682263362f146 | 0.526012 | 3.664988 | false | false | false | false |
alemedeiros/flappy_vhdl | modules/output_pack.vhd | 1 | 4,330 | -- file: modules/output_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
library ieee ;
use ieee.std_logic_1164.all ;
package output is
-- Draw game images from current game state (player position and current
-- obstacles) using vgacon.
component draw_frame
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
-- Input data
player : in integer range 0 to V_RES - 1 ;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
obst_pos : in integer range 0 to H_RES / N_OBST - 1;
obst_id : out integer range 0 to N_OBST - 1 ;
-- VGA output
red : out std_logic_vector(3 downto 0) ;
green : out std_logic_vector(3 downto 0) ;
blue : out std_logic_vector(3 downto 0) ;
hsync : out std_logic ;
vsync : out std_logic ;
-- Control signals
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end component ;
-- Sweeps through each bit of a VGA screen.
component pixel_counter
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
lin : out integer range 0 to V_RES - 1 ;
col : out integer range 0 to H_RES - 1 ;
clock : in std_logic ;
reset : in std_logic ;
enable : in std_logic
) ;
end component ;
-- Generate a frame from the current game state.
component frame_builder
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 ; -- Number of obstacles
P_POS : natural := 20 -- Player Horizontal position
) ;
port (
-- Game state data.
player : in integer range 0 to V_RES - 1 ;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
obst_pos : in integer range 0 to H_RES / N_OBST - 1 ;
obst_id : out integer range 0 to N_OBST - 1 ;
lin : in integer range 0 to V_RES - 1 ;
col : in integer range 0 to H_RES - 1 ;
enable : in std_logic ;
colour : out std_logic_vector(2 downto 0)
) ;
end component ;
-- Leds and 7seg display controller -- converts internal signals to led
-- outputs.
component ledcon
port (
obst_count : in integer range -2 to 255 ;
pause : in std_logic ;
game_over : in std_logic ;
hex0 : out std_logic_vector(0 to 6) ;
hex1 : out std_logic_vector(0 to 6) ;
hex2 : out std_logic_vector(0 to 6) ;
hex3 : out std_logic_vector(0 to 6) ;
ledr : out std_logic_vector(0 to 9) ;
ledg : out std_logic_vector(0 to 7)
) ;
end component ;
component hex2disp
port ( num : in std_logic_vector(3 downto 0) ; -- Input value
led : out std_logic_vector(0 to 6) -- 7seg led display signal
) ;
end component ;
-- VGA controller
component vgacon
generic (
-- When changing this, remember to keep 4:3 aspect ratio
-- Must also keep in mind that our native resolution is 640x480, and
-- you can't cross these bounds (although you will seldom have enough
-- on-chip memory to instantiate this module with higher res).
NUM_HORZ_PIXELS : natural := 128 ; -- Number of horizontal pixels
NUM_VERT_PIXELS : natural := 96 -- Number of vertical pixels
) ;
port (
clk27M : in std_logic ;
rstn : in std_logic ;
write_enable : in std_logic ;
write_clk : in std_logic ;
write_addr : in integer range 0 to
NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1 ;
data_in : in std_logic_vector(2 downto 0) ;
vga_clk : buffer std_logic ; -- Ideally 25.175 MHz
red : out std_logic_vector(3 downto 0) ;
green : out std_logic_vector(3 downto 0) ;
blue : out std_logic_vector(3 downto 0) ;
hsync : out std_logic ;
vsync : out std_logic
) ;
end component ;
end output ;
| bsd-3-clause | c300eede73c9755855db146a580f7778 | 0.583372 | 3.428345 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/SearchModule.vhd | 1 | 8,152 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package SearchModule_pkg is
constant DATA_WIDTH_A_USAR: integer := 32;
constant ADDR_WIDTH_A_USAR: integer := 10;
type arrayOfADDR_WIDTH is array (integer range <>) of std_logic_vector((ADDR_WIDTH_A_USAR-1) downto 0);
type arrayOfDATA_WIDTH is array (integer range <>) of std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0);
type arrayUOfDATA_WIDTH is array (integer range <>) of ieee.numeric_std.unsigned( (DATA_WIDTH_A_USAR-1) downto 0) ;
end package;
use work.SearchModule_pkg.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SearchModule is
generic (
DATA_WIDTH: integer := 32;
ADDR_WIDTH: integer := 10
);
Port (
clk : in std_logic;-- un solo reloj para ambos puertos de la BRAM
--Signals to start a search
search : in std_logic;--El dato actual se debe comparar
dataToCompare : in std_logic_vector((DATA_WIDTH-1) downto 0);
operationID : in std_logic_vector((DATA_WIDTH-1) downto 0);
--Puerto de escritura de datos
porta_wr : in std_logic;
porta_waddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
porta_din : in std_logic_vector( (DATA_WIDTH-1) downto 0);
--Result
searchFinished : out std_logic;--Resultado de una comparación listo
searchresult : out std_logic;--Si se ha encontrado o no. searchresult='1' indica que si se ha encontrado el elemento
resultIndex : out std_logic_vector( (ADDR_WIDTH-1) downto 0);--Solo es valido si searchresult='1'
result_operationID : out std_logic_vector((DATA_WIDTH-1) downto 0);
--debug signals
internalResultFinished_dbg : out std_logic_vector( (ADDR_WIDTH-1) downto 0);
resultIndexs_dbg : out arrayOfADDR_WIDTH((ADDR_WIDTH-1) downto 0);
dataFound_dbg : out arrayUOfDATA_WIDTH((ADDR_WIDTH-1) downto 0)
);
end SearchModule;
architecture Behavioral of SearchModule is
--entradas de los renglones de busqueda
type arrayOfDATA_WIDTH is array ((ADDR_WIDTH-1) downto 0) of std_logic_vector((DATA_WIDTH-1) downto 0);
type arrayOfADDR_WIDTH is array ((ADDR_WIDTH-1) downto 0) of std_logic_vector((ADDR_WIDTH-1) downto 0);
signal dataToCompare_iarray : arrayOfDATA_WIDTH;
signal operationID_iarray : arrayOfDATA_WIDTH;
signal previousIndex_iarray : arrayOfADDR_WIDTH;
signal compare_iarray : std_logic_vector( (ADDR_WIDTH-1) downto 0);
signal previousResult_iarray : std_logic_vector( (ADDR_WIDTH-1) downto 0);
--salidas de los renglones de busqueda
signal result_oarray : std_logic_vector( (ADDR_WIDTH-1) downto 0);
signal nextIndex_oarray : arrayOfADDR_WIDTH;
signal compareFinished_oarray : std_logic_vector( (ADDR_WIDTH-1) downto 0);
constant firstRadio : std_logic_vector( (ADDR_WIDTH-1) downto 0) := ( (ADDR_WIDTH-2) => '1', others => '0' );
constant firstPreviousIndex : std_logic_vector( (ADDR_WIDTH-1) downto 0) := ( (ADDR_WIDTH-1) => '0', others => '1' );
signal operationID_oarray : arrayOfDATA_WIDTH;
signal dataCompared_oarray : arrayOfDATA_WIDTH;
signal searchFinished_temp : std_logic;--Resultado de una comparación listo
signal searchresult_temp : std_logic;--Si se ha encontrado o no. searchresult='1' indica que si se ha encontrado el elemento
signal resultIndex_temp : std_logic_vector( (ADDR_WIDTH-1) downto 0);--Solo es valido si searchresult='1'
signal result_operationID_temp : std_logic_vector((DATA_WIDTH-1) downto 0);
begin
generarFilasDeBusqueda: for i in 0 to (ADDR_WIDTH-1) generate
firstRow: if i=0 generate
row: entity work.BinarySearch_ComparingRow
generic map( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH )
port map(
clk => clk,
radio => firstRadio,
dataToCompare => dataToCompare,
operationID => operationID,
previousIndex => firstPreviousIndex,
compare => search,
previousResult => '0',
porta_wr => porta_wr,
porta_waddr => porta_waddr,
porta_din => porta_din,
result => result_oarray(i),
nextIndex => nextIndex_oarray(i),
compareFinished => compareFinished_oarray(i),
result_operationID => operationID_oarray(i),
dataCompared => dataCompared_oarray(i),
valorLeido_dbg => dataFound_dbg(i)
);
end generate firstRow;
intermediateRows: if ((i/=0) and (i/=(ADDR_WIDTH-1)) ) generate
row: entity work.BinarySearch_ComparingRow
generic map( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH )
port map(
clk => clk,
radio => ( (ADDR_WIDTH-2-i) => '1', others => '0' ),
dataToCompare => dataCompared_oarray(i-1),
operationID => operationID_oarray(i-1),
previousIndex => nextIndex_oarray(i-1),
compare => compareFinished_oarray(i-1),
previousResult => result_oarray(i-1),
porta_wr => porta_wr,
porta_waddr => porta_waddr,
porta_din => porta_din,
result => result_oarray(i),
nextIndex => nextIndex_oarray(i),
compareFinished => compareFinished_oarray(i),
result_operationID => operationID_oarray(i),
dataCompared => dataCompared_oarray(i),
valorLeido_dbg => dataFound_dbg(i)
);
end generate intermediateRows;
finalRow: if i=(ADDR_WIDTH-1) generate
row: entity work.BinarySearch_ComparingRow
generic map( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH )
port map(
clk => clk,
radio => ( others => '0' ),
dataToCompare => dataCompared_oarray(i-1),
operationID => operationID_oarray(i-1),
previousIndex => nextIndex_oarray(i-1),
compare => compareFinished_oarray(i-1),
previousResult => result_oarray(i-1),
porta_wr => porta_wr,
porta_waddr => porta_waddr,
porta_din => porta_din,
result => result_oarray(i),
nextIndex => nextIndex_oarray(i),
compareFinished => compareFinished_oarray(i),
result_operationID => operationID_oarray(i),
dataCompared => dataCompared_oarray(i),
valorLeido_dbg => dataFound_dbg(i)
);
end generate finalRow;
resultIndexs_dbg(i) <= nextIndex_oarray(i);
end generate generarFilasDeBusqueda;
internalResultFinished_dbg <= compareFinished_oarray;
searchFinished_temp <= compareFinished_oarray(ADDR_WIDTH-1);
searchresult_temp <= result_oarray(ADDR_WIDTH-1);
resultIndex_temp <= nextIndex_oarray(ADDR_WIDTH-1);
result_operationID_temp <= operationID_oarray(ADDR_WIDTH-1);
FinalStage: process(clk, searchFinished_temp, searchresult_temp, resultIndex_temp, result_operationID_temp) begin
if rising_edge(clk) then
searchFinished <= searchFinished_temp;
searchresult <= searchresult_temp;
resultIndex <= resultIndex_temp;
result_operationID <= result_operationID_temp;
end if;--clk
end process FinalStage;
end Behavioral;
| bsd-3-clause | 6dfffceb2366b3bd68f5ebab0ddf4c10 | 0.56638 | 4.220611 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/Tbtercerprocesaor.vhd | 1 | 2,982 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:42:42 10/22/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesador3full/Tbtercerprocesaor.vhd
-- Project Name: procesador3full
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: firstrpart
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tbtercerprocesaor IS
END Tbtercerprocesaor;
ARCHITECTURE behavior OF Tbtercerprocesaor IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT firstrpart
PORT(
Resetext : IN std_logic;
Clkinext : IN std_logic;
Adressext : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Resetext : std_logic := '0';
signal Clkinext : std_logic := '0';
--Outputs
signal Adressext : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clkinext_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: firstrpart PORT MAP (
Resetext => Resetext,
Clkinext => Clkinext,
Adressext => Adressext
);
-- Clock process definitions
Clkinext_process :process
begin
Clkinext <= '0';
wait for Clkinext_period/2;
Clkinext <= '1';
wait for Clkinext_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Resetext <= '0';
wait for 100 ns;
Resetext <= '1';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 11a167cb8efb0b753ddeda08b1d8b89d | 0.581824 | 4.04065 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Mux2.vhd | 1 | 1,328 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:44:00 11/09/2017
-- Design Name:
-- Module Name: Mux2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Mux2 is
Port ( Entrada : in STD_LOGIC_VECTOR (31 downto 0);
sumador : in STD_LOGIC_VECTOR (31 downto 0);
Cuentrada : in STD_LOGIC_VECTOR (1 downto 0);
posicion : out STD_LOGIC_VECTOR (31 downto 0));
end Mux2;
architecture Behavioral of Mux2 is
begin
process(Entrada,sumador,Cuentrada)
begin
if (Cuentrada="10") then
posicion<=sumador;
elsif (Cuentrada="00" or Cuentrada="01" or Cuentrada="11") then
posicion<=Entrada;
end if;
end process;
end Behavioral;
| gpl-3.0 | c8ad2531ffca265474cef72df4b33582 | 0.593373 | 3.894428 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd | 3 | 4,760 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| bsd-3-clause | 102a6da2dd8b50c3279e5ffc7cc9b5bb | 0.610924 | 4.117647 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/tbmux2.vhd | 1 | 2,585 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:26:50 11/09/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/segmentado1intento/tbmux2.vhd
-- Project Name: segmentado1intento
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Mux2
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbmux2 IS
END tbmux2;
ARCHITECTURE behavior OF tbmux2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Mux2
PORT(
Entrada : IN std_logic_vector(31 downto 0);
sumador : IN std_logic_vector(31 downto 0);
Cuentrada : IN std_logic;
posicion : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Entrada : std_logic_vector(31 downto 0) := (others => '0');
signal sumador : std_logic_vector(31 downto 0) := (others => '0');
signal Cuentrada : std_logic := '0';
--Outputs
signal posicion : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Mux2 PORT MAP (
Entrada => Entrada,
sumador => sumador,
Cuentrada => Cuentrada,
posicion => posicion
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
Entrada <= "00000000000000000000000000000001";
sumador <= "00000000000000000000000000000000";
Cuentrada <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
Entrada <= "00000000000000000000000000000001";
sumador <= "00000000000000000000000000000000";
Cuentrada <= '1';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | ff6fac0b278ae2434f1bbbca4001e922 | 0.615474 | 4.286899 | false | true | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd | 9 | 86,039 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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pTutWGYqNILLuDglfF0qg8mdpI5q2Is29MORHgT2/M7EBDZqhjJ5beRlisktS4nWyVRSBEnu9kGh
vn4q0E8fRnJSpapitu5UNx9QDPhII7sdvgIVWAsQTJAmTrOen9XxMRWzstwzn4jtT/K5IoFSmxxY
YxuHXYiLcLT+wDpAez/OEKXb+DjRdcUb7TbFdojkL0k2lA2rtPeDtp8QvAt/doNni9oDup/K4PX5
5ByjWtbI3C4smMKZ+WEhBDZPWb8R4h7Ma7nA+ZIf/OO8/dc/ga83NAkarCM8hIkTSuc=
`protect end_protected
| mit | 9e60f6e26436a47e61a1f0a43f3e44a7 | 0.952615 | 1.835616 | false | false | false | false |
makestuff/s3b_sdram | try1/memctrl/memctrl_tb.vhdl | 1 | 2,994 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.memctrl_pkg.all;
use work.hexutil.all;
entity memctrl_tb is
end memctrl_tb;
architecture behavioural of memctrl_tb is
-- Memory controller signals
signal mcClk : std_logic;
signal mcRDV : std_logic;
-- SDRAM signals
signal ramCmd : std_logic_vector(2 downto 0);
signal ramClk : std_logic;
signal ramRAS : std_logic;
signal ramCAS : std_logic;
signal ramWE : std_logic;
signal ramAddr : std_logic_vector(11 downto 0);
signal ramData_io : std_logic_vector(15 downto 0);
signal ramBank_out : std_logic_vector(1 downto 0);
signal ramLDQM : std_logic;
signal ramUDQM : std_logic;
begin
-- Instantiate the memory controller for testing
uut: memctrl
generic map(
INIT_COUNT => "0" & x"004" -- Much longer in real hardware!
)
port map(
mcClk_in => mcClk,
mcRDV_out => mcRDV,
ramRAS_out => ramRAS,
ramCAS_out => ramCAS,
ramWE_out => ramWE,
ramAddr_out => ramAddr,
ramData_io => ramData_io,
ramBank_out => ramBank_out,
ramLDQM_out => ramLDQM,
ramUDQM_out => ramUDQM
);
ramCmd <= ramRAS & ramCAS & ramWE;
-- Drive the unit under test. Read stimulus from stimulus.txt and write results to results.txt
--
process
begin
mcClk <= '0';
ramData_io <= (others => 'Z');
ramClk <= '1';
wait for 10 ns;
ramClk <= '0';
wait for 4 ns;
loop
mcClk <= '0';
wait for 6 ns;
ramClk <= '1';
wait for 4 ns;
mcClk <= '1';
-- Assert signals from line in stimulus file here
wait for 6 ns;
-- Sample outputs here
ramClk <= '0';
wait for 4 ns;
-- Write to results file here
end loop;
wait;
end process;
-- Simulate the SDRAM returning data two clocks after a read command
process
begin
loop
ramData_io <= (others => 'Z');
wait until ramRAS = '1' and ramCAS = '0' and ramWE = '1' and mcClk = '1';
wait until mcClk = '0';
wait until mcClk = '1';
wait until mcClk = '0';
wait until mcClk = '1';
wait for 6 ns;
ramData_io <= x"CAFE";
wait until mcClk = '0';
wait until mcClk = '1';
wait for 3 ns;
end loop;
end process;
end architecture;
| gpl-3.0 | 316b269525a98a17ab53fe225ee55ada | 0.647629 | 3.326667 | false | false | false | false |
loetlab-jena/das-atv | hdl/syn/ip/pll2.vhd | 1 | 15,117 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll2.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll2 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll2;
ARCHITECTURE SYN OF pll2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 50,
clk0_duty_cycle => 50,
clk0_multiply_by => 27,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll2",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "108"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "27.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | e60df2a71e5fd43b194b219e69b7963a | 0.69875 | 3.348914 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/synth/tri_intersect_ap_fsub_7_full_dsp_32.vhd | 3 | 12,691 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fsub_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fsub_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fsub_7_full_dsp_32_arch OF tri_intersect_ap_fsub_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fsub_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fsub_7_full_dsp_32_arch;
| mit | cda22a641eb74dd35ebb5e2099d7b695 | 0.652194 | 3.023827 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Barra1.vhd | 1 | 1,474 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:35:29 12/02/2017
-- Design Name:
-- Module Name: Barra1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Barra1 is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
instrutin : in STD_LOGIC_VECTOR (31 downto 0);
PCin : in STD_LOGIC_VECTOR (31 downto 0);
instrutout : out STD_LOGIC_VECTOR (31 downto 0);
PCout : out STD_LOGIC_VECTOR (31 downto 0));
end Barra1;
architecture Behavioral of Barra1 is
begin
process(Clk,Reset,instrutin,PCin )
begin
if reset='1' then
instrutout <= "00000000000000000000000000000000";
PCout <= "00000000000000000000000000000000";
elsif(rising_edge(Clk)) then
instrutout <= instrutin;
PCout <= PCin;
end if;
end process;
end Behavioral;
| gpl-3.0 | d8696a1c334390b91e5cef1104fbe4df | 0.589552 | 4.027322 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/tbdecode.vhd | 1 | 4,605 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:38 11/11/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/decode/tbdecode.vhd
-- Project Name: decode
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Decode
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbdecode IS
END tbdecode;
ARCHITECTURE behavior OF tbdecode IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Decode
PORT(
Instruction : IN std_logic_vector(31 downto 0);
posicionin : IN std_logic_vector(31 downto 0);
Regtomemin : IN std_logic_vector(31 downto 0);
cwpin : IN std_logic;
iccin : IN std_logic_vector(3 downto 0);
Resetext : IN std_logic;
ncwpout : OUT std_logic;
callout : OUT std_logic_vector(31 downto 0);
ifout : OUT std_logic_vector(31 downto 0);
rfdestout : OUT std_logic;
rfsourceout : OUT std_logic_vector(1 downto 0);
wrenmen : OUT std_logic;
pcsource : OUT std_logic_vector(1 downto 0);
aluop : OUT std_logic_vector(5 downto 0);
a18 : OUT std_logic_vector(31 downto 0);
crs1out : OUT std_logic_vector(31 downto 0);
op2out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
signal posicionin : std_logic_vector(31 downto 0) := (others => '0');
signal Regtomemin : std_logic_vector(31 downto 0) := (others => '0');
signal cwpin : std_logic := '0';
signal iccin : std_logic_vector(3 downto 0) := (others => '0');
signal Resetext : std_logic := '0';
--Outputs
signal ncwpout : std_logic;
signal callout : std_logic_vector(31 downto 0);
signal ifout : std_logic_vector(31 downto 0);
signal rfdestout : std_logic;
signal rfsourceout : std_logic_vector(1 downto 0);
signal wrenmen : std_logic;
signal pcsource : std_logic_vector(1 downto 0);
signal aluop : std_logic_vector(5 downto 0);
signal a18 : std_logic_vector(31 downto 0);
signal crs1out : std_logic_vector(31 downto 0);
signal op2out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Decode PORT MAP (
Instruction => Instruction,
posicionin => posicionin,
Regtomemin => Regtomemin,
cwpin => cwpin,
iccin => iccin,
Resetext => Resetext,
ncwpout => ncwpout,
callout => callout,
ifout => ifout,
rfdestout => rfdestout,
rfsourceout => rfsourceout,
wrenmen => wrenmen,
pcsource => pcsource,
aluop => aluop,
a18 => a18,
crs1out => crs1out,
op2out => op2out
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Instruction <= "10100100000100000010000000000101";
posicionin <= "00000000000000000000000000000001";
Regtomemin <= "00000000000000000000000000111111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '1';
wait for 100 ns;
Instruction <= "10100100000100000010000000000101";
posicionin <= "00000000000000000000000000000001";
Regtomemin <= "00000000000000000000000000111111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '0';
wait for 100 ns;
Instruction <= "10100100000100000010000000001111";
posicionin <= "00000000000000000000000000000010";
Regtomemin <= "00000000000000000000000000001111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '0';
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 9a740742b1c3e7842aba6cb77c4c8819 | 0.611726 | 4.046573 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth.vhd | 3 | 10,215 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 5,
C_DOUT_WIDTH => 5,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 5,
C_DIN_WIDTH => 5,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 5,
C_DIN_WIDTH => 5,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_inst : system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-3-clause | 76e9b5a5d31b88131a8e22a3b6cffbb4 | 0.474107 | 4.087635 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/RF.vhd | 1 | 1,707 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
wre : in STD_LOGIC;
cRd : out STD_LOGIC_VECTOR (31 downto 0);
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (39 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type;
begin
RAM(0)<= "00000000000000000000000000000000";--serciora g0
process (rst,rd,rs1,rs2,dwr,RAM,wre)
begin
if rst = '1' then
RAM <= (others=>"00000000000000000000000000000000");
crs1 <="00000000000000000000000000000000";
crs2 <="00000000000000000000000000000000";
cRd <= "00000000000000000000000000000000";
RAM(15)<= "00000000000000000000000000010110";--por el jmpl para que lea el main
elsif rd /= "000000" and wre='1' and rd /= "001111" then
RAM(conv_integer(rd)) <= dwr;
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
cRd <= RAM(conv_integer(rd));
else
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
cRd <= RAM(conv_integer(rd));
end if;
end process;
end Behavioral;
| gpl-3.0 | b15b5fd3eeb80b0b3981a89d3e4b4ccf | 0.543644 | 4.016471 | false | false | false | false |
alemedeiros/flappy_vhdl | input/clock_divider.vhd | 1 | 927 | -- file: input/clock_divider.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Divides 27MHz clock into adequate clock value
library ieee ;
use ieee.std_logic_1164.all ;
entity clock_divider is
generic (
RATE : natural := 270000
) ;
port (
clk_in : in std_logic ;
clk_out : out std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end clock_divider ;
architecture behavior of clock_divider is
signal count: integer range 0 to RATE - 1;
begin
-- Counter for rate
process(clk_in, reset)
begin
if reset = '1' then
count <= 0 ;
elsif rising_edge(clk_in) and enable = '1' then
if count = RATE - 1 then
count <= 0 ;
else
count <= count + 1 ;
end if ;
end if ;
end process ;
-- Sets clk_out
clk_out <= '1' when count = (RATE - 1) else '0' ;
end behavior ;
| bsd-3-clause | b31283e0bbc196ba6cb439836b520cad | 0.636462 | 3.131757 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/pcores/axi_dispctrl_v1_00_a/hdl/vhdl/axi_dispctrl.vhd | 3 | 15,200 | ----------------------------------------------------------------------------------
-- axi_dispctrl.vhd - entity/architecture pair
----------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
----------------------------------------------------------------------------------
--
-- *******************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- *******************************************************************************
--
----------------------------------------------------------------------------------
-- Filename: axi_dispctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Sat Sep 28 10:06:38 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
----------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_dispctrl_v1_00_a;
use axi_dispctrl_v1_00_a.user_logic;
----------------------------------------------------------------------------------
-- Entity section
----------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity axi_dispctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_MM2S_TDATA_WIDTH : integer := 32;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : OUT std_logic_vector(7 downto 0);
GREEN_O : OUT std_logic_vector(7 downto 0);
BLUE_O : OUT std_logic_vector(7 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dispctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_dispctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 13;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_dispctrl_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 => C_USE_BUFR_DIV5,
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_MM2S_TDATA_WIDTH,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
REF_CLK_I => REF_CLK_I,
PXL_CLK_O => PXL_CLK_O,
VDMA_CLK_O => VDMA_CLK_O,
PXL_CLK_5X_O => PXL_CLK_5X_O,
LOCKED_O => LOCKED_O,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
DEBUG_O => DEBUG_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
ENABLE_O => ENABLE_O,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| bsd-3-clause | 8ec321730c91d8a4399b195471dd450e | 0.570263 | 2.975724 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd | 1 | 92,801 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM FULL Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all ;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset ;
use axi_datamover_v5_1.axi_datamover_cmd_status ;
use axi_datamover_v5_1.axi_datamover_pcc ;
use axi_datamover_v5_1.axi_datamover_ibttcc ;
use axi_datamover_v5_1.axi_datamover_indet_btt ;
use axi_datamover_v5_1.axi_datamover_s2mm_realign ;
use axi_datamover_v5_1.axi_datamover_addr_cntl ;
use axi_datamover_v5_1.axi_datamover_wrdata_cntl ;
use axi_datamover_v5_1.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1.axi_datamover_skid2mm_buf ;
Use axi_datamover_v5_1.axi_datamover_skid_buf ;
Use axi_datamover_v5_1.axi_datamover_wr_sf ;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_full_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 1;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) General Purpose Store and Forward function
-- 0 = Omit GP Store and Forward
-- 1 = Include GP Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and Reset inputs ----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
-------------------------------------------------------------------
-- S2MM Primary Reset input ---------------------------------------
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- S2MM Halt request input control --------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------------
-- S2MM Error discrete output -------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------------
-- Optional Command and Status Clock and Reset -------------------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls ---------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_full_wrap;
architecture implementation of axi_datamover_s2mm_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
if (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_status_width
--
-- Function Description:
-- This function sets the width of the Status pipe depending on the
-- Store and Forward inclusion or ommision.
--
-------------------------------------------------------------------
function funct_set_status_width (store_forward_enabled : integer)
return integer is
Variable temp_status_bit_width : Integer := 8;
begin
If (store_forward_enabled = 1) Then
temp_status_bit_width := 32;
Else
temp_status_bit_width := 8;
End if;
Return (temp_status_bit_width);
end function funct_set_status_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_bits_needed
--
-- Function Description:
--
--
-------------------------------------------------------------------
function get_bits_needed (max_bytes : integer) return integer is
Variable fvar_temp_bit_width : Integer := 1;
begin
if (max_bytes <= 1) then
fvar_temp_bit_width := 1;
elsif (max_bytes <= 3) then
fvar_temp_bit_width := 2;
elsif (max_bytes <= 7) then
fvar_temp_bit_width := 3;
elsif (max_bytes <= 15) then
fvar_temp_bit_width := 4;
elsif (max_bytes <= 31) then
fvar_temp_bit_width := 5;
elsif (max_bytes <= 63) then
fvar_temp_bit_width := 6;
elsif (max_bytes <= 127) then
fvar_temp_bit_width := 7;
elsif (max_bytes <= 255) then
fvar_temp_bit_width := 8;
elsif (max_bytes <= 511) then
fvar_temp_bit_width := 9;
elsif (max_bytes <= 1023) then
fvar_temp_bit_width := 10;
elsif (max_bytes <= 2047) then
fvar_temp_bit_width := 11;
elsif (max_bytes <= 4095) then
fvar_temp_bit_width := 12;
elsif (max_bytes <= 8191) then
fvar_temp_bit_width := 13;
else -- 8k - 16K
fvar_temp_bit_width := 14;
end if;
Return (fvar_temp_bit_width);
end function get_bits_needed;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_need_realigner
--
-- Function Description:
-- Determines if the Realigner module needs to be included.
--
-------------------------------------------------------------------
function funct_need_realigner (indet_btt_enabled : integer;
dre_included : integer;
gp_sf_included : integer) return integer is
Variable temp_val : Integer := 0;
begin
If ((indet_btt_enabled = 1) or
(dre_included = 1) or
(gp_sf_included = 1)) Then
temp_val := 1;
else
temp_val := 0;
End if;
Return (temp_val);
end function funct_need_realigner;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others =>
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for S2MM
-- modules downstream from the upsizing Store and Forward. If
-- Store and forward is present, then the effective Stream width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Stream width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled > 0) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_bytes_per_dbeat
--
-- Function Description:
-- This function calculates the number of bytes transfered per
-- databeat on the MMap AXI4 Write Data Channel by the S2MM. The
-- value is based on input parameterization of included functions
-- in the S2MM block.
--
-------------------------------------------------------------------
function funct_get_bytes_per_dbeat (ibtt_enabled : integer ;
gpsf_enabled : integer ;
stream_dwidth : integer ;
mmap_dwidth : integer ) return integer is
Variable fvar_temp_bytes_per_xfer : Integer := 4;
begin
If (ibtt_enabled > 0 or
gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width
fvar_temp_bytes_per_xfer := mmap_dwidth/8;
Else -- transfers will be in stream data widths (may be narrow transfers on mmap)
fvar_temp_bytes_per_xfer := stream_dwidth/8;
End if;
Return (fvar_temp_bytes_per_xfer);
end function funct_get_bytes_per_dbeat;
-- Constant Declarations ----------------------------------------
Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH,
C_S2MM_SDATA_WIDTH,
SF_ENABLED);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant IS_NOT_MM2S : integer range 0 to 1 := 0;
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH;
Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32);
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED;
Constant BITS_PER_BYTE : integer := 8;
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1;
Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT;
Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ;
Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF ,
ENABLE_GP_SF ,
S2MM_SDATA_WIDTH ,
S2MM_MDATA_WIDTH);
Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE;
Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST);
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going
-- full thresholding
-- in WSC
Constant WSC_STATUS_WIDTH : integer range 8 to 32 :=
funct_set_status_width(ENABLE_INDET_BTT_SF);
Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED;
Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF ,
INCLUDE_S2MM_DRE ,
ENABLE_GP_SF);
-- Calculates the minimum needed depth of the GP Store and Forward FIFO
-- based on the S2MM pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE;
-- Assigns the depth of the optional GP Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH,
S2MM_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0');
signal sig_dre2ibtt_tvalid : std_logic := '0';
signal sig_ibtt2dre_tready : std_logic := '0';
signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tlast : std_logic := '0';
signal sig_dre2ibtt_eop : std_logic := '0';
signal sig_dre2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2dre_cmd_valid : std_logic := '0';
signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2dre_drr : std_logic := '0';
signal sig_mstr2dre_eof : std_logic := '0';
signal sig_mstr2dre_cmd_cmplt : std_logic := '0';
signal sig_mstr2dre_calc_error : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal sig_dre2all_halted : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal skid2dre_wvalid : std_logic := '0';
signal dre2skid_wready : std_logic := '0';
signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2dre_wlast : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_ibtt2wdc_error : std_logic := '0';
signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal s2mm_awuser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug/Test Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADD_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen adds in the EOP status marker to the debug
-- vector data when Indet BTT Store and Forward is enabled.
--
------------------------------------------------------------
GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate
begin
sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker
end generate GEN_ADD_DEBUG_EOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen zeros the debug vector bit used for the EOP
-- status marker when Indet BTT Store and Forward is not
-- enabled.
--
------------------------------------------------------------
GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate
begin
sig_dbg_data_1(19) <= '0' ; -- EOP Marker
end generate GEN_NO_DEBUG_EOP;
---- End of Debug/Test Support --------------------------------
-- Assign the Address posting control outputs
s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ;
s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ;
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ;
s2mm_wr_len <= sig_s2mm_wr_len ;
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
s2mm_wstrb <= sig_skid2axi_wstrb ;
end generate GEN_S2MM_TKEEP_ENABLE2;
GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
s2mm_wstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE2;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters
s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_WR_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_PCC
--
-- If Generate Description:
-- Include the normal Predictive Command Calculator function,
-- Store and Forward is not an included feature.
--
--
------------------------------------------------------------
GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_NOT_MM2S ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => open ,
mstr2data_dre_dest_align => open ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_PCC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_IBTTCC
--
-- If Generate Description:
-- Include the Indeterminate BTT Command Calculator function,
-- Store and Forward is enabled in the S2MM.
--
--
------------------------------------------------------------
GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_MSTR_SFCC
--
-- Description:
-- Instantiates the Store and Forward Command Calculator
-- Block.
--
------------------------------------------------------------
I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1.axi_datamover_ibttcc
generic map (
C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_IBTTCC;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2dre_wvalid ,
m_ready => dre2skid_wready ,
m_data => skid2dre_wdata ,
m_strb => skid2dre_wstrb ,
m_last => skid2dre_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2dre_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= dre2skid_wready;
skid2dre_wdata <= s2mm_strm_wdata;
skid2dre_wstrb <= s2mm_strm_wstrb;
skid2dre_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_REALIGNER
--
-- If Generate Description:
-- Omit the S2MM Realignment Engine
--
--
------------------------------------------------------------
GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate
begin
-- Set to Always ready for DRE to PCC Command Interface
sig_dre2mstr_cmd_ready <= LOGIC_HIGH;
-- Without DRE and Scatter, the end of packet is the TLAST
--sig_dre2ibtt_eop <= skid2dre_wlast ;
sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version
-- Cant't detect undrrun/overrun here
sig_realign2wdc_eop_error <= '0';
ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_NO_REALIGN_SKID_BUF
--
-- Description:
-- Instance for a Skid Buffer which provides for
-- Fmax timing improvement between the Null Absorber and
-- the Write Data controller when the Realigner is not
-- present (no DRE and no Store and Forward case).
--
------------------------------------------------------------
I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Null Absorber Input)
s_valid => skid2dre_wvalid ,
s_ready => dre2skid_wready ,
s_data => skid2dre_wdata ,
s_strb => skid2dre_wstrb ,
s_last => skid2dre_wlast ,
-- Master Side (Stream Data Output to WData Cntlr)
m_valid => sig_dre2ibtt_tvalid ,
m_ready => sig_ibtt2dre_tready ,
m_data => sig_dre2ibtt_tdata ,
m_strb => sig_dre2ibtt_tstrb ,
m_last => sig_dre2ibtt_tlast
);
end generate ENABLE_NOREALIGNER_SKID;
DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate
begin
sig_dre2ibtt_tvalid <= skid2dre_wvalid;
dre2skid_wready <= sig_ibtt2dre_tready;
sig_dre2ibtt_tdata <= skid2dre_wdata;
sig_dre2ibtt_tstrb <= skid2dre_wstrb;
sig_dre2ibtt_tlast <= skid2dre_wlast;
end generate DISABLE_NOREALIGNER_SKID;
end generate GEN_NO_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_REALIGNER
--
-- If Generate Description:
-- Include the S2MM realigner Module. It hosts the S2MM DRE
-- and the Scatter Block.
--
-- Note that the General Purpose Store and Forward Module
-- needs the Scatter function to detect input overrun and
-- underrun events on the AXI Stream input. Thus the Realigner
-- is included whenever the GP Store and Forward is enabled.
--
------------------------------------------------------------
GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_REALIGNER
--
-- Description:
-- Instance for the S2MM Data Realignment Module.
--
------------------------------------------------------------
I_S2MM_REALIGNER : entity axi_datamover_v5_1.axi_datamover_s2mm_realign
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_INCLUDE_DRE => INCLUDE_S2MM_DRE ,
C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER ,
C_BTT_USED => S2MM_BTT_USED ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
-- Write Data Controller or Store and Forward I/O -------
wdc2dre_wready => sig_ibtt2dre_tready ,
dre2wdc_wvalid => sig_dre2ibtt_tvalid ,
dre2wdc_wdata => sig_dre2ibtt_tdata ,
dre2wdc_wstrb => sig_dre2ibtt_tstrb ,
dre2wdc_wlast => sig_dre2ibtt_tlast ,
dre2wdc_eop => sig_dre2ibtt_eop ,
-- Starting offset output -------------------------------
dre2sf_strt_offset => sig_sf_strt_addr_offset ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_wready => dre2skid_wready ,
s2mm_strm_wvalid => skid2dre_wvalid ,
s2mm_strm_wdata => skid2dre_wdata ,
s2mm_strm_wstrb => skid2dre_wstrb ,
s2mm_strm_wlast => skid2dre_wlast ,
-- Command Calculator Interface --------------------------
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ,
-- Premature TLAST assertion error flag
dre2all_tlast_error => sig_realign2wdc_eop_error ,
-- DRE Halted Status
dre2all_halted => sig_dre2all_halted
);
end generate GEN_INCLUDE_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT_SF
--
-- If Generate Description:
-- Include the Indeterminate BTT Logic with specialized
-- Store and Forward function, This also requires the
-- Scatter Engine in the Realigner module.
--
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate
begin
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
------------------------------------------------------------
-- Instance: I_INDET_BTT
--
-- Description:
-- Instance for the Indeterminate BTT with Store and Forward
-- module.
--
------------------------------------------------------------
I_INDET_BTT : entity axi_datamover_v5_1.axi_datamover_indet_btt
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_DRE => INCLUDE_S2MM_DRE ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
ibtt2wdc_eop => sig_ibtt2wdc_eop ,
ibtt2wdc_tdata => sig_ibtt2wdc_tdata ,
ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb ,
ibtt2wdc_tlast => sig_ibtt2wdc_tlast ,
ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid ,
wdc2ibtt_tready => sig_wdc2ibtt_tready ,
dre2ibtt_tvalid => sig_dre2ibtt_tvalid ,
ibtt2dre_tready => sig_ibtt2dre_tready ,
dre2ibtt_tdata => sig_dre2ibtt_tdata ,
dre2ibtt_tstrb => sig_dre2ibtt_tstrb ,
dre2ibtt_tlast => sig_dre2ibtt_tlast ,
dre2ibtt_eop => sig_dre2ibtt_eop ,
dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes
);
end generate GEN_ENABLE_INDET_BTT_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_SF
--
-- If Generate Description:
-- Bypasses any store and Forward functions.
--
--
------------------------------------------------------------
GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 0) generate
begin
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
-- Housekeep unused signal in this case
sig_ok_to_post_wr_addr <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
-- Just pass DRE signals through
sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ;
sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ;
sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ;
sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ;
sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ;
sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ;
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
end generate GEN_NO_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_GP_SF
--
-- If Generate Description:
-- Include the General Purpose Store and Forward module.
-- This If Generate can only be enabled when
-- Indeterminate BTT mode is not enabled. The General Purpose
-- Store and Forward is instantiated in place of the Indet
-- BTT Store and Forward.
--
------------------------------------------------------------
GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 1) generate
begin
-- Merge the external address posting control with the
-- SF address posting control.
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and
sig_ok_to_post_wr_addr ;
-- Zero these out since Indet BTT is not enabled, they
-- are only used by the WDC in that mode
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
sig_ibtt2wdc_eop <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
------------------------------------------------------------
-- Instance: I_S2MM_GP_SF
--
-- Description:
-- Instance for the S2MM (Write) General Purpose Store and
-- Forward Module. This module can only be enabled when
-- Indeterminate BTT mode is not enabled. It is connected
-- in place of the IBTT Module when GP SF is enabled.
--
------------------------------------------------------------
I_S2MM_GP_SF : entity axi_datamover_v5_1.axi_datamover_wr_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -----------------------------
aclk => s2mm_aclk ,
reset => sig_mmap_rst ,
-- Slave Stream Input --------------------------------
sf2sin_tready => sig_ibtt2dre_tready ,
sin2sf_tvalid => sig_dre2ibtt_tvalid ,
sin2sf_tdata => sig_dre2ibtt_tdata ,
sin2sf_tkeep => sig_dre2ibtt_tstrb ,
sin2sf_tlast => sig_dre2ibtt_tlast ,
sin2sf_error => sig_realign2wdc_eop_error ,
-- Starting Address Offset Input ---------------------
sin2sf_strt_addr_offset => sig_sf_strt_addr_offset ,
-- DataMover Write Side Address Pipelining Control Interface --------
ok_to_post_wr_addr => sig_ok_to_post_wr_addr ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM -------------
sout2sf_tready => sig_wdc2ibtt_tready ,
sf2sout_tvalid => sig_ibtt2wdc_tvalid ,
sf2sout_tdata => sig_ibtt2wdc_tdata ,
sf2sout_tkeep => sig_ibtt2wdc_tstrb ,
sf2sout_tlast => sig_ibtt2wdc_tlast ,
sf2sout_error => sig_ibtt2wdc_error
);
end generate GEN_INCLUDE_GP_SF;
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => s2mm_awcache_int ,
addr2axi_auser => s2mm_awuser_int ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
-- mstr2addr_cache_info => sig_cache2mstr_command ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_s2mm_allow_addr_req ,
addr_req_posted => sig_s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_wrdata_cntl
generic map (
C_REALIGNER_INCLUDED => ADD_REALIGNER ,
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => sig_ibtt2wdc_tvalid ,
s2mm_strm_wready => sig_wdc2ibtt_tready ,
s2mm_strm_wdata => sig_ibtt2wdc_tdata ,
s2mm_strm_wstrb => sig_ibtt2wdc_tstrb ,
s2mm_strm_wlast => sig_ibtt2wdc_tlast ,
s2mm_strm_eop => sig_ibtt2wdc_eop ,
s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
realign2wdc_eop_error => sig_ibtt2wdc_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
--ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
--begin
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
--end generate ENABLE_AXIMMAP_SKID;
end implementation;
| mit | db6d64c30b4502ec261881f6cf80eaa7 | 0.451665 | 4.160547 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen.vhd | 3 | 4,760 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| bsd-3-clause | d25405ed8f1c09e5af705f38078d43f5 | 0.610924 | 4.117647 | false | false | false | false |
quicky2000/top_wireworld | wireworld_cell.vhd | 1 | 2,773 | --
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.my_package.all;
entity wireworld_cell is
generic (
init_state : state_type := t_copper
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
neighbours : in STD_LOGIC_VECTOR (7 downto 0);
electron_head : out STD_LOGIC;
electron_queue : out STD_LOGIC);
end wireworld_cell;
architecture Behavioral of wireworld_cell is
signal state : state_type := init_state;
signal next_state : state_type;
begin
--state process
process(clk,reset)
begin
if reset = '1' then
state <= init_state;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
--state transition
process(state,neighbours)
variable a : integer := 0;
begin
case state is
when t_copper => next_state <= t_electron_head ;
a:=0;
for index in 0 to 7 loop
if neighbours(index) = '1' then
a := a + 1;
else
a := a;
end if;
end loop;
if a = 1 or a = 2 then
next_state <= t_electron_head ;
else
next_state <= t_copper;
end if;
when t_electron_head => next_state <= t_electron_queue;
when t_electron_queue => next_state <= t_copper;
end case;
end process;
--output function
electron_head <= '1' when state = t_electron_head else '0';
electron_queue <= '1' when state = t_electron_queue else '0';
end Behavioral;
| gpl-3.0 | 706cde4d521299045cf3e9d8e2827de8 | 0.59863 | 4.120357 | false | false | false | false |
Kalugy/Procesadorarquitectura | Primerprocesador17octubre/Tbfirstpart.vhd | 1 | 2,743 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:58:40 10/03/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/Tbfirstpart.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: firstrpart
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tbfirstpart IS
END Tbfirstpart;
ARCHITECTURE behavior OF Tbfirstpart IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT firstrpart
PORT(
Resetext : IN std_logic;
Clkinext : IN std_logic;
Adressext : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Resetext : std_logic := '0';
signal Clkinext : std_logic := '0';
--Outputs
signal Adressext : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clkinext_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: firstrpart PORT MAP (
Resetext => Resetext,
Clkinext => Clkinext,
Adressext => Adressext
);
-- Clock process definitions
Clkinext_process :process
begin
Clkinext <= '0';
wait for Clkinext_period/2;
Clkinext <= '1';
wait for Clkinext_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Resetext <= '0';
wait for 100 ns;
Resetext <= '1';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | dd11b9bf7cb99bd296c297325eae0d1f | 0.589136 | 4.156061 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fmul_3_max_dsp_32/synth/tri_intersect_ap_fmul_3_max_dsp_32.vhd | 1 | 12,674 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fmul_3_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fmul_3_max_dsp_32;
ARCHITECTURE tri_intersect_ap_fmul_3_max_dsp_32_arch OF tri_intersect_ap_fmul_3_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fmul_3_max_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fmul_3_max_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fmul_3_max_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fmul_3_max_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fmul_3_max_dsp_32_arch;
| mit | 727f9df56f10a75f7458c40cf00679c3 | 0.651728 | 3.021216 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_rst_processing_system7_0_100M_0/synth/triangle_intersect_rst_processing_system7_0_100M_0.vhd | 1 | 6,938 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY triangle_intersect_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END triangle_intersect_rst_processing_system7_0_100M_0;
ARCHITECTURE triangle_intersect_rst_processing_system7_0_100M_0_arch OF triangle_intersect_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF triangle_intersect_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "triangle_intersect_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "triangle_intersect_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END triangle_intersect_rst_processing_system7_0_100M_0_arch;
| mit | 57e6e8a6a5cdcca87fb7982666e9fabd | 0.721822 | 3.491696 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth.vhd | 3 | 11,564 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(34-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 34,
C_DOUT_WIDTH => 34,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 34,
C_DIN_WIDTH => 34,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 34,
C_DIN_WIDTH => 34,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_1_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-3-clause | 68233193aaf12670c5d9816215e3adec | 0.468264 | 3.892292 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/TbWindownmanager.vhd | 2 | 3,607 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:05:36 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Segundoprocesador/TbWindownmanager.vhd
-- Project Name: Segundoprocesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: WindowsManager
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TbWindownmanager IS
END TbWindownmanager;
ARCHITECTURE behavior OF TbWindownmanager IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT WindowsManager
PORT(
cwp : IN std_logic;
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
cwpout : OUT std_logic;
rs1out : OUT std_logic_vector(5 downto 0);
rs2out : OUT std_logic_vector(5 downto 0);
rdout : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal cwp : std_logic := '0';
signal rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal rd : std_logic_vector(4 downto 0) := (others => '0');
signal op : std_logic_vector(1 downto 0) := (others => '0');
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal cwpout : std_logic;
signal rs1out : std_logic_vector(5 downto 0);
signal rs2out : std_logic_vector(5 downto 0);
signal rdout : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: WindowsManager PORT MAP (
cwp => cwp,
rs1 => rs1,
rs2 => rs2,
rd => rd,
op => op,
op3 => op3,
cwpout => cwpout,
rs1out => rs1out,
rs2out => rs2out,
rdout => rdout
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 50 ns;
cwp <= '0';
rs1 <= "00000";
rs2 <= "00000";
rd <= "00000";
op <= "00";
op3 <= "000000";
wait for 50 ns;
cwp <= '0';
rs1 <= "10000";
rs2 <= "10001";
rd <= "10010";
op <= "10";
op3 <= "000000";
wait for 50 ns;
cwp <= '1';
rs1 <= "10000";
rs2 <= "10001";
rd <= "10010";
op <= "10";
op3 <= "111100";
wait for 50 ns;
cwp <= '1';
rs1 <= "01100";
rs2 <= "01101";
rd <= "00000";
op <= "00";
op3 <= "000000";
wait for 50 ns;
cwp <= '1';
rs1 <= "11000";
rs2 <= "11001";
rd <= "10010";
op <= "10";
op3 <= "000000";
wait for 50 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 108a03c12a31b37b7aca9fecc977c775 | 0.561131 | 3.425451 | false | false | false | false |
loetlab-jena/das-atv | hdl/src/frequency_counter.vhd | 1 | 1,475 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity frequency_counter is
generic
(
res : positive;
gate : positive
);
port
(
clk : in std_logic;
cnt_in : in std_logic;
cnt_out : out std_logic_vector(res-1 downto 0)
);
end entity;
architecture rtl of frequency_counter is
signal clk1_en : std_logic := '0';
signal clk1_en_s: std_logic := '0';
signal rst : std_logic := '0';
signal latch : std_logic := '0';
signal cnt1 : unsigned(res-1 downto 0);
signal cnt2 : unsigned(res-1 downto 0);
begin
sync : process
begin
wait until rising_edge(cnt_in);
clk1_en_s <= clk1_en;
end process;
output : process
begin
wait until rising_edge(clk);
if latch = '1' then
cnt_out <= std_logic_vector(cnt1);
end if;
end process;
counter1 : process(rst, cnt_in)
begin
if rst = '1' then
cnt1 <= (others => '0');
elsif rising_edge(cnt_in) then
if clk1_en_s = '1' then
cnt1 <= cnt1 + 1;
end if;
end if;
end process;
counter2 : process
begin
wait until rising_edge(clk);
if rst = '1' then
cnt2 <= (others => '0');
elsif clk1_en = '1' then
cnt2 <= cnt2 + 1;
end if;
end process;
process
begin
wait until rising_edge(clk);
if cnt2 = 0 then
clk1_en <= '1';
latch <= '0';
rst <= '0';
elsif cnt2 = gate then
clk1_en <= '0';
latch <= '1';
rst <= '0';
elsif cnt2 = gate+1 then
clk1_en <= '0';
latch <= '0';
rst <= '1';
end if;
end process;
end rtl;
| gpl-2.0 | 8bb47a907e6f6d842feef6007b83e260 | 0.600678 | 2.487352 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma.vhd | 1 | 126,849 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma.vhd
-- Description: This entity is the top level entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library axi_sg_v4_1;
use axi_sg_v4_1.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 10;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
-- C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_MM2S_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_S2MM_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
-- Enable CACHE support, primarily for MCDMA
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
-- Number of S2MM channels, primarily for MCDMA
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
-- Number of MM2S channels, primarily for MCDMA
C_FAMILY : string := "virtex7";
C_MICRO_DMA : integer range 0 to 1 := 0;
-- Target FPGA Device Family
C_INSTANCE : string := "axi_dma"
);
port (
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axi_s2mm_aclk : in std_logic := '0' ; --
-----------------------------------------------------------------------
-- Primary Clock CDMA
-----------------------------------------------------------------------
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
-- s_axi_lite_awaddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_awaddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
-- s_axi_lite_araddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_araddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic := '0' ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic := '0' ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := "00" ; --
m_axi_sg_bvalid : in std_logic := '0' ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0' ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
m_axis_mm2s_tuser : out std_logic_vector (3 downto 0) ; --
m_axis_mm2s_tid : out std_logic_vector (4 downto 0) ; --
m_axis_mm2s_tdest : out std_logic_vector (4 downto 0) ; --
--
-- Memory Map to Stream Control Stream Interface --
mm2s_cntrl_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
s_axis_s2mm_tuser : in std_logic_vector (3 downto 0) := "0000" ; --
s_axis_s2mm_tid : in std_logic_vector (4 downto 0) := "00000" ; --
s_axis_s2mm_tdest : in std_logic_vector (4 downto 0) := "00000" ; --
--
-- Stream to Memory Map Status Steam Interface --
s2mm_sts_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_sts_tvalid : in std_logic := '0'; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic := '0'; --
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_dma_tstvec : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
);
end axi_dma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- The FREQ are needed only for ASYNC mode, for SYNC mode these are irrelevant
-- For Async, mm2s or s2mm >= sg >= lite
constant C_S_AXI_LITE_ACLK_FREQ_HZ : integer := 100000000;
-- AXI Lite clock frequency in hertz
constant C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- AXI MM2S clock frequency in hertz
constant C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- AXI S2MM clock frequency in hertz
constant C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000;
-- Scatter Gather clock frequency in hertz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_string (value_in_1 : integer)
return string is
Variable max_value : string (1 to 5) := "00000";
begin
If (value_in_1 = 1) Then
-- coverage off
max_value := "11100";
-- coverage on
else
max_value := "11111";
End if;
Return (max_value);
end function funct_get_string;
function width_calc (value_in : integer)
return integer is
variable addr_value : integer := 32;
begin
if (value_in > 32) then
addr_value := 64;
else
addr_value := 32;
end if;
return(addr_value);
end function width_calc;
-- -------------------------------------------------------------------
--
--
--
-- -------------------------------------------------------------------
-- -- Function
-- --
-- -- Function Name: funct_rnd2pwr_of_2
-- --
-- -- Function Description:
-- -- Rounds the input value up to the nearest power of 2 between
-- -- 128 and 8192.
-- --
-- -------------------------------------------------------------------
-- function funct_rnd2pwr_of_2 (input_value : integer) return integer is
--
-- Variable temp_pwr2 : Integer := 128;
--
-- begin
--
-- if (input_value <= 128) then
--
-- temp_pwr2 := 128;
--
-- elsif (input_value <= 256) then
--
-- temp_pwr2 := 256;
--
-- elsif (input_value <= 512) then
--
-- temp_pwr2 := 512;
--
-- elsif (input_value <= 1024) then
--
-- temp_pwr2 := 1024;
--
-- elsif (input_value <= 2048) then
--
-- temp_pwr2 := 2048;
--
-- elsif (input_value <= 4096) then
--
-- temp_pwr2 := 4096;
--
-- else
--
-- temp_pwr2 := 8192;
--
-- end if;
--
--
-- Return (temp_pwr2);
--
-- end function funct_rnd2pwr_of_2;
-- -------------------------------------------------------------------
--
--
--
--
--
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
constant skid_enable : string := (funct_get_string(0));
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
-- Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
-- (funct_get_max(4, 4)+2)
-- * C_M_AXI_MAX_BURST_LEN;
--
-- -- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- -- power of 2
-- Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
-- funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Scatter Gather Engine Configuration
-- Number of Fetch Descriptors to Queue
constant ADDR_WIDTH : integer := width_calc (C_M_AXI_SG_ADDR_WIDTH);
constant MCDMA : integer := (1 - C_ENABLE_MULTI_CHANNEL);
constant DESC_QUEUE : integer := (1*MCDMA);
constant STSCNTRL_ENABLE : integer := (C_SG_INCLUDE_STSCNTRL_STRM*MCDMA);
constant APPLENGTH_ENABLE : integer := (C_SG_USE_STSAPP_LENGTH*MCDMA);
constant C_SG_LENGTH_WIDTH_INT : integer := (C_SG_LENGTH_WIDTH*MCDMA + 23*C_ENABLE_MULTI_CHANNEL);
-- Comment the foll 2 line to disable queuing for McDMA and uncomment the 3rd and 4th lines
--constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
-- Number of Update Descriptors to Queue
--constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 8 + (5 * STSCNTRL_ENABLE);
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 8; -- Only need to fetch 1st 8wrds for s2mm
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- Only status needs update for mm2s
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1 + (5 * STSCNTRL_ENABLE);
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERROR : integer := 1;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor update pointer bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor update status bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- IOC (1 bit) & DescStatus (32 bits)
-- Include SG Descriptor Updates
constant INCLUDE_DESC_UPDATE : integer := 1;
-- Include SG Interrupt Logic
constant INCLUDE_INTRPT : integer := 1;
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
--constant DM_CMDSTS_FIFO_DEPTH : integer := 1*C_ENABLE_MULTI_CHANNEL + (max2(1,SG_UPDT_DESC2QUEUE))*MCDMA;
constant DM_CMDSTS_FIFO_DEPTH : integer := max2(1,SG_UPDT_DESC2QUEUE);
constant DM_CMDSTS_FIFO_DEPTH_1 : integer := ((1-C_PRMRY_IS_ACLK_ASYNC)+C_PRMRY_IS_ACLK_ASYNC*DM_CMDSTS_FIFO_DEPTH);
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- Enable indeterminate BTT on datamover when stscntrl stream not included or
-- when use status app rx length is not enable or when in Simple DMA mode.
constant DM_SUPPORT_INDET_BTT : integer := 1 - (STSCNTRL_ENABLE
* APPLENGTH_ENABLE
* C_INCLUDE_SG) - C_MICRO_DMA;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- DataMover status width - is based on mode of operation
constant DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 1;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := (C_INCLUDE_MM2S) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_MM2S;
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := (C_INCLUDE_S2MM) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_S2MM;
-- Minimum value required for length width based on burst size and stream dwidth
-- If user sets c_sg_length_width too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant DM_BTT_LENGTH_WIDTH : integer := max2((required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH,
C_MM2S_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_MM2S),
(required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH,
C_S2MM_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_S2MM));
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH);
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- Return correct freq_hz parameter depending on if sg engine is included
constant M_AXI_SG_ACLK_FREQ_HZ :integer := hertz_prmtr_select(C_INCLUDE_SG,
C_S_AXI_LITE_ACLK_FREQ_HZ,
C_M_AXI_SG_ACLK_FREQ_HZ);
-- Scatter / Gather is always configure for synchronous operation for AXI DMA
constant SG_IS_SYNCHRONOUS : integer := 0;
constant CMD_WIDTH : integer := ((8*C_ENABLE_MULTI_CHANNEL)+ ADDR_WIDTH+ CMD_BASE_WIDTH) ;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi_lite_aclk : std_logic := '1';
signal axi_sg_aclk : std_logic := '1';
signal m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard)
signal dm_m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard) (Raw)
signal m_axi_mm2s_aresetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal m_axi_s2mm_aresetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg aclk domain (Soft/Hard)
signal s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg aclk domain (Soft/Hard)
signal mm2s_prmry_resetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)
signal s2mm_prmry_resetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)
signal axi_lite_reset_n : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_hrdresetn : std_logic := '1'; -- AXI Lite Interface Reset on SG clock domain (Hard Only)
signal dm_mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg domain (Soft/Hard)(Raw)
signal dm_s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg domain (Soft/Hard)(Raw)
-- Register Module Signals
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); --(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal mm2s_length_wren : std_logic := '0';
signal mm2s_smpl_interr_set : std_logic := '0';
signal mm2s_smpl_slverr_set : std_logic := '0';
signal mm2s_smpl_decerr_set : std_logic := '0';
signal mm2s_smpl_done : std_logic := '0';
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_packet_eof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal mm2s_dlyirq_dsble : std_logic := '0'; -- CR605888
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0'); --(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_length_wren : std_logic := '0';
signal s2mm_bytes_rcvd : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_bytes_rcvd_wren : std_logic := '0';
signal s2mm_smpl_interr_set : std_logic := '0';
signal s2mm_smpl_slverr_set : std_logic := '0';
signal s2mm_smpl_decerr_set : std_logic := '0';
signal s2mm_smpl_done : std_logic := '0';
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_error : std_logic := '0';
signal s2mm_dlyirq_dsble : std_logic := '0'; -- CR605888
signal mm2s_stop : std_logic := '0';
signal s2mm_stop : std_logic := '0';
signal ftch_error : std_logic := '0';
signal ftch_error_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_error : std_logic := '0';
signal updt_error_addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
--*********************************
-- MM2S Signals
--*********************************
-- MM2S DMA Controller Signals
signal mm2s_desc_flush : std_logic := '0';
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata_new : std_logic_vector(96+31*0+(0+2)*(ADDR_WIDTH-32) downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid_new : std_logic := '0';
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- SG MM2S Descriptor Update AXI Stream Out
signal s_axis_mm2s_updtptr_tdata : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtptr_tvalid : std_logic := '0';
signal s_axis_mm2s_updtptr_tready : std_logic := '0';
signal s_axis_mm2s_updtptr_tlast : std_logic := '0';
signal s_axis_mm2s_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtsts_tvalid : std_logic := '0';
signal s_axis_mm2s_updtsts_tready : std_logic := '0';
signal s_axis_mm2s_updtsts_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid_split : std_logic := '0';
signal s_axis_mm2s_cmd_tready_split : std_logic := '0';
signal s_axis_mm2s_cmd_tdata_split : std_logic_vector
((ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_s2mm_cmd_tvalid_split : std_logic := '0';
signal s_axis_s2mm_cmd_tready_split : std_logic := '0';
signal s_axis_s2mm_cmd_tdata_split : std_logic_vector
((ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tvalid_int : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_updt_idle : std_logic := '0';
signal s2mm_updt_ioc_irq_set : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata_new : std_logic_vector(96+31*0+(0+2)*(ADDR_WIDTH-32) downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_nxt : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid_new : std_logic := '0';
signal m_axis_ftch2_desc_available, m_axis_ftch1_desc_available : std_logic;
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
signal mm2s_axis_info : std_logic_vector(13 downto 0) := (others => '0');
-- SG S2MM Descriptor Update AXI Stream Out
signal s_axis_s2mm_updtptr_tdata : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtptr_tvalid : std_logic := '0';
signal s_axis_s2mm_updtptr_tready : std_logic := '0';
signal s_axis_s2mm_updtptr_tlast : std_logic := '0';
signal s_axis_s2mm_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtsts_tvalid : std_logic := '0';
signal s_axis_s2mm_updtsts_tready : std_logic := '0';
signal s_axis_s2mm_updtsts_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tvalid_int : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tdata_int : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tkeep : std_logic_vector((DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
signal mm2s_updt_interr_set : std_logic := '0';
signal mm2s_updt_slverr_set : std_logic := '0';
signal mm2s_updt_decerr_set : std_logic := '0';
signal mm2s_ftch_err_early : std_logic := '0';
signal mm2s_ftch_stale_desc : std_logic := '0';
signal s2mm_updt_interr_set : std_logic := '0';
signal s2mm_updt_slverr_set : std_logic := '0';
signal s2mm_updt_decerr_set : std_logic := '0';
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
signal s2mm_ftch_err_early : std_logic := '0';
signal s2mm_ftch_stale_desc : std_logic := '0';
signal soft_reset_clr : std_logic := '0';
signal soft_reset : std_logic := '0';
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_int : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_user : std_logic := '0';
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal sg_ctl : std_logic_vector (7 downto 0);
signal s_axis_s2mm_tvalid_int : std_logic;
signal s_axis_s2mm_tlast_int : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal same_tdest : std_logic;
signal s2mm_eof_s2mm : std_logic;
signal ch2_update_active : std_logic;
signal s2mm_desc_info_in : std_logic_vector (13 downto 0);
signal m_axis_mm2s_tlast_i_mcdma : std_logic;
signal s2mm_run_stop_del : std_logic;
signal s2mm_desc_flush_del : std_logic;
signal s2mm_tvalid_latch : std_logic;
signal s2mm_tvalid_latch_del : std_logic;
signal clock_splt : std_logic;
signal clock_splt_s2mm : std_logic;
signal updt_cmpt : std_logic;
signal cmpt_updt : std_logic_vector (1 downto 0);
signal reset1, reset2 : std_logic;
signal mm2s_cntrl_strm_stop : std_logic;
signal bd_eq : std_logic;
signal m_axi_sg_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_sg_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_mm2s_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_s2mm_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_dma_tstvec(31 downto 6) <= (others => '0');
axi_dma_tstvec(5) <= s2mm_updt_ioc_irq_set;
axi_dma_tstvec(4) <= mm2s_updt_ioc_irq_set;
axi_dma_tstvec(3) <= s2mm_packet_eof;
axi_dma_tstvec(2) <= s2mm_packet_sof;
axi_dma_tstvec(1) <= mm2s_packet_eof;
axi_dma_tstvec(0) <= mm2s_packet_sof;
-- Primary MM2S Stream outputs (used internally to gen eof and sof for
-- interrupt coalescing
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i;
-- Primary S2MM Stream output (used internally to gen eof and sof for
-- interrupt coalescing
s_axis_s2mm_tready <= s_axis_s2mm_tready_i;
GEN_INCLUDE_SG : if C_INCLUDE_SG = 1 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= m_axi_sg_aclk;
end generate GEN_INCLUDE_SG;
GEN_EXCLUDE_SG : if C_INCLUDE_SG = 0 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= s_axi_lite_aclk;
end generate GEN_EXCLUDE_SG;
-------------------------------------------------------------------------------
-- AXI DMA Reset Module
-------------------------------------------------------------------------------
I_RST_MODULE : entity axi_dma_v7_1.axi_dma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_MM2S_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_M_AXI_S2MM_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_M_AXI_SG_ACLK_FREQ_HZ => M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
s_axi_lite_aclk => axi_lite_aclk ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- Soft Reset
-----------------------------------------------------------------------
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out (m_axi_mm2s_aclk)
-----------------------------------------------------------------------
dm_mm2s_prmry_resetn => m_axi_mm2s_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_mm2s_scndry_resetn => dm_mm2s_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n , -- AXI Stream Control Reset Outputs
mm2s_scndry_resetn => mm2s_scndry_resetn , -- AXI Secondary Reset
mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out (m_axi_s2mm_aclk)
-----------------------------------------------------------------------
dm_s2mm_prmry_resetn => m_axi_s2mm_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_s2mm_scndry_resetn => dm_s2mm_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n , -- AXI Stream Control Reset Outputs
s2mm_scndry_resetn => s2mm_scndry_resetn , -- AXI Secondary Reset
s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out (m_axi_sg_aclk)
-----------------------------------------------------------------------
m_axi_sg_aresetn => m_axi_sg_aresetn , -- AXI Scatter Gather Reset Out
dm_m_axi_sg_aresetn => dm_m_axi_sg_aresetn , -- AXI Scatter Gather Datamover Reset Out
-----------------------------------------------------------------------
-- Hard Reset Out (s_axi_lite_aclk)
-----------------------------------------------------------------------
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn , -- AXI Lite Ingerface (sg aclk) (Hard Only)
s_axi_lite_resetn => axi_lite_reset_n -- AXI Lite Interface reset (Hard Only)
);
-------------------------------------------------------------------------------
-- AXI DMA Register Module
-------------------------------------------------------------------------------
I_AXI_DMA_REG_MODULE : entity axi_dma_v7_1.axi_dma_reg_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_AXI_LITE_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset_n => axi_lite_reset_n ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S DMASR Status
mm2s_stop => mm2s_stop ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_dma_interr_set => mm2s_dma_interr_set ,
mm2s_dma_slverr_set => mm2s_dma_slverr_set ,
mm2s_dma_decerr_set => mm2s_dma_decerr_set ,
mm2s_ioc_irq_set => mm2s_ioc_irq_set ,
mm2s_dly_irq_set => mm2s_dly_irq_set ,
mm2s_irqthresh_wren => mm2s_irqthresh_wren ,
mm2s_irqdelay_wren => mm2s_irqdelay_wren ,
mm2s_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
mm2s_irqdelay_status => mm2s_irqdelay_status ,
mm2s_irqthresh_status => mm2s_irqthresh_status ,
mm2s_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
mm2s_ftch_interr_set => mm2s_ftch_interr_set ,
mm2s_ftch_slverr_set => mm2s_ftch_slverr_set ,
mm2s_ftch_decerr_set => mm2s_ftch_decerr_set ,
mm2s_updt_interr_set => mm2s_updt_interr_set ,
mm2s_updt_slverr_set => mm2s_updt_slverr_set ,
mm2s_updt_decerr_set => mm2s_updt_decerr_set ,
-- MM2S CURDESC Update
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_new_curdesc => mm2s_new_curdesc ,
-- MM2S TAILDESC Update
mm2s_tailpntr_updated => mm2s_tailpntr_updated ,
-- MM2S Registers
mm2s_dmacr => mm2s_dmacr ,
mm2s_dmasr => mm2s_dmasr ,
mm2s_curdesc => mm2s_curdesc ,
mm2s_taildesc => mm2s_taildesc ,
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
s2mm_sof => s2mm_packet_sof ,
s2mm_eof => s2mm_packet_eof ,
-- S2MM DMASR Status
s2mm_stop => s2mm_stop ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_dma_interr_set => s2mm_dma_interr_set ,
s2mm_dma_slverr_set => s2mm_dma_slverr_set ,
s2mm_dma_decerr_set => s2mm_dma_decerr_set ,
s2mm_ioc_irq_set => s2mm_ioc_irq_set ,
s2mm_dly_irq_set => s2mm_dly_irq_set ,
s2mm_irqthresh_wren => s2mm_irqthresh_wren ,
s2mm_irqdelay_wren => s2mm_irqdelay_wren ,
s2mm_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
s2mm_irqdelay_status => s2mm_irqdelay_status ,
s2mm_irqthresh_status => s2mm_irqthresh_status ,
s2mm_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
s2mm_ftch_interr_set => s2mm_ftch_interr_set ,
s2mm_ftch_slverr_set => s2mm_ftch_slverr_set ,
s2mm_ftch_decerr_set => s2mm_ftch_decerr_set ,
s2mm_updt_interr_set => s2mm_updt_interr_set ,
s2mm_updt_slverr_set => s2mm_updt_slverr_set ,
s2mm_updt_decerr_set => s2mm_updt_decerr_set ,
-- MM2S CURDESC Update
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_tvalid => s_axis_s2mm_tvalid ,
s2mm_tvalid_latch => s2mm_tvalid_latch ,
s2mm_tvalid_latch_del => s2mm_tvalid_latch_del ,
-- MM2S TAILDESC Update
s2mm_tailpntr_updated => s2mm_tailpntr_updated ,
-- S2MM Registers
s2mm_dmacr => s2mm_dmacr ,
s2mm_dmasr => s2mm_dmasr ,
s2mm_curdesc => s2mm_curdesc ,
s2mm_taildesc => s2mm_taildesc ,
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
tdest_in => tdest_out_int, --s_axis_s2mm_tdest ,
same_tdest_in => same_tdest,
sg_ctl => sg_ctl ,
-- Soft reset and clear
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
-- Fetch/Update error addresses
ftch_error_addr => ftch_error_addr ,
updt_error_addr => updt_error_addr ,
-- DMA Interrupt Outputs
mm2s_introut => mm2s_introut ,
s2mm_introut => s2mm_introut ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Mode (C_INCLUDE_SG = 1)
-------------------------------------------------------------------------------
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
begin
-- reset1 <= dm_m_axi_sg_aresetn and s2mm_tvalid_latch;
-- reset2 <= m_axi_sg_aresetn and s2mm_tvalid_latch;
s2mm_run_stop_del <= s2mm_tvalid_latch_del and s2mm_dmacr(DMACR_RS_BIT);
-- s2mm_run_stop_del <= (not (updt_cmpt)) and s2mm_dmacr(DMACR_RS_BIT);
s2mm_desc_flush_del <= s2mm_desc_flush or (not s2mm_tvalid_latch);
-- Scatter Gather Engine
I_SG_ENGINE : entity axi_sg_v4_1.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_AXIS_IS_ASYNC => SG_IS_SYNCHRONOUS ,
C_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => INCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => INCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => STSCNTRL_ENABLE ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_NUM_MM2S_CHANNELS => C_NUM_MM2S_CHANNELS ,
C_ACTUAL_ADDR => C_M_AXI_SG_ADDR_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
dm_resetn => dm_m_axi_sg_aresetn ,
p_reset_n => mm2s_prmry_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr_internal ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => m_axi_sg_awuser ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr_internal ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => m_axi_sg_aruser ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
sg_ctl => sg_ctl ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
ch1_cyclic => mm2s_dmacr(CYCLIC_BIT) ,
ch1_desc_flush => mm2s_desc_flush ,
ch1_cntrl_strm_stop => mm2s_cntrl_strm_stop ,
ch1_ftch_idle => mm2s_ftch_idle ,
ch1_ftch_interr_set => mm2s_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_ftch_decerr_set ,
ch1_ftch_err_early => mm2s_ftch_err_early ,
ch1_ftch_stale_desc => mm2s_ftch_stale_desc ,
ch1_updt_idle => mm2s_updt_idle ,
ch1_updt_ioc_irq_set => mm2s_updt_ioc_irq_set ,
ch1_updt_interr_set => mm2s_updt_interr_set ,
ch1_updt_slverr_set => mm2s_updt_slverr_set ,
ch1_updt_decerr_set => mm2s_updt_decerr_set ,
ch1_dma_interr_set => mm2s_dma_interr_set ,
ch1_dma_slverr_set => mm2s_dma_slverr_set ,
ch1_dma_decerr_set => mm2s_dma_decerr_set ,
ch1_tailpntr_enabled => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => mm2s_tailpntr_updated ,
ch1_taildesc => mm2s_taildesc ,
ch1_curdesc => mm2s_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
--ch1_dlyirq_dsble => mm2s_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch1_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_packet_eof ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_sg_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => axi_sg_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_run_stop_del , --s2mm_dmacr(DMACR_RS_BIT) ,
ch2_cyclic => s2mm_dmacr(CYCLIC_BIT) ,
ch2_desc_flush => s2mm_desc_flush_del, --s2mm_desc_flush ,
ch2_ftch_idle => s2mm_ftch_idle ,
ch2_ftch_interr_set => s2mm_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_ftch_decerr_set ,
ch2_ftch_err_early => s2mm_ftch_err_early ,
ch2_ftch_stale_desc => s2mm_ftch_stale_desc ,
ch2_updt_idle => s2mm_updt_idle ,
ch2_updt_ioc_irq_set => s2mm_updt_ioc_irq_set , -- For TestVector
ch2_updt_interr_set => s2mm_updt_interr_set ,
ch2_updt_slverr_set => s2mm_updt_slverr_set ,
ch2_updt_decerr_set => s2mm_updt_decerr_set ,
ch2_dma_interr_set => s2mm_dma_interr_set ,
ch2_dma_slverr_set => s2mm_dma_slverr_set ,
ch2_dma_decerr_set => s2mm_dma_decerr_set ,
ch2_tailpntr_enabled => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
ch2_taildesc_wren => s2mm_tailpntr_updated ,
ch2_taildesc => s2mm_taildesc ,
ch2_curdesc => s2mm_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
--ch2_dlyirq_dsble => s2mm_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch2_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_packet_eof ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status ,
ch2_update_active => ch2_update_active ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_sg_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_ch2_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => axi_sg_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Error addresses
ftch_error => ftch_error ,
ftch_error_addr => ftch_error_addr ,
updt_error => updt_error ,
updt_error_addr => updt_error_addr ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ,
bd_eq => bd_eq
);
m_axi_sg_awaddr <= m_axi_sg_awaddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_araddr <= m_axi_sg_araddr_internal (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
end generate GEN_SG_ENGINE;
-------------------------------------------------------------------------------
-- Exclude Scatter Gather Engine (Simple DMA Mode Enabled)
-------------------------------------------------------------------------------
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather AXI Master Interface Tie-Off
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
m_axi_sg_awvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0';
m_axi_sg_wvalid <= '0';
m_axi_sg_bready <= '0';
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
-- MM2S Signal Remapping/Tie Off for Simple DMA Mode
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s_axis_mm2s_updtptr_tready <= '0';
s_axis_mm2s_updtsts_tready <= '0';
mm2s_ftch_idle <= '1';
mm2s_updt_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
mm2s_ftch_err_early <= '0';
mm2s_ftch_stale_desc <= '0';
mm2s_updt_interr_set <= '0';
mm2s_updt_slverr_set <= '0';
mm2s_updt_decerr_set <= '0';
mm2s_updt_ioc_irq_set <= mm2s_smpl_done; -- For TestVector
mm2s_dma_interr_set <= mm2s_smpl_interr_set; -- To DMASR
mm2s_dma_slverr_set <= mm2s_smpl_slverr_set; -- To DMASR
mm2s_dma_decerr_set <= mm2s_smpl_decerr_set; -- To DMASR
-- S2MM Signal Remapping/Tie Off for Simple DMA Mode
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
s_axis_s2mm_updtptr_tready <= '0';
s_axis_s2mm_updtsts_tready <= '0';
s2mm_ftch_idle <= '1';
s2mm_updt_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
s2mm_ftch_err_early <= '0';
s2mm_ftch_stale_desc <= '0';
s2mm_updt_interr_set <= '0';
s2mm_updt_slverr_set <= '0';
s2mm_updt_decerr_set <= '0';
s2mm_updt_ioc_irq_set <= s2mm_smpl_done; -- For TestVector
s2mm_dma_interr_set <= s2mm_smpl_interr_set; -- To DMASR
s2mm_dma_slverr_set <= s2mm_smpl_slverr_set; -- To DMASR
s2mm_dma_decerr_set <= s2mm_smpl_decerr_set; -- To DMASR
ftch_error <= '0';
ftch_error_addr <= (others => '0');
updt_error <= '0';
updt_error_addr <= (others=> '0');
-- CR595462 - Removed interrupt coalescing logic for Simple DMA mode and replaced
-- with interrupt complete.
mm2s_ioc_irq_set <= mm2s_smpl_done;
mm2s_dly_irq_set <= '0';
mm2s_irqdelay_status <= (others => '0');
mm2s_irqthresh_status <= (others => '0');
s2mm_ioc_irq_set <= s2mm_smpl_done;
s2mm_dly_irq_set <= '0';
s2mm_irqdelay_status <= (others => '0');
s2mm_irqthresh_status <= (others => '0');
end generate GEN_NO_SG_ENGINE;
INCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 1 generate
begin
-------------------------------------------------------------------------------
-- MM2S DMA Controller
-------------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH, --C_M_AXI_MM2S_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
soft_reset => soft_reset ,
-- MM2S Control and Status
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
mm2s_keyhole => mm2s_dmacr(DMACR_KH_BIT) ,
mm2s_halted => mm2s_dmasr(DMASR_HALTED_BIT) ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_stop => mm2s_stop ,
mm2s_ftch_err_early => mm2s_ftch_err_early ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_desc_flush => mm2s_desc_flush ,
cntrl_strm_stop => mm2s_cntrl_strm_stop ,
mm2s_tailpntr_enble => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_error => mm2s_error ,
s2mm_error => s2mm_error ,
-- Simple DMA Mode Signals
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
mm2s_smple_done => mm2s_smpl_done ,
mm2s_interr_set => mm2s_smpl_interr_set ,
mm2s_slverr_set => mm2s_smpl_slverr_set ,
mm2s_decerr_set => mm2s_smpl_decerr_set ,
m_axis_mm2s_aclk => m_axi_mm2s_aclk,
mm2s_strm_tlast => m_axis_mm2s_tlast_i_user,
mm2s_strm_tready => m_axis_mm2s_tready,
mm2s_axis_info => mm2s_axis_info,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Currently Being Processed Descriptor
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready_split ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
mm2s_err => mm2s_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => open, --m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => open, --m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => open, --m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => '0', --m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => open --m_axis_mm2s_cntrl_tlast
);
m_axis_mm2s_tuser <= mm2s_axis_info (13 downto 10);
m_axis_mm2s_tid <= mm2s_axis_info (9 downto 5); --
m_axis_mm2s_tdest <= mm2s_axis_info (4 downto 0) ; --
-- If MM2S channel included then include sof/eof generator
-------------------------------------------------------------------------------
-- MM2S SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_MM2S_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
axis_tready => m_axis_mm2s_tready ,
axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tlast => m_axis_mm2s_tlast_i ,
packet_sof => mm2s_packet_sof ,
packet_eof => mm2s_packet_eof
);
end generate INCLUDE_MM2S_SOF_EOF_GENERATOR;
-- If MM2S channel not included then exclude sof/eof generator
EXCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_packet_sof <= '0';
mm2s_packet_eof <= '0';
end generate EXCLUDE_MM2S_SOF_EOF_GENERATOR;
INCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 1 generate
begin
-------------------------------------------------------------------------------
-- S2MM DMA Controller
-------------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => APPLENGTH_ENABLE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
soft_reset => soft_reset ,
-- S2MM Control and Status
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
s2mm_keyhole => s2mm_dmacr(DMACR_KH_BIT) ,
s2mm_halted => s2mm_dmasr(DMASR_HALTED_BIT) ,
s2mm_packet_eof_out => s2mm_eof_s2mm ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_stop => s2mm_stop ,
s2mm_ftch_err_early => s2mm_ftch_err_early ,
s2mm_ftch_stale_desc => s2mm_ftch_stale_desc ,
s2mm_desc_flush => s2mm_desc_flush ,
s2mm_tailpntr_enble => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_error => s2mm_error ,
mm2s_error => mm2s_error ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- Simple DMA Mode Signals
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_smple_done => s2mm_smpl_done ,
s2mm_interr_set => s2mm_smpl_interr_set ,
s2mm_slverr_set => s2mm_smpl_slverr_set ,
s2mm_decerr_set => s2mm_smpl_decerr_set ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Currently Being Processed Descriptor
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
-- s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
-- s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
-- s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
s2mm_err => s2mm_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Stream to Memory Map Status Stream Interface
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
-- If S2MM channel included then include sof/eof generator
-------------------------------------------------------------------------------
-- S2MM SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_S2MM_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid ,
axis_tlast => s_axis_s2mm_tlast ,
packet_sof => s2mm_packet_sof ,
packet_eof => s2mm_packet_eof
);
end generate INCLUDE_S2MM_SOF_EOF_GENERATOR;
-- If S2MM channel not included then exclude sof/eof generator
EXCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_packet_sof <= '0';
s2mm_packet_eof <= '0';
end generate EXCLUDE_S2MM_SOF_EOF_GENERATOR;
INCLUDE_S2MM_GATE : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
cmpt_updt <= m_axis_s2mm_sts_tvalid & s2mm_eof_s2mm;
I_S2MM_GATE_GEN : entity axi_dma_v7_1.axi_dma_s2mm
generic map (
C_FAMILY => C_FAMILY
)
port map (
clk_in => m_axi_s2mm_aclk,
sg_clk => axi_sg_aclk,
resetn => s2mm_prmry_resetn,
reset_sg => m_axi_sg_aresetn,
s2mm_tvalid => s_axis_s2mm_tvalid,
s2mm_tready => s_axis_s2mm_tready_i,
s2mm_tlast => s_axis_s2mm_tlast,
s2mm_tdest => s_axis_s2mm_tdest,
s2mm_tuser => s_axis_s2mm_tuser,
s2mm_tid => s_axis_s2mm_tid,
desc_available => s_axis_s2mm_cmd_tvalid_split,
-- s2mm_eof => s2mm_eof_s2mm,
s2mm_eof_det => cmpt_updt, --m_axis_s2mm_sts_tvalid, --s2mm_eof_s2mm,
ch2_update_active => ch2_update_active,
tdest_out => tdest_out_int,
same_tdest => same_tdest,
-- to DM
-- updt_cmpt => updt_cmpt,
s2mm_desc_info => s2mm_desc_info_in,
s2mm_tvalid_out => open, --s_axis_s2mm_tvalid_int,
s2mm_tready_out => open, --s_axis_s2mm_tready_i,
s2mm_tlast_out => open, --s_axis_s2mm_tlast_int,
s2mm_tdest_out => open
);
end generate INCLUDE_S2MM_GATE;
INCLUDE_S2MM_NOGATE : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
updt_cmpt <= '0';
tdest_out_int <= (others => '0');
same_tdest <= '0';
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid;
s_axis_s2mm_tlast_int <= s_axis_s2mm_tlast;
end generate INCLUDE_S2MM_NOGATE;
MM2S_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_MM2S = 1) generate
begin
CLOCKS : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt <= axi_sg_aclk;
end generate CLOCKS;
CLOCKS_SYNC : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt <= m_axi_mm2s_aclk;
end generate CLOCKS_SYNC;
I_COMMAND_MM2S_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => ADDR_WIDTH,
C_INCLUDE_S2MM => 0,
C_DM_STATUS_WIDTH => 8
)
port map (
clock => clock_splt, --axi_sg_aclk,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_mm2s_aclk, --axi_sg_aclk,
aresetn => m_axi_mm2s_aresetn,
-- MM2S command coming from MM2S_MNGR
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready_split,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata_split,
-- MM2S split command to DM
s_axis_cmd_tvalid_s => s_axis_mm2s_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_mm2s_cmd_tready,
s_axis_cmd_tdata_s => s_axis_mm2s_cmd_tdata,
tvalid_from_datamover => m_axis_mm2s_sts_tvalid_int,
status_in => m_axis_mm2s_sts_tdata_int,
tvalid_unsplit => m_axis_mm2s_sts_tvalid,
status_out => m_axis_mm2s_sts_tdata,
tlast_stream_data => m_axis_mm2s_tlast_i_mcdma,
tready_stream_data => m_axis_mm2s_tready,
tlast_unsplit => m_axis_mm2s_tlast_i,
tlast_unsplit_user => m_axis_mm2s_tlast_i_user
);
end generate MM2S_SPLIT;
MM2S_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_MM2S = 1) generate
begin
s_axis_mm2s_cmd_tvalid <= s_axis_mm2s_cmd_tvalid_split;
s_axis_mm2s_cmd_tready_split <= s_axis_mm2s_cmd_tready;
s_axis_mm2s_cmd_tdata <= s_axis_mm2s_cmd_tdata_split ((ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_mm2s_sts_tvalid <= m_axis_mm2s_sts_tvalid_int;
m_axis_mm2s_sts_tdata <= m_axis_mm2s_sts_tdata_int;
m_axis_mm2s_tlast_i <= m_axis_mm2s_tlast_i_mcdma;
m_axis_mm2s_tlast_i_user <= '0';
end generate MM2S_SPLIT_NOMCDMA;
S2MM_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
CLOCKS_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt_s2mm <= axi_sg_aclk;
end generate CLOCKS_S2MM;
CLOCKS_SYNC_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt_s2mm <= m_axi_s2mm_aclk;
end generate CLOCKS_SYNC_S2MM;
I_COMMAND_S2MM_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => ADDR_WIDTH,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH
)
port map (
clock => clock_splt_s2mm,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_s2mm_aclk, --axi_sg_aclk, --m_axi_s2mm_aclk,
aresetn => m_axi_s2mm_aresetn,
-- S2MM command coming from S2MM_MNGR
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready_split,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata_split,
-- S2MM split command to DM
s_axis_cmd_tvalid_s => s_axis_s2mm_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_s2mm_cmd_tready,
s_axis_cmd_tdata_s => s_axis_s2mm_cmd_tdata,
tvalid_from_datamover => m_axis_s2mm_sts_tvalid_int,
status_in => m_axis_s2mm_sts_tdata_int,
tvalid_unsplit => m_axis_s2mm_sts_tvalid,
status_out => m_axis_s2mm_sts_tdata,
tlast_stream_data => '0',
tready_stream_data => '0',
tlast_unsplit => open,
tlast_unsplit_user => open
);
end generate S2MM_SPLIT;
S2MM_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
s_axis_s2mm_cmd_tvalid <= s_axis_s2mm_cmd_tvalid_split;
s_axis_s2mm_cmd_tready_split <= s_axis_s2mm_cmd_tready;
s_axis_s2mm_cmd_tdata <= s_axis_s2mm_cmd_tdata_split ((ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_s2mm_sts_tvalid <= m_axis_s2mm_sts_tvalid_int;
m_axis_s2mm_sts_tdata <= m_axis_s2mm_sts_tdata_int;
end generate S2MM_SPLIT_NOMCDMA;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE,
C_M_AXI_MM2S_ADDR_WIDTH => ADDR_WIDTH,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_MM2S_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE,
C_MM2S_BURST_SIZE => C_MM2S_BURST_SIZE,
C_MM2S_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF,
C_ENABLE_CACHE_USER => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_SKID_BUF => skid_enable, --"11111",
C_MICRO_DMA => C_MICRO_DMA,
C_CMD_WIDTH => CMD_WIDTH,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE,
C_M_AXI_S2MM_ADDR_WIDTH => ADDR_WIDTH,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_S2MM_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE,
C_S2MM_BURST_SIZE => C_S2MM_BURST_SIZE,
C_S2MM_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_mm2s_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata
(((8*C_ENABLE_MULTI_CHANNEL)+
ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid_int ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata_int ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr_internal ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_aruser => m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast_i_mcdma ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_s2mm_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata (
((8*C_ENABLE_MULTI_CHANNEL)+
ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid_int ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata_int ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr_internal ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awuser => m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready_i ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
| mit | 6386db11e34646ce433e97f4b2bb4169 | 0.438474 | 3.788234 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/tb_PSR_Modifier.vhd | 2 | 3,254 | --------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_PSR_Modifier IS
END tb_PSR_Modifier;
ARCHITECTURE behavior OF tb_PSR_Modifier IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PSR_Modifier
PORT(
oper1 : IN std_logic_vector(31 downto 0);
oper2 : IN std_logic_vector(31 downto 0);
aluop : IN std_logic_vector(5 downto 0);
aluResult : IN std_logic_vector(31 downto 0);
conditionalCodes : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal aluop : std_logic_vector(5 downto 0) := (others => '0');
signal aluResult : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal conditionalCodes : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PSR_Modifier PORT MAP (
oper1 => oper1,
oper2 => oper2,
aluop => aluop,
aluResult => aluResult,
conditionalCodes => conditionalCodes
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns. Para las instrucciones Logicas
wait for 100 ns;
aluop<="010101";
aluResult<="11111100000000000000000000000000";
wait for 100 ns;
aluop<="010110";
aluResult<="01111100000000000000000000000000";
wait for 100 ns;
aluop<="010101";
aluResult<="00000000000000000000000000000000";
wait for 100 ns;
aluop<="111111";
aluResult<="00000000000000000000000000000111";
------------------------------------------------- para los ADDccs
wait for 100 ns;
aluop<="010000";
aluResult<="00000000000000000000000000000111";
oper1<="00000000000000000001000000000111";
oper2<="00000001000000000001000000000111";
wait for 100 ns;
aluop<="010000";
aluResult<="00000000000000000000000000000111";
oper1<="10000000000000000001000000000111";
oper2<="10000001000000000001000000000111";
wait for 100 ns;
aluop<="010000";
aluResult<="10000000000000000000000000000111";
oper1<="11000000000000000001000000000111";
oper2<="11000001000000000001000000000111";
wait for 100 ns;
aluop<="010000";
aluResult<="00000000000000000000000000000000";
oper1<="11000000000000000001000000000111";
oper2<="11000001000000000001000000000111";
------------------------------------------------- para los SUBccs
wait for 100 ns;
aluop<="010100";
aluResult<="00000000000000000000000000000111";
oper1<="00000000000000000001000000000111";
oper2<="10000001000000000001000000000111";
wait for 100 ns;
aluop<="010100";
aluResult<="10000000000000000000000000000111";
oper1<="00000000000000000001000000000111";
oper2<="10000001000000000001000000000111";
wait for 100 ns;
aluop<="011111";
aluResult<="10000000000000000000000000000111";
oper1<="11000000000000000001000000000111";
oper2<="11000001000000000001000000000111";
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | 1a51f6cfe9d284739eee9b5ac445fde2 | 0.637984 | 4.615603 | false | false | false | false |
fumyuun/tasty | src/platform/nexys4ddr/seven_segment_ctrl.vhd | 1 | 3,285 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity seven_segment_ctrl is
port (
clk_i : in std_logic;
num_i : in std_logic_vector(15 downto 0);
an_o : out std_logic_vector(7 downto 0);
c_o : out std_logic_vector(7 downto 0)
);
end entity;
architecture behavioral of seven_segment_ctrl is
signal active_digit_s : std_logic_vector(3 downto 0);
signal pattern_s : std_logic_vector(7 downto 0);
signal digit_s : unsigned(3 downto 0);
signal turn_s : unsigned(2 downto 0); -- who's turn is it?
signal turn_next_s : unsigned(2 downto 0);
signal cycle_count_s : unsigned(15 downto 0); -- on overflow (every 65,535 cycles, increment turn)
signal cycle_count_next_s : unsigned(15 downto 0);
begin
an_o <= "11111110" when turn_s = 0 else
"11111101" when turn_s = 1 else
"11111011" when turn_s = 2 else
"11110111" when turn_s = 3 else
--"11101111" when turn_s = 4 else
--"11011111" when turn_s = 5 else
--"10111111" when turn_s = 6 else
--"01111111" when turn_s = 7 else
"11111111";
c_o <= pattern_s;
active_digit_s <= num_i(1 * 4 - 1 downto 0 * 4) when turn_s = 0 else
num_i(2 * 4 - 1 downto 1 * 4) when turn_s = 1 else
num_i(3 * 4 - 1 downto 2 * 4) when turn_s = 2 else
num_i(4 * 4 - 1 downto 3 * 4) when turn_s = 3 else
--num_i(5 * 4 - 1 downto 4 * 4) when turn_s = 4 else
--num_i(6 * 4 - 1 downto 5 * 4) when turn_s = 5 else
--num_i(7 * 4 - 1 downto 6 * 4) when turn_s = 6 else
--num_i(8 * 4 - 1 downto 7 * 4) when turn_s = 7 else
x"0";
digit_s <= unsigned(active_digit_s);
pattern_s <= "00000011" when digit_s = x"0" else
"10011111" when digit_s = x"1" else
"00100101" when digit_s = x"2" else
"00001101" when digit_s = x"3" else
"10011001" when digit_s = x"4" else
"01001001" when digit_s = x"5" else
"01000001" when digit_s = x"6" else
"00011111" when digit_s = x"7" else
"00000001" when digit_s = x"8" else
"00001001" when digit_s = x"9" else
"00010001" when digit_s = x"A" else
"11000001" when digit_s = x"B" else
"01100011" when digit_s = x"C" else
"10000101" when digit_s = x"D" else
"01100001" when digit_s = x"E" else
"01110001" when digit_s = x"F" else
"11111111";
clock_proc : process (clk_i)
begin
if rising_edge(clk_i) then
turn_s <= turn_next_s;
cycle_count_s <= cycle_count_next_s;
end if;
end process;
comb_proc : process (cycle_count_s)
begin
turn_next_s <= turn_s;
cycle_count_next_s <= cycle_count_s + 1;
if cycle_count_s = x"FFFF" then
turn_next_s <= turn_s + 1;
cycle_count_next_s <= x"0000";
end if;
end process;
end architecture;
| mit | 5745c041f9e6d2d6e3461e03f54ceadd | 0.501674 | 3.502132 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/tbfetchhhh.vhd | 1 | 3,306 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:22:34 12/02/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/jummmmmmmm/tbfetchhhh.vhd
-- Project Name: jummmmmmmm
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fetch
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbfetchhhh IS
END tbfetchhhh;
ARCHITECTURE behavior OF tbfetchhhh IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fetch
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
CUentrada : IN std_logic_vector(1 downto 0);
Entradain : IN std_logic_vector(31 downto 0);
Instruccionout : OUT std_logic_vector(31 downto 0);
PCout : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal CUentrada : std_logic_vector(1 downto 0) := (others => '0');
signal Entradain : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Instruccionout : std_logic_vector(31 downto 0);
signal PCout : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fetch PORT MAP (
Clk => Clk,
Reset => Reset,
CUentrada => CUentrada,
Entradain => Entradain,
Instruccionout => Instruccionout,
PCout => PCout
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '1';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000101";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000000";
wait for 100 ns;
Reset <= '0';
CUentrada <= "10";
Entradain <= "00000000000000000000000000000001";
wait for 100 ns;
wait;
end process;
END;
| gpl-3.0 | 0049c9b009260b5cd522cb56b8196fed | 0.596794 | 4.158491 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/TestBench1_FourByteAlignedTests.vhd | 1 | 10,289 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.11.2013 00:20:28
-- Design Name:
-- Module Name: TestBench1_FourByteAlignedTests - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestBench1_FourByteAlignedTests is
end TestBench1_FourByteAlignedTests;
architecture Behavioral of TestBench1_FourByteAlignedTests is
-- Signals to evaluate
--ENTRADAS
signal inputBlock : std_logic_vector(31 downto 0);
signal readInput : std_logic;
signal blockLength : std_logic_vector(1 downto 0);
signal finalBlock : std_logic;
signal start : std_logic;
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
--SALIDAS
signal canAccept : std_logic;
signal resultReady : std_logic;
signal result : std_logic_vector(31 downto 0);
signal resultID : std_logic_vector(31 downto 0);
--RELOJ
signal clk : std_logic;
--Salidas de depuracion
signal dataStep1_dbg : std_logic_vector(31 downto 0);
signal dataStep2_dbg : std_logic_vector(31 downto 0);
signal dataStep3_dbg : std_logic_vector(31 downto 0);
signal dataStep4_dbg : std_logic_vector(31 downto 0);
signal dataStep5_dbg : std_logic_vector(31 downto 0);
signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep1_dbg : std_logic_vector(31 downto 0);
signal finalStep2_dbg : std_logic_vector(31 downto 0);
signal finalStep3_dbg : std_logic_vector(31 downto 0);
signal finalStep4_dbg : std_logic_vector(31 downto 0);
signal finalStep5_dbg : std_logic_vector(31 downto 0);
signal finalStep1_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep2_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep3_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep4_ID_dbg : std_logic_vector(31 downto 0);
signal finalStep5_ID_dbg : std_logic_vector(31 downto 0);
type resultReference is array (0 to 13) of std_logic_vector(31 downto 0);
constant resultsBank : resultReference := ( x"2362f9de", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
constant opsIDs : resultReference := ( x"2362f9de", x"fbf1402a", x"2362f9de", x"fbf1402a", x"40b23b7f", x"32850971", x"9994d794", x"4c382e54", x"7117fdd0", x"db55ec24", x"76293b50", x"7e33a1a1", x"82f2c7d0", x"885962c1" );
signal resultsBankCounter : integer := 0;
signal errorDetected : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
--Inicializar el banco de resultados
verification: process (clk, resultReady, result, resultsBankCounter)
begin
if( rising_edge(clk) ) then
if( resultsBankCounter = resultReference'length ) then
errorDetected <= '0';
else
if (resultReady = '1') then
if( (resultsBank(resultsBankCounter)/=result) or (resultID/=opsIDs(resultsBankCounter)) ) then
errorDetected <= '1';
else
errorDetected <= '0';
end if;
resultsBankCounter <= resultsBankCounter+1;
else
errorDetected <= '0';
end if;
end if;
end if;
end process verification;
uut: work.MurmurHashUtils.MurmurHash32Generator PORT MAP (
--ENTRADAS
inputBlock => inputBlock,
readInput => readInput,
blockLength => blockLength,
finalBlock => finalBlock,
start => start,
operationID => operationID,
seed => seed,
--SALIDAS
canAccept => canAccept,
resultReady => resultReady,
result => result,
resultID => resultID,
--RELOJ
clk => clk,
--Salidas de depuracion
dataStep1_dbg => dataStep1_dbg,
dataStep2_dbg => dataStep2_dbg,
dataStep3_dbg => dataStep3_dbg,
dataStep4_dbg => dataStep4_dbg,
dataStep5_dbg => dataStep5_dbg,
dataStep1_ID_dbg => dataStep1_ID_dbg,
dataStep2_ID_dbg => dataStep2_ID_dbg,
dataStep3_ID_dbg => dataStep3_ID_dbg,
dataStep4_ID_dbg => dataStep4_ID_dbg,
dataStep5_ID_dbg => dataStep5_ID_dbg,
finalStep1_dbg => finalStep1_dbg,
finalStep2_dbg => finalStep2_dbg,
finalStep3_dbg => finalStep3_dbg,
finalStep4_dbg => finalStep4_dbg,
finalStep5_dbg => finalStep5_dbg,
finalStep1_ID_dbg => finalStep1_ID_dbg,
finalStep2_ID_dbg => finalStep2_ID_dbg,
finalStep3_ID_dbg => finalStep3_ID_dbg,
finalStep4_ID_dbg => finalStep4_ID_dbg,
finalStep5_ID_dbg => finalStep5_ID_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
blockLength <= "11";
--operationID <= "0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101"&"0101";
operationID <= opsIDs(0);
--PRUEBA 1, HASH DEL VECTOR 0
--Se einicializan los datos y
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
start <= '1';
finalBlock <= '1';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
readInput <= '0';
wait for clk_period;
--hacer que realize una lectura de datos
readInput <= '1';
wait for clk_period;
start <= '0';--que ya no lea otro dato
readInput <= '0';
wait for clk_period;
--Prueba 2 hash del vector 1
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0001";
operationID <= opsIDs(1);
finalBlock <= '1';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
start <= '1';
readInput <= '0';
wait for clk_period;
--hacer que realize una lectura de datos
readInput <= '1';
wait for clk_period;
start <= '0';--que ya no lea otro dato
readInput <= '0';
wait for clk_period;
wait for clk_period;
--PROBAR QUE AMBAS SALIDAS CONSECUTIVAS SE REALIZEN DE FORMA CONSECUTIVA
start <= '1';
finalBlock <= '1';
readInput <= '1';
seed <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
--Probando valroes consecutivos
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(2);
wait for clk_period;
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0001";
operationID <= opsIDs(3);
wait for clk_period;
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0010";
operationID <= opsIDs(4);
wait for clk_period;
inputBlock <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0011";
operationID <= opsIDs(5);
wait for clk_period;
readInput <= '0';
wait for clk_period;
readInput <= '1';
inputBlock <= "1000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(6);
wait for clk_period;
inputBlock <= "0100"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(7);
wait for clk_period;
inputBlock <= "1100"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(8);
wait for clk_period;
inputBlock <= "0010"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000";
operationID <= opsIDs(9);
wait for clk_period;
inputBlock <= "1111"&"1111"&"1111"&"1111"&"1111"&"1111"&"1111"&"1111";
operationID <= opsIDs(10);
wait for clk_period;
inputBlock <= "1111"&"0000"&"1111"&"0000"&"1111"&"0000"&"1111"&"0000";
operationID <= opsIDs(11);
wait for clk_period;
inputBlock <= "0000"&"1111"&"0000"&"1111"&"0000"&"1111"&"0000"&"1111";
operationID <= opsIDs(12);
wait for clk_period;
inputBlock <= "1100"&"1100"&"1100"&"1100"&"1100"&"1100"&"1100"&"1100";
operationID <= opsIDs(13);
wait for clk_period;
readInput <= '0';
wait for clk_period;
wait;
end process stim_proc;
end Behavioral;
| bsd-3-clause | d138eae82f0471b643e281d4fac229b6 | 0.541646 | 4.174037 | false | false | false | false |
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