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fabioperez/space-invaders-vhdl | spaceinvaders.vhd | 1 | 14,384 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library lib;
use lib.controller.all;
use lib.general.all;
use lib.io.all;
entity spaceinvaders is
generic
(
rx : integer := 160; -- H resolution
ry : integer := 120; -- W resolution
cpu_num : integer := ALIENS_PER_LINE; -- aliens per line (set in io.vhd)
cpu_lines : integer := ALIEN_LINES; -- number of lines (set in io.vhd)
py : integer := 110; --
alien_w : integer := 11; -- enemy width
alien_h : integer := 8; -- enemy height
player_w : integer := 13; -- player width
player_h : integer := 6 -- player height
);
port
(
------------------------ Clock Input ------------------------
CLOCK_24 : in STD_LOGIC_VECTOR (1 downto 0); -- 24 MHz
CLOCK_50 : in STD_LOGIC; -- 50 MHz
CLOCK_27 : in STD_LOGIC; -- 27 MHz
------------------------ Push Button ------------------------
KEY : in STD_LOGIC_VECTOR (3 downto 0); -- Pushbutton[3:0]
------------------------ 7-SEG Display ------------------------
HEX0 : out STD_LOGIC_VECTOR (6 downto 0);
HEX1 : out STD_LOGIC_VECTOR (6 downto 0);
HEX2 : out STD_LOGIC_VECTOR (6 downto 0);
HEX3 : out STD_LOGIC_VECTOR (6 downto 0);
---------------------------- LED ----------------------------
LEDG : out STD_LOGIC_VECTOR (7 downto 0); -- LED Green[7:0]
------------------------ PS2 --------------------------------
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
------------------------ VGA --------------------------------
VGA_R, VGA_G, VGA_B : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
VGA_HS, VGA_VS : OUT STD_LOGIC
);
end entity;
architecture Behavior of spaceinvaders is
--------------------------- CLK/RESET ------------------------------
signal clock_s,reset_s,reset: std_logic;
SIGNAL state : GAME_STATE;
------------------------ PLAYER ----------------------------
signal move_s,shot_s,shot_e_s: std_logic;
signal controls: std_logic_vector(2 downto 0);
signal position_x_s: integer range 0 to rx;
signal position_y_s: integer range 0 to ry;
signal shot_y_s: integer range 0 to ry;
signal shot_x_s: integer range 0 to rx;
signal shot_r_s: std_logic;
------------------------ CPU --------------------------------
signal cpu_arr_x: pos_arr_xt;
signal cpu_arr_y: pos_arr_yt;
signal cpu_arr_e: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_c: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_m: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_d: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_game_over: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal turn: std_logic;
signal shot_enemy_y_s: integer range 0 to ry;
signal shot_enemy_x_s: integer range 0 to rx;
signal shot_enemy_e_s: std_logic;
signal shot_enemy_r_s: std_logic;
signal enemy_shooting: std_logic;
signal clk_enemy_shoot: std_logic;
signal player_death, player_reset : std_logic;
signal player_death_by_alien : std_logic;
signal player_exploding,pc_dead_delay : std_logic;
type PC_STATE_TYPE is (ALIVE, EXPLODING, DEAD);
signal pc_state : PC_STATE_TYPE;
signal game_over,game_over_by_lives : std_logic;
signal game_win : std_logic;
------------------------ HEX --------------------------------
signal hex_s: std_logic_vector(27 downto 0);
signal rnd_s,cmb_s: integer;
signal choosen_enemy : integer;
type hex_arr_t is array(cpu_num-1 downto 0) of std_logic_vector(6 downto 0);
signal hex0_arr,hex1_arr,hex2_arr,hex3_arr: hex_arr_t;
signal lives : natural range 0 to 4 := 4;
begin
----------------------------------------------------------------
-- Game reset
----------------------------------------------------------------
reset <= not(KEY(0)); -- Push Button 0
----------------------------------------------------------------
----------------------------------------------------------------
-- Keyboard control
----------------------------------------------------------------
control: kbd_input
port map
( CLOCK_24(0), not(reset_s), KEY(1), PS2_DAT, PS2_CLK, SHOT_S, MOVE_S, CONTROLS );
----------------------------------------------------------------
----------------------------------------------------------------
-- VGA
----------------------------------------------------------------
vga: vga_module
generic map (
rx,
ry,
cpu_num*cpu_lines
)
port map
(
CLOCK_27, NOT(reset),
state,
POSITION_X_S,
POSITION_Y_S,
player_exploding,
SHOT_X_S,
SHOT_Y_S,
shot_enemy_x_s,
shot_enemy_y_s,
cpu_arr_e,
cpu_arr_d,
cpu_arr_x,
cpu_arr_y,
VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS
);
----------------------------------------------------------------
----------------------------------------------------------------
-- Player
----------------------------------------------------------------
-- Player controller
player: pc
generic map
(
clock_div => 1000000,
res_x=>rx,
res_y=>ry,
aux_x=>player_w,
aux_y=>player_h,
pos_y=>py
)
port map
( reset_s OR player_reset, move_s and not(player_exploding), controls(0), CLOCK_50, clock_s, position_x_s, position_y_s);
-- Player shot
pc_shooter: shot
generic map
(
clock_div => 500000,
res_x=>rx,
res_y=>ry,
aux_x=>player_w,
aux_y=>player_h
)
port map
(CLOCK_50, reset_s or shot_r_s, shot_s and not(player_exploding), position_x_s, position_y_s,shot_e_s,shot_x_s,shot_y_s);
-- Player dead sprite
pc_delay: clock_counter
generic map ( 18000000 )
port map ( CLOCK_27, pc_dead_delay );
process (pc_dead_delay)
begin
if reset_s = '1' or player_reset = '1' then
player_exploding <= '0';
player_reset <= '0';
pc_state <= ALIVE;
elsif player_death = '1' then
player_exploding <= '1';
pc_state <= EXPLODING;
elsif rising_edge(pc_dead_delay) then
case pc_state is
when ALIVE =>
when EXPLODING =>
pc_state <= DEAD;
when DEAD =>
player_reset <= '1';
player_exploding <= '0';
end case;
end if;
end process;
----------------------------------------------------------------
----------------------------------------------------------------
-- Aliens generator
----------------------------------------------------------------
-- Verify if any enemy reached one of the sides
turn <= '0' when cpu_arr_m = (cpu_arr_m'range => '0') else '1';
-- Generate enemies
generate_cpu:
for i in 0 to (cpu_num*cpu_lines-1) generate
cpu_x: cpu
generic map
(
res_x => rx,
res_y => ry,
pos_x => 15+(18*(i mod cpu_num)),
pos_y => 15+10*(i/cpu_num),
aux_x => alien_w,
aux_y => alien_h,
clock_div => 18000000 -- 18000000
)
port map
(reset_s,cpu_arr_c(i),CLOCK_50,turn,cpu_arr_m(i),cpu_arr_e(i),cpu_arr_x(i),cpu_arr_y(i),cpu_arr_d(i),cpu_game_over(i));
collision_x: collisor
generic map
( res_x=>rx,
res_y=>ry,
w=>alien_w,
h=>alien_h,
clock_div=>100
)
port map
(CLOCK_27, cpu_arr_e(i) and shot_e_s, shot_x_s,cpu_arr_x(i),shot_y_s,cpu_arr_y(i),cpu_arr_c(i));
end generate;
----------------------------------------------------------------
----------------------------------------------------------------
-- ALIEN SHOOTER
----------------------------------------------------------------
enemy_shot_clock: clock_counter
generic map ( 27000000 )
port map ( CLOCK_27, clk_enemy_shoot );
-- Randomly select an alive enemy to shoot
PROCESS (clk_enemy_shoot)
BEGIN
if rising_edge(clk_enemy_shoot) then
choosen_enemy <= rnd_s;
enemy_shooting <= cpu_arr_e(choosen_enemy);
end if;
end process;
cpu_x_shooter: shot
generic map
(
clock_div => 1000000, -- 2500000
res_x=>rx,
res_y=>ry,
aux_x=>alien_w,
aux_y=>0,
flag_up=>'0'
)
port map
(CLOCK_50, reset_s OR shot_enemy_r_s, enemy_shooting, cpu_arr_x(choosen_enemy), cpu_arr_y(choosen_enemy),shot_enemy_e_s,shot_enemy_x_s,shot_enemy_y_s);
-- ALIEN SHOOT COLLISION WITH PLAYER
collision_x: collisor
generic map
( res_x=>rx,
res_y=>ry,
w=>player_w,
h=>player_h,
clock_div=>100
)
port map
(CLOCK_27, shot_enemy_e_s, shot_enemy_x_s, position_x_s, shot_enemy_y_s, position_y_s, shot_enemy_r_s);
shot_r_s <= '0' when cpu_arr_c = (cpu_arr_c'range => '0') else '1';
----------------------------------------------------------------
----------------------------------------------------------------
-- GAME STATE MACHINE
----------------------------------------------------------------
spaceinvaders_fsm:
PROCESS (reset,CLOCK_27)
BEGIN
IF reset = '1' THEN
reset_s <= '1';
state <= START;
ELSIF rising_edge(CLOCK_27) THEN
CASE state IS
WHEN START =>
reset_s <= '0';
IF controls(1) = '1' THEN
reset_s <= '1';
state <= PLAYING;
END IF;
WHEN PLAYING =>
reset_s <= '0';
IF game_over = '1' THEN
state <= GAME_OVER_STATE;
ELSIF game_win = '1' THEN
state <= WIN;
END IF;
WHEN GAME_OVER_STATE | WIN =>
IF controls(1) = '1' THEN
reset_s <= '1';
state <= PLAYING;
END IF;
END CASE;
END IF;
END PROCESS;
----------------------------------------------------------------
----------------------------------------------------------------
-- Live system
----------------------------------------------------------------
-- Death verification
player_death_by_alien <= '0' when cpu_game_over = (cpu_game_over'range => '0') else '1';
player_death <= shot_enemy_r_s;
-- lives: asynchronous reverse counter
process (player_death, reset_s)
begin
if reset_s = '1' then
lives <= 4;
elsif rising_edge(player_death) then
lives <= lives - 1;
end if;
end process;
-- Game win verification
game_win <= '1' when cpu_arr_e = (cpu_arr_e'range => '0') else '0';
-- Game over verification
game_over_by_lives <= '1' when lives = 0 else '0'; -- game over when lives = 0
game_over <= (player_death_by_alien OR game_over_by_lives) and not (player_exploding); -- game over when aliens reach player
-- Lives counter (shown in LEDS)
with lives select
LEDG(0) <= '0' when 0 | 1,
'1' when others;
with lives select
LEDG(1) <= '0' when 0 | 1 | 2,
'1' when others;
with lives select
LEDG(2) <= '1' when 4,
'0' when others;
----------------------------------------------------------------
----------------------------------------------------------------
-- Random number generator
----------------------------------------------------------------
rnd: random_gen
generic map ( cpu_num*cpu_lines )
port map ( clk_enemy_shoot, clock_50, rnd_s);
----------------------------------------------------------------
-- Score system
----------------------------------------------------------------
show_score: score
port map(shot_r_s, reset_s, hex_s); -- shot_r_s as clock
HEX0 <= hex_s(6 downto 0);
HEX1 <= hex_s(13 downto 7);
HEX2 <= hex_s(20 downto 14);
HEX3 <= hex_s(27 downto 21);
----------------------------------------------------------------
end architecture;
| mit | ea47b45e430fc3961707bd9b13088af6 | 0.374166 | 4.406863 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/sim/IPv4Test.vhd | 1 | 12,282 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:36:20 08/28/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Google Drive/mTC/svn/src/Ethernet/General/sim/IPv4Test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IPv4Tx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY IPv4Test IS
END IPv4Test;
ARCHITECTURE behavior OF IPv4Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IPv4Tx
PORT(
ethTxClk : IN std_logic;
ethTxRst : IN std_logic;
ipPacketLength : IN std_logic_vector(15 downto 0);
ipPacketId : IN std_logic_vector(15 downto 0);
ipMoreFragments : IN std_logic;
ipFragOffset : IN std_logic_vector(12 downto 0);
ipProtocol : IN std_logic_vector(7 downto 0);
ipSrcAddr : IN IpAddrType;
ipDstAddr : IN IpAddrType;
ipData : IN std_logic_vector(31 downto 0);
ipDataValid : IN std_logic;
ipDataReady : OUT std_logic;
ethTxDataIn : OUT std_logic_vector(7 downto 0);
ethTxDataValid : OUT std_logic;
ethTxDataLastByte : OUT std_logic;
ethTxDataReady : IN std_logic
);
END COMPONENT;
--Inputs
signal ethTxClk : std_logic := '0';
signal ethTxRst : std_logic := '0';
signal ipPacketLength : std_logic_vector(15 downto 0) := x"0020";
signal ipPacketId : std_logic_vector(15 downto 0) := x"A5B6";
signal ipMoreFragments : std_logic := '0';
signal ipFragOffset : std_logic_vector(12 downto 0) := (others => '0');
signal ipProtocol : std_logic_vector(7 downto 0) := IPV4_PROTO_UDP_C;
signal ipSrcAddr : IpAddrType := IP_ADDR_DEFAULT_C;
signal ipDstAddr : IpAddrType := (3 => x"c0", 2 => x"a8", 1 => x"01", 0 => x"02");
signal ipData : std_logic_vector(31 downto 0) := (others => '0');
signal ipDataValid : std_logic := '0';
signal ethTxDataReady : std_logic := '1';
--Outputs
signal ipDataReady : std_logic;
signal ethTxDataIn : std_logic_vector(7 downto 0);
signal ethTxDataValid : std_logic;
signal ethTxDataLastByte : std_logic;
-- UDP signals
signal udpData : slv(31 downto 0);
signal udpDataValid : sl;
signal udpDataReady : sl;
signal udpLength : slv(15 downto 0);
signal udpReq : sl;
signal udpAck : sl;
-- Signals for ARP interfacing
signal arpTxSenderMac : MacAddrType;
signal arpTxSenderIp : IpAddrType;
signal arpTxTargetMac : MacAddrType;
signal arpTxTargetIp : IpAddrType;
signal arpTxOp : slv(15 downto 0);
signal arpTxReq : sl;
signal arpTxAck : sl;
signal arpRxOp : slv(15 downto 0) := x"0001";
signal arpRxSenderMac : MacAddrType := (5 => x"08", 4 => x"00", 3 => x"27", 2 => x"C9", 1 => x"88", 0 => x"19");
signal arpRxSenderIp : IpAddrType := (3 => x"C0", 2 => x"A8", 1 => x"01", 0 => x"02");
signal arpRxTargetMac : MacAddrType := MAC_ADDR_DEFAULT_C;
signal arpRxTargetIp : IpAddrType := IP_ADDR_DEFAULT_C;
signal arpRxValid : sl;
signal macTxData : EthMacDataType;
-- User Data signals
signal userData : slv(31 downto 0);
signal userDataValid : sl;
signal userDataLast : sl := '0';
signal userDataReady : sl;
-- Clock period definitions
constant ethTxClk_period : time := 8 ns;
BEGIN
U_EthTx : entity work.EthTx
port map (
-- 125 MHz clock and reset
ethClk => ethTxClk,
ethRst => ethTxRst,
-- Addressing
macAddr => MAC_ADDR_DEFAULT_C,
-- Connection to GT
macData => macTxData,
-- Connection to upper level ARP
arpTxSenderMac => arpTxSenderMac,
arpTxSenderIp => arpTxSenderIp,
arpTxTargetMac => arpTxTargetMac,
arpTxTargetIp => arpTxTargetIp,
arpTxOp => arpTxOp,
arpTxReq => arpTxReq,
arpTxAck => arpTxAck,
-- Connection to IPv4 interface
ipTxData => ethTxDataIn,
ipTxDataValid => ethTxDataValid,
ipTxDataLastByte => ethTxDataLastByte,
ipTxDataReady => ethTxDataReady
);
-- ARP requester
----------------------------
-- Higher level protocols --
----------------------------
-- ARP : respond to ARP requests based on our IPs
U_ArpResponder : entity work.ArpResponder
port map (
-- 125 MHz ethernet clock in
ethClk => ethTxClk,
ethRst => ethTxRst,
-- Local MAC/IP settings
macAddress => MAC_ADDR_DEFAULT_C,
ipAddresses => (others => IP_ADDR_DEFAULT_C),
-- Connection to ARP RX
arpRxOp => arpRxOp,
arpRxSenderMac => arpRxSenderMac,
arpRxSenderIp => arpRxSenderIp,
arpRxTargetMac => arpRxTargetMac,
arpRxTargetIp => arpRxTargetIp,
arpRxValid => arpRxValid,
-- Connection to ARP TX
arpTxSenderMac => arpTxSenderMac,
arpTxSenderIp => arpTxSenderIp,
arpTxTargetMac => arpTxTargetMac,
arpTxTargetIp => arpTxTargetIp,
arpTxOp => arpTxOp,
arpTxReq => arpTxReq,
arpTxAck => arpTxAck
);
-- Instantiate the Unit Under Test (UUT)
U_IPV4TX : IPv4Tx
port map (
ethTxClk => ethTxClk,
ethTxRst => ethTxRst,
ipPacketLength => ipPacketLength,
ipPacketId => ipPacketId,
ipMoreFragments => ipMoreFragments,
ipFragOffset => ipFragOffset,
ipProtocol => ipProtocol,
ipSrcAddr => ipSrcAddr,
ipDstAddr => ipDstAddr,
ipData => ipData,
ipDataValid => ipDataValid,
ipDataReady => ipDataReady,
ethTxDataIn => ethTxDataIn,
ethTxDataValid => ethTxDataValid,
ethTxDataLastByte => ethTxDataLastByte,
ethTxDataReady => ethTxDataReady
);
U_UdpTxFragmenter : entity work.UdpTxFragmenter
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethTxClk,
ethTxRst => ethTxRst,
-- Header data
ipPacketLength => ipPacketLength,
ipPacketId => ipPacketId,
ipMoreFragments => ipMoreFragments,
ipFragOffset => ipFragOffset,
ipProtocol => ipProtocol,
-- User data to be sent
udpData => udpData,
udpDataValid => udpDataValid,
udpDataReady => udpDataReady,
udpLength => udpLength,
udpReq => udpReq,
udpAck => udpAck,
-- Interface to IPv4 frame block
ipData => ipData,
ipDataValid => ipDataValid,
ipDataReady => ipDataReady
);
U_UdpBufferTx : entity work.UdpBufferTx
port map (
-- User clock and reset (for writes to FIFO)
userClk => ethTxClk,
userRst => ethTxRst,
-- 125 MHz clock and reset (for reads from FIFO, interface to Eth blocks)
ethTxClk => ethTxClk,
ethTxRst => ethTxRst,
-- User data interfaces
userData => userData,
userDataValid => userDataValid,
userDataLast => userDataLast,
userDataReady => userDataReady,
-- UDP settings
udpSrcPort => x"B00B",
udpDstPort => x"ABBA",
-- Inputs for calculating checksums
ipSrcAddr => arpRxTargetIp,
ipDstAddr => arpRxSenderIp,
-- UDP fragmenter interfaces
udpData => udpData,
udpDataValid => udpDataValid,
udpDataReady => udpDataReady,
udpLength => udpLength,
udpReq => udpReq,
udpAck => udpAck
);
U_TpGenTx : entity work.TpGenTx
generic map (
NUM_WORDS_G => 1000
)
port map (
-- User clock and reset
userClk => ethTxClk,
userRst => ethTxRst,
-- Connection to user logic
userTxData => userData,
userTxDataValid => userDataValid,
userTxDataLast => userDataLast,
userTxDataReady => userDataReady
);
-- Clock process definitions
ethTxClk_process : process
begin
ethTxClk <= '0';
wait for ethTxClk_period/2;
ethTxClk <= '1';
wait for ethTxClk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
ethTxRst <= '1';
wait for 100 ns;
ethTxRst <= '0';
wait for ethTxClk_period*10;
-- insert stimulus here
wait;
end process;
process(ethTxClk)
variable arpCount : slv(31 downto 0) := x"00000000";
variable count : slv(31 downto 0) := x"00000000";
variable done : sl := '0';
begin
if rising_edge(ethTxClk) then
if ethTxRst = '1' then
-- userData <= (others => '0') after 1 ns;
-- userDataValid <= '0' after 1 ns;
arpRxValid <= '0' after 1 ns;
done := '0';
else
if (arpCount = 10 or arpCount = 400) then
arpRxValid <= '1' after 1 ns;
else
arpRxValid <= '0' after 1 ns;
end if;
arpCount := arpCount + 1;
-- userDataLast <= '0' after 1 ns;
if arpCount > 100 then
if count < 1000 then
if count = 999 then
-- userDataLast <= '1' after 1 ns;
end if;
if userDataReady = '1' then
count := count + 1;
end if;
else
done := '1';
end if;
-- userDataValid <= not(done) after 1 ns;
-- userData <= count after 1 ns;
else
-- userDataValid <= '0';
end if;
end if;
end if;
end process;
-- process(ethTxClk)
-- variable count : slv(31 downto 0) := x"00000000";
-- variable done : sl := '0';
-- begin
-- if rising_edge(ethTxClk) then
-- if ethTxRst = '1' then
-- udpData <= (others => '0');
-- udpDataValid <= '0';
-- udpLength <= conv_std_logic_vector(8000,udpLength'length);
-- arpRxValid <= '0';
-- done := '0';
-- else
-- if (count = 2) then
-- arpRxValid <= '1';
-- else
-- arpRxValid <= '0';
-- end if;
-- udpData <= count;
-- udpDataValid <= not(done);
-- udpReq <= not(done);
-- if udpDataReady = '1' then
-- count := count + 1;
-- end if;
-- if (udpAck = '1') then
-- done := '1';
-- end if;
-- end if;
-- end if;
-- end process;
END;
| lgpl-2.1 | 194305eb0ab3cf7e3cf9d14827bc6361 | 0.527194 | 4.788304 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/controllers/collisor.vhd | 1 | 1,494 | library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
entity collisor is
generic
(
res_x : integer := 15; --
res_y : integer := 15; --
w : integer := 13; --
h : integer := 6; --
clock_div : integer := 100
);
port
(
clock : in std_logic;
enable_i : in std_logic;
position_x1,
position_x2 : in integer range 0 to res_x;
position_y1,
position_y2 : in integer range 0 to res_y;
collision_o : out std_logic
);
end entity;
architecture behavior of collisor is
signal clock_slow : std_logic;
begin
-- Divisor de clock
clock_division: clock_counter
generic map ( clock_div )
port map ( clock, clock_slow );
process(clock_slow, enable_i, position_x1, position_y1, position_x2, position_y2)
begin
if enable_i = '0' then
collision_o <= '0';
elsif rising_edge(clock_slow) then
collision_o <= '0';
if (position_x1 >= position_x2)
and (position_x1 < position_x2 + w)
and (position_y1 >= position_y2)
and (position_y1 <= position_y2 + h) then
collision_o <= '1';
end if;
end if;
end process;
end architecture;
| mit | 8a60ce4966810eab5ad0ac5b7b2450ce | 0.472557 | 3.782278 | false | false | false | false |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/trace_cntrl_1_2/hdl/vhdl/trace_cntrl_mul_32s_32s_32_7.vhd | 4 | 3,069 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(32 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(32 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(32 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(32 - 1 downto 0);
signal buff1 : std_logic_vector(32 - 1 downto 0);
signal buff2 : std_logic_vector(32 - 1 downto 0);
signal buff3 : std_logic_vector(32 - 1 downto 0);
signal buff4 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff4;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity trace_cntrl_mul_32s_32s_32_7 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of trace_cntrl_mul_32s_32s_32_7 is
component trace_cntrl_mul_32s_32s_32_7_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
trace_cntrl_mul_32s_32s_32_7_MulnS_0_U : component trace_cntrl_mul_32s_32s_32_7_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| bsd-3-clause | 945dbb8f7da6a691986cc9c124b89177 | 0.548387 | 3.264894 | false | false | false | false |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/dvi2rgb_v1_6/src/dvi2rgb.vhd | 3 | 11,118 | -------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kEdidFileName : string := "900p_edid.txt"; -- Select EDID file to use
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(0); -- green is channel 1
pData(15 downto 8) <= pDataIn(1); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => kEdidFileName) -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
| bsd-3-clause | a2fc1529ffd83d57e0394b352091700d | 0.606584 | 4.552826 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/io/kbd_input.vhd | 1 | 3,269 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lib;
USE lib.io.all;
entity kbd_input is
port
(
clock_i : in std_logic;
reset_i : in std_logic;
hold_i : in std_logic;
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
shot_o : buffer std_logic;
move_o : buffer std_logic;
control_o : buffer std_logic_vector(2 downto 0)
);
end;
architecture struct of kbd_input is
component kbdex_ctrl
generic(
clkfreq : integer
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
lights : in std_logic_vector(2 downto 0); -- lights(Caps, Nun, Scroll)
key_on : out std_logic_vector(2 downto 0);
key_code : out std_logic_vector(47 downto 0)
);
end component;
signal CLOCKHZ, resetn : std_logic;
signal keys : std_logic_vector(31 downto 0);
signal control_s1, control_s2 : std_logic_vector(2 downto 0);
signal lights : std_logic_vector(2 downto 0);
begin
resetn <= reset_i;
kbd_ctrl : kbdex_ctrl generic map(24000) port map(
PS2_DAT, PS2_CLK, clock_i, hold_i, resetn, lights,
open, key_code(31 downto 0) => keys
);
-- Clock divider
process(clock_i)
constant F_HZ : integer := 5;
constant DIVIDER : integer := 24000000/F_HZ;
variable count : integer range 0 to DIVIDER := 0;
begin
if rising_edge(clock_i) then
if count < DIVIDER / 2 then
CLOCKHZ <= '1';
else
CLOCKHZ <= '0';
end if;
if count = DIVIDER then
count := 0;
end if;
count := count + 1;
end if;
end process;
---------------------------------------------
-- MUX FOR KEYBOARD CONTROL --
-- NUMERIC KEYPAD:
-- 4: Move left
-- 5: Shoot
-- 6: Move right
-- SPACE: Shoot
-- This component can handle two commands at
-- the same time, such as a movement key and
-- a shooting key.
---------------------------------------------
-- MUX for the first pressed key
with keys(15 downto 0) select
control_s1 <=
"001" when "0000000001110100", -- Right
"010" when "0000000001110011", -- Shoot
"010" when "0000000000101001", -- Shoot
"100" when "0000000001101011", -- Left
"000" when others;
-- MUX for the second pressed key
with keys(31 downto 16) select
control_s2 <=
"001" when "0000000001110100", -- Right
"010" when "0000000001110011", -- Shoot
"010" when "0000000000101001", -- Shoot
"100" when "0000000001101011", -- Left
"000" when others;
shot_o <= control_s1(1) or control_s2(1); -- Shot
move_o <= (control_s1(2) or control_s1(0)) xor (control_s2(2) or control_s2(0)); -- Movement
control_o <= control_s1 xor control_s2; -- Controls
end struct;
| mit | 5260562335c73822eb2afcb400ef181e | 0.510248 | 3.624169 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.vhd | 1 | 111,054 | --*****************************************************************************
-- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1.5
-- \ \ Application : MIG
-- / / Filename : ddr_phy_top.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Jan 31 2012
-- \___\/\___\
--
--Device : 7 Series
--Design Name : DDR3 SDRAM
--Purpose : Top level memory interface block. Instantiates a clock
-- and reset generator, the memory controller, the phy and
-- the user interface blocks.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mig_7series_v4_0_ddr_phy_top is
generic (
TCQ : integer := 100; -- Register delay (simulation only)
DDR3_VDD_OP_VOLT : string := "135"; -- Voltage mode used for DDR3
AL : string := "0"; -- Additive Latency option
BANK_WIDTH : integer := 3; -- # of bank bits
BURST_MODE : string := "8"; -- Burst length
BURST_TYPE : string := "SEQ"; -- Burst type
CA_MIRROR : string := "OFF"; -- C/A mirror opt for DDR3 dual rank
CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory
CL : integer := 5;
COL_WIDTH : integer := 12; -- column address width
CS_WIDTH : integer := 1; -- # of unique CS outputs
CKE_WIDTH : integer := 1; -- # of cke outputs
CWL : integer := 5;
DM_WIDTH : integer := 8; -- # of DM (data mask)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH))
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DRAM_TYPE : string := "DDR3";
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
MASTER_PHY_CTL : integer := 0; -- The bank number where master PHY_CONTROL resides
LP_DDR_CK_WIDTH : integer := 2;
-- Hard PHY parameters
PHYCTL_CMD_FIFO : string := "FALSE";
-- five fields, one per possible I/O bank, 4 bits in each field,
-- 1 per lane data=1/ctl=0
DATA_CTL_B0 : std_logic_vector(3 downto 0) := X"c";
DATA_CTL_B1 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B2 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B3 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B4 : std_logic_vector(3 downto 0) := X"f";
-- defines the byte lanes in I/O banks being used in the interface
-- 1- Used, 0- Unused
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- defines the bit lanes in I/O banks being used in the interface. Each
-- = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
ADDR_MAP : std_logic_vector(191 downto 0) := X"000000000000000000000000000000000000000000000000";
BANK_MAP : std_logic_vector(35 downto 0) := X"000000000";
CAS_MAP : std_logic_vector(11 downto 0) := X"000";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
CKE_ODT_AUX : string := "FALSE";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000000";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"000";
WE_MAP : std_logic_vector(11 downto 0) := X"000";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DATA0_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA1_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
-- This parameter must be set based on memory clock frequency
-- It must be set to 4 for frequencies above 533 MHz?? (undecided)
-- and set to 2 for 533 MHz and below
PRE_REV3ES : string := "OFF"; -- Delay O/Ps using Phaser_Out fine dly
nCK_PER_CLK : integer := 2; -- # of memory CKs per fabric CLK
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
ADDR_CMD_MODE : string := "1T"; -- ADDR/CTRL timing: "2T", "1T"
BANK_TYPE : string := "HP_IO"; -- # = "HP_LP", "HR_LP", "DEFAULT"
DATA_IO_PRIM_TYPE : string := "DEFAULT"; -- # = "HP_LP", "HR_LP", "DEFAULT"
DATA_IO_IDLE_PWRDWN : string := "ON"; -- # = "ON" or "OFF"
IODELAY_GRP : string := "IODELAY_MIG";
FPGA_SPEED_GRADE : integer := 1;
IBUF_LPWR_MODE : string := "OFF"; -- input buffer low power option
OUTPUT_DRV : string := "HIGH"; -- to calib_top
REG_CTRL : string := "OFF"; -- to calib_top
RTT_NOM : string := "60"; -- to calib_top
RTT_WR : string := "120"; -- to calib_top
tCK : integer := 2500; -- pS
tRFC : integer := 110000; -- pS
tREFI : integer := 7800000; -- pS
DDR2_DQSN_ENABLE : string := "YES"; -- Enable differential DQS for DDR2
WRLVL : string := "OFF"; -- to calib_top
DEBUG_PORT : string := "OFF"; -- to calib_top
RANKS : integer := 4;
ODT_WIDTH : integer := 1;
ROW_WIDTH : integer := 16; -- DRAM address bus width
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- calibration Address. The address given below will be used for calibration
-- read and write operations.
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000"; -- Calibration row address
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000"; -- Calibration column address
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000"; -- Calibration bank address
-- Simulation /debug options
SIM_BYPASS_INIT_CAL : string := "OFF";
-- Parameter used to force skipping
-- or abbreviation of initialization
-- and calibration. Overrides
-- SIM_INIT_OPTION, SIM_CAL_OPTION,
-- and disables various other blocks
--parameter SIM_INIT_OPTION = "SKIP_PU_DLY", -- Skip various init steps
--parameter SIM_CAL_OPTION = "NONE", -- Skip various calib steps
REFCLK_FREQ : real := 200.0; -- IODELAY ref clock freq (MHz)
USE_CS_PORT : integer := 1; -- Support chip select output
USE_DM_PORT : integer := 1; -- Support data mask output
USE_ODT_PORT : integer := 1; -- Support ODT output
RD_PATH_REG : integer := 0; -- optional registers in the read path
-- to MC for timing improvement.
-- =1 enabled, = 0 disabled
IDELAY_ADJ : string := "ON"; -- ON: IDELAY-1, OFF: No change
FINE_PER_BIT : string := "ON"; -- ON: Use per bit calib for complex rdlvl
CENTER_COMP_MODE : string := "ON"; -- ON: use PI stg2 tap compensation
PI_VAL_ADJ : string := "ON"; -- ON: PI stg2 tap -1 for centering
TAPSPERKCLK : integer := 56;
SKIP_CALIB : string := "FALSE"; -- skip calibration define
POC_USE_METASTABLE_SAMP : string := "FALSE";
FPGA_VOLT_TYPE : string := "N"
);
port (
clk : in std_logic; -- Fabric logic clock
-- To MC, calib_top, hard PHY
clk_div2 : in std_logic; -- mem_refclk divided by 2 for PI indec
rst_div2 : in std_logic; -- reset in clk_div2 domain
clk_ref : in std_logic; -- Idelay_ctrl reference clock
-- To hard PHY (external source)
freq_refclk : in std_logic; -- To hard PHY for Phasers
mem_refclk : in std_logic; -- Memory clock to hard PHY
pll_lock : in std_logic; -- System PLL lock signal
sync_pulse : in std_logic; -- 1/N sync pulse used to
-- synchronize all PHASERS
mmcm_ps_clk : in std_logic;
poc_sample_pd : in std_logic;
error : in std_logic; -- Support for TG error detect
rst_tg_mc : out std_logic; -- Support for TG error detect
device_temp : in std_logic_vector(11 downto 0);
tempmon_sample_en : in std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
rst : in std_logic;
iddr_rst : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
-- From MC
mc_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
mc_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
mc_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
mc_reset_n : in std_logic;
mc_odt : in std_logic_vector(1 downto 0);
mc_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
-- AUX - For ODT and CKE assertion during reads and writes
mc_aux_out0 : in std_logic_vector(3 downto 0);
mc_aux_out1 : in std_logic_vector(3 downto 0);
mc_cmd_wren : in std_logic;
mc_ctl_wren : in std_logic;
mc_cmd : in std_logic_vector(2 downto 0);
mc_cas_slot : in std_logic_vector(1 downto 0);
mc_data_offset : in std_logic_vector(5 downto 0);
mc_data_offset_1 : in std_logic_vector(5 downto 0);
mc_data_offset_2 : in std_logic_vector(5 downto 0);
mc_rank_cnt : in std_logic_vector(1 downto 0);
-- Write
mc_wrdata_en : in std_logic;
mc_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
mc_wrdata_mask : in std_logic_vector((2*nCK_PER_CLK*(DQ_WIDTH/8))-1 downto 0);
idle : in std_logic;
-- DDR bus signals
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
calib_tap_req : out std_logic;
calib_tap_load : in std_logic;
calib_tap_addr : in std_logic_vector(6 downto 0);
calib_tap_val : in std_logic_vector(7 downto 0);
calib_tap_load_done : in std_logic;
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_poc : out std_logic_vector(1023 downto 0);
-- FIFO status flags
phy_mc_ctl_full : out std_logic;
phy_mc_cmd_full : out std_logic;
phy_mc_data_full : out std_logic;
-- Calibration status and resultant outputs
init_calib_complete : out std_logic;
init_wrcal_complete : out std_logic;
calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
phy_rddata_valid : out std_logic;
phy_rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
ref_dll_lock : out std_logic;
rst_phaser_ref : in std_logic;
dbg_rd_data_offset : out std_logic_vector(6*RANKS-1 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0);
prbs_final_dqs_tap_cnt_r : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0)
);
end entity;
architecture arch_ddr_phy_top of mig_7series_v4_0_ddr_phy_top is
-- function to OR the bits in a vectored signal
function OR_BR (inp_var: std_logic_vector)
return std_logic is
variable temp: std_logic := '0';
begin
for idx in inp_var'range loop
temp := temp or inp_var(idx);
end loop;
return temp;
end function;
-- Calculate number of slots in the system
function CALC_nSLOTS return integer is
begin
if (OR_BR(SLOT_1_CONFIG) = '1') then
return (2);
else
return (1);
end if;
end function;
function SIM_INIT_OPTION_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("SKIP_INIT");
elsif (SIM_BYPASS_INIT_CAL = "FAST" or
SIM_BYPASS_INIT_CAL = "SIM_FULL") then
return ("SKIP_PU_DLY");
else
return ("NONE");
end if;
end function;
function SIM_CAL_OPTION_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("SKIP_CAL");
elsif (SIM_BYPASS_INIT_CAL = "FAST") then
return ("FAST_CAL");
elsif (SIM_BYPASS_INIT_CAL = "SIM_FULL" or
SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL") then
return ("FAST_WIN_DETECT");
else
return ("NONE");
end if;
end function;
function CALC_WRLVL_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("OFF");
else
return (WRLVL);
end if;
end function;
function HIGHEST_BANK_W return integer is
begin
if (BYTE_LANES_B4 /= "0000") then
return (5);
elsif (BYTE_LANES_B3 /= "0000") then
return (4);
elsif (BYTE_LANES_B2 /= "0000") then
return (3);
elsif (BYTE_LANES_B1 /= "0000") then
return (2);
else
return (1);
end if;
end function;
function HIGHEST_LANE_B0_W return integer is
begin
if (BYTE_LANES_B0(3) = '1') then
return (4);
elsif (BYTE_LANES_B0(2) = '1') then
return (3);
elsif (BYTE_LANES_B0(1) = '1') then
return (2);
elsif (BYTE_LANES_B0(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B1_W return integer is
begin
if (BYTE_LANES_B1(3) = '1') then
return (4);
elsif (BYTE_LANES_B1(2) = '1') then
return (3);
elsif (BYTE_LANES_B1(1) = '1') then
return (2);
elsif (BYTE_LANES_B1(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B2_W return integer is
begin
if (BYTE_LANES_B2(3) = '1') then
return (4);
elsif (BYTE_LANES_B2(2) = '1') then
return (3);
elsif (BYTE_LANES_B2(1) = '1') then
return (2);
elsif (BYTE_LANES_B2(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B3_W return integer is
begin
if (BYTE_LANES_B3(3) = '1') then
return (4);
elsif (BYTE_LANES_B3(2) = '1') then
return (3);
elsif (BYTE_LANES_B3(1) = '1') then
return (2);
elsif (BYTE_LANES_B3(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B4_W return integer is
begin
if (BYTE_LANES_B4(3) = '1') then
return (4);
elsif (BYTE_LANES_B4(2) = '1') then
return (3);
elsif (BYTE_LANES_B4(1) = '1') then
return (2);
elsif (BYTE_LANES_B4(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_W return integer is
begin
if (HIGHEST_LANE_B4_W /= 0) then
return (HIGHEST_LANE_B4_W+16);
elsif (HIGHEST_LANE_B3_W /= 0) then
return (HIGHEST_LANE_B3_W+12);
elsif (HIGHEST_LANE_B2_W /= 0) then
return (HIGHEST_LANE_B2_W+8);
elsif (HIGHEST_LANE_B1_W /= 0) then
return (HIGHEST_LANE_B1_W+4);
else
return (HIGHEST_LANE_B0_W);
end if;
end function;
function N_CTL_LANES_B0 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B0(idx)) = '1' and BYTE_LANES_B0(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B1 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B1(idx)) = '1' and BYTE_LANES_B1(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B2 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B2(idx)) = '1' and BYTE_LANES_B2(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B3 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B3(idx)) = '1' and BYTE_LANES_B3(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B4 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B4(idx)) = '1' and BYTE_LANES_B4(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function CTL_BANK_B0 return std_logic is
begin
if ((not(DATA_CTL_B0(0)) = '1' and BYTE_LANES_B0(0) = '1') or
(not(DATA_CTL_B0(1)) = '1' and BYTE_LANES_B0(1) = '1') or
(not(DATA_CTL_B0(2)) = '1' and BYTE_LANES_B0(2) = '1') or
(not(DATA_CTL_B0(3)) = '1' and BYTE_LANES_B0(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B1 return std_logic is
begin
if ((not(DATA_CTL_B1(0)) = '1' and BYTE_LANES_B1(0) = '1') or
(not(DATA_CTL_B1(1)) = '1' and BYTE_LANES_B1(1) = '1') or
(not(DATA_CTL_B1(2)) = '1' and BYTE_LANES_B1(2) = '1') or
(not(DATA_CTL_B1(3)) = '1' and BYTE_LANES_B1(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B2 return std_logic is
begin
if ((not(DATA_CTL_B2(0)) = '1' and BYTE_LANES_B2(0) = '1') or
(not(DATA_CTL_B2(1)) = '1' and BYTE_LANES_B2(1) = '1') or
(not(DATA_CTL_B2(2)) = '1' and BYTE_LANES_B2(2) = '1') or
(not(DATA_CTL_B2(3)) = '1' and BYTE_LANES_B2(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B3 return std_logic is
begin
if ((not(DATA_CTL_B3(0)) = '1' and BYTE_LANES_B3(0) = '1') or
(not(DATA_CTL_B3(1)) = '1' and BYTE_LANES_B3(1) = '1') or
(not(DATA_CTL_B3(2)) = '1' and BYTE_LANES_B3(2) = '1') or
(not(DATA_CTL_B3(3)) = '1' and BYTE_LANES_B3(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B4 return std_logic is
begin
if ((not(DATA_CTL_B4(0)) = '1' and BYTE_LANES_B4(0) = '1') or
(not(DATA_CTL_B4(1)) = '1' and BYTE_LANES_B4(1) = '1') or
(not(DATA_CTL_B4(2)) = '1' and BYTE_LANES_B4(2) = '1') or
(not(DATA_CTL_B4(3)) = '1' and BYTE_LANES_B4(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_W return std_logic_vector is
variable ctl_bank_var : std_logic_vector(2 downto 0);
begin
if (CTL_BANK_B0 = '1') then
ctl_bank_var := "000";
elsif (CTL_BANK_B1 = '1') then
ctl_bank_var := "001";
elsif (CTL_BANK_B2 = '1') then
ctl_bank_var := "010";
elsif (CTL_BANK_B3 = '1') then
ctl_bank_var := "011";
elsif (CTL_BANK_B4 = '1') then
ctl_bank_var := "100";
else
ctl_bank_var := "000";
end if;
return (ctl_bank_var);
end function;
function ODD_PARITY (inp_var : std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for idx in inp_var'range loop
tmp := tmp XOR inp_var(idx);
end loop;
return tmp;
end ODD_PARITY;
-- Calculate number of slots in the system
constant nSLOTS : integer := CALC_nSLOTS;
constant CLK_PERIOD : integer := tCK * nCK_PER_CLK;
-- Parameter used to force skipping or abbreviation of initialization
-- and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
-- disables various other blocks depending on the option selected
-- This option should only be used during simulation. In the case of
-- the "SKIP" option, the testbench used should also not be modeling
-- propagation delays.
-- Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
-- "NONE" = options determined by the individual parameter settings
-- "SIM_FULL" = skip power-up delay. FULL calibration performed without
-- averaging algorithm turned ON during window detection.
-- "SKIP" = skip power-up delay. Skip calibration not yet supported.
-- "FAST" = skip power-up delay, and calibrate (read leveling, write
-- leveling, and phase detector) only using one DQS group, and
-- apply the results to all other DQS groups.
constant SIM_INIT_OPTION : string := SIM_INIT_OPTION_W;
constant SIM_CAL_OPTION : string := SIM_CAL_OPTION_W;
constant WRLVL_W : string := CALC_WRLVL_W;
constant HIGHEST_BANK : integer := HIGHEST_BANK_W;
-- constant HIGHEST_LANE_B0 = HIGHEST_LANE_B0_W;
-- constant HIGHEST_LANE_B1 = HIGHEST_LANE_B1_W;
-- constant HIGHEST_LANE_B2 = HIGHEST_LANE_B2_W;
-- constant HIGHEST_LANE_B3 = HIGHEST_LANE_B3_W;
-- constant HIGHEST_LANE_B4 = HIGHEST_LANE_B4_W;
constant HIGHEST_LANE : integer := HIGHEST_LANE_W;
constant N_CTL_LANES : integer := N_CTL_LANES_B0 + N_CTL_LANES_B1 + N_CTL_LANES_B2 + N_CTL_LANES_B3 + N_CTL_LANES_B4;
-- Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
-- This should be the case since the PLL should be placed adjacent
-- to the same IO Bank as Ck/Addr/Cmd and Control
constant CTL_BANK : std_logic_vector(2 downto 0):= CTL_BANK_W;
function CTL_BYTE_LANE_W return std_logic_vector is
variable ctl_byte_lane_var: std_logic_vector(7 downto 0);
begin
if (N_CTL_LANES = 4) then
ctl_byte_lane_var := "11100100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00100100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00110100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00111000";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00111001";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1'))) then
ctl_byte_lane_var := "00000100";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001100";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001110";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00001001";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001101";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00001000";
else
ctl_byte_lane_var := "11100100";
end if;
return (ctl_byte_lane_var);
end function;
constant CTL_BYTE_LANE : std_logic_vector(7 downto 0):= CTL_BYTE_LANE_W;
function PI_DIV2_INCDEC_FUN return string is
begin
if (DRAM_TYPE = "DDR2") then
return ("FALSE");
elsif ((FPGA_VOLT_TYPE = "L") and (nCK_PER_CLK = 4)) then
return ("TRUE");
else
return ("FALSE");
end if;
end function;
constant PI_DIV2_INCDEC : string := PI_DIV2_INCDEC_FUN;
component mig_7series_v4_0_ddr_mc_phy_wrapper is
generic (
TCQ : integer;
tCK : integer;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN :string;
IODELAY_GRP : string;
FPGA_SPEED_GRADE : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
BANK_WIDTH : integer;
CKE_WIDTH : integer;
CS_WIDTH : integer;
CK_WIDTH : integer;
CWL : integer;
DDR2_DQSN_ENABLE : string;
DM_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
RANKS : integer;
ODT_WIDTH : integer;
REG_CTRL : string;
ROW_WIDTH : integer;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IBUF_LPWR_MODE : string;
LP_DDR_CK_WIDTH : integer;
PHYCTL_CMD_FIFO : string;
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
HIGHEST_BANK : integer;
HIGHEST_LANE : integer;
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SIM_CAL_OPTION : string;
MASTER_PHY_CTL : integer;
DRAM_WIDTH : integer;
POC_USE_METASTABLE_SAMP : string;
PI_DIV2_INCDEC : string
);
port (
rst : in std_logic;
iddr_rst : in std_logic;
clk : in std_logic;
clk_div2 : in std_logic;
freq_refclk : in std_logic;
mem_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
mmcm_ps_clk : in std_logic;
idelayctrl_refclk : in std_logic;
phy_cmd_wr_en : in std_logic;
phy_data_wr_en : in std_logic;
phy_ctl_wd : in std_logic_vector(31 downto 0);
phy_ctl_wr : in std_logic;
phy_if_empty_def : in std_logic;
phy_if_reset : in std_logic;
data_offset_1 : in std_logic_vector(5 downto 0);
data_offset_2 : in std_logic_vector(5 downto 0);
aux_in_1 : in std_logic_vector(3 downto 0);
aux_in_2 : in std_logic_vector(3 downto 0);
idelaye2_init_val : out std_logic_vector(4 downto 0);
oclkdelay_init_val : out std_logic_vector(5 downto 0);
if_empty : out std_logic;
phy_ctl_full : out std_logic;
phy_cmd_full : out std_logic;
phy_data_full : out std_logic;
phy_pre_data_a_full : out std_logic;
ddr_clk : out std_logic_vector(CK_WIDTH*LP_DDR_CK_WIDTH-1 downto 0);
phy_mc_go : out std_logic;
phy_write_calib : in std_logic;
phy_read_calib : in std_logic;
calib_in_common : in std_logic;
calib_sel : in std_logic_vector(5 downto 0);
calib_zero_inputs : in std_logic_vector(HIGHEST_BANK-1 downto 0);
calib_zero_ctrl : in std_logic_vector(HIGHEST_BANK-1 downto 0);
po_fine_enable : in std_logic_vector(2 downto 0);
po_coarse_enable : in std_logic_vector(2 downto 0);
po_fine_inc : in std_logic_vector(2 downto 0);
po_coarse_inc : in std_logic_vector(2 downto 0);
po_counter_load_en : in std_logic;
po_counter_read_en : in std_logic;
po_sel_fine_oclk_delay : in std_logic_vector(2 downto 0);
po_counter_load_val : in std_logic_vector(8 downto 0);
po_counter_read_val : out std_logic_vector(8 downto 0);
pi_counter_read_val : out std_logic_vector(5 downto 0);
pi_rst_dqs_find : in std_logic_vector(HIGHEST_BANK-1 downto 0);
pi_fine_enable : in std_logic;
pi_fine_inc : in std_logic;
pi_counter_load_en : in std_logic;
pi_counter_load_val : in std_logic_vector(5 downto 0);
idelay_ce : in std_logic;
idelay_inc : in std_logic;
idelay_ld : in std_logic;
idle : in std_logic;
pi_phase_locked : out std_logic;
pi_phase_locked_all : out std_logic;
pi_dqs_found : out std_logic;
pi_dqs_found_all : out std_logic;
pi_dqs_out_of_range : out std_logic;
phy_init_data_sel : in std_logic;
mux_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
mux_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
mux_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
mux_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_odt : in std_logic_vector(1 downto 0);
mux_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
parity_in : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
mux_wrdata_mask : in std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
mux_reset_n : in std_logic;
rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_parity : out std_logic;
ddr_ras_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_pi_counter_read_en : in std_logic;
ref_dll_lock : out std_logic;
rst_phaser_ref : in std_logic;
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
byte_sel_cnt : in std_logic_vector(DQS_CNT_WIDTH downto 0);
fine_delay_incdec_pb : in std_logic_vector(DRAM_WIDTH-1 downto 0);
fine_delay_sel : in std_logic;
pd_out : out std_logic
);
end component mig_7series_v4_0_ddr_mc_phy_wrapper;
component mig_7series_v4_0_ddr_calib_top is
generic (
TCQ : integer;
nCK_PER_CLK : integer;
tCK : integer;
DDR3_VDD_OP_VOLT : string ;
CLK_PERIOD : integer;
N_CTL_LANES : integer;
DRAM_TYPE : string;
PRBS_WIDTH : integer;
HIGHEST_LANE : integer;
HIGHEST_BANK : integer;
BANK_TYPE : string;
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
CTL_BYTE_LANE : std_logic_vector(7 downto 0);
CTL_BANK : std_logic_vector(2 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
BANK_WIDTH : integer;
CA_MIRROR : string;
COL_WIDTH : integer;
nCS_PER_RANK : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_WIDTH : integer;
ROW_WIDTH : integer;
RANKS : integer;
CS_WIDTH : integer;
CKE_WIDTH : integer;
DDR2_DQSN_ENABLE : string;
PER_BIT_DESKEW : string;
NUM_DQSFOUND_CAL : integer := 1020;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
AL : string;
TEST_AL : string := "0";
ADDR_CMD_MODE : string;
BURST_MODE : string;
BURST_TYPE : string;
nCL : integer;
nCWL : integer;
tRFC : integer;
tREFI : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string;
USE_ODT_PORT : integer;
WRLVL : string;
PRE_REV3ES : string;
SIM_INIT_OPTION : string;
SIM_CAL_OPTION : string;
CKE_ODT_AUX : string;
IDELAY_ADJ : string;
FINE_PER_BIT : string;
CENTER_COMP_MODE : string;
PI_VAL_ADJ : string;
TAPSPERKCLK : integer;
DEBUG_PORT : string;
SKIP_CALIB : string;
POC_USE_METASTABLE_SAMP : string;
PI_DIV2_INCDEC : string
);
port (
clk : in std_logic;
rst : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
phy_ctl_ready : in std_logic;
phy_ctl_full : in std_logic;
phy_cmd_full : in std_logic;
phy_data_full : in std_logic;
write_calib : out std_logic;
read_calib : out std_logic;
calib_ctl_wren : out std_logic;
calib_cmd_wren : out std_logic;
calib_seq : out std_logic_vector(1 downto 0);
calib_aux_out : out std_logic_vector(3 downto 0);
calib_cke : out std_logic_vector(nCK_PER_CLK-1 downto 0);
calib_odt : out std_logic_vector(1 downto 0);
calib_cmd : out std_logic_vector(2 downto 0);
calib_wrdata_en : out std_logic;
calib_rank_cnt : out std_logic_vector(1 downto 0);
calib_cas_slot : out std_logic_vector(1 downto 0);
calib_data_offset_0 : out std_logic_vector(5 downto 0);
calib_data_offset_1 : out std_logic_vector(5 downto 0);
calib_data_offset_2 : out std_logic_vector(5 downto 0);
phy_address : out std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
phy_bank : out std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
phy_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
phy_ras_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_cas_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_we_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_reset_n : out std_logic;
calib_sel : out std_logic_vector(5 downto 0);
calib_in_common : out std_logic;
calib_zero_inputs : out std_logic_vector(HIGHEST_BANK-1 downto 0);
calib_zero_ctrl : out std_logic_vector(HIGHEST_BANK-1 downto 0);
phy_if_empty_def : out std_logic;
phy_if_reset : out std_logic;
pi_phaselocked : in std_logic;
pi_phase_locked_all : in std_logic;
pi_found_dqs : in std_logic;
pi_dqs_found_all : in std_logic;
pi_dqs_found_lanes : in std_logic_vector(HIGHEST_LANE-1 downto 0);
pi_counter_read_val : in std_logic_vector(5 downto 0);
pi_rst_stg1_cal : out std_logic_vector(HIGHEST_BANK-1 downto 0);
pi_en_stg2_f : out std_logic;
pi_stg2_f_incdec : out std_logic;
pi_stg2_load : out std_logic;
pi_stg2_reg_l : out std_logic_vector(5 downto 0);
idelay_ce : out std_logic;
idelay_inc : out std_logic;
idelay_ld : out std_logic;
po_sel_stg2stg3 : out std_logic_vector(2 downto 0);
po_stg2_c_incdec : out std_logic_vector(2 downto 0);
po_en_stg2_c : out std_logic_vector(2 downto 0);
po_stg2_f_incdec : out std_logic_vector(2 downto 0);
po_en_stg2_f : out std_logic_vector(2 downto 0);
po_counter_load_en : out std_logic;
po_counter_read_val : in std_logic_vector(8 downto 0);
device_temp : in std_logic_vector(11 downto 0);
tempmon_sample_en : in std_logic;
phy_if_empty : in std_logic;
idelaye2_init_val : in std_logic_vector(4 downto 0);
oclkdelay_init_val : in std_logic_vector(5 downto 0);
tg_err : in std_logic;
rst_tg_mc : out std_logic;
phy_wrdata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
dlyval_dq : out std_logic_vector(5*RANKS*DQ_WIDTH-1 downto 0);
phy_rddata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
phy_rddata_valid : out std_logic;
calib_writes : out std_logic;
init_calib_complete : out std_logic;
init_wrcal_complete : out std_logic;
pi_phase_locked_err : out std_logic;
pi_dqsfound_err : out std_logic;
wrcal_err : out std_logic;
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
poc_sample_pd : in std_logic;
calib_tap_req : out std_logic;
calib_tap_load : in std_logic;
calib_tap_addr : in std_logic_vector(6 downto 0);
calib_tap_val : in std_logic_vector(7 downto 0);
calib_tap_load_done : in std_logic;
dbg_pi_phaselock_start : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_sel_all_idel_cpt : in std_logic;
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_poc : out std_logic_vector(1023 downto 0);
prbs_final_dqs_tap_cnt_r : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
byte_sel_cnt : out std_logic_vector(DQS_CNT_WIDTH downto 0);
fine_delay_incdec_pb : out std_logic_vector(DRAM_WIDTH-1 downto 0);
fine_delay_sel : out std_logic;
pd_out : in std_logic
);
end component mig_7series_v4_0_ddr_calib_top;
signal phy_din : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
signal phy_dout : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
signal ddr_cmd_ctl_data : std_logic_vector(HIGHEST_LANE*12-1 downto 0);
signal aux_out : std_logic_vector((((HIGHEST_LANE+3)/4)*4)-1 downto 0);
signal ddr_clk : std_logic_vector(CK_WIDTH * LP_DDR_CK_WIDTH-1 downto 0);
signal phy_mc_go : std_logic;
signal phy_ctl_full : std_logic;
signal phy_cmd_full : std_logic;
signal phy_data_full : std_logic;
signal phy_pre_data_a_full : std_logic;
signal if_empty : std_logic;
signal phy_write_calib : std_logic;
signal phy_read_calib : std_logic;
signal rst_stg1_cal : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal calib_sel : std_logic_vector(5 downto 0);
signal calib_in_common : std_logic;
signal calib_zero_inputs : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal calib_zero_ctrl : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal pi_phase_locked : std_logic;
signal pi_phase_locked_all : std_logic;
signal pi_found_dqs : std_logic;
signal pi_dqs_found_all : std_logic;
signal pi_dqs_out_of_range : std_logic;
signal pi_enstg2_f : std_logic;
signal pi_stg2_fincdec : std_logic;
signal pi_stg2_load : std_logic;
signal pi_stg2_reg_l : std_logic_vector(5 downto 0);
signal idelay_ce : std_logic;
signal idelay_inc : std_logic;
signal idelay_ld : std_logic;
signal po_sel_stg2stg3 : std_logic_vector(2 downto 0);
signal po_stg2_cincdec : std_logic_vector(2 downto 0);
signal po_enstg2_c : std_logic_vector(2 downto 0);
signal po_stg2_fincdec : std_logic_vector(2 downto 0);
signal po_enstg2_f : std_logic_vector(2 downto 0);
signal po_counter_read_val : std_logic_vector(8 downto 0);
signal pi_counter_read_val : std_logic_vector(5 downto 0);
signal phy_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal parity : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
signal phy_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
signal phy_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal phy_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_reset_n : std_logic;
signal calib_aux_out : std_logic_vector(3 downto 0);
signal calib_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal calib_odt : std_logic_vector(1 downto 0);
signal calib_ctl_wren : std_logic;
signal calib_cmd_wren : std_logic;
signal calib_wrdata_en : std_logic;
signal calib_cmd : std_logic_vector(2 downto 0);
signal calib_seq : std_logic_vector(1 downto 0);
signal calib_data_offset_0 : std_logic_vector(5 downto 0);
signal calib_data_offset_1 : std_logic_vector(5 downto 0);
signal calib_data_offset_2 : std_logic_vector(5 downto 0);
signal calib_rank_cnt : std_logic_vector(1 downto 0);
signal calib_cas_slot : std_logic_vector(1 downto 0);
signal mux_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
signal mux_aux_out : std_logic_vector(3 downto 0);
signal aux_out_map : std_logic_vector(3 downto 0);
signal mux_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
signal mux_cmd : std_logic_vector(2 downto 0);
signal mux_cmd_wren : std_logic;
signal mux_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal mux_ctl_wren : std_logic;
signal mux_cas_slot : std_logic_vector(1 downto 0);
signal mux_data_offset : std_logic_vector(5 downto 0);
signal mux_data_offset_1 : std_logic_vector(5 downto 0);
signal mux_data_offset_2 : std_logic_vector(5 downto 0);
signal mux_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_rank_cnt : std_logic_vector(1 downto 0);
signal mux_reset_n : std_logic;
signal mux_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal mux_wrdata_mask : std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
signal mux_wrdata_en : std_logic;
signal mux_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_odt : std_logic_vector(1 downto 0);
signal phy_if_empty_def : std_logic;
signal phy_if_reset : std_logic;
signal phy_init_data_sel : std_logic;
signal rd_data_map : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal phy_rddata_valid_w : std_logic;
signal rddata_valid_reg : std_logic;
signal rd_data_reg : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal idelaye2_init_val : std_logic_vector(4 downto 0);
signal oclkdelay_init_val : std_logic_vector(5 downto 0);
signal mc_cs_n_temp : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal calib_rd_data_offset_i0 : std_logic_vector(6*RANKS-1 downto 0);
signal init_wrcal_complete_i : std_logic;
signal phy_ctl_wd_i : std_logic_vector(31 downto 0);
signal po_counter_load_en : std_logic;
signal parity_0_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_1_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_2_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_3_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal dbg_pi_dqs_found_lanes_phy4lanes_i : std_logic_vector(11 downto 0);
signal all_zeros : std_logic_vector(8 downto 0):= (others => '0');
signal byte_sel_cnt : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal fine_delay_incdec_pb : std_logic_vector(DRAM_WIDTH-1 downto 0);
signal fine_delay_sel : std_logic;
signal pd_out : std_logic;
-- 3-stage synchronizer registers
signal pi_fine_enable : std_logic;
signal pi_fine_inc : std_logic;
signal pi_counter_load_en : std_logic;
signal pi_counter_load_val : std_logic_vector(5 downto 0);
signal pi_rst_dqs_find : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal pi_enstg2_f_div2r1 : std_logic;
signal pi_enstg2_f_div2r2 : std_logic;
signal pi_enstg2_f_div2r3 : std_logic;
signal pi_stg2_fincdec_div2r1 : std_logic;
signal pi_stg2_fincdec_div2r2 : std_logic;
signal pi_stg2_fincdec_div2r3 : std_logic;
signal pi_stg2_load_div2r1 : std_logic;
signal pi_stg2_load_div2r2 : std_logic;
signal pi_stg2_load_div2r3 : std_logic;
signal rst_stg1_cal_div2r1 : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal rst_stg1_cal_div2r2 : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal pi_stg2_reg_l_div2r1 : std_logic_vector(5 downto 0);
signal pi_stg2_reg_l_div2r2 : std_logic_vector(5 downto 0);
signal pi_stg2_reg_l_div2r3 : std_logic_vector(5 downto 0);
signal pi_dqs_find_rst : std_logic_vector(HIGHEST_BANK-1 downto 0);
attribute ASYNC_REG : string;
attribute ASYNC_REG of pi_fine_enable : signal is "TRUE";
attribute ASYNC_REG of pi_fine_inc : signal is "TRUE";
attribute ASYNC_REG of pi_counter_load_en : signal is "TRUE";
attribute ASYNC_REG of pi_counter_load_val : signal is "TRUE";
attribute ASYNC_REG of pi_rst_dqs_find : signal is "TRUE";
attribute ASYNC_REG of pi_enstg2_f_div2r1 : signal is "TRUE";
attribute ASYNC_REG of pi_enstg2_f_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_enstg2_f_div2r3 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_fincdec_div2r1 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_fincdec_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_fincdec_div2r3 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_load_div2r1 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_load_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_load_div2r3 : signal is "TRUE";
attribute ASYNC_REG of rst_stg1_cal_div2r1 : signal is "TRUE";
attribute ASYNC_REG of rst_stg1_cal_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_reg_l_div2r1 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_reg_l_div2r2 : signal is "TRUE";
attribute ASYNC_REG of pi_stg2_reg_l_div2r3 : signal is "TRUE";
attribute ASYNC_REG of pi_dqs_find_rst : signal is "TRUE";
signal pi_stg2_fine_enable, pi_stg2_fine_enable_r1 : std_logic;
signal pi_stg2_fine_inc, pi_stg2_fine_inc_r1 : std_logic;
signal pi_stg2_load_en, pi_stg2_load_en_r1 : std_logic;
signal pi_stg2_load_val : std_logic_vector(5 downto 0);
begin
--***************************************************************************
dbg_rddata_valid <= rddata_valid_reg;
dbg_rddata <= rd_data_reg;
dbg_rd_data_offset <= calib_rd_data_offset_i0;
calib_rd_data_offset_0 <= calib_rd_data_offset_i0;
dbg_pi_phaselocked_done <= pi_phase_locked_all;
dbg_po_counter_read_val <= po_counter_read_val;
dbg_pi_counter_read_val <= pi_counter_read_val;
dbg_pi_dqs_found_lanes_phy4lanes <= dbg_pi_dqs_found_lanes_phy4lanes_i;
init_wrcal_complete <= init_wrcal_complete_i;
--***************************************************************************
--***************************************************************************
-- Clock domain crossing from DIV4 to DIV2 for Phaser_In stage2 incdec
--***************************************************************************
div2_incdec : if (PI_DIV2_INCDEC = "TRUE") generate
-- 3-stage synchronizer
process (clk_div2) begin
if (rising_edge(clk_div2)) then
-- Phaser_In fine enable
pi_enstg2_f_div2r1 <= pi_enstg2_f after (TCQ) * 1 ps;
pi_enstg2_f_div2r2 <= pi_enstg2_f_div2r1 after (TCQ) * 1 ps;
pi_enstg2_f_div2r3 <= pi_enstg2_f_div2r2 after (TCQ) * 1 ps;
-- Phaser_In fine incdec
pi_stg2_fincdec_div2r1 <= pi_stg2_fincdec after (TCQ) * 1 ps;
pi_stg2_fincdec_div2r2 <= pi_stg2_fincdec_div2r1 after (TCQ) * 1 ps;
pi_stg2_fincdec_div2r3 <= pi_stg2_fincdec_div2r2 after (TCQ) * 1 ps;
-- Phaser_In stage2 load
pi_stg2_load_div2r1 <= pi_stg2_load after (TCQ) * 1 ps;
pi_stg2_load_div2r2 <= pi_stg2_load_div2r1 after (TCQ) * 1 ps;
pi_stg2_load_div2r3 <= pi_stg2_load_div2r2 after (TCQ) * 1 ps;
-- Phaser_In stage2 load value
pi_stg2_reg_l_div2r1 <= pi_stg2_reg_l after (TCQ) * 1 ps;
pi_stg2_reg_l_div2r2 <= pi_stg2_reg_l_div2r1 after (TCQ) * 1 ps;
pi_stg2_reg_l_div2r3 <= pi_stg2_reg_l_div2r2 after (TCQ) * 1 ps;
-- Phaser_In reset DQSFOUND
rst_stg1_cal_div2r1 <= rst_stg1_cal after (TCQ) * 1 ps;
rst_stg1_cal_div2r2 <= rst_stg1_cal_div2r1 after (TCQ) * 1 ps;
pi_dqs_find_rst <= rst_stg1_cal_div2r2 after (TCQ) * 1 ps;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
pi_stg2_fine_enable_r1 <= pi_stg2_fine_enable after (TCQ) * 1 ps;
pi_stg2_fine_inc_r1 <= pi_stg2_fine_inc after (TCQ) * 1 ps;
pi_stg2_load_en_r1 <= pi_stg2_load_en after (TCQ) * 1 ps;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
if ((rst_div2 = '1') or (pi_stg2_fine_enable = '1') or (pi_stg2_fine_enable_r1 = '1')) then
pi_stg2_fine_enable <= '0' after (TCQ) * 1 ps;
elsif (pi_enstg2_f_div2r3 = '1') then
pi_stg2_fine_enable <= '1' after (TCQ) * 1 ps;
end if;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
if ((rst_div2 = '1') or (pi_stg2_fine_inc = '1') or (pi_stg2_fine_inc_r1 = '1')) then
pi_stg2_fine_inc <= '0' after (TCQ) * 1 ps;
elsif (pi_stg2_fincdec_div2r3 = '1') then
pi_stg2_fine_inc <= '1' after (TCQ) * 1 ps;
end if;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
if ((rst_div2 = '1') or (pi_stg2_load_en = '1') or (pi_stg2_load_en_r1 = '1')) then
pi_stg2_load_en <= '0' after (TCQ) * 1 ps;
elsif (pi_stg2_load_div2r3 = '1') then
pi_stg2_load_en <= '1' after (TCQ) * 1 ps;
end if;
end if;
end process;
process (clk_div2) begin
if (rising_edge(clk_div2)) then
if ((rst_div2 = '1') or (pi_stg2_load_en = '1') or (pi_stg2_load_en_r1 = '1')) then
pi_stg2_load_val <= (others => '0') after (TCQ) * 1 ps;
elsif (pi_stg2_load_div2r3 = '1') then
pi_stg2_load_val <= pi_stg2_reg_l_div2r3 after (TCQ) * 1 ps;
end if;
end if;
end process;
pi_fine_enable <= pi_stg2_fine_enable;
pi_fine_inc <= pi_stg2_fine_inc;
pi_counter_load_en <= pi_stg2_load_en;
pi_counter_load_val <= pi_stg2_load_val;
pi_rst_dqs_find <= pi_dqs_find_rst;
end generate div2_incdec;
div4_incdec : if (PI_DIV2_INCDEC = "FALSE") generate
pi_fine_enable <= pi_enstg2_f;
pi_fine_inc <= pi_stg2_fincdec;
pi_counter_load_en <= pi_stg2_load;
pi_counter_load_val <= pi_stg2_reg_l;
pi_rst_dqs_find <= rst_stg1_cal;
end generate div4_incdec;
--***************************************************************************
clock_gen : for i in 0 to (CK_WIDTH-1) generate
ddr_ck(i) <= ddr_clk(LP_DDR_CK_WIDTH * i);
ddr_ck_n(i) <= ddr_clk((LP_DDR_CK_WIDTH * i) + 1);
end generate;
--***************************************************************************
-- During memory initialization and calibration the calibration logic drives
-- the memory signals. After calibration is complete the memory controller
-- drives the memory signals.
-- Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
--***************************************************************************
cs_rdimm : if((REG_CTRL = "ON") and (DRAM_TYPE = "DDR3") and (RANKS = 1) and (nCS_PER_RANK = 2)) generate
cs_rdimm_gen: for v in 0 to (CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK)-1 generate
cs_rdimm_gen_i : if((v mod (CS_WIDTH*nCS_PER_RANK)) = 0) generate
mc_cs_n_temp(v) <= mc_cs_n(v) ;
end generate;
cs_rdimm_gen_j : if(not((v mod (CS_WIDTH*nCS_PER_RANK)) = 0)) generate
mc_cs_n_temp(v) <= '1' ;
end generate;
end generate;
end generate;
cs_others : if(not(REG_CTRL = "ON") or not(DRAM_TYPE = "DDR3") or not(RANKS = 1) or not(nCS_PER_RANK = 2)) generate
mc_cs_n_temp <= mc_cs_n ;
end generate;
mux_wrdata <= mc_wrdata when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_wrdata;
mux_wrdata_mask <= mc_wrdata_mask when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else (others => '0');
mux_address <= mc_address when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_address;
mux_bank <= mc_bank when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_bank;
mux_cs_n <= mc_cs_n_temp when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cs_n;
mux_ras_n <= mc_ras_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_ras_n;
mux_cas_n <= mc_cas_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cas_n;
mux_we_n <= mc_we_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_we_n;
mux_reset_n <= mc_reset_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_reset_n;
mux_aux_out <= mc_aux_out0 when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_aux_out;
mux_odt <= mc_odt when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_odt;
mux_cke <= mc_cke when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_cke;
mux_cmd_wren <= mc_cmd_wren when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cmd_wren;
mux_ctl_wren <= mc_ctl_wren when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_ctl_wren;
mux_wrdata_en <= mc_wrdata_en when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_wrdata_en;
mux_cmd <= mc_cmd when (phy_init_data_sel ='1' or init_wrcal_complete_i ='1') else calib_cmd;
mux_cas_slot <= mc_cas_slot when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cas_slot;
mux_data_offset <= mc_data_offset when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_0;
mux_data_offset_1 <= mc_data_offset_1 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_1;
mux_data_offset_2 <= mc_data_offset_2 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_2;
-- Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
mux_rank_cnt <= "00";
-- Assigning cke & odt for DDR2 & DDR3
-- No changes for DDR3 & DDR2 dual rank
-- DDR2 single rank systems might potentially need 3 odt signals.
-- Aux_out[2] will have the odt toggled by phy and controller
-- wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
-- all of the three odt bits or some of them might be used.
-- mapping done in mc_phy_wrapper module
aux_out_gen : if(CKE_ODT_AUX = "TRUE") generate
aux_out_map <= (mux_aux_out(1) & mux_aux_out(1) & mux_aux_out(1) &
mux_aux_out(0)) when ((DRAM_TYPE = "DDR2") and
(RANKS = 1)) else
mux_aux_out;
end generate;
wo_aux_out_gen : if(not(CKE_ODT_AUX = "TRUE")) generate
aux_out_map <= "0000";
end generate;
init_calib_complete <= phy_init_data_sel;
phy_mc_ctl_full <= phy_ctl_full;
phy_mc_cmd_full <= phy_cmd_full;
phy_mc_data_full <= phy_pre_data_a_full;
--***************************************************************************
-- Generate parity for DDR3 RDIMM.
--***************************************************************************
gen_ddr3_parity : if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
gen_ddr3_parity_4by1: if (nCK_PER_CLK = 4) generate
parity_0_wire <= (mux_address((ROW_WIDTH*4)-1 downto ROW_WIDTH*3) &
mux_bank((BANK_WIDTH*4)-1 downto BANK_WIDTH*3) &
mux_cas_n(3) & mux_ras_n(3) & mux_we_n(3));
parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
mux_ras_n(0) & mux_we_n(0));
parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
parity_3_wire <= (mux_address((ROW_WIDTH*3)-1 downto ROW_WIDTH*2) &
mux_bank((BANK_WIDTH*3)-1 downto BANK_WIDTH*2) &
mux_cas_n(2) & mux_ras_n(2) & mux_we_n(2));
process (clk)
begin
if (clk'event and clk = '1') then
parity(0) <= ODD_PARITY(parity_0_wire) after (TCQ) * 1 ps;
end if;
end process;
process (mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
begin
parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
parity(2) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
parity(3) <= ODD_PARITY(parity_3_wire) after (TCQ) * 1 ps;
end process;
end generate;
gen_ddr3_parity_2by1: if ( not(nCK_PER_CLK = 4)) generate
parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
mux_ras_n(0) & mux_we_n(0));
parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
end if;
end process;
process(mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
begin
parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
end process;
end generate;
end generate;
gen_ddr3_noparity : if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
gen_ddr3_noparity_4by1 : if (nCK_PER_CLK = 4) generate
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= '0' after (TCQ)*1 ps;
parity(1) <= '0' after (TCQ)*1 ps;
parity(2) <= '0' after (TCQ)*1 ps;
parity(3) <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr3_noparity_2by1 : if (not(nCK_PER_CLK = 4)) generate
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= '0' after (TCQ)*1 ps;
parity(1) <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
end generate;
--***************************************************************************
-- Code for optional register stage in read path to MC for timing
--***************************************************************************
RD_REG_TIMING : if(RD_PATH_REG = 1) generate
process (clk)
begin
if (clk'event and clk='1') then
rddata_valid_reg <= phy_rddata_valid_w after (TCQ)*1 ps;
rd_data_reg <= rd_data_map after (TCQ)*1 ps;
end if;
end process;
end generate;
RD_REG_NO_TIMING : if( not(RD_PATH_REG = 1)) generate
process (phy_rddata_valid_w, rd_data_map)
begin
rddata_valid_reg <= phy_rddata_valid_w;
rd_data_reg <= rd_data_map;
end process;
end generate;
phy_rddata_valid <= rddata_valid_reg;
phy_rd_data <= rd_data_reg;
--***************************************************************************
-- Hard PHY and accompanying bit mapping logic
--***************************************************************************
phy_ctl_wd_i <= ("00000" & mux_cas_slot & calib_seq & mux_data_offset &
mux_rank_cnt & "000" & aux_out_map & "00000" & mux_cmd);
u_ddr_mc_phy_wrapper : mig_7series_v4_0_ddr_mc_phy_wrapper
generic map (
TCQ => TCQ,
tCK => tCK,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP => IODELAY_GRP,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
DATA_IO_IDLE_PWRDWN=> DATA_IO_IDLE_PWRDWN,
nCK_PER_CLK => nCK_PER_CLK,
nCS_PER_RANK => nCS_PER_RANK,
BANK_WIDTH => BANK_WIDTH,
CKE_WIDTH => CKE_WIDTH,
CS_WIDTH => CS_WIDTH,
CK_WIDTH => CK_WIDTH,
CWL => CWL,
DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
DM_WIDTH => DM_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
REG_CTRL => REG_CTRL,
ROW_WIDTH => ROW_WIDTH,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
LP_DDR_CK_WIDTH => LP_DDR_CK_WIDTH,
PHYCTL_CMD_FIFO => PHYCTL_CMD_FIFO,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
HIGHEST_BANK => HIGHEST_BANK,
HIGHEST_LANE => HIGHEST_LANE,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CKE_ODT_AUX => CKE_ODT_AUX,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
SIM_CAL_OPTION => SIM_CAL_OPTION,
MASTER_PHY_CTL => MASTER_PHY_CTL,
DRAM_WIDTH => DRAM_WIDTH,
POC_USE_METASTABLE_SAMP => POC_USE_METASTABLE_SAMP,
PI_DIV2_INCDEC => PI_DIV2_INCDEC
)
port map (
rst => rst,
iddr_rst => iddr_rst,
clk => clk,
clk_div2 => clk_div2,
-- For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
-- For memory frequencies below 400 MHz mem_refclk = mem_refclk and
-- freq_refclk = 2x or 4x mem_refclk such that it remains in the
-- 400~1066 MHz range
freq_refclk => freq_refclk,
mem_refclk => mem_refclk,
pll_lock => pll_lock,
sync_pulse => sync_pulse,
mmcm_ps_clk => mmcm_ps_clk,
idelayctrl_refclk => clk_ref,
phy_cmd_wr_en => mux_cmd_wren,
phy_data_wr_en => mux_wrdata_en,
-- phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
-- DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
-- AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
-- The fields ACTPRE, and BankCount are only used
-- when the hard PHY counters are used by the MC.
phy_ctl_wd => phy_ctl_wd_i,
phy_ctl_wr => mux_ctl_wren,
phy_if_empty_def => phy_if_empty_def,
phy_if_reset => phy_if_reset,
data_offset_1 => mux_data_offset_1,
data_offset_2 => mux_data_offset_2,
aux_in_1 => aux_out_map,
aux_in_2 => aux_out_map,
idelaye2_init_val => idelaye2_init_val,
oclkdelay_init_val => oclkdelay_init_val,
if_empty => if_empty,
phy_ctl_full => phy_ctl_full,
phy_cmd_full => phy_cmd_full,
phy_data_full => phy_data_full,
phy_pre_data_a_full => phy_pre_data_a_full,
ddr_clk => ddr_clk,
phy_mc_go => phy_mc_go,
phy_write_calib => phy_write_calib,
phy_read_calib => phy_read_calib,
calib_in_common => calib_in_common,
calib_sel => calib_sel,
calib_zero_inputs => calib_zero_inputs,
calib_zero_ctrl => calib_zero_ctrl,
po_fine_enable => po_enstg2_f,
po_coarse_enable => po_enstg2_c,
po_fine_inc => po_stg2_fincdec,
po_coarse_inc => po_stg2_cincdec,
po_counter_load_en => po_counter_load_en,
po_counter_read_en => '1',
po_sel_fine_oclk_delay => po_sel_stg2stg3,
po_counter_load_val => all_zeros,
po_counter_read_val => po_counter_read_val,
pi_counter_read_val => pi_counter_read_val,
pi_rst_dqs_find => pi_rst_dqs_find,
pi_fine_enable => pi_fine_enable,
pi_fine_inc => pi_fine_inc,
pi_counter_load_en => pi_counter_load_en,
pi_counter_load_val => pi_counter_load_val,
idelay_ce => idelay_ce,
idelay_inc => idelay_inc,
idelay_ld => idelay_ld,
idle => idle,
pi_phase_locked => pi_phase_locked,
pi_phase_locked_all => pi_phase_locked_all,
pi_dqs_found => pi_found_dqs,
pi_dqs_found_all => pi_dqs_found_all,
-- Currently not being used. May be used in future if periodic reads
-- become a requirement. This output could also be used to signal a
-- catastrophic failure in read capture and the need for re-cal
pi_dqs_out_of_range => pi_dqs_out_of_range,
phy_init_data_sel => phy_init_data_sel,
mux_address => mux_address,
mux_bank => mux_bank,
mux_cas_n => mux_cas_n,
mux_cs_n => mux_cs_n,
mux_ras_n => mux_ras_n,
mux_odt => mux_odt,
mux_cke => mux_cke,
mux_we_n => mux_we_n,
parity_in => parity,
mux_wrdata => mux_wrdata,
mux_wrdata_mask => mux_wrdata_mask,
mux_reset_n => mux_reset_n,
rd_data => rd_data_map,
ddr_addr => ddr_addr,
ddr_ba => ddr_ba,
ddr_cas_n => ddr_cas_n,
ddr_cke => ddr_cke,
ddr_cs_n => ddr_cs_n,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
ddr_parity => ddr_parity,
ddr_ras_n => ddr_ras_n,
ddr_we_n => ddr_we_n,
ddr_reset_n => ddr_reset_n,
ddr_dq => ddr_dq,
ddr_dqs => ddr_dqs,
ddr_dqs_n => ddr_dqs_n,
dbg_pi_counter_read_en => '1',
ref_dll_lock => ref_dll_lock,
rst_phaser_ref => rst_phaser_ref,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes_i,
byte_sel_cnt => byte_sel_cnt,
fine_delay_incdec_pb => fine_delay_incdec_pb,
fine_delay_sel => fine_delay_sel,
pd_out => pd_out
);
--***************************************************************************
-- Soft memory initialization and calibration logic
--***************************************************************************
u_ddr_calib_top : mig_7series_v4_0_ddr_calib_top
generic map (
TCQ => TCQ,
DDR3_VDD_OP_VOLT => DDR3_VDD_OP_VOLT,
nCK_PER_CLK => nCK_PER_CLK,
tCK => tCK,
CLK_PERIOD => CLK_PERIOD,
N_CTL_LANES => N_CTL_LANES,
DRAM_TYPE => DRAM_TYPE,
PRBS_WIDTH => 8,
HIGHEST_LANE => HIGHEST_LANE,
HIGHEST_BANK => HIGHEST_BANK,
BANK_TYPE => BANK_TYPE,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
DQS_BYTE_MAP => DQS_BYTE_MAP,
CTL_BYTE_LANE => CTL_BYTE_LANE,
CTL_BANK => CTL_BANK,
SLOT_1_CONFIG => SLOT_1_CONFIG,
BANK_WIDTH => BANK_WIDTH,
CA_MIRROR => CA_MIRROR,
COL_WIDTH => COL_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_WIDTH => DRAM_WIDTH,
ROW_WIDTH => ROW_WIDTH,
RANKS => RANKS,
CS_WIDTH => CS_WIDTH,
CKE_WIDTH => CKE_WIDTH,
DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
PER_BIT_DESKEW => "OFF",
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
AL => AL,
ADDR_CMD_MODE => ADDR_CMD_MODE,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
nCL => CL,
nCWL => CWL,
tRFC => tRFC,
tREFI => tREFI,
OUTPUT_DRV => OUTPUT_DRV,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
RTT_WR => RTT_WR,
USE_ODT_PORT => USE_ODT_PORT,
WRLVL => WRLVL_W,
PRE_REV3ES => PRE_REV3ES,
SIM_INIT_OPTION => SIM_INIT_OPTION,
SIM_CAL_OPTION => SIM_CAL_OPTION,
CKE_ODT_AUX => CKE_ODT_AUX,
DEBUG_PORT => DEBUG_PORT,
IDELAY_ADJ => IDELAY_ADJ,
FINE_PER_BIT => FINE_PER_BIT,
CENTER_COMP_MODE => CENTER_COMP_MODE,
PI_VAL_ADJ => PI_VAL_ADJ,
TAPSPERKCLK => TAPSPERKCLK,
SKIP_CALIB => SKIP_CALIB,
POC_USE_METASTABLE_SAMP => POC_USE_METASTABLE_SAMP,
PI_DIV2_INCDEC => PI_DIV2_INCDEC
)
port map (
clk => clk,
rst => rst,
slot_0_present => slot_0_present,
slot_1_present => slot_1_present,
-- PHY Control Block and IN_FIFO status
phy_ctl_ready => phy_mc_go,
phy_ctl_full => '0',
phy_cmd_full => '0',
phy_data_full => '0',
-- hard PHY calibration modes
write_calib => phy_write_calib,
read_calib => phy_read_calib,
-- Signals from calib logic to be MUXED with MC
-- signals before sending to hard PHY
calib_ctl_wren => calib_ctl_wren,
calib_cmd_wren => calib_cmd_wren,
calib_seq => calib_seq,
calib_aux_out => calib_aux_out,
calib_odt => calib_odt,
calib_cke => calib_cke,
calib_cmd => calib_cmd,
calib_wrdata_en => calib_wrdata_en,
calib_rank_cnt => calib_rank_cnt,
calib_cas_slot => calib_cas_slot,
calib_data_offset_0 => calib_data_offset_0,
calib_data_offset_1 => calib_data_offset_1,
calib_data_offset_2 => calib_data_offset_2,
phy_address => phy_address,
phy_bank => phy_bank,
phy_cs_n => phy_cs_n,
phy_ras_n => phy_ras_n,
phy_cas_n => phy_cas_n,
phy_we_n => phy_we_n,
phy_reset_n => phy_reset_n,
-- DQS count and ck/addr/cmd to be mapped to calib_sel
-- based on parameter that defines placement of ctl lanes
-- and DQS byte groups in each bank. When phy_write_calib
-- is de-asserted calib_sel should select CK/addr/cmd/ctl.
calib_sel => calib_sel,
calib_in_common => calib_in_common,
calib_zero_inputs => calib_zero_inputs,
calib_zero_ctrl => calib_zero_ctrl,
phy_if_empty_def => phy_if_empty_def,
phy_if_reset => phy_if_reset,
-- DQS Phaser_IN calibration/status signals
pi_phaselocked => pi_phase_locked,
pi_phase_locked_all => pi_phase_locked_all,
pi_found_dqs => pi_found_dqs,
pi_dqs_found_all => pi_dqs_found_all,
pi_dqs_found_lanes => dbg_pi_dqs_found_lanes_phy4lanes_i(HIGHEST_LANE-1 downto 0),
pi_rst_stg1_cal => rst_stg1_cal,
pi_en_stg2_f => pi_enstg2_f,
pi_stg2_f_incdec => pi_stg2_fincdec,
pi_stg2_load => pi_stg2_load,
pi_stg2_reg_l => pi_stg2_reg_l,
pi_counter_read_val => pi_counter_read_val,
device_temp => device_temp,
tempmon_sample_en => tempmon_sample_en,
-- IDELAY tap enable and inc signals
idelay_ce => idelay_ce,
idelay_inc => idelay_inc,
idelay_ld => idelay_ld,
-- DQS Phaser_OUT calibration/status signals
po_sel_stg2stg3 => po_sel_stg2stg3,
po_stg2_c_incdec => po_stg2_cincdec,
po_en_stg2_c => po_enstg2_c,
po_stg2_f_incdec => po_stg2_fincdec,
po_en_stg2_f => po_enstg2_f,
po_counter_load_en => po_counter_load_en,
po_counter_read_val => po_counter_read_val,
phy_if_empty => if_empty,
idelaye2_init_val => idelaye2_init_val,
oclkdelay_init_val => oclkdelay_init_val,
tg_err => error,
rst_tg_mc => rst_tg_mc,
phy_wrdata => phy_wrdata,
-- From calib logic To data IN_FIFO
-- DQ IDELAY tap value from Calib logic
-- port to be added to mc_phy by Gary
dlyval_dq => open,
-- From data IN_FIFO To Calib logic and MC/UI
phy_rddata => rd_data_map,
-- From calib logic To MC
phy_rddata_valid => phy_rddata_valid_w,
calib_rd_data_offset_0 => calib_rd_data_offset_i0,
calib_rd_data_offset_1 => calib_rd_data_offset_1,
calib_rd_data_offset_2 => calib_rd_data_offset_2,
calib_writes => open,
-- Mem Init and Calibration status To MC
init_calib_complete => phy_init_data_sel,
init_wrcal_complete => init_wrcal_complete_i,
-- Debug Error signals
pi_phase_locked_err => dbg_pi_phaselock_err,
pi_dqsfound_err => dbg_pi_dqsfound_err,
wrcal_err => dbg_wrcal_err,
-- MMCM phase shift clock control
psen => psen,
psincdec => psincdec,
psdone => psdone,
poc_sample_pd => poc_sample_pd,
-- skip calibration
calib_tap_req => calib_tap_req,
calib_tap_load => calib_tap_load,
calib_tap_addr => calib_tap_addr,
calib_tap_val => calib_tap_val,
calib_tap_load_done => calib_tap_load_done,
-- Debug Signals
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_calib_top => dbg_calib_top,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
dbg_poc => dbg_poc,
prbs_final_dqs_tap_cnt_r => prbs_final_dqs_tap_cnt_r,
dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps,
dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps,
byte_sel_cnt => byte_sel_cnt,
fine_delay_incdec_pb => fine_delay_incdec_pb,
fine_delay_sel => fine_delay_sel,
pd_out => pd_out
);
end architecture arch_ddr_phy_top;
| mit | d496056d5d4b8835722fb2b9cf849720 | 0.511931 | 3.29205 | false | false | false | false |
fumyuun/tasty | src/platform/sim/tb.vhd | 1 | 1,908 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity tb is
end entity;
architecture tb_arch of tb is
signal clk_s : std_logic;
signal rst_s : std_logic;
signal btn_s : std_logic_vector(12 downto 0);
signal js_clock_s : std_logic := '0';
signal js_latch_s : std_logic := '0';
signal js_data_s : std_logic;
signal clock_active_s : std_logic := '0';
signal snes_js_btn_s : snes_js_btn_r;
signal snes_js_bus_i_s : snes_js_bus_i_r;
signal snes_js_bus_o_s : snes_js_bus_o_r;
begin
-- up & b
btn_s <= "0000000100001";
snes_js_btn_s.up <= btn_s(0);
snes_js_btn_s.down <= btn_s(1);
snes_js_btn_s.left <= btn_s(2);
snes_js_btn_s.right <= btn_s(3);
snes_js_btn_s.a <= btn_s(4);
snes_js_btn_s.b <= btn_s(5);
snes_js_btn_s.x <= btn_s(6);
snes_js_btn_s.y <= btn_s(7);
snes_js_btn_s.l <= btn_s(8);
snes_js_btn_s.r <= btn_s(9);
snes_js_btn_s.start <= btn_s(10);
snes_js_btn_s.sel <= btn_s(11);
snes_js_bus_i_s.clock <= js_clock_s;
snes_js_bus_i_s.latch <= js_latch_s;
js_data_s <= snes_js_bus_o_s.data;
clk_s <= '0', not clk_s after 10 ns;
rst_s <= '1', '0' after 1 us;
tasty: entity work.tasty_snes
port map (
clk_i => clk_s,
snes_js_btn_i => snes_js_btn_s,
snes_js_bus_i => snes_js_bus_i_s,
snes_js_bus_o => snes_js_bus_o_s,
debug_enabled_i => '1',
btnreg_o => open
);
test_proc: process
begin
clock_active_s <= '0';
wait for 10 us;
js_latch_s <= '1';
wait for 12 us;
js_latch_s <= '0';
clock_active_s <= '1';
wait for 16*12 us;
clock_active_s <= '0';
end process;
js_clock_s <= '1' when clock_active_s = '0' else not js_clock_s after 6 us;
end architecture tb_arch;
| mit | b8c564f6903d84def0a3ebdf56b2206e | 0.533019 | 2.550802 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_ftch_queue.vhd | 1 | 41,467 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
--use axi_sg_v4_1.axi_sg_afifo_autord.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
-- Channel Control --
desc1_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
desc2_flush : in std_logic ; --
ftch1_active : in std_logic ; --
ftch2_active : in std_logic ; --
ftch1_queue_empty : out std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch1_queue_full : out std_logic ; --
ftch2_queue_full : out std_logic ; --
ftch1_pause : out std_logic ; --
ftch2_pause : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing1_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
sof_ftch_desc : in std_logic ;
m_axis1_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
--
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_64_cdma : in std_logic_vector --
(31 downto 0) ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
data_concat_tlast : in std_logic ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_aclk : in std_logic ; --
m_axis_ftch1_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch1_tvalid : out std_logic ; --
m_axis_ftch1_tready : in std_logic ; --
m_axis_ftch1_tlast : out std_logic ; --
m_axis_ftch1_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch1_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch1_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
m_axis_ftch2_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch2_tvalid : out std_logic ; --
m_axis_ftch2_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch2_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch2_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
m_axis_ftch2_tready : in std_logic ; --
m_axis_ftch2_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-- Number of words deep fifo needs to be
-- 6 is subtracted as BD address are always 16 word aligned
constant FIFO_WIDTH : integer := (128*C_ENABLE_CDMA + 97*(1-C_ENABLE_CDMA) -6);
constant C_SG_WORDS_TO_FETCH1 : integer := C_SG_WORDS_TO_FETCH + 2*C_ENABLE_MULTI_CHANNEL;
--constant FETCH_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
-- * C_SG_WORDS_TO_FETCH1));
constant FETCH_QUEUE_DEPTH : integer := 16;
-- Select between BRAM or Logic Memory Type
constant MEMORY_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG_WORDS_TO_FETCH1 > 16);
constant FETCH_QUEUE_CNT_WIDTH : integer := clog2(FETCH_QUEUE_DEPTH+1);
constant DCNT_LO_INDEX : integer := max2(1,clog2(C_SG_WORDS_TO_FETCH1)) - 1;
constant DCNT_HI_INDEX : integer := FETCH_QUEUE_CNT_WIDTH-1; -- CR616461
constant C_SG2_WORDS_TO_FETCH1 : integer := C_SG2_WORDS_TO_FETCH;
constant FETCH2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1));
-- Select between BRAM or Logic Memory Type
constant MEMORY2_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1 > 16);
constant FETCH2_QUEUE_CNT_WIDTH : integer := clog2(FETCH2_QUEUE_DEPTH+1);
constant DCNT2_LO_INDEX : integer := max2(1,clog2(C_SG2_WORDS_TO_FETCH1)) - 1;
constant DCNT2_HI_INDEX : integer := FETCH2_QUEUE_CNT_WIDTH-1; -- CR616461
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant DESC2QUEUE_VECT_WIDTH : integer := 4;
--constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
--constant DCNT_HI_INDEX : integer := (DCNT_LO_INDEX + DESC2QUEUE_VECT_WIDTH) - 1; -- CR616461
constant ZERO_COUNT : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
constant ZERO_COUNT1 : std_logic_vector(FETCH2_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tvalid_new : std_logic := '0';
signal ftch_tdata : std_logic_vector
(31 downto 0) := (others => '0');
signal ftch_tdata_new, reg1, reg2 : std_logic_vector
(FIFO_WIDTH-1 downto 0) := (others => '0');
signal ftch_tdata_new_64, reg1_64, reg2_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal ftch_tdata_new_bd, reg2_bd_64, reg1_bd_64 : std_logic_vector (31 downto 0) := (others => '0');
attribute mark_debug of ftch_tdata_new : signal is "true";
signal ftch_tlast : std_logic := '0';
signal ftch_tlast_new : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal ftch_tready_ch1 : std_logic := '0';
signal ftch_tready_ch2 : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
-- FIFO signals
signal queue_rden2 : std_logic := '0';
signal queue_rden2_new : std_logic := '0';
signal queue_wren2 : std_logic := '0';
signal queue_wren2_new : std_logic := '0';
signal queue_empty2 : std_logic := '0';
signal queue_empty2_new : std_logic := '0';
signal queue_rden : std_logic := '0';
signal queue_rden_new : std_logic := '0';
signal queue_wren : std_logic := '0';
signal queue_wren_new : std_logic := '0';
signal queue_empty : std_logic := '0';
signal queue_empty_new : std_logic := '0';
signal queue_dout_valid : std_logic := '0';
signal queue_dout2_valid : std_logic := '0';
attribute mark_debug of queue_dout_valid : signal is "true";
attribute mark_debug of queue_dout2_valid : signal is "true";
signal queue_full_new : std_logic := '0';
signal queue_full2_new : std_logic := '0';
signal queue_full, queue_full2 : std_logic := '0';
signal queue_din_new : std_logic_vector
(127 downto 0) := (others => '0');
signal queue_dout_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_dout2_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout2_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout2_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
attribute mark_debug of queue_dout_new : signal is "true";
attribute mark_debug of queue_dout2_new : signal is "true";
signal queue_dout2_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_din : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout2 : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_sinit : std_logic := '0';
signal queue_sinit2 : std_logic := '0';
signal queue_dcount_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal queue_dcount2_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal ftch_no_room : std_logic;
signal ftch_active : std_logic := '0';
attribute mark_debug of ftch_active : signal is "true";
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal sof_ftch_desc_del : std_logic;
signal sof_ftch_desc_del1 : std_logic;
signal sof_ftch_desc_pulse : std_logic;
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal xfer_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1'))then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
ftch_active <= ftch1_active or ftch2_active;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
CURRENT_BD_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(32+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_64;
CURRENT_BD_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_32;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
m_axis_ftch1_tdata_mcdma_new <= (others => '0');
m_axis_ftch2_tdata_mcdma_new <= (others => '0');
COUNTER_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
counter <= (others => '0');
elsif (m_axis_mm2s_tvalid = '1') then
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process COUNTER_PROCESS;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- TVALID MUX
-- MUX tvalid out channel port
---------------------------------------------------------------------------
CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate
begin
CDMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (63 downto 0) <= data_concat_64_cdma & data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate CDMA_FIELDS_64;
ftch_tdata_new (95 downto 0) <= data_concat;
-- BD is always 16 word aligned
ftch_tdata_new (121 downto 96) <= current_bd (31 downto 6);
end generate CDMA_FIELDS;
DMA_FIELDS : if C_ENABLE_CDMA = 0 generate
begin
DMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (31 downto 0) <= data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate DMA_FIELDS_64;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
-- BD is always 16 word aligned
ftch_tdata_new (90 downto 65) <= current_bd (31 downto 6);
end generate DMA_FIELDS;
ftch_tvalid_new <= data_concat_valid and ftch_active;
ftch_tlast_new <= data_concat_tlast and ftch_active;
GEN_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_rden_new = '1') then
queue_empty_new <= '1';
queue_full_new <= '0';
elsif (queue_wren_new = '1') then
queue_empty_new <= '0';
queue_full_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
reg1 <= (others => '0');
reg1_64 <= (others => '0');
reg1_bd_64 <= (others => '0');
elsif (queue_wren_new = '1') then
reg1 <= ftch_tdata_new;
reg1_64 <= ftch_tdata_new_64;
reg1_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
queue_dout_new <= (others => '0');
queue_dout_new_64 <= (others => '0');
queue_dout_new_bd <= (others => '0');
elsif (queue_rden_new = '1') then
queue_dout_new <= reg1;
queue_dout_new_64 <= reg1_64;
queue_dout_new_bd <= reg1_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_dout_valid = '1') then
queue_dout_valid <= '0';
elsif (queue_rden_new = '1') then
queue_dout_valid <= '1';
end if;
end if;
end process;
MCDMA_MM2S : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH1_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren_new ,
Rd_en => queue_rden_new ,
Dout => queue_dout_mcdma_new ,
Full => open, --queue_full_new ,
Empty => open, --queue_empty_new ,
Almost_full => open ,
Data_count => open, --queue_dcount_new ,
Rd_ack => open, --queue_dout_valid, --open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch1_tdata_mcdma_new <= queue_dout_mcdma_new;
end generate MCDMA_MM2S;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 generate
begin
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
end generate GEN_MM2S;
GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_rden2_new = '1') then
queue_empty2_new <= '1';
queue_full2_new <= '0';
elsif (queue_wren2_new = '1') then
queue_empty2_new <= '0';
queue_full2_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
reg2 <= (others => '0');
reg2_64 <= (others => '0');
reg2_bd_64 <= (others => '0');
elsif (queue_wren2_new = '1') then
reg2 <= ftch_tdata_new;
reg2_64 <= ftch_tdata_new_64;
reg2_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
queue_dout2_new <= (others => '0');
queue_dout2_new_64 <= (others => '0');
queue_dout2_new_bd <= (others => '0');
elsif (queue_rden2_new = '1') then
queue_dout2_new <= reg2;
queue_dout2_new_64 <= reg2_64;
queue_dout2_new_bd <= reg2_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_dout2_valid = '1') then
queue_dout2_valid <= '0';
elsif (queue_rden2_new = '1') then
queue_dout2_valid <= '1';
end if;
end if;
end process;
MCDMA_S2MM : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH2_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit2 ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren2_new ,
Rd_en => queue_rden2_new ,
Dout => queue_dout2_new ,
Full => open, --queue_full2_new ,
Empty => open, --queue_empty2_new ,
Almost_full => open ,
Data_count => queue_dcount2_new ,
Rd_ack => open, --queue_dout2_valid ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch2_tdata_mcdma_new <= queue_dcount2_new;
end generate MCDMA_S2MM;
end generate GEN_S2MM;
-----------------------------------------------------------------------
-- Internal Side
-----------------------------------------------------------------------
-- Drive tready with fifo not full
ftch_tready <= ftch_tready_ch1 or ftch_tready_ch2;
-- Following is the APP data that goes into APP FIFO
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
GEN_CH1_CTRL : if C_INCLUDE_MM2S =1 generate
begin
--queue_full_new <= '1' when (queue_dcount_new = "00100") else '0';
queue_sinit <= desc1_flush or not m_axi_sg_aresetn;
ftch_tready_ch1 <= (not queue_full and ftch1_active);
m_axis1_mm2s_tready <= ftch_tready_ch1;
-- Wr_en to APP FIFO. Data is written only when BD with SOF is fetched.
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch1_active;
-- Wr_en of BD FIFO
queue_wren_new <= not queue_full_new
and ftch_tvalid_new
and ftch1_active;
ftch1_queue_empty <= queue_empty_new;
ftch1_queue_full <= queue_full_new;
ftch1_pause <= queue_full_new;
-- RD_en of APP FIFO based on empty and tready
-- RD_EN of BD FIFO based on empty and tready
queue_rden_new <= not queue_empty_new
and m_axis_ftch1_tready;
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
m_axis_ftch1_tvalid_new <= queue_dout_valid; --not queue_empty_new and (not ch2_sg_idle);
-- below signal triggers the fetch of BD in MM2S Mngr
m_axis_ftch1_desc_available <= not queue_empty_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
FTCH_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new_bd & queue_dout_new_64 & queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64;
FTCH_FIELDS_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32;
writing1_curdesc_out <= writing_curdesc and ftch1_active;
NOCONTROL_STREAM_ASST : if C_SG_WORDS_TO_FETCH = 8 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NOCONTROL_STREAM_ASST;
end generate GEN_CH1_CTRL;
GEN_NO_CH1_CTRL : if C_INCLUDE_MM2S =0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
ftch_tready_ch1 <= '0';
m_axis1_mm2s_tready <= '0';
-- Write to fifo if it is not full and data is valid
queue_wren <= '0';
ftch1_queue_empty <= '0';
ftch1_queue_full <= '0';
ftch1_pause <= '0';
queue_rden <= '0';
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
writing1_curdesc_out <= '0';
m_axis_ftch1_tdata_new <= (others => '0');
m_axis_ftch1_tvalid_new <= '0';
m_axis_ftch1_desc_available <= '0';
end generate GEN_NO_CH1_CTRL;
GEN_CH2_CTRL : if C_INCLUDE_S2MM =1 generate
begin
queue_sinit2 <= desc2_flush or not m_axi_sg_aresetn;
ftch_tready_ch2 <= (not queue_full2_new and ftch2_active);
m_axis2_mm2s_tready <= ftch_tready_ch2;
queue_wren2 <= '0';
-- Wr_en for S2MM BD FIFO
queue_wren2_new <= not queue_full2_new
and ftch_tvalid_new
and ftch2_active;
--queue_full2_new <= '1' when (queue_dcount2_new = "00100") else '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
ftch2_queue_empty <= queue_empty2_new;
ftch2_queue_full <= queue_full2_new;
ftch2_pause <= queue_full2_new;
queue_rden2 <= '0';
-- Rd_en for S2MM BD FIFO
queue_rden2_new <= not queue_empty2_new
and m_axis_ftch2_tready;
m_axis_ftch2_tvalid <= '0';
m_axis_ftch2_tvalid_new <= queue_dout2_valid; -- not queue_empty2_new and (not ch2_sg_idle);
m_axis_ftch2_desc_available <= not queue_empty2_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
FTCH_FIELDS_64_2 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new_bd & queue_dout2_new_64 & queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64_2;
FTCH_FIELDS_32_2 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32_2;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
end generate GEN_CH2_CTRL;
GEN_NO_CH2_CTRL : if C_INCLUDE_S2MM =0 generate
begin
ftch_tready_ch2 <= '0';
m_axis2_mm2s_tready <= '0';
queue_wren2 <= '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
--ftch_queue_empty <= queue_empty; CR 621600
ftch2_queue_empty <= '0';
ftch2_queue_full <= '0';
ftch2_pause <= '0';
queue_rden2 <= '0';
m_axis_ftch2_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
m_axis_ftch2_tdata_new <= (others => '0');
m_axis_ftch2_tvalid_new <= '0';
writing2_curdesc_out <= '0';
m_axis_ftch2_desc_available <= '0';
end generate GEN_NO_CH2_CTRL;
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| mit | 059eb78e1a2ee3b3716fa9e9ff5af60e | 0.478718 | 3.683336 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Writeback.vhd | 1 | 1,774 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:37:36 11/11/2017
-- Design Name:
-- Module Name: Writeback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Writeback is
Port ( datatomenin : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
pc : in STD_LOGIC_VECTOR (31 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
datatoreg : out STD_LOGIC_VECTOR (31 downto 0));
end Writeback;
architecture Behavioral of Writeback is
COMPONENT MuxDM
PORT(
DataMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
RFSC : in STD_LOGIC_VECTOR (1 downto 0);
DWR : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a999: std_logic_vector(31 downto 0);
begin ints_muxdatamemory: MuxDM PORT MAP(
DataMem => datatomenin,
AluResult => aluresultin,
PC => pc,
RFSC => rfsourcein,
DWR => a999
);
datatoreg<=a999;
end Behavioral;
| gpl-3.0 | 0edc4b9a42b07a25fd2beb71bf64dfa9 | 0.574972 | 4.022676 | false | false | false | false |
hhuang25/uwaterloo_ece224 | Lab1Good/ece324_pulse_generator.vhd | 2 | 1,058 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ece324_pulse_generator is
port(
clk, oneStep : in std_logic;
duty_cycle : in std_logic_vector(3 downto 0);
reset : in std_logic;
enable : in std_logic;
pulse : out std_logic
);
end ece324_pulse_generator;
architecture Behavioral of ece324_pulse_generator is
signal count : std_logic_vector(3 downto 0);
signal generatedSignal : std_logic;
begin
pulsar: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(reset = '1') then
count <= "1111";
elsif(enable = '1') then
if(count = "1111") then
count <= "0000";
else
count <= count + 1;
end if;
end if;
if(count < duty_cycle) then
generatedSignal <= '1';
else
generatedSignal <= '0';
end if;
end if;
end process;
-- clocked multiplexer
Mux: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(duty_cycle = "0000") then
pulse <= oneStep;
else
pulse <= generatedSignal;
end if;
end if;
end process;
end Behavioral; | mit | 03555d7d00926c3ef864006a22b01885 | 0.638941 | 2.875 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb.vhd | 3 | 6,190 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_3_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 70
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| bsd-3-clause | c481ec0f707939bc116f5c6c0d5ebd29 | 0.627141 | 4.048398 | false | false | false | false |
qynvi/rtl-2dtimer | 2dtimer.vhd | 1 | 1,608 | -- William Fan
-- 2/19/2011
-- 2 Digit Timer RTL
entity 2dtimer is
generic (fclk: integer := 50_000_000); --50MHz
port (ena, clk, rst: in bit;
ssdL, ssdR: out bit_vector(6 downto 0));
end entity;
architecture tdt of 2dtimer is
begin
process (clk, rst, ena)
variable ncounter: natural range 0 to fclk := 0;
variable counterR: natural range 0 to 10 := 0;
variable counterL: natural range 0 to 6 := 0;
begin
--- timer counter
if (rst='1') then
ncounter := 0;
counterR := 0;
counterL := 0;
elsif (rst='0') then
if (clk'event and clk='1') then
if (ena='1' and counterL<6) then
ncounter := ncounter + 1;
if (ncounter=fclk) then
ncounter := 0;
counterR := counterR + 1;
end if;
if (counterR=10) then
counterR := 0;
counterL := counterL + 1;
end if;
end if;
end if;
end if;
--- LCD driver
case counterR is
when 0 => ssdR<="0000001";
when 1 => ssdR<="1001111";
when 2 => ssdR<="0010010";
when 3 => ssdR<="0000110";
when 4 => ssdR<="1001100";
when 5 => ssdR<="0100100";
when 6 => ssdR<="0100000";
when 7 => ssdR<="0001111";
when 8 => ssdR<="0000000";
when 9 => ssdR<="0000100";
when others => ssdR<="0110000";
end case;
case counterL is
when 0 => ssdL<="0000001";
when 1 => ssdL<="1001111";
when 2 => ssdL<="0010010";
when 3 => ssdL<="0000110";
when 4 => ssdL<="1001100";
when 5 => ssdL<="0100100";
when 6 => ssdL<="0100000";
when others => ssdL<="0110000";
end case;
end process;
end architecture;
| mit | 1145327f40751890acea6e3a6c507d8b | 0.56592 | 3.196819 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng.vhd | 3 | 4,028 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| bsd-3-clause | 6345e82575cb7c0b7260d877ac2c5ad5 | 0.643992 | 4.266949 | false | false | false | false |
davewebb8211/ghdl | libraries/vital95/vital_timing.vhdl | 6 | 46,973 | -------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set of
-- VitalDelayType01Z values.
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType
:= VitalDefaultOutputMap
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum and maximum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
END VITAL_Timing;
| gpl-2.0 | f9991039ec8ff44222f3f0d6acd4f144 | 0.448768 | 6.112297 | false | true | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/example_design/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes.vhd | 3 | 5,073 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes;
architecture xilinx of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-3-clause | eebeb1ad66af4d26f3beacdaa194bb8e | 0.542874 | 4.767857 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/PSR.vhd | 2 | 737 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
rest : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
begin
process(clk,nzvc,ncwp,rest)
begin
if(rest = '1') then
cwp <='0';
c <= '0';
icc <= "0000";
elsif rising_edge(clk) then
c<=nzvc(0);
cwp<=ncwp;
icc <= nzvc;
end if;
end process;
end Behavioral;
| gpl-3.0 | c83714523da944f78d98079d978f9257 | 0.450475 | 3.612745 | false | false | false | false |
alemedeiros/flappy_vhdl | output/vgacon.vhd | 1 | 15,657 | -------------------------------------------------------------------------------
-- Title : VGA Controller for DE1 boards
-- Project :
-------------------------------------------------------------------------------
-- File : vgacontop.vhd
-- Author : Rafael Auler
-- Company :
-- Created : 2010-03-21
-- Last update: 2010-03-26
-- Platform :
-- Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-03-21 1.0 Rafael Auler Created
-- 2010-03-26 1.1 Rafael Auler Working 64x60 display w/ internal mem.
-- 2010-03-26 1.2 Rafael Auler Working with arbitrary res. (up to
-- 640x480, tied to on-chip memory
-- availability). Defaults to 128x96.
-------------------------------------------------------------------------------
-- How sync signals are generated for 640x480
-- Note: sync signals are active low
-------------------------------------------------------------------------------
-- Horizontal sync:
-- -------------------__--------
-- | | | |
-- <----------->
-- 640
-- <---------------->
-- 660
-- <------------------->
-- 756
-- <-------------------------->
-- 800
-------------------------------------------------------------------------------
-- Vertical sync:
-- -----------------__-------
--
-- | | | |
-- <--------->
-- 480
-- <-------------->
-- 494
-- <----------------->
-- 495
-- <----------------------->
-- 525
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Notes:
-- write_clk, write_addr, write_enable and data_in are input signals used to
-- write to this controller memory and thus altering the displayed image on VGA.
--
-- "data_in" has 3 bits and represents a single image pixel.
-- (high bit for RED, middle for GREEN and lower for BLUE - total of 8 colors).
--
-- These signals follow simple memory write protocol (we=1 writes
-- data_in to address (pixel number) write_addr. This last signal may assume
-- NUM_HORZ_PIXELS * NUM_VERT_PIXELS different values, corresponding to each
-- one of the displayable pixels.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity vgacon is
generic (
-- When changing this, remember to keep 4:3 aspect ratio
-- Must also keep in mind that our native resolution is 640x480, and
-- you can't cross these bounds (although you will seldom have enough
-- on-chip memory to instantiate this module with higher res).
NUM_HORZ_PIXELS : natural := 128; -- Number of horizontal pixels
NUM_VERT_PIXELS : natural := 96); -- Number of vertical pixels
port (
clk27M, rstn : in std_logic;
write_clk, write_enable : in std_logic;
write_addr : in integer range 0 to
NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1;
data_in : in std_logic_vector(2 downto 0);
vga_clk : buffer std_logic; -- Ideally 25.175 MHz
red, green, blue : out std_logic_vector(3 downto 0);
hsync, vsync : out std_logic);
end vgacon;
architecture behav of vgacon is
-- Two signals: one is delayed by one clock cycle. The monitor control uses
-- the delayed one. We need a counter 1 clock cycle earlier, relative
-- to the monitor signal, in order to index the memory contents
-- for the next cycle, when the pixel is in fact sent to the monitor.
signal h_count, h_count_d : integer range 0 to 799; -- horizontal counter
signal v_count, v_count_d : integer range 0 to 524; -- vertical counter
-- We only want to address HORZ*VERT pixels in memory
signal read_addr : integer range 0 to NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1;
signal h_drawarea, v_drawarea, drawarea : std_logic;
signal data_out : std_logic_vector(2 downto 0);
begin -- behav
-- This is our PLL (Phase Locked Loop) to divide the DE1 27 MHz
-- clock and produce a 25.2MHz clock adequate to our VGA controller
divider: work.vga_pll port map (clk27M, vga_clk);
-- This is our dual clock RAM. We use our VGA clock to read contents from
-- memory (pixel color value). The user of this module may use any clock
-- to write contents to this memory, modifying pixels individually.
vgamem : work.dual_clock_ram
generic map (
MEMSIZE => NUM_HORZ_PIXELS * NUM_VERT_PIXELS)
port map (
read_clk => vga_clk,
write_clk => write_clk,
read_address => read_addr,
write_address => write_addr,
data_in => data_in,
data_out => data_out,
we => write_enable);
-- purpose: Increments the current horizontal position counter
-- type : sequential
-- inputs : vga_clk, rstn
-- outputs: h_count, h_count_d
horz_counter: process (vga_clk, rstn)
begin -- process horz_counter
if rstn = '0' then -- asynchronous reset (active low)
h_count <= 0;
h_count_d <= 0;
elsif vga_clk'event and vga_clk = '1' then -- rising clock edge
h_count_d <= h_count; -- 1 clock cycle delayed counter
if h_count = 799 then
h_count <= 0;
else
h_count <= h_count + 1;
end if;
end if;
end process horz_counter;
-- purpose: Determines if we are in the horizontal "drawable" area
-- type : combinational
-- inputs : h_count_d
-- outputs: h_drawarea
horz_sync: process (h_count_d)
begin -- process horz_sync
if h_count_d < 640 then
h_drawarea <= '1';
else
h_drawarea <= '0';
end if;
end process horz_sync;
-- purpose: Increments the current vertical counter position
-- type : sequential
-- inputs : vga_clk, rstn
-- outputs: v_count, v_count_d
vert_counter: process (vga_clk, rstn)
begin -- process vert_counter
if rstn = '0' then -- asynchronous reset (active low)
v_count <= 0;
v_count_d <= 0;
elsif vga_clk'event and vga_clk = '1' then -- rising clock edge
v_count_d <= v_count; -- 1 clock cycle delayed counter
if h_count = 699 then
if v_count = 524 then
v_count <= 0;
else
v_count <= v_count + 1;
end if;
end if;
end if;
end process vert_counter;
-- purpose: Updates information based on vertical position
-- type : combinational
-- inputs : v_count_d
-- outputs: v_drawarea
vert_sync: process (v_count_d)
begin -- process vert_sync
if v_count_d < 480 then
v_drawarea <= '1';
else
v_drawarea <= '0';
end if;
end process vert_sync;
-- purpose: Generates synchronization signals
-- type : combinational
-- inputs : v_count_d, h_count_d
-- outputs: hsync, vsync
sync: process (v_count_d, h_count_d)
begin -- process sync
if (h_count_d >= 659) and (h_count_d <= 755) then
hsync <= '0';
else
hsync <= '1';
end if;
if (v_count_d >= 493) and (v_count_d <= 494) then
vsync <= '0';
else
vsync <= '1';
end if;
end process sync;
-- determines whether we are in drawable area on screen a.t.m.
drawarea <= v_drawarea and h_drawarea;
-- purpose: calculates the controller memory address to read pixel data
-- type : combinational
-- inputs : h_count, v_count
-- outputs: read_addr
gen_r_addr: process (h_count, v_count)
begin -- process gen_r_addr
read_addr <= h_count / (640 / NUM_HORZ_PIXELS)
+ ((v_count/(480 / NUM_VERT_PIXELS))
* NUM_HORZ_PIXELS);
end process gen_r_addr;
-- Build color signals based on memory output and "drawarea" signal
-- (if we are not in the drawable area of 640x480, must deassert all
-- color signals).
red <= (others => data_out(2) and drawarea);
green <= (others => data_out(1) and drawarea);
blue <= (others => data_out(0) and drawarea);
end behav;
-------------------------------------------------------------------------------
-- The following entity is a dual clock RAM (read operates at different
-- clock from write). This is used to isolate two clock domains. The first
-- is the 25.2 MHz clock domain in which our VGA controller needs to operate.
-- This is the read clock, because we read from this memory to determine
-- the color of a pixel. The second is the clock domain of the user of this
-- module, writing in the memory the contents it wants to display in the VGA.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dual_clock_ram is
generic (
MEMSIZE : natural);
port (
read_clk, write_clk : in std_logic; -- support different clocks
data_in : in std_logic_vector(2 downto 0);
write_address, read_address : in integer range 0 to MEMSIZE - 1;
we : in std_logic; -- write enable
data_out : out std_logic_vector(2 downto 0));
end dual_clock_ram;
architecture behav of dual_clock_ram is
-- we only want to address (store) MEMSIZE elements
subtype addr is integer range 0 to MEMSIZE - 1;
type mem is array (addr) of std_logic_vector(2 downto 0);
signal ram_block : mem;
-- we don't care with read after write behavior (whether ram reads
-- old or new data in the same cycle).
attribute ramstyle : string;
attribute ramstyle of dual_clock_ram : entity is "no_rw_check";
attribute ram_init_file : string;
attribute ram_init_file of ram_block : signal is "vga_mem.mif";
begin -- behav
-- purpose: Reads data from RAM
-- type : sequential
-- inputs : read_clk, read_address
-- outputs: data_out
read: process (read_clk)
begin -- process read
if read_clk'event and read_clk = '1' then -- rising clock edge
data_out <= ram_block(read_address);
end if;
end process read;
-- purpose: Writes data to RAM
-- type : sequential
-- inputs : write_clk, write_address
-- outputs: ram_block
write: process (write_clk)
begin -- process write
if write_clk'event and write_clk = '1' then -- rising clock edge
if we = '1' then
ram_block(write_address) <= data_in;
end if;
end if;
end process write;
end behav;
-------------------------------------------------------------------------------
-- The following entity is automatically generated by Quartus (a megafunction).
-- As Altera DE1 board does not have a 25.175 MHz, but a 27 Mhz, we
-- instantiate a PLL (Phase Locked Loop) to divide out 27 MHz clock
-- and reach a satisfiable 25.2MHz clock for our VGA controller (14/15 ratio)
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY vga_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END vga_pll;
ARCHITECTURE SYN OF vga_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 15,
clk0_duty_cycle => 50,
clk0_multiply_by => 14,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=vga_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
| bsd-3-clause | 968b96daec066f1f9b5817b24538c26b | 0.553427 | 3.609267 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/vhdl/tri_intersect_data_array.vhd | 1 | 4,551 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tri_intersect_data_array_ram is
generic(
mem_type : string := "block";
dwidth : integer := 576;
awidth : integer := 1;
mem_size : integer := 2
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of tri_intersect_data_array_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1_tmp)) := d1;
end if;
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity tri_intersect_data_array is
generic (
DataWidth : INTEGER := 576;
AddressRange : INTEGER := 2;
AddressWidth : INTEGER := 1);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of tri_intersect_data_array is
component tri_intersect_data_array_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
tri_intersect_data_array_ram_U : component tri_intersect_data_array_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1,
q1 => q1);
end architecture;
| mit | e9a81157528d3f0d1309d2cb428611e9 | 0.537025 | 3.498078 | false | false | false | false |
fumyuun/tasty | src/snes/snes_btn_ctrl.vhd | 1 | 3,561 | --
-- This entity converts button states to the SNES communication protocol
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity snes_btn_ctrl is
port (
clk_i : in std_logic;
pause_o : out std_logic;
snes_js_btn_i : in snes_js_btn_r;
snes_js_bus_i : in snes_js_bus_i_r;
snes_js_bus_o : out snes_js_bus_o_r;
clock_indicator_o : out std_logic;
latch_indicator_o : out std_logic
);
end entity snes_btn_ctrl;
architecture behavioral of snes_btn_ctrl is
-- latches the state of the buttons
signal btn_r : std_logic_vector(15 downto 0);
signal btn_next_r : std_logic_vector(15 downto 0);
signal latch_r : std_logic;
signal ext_clock_r : std_logic;
signal prev_latch_r : std_logic;
signal prev_ext_clock_r : std_logic;
signal latch_rising_s : std_logic;
signal ext_clock_rising_s : std_logic;
signal clk_counter_s : unsigned(15 downto 0);
signal clk_counter_next_s : unsigned(15 downto 0);
signal latch_counter_s : unsigned(15 downto 0);
signal latch_counter_next_s : unsigned(15 downto 0);
begin
clock_proc: process (clk_i)
begin
if rising_edge(clk_i) then
prev_latch_r <= latch_r;
prev_ext_clock_r <= ext_clock_r;
ext_clock_r <= snes_js_bus_i.clock;
latch_r <= snes_js_bus_i.latch;
btn_r <= btn_next_r;
clk_counter_s <= clk_counter_next_s;
latch_counter_s <= latch_counter_next_s;
end if;
end process;
latch_rising_s <= not(prev_latch_r) and latch_r;
ext_clock_rising_s <= not(prev_ext_clock_r) and ext_clock_r;
clock_indicator_o <= clk_counter_s(3);
latch_indicator_o <= latch_counter_s(6);
pause_o <= '0' when clk_counter_s > 15 else '1';
snes_js_bus_o.data <= not(btn_r(0));
comb_proc : process (ext_clock_rising_s, latch_r, btn_r, btn_next_r, clk_counter_s, latch_counter_s, latch_rising_s,
snes_js_btn_i.up, snes_js_btn_i.left, snes_js_btn_i.right, snes_js_btn_i.down,
snes_js_btn_i.a, snes_js_btn_i.b, snes_js_btn_i.x, snes_js_btn_i.y, snes_js_btn_i.start,
snes_js_btn_i.sel, snes_js_btn_i.l, snes_js_btn_i.r)
begin
btn_next_r <= btn_r;
latch_counter_next_s <= latch_counter_s;
clk_counter_next_s <= clk_counter_s;
-- latch button state
if latch_rising_s = '1' then
latch_counter_next_s <= latch_counter_s + 1;
elsif latch_r = '1' then
btn_next_r(0) <= snes_js_btn_i.b;
btn_next_r(1) <= snes_js_btn_i.y;
btn_next_r(2) <= snes_js_btn_i.sel;
btn_next_r(3) <= snes_js_btn_i.start;
btn_next_r(4) <= snes_js_btn_i.up;
btn_next_r(5) <= snes_js_btn_i.down;
btn_next_r(6) <= snes_js_btn_i.left;
btn_next_r(7) <= snes_js_btn_i.right;
btn_next_r(8) <= snes_js_btn_i.a;
btn_next_r(9) <= snes_js_btn_i.x;
btn_next_r(10) <= snes_js_btn_i.l;
btn_next_r(11) <= snes_js_btn_i.r;
btn_next_r(15 downto 12) <= "0000"; -- unused bits
clk_counter_next_s <= x"0000";
-- shift out our values
elsif ext_clock_rising_s = '1' then
for i in 0 to 14 loop
btn_next_r(i) <= btn_r(i+1);
end loop;
btn_next_r(15) <= '0';
clk_counter_next_s <= clk_counter_s + 1;
end if;
end process;
end;
| mit | cda192f3851e76fdc6e8f499c02c86e7 | 0.558832 | 2.874092 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/ALU.vhd | 2 | 3,236 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:19:49 10/04/2017
-- Design Name:
-- Module Name: ALU - ARQALU
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
c: in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0));
end ALU;
architecture ARQALU of ALU is
begin
process(OPER1,OPER2,ALUOP)
begin
case (ALUOP) is
when "000000" => -- add
ALURESULT <= OPER1 + OPER2;
when "000001" =>--AND
ALURESULT <= OPER1 and OPER2;
when "000010" =>--OR
ALURESULT <= OPER1 or OPER2;
when "000011" =>--xor
ALURESULT <= OPER1 xor OPER2;
when "000111" =>--xnor
ALURESULT <= OPER1 xnor OPER2;
when "000100"=>--Sub
ALURESULT <= OPER1 - OPER2;
when "000101"=>--and not
ALURESULT<=OPER1 and not OPER2;
when "000110"=>--nor
ALURESULT<= OPER1 or not OPER2;
when "010000"=>--addcc
ALURESULT <= OPER1 + OPER2;
when "010100"=>--subcc
ALURESULT <= OPER1 - OPER2;
when "010001" =>--andcc
ALURESULT<= OPER1 and OPER2;
when "010101" =>--andncc
ALURESULT<= OPER1 and not OPER2;
when "010010" => --orcc
ALURESULT <= OPER1 or OPER2;
when "010110" =>--orncc
ALURESULT <= OPER1 or not OPER2;
when "001000"=>--addx
ALURESULT <= OPER1 + OPER2 + c;
when "011000" =>--addxcc
ALURESULT <= OPER1 + OPER2 + c;
when "001100" => --subx
ALURESULT <= OPER1- OPER2 - c;
when "011100" => --subxcc
ALURESULT <= OPER1 - OPER2 - c;
when "010011" => --xorcc
ALURESULT <= OPER1 xor OPER2;
when "010111" => --xnorcc
ALURESULT <= OPER1 xor OPER2;
when "100101" => --sll
ALURESULT <= to_stdlogicvector(to_bitvector(OPER1) sll conv_integer(OPER2));
when "100110" => --srl
ALURESULT <= to_stdlogicvector(to_bitvector(OPER1) srl conv_integer(OPER2));
when "111100" => --save
ALURESULT <= OPER1 + OPER2;
when "111101" => --restore
ALURESULT <= OPER1 + OPER2;
when "011011" => -- jmpl
ALURESULT <=OPER1 + OPER2;
when "111110" => --st y --ld
ALURESULT <= OPER1 + OPER2;
when others => --nops
ALURESULT<= x"00000000";
end case;
end process;
end ARQALU;
| gpl-3.0 | 4f66c3d2c26ab188db847d651b6461f3 | 0.539246 | 3.75842 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.vhd | 3 | 11,785 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg;
PACKAGE BODY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg;
| bsd-3-clause | 7a86b28d410e24be321f385535f0e5e7 | 0.519813 | 3.87537 | false | false | false | false |
alemedeiros/flappy_vhdl | player/calculate_speed.vhd | 1 | 1,092 | -- file: player/calculate_speed.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Calculate current speed based on internal register for speed, gravity value
-- and jump signal.
library ieee ;
use ieee.std_logic_1164.all ;
entity calculate_speed is
generic (
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
jump : in std_logic ;
gravity : in integer range 0 to V_RES - 1 ;
speed : out integer range - V_RES to V_RES - 1 ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end calculate_speed ;
architecture behavior of calculate_speed is
--signal sp : integer range - V_RES to V_RES - 1 := -1;
signal jump_aux : std_logic ;
begin
process (clock, reset)
variable sp : integer range - V_RES to V_RES - 1 := -1;
begin
if enable = '1' and rising_edge(clock) then
if jump = '1' then
sp := -1 ;
else
sp := sp + gravity ;
end if ;
end if ;
speed <= sp;
end process ;
end behavior;
| bsd-3-clause | 15e873b1438e82aec28b14f91e6319db | 0.6337 | 3.211765 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/UnidadControl.vhd | 1 | 7,392 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:49:14 10/20/2017
-- Design Name:
-- Module Name: UnidadControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UnidadControl is
Port ( Op : in STD_LOGIC_VECTOR (1 downto 0);
Op2 : in STD_LOGIC_VECTOR (2 downto 0);
Op3 : in STD_LOGIC_VECTOR (5 downto 0);
icc: in STD_LOGIC_VECTOR (3 downto 0);
cond: in STD_LOGIC_VECTOR (3 downto 0);
rfDest : out STD_LOGIC;
rfSource : out STD_LOGIC_VECTOR (1 downto 0);
wrEnMem : out STD_LOGIC;
wrEnRF : out STD_LOGIC;
pcSource : out STD_LOGIC_VECTOR (1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0));
end UnidadControl;
architecture Behavioral of UnidadControl is
begin
process(Op, Op2, Op3, icc, cond)
begin
wrEnMem <= '0';
rfDest <= '0';
if(op = "01")then --CALL
rfDest <= '1';
rfSource <= "10";
wrEnRF <= '1';
pcSource <= "00";
AluOp <= "111111";
else
if(Op = "00")then
if(Op2 = "010")then
case cond is
when "1000" => --ba
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
when "1001" => --bne
if(not(icc(2)) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0001" => --be
if(icc(2) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "1010" => --bg
if((not(icc(2) or (icc(3) xor icc(1)))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0010" => --ble
if((icc(2) or (icc(3) xor icc(1))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <="111111";
else
rfSource <="01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "1011" => --bge
if((not(icc(3) xor icc(1))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0011" => --bl
if((icc(3) xor icc(1)) = '1')then --sacado de manual
rfSource <="01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <="01" ;
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
else
if(Op2 = "100")then -- NOP
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
end if;
else
if(Op = "10")then
case Op3 is
when "000000" => --Add
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when "010000" => --Addcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010000";
when "001000" => --Addx
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "001000";
when "011000" => --Addxcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "011000";
when "000100" => --Sub
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000100";
when "010100" => --Subcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010100";
when "001100" => --Subx
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "001100";
when "011100" => --Subxcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "011100";
when "000001" => --And
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000001";
when "010001" => --Andcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010001";
when "000101" => --AndN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000101";
when "010101" => --AndNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010101";
when "000010" => --Or
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000010";
rfDest <= '0';
when "010010" => --Orcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010010";
when "000110" => --OrN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000110";
when "010110" => --OrNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010110";
when "000011" => --Xor
rfSource <= "01";
wrEnRF <='1' ;
pcSource <="10";
AluOp <= "000011";
when "010011" => --Xorcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010011";
when "111000" => -- JMPL
rfSource <= "10";
wrEnRF <= '1';
pcSource <="11";
AluOp <= "000000";
when "000111" => --XorN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000111";
when "010111" => --XnorNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010111";
when "111100" => -- SAVE
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when "111101" => -- RESTORE
rfSource <= "01";
wrEnRF <='1';
pcSource <="10";
AluOp <= "000000";
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
else
if(op = "11")then
case op3 is
when "000100" => -- STORE
rfSource <= "01"; -- leer
wrEnMem <= '1';
wrEnRF <= '0';
pcSource <="10";
AluOp <= "000000";
when "000000" => -- LOAD
rfSource <= "00"; --guardar
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 205f6aeab350b7357c7d553b63e07802 | 0.440206 | 3.364588 | false | false | false | false |
dhesant/elec4320 | Lab2/ipcore_dir/bram_decoder/simulation/bmg_tb_synth.vhd | 1 | 6,178 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_TB IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE BMG_TB_ARCH OF BMG_TB IS
COMPONENT bram_decoder_top
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC;
SIGNAL RESET_SYNC_R2 : STD_LOGIC;
SIGNAL RESET_SYNC_R3 : STD_LOGIC;
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_buf: bufg
PORT map(
i => CLK_IN,
o => clk_in_i
);
CLKA <= clk_in_i;
RSTA <= RESET_IN;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => CLK_IN,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
BMG_PORT: bram_decoder_top PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 732197e8f0cbcb0616739b2f1d228fbd | 0.59032 | 3.856429 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/synth/tri_intersect_ap_fdiv_28_no_dsp_32.vhd | 1 | 12,676 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fdiv_28_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fdiv_28_no_dsp_32;
ARCHITECTURE tri_intersect_ap_fdiv_28_no_dsp_32_arch OF tri_intersect_ap_fdiv_28_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fdiv_28_no_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fdiv_28_no_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fdiv_28_no_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=28,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fdiv_28_no_dsp_32_arch;
| mit | 6d6ad7f6aa45e64ccce453a76d32ffcd | 0.651783 | 3.021692 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg.vhd | 1 | 84,392 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
dm_resetn : in std_logic ; --
sg_ctl : in std_logic_vector (7 downto 0) ;
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic;
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
ch2_update_active : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic;
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ;
bd_eq : out std_logic
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
signal m_axi_sg_awaddr_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal m_axi_sg_awlen_int : std_logic_vector(7 downto 0) ; --
signal m_axi_sg_awsize_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awburst_int : std_logic_vector(1 downto 0) ; --
signal m_axi_sg_awprot_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awcache_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awuser_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awvalid_int : std_logic ; --
signal m_axi_sg_awready_int : std_logic ; --
--
-- Scatter Gather Write Data Channel --
signal m_axi_sg_wdata_int : std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
signal m_axi_sg_wstrb_int : std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
signal m_axi_sg_wlast_int : std_logic ; --
signal m_axi_sg_wvalid_int : std_logic ; --
signal m_axi_sg_wready_int : std_logic ; --
signal m_axi_sg_bresp_int : std_logic_vector (1 downto 0);
signal m_axi_sg_bvalid_int : std_logic;
signal m_axi_sg_bready_int : std_logic;
signal m_axi_sg_bvalid_int_del : std_logic;
signal ch2_eof_detected : std_logic;
signal s_axis_ch2_updtsts_tready_i : std_logic;
signal ch2_sg_idle, tail_updt_latch : std_logic;
signal tail_updt : std_logic;
signal ch2_taildesc_wren_int : std_logic;
signal ch2_sg_idle_int : std_logic;
signal ftch_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal updt_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch1_ftch_slverr_set_i : std_logic := '0';
signal ch1_ftch_decerr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_slverr_set_i : std_logic := '0';
signal ch2_ftch_decerr_set_i : std_logic := '0';
signal ch1_updt_interr_set_i : std_logic := '0';
signal ch1_updt_slverr_set_i : std_logic := '0';
signal ch1_updt_decerr_set_i : std_logic := '0';
signal ch2_updt_interr_set_i : std_logic := '0';
signal ch2_updt_slverr_set_i : std_logic := '0';
signal ch2_updt_decerr_set_i : std_logic := '0';
signal ftch_error_capture : std_logic := '0';
signal updt_error_capture : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
ftch_error_capture <= ch1_ftch_interr_set_i or
ch1_ftch_slverr_set_i or
ch1_ftch_decerr_set_i or
ch2_ftch_interr_set_i or
ch2_ftch_slverr_set_i or
ch2_ftch_decerr_set_i;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
ch1_ftch_slverr_set <= ch1_ftch_slverr_set_i;
ch1_ftch_decerr_set <= ch1_ftch_decerr_set_i;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
ch2_ftch_slverr_set <= ch2_ftch_slverr_set_i;
ch2_ftch_decerr_set <= ch2_ftch_decerr_set_i;
updt_error_capture <= ch1_updt_interr_set_i or
ch1_updt_slverr_set_i or
ch1_updt_decerr_set_i or
ch2_updt_interr_set_i or
ch2_updt_slverr_set_i or
ch2_updt_decerr_set_i or
ch2_dma_interr_set_i or
ch2_dma_slverr_set_i or
ch2_dma_decerr_set_i or
ch1_dma_interr_set_i or
ch1_dma_slverr_set_i or
ch1_dma_decerr_set_i;
ch1_updt_interr_set <= ch1_updt_interr_set_i;
ch1_updt_slverr_set <= ch1_updt_slverr_set_i;
ch1_updt_decerr_set <= ch1_updt_decerr_set_i;
ch2_updt_interr_set <= ch2_updt_interr_set_i;
ch2_updt_slverr_set <= ch2_updt_slverr_set_i;
ch2_updt_decerr_set <= ch2_updt_decerr_set_i;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (31 downto 6) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (31 downto 6)<= ftch_error_addr_1(31 downto 6);
elsif (updt_error_capture = '1') then
ftch_error_addr (31 downto 6)<= updt_error_addr_1(31 downto 6);
end if;
end if;
end process;
ADDR_64 : if (C_M_AXI_SG_ADDR_WIDTH > 32) generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (63 downto 32) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (63 downto 32)<= ftch_error_addr_1(63 downto 32);
elsif (updt_error_capture = '1') then
ftch_error_addr (63 downto 32)<= updt_error_addr_1(63 downto 32);
end if;
end if;
end process;
end generate ADDR_64;
updt_error_addr <= (others => '0');
ftch_error_addr (5 downto 0) <= (others => '0');
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
s_axis_ch2_updtsts_tready <= s_axis_ch2_updtsts_tready_i;
EOF_DET : if (C_ENABLE_MULTI_CHANNEL = 1) generate
ch2_eof_detected <= s_axis_ch2_updtsts_tdata (26)
and s_axis_ch2_updtsts_tready_i
and s_axis_ch2_updtsts_tvalid
and s_axis_ch2_updtsts_tlast;
-- ch2_eof_detected <= '0';
ch2_sg_idle_int <= ch2_sg_idle;
-- ch2_sg_idle_int <= '0'; --ch2_sg_idle;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or tail_updt = '1' ) then -- nned to have some reset condition here
tail_updt <= '0';
elsif(ch2_sg_idle = '1' and tail_updt_latch = '1' and tail_updt = '0')then
tail_updt <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
ch2_taildesc_wren_int <= ch2_taildesc_wren or tail_updt;
--ch2_taildesc_wren_int <= ch2_taildesc_wren;
end generate EOF_DET;
NOEOF_DET : if (C_ENABLE_MULTI_CHANNEL = 0) generate
tail_updt <= '0';
ch2_eof_detected <= '0';
ch2_taildesc_wren_int <= ch2_taildesc_wren;
ch2_sg_idle_int <= '0'; --ch2_sg_idle;
end generate NOEOF_DET;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_sg_v4_1.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set_i ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set_i ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set_i ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set_i ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set_i ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set_i ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren_int ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
ch2_eof_detected => ch2_eof_detected ,
tail_updt => tail_updt ,
tail_updt_latch => tail_updt_latch ,
ch2_sg_idle => ch2_sg_idle ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr_1 ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_sg_v4_1.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ACTUAL_ADDR => C_ACTUAL_ADDR,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => ch2_sg_idle_int ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_cyclic => ch1_cyclic ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_cyclic => ch2_cyclic ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
m_axis_ch2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_sg_v4_1.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set_i ,
ch1_updt_slverr_set => ch1_updt_slverr_set_i ,
ch1_updt_decerr_set => ch1_updt_decerr_set_i ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set_i ,
ch2_updt_slverr_set => ch2_updt_slverr_set_i ,
ch2_updt_decerr_set => ch2_updt_decerr_set_i ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr_1
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_sg_v4_1.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready_i ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_sg_v4_1.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_sg_v4_1.axi_sg_datamover
generic map(
C_INCLUDE_MM2S => 2, --INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, --
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_INCLUDE_S2MM => 2, --INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
sg_ctl => sg_ctl ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_aruser => m_axi_sg_aruser ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr_int ,
m_axi_s2mm_awlen => m_axi_sg_awlen_int ,
m_axi_s2mm_awsize => m_axi_sg_awsize_int ,
m_axi_s2mm_awburst => m_axi_sg_awburst_int ,
m_axi_s2mm_awprot => m_axi_sg_awprot_int ,
m_axi_s2mm_awcache => m_axi_sg_awcache_int ,
m_axi_s2mm_awuser => m_axi_sg_awuser_int ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid_int ,
m_axi_s2mm_awready => m_axi_sg_awready_int ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid_int ,
m_axi_s2mm_wready => m_axi_sg_wready_int ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp_int ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid_int ,
m_axi_s2mm_bready => m_axi_sg_bready_int ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
--ENABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS = 1) generate
-- begin
m_axi_sg_awaddr <= m_axi_sg_awaddr_int ;
m_axi_sg_awlen <= m_axi_sg_awlen_int ;
m_axi_sg_awsize <= m_axi_sg_awsize_int ;
m_axi_sg_awburst <= m_axi_sg_awburst_int;
m_axi_sg_awprot <= m_axi_sg_awprot_int ;
m_axi_sg_awcache <= m_axi_sg_awcache_int;
m_axi_sg_awuser <= m_axi_sg_awuser_int ;
m_axi_sg_awvalid <= m_axi_sg_awvalid_int;
m_axi_sg_awready_int <= m_axi_sg_awready;
m_axi_sg_wvalid <= m_axi_sg_wvalid_int;
m_axi_sg_wready_int <= m_axi_sg_wready;
m_axi_sg_bresp_int <= m_axi_sg_bresp;
m_axi_sg_bvalid_int <= m_axi_sg_bvalid;
m_axi_sg_bready <= m_axi_sg_bready_int;
-- end generate ENABLE_MM2S_STATUS;
--DISABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS > 1) generate
--
-- m_axi_sg_awaddr <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awaddr_int;
-- m_axi_sg_awlen <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awlen_int;
-- m_axi_sg_awsize <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awsize_int;
-- m_axi_sg_awburst <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awburst_int;
-- m_axi_sg_awprot <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awprot_int;
-- m_axi_sg_awcache <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awcache_int;
-- m_axi_sg_awuser <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awuser_int;
-- m_axi_sg_awvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_awvalid_int;
-- m_axi_sg_awready_int <= m_axi_sg_awvalid_int when ch1_updt_active = '1' else m_axi_sg_awready; -- to make sure that AXI logic is fine.
--
-- m_axi_sg_wvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_wvalid_int;
-- m_axi_sg_wready_int <= m_axi_sg_wvalid_int when ch1_updt_active = '1' else m_axi_sg_wready; -- to make sure that AXI logic is fine
--
-- m_axi_sg_bresp_int <= m_axi_sg_bresp;
-- m_axi_sg_bvalid_int <= m_axi_sg_bvalid_int_del when ch1_updt_active = '1' else m_axi_sg_bvalid;
-- m_axi_sg_bready <= m_axi_sg_bready_int;
--
ch2_update_active <= ch2_updt_active;
--
---- A dummy response is needed to keep things running on DMA side
-- PROC_DUMMY_RESP : process (m_axi_sg_aclk)
-- begin
-- if (dm_resetn = '0') then
-- m_axi_sg_bvalid_int_del <= '0';
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- m_axi_sg_bvalid_int_del <= m_axi_sg_wvalid_int;
-- end if;
-- end process PROC_DUMMY_RESP;
--
-- end generate DISABLE_MM2S_STATUS;
end implementation;
| mit | 3085ed653e5d2268611db779517ade7b | 0.402479 | 4.029412 | false | false | false | false |
hhuang25/uwaterloo_ece224 | Lab1Good/sdram_pll.vhd | 4 | 16,139 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: sdram_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sdram_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END sdram_pll;
ARCHITECTURE SYN OF sdram_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "-3000",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=sdram_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| mit | 0aca18d57849969444466c3304ff070d | 0.701035 | 3.336572 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 9 | 142,019 | `protect begin_protected
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9XswLJ2ir0zjr/ytWz4AdugoMiHf3QQeULPuW/TrIsbXmxSbxArZaK4IylNl9QyZDpM+cbgsEt5d
I5u/3JfB5EhI1+hss++4nqr8G8nhrXo9kz+6YIqsiO2CDJMd0QR31r1llYqpekNfAobl7yToClV9
cYEaf+6B/o+wV/KAczhPD4GuE49gDmOhk3DZQ+cXwazkcsyr8Ay/0uJ6dKpvKyfa5gXtpG2vjYbv
r1VgoczzuviWv6Xe6s4OijtJM1mtZET2sL3D10o4EL/BQoErsRrLsO3w2rpr1P4Pg980L2vic9Xd
y61D9L9T7dTla5OMKiy2W4/DS4lPeHy5jDNDVL2gybQOpIluM+0QmTx5kTrhgV2TkGSNuz15m94e
VDEsBT+O+0PWcve3nnuwC+k3BQfeM+xB9w/z3O7AIS8y85D2AsG/Rxlzq1HN8fqhF2s7JlYE3rMD
o6GjJe6UfFC2s4qz6BG/3mHXgOnFLGwhAgHKREslT5XRCsjQfLQJi7H99KAdgcO2TC8o
`protect end_protected
| mit | b89857e38977ccbbb0edd7d38325151f | 0.953246 | 1.828846 | false | false | false | false |
alemedeiros/flappy_vhdl | obstacles/generate_random.vhd | 1 | 983 | -- file: obstacles/generate_random.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Random number module.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.numeric_std.all ;
entity generate_random is
generic (
V_RES : integer := 96 -- Vertical Resolution
) ;
port (
seed : in std_logic_vector (4 downto 0) ;
rand : out integer range 0 to (V_RES/2 - 1) ;
clock : in std_logic
) ;
end generate_random ;
architecture behavior of generate_random is
begin
process (clock)
variable lfsr : std_logic_vector (4 downto 0) := "10011" ;
begin
if rising_edge(clock) then
lfsr(0) := lfsr(4) xor (lfsr(3) and lfsr(2));
lfsr(4 downto 1) := lfsr(3 downto 0);
end if ;
rand <= to_integer(unsigned(lfsr)) + 16 ;
end process ;
end behavior ; | bsd-3-clause | 597abd368005e028ea5b24f9e62ec2f0 | 0.61648 | 3.473498 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Barra4.vhd | 1 | 2,024 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:20:53 12/04/2017
-- Design Name:
-- Module Name: Barra4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Barra4 is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
datatomenout : out STD_LOGIC_VECTOR (31 downto 0);
aluresultout : out STD_LOGIC_VECTOR (31 downto 0);
datatomenin : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
pcin : in STD_LOGIC_VECTOR (31 downto 0);
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
rfsourcein : in STD_LOGIC_VECTOR (1 downto 0);
rfsource : out STD_LOGIC_VECTOR (1 downto 0);
pcout : out STD_LOGIC_VECTOR (31 downto 0));
end Barra4;
architecture Behavioral of Barra4 is
begin
process(Clk,Reset,datatomenin,aluresultin,pcin,rfsourcein,RD)
begin
if reset='1' then
datatomenout <= "00000000000000000000000000000000";
aluresultout <= "00000000000000000000000000000000";
rfsource <= "00";
pcout <= "00000000000000000000000000000000";
RDout <= "000000";
elsif(rising_edge(Clk)) then
RDout <= RD;
datatomenout <= datatomenin;
aluresultout <= aluresultin;
rfsource <= rfsourcein;
pcout <= pcin;
end if;
end process;
end Behavioral;
| gpl-3.0 | aadf33c06a8f0c7974563102f3650e63 | 0.599802 | 4.097166 | false | false | false | false |
loetlab-jena/das-atv | hdl/syn/hdmi2pal.vhd | 1 | 2,961 | -- DAS ATV-System Testplatform
-- Pinout:
-- HDMI_CLK: GPIO_1_IN0
-- HDMI_DE: GPIO_12
-- HDMI_VS: GPIO_11
-- HDMI_HS: GPIO_10
-- HDMI_R(5:0): GPIO_13, GPIO_14, GPIO_15, GPIO_16, GPIO_17, GPIO_18
-- HDMI_G(5:0): GPIO_110, GPIO_111, GPIO_112, GPIO_113, GPIO_114, GPIO_115
-- HDMI_B(5:0): GPIO_116, GPIO_117, GPIO_118, GPIO_119, GPIO_120, GPIO_121
-- DAC_CLK_I: GPIO_125
-- DAC_CLK_Q: GPIO_122
-- DAC_D(11:0): GPIO_21, GPIO_22, GPIO_20, GPIO_25, GPIO_23, GPIO_24, GPIO_26,
-- GPIO_27, GPIO_28, GPIO_29, GPIO_210, GPIO_211
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hdmi2pal is
port
(
CLK50 : in std_logic;
HDMI_CLK : in std_logic;
HDMI_DE : in std_logic;
HDMI_VS : in std_logic;
HDMI_HS : in std_logic;
HDMI_R : in std_logic_vector(5 downto 0);
HDMI_G : in std_logic_vector(5 downto 0);
HDMI_B : in std_logic_vector(5 downto 0);
DAC_CLK_I : out std_logic;
DAC_CLK_Q : out std_logic;
DAC_D : out std_logic_vector(11 downto 0);
LED : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of hdmi2pal is
function to_fcw(frequency : real) return positive is
constant sample_rate : real := 50_000_000.0;
constant bit_width : integer := 16;
begin
return integer(frequency / sample_rate * real(2**bit_width));
end function;
signal sync : std_logic;
signal burst : std_logic;
signal hdmi_freq : std_logic_vector(10 downto 0);
signal hdmi_ok : std_logic;
signal clk27 : std_logic;
signal clk27_locked : std_logic;
signal clk27_sw : std_logic;
signal clk108 : std_logic;
signal clk108_locked: std_logic;
signal clksel : std_logic;
signal sin_out : signed(11 downto 0);
begin
pll1 : entity work.pll
port map(
clkswitch => clksel,
inclk0 => HDMI_CLK,
inclk1 => clk27,
c0 => clk108,
locked => clk108_locked
);
DAC_CLK_I <= CLK50;
pll2 : entity work.pll2
port map(
inclk0 => CLK50,
c0 => clk27,
locked => clk27_locked
);
clksel <= '0' when hdmi_ok = '1' else '1';
ctrl : entity work.clkctrl
port map(
clkselect => clksel,
ena => '1',
inclk0x => HDMI_CLK,
inclk1x => clk27,
outclk => clk27_sw
);
hdmi_ok <= '1' when unsigned(hdmi_freq) = 270 else '0';
fcnt : entity work.frequency_counter
generic map(
res => 11,
gate => 500
)
port map(
clk => CLK50,
cnt_in => HDMI_CLK,
cnt_out => hdmi_freq
);
tgen : entity work.timing_gen
port map(
clk => HDMI_CLK,
vs => HDMI_VS,
hs => HDMI_HS,
de => HDMI_DE,
sync => sync,
burst => burst
);
sin_gen : entity work.nco
generic map(
A => 12,
F => 16,
P => 16,
N => 14,
FCW => to_fcw(1_000_000.0)
)
port map(
clk => CLK50,
sin => sin_out,
cos => open
);
DAC_D <= std_logic_vector(b"1000_0000_0000" - sin_out);
LED(7) <= sync;
LED(6) <= HDMI_DE;
LED(5) <= HDMI_HS;
LED(4) <= HDMI_VS;
LED(3) <= burst;
LED(2) <= hdmi_ok;
LED(1) <= clk27_locked;
LED(0) <= clk108_locked;
end rtl;
| gpl-2.0 | e8794c195b824364b2004bd17cf21247 | 0.613306 | 2.272448 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb.vhd | 3 | 6,381 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_vdma_0_wrapper_fifo_generator_v9_1_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth_inst:system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 44
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| bsd-3-clause | 7e17d225daa5d3145857092ca8b97048 | 0.62404 | 3.975701 | false | false | false | false |
louis-bonicel/VHDL | Porte_AND/add4_tb.vhd | 2 | 1,834 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:10:22 01/15/2015
-- Design Name:
-- Module Name: add4_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity add4_tb is
end add4_tb;
architecture Behavioral of add4_tb is
component add4 is
Port ( r0 : in STD_LOGIC;
a,b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (4 downto 0));
end component;
signal entree1 : std_logic;
signal entree2, entree3 : std_logic_vector(3 downto 0);
signal sortie : std_logic_vector(4 downto 0);
begin
uut : add4 port map (r0 => entree1, a => entree2, b => entree3, s => sortie);
stimuli : process
begin
boucle1:for i in 0 to 15 loop
entree2 <= std_logic_vector(to_unsigned(i,entree2'length));
boucle2:for j in 0 to 15 loop
entree3 <= std_logic_vector(to_unsigned(j,entree3'length));
boucle3:for k in std_logic range '0' to '1' loop
entree1 <= k;
wait for 1 ns;
end loop;
end loop;
end loop;
end process;
end Behavioral;
| gpl-2.0 | 2f551d2a2559eb7c6d3f69a66b0152f5 | 0.565976 | 3.554264 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/TBMUX32.vhd | 3 | 2,804 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:32 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBMUX32.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MUX32
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBMUX32 IS
END TBMUX32;
ARCHITECTURE behavior OF TBMUX32 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX32
PORT(
SEUIMM : IN std_logic_vector(31 downto 0);
CRS2 : IN std_logic_vector(31 downto 0);
OPER2 : OUT std_logic_vector(31 downto 0);
Instruction : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal SEUIMM : std_logic_vector(31 downto 0) := (others => '0');
signal CRS2 : std_logic_vector(31 downto 0) := (others => '0');
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal OPER2 : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX32 PORT MAP (
SEUIMM => SEUIMM,
CRS2 => CRS2,
OPER2 => OPER2,
Instruction => Instruction
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Instruction <= "00000000000000000000000000000000";
CRS2 <= "00000000000000000000000000000011";
SEUIMM <= "11000000000000000000000000000011";
wait for 100 ns;
Instruction <= "00000000000000000001000000000000";
CRS2 <= "00000000000000000000000000000011";
SEUIMM <= "11000000000000000000000000000011";
wait for 100 ns;
Instruction <= "00000000000000000010000000000000";
CRS2 <= "00000000000000000000000000000011";
SEUIMM <= "11000000000000000000000000000011";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | d2d8fc71487930cca23e264179a20813 | 0.631241 | 4.32716 | false | true | false | false |
loetlab-jena/das-atv | hdl/sim/yuv_tb.vhd | 1 | 2,544 | -- RGB2YUV Testbench
-- tests the rgb to yuv transormation
--
-- file: yuv_tb.vhd
-- author: Sebastian Weiss <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity yuv_tb is
end entity yuv_tb;
architecture sim of yuv_tb is
signal clk : std_logic := '0';
signal r : std_logic_vector(7 downto 0) := (others => '0');
signal g : std_logic_vector(7 downto 0) := (others => '0');
signal b : std_logic_vector(7 downto 0) := (others => '0');
signal y : std_logic_vector(7 downto 0) := (others => '0');
signal u : std_logic_vector(7 downto 0) := (others => '0');
signal v : std_logic_vector(7 downto 0) := (others => '0');
begin
clk <= not clk after 1 ns;
dut : entity work.rgb2yuv
generic map (
width => 8,
resolution => 10
)
port map (
clk => clk,
red => r,
green => g,
blue => b,
y => y,
u => u,
v => v
);
test : process
begin
wait until rising_edge(clk);
r <= x"FF";
g <= x"FF";
b <= x"FF";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
assert (y = x"FF") report "check 1: failed (y wrong)" severity failure;
assert (u = x"00") report "check 1: failed (u wrong)" severity failure;
assert (v = x"00") report "check 1: failed (v wrong)" severity failure;
report "check 1: ok";
r <= x"00";
g <= x"00";
b <= x"00";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
assert (y = x"00") report "check 2: failed (y wrong)" severity failure;
assert (u = x"00") report "check 2: failed (u wrong)" severity failure;
assert (v = x"00") report "check 2: failed (v wrong)" severity failure;
report "check 2: ok";
r <= x"B2";
g <= x"B2";
b <= x"B2";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
assert (y = x"B2") report "check 3: failed (y wrong)" severity failure;
assert (u = x"00") report "check 3: failed (u wrong)" severity failure;
assert (v = x"00") report "check 3: failed (v wrong)" severity failure;
report "check 3: ok";
r <= x"12";
g <= x"A3";
b <= x"E6";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
assert (y = x"7F") report "check 4: failed (y wrong)" severity failure;
assert (u = x"32") report "check 4: failed (u wrong)" severity failure;
assert (v = x"00") report "check 4: failed (v wrong)" severity failure;
report "check 4: ok";
wait;
end process test;
end architecture sim;
| gpl-2.0 | afd395818d7ce28418e01ba41ce9ad5d | 0.620283 | 2.729614 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/TextbSumador32bit.vhd | 3 | 2,233 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:33:50 09/27/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Procesador/TextbSumador32bit.vhd
-- Project Name: Procesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Sumador32bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TextbSumador32bit IS
END TextbSumador32bit;
ARCHITECTURE behavior OF TextbSumador32bit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sumador32bit
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Result : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sumador32bit PORT MAP (
Oper1 => Oper1,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Oper1 <= "00000000000000000000000000000001";
wait for 100 ns;
Oper1 <= "00000000000000000000000000000000";
wait for 100 ns;
Oper1 <= "00000000000000000000000000000100";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | f50a9b8d86f0db000d55e60be3d75a45 | 0.622033 | 4.253333 | false | true | false | false |
kennethlyn/parallella-lcd-fpga | system/hdl/system_stub.vhd | 3 | 6,782 | -------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
axi_dispctrl_0_HSYNC_O_pin => axi_dispctrl_0_HSYNC_O_pin,
axi_dispctrl_0_VSYNC_O_pin => axi_dispctrl_0_VSYNC_O_pin,
axi_dispctrl_0_PXL_CLK_O_pin => axi_dispctrl_0_PXL_CLK_O_pin,
axi_dispctrl_0_DE_O_pin => axi_dispctrl_0_DE_O_pin,
axi_dispctrl_0_RED_O_pin => axi_dispctrl_0_RED_O_pin,
axi_dispctrl_0_GREEN_O_pin => axi_dispctrl_0_GREEN_O_pin,
axi_dispctrl_0_BLUE_O_pin => axi_dispctrl_0_BLUE_O_pin,
axi_dispctrl_0_ENABLE_O_pin => axi_dispctrl_0_ENABLE_O_pin,
processing_system7_0_I2C0_SDA_pin => processing_system7_0_I2C0_SDA_pin,
processing_system7_0_I2C0_SCL_pin => processing_system7_0_I2C0_SCL_pin,
processing_system7_0_I2C0_INT_N_pin => processing_system7_0_I2C0_INT_N_pin,
processing_system7_0_FCLK_CLK0_pin => processing_system7_0_FCLK_CLK0_pin
);
end architecture STRUCTURE;
| bsd-3-clause | 4c6975678b28c90afef58ab1b10b26ee | 0.676349 | 2.938475 | false | false | false | false |
dhesant/elec4320 | Lab2/ipcore_dir/bram_decoder/example_design/bram_decoder_top.vhd | 1 | 4,333 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bram_decoder_top IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END bram_decoder_top;
ARCHITECTURE xilinx OF bram_decoder_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT bram_decoder IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : bram_decoder
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | a3e9952a94f2295e4578cf4a12679355 | 0.576967 | 4.8198 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/firstrpart.vhd | 1 | 10,227 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:12 09/26/2017
-- Design Name:
-- Module Name: firstrpart - arqfirstrpart
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity firstrpart is
Port ( Resetext : in STD_LOGIC;
Clkinext : in STD_LOGIC;
Adressext : out STD_LOGIC_VECTOR (31 downto 0));
end firstrpart;
architecture arqfirstrpart of firstrpart is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT NPC
PORT(
inNPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outNPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT PC
PORT(
inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT IM
PORT(
Address : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT UnidadControl
PORT(
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
op2 : in STD_LOGIC_VECTOR (2 downto 0);
cond : in STD_LOGIC_VECTOR (3 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
rfDest : out STD_LOGIC;
rfSource : out STD_LOGIC_VECTOR (1 downto 0);
wrEnMem : out STD_LOGIC;
wrEnRF : out STD_LOGIC;
pcSource : out STD_LOGIC_VECTOR (1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
OUTSEU : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MUX32
PORT(
SEUIMM : in STD_LOGIC_VECTOR (31 downto 0);
CRS2 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : out STD_LOGIC_VECTOR (31 downto 0);
Instruction : in STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
c :in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
wre : in STD_LOGIC;
cRd : out STD_LOGIC_VECTOR (31 downto 0);
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MuxRF
PORT(
Rd : in STD_LOGIC_VECTOR (5 downto 0);
O7 : in STD_LOGIC_VECTOR (5 downto 0);
RFDEST : in STD_LOGIC;
nRD : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT Windowsmanager
PORT(
cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0')
);
END COMPONENT;
COMPONENT PSR
PORT(
nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC ;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
rest : in STD_LOGIC;
c : out STD_LOGIC
);
END COMPONENT;
COMPONENT PSR_Modifier
PORT(
oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
COMPONENT SEU_22
PORT(
Imm_22 : in STD_LOGIC_VECTOR (21 downto 0);
Imm_32 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT SEU_30
PORT(
Imm_30 : in STD_LOGIC_VECTOR (29 downto 0);
Imm_32 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MuxPC
PORT(
Disp30 : in STD_LOGIC_VECTOR (31 downto 0);
Disp22 : in STD_LOGIC_VECTOR (31 downto 0);
PC1 : in STD_LOGIC_VECTOR (31 downto 0);
Direccion : in STD_LOGIC_VECTOR (31 downto 0);
Selector : in STD_LOGIC_VECTOR (1 downto 0);
Direccion_Out : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT DataMemory
PORT(
cRD : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
WRENMEM : in STD_LOGIC;
Reset : in STD_LOGIC;
DataMem : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MuxDM
PORT(
DataMem : in STD_LOGIC_VECTOR (31 downto 0);
AluResult : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
RFSC : in STD_LOGIC_VECTOR (1 downto 0);
DWR : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a1,a2,a3,a4,a5,a18,a19,a20,a21,a22,a23,a24,a10,a31,a25,a32,a33: std_logic_vector(31 downto 0);
--ventanas
signal a6,a7: STD_LOGIC;
--nrs1,
signal a8,a9,a26,a27,a16: std_logic_vector(5 downto 0);
signal a11,a12,a14,a15,a29: STD_LOGIC;
signal a30,a28: std_logic_vector(3 downto 0);
signal a13,a17: std_logic_vector(1 downto 0);
begin
ints_NPC: PC PORT MAP(
inPC => a1,
Reset => Resetext,
Clk => Clkinext,
outPC => a2
);
ints_PC: PC PORT MAP(
inPC => a2,
Reset => Resetext,
Clk => Clkinext,
outPC => a5
);
ints_sum: Sumador32bit PORT MAP(
Oper1 => a5,
Oper2 =>"00000000000000000000000000000001",
Result => a3
);
ints_IM: IM PORT MAP(
Address => a5,
Reset => Resetext,
Instruction => a4
);
ints_sumdisp30: Sumador32bit PORT MAP(
Oper1 => a31,
Oper2 => a5,
Result => a33
);
ints_sumdisp22: Sumador32bit PORT MAP(
Oper1 => a10,
Oper2 => a5,
Result => a32
);
ints_windowsmanager: Windowsmanager PORT MAP(
cwp =>a6,
rs1 =>a4(18 downto 14),
rs2 =>a4(4 downto 0),
rd =>a4(29 downto 25),
op =>a4(31 downto 30),
op3 =>a4(24 downto 19),
cwpout=> a7,
rs1out=>a9,
rs2out=> a26,
rdout=> a8
);
ints_rf: RF PORT MAP(
rs1 => a9,
rs2 => a26,
rd => a27,
dwr => a25,
rst => Resetext,
wre => a11,
cRd => a18,
crs1 => a19,
crs2 => a20
);
ints_muxrf: MuxRF PORT MAP(
Rd => a8,
O7 => "001111",
RFDEST => a12,
nRD => a27
);
ints_CU: UnidadControl PORT MAP(
op =>a4(31 downto 30),
op3 =>a4(24 downto 19),
op2 =>a4(24 downto 22),
cond =>a4(28 downto 25),
icc =>a30,
rfDest =>a12,
rfSource =>a13,
wrEnMem =>a14,
wrEnRF =>a11,
pcSource =>a17,
AluOp =>a16
);
ints_seu: SEU PORT MAP(
Instruction =>a4,
OUTSEU =>a21
);
ints_mux32: MUX32 PORT MAP(
SEUIMM => a21,
CRS2 => a20,
OPER2 => a22,
Instruction => a4
);
ints_alu: ALU PORT MAP(
OPER1 => a19,
OPER2 => a22,
c =>a29,
ALURESULT => a23,
ALUOP => a16
);
ints_psr: PSR PORT MAP(
nzvc => a28,
clk => Clkinext,
cwp => a6,
rest => Resetext,
ncwp => a7,
icc => a30,
c => a29
);
ints_psrmodifier: PSR_Modifier PORT MAP(
oper1 => a19,
oper2 => a22,
aluop => a16,
aluResult => a23,
conditionalCodes => a28
);
ints_seu22: SEU_22 PORT MAP(
Imm_22 => a4(21 downto 0),
Imm_32 => a10
);
ints_seu30: SEU_30 PORT MAP(
Imm_30 => a4(29 downto 0),
Imm_32 => a31
);
ints_muxPC: MuxPC PORT MAP(
Disp30 => a33,
Disp22 => a32,
PC1 => a3,
Direccion => a23,
Selector => a17,
Direccion_Out => a1
);
ints_datamemmory: DataMemory PORT MAP(
cRD => a18,
AluResult => a23,
WRENMEM => a14,
Reset => Resetext,
DataMem => a24
);
ints_muxdatamemory: MuxDM PORT MAP(
DataMem => a24,
AluResult => a23,
PC => a5,
RFSC => a13,
DWR => a25
);
Adressext<=a25;
end arqfirstrpart;
| gpl-3.0 | b3bed9a09c65982ddf6984c6d5b45b54 | 0.513836 | 3.486874 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_s2mm_basic_wrap.vhd | 1 | 50,332 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_scc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
| mit | 511d632facbb5589ea3cb39ea2a5b3ec | 0.442979 | 4.141188 | false | false | false | false |
alemedeiros/flappy_vhdl | output/pixel_counter.vhd | 1 | 1,448 | -- file: output/pixel_counter.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Sweeps through each bit of a VGA screen.
library ieee ;
use ieee.std_logic_1164.all ;
entity pixel_counter is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
lin : out integer range 0 to V_RES - 1 ;
col : out integer range 0 to H_RES - 1 ;
clock : in std_logic ;
reset : in std_logic ;
enable : in std_logic
) ;
end pixel_counter ;
architecture behavior of pixel_counter is
signal my_lin : integer range 0 to V_RES - 1 ;
signal my_col : integer range 0 to H_RES - 1 ;
begin
-- Columns counter
count_col: process (clock, reset)
begin
if reset = '1' then
my_col <= 0 ;
elsif rising_edge(clock) then
if enable = '1' then
if my_col = H_RES - 1 then
my_col <= 0 ;
else
my_col <= my_col + 1 ;
end if ;
end if ;
end if ;
end process count_col ;
-- Lines counter
count_lin: process (clock, reset)
begin
if reset = '1' then
my_lin <= 0;
elsif rising_edge(clock) then
if enable = '1' and my_col = H_RES - 1 then
if my_lin = V_RES - 1 then
my_lin <= 0 ;
else
my_lin <= my_lin + 1 ;
end if;
end if;
end if;
end process count_lin ;
lin <= my_lin ;
col <= my_col ;
end behavior ;
| bsd-3-clause | 2e8c69354bcf16623f881e34903d5f4d | 0.609116 | 2.991736 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/tri_intersect_data_array.vhd | 3 | 4,553 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tri_intersect_data_array_ram is
generic(
mem_type : string := "block";
dwidth : integer := 576;
awidth : integer := 5;
mem_size : integer := 20
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(dwidth-1 downto 0);
we1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of tri_intersect_data_array_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1_tmp)) := d1;
end if;
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity tri_intersect_data_array is
generic (
DataWidth : INTEGER := 576;
AddressRange : INTEGER := 20;
AddressWidth : INTEGER := 5);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of tri_intersect_data_array is
component tri_intersect_data_array_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR;
we1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
tri_intersect_data_array_ram_U : component tri_intersect_data_array_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
d1 => d1,
we1 => we1,
q1 => q1);
end architecture;
| mit | c34785d17523c7d28fe69a224932eb63 | 0.537228 | 3.499616 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/pcores/axi_dispctrl_v1_00_a/hdl/vhdl/vdma_to_vga.vhd | 3 | 13,029 | --------------------------------------------------------------------------------
--
-- File:
-- vdma_to_vga.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author:
-- Sam Bobrowicz
--
-- Description:
-- AXI Display Controller
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity vdma_to_vga is
generic (
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
C_S_AXIS_TDATA_WIDTH : integer := 32 --must be 32
);
Port (
LOCKED_I : in STD_LOGIC;
ENABLE_I : in STD_LOGIC;
RUNNING_O : out STD_LOGIC;
FSYNC_O : out STD_LOGIC;
S_AXIS_ACLK : in STD_LOGIC;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
DEBUG_O : out STD_LOGIC_VECTOR (31 downto 0);
HSYNC_O : out STD_LOGIC;
VSYNC_O : out STD_LOGIC;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR (C_RED_WIDTH-1 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (C_GREEN_WIDTH-1 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (C_BLUE_WIDTH-1 downto 0);
USR_WIDTH_I : in STD_LOGIC_VECTOR (11 downto 0);
USR_HEIGHT_I : in STD_LOGIC_VECTOR (11 downto 0);
USR_HPS_I : in STD_LOGIC_VECTOR (11 downto 0);
USR_HPE_I : in STD_LOGIC_VECTOR (11 downto 0);
USR_HPOL_I : in STD_LOGIC;
USR_HMAX_I : in STD_LOGIC_VECTOR (11 downto 0);
USR_VPS_I : in STD_LOGIC_VECTOR (11 downto 0);
USR_VPE_I : in STD_LOGIC_VECTOR (11 downto 0);
USR_VPOL_I : in STD_LOGIC;
USR_VMAX_I : in STD_LOGIC_VECTOR (11 downto 0));
end vdma_to_vga;
architecture Behavioral of vdma_to_vga is
type VGA_STATE_TYPE is (VGA_RESET, VGA_WAIT_EN, VGA_LATCH, VGA_INIT, VGA_WAIT_VLD, VGA_RUN);
signal pxl_clk : std_logic;
signal locked : std_logic;
signal vga_running : std_logic;
signal frame_edge : std_logic;
signal running_reg : std_logic := '0';
signal vga_en : std_logic := '0';
signal frm_width : std_logic_vector(11 downto 0) := (others =>'0');
signal frm_height : std_logic_vector(11 downto 0) := (others =>'0');
signal h_ps : std_logic_vector(11 downto 0) := (others =>'0');
signal h_pe : std_logic_vector(11 downto 0) := (others =>'0');
signal h_max : std_logic_vector(11 downto 0) := (others =>'0');
signal v_ps : std_logic_vector(11 downto 0) := (others =>'0');
signal v_pe : std_logic_vector(11 downto 0) := (others =>'0');
signal v_max : std_logic_vector(11 downto 0) := (others =>'0');
signal h_pol : std_logic := '0';
signal v_pol : std_logic := '0';
signal h_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
signal v_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
signal h_sync_reg : std_logic := '0';
signal v_sync_reg : std_logic := '0';
signal h_sync_dly : std_logic := '0';
signal v_sync_dly : std_logic := '0';
signal fsync_reg : std_logic := '0';
signal video_dv : std_logic := '0';
signal video_dv_dly : std_logic := '0';
signal red_reg : std_logic_vector(7 downto 0) := (others =>'0');
signal green_reg : std_logic_vector(7 downto 0) := (others =>'0');
signal blue_reg : std_logic_vector(7 downto 0) := (others =>'0');
signal vga_state : VGA_STATE_TYPE := VGA_RESET;
begin
locked <= LOCKED_I;
pxl_clk <= S_AXIS_ACLK;
DEBUG_O(11 downto 0) <= h_cntr_reg;
DEBUG_O(23 downto 12) <= v_cntr_reg;
DEBUG_O(24) <= vga_running;
DEBUG_O(25) <= frame_edge;
DEBUG_O(26) <= fsync_reg;
DEBUG_O(27) <= h_sync_dly;
DEBUG_O(28) <= v_sync_dly;
DEBUG_O(29) <= video_dv_dly; --Data valid
DEBUG_O(30) <= video_dv; --TREADY
DEBUG_O(31) <= S_AXIS_TVALID;
------------------------------------------------------------------
------ CONTROL STATE MACHINE -------
------------------------------------------------------------------
--Synchronize ENABLE_I signal from axi_lite domain to pixel clock
--domain
process (pxl_clk, locked)
begin
if (locked = '0') then
vga_en <= '0';
elsif (rising_edge(pxl_clk)) then
vga_en <= ENABLE_I;
end if;
end process;
process (pxl_clk, locked)
begin
if (locked = '0') then
vga_state <= VGA_RESET;
elsif (rising_edge(pxl_clk)) then
case vga_state is
when VGA_RESET =>
vga_state <= VGA_WAIT_EN;
when VGA_WAIT_EN =>
if (vga_en = '1') then
vga_state <= VGA_LATCH;
end if;
when VGA_LATCH =>
vga_state <= VGA_INIT;
when VGA_INIT =>
vga_state <= VGA_WAIT_VLD;
when VGA_WAIT_VLD =>
--It seems the first frame requires a bit of time for the linebuffer to fill. This
--State ensures we do not begin requesting data before the VDMA reports it is valid
if (S_AXIS_TVALID = '1') then
vga_state <= VGA_RUN;
end if;
when VGA_RUN =>
if (vga_en = '0' and frame_edge = '1') then
vga_state <= VGA_WAIT_EN;
end if;
when others => --Never reached
vga_state <= VGA_RESET;
end case;
end if;
end process;
--This component treats the first pixel of the first non-visible line as the beginning
--of the frame.
frame_edge <= '1' when ((v_cntr_reg = frm_height) and (h_cntr_reg = 0)) else
'0';
vga_running <= '1' when vga_state = VGA_RUN else
'0';
process (pxl_clk, locked)
begin
if (locked = '0') then
running_reg <= '0';
elsif (rising_edge(pxl_clk)) then
running_reg <= vga_running;
end if;
end process;
RUNNING_O <= running_reg;
------------------------------------------------------------------
------ USER REGISTER LATCH -------
------------------------------------------------------------------
--Note that the USR_ inputs are crossing from the axi_lite clock domain
--to the pixel clock domain
process (pxl_clk, locked)
begin
if (locked = '0') then
frm_width <= (others => '0');
frm_height <= (others => '0');
h_ps <= (others => '0');
h_pe <= (others => '0');
h_pol <= '0';
h_max <= (others => '0');
v_ps <= (others => '0');
v_pe <= (others => '0');
v_pol <= '0';
v_max <= (others => '0');
elsif (rising_edge(pxl_clk)) then
if (vga_state = VGA_LATCH) then
frm_width <= USR_WIDTH_I;
frm_height <= USR_HEIGHT_I;
h_ps <= USR_HPS_I;
h_pe <= USR_HPE_I;
h_pol <= USR_HPOL_I;
h_max <= USR_HMAX_I;
v_ps <= USR_VPS_I;
v_pe <= USR_VPE_I;
v_pol <= USR_VPOL_I;
v_max <= USR_VMAX_I;
end if;
end if;
end process;
------------------------------------------------------------------
------ PIXEL ADDRESS COUNTERS -------
------------------------------------------------------------------
process (pxl_clk, locked)
begin
if (locked = '0') then
h_cntr_reg <= (others => '0');
elsif (rising_edge(pxl_clk)) then
if (vga_state = VGA_WAIT_VLD) then
h_cntr_reg <= (others =>'0'); --Note that the first frame starts on the second non-visible line, right after when FSYNC would pulse
elsif (vga_running = '1') then
if (h_cntr_reg = h_max) then
h_cntr_reg <= (others => '0');
else
h_cntr_reg <= h_cntr_reg + 1;
end if;
else
h_cntr_reg <= (others =>'0');
end if;
end if;
end process;
process (pxl_clk, locked)
begin
if (locked = '0') then
v_cntr_reg <= (others => '0');
elsif (rising_edge(pxl_clk)) then
if (vga_state = VGA_WAIT_VLD) then
v_cntr_reg <= frm_height + 1; --Note that the first frame starts on the second non-visible line, right after when FSYNC would pulse
elsif (vga_running = '1') then
if ((h_cntr_reg = h_max) and (v_cntr_reg = v_max))then
v_cntr_reg <= (others => '0');
elsif (h_cntr_reg = h_max) then
v_cntr_reg <= v_cntr_reg + 1;
end if;
else
v_cntr_reg <= (others =>'0');
end if;
end if;
end process;
------------------------------------------------------------------
------ SYNC GENERATION -------
------------------------------------------------------------------
process (pxl_clk, locked)
begin
if (locked = '0') then
h_sync_reg <= '0';
elsif (rising_edge(pxl_clk)) then
if (vga_running = '1') then
if ((h_cntr_reg >= h_ps) and (h_cntr_reg < h_pe)) then
h_sync_reg <= h_pol;
else
h_sync_reg <= not(h_pol);
end if;
else
h_sync_reg <= '0';
end if;
end if;
end process;
process (pxl_clk, locked)
begin
if (locked = '0') then
v_sync_reg <= '0';
elsif (rising_edge(pxl_clk)) then
if (vga_running = '1') then
if ((v_cntr_reg >= v_ps) and (v_cntr_reg < v_pe)) then
v_sync_reg <= v_pol;
else
v_sync_reg <= not(v_pol);
end if;
else
v_sync_reg <= '0';
end if;
end if;
end process;
process (pxl_clk, locked)
begin
if (locked = '0') then
v_sync_dly <= '0';
h_sync_dly <= '0';
elsif (rising_edge(pxl_clk)) then
v_sync_dly <= v_sync_reg;
h_sync_dly <= h_sync_reg;
end if;
end process;
HSYNC_O <= h_sync_dly;
VSYNC_O <= v_sync_dly;
--Signal a new frame to the VDMA at the end of the first non-visible line. This
--should allow plenty of time for the line buffer to fill between frames, before
--data is required. The first fsync pulse is signaled during the VGA_INIT state.
process (pxl_clk, locked)
begin
if (locked = '0') then
fsync_reg <= '0';
elsif (rising_edge(pxl_clk)) then
if ((((v_cntr_reg = frm_height) and (h_cntr_reg = h_max)) and (vga_running = '1')) or (vga_state = VGA_INIT)) then
fsync_reg <= '1';
else
fsync_reg <= '0';
end if;
end if;
end process;
FSYNC_O <= fsync_reg;
------------------------------------------------------------------
------ DATA CAPTURE -------
------------------------------------------------------------------
process (pxl_clk, locked)
begin
if (locked = '0') then
video_dv <= '0';
video_dv_dly <= '0';
elsif (rising_edge(pxl_clk)) then
video_dv_dly <= video_dv;
if ((vga_running = '1') and (v_cntr_reg < frm_height) and (h_cntr_reg < frm_width)) then
video_dv <= '1';
else
video_dv <= '0';
end if;
end if;
end process;
process (pxl_clk, locked)
begin
if (locked = '0') then
red_reg <= (others => '0');
green_reg <= (others => '0');
blue_reg <= (others => '0');
elsif (rising_edge(pxl_clk)) then
if (video_dv = '1') then
red_reg <= S_AXIS_TDATA(23 downto 16);
green_reg <= S_AXIS_TDATA(15 downto 8);
blue_reg <= S_AXIS_TDATA(7 downto 0);
else
red_reg <= (others => '0');
green_reg <= (others => '0');
blue_reg <= (others => '0');
end if;
end if;
end process;
S_AXIS_TREADY <= video_dv;
DE_O <= video_dv_dly;
RED_O <= red_reg(7 downto 8-C_RED_WIDTH);
GREEN_O <= green_reg(7 downto 8-C_GREEN_WIDTH);
BLUE_O <= blue_reg(7 downto 8-C_BLUE_WIDTH);
end Behavioral;
| bsd-3-clause | ce96ac1d00e4d83df9d047e8dfd1b656 | 0.555837 | 3.150907 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/tri_intersect.vhd | 3 | 950,495 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tri_intersect is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ins_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
ins_TVALID : IN STD_LOGIC;
ins_TREADY : OUT STD_LOGIC;
ins_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
ins_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
ins_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TID : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
outs_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
outs_TVALID : OUT STD_LOGIC;
outs_TREADY : IN STD_LOGIC;
outs_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
outs_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
outs_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of tri_intersect is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"tri_intersect,hls_ip_2015_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=463,HLS_SYN_TPT=none,HLS_SYN_MEM=32,HLS_SYN_DSP=127,HLS_SYN_FF=20827,HLS_SYN_LUT=27149}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st151_fsm_150 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st152_fsm_151 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st153_fsm_152 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st154_fsm_153 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st155_fsm_154 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st156_fsm_155 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st157_fsm_156 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st158_fsm_157 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st159_fsm_158 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st160_fsm_159 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st161_fsm_160 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st162_fsm_161 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st163_fsm_162 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st164_fsm_163 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st165_fsm_164 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st166_fsm_165 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st167_fsm_166 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st168_fsm_167 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st169_fsm_168 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st170_fsm_169 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st171_fsm_170 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st172_fsm_171 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st173_fsm_172 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st174_fsm_173 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st175_fsm_174 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st176_fsm_175 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st177_fsm_176 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st178_fsm_177 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st179_fsm_178 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st180_fsm_179 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st181_fsm_180 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st182_fsm_181 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st183_fsm_182 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st184_fsm_183 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st185_fsm_184 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st186_fsm_185 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st187_fsm_186 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st188_fsm_187 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st189_fsm_188 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st190_fsm_189 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st191_fsm_190 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st192_fsm_191 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st193_fsm_192 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st194_fsm_193 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st195_fsm_194 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st196_fsm_195 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st197_fsm_196 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st198_fsm_197 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st199_fsm_198 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st200_fsm_199 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st201_fsm_200 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st202_fsm_201 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st203_fsm_202 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st204_fsm_203 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st205_fsm_204 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st206_fsm_205 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st207_fsm_206 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st208_fsm_207 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st209_fsm_208 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st210_fsm_209 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st211_fsm_210 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st212_fsm_211 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st213_fsm_212 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st214_fsm_213 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st215_fsm_214 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st216_fsm_215 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st217_fsm_216 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st218_fsm_217 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st219_fsm_218 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st220_fsm_219 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st221_fsm_220 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st222_fsm_221 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st223_fsm_222 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st224_fsm_223 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st225_fsm_224 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st226_fsm_225 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st227_fsm_226 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st228_fsm_227 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st229_fsm_228 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st230_fsm_229 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st231_fsm_230 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st232_fsm_231 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st233_fsm_232 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st234_fsm_233 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st235_fsm_234 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st236_fsm_235 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st237_fsm_236 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st238_fsm_237 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st239_fsm_238 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st240_fsm_239 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st241_fsm_240 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st242_fsm_241 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st243_fsm_242 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st244_fsm_243 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st245_fsm_244 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st246_fsm_245 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st247_fsm_246 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st248_fsm_247 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st249_fsm_248 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st250_fsm_249 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st251_fsm_250 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st252_fsm_251 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st253_fsm_252 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st254_fsm_253 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st255_fsm_254 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st256_fsm_255 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st257_fsm_256 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st258_fsm_257 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st259_fsm_258 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st260_fsm_259 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st261_fsm_260 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st262_fsm_261 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st263_fsm_262 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st264_fsm_263 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st265_fsm_264 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st266_fsm_265 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st267_fsm_266 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st268_fsm_267 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st269_fsm_268 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st270_fsm_269 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st271_fsm_270 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st272_fsm_271 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st273_fsm_272 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st274_fsm_273 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st275_fsm_274 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st276_fsm_275 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st277_fsm_276 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st278_fsm_277 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st279_fsm_278 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st280_fsm_279 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st281_fsm_280 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st282_fsm_281 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st283_fsm_282 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st284_fsm_283 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st285_fsm_284 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st286_fsm_285 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st287_fsm_286 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st288_fsm_287 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st289_fsm_288 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st290_fsm_289 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st291_fsm_290 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st292_fsm_291 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st293_fsm_292 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st294_fsm_293 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st295_fsm_294 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st296_fsm_295 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st297_fsm_296 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st298_fsm_297 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st299_fsm_298 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st300_fsm_299 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_pp0_stg0_fsm_300 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st385_fsm_301 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st386_fsm_302 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st387_fsm_303 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st388_fsm_304 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st389_fsm_305 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st390_fsm_306 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st391_fsm_307 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st392_fsm_308 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st393_fsm_309 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st394_fsm_310 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st395_fsm_311 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st396_fsm_312 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st397_fsm_313 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st398_fsm_314 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st399_fsm_315 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st400_fsm_316 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st401_fsm_317 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st402_fsm_318 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st403_fsm_319 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st404_fsm_320 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st405_fsm_321 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st406_fsm_322 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st407_fsm_323 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st408_fsm_324 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st409_fsm_325 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st410_fsm_326 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st411_fsm_327 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st412_fsm_328 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st413_fsm_329 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st414_fsm_330 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st415_fsm_331 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st416_fsm_332 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st417_fsm_333 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st418_fsm_334 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st419_fsm_335 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st420_fsm_336 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st421_fsm_337 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st422_fsm_338 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st423_fsm_339 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st424_fsm_340 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st425_fsm_341 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st426_fsm_342 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st427_fsm_343 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st428_fsm_344 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st429_fsm_345 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st430_fsm_346 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st431_fsm_347 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st432_fsm_348 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st433_fsm_349 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st434_fsm_350 : STD_LOGIC_VECTOR (361 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st435_fsm_351 : STD_LOGIC_VECTOR (361 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st436_fsm_352 : STD_LOGIC_VECTOR (361 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st437_fsm_353 : STD_LOGIC_VECTOR (361 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st438_fsm_354 : STD_LOGIC_VECTOR (361 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st439_fsm_355 : STD_LOGIC_VECTOR (361 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st440_fsm_356 : STD_LOGIC_VECTOR (361 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st441_fsm_357 : STD_LOGIC_VECTOR (361 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st442_fsm_358 : STD_LOGIC_VECTOR (361 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st443_fsm_359 : STD_LOGIC_VECTOR (361 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st444_fsm_360 : STD_LOGIC_VECTOR (361 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st445_fsm_361 : STD_LOGIC_VECTOR (361 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_true : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_48 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001000";
constant ap_const_lv32_4B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001011";
constant ap_const_lv32_5A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011010";
constant ap_const_lv32_69 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101001";
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_87 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000111";
constant ap_const_lv32_96 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010110";
constant ap_const_lv32_A5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100101";
constant ap_const_lv32_B4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110100";
constant ap_const_lv32_C3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000011";
constant ap_const_lv32_D2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010010";
constant ap_const_lv32_E1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100001";
constant ap_const_lv32_F0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_10E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001110";
constant ap_const_lv32_11D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011101";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_49 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001001";
constant ap_const_lv32_4C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001100";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_6A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101010";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_88 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001000";
constant ap_const_lv32_97 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010111";
constant ap_const_lv32_A6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100110";
constant ap_const_lv32_B5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110101";
constant ap_const_lv32_C4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000100";
constant ap_const_lv32_D3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010011";
constant ap_const_lv32_E2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100010";
constant ap_const_lv32_F1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110001";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_10F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001111";
constant ap_const_lv32_11E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011110";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_6B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101011";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_89 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001001";
constant ap_const_lv32_98 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011000";
constant ap_const_lv32_A7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100111";
constant ap_const_lv32_B6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110110";
constant ap_const_lv32_C5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000101";
constant ap_const_lv32_D4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010100";
constant ap_const_lv32_E3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100011";
constant ap_const_lv32_F2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110010";
constant ap_const_lv32_101 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000001";
constant ap_const_lv32_110 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_5D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011101";
constant ap_const_lv32_6C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101100";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_8A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001010";
constant ap_const_lv32_99 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011001";
constant ap_const_lv32_A8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101000";
constant ap_const_lv32_B7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110111";
constant ap_const_lv32_C6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000110";
constant ap_const_lv32_D5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010101";
constant ap_const_lv32_E4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100100";
constant ap_const_lv32_F3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110011";
constant ap_const_lv32_102 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000010";
constant ap_const_lv32_111 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010001";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_5E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011110";
constant ap_const_lv32_6D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101101";
constant ap_const_lv32_7C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111100";
constant ap_const_lv32_8B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001011";
constant ap_const_lv32_9A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011010";
constant ap_const_lv32_A9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101001";
constant ap_const_lv32_B8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111000";
constant ap_const_lv32_C7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000111";
constant ap_const_lv32_D6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010110";
constant ap_const_lv32_E5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100101";
constant ap_const_lv32_F4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110100";
constant ap_const_lv32_103 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000011";
constant ap_const_lv32_112 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010010";
constant ap_const_lv32_121 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100001";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_6E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101110";
constant ap_const_lv32_7D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111101";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_9B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011011";
constant ap_const_lv32_AA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101010";
constant ap_const_lv32_B9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111001";
constant ap_const_lv32_C8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001000";
constant ap_const_lv32_D7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010111";
constant ap_const_lv32_E6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100110";
constant ap_const_lv32_F5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110101";
constant ap_const_lv32_104 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000100";
constant ap_const_lv32_113 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010011";
constant ap_const_lv32_122 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100010";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_6F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101111";
constant ap_const_lv32_7E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111110";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv32_9C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011100";
constant ap_const_lv32_AB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101011";
constant ap_const_lv32_BA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111010";
constant ap_const_lv32_C9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001001";
constant ap_const_lv32_D8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011000";
constant ap_const_lv32_E7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100111";
constant ap_const_lv32_F6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110110";
constant ap_const_lv32_105 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000101";
constant ap_const_lv32_114 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010100";
constant ap_const_lv32_123 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100011";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv32_9D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011101";
constant ap_const_lv32_AC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101100";
constant ap_const_lv32_BB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111011";
constant ap_const_lv32_CA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001010";
constant ap_const_lv32_D9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011001";
constant ap_const_lv32_E8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101000";
constant ap_const_lv32_F7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110111";
constant ap_const_lv32_106 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000110";
constant ap_const_lv32_115 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010101";
constant ap_const_lv32_124 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100100";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv32_71 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110001";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
constant ap_const_lv32_9E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011110";
constant ap_const_lv32_AD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101101";
constant ap_const_lv32_BC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111100";
constant ap_const_lv32_CB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001011";
constant ap_const_lv32_DA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011010";
constant ap_const_lv32_E9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101001";
constant ap_const_lv32_F8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111000";
constant ap_const_lv32_107 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000111";
constant ap_const_lv32_116 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010110";
constant ap_const_lv32_125 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100101";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_54 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010100";
constant ap_const_lv32_63 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100011";
constant ap_const_lv32_72 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110010";
constant ap_const_lv32_81 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000001";
constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_AE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101110";
constant ap_const_lv32_BD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111101";
constant ap_const_lv32_CC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001100";
constant ap_const_lv32_DB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011011";
constant ap_const_lv32_EA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101010";
constant ap_const_lv32_F9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111001";
constant ap_const_lv32_108 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001000";
constant ap_const_lv32_117 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100010111";
constant ap_const_lv32_126 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100110";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_55 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010101";
constant ap_const_lv32_64 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100100";
constant ap_const_lv32_73 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110011";
constant ap_const_lv32_82 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000010";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_AF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101111";
constant ap_const_lv32_BE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111110";
constant ap_const_lv32_CD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001101";
constant ap_const_lv32_DC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011100";
constant ap_const_lv32_EB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101011";
constant ap_const_lv32_FA : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111010";
constant ap_const_lv32_109 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001001";
constant ap_const_lv32_118 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011000";
constant ap_const_lv32_127 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100111";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_65 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100101";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv32_83 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000011";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_A1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100001";
constant ap_const_lv32_B0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_CE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001110";
constant ap_const_lv32_DD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011101";
constant ap_const_lv32_EC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101100";
constant ap_const_lv32_FB : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111011";
constant ap_const_lv32_10A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001010";
constant ap_const_lv32_119 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011001";
constant ap_const_lv32_128 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101000";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_66 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100110";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv32_84 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000100";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv32_A2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100010";
constant ap_const_lv32_B1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110001";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_CF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001111";
constant ap_const_lv32_DE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011110";
constant ap_const_lv32_ED : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101101";
constant ap_const_lv32_FC : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111100";
constant ap_const_lv32_10B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001011";
constant ap_const_lv32_11A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011010";
constant ap_const_lv32_129 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101001";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
constant ap_const_lv32_67 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100111";
constant ap_const_lv32_76 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110110";
constant ap_const_lv32_85 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000101";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv32_A3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100011";
constant ap_const_lv32_B2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110010";
constant ap_const_lv32_C1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000001";
constant ap_const_lv32_D0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_EE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101110";
constant ap_const_lv32_FD : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111101";
constant ap_const_lv32_10C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001100";
constant ap_const_lv32_11B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011011";
constant ap_const_lv32_12A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101010";
constant ap_const_lv32_47 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000111";
constant ap_const_lv32_12C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_12E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101110";
constant ap_const_lv32_131 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110001";
constant ap_const_lv32_134 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110100";
constant ap_const_lv32_137 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110111";
constant ap_const_lv32_13A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111010";
constant ap_const_lv32_13D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111101";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_143 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000011";
constant ap_const_lv32_146 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000110";
constant ap_const_lv32_149 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001001";
constant ap_const_lv32_14C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001100";
constant ap_const_lv32_14F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001111";
constant ap_const_lv32_152 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010010";
constant ap_const_lv32_155 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010101";
constant ap_const_lv32_158 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011000";
constant ap_const_lv32_15B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011011";
constant ap_const_lv32_15E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011110";
constant ap_const_lv32_161 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100001";
constant ap_const_lv32_164 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100100";
constant ap_const_lv32_167 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100111";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010";
constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011";
constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_41 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000001";
constant ap_const_lv32_42 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000010";
constant ap_const_lv32_43 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000011";
constant ap_const_lv32_44 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000100";
constant ap_const_lv32_45 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000101";
constant ap_const_lv32_46 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000110";
constant ap_const_lv32_4A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001010";
constant ap_const_lv32_59 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011001";
constant ap_const_lv32_68 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101000";
constant ap_const_lv32_77 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110111";
constant ap_const_lv32_86 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000110";
constant ap_const_lv32_95 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010101";
constant ap_const_lv32_A4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100100";
constant ap_const_lv32_B3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110011";
constant ap_const_lv32_C2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000010";
constant ap_const_lv32_D1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010001";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_EF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101111";
constant ap_const_lv32_12B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101011";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv64_10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000";
constant ap_const_lv64_12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_const_lv64_11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010001";
constant ap_const_lv64_13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010011";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011";
constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101";
constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110";
constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111";
constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_const_lv64_9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001001";
constant ap_const_lv64_A : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001010";
constant ap_const_lv64_B : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001011";
constant ap_const_lv64_C : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001100";
constant ap_const_lv64_D : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001101";
constant ap_const_lv64_E : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001110";
constant ap_const_lv64_F : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001111";
constant ap_const_lv32_FE : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111110";
constant ap_const_lv32_10D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100001101";
constant ap_const_lv32_11C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011100";
constant ap_const_lv32_12F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101111";
constant ap_const_lv32_130 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110000";
constant ap_const_lv32_132 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110010";
constant ap_const_lv32_133 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110011";
constant ap_const_lv32_135 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110101";
constant ap_const_lv32_136 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100110110";
constant ap_const_lv32_138 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111000";
constant ap_const_lv32_139 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111001";
constant ap_const_lv32_13B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111011";
constant ap_const_lv32_13C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111100";
constant ap_const_lv32_13E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111110";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_141 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000001";
constant ap_const_lv32_142 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000010";
constant ap_const_lv32_144 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000100";
constant ap_const_lv32_145 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000101";
constant ap_const_lv32_147 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000111";
constant ap_const_lv32_148 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001000";
constant ap_const_lv32_14A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001010";
constant ap_const_lv32_14B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001011";
constant ap_const_lv32_14D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001101";
constant ap_const_lv32_14E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101001110";
constant ap_const_lv32_150 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010000";
constant ap_const_lv32_151 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010001";
constant ap_const_lv32_153 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010011";
constant ap_const_lv32_154 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010100";
constant ap_const_lv32_156 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010110";
constant ap_const_lv32_157 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101010111";
constant ap_const_lv32_159 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011001";
constant ap_const_lv32_15A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011010";
constant ap_const_lv32_15C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011100";
constant ap_const_lv32_15D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011101";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_162 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100010";
constant ap_const_lv32_163 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100011";
constant ap_const_lv32_165 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100101";
constant ap_const_lv32_166 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100110";
constant ap_const_lv32_168 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101101000";
constant ap_const_lv32_169 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101101001";
constant ap_const_lv32_12D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100101101";
constant ap_const_lv32_3F800000 : STD_LOGIC_VECTOR (31 downto 0) := "00111111100000000000000000000000";
constant ap_const_lv32_1E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111100000";
constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111";
constant ap_const_lv32_200 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000000000";
constant ap_const_lv32_21F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000011111";
constant ap_const_lv32_220 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000100000";
constant ap_const_lv32_23F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000111111";
constant ap_const_lv576_lc_1 : STD_LOGIC_VECTOR (575 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_1DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111011111";
constant ap_const_lv5_14 : STD_LOGIC_VECTOR (4 downto 0) := "10100";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv32_1A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110100000";
constant ap_const_lv32_1BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110111111";
constant ap_const_lv32_1C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111000000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal i1_reg_418 : STD_LOGIC_VECTOR (4 downto 0);
signal reg_669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (361 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_399 : BOOLEAN;
signal ap_sig_cseq_ST_st73_fsm_72 : STD_LOGIC;
signal ap_sig_bdd_410 : BOOLEAN;
signal ap_sig_cseq_ST_st76_fsm_75 : STD_LOGIC;
signal ap_sig_bdd_419 : BOOLEAN;
signal ap_sig_cseq_ST_st91_fsm_90 : STD_LOGIC;
signal ap_sig_bdd_428 : BOOLEAN;
signal ap_sig_cseq_ST_st106_fsm_105 : STD_LOGIC;
signal ap_sig_bdd_437 : BOOLEAN;
signal ap_sig_cseq_ST_st121_fsm_120 : STD_LOGIC;
signal ap_sig_bdd_446 : BOOLEAN;
signal ap_sig_cseq_ST_st136_fsm_135 : STD_LOGIC;
signal ap_sig_bdd_455 : BOOLEAN;
signal ap_sig_cseq_ST_st151_fsm_150 : STD_LOGIC;
signal ap_sig_bdd_464 : BOOLEAN;
signal ap_sig_cseq_ST_st166_fsm_165 : STD_LOGIC;
signal ap_sig_bdd_473 : BOOLEAN;
signal ap_sig_cseq_ST_st181_fsm_180 : STD_LOGIC;
signal ap_sig_bdd_482 : BOOLEAN;
signal ap_sig_cseq_ST_st196_fsm_195 : STD_LOGIC;
signal ap_sig_bdd_491 : BOOLEAN;
signal ap_sig_cseq_ST_st211_fsm_210 : STD_LOGIC;
signal ap_sig_bdd_500 : BOOLEAN;
signal ap_sig_cseq_ST_st226_fsm_225 : STD_LOGIC;
signal ap_sig_bdd_509 : BOOLEAN;
signal ap_sig_cseq_ST_st241_fsm_240 : STD_LOGIC;
signal ap_sig_bdd_518 : BOOLEAN;
signal ap_sig_cseq_ST_st256_fsm_255 : STD_LOGIC;
signal ap_sig_bdd_527 : BOOLEAN;
signal ap_sig_cseq_ST_st271_fsm_270 : STD_LOGIC;
signal ap_sig_bdd_536 : BOOLEAN;
signal ap_sig_cseq_ST_st286_fsm_285 : STD_LOGIC;
signal ap_sig_bdd_545 : BOOLEAN;
signal reg_673 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_555 : BOOLEAN;
signal ap_sig_cseq_ST_st74_fsm_73 : STD_LOGIC;
signal ap_sig_bdd_563 : BOOLEAN;
signal ap_sig_cseq_ST_st77_fsm_76 : STD_LOGIC;
signal ap_sig_bdd_572 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_581 : BOOLEAN;
signal ap_sig_cseq_ST_st107_fsm_106 : STD_LOGIC;
signal ap_sig_bdd_590 : BOOLEAN;
signal ap_sig_cseq_ST_st122_fsm_121 : STD_LOGIC;
signal ap_sig_bdd_599 : BOOLEAN;
signal ap_sig_cseq_ST_st137_fsm_136 : STD_LOGIC;
signal ap_sig_bdd_608 : BOOLEAN;
signal ap_sig_cseq_ST_st152_fsm_151 : STD_LOGIC;
signal ap_sig_bdd_617 : BOOLEAN;
signal ap_sig_cseq_ST_st167_fsm_166 : STD_LOGIC;
signal ap_sig_bdd_626 : BOOLEAN;
signal ap_sig_cseq_ST_st182_fsm_181 : STD_LOGIC;
signal ap_sig_bdd_635 : BOOLEAN;
signal ap_sig_cseq_ST_st197_fsm_196 : STD_LOGIC;
signal ap_sig_bdd_644 : BOOLEAN;
signal ap_sig_cseq_ST_st212_fsm_211 : STD_LOGIC;
signal ap_sig_bdd_653 : BOOLEAN;
signal ap_sig_cseq_ST_st227_fsm_226 : STD_LOGIC;
signal ap_sig_bdd_662 : BOOLEAN;
signal ap_sig_cseq_ST_st242_fsm_241 : STD_LOGIC;
signal ap_sig_bdd_671 : BOOLEAN;
signal ap_sig_cseq_ST_st257_fsm_256 : STD_LOGIC;
signal ap_sig_bdd_680 : BOOLEAN;
signal ap_sig_cseq_ST_st272_fsm_271 : STD_LOGIC;
signal ap_sig_bdd_689 : BOOLEAN;
signal ap_sig_cseq_ST_st287_fsm_286 : STD_LOGIC;
signal ap_sig_bdd_698 : BOOLEAN;
signal reg_677 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_708 : BOOLEAN;
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_716 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_725 : BOOLEAN;
signal ap_sig_cseq_ST_st108_fsm_107 : STD_LOGIC;
signal ap_sig_bdd_734 : BOOLEAN;
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_743 : BOOLEAN;
signal ap_sig_cseq_ST_st138_fsm_137 : STD_LOGIC;
signal ap_sig_bdd_752 : BOOLEAN;
signal ap_sig_cseq_ST_st153_fsm_152 : STD_LOGIC;
signal ap_sig_bdd_761 : BOOLEAN;
signal ap_sig_cseq_ST_st168_fsm_167 : STD_LOGIC;
signal ap_sig_bdd_770 : BOOLEAN;
signal ap_sig_cseq_ST_st183_fsm_182 : STD_LOGIC;
signal ap_sig_bdd_779 : BOOLEAN;
signal ap_sig_cseq_ST_st198_fsm_197 : STD_LOGIC;
signal ap_sig_bdd_788 : BOOLEAN;
signal ap_sig_cseq_ST_st213_fsm_212 : STD_LOGIC;
signal ap_sig_bdd_797 : BOOLEAN;
signal ap_sig_cseq_ST_st228_fsm_227 : STD_LOGIC;
signal ap_sig_bdd_806 : BOOLEAN;
signal ap_sig_cseq_ST_st243_fsm_242 : STD_LOGIC;
signal ap_sig_bdd_815 : BOOLEAN;
signal ap_sig_cseq_ST_st258_fsm_257 : STD_LOGIC;
signal ap_sig_bdd_824 : BOOLEAN;
signal ap_sig_cseq_ST_st273_fsm_272 : STD_LOGIC;
signal ap_sig_bdd_833 : BOOLEAN;
signal ap_sig_cseq_ST_st288_fsm_287 : STD_LOGIC;
signal ap_sig_bdd_842 : BOOLEAN;
signal reg_681 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_852 : BOOLEAN;
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_860 : BOOLEAN;
signal ap_sig_cseq_ST_st94_fsm_93 : STD_LOGIC;
signal ap_sig_bdd_869 : BOOLEAN;
signal ap_sig_cseq_ST_st109_fsm_108 : STD_LOGIC;
signal ap_sig_bdd_878 : BOOLEAN;
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_887 : BOOLEAN;
signal ap_sig_cseq_ST_st139_fsm_138 : STD_LOGIC;
signal ap_sig_bdd_896 : BOOLEAN;
signal ap_sig_cseq_ST_st154_fsm_153 : STD_LOGIC;
signal ap_sig_bdd_905 : BOOLEAN;
signal ap_sig_cseq_ST_st169_fsm_168 : STD_LOGIC;
signal ap_sig_bdd_914 : BOOLEAN;
signal ap_sig_cseq_ST_st184_fsm_183 : STD_LOGIC;
signal ap_sig_bdd_923 : BOOLEAN;
signal ap_sig_cseq_ST_st199_fsm_198 : STD_LOGIC;
signal ap_sig_bdd_932 : BOOLEAN;
signal ap_sig_cseq_ST_st214_fsm_213 : STD_LOGIC;
signal ap_sig_bdd_941 : BOOLEAN;
signal ap_sig_cseq_ST_st229_fsm_228 : STD_LOGIC;
signal ap_sig_bdd_950 : BOOLEAN;
signal ap_sig_cseq_ST_st244_fsm_243 : STD_LOGIC;
signal ap_sig_bdd_959 : BOOLEAN;
signal ap_sig_cseq_ST_st259_fsm_258 : STD_LOGIC;
signal ap_sig_bdd_968 : BOOLEAN;
signal ap_sig_cseq_ST_st274_fsm_273 : STD_LOGIC;
signal ap_sig_bdd_977 : BOOLEAN;
signal ap_sig_cseq_ST_st289_fsm_288 : STD_LOGIC;
signal ap_sig_bdd_986 : BOOLEAN;
signal reg_685 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_996 : BOOLEAN;
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_1004 : BOOLEAN;
signal ap_sig_cseq_ST_st95_fsm_94 : STD_LOGIC;
signal ap_sig_bdd_1013 : BOOLEAN;
signal ap_sig_cseq_ST_st110_fsm_109 : STD_LOGIC;
signal ap_sig_bdd_1022 : BOOLEAN;
signal ap_sig_cseq_ST_st125_fsm_124 : STD_LOGIC;
signal ap_sig_bdd_1031 : BOOLEAN;
signal ap_sig_cseq_ST_st140_fsm_139 : STD_LOGIC;
signal ap_sig_bdd_1040 : BOOLEAN;
signal ap_sig_cseq_ST_st155_fsm_154 : STD_LOGIC;
signal ap_sig_bdd_1049 : BOOLEAN;
signal ap_sig_cseq_ST_st170_fsm_169 : STD_LOGIC;
signal ap_sig_bdd_1058 : BOOLEAN;
signal ap_sig_cseq_ST_st185_fsm_184 : STD_LOGIC;
signal ap_sig_bdd_1067 : BOOLEAN;
signal ap_sig_cseq_ST_st200_fsm_199 : STD_LOGIC;
signal ap_sig_bdd_1076 : BOOLEAN;
signal ap_sig_cseq_ST_st215_fsm_214 : STD_LOGIC;
signal ap_sig_bdd_1085 : BOOLEAN;
signal ap_sig_cseq_ST_st230_fsm_229 : STD_LOGIC;
signal ap_sig_bdd_1094 : BOOLEAN;
signal ap_sig_cseq_ST_st245_fsm_244 : STD_LOGIC;
signal ap_sig_bdd_1103 : BOOLEAN;
signal ap_sig_cseq_ST_st260_fsm_259 : STD_LOGIC;
signal ap_sig_bdd_1112 : BOOLEAN;
signal ap_sig_cseq_ST_st275_fsm_274 : STD_LOGIC;
signal ap_sig_bdd_1121 : BOOLEAN;
signal ap_sig_cseq_ST_st290_fsm_289 : STD_LOGIC;
signal ap_sig_bdd_1130 : BOOLEAN;
signal reg_689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_1140 : BOOLEAN;
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_1148 : BOOLEAN;
signal ap_sig_cseq_ST_st96_fsm_95 : STD_LOGIC;
signal ap_sig_bdd_1157 : BOOLEAN;
signal ap_sig_cseq_ST_st111_fsm_110 : STD_LOGIC;
signal ap_sig_bdd_1166 : BOOLEAN;
signal ap_sig_cseq_ST_st126_fsm_125 : STD_LOGIC;
signal ap_sig_bdd_1175 : BOOLEAN;
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_1184 : BOOLEAN;
signal ap_sig_cseq_ST_st156_fsm_155 : STD_LOGIC;
signal ap_sig_bdd_1193 : BOOLEAN;
signal ap_sig_cseq_ST_st171_fsm_170 : STD_LOGIC;
signal ap_sig_bdd_1202 : BOOLEAN;
signal ap_sig_cseq_ST_st186_fsm_185 : STD_LOGIC;
signal ap_sig_bdd_1211 : BOOLEAN;
signal ap_sig_cseq_ST_st201_fsm_200 : STD_LOGIC;
signal ap_sig_bdd_1220 : BOOLEAN;
signal ap_sig_cseq_ST_st216_fsm_215 : STD_LOGIC;
signal ap_sig_bdd_1229 : BOOLEAN;
signal ap_sig_cseq_ST_st231_fsm_230 : STD_LOGIC;
signal ap_sig_bdd_1238 : BOOLEAN;
signal ap_sig_cseq_ST_st246_fsm_245 : STD_LOGIC;
signal ap_sig_bdd_1247 : BOOLEAN;
signal ap_sig_cseq_ST_st261_fsm_260 : STD_LOGIC;
signal ap_sig_bdd_1256 : BOOLEAN;
signal ap_sig_cseq_ST_st276_fsm_275 : STD_LOGIC;
signal ap_sig_bdd_1265 : BOOLEAN;
signal ap_sig_cseq_ST_st291_fsm_290 : STD_LOGIC;
signal ap_sig_bdd_1274 : BOOLEAN;
signal reg_693 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_1284 : BOOLEAN;
signal ap_sig_cseq_ST_st82_fsm_81 : STD_LOGIC;
signal ap_sig_bdd_1292 : BOOLEAN;
signal ap_sig_cseq_ST_st97_fsm_96 : STD_LOGIC;
signal ap_sig_bdd_1301 : BOOLEAN;
signal ap_sig_cseq_ST_st112_fsm_111 : STD_LOGIC;
signal ap_sig_bdd_1310 : BOOLEAN;
signal ap_sig_cseq_ST_st127_fsm_126 : STD_LOGIC;
signal ap_sig_bdd_1319 : BOOLEAN;
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_1328 : BOOLEAN;
signal ap_sig_cseq_ST_st157_fsm_156 : STD_LOGIC;
signal ap_sig_bdd_1337 : BOOLEAN;
signal ap_sig_cseq_ST_st172_fsm_171 : STD_LOGIC;
signal ap_sig_bdd_1346 : BOOLEAN;
signal ap_sig_cseq_ST_st187_fsm_186 : STD_LOGIC;
signal ap_sig_bdd_1355 : BOOLEAN;
signal ap_sig_cseq_ST_st202_fsm_201 : STD_LOGIC;
signal ap_sig_bdd_1364 : BOOLEAN;
signal ap_sig_cseq_ST_st217_fsm_216 : STD_LOGIC;
signal ap_sig_bdd_1373 : BOOLEAN;
signal ap_sig_cseq_ST_st232_fsm_231 : STD_LOGIC;
signal ap_sig_bdd_1382 : BOOLEAN;
signal ap_sig_cseq_ST_st247_fsm_246 : STD_LOGIC;
signal ap_sig_bdd_1391 : BOOLEAN;
signal ap_sig_cseq_ST_st262_fsm_261 : STD_LOGIC;
signal ap_sig_bdd_1400 : BOOLEAN;
signal ap_sig_cseq_ST_st277_fsm_276 : STD_LOGIC;
signal ap_sig_bdd_1409 : BOOLEAN;
signal ap_sig_cseq_ST_st292_fsm_291 : STD_LOGIC;
signal ap_sig_bdd_1418 : BOOLEAN;
signal reg_697 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_1428 : BOOLEAN;
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_1436 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_1445 : BOOLEAN;
signal ap_sig_cseq_ST_st113_fsm_112 : STD_LOGIC;
signal ap_sig_bdd_1454 : BOOLEAN;
signal ap_sig_cseq_ST_st128_fsm_127 : STD_LOGIC;
signal ap_sig_bdd_1463 : BOOLEAN;
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_1472 : BOOLEAN;
signal ap_sig_cseq_ST_st158_fsm_157 : STD_LOGIC;
signal ap_sig_bdd_1481 : BOOLEAN;
signal ap_sig_cseq_ST_st173_fsm_172 : STD_LOGIC;
signal ap_sig_bdd_1490 : BOOLEAN;
signal ap_sig_cseq_ST_st188_fsm_187 : STD_LOGIC;
signal ap_sig_bdd_1499 : BOOLEAN;
signal ap_sig_cseq_ST_st203_fsm_202 : STD_LOGIC;
signal ap_sig_bdd_1508 : BOOLEAN;
signal ap_sig_cseq_ST_st218_fsm_217 : STD_LOGIC;
signal ap_sig_bdd_1517 : BOOLEAN;
signal ap_sig_cseq_ST_st233_fsm_232 : STD_LOGIC;
signal ap_sig_bdd_1526 : BOOLEAN;
signal ap_sig_cseq_ST_st248_fsm_247 : STD_LOGIC;
signal ap_sig_bdd_1535 : BOOLEAN;
signal ap_sig_cseq_ST_st263_fsm_262 : STD_LOGIC;
signal ap_sig_bdd_1544 : BOOLEAN;
signal ap_sig_cseq_ST_st278_fsm_277 : STD_LOGIC;
signal ap_sig_bdd_1553 : BOOLEAN;
signal ap_sig_cseq_ST_st293_fsm_292 : STD_LOGIC;
signal ap_sig_bdd_1562 : BOOLEAN;
signal reg_701 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_1572 : BOOLEAN;
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_1580 : BOOLEAN;
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_1589 : BOOLEAN;
signal ap_sig_cseq_ST_st114_fsm_113 : STD_LOGIC;
signal ap_sig_bdd_1598 : BOOLEAN;
signal ap_sig_cseq_ST_st129_fsm_128 : STD_LOGIC;
signal ap_sig_bdd_1607 : BOOLEAN;
signal ap_sig_cseq_ST_st144_fsm_143 : STD_LOGIC;
signal ap_sig_bdd_1616 : BOOLEAN;
signal ap_sig_cseq_ST_st159_fsm_158 : STD_LOGIC;
signal ap_sig_bdd_1625 : BOOLEAN;
signal ap_sig_cseq_ST_st174_fsm_173 : STD_LOGIC;
signal ap_sig_bdd_1634 : BOOLEAN;
signal ap_sig_cseq_ST_st189_fsm_188 : STD_LOGIC;
signal ap_sig_bdd_1643 : BOOLEAN;
signal ap_sig_cseq_ST_st204_fsm_203 : STD_LOGIC;
signal ap_sig_bdd_1652 : BOOLEAN;
signal ap_sig_cseq_ST_st219_fsm_218 : STD_LOGIC;
signal ap_sig_bdd_1661 : BOOLEAN;
signal ap_sig_cseq_ST_st234_fsm_233 : STD_LOGIC;
signal ap_sig_bdd_1670 : BOOLEAN;
signal ap_sig_cseq_ST_st249_fsm_248 : STD_LOGIC;
signal ap_sig_bdd_1679 : BOOLEAN;
signal ap_sig_cseq_ST_st264_fsm_263 : STD_LOGIC;
signal ap_sig_bdd_1688 : BOOLEAN;
signal ap_sig_cseq_ST_st279_fsm_278 : STD_LOGIC;
signal ap_sig_bdd_1697 : BOOLEAN;
signal ap_sig_cseq_ST_st294_fsm_293 : STD_LOGIC;
signal ap_sig_bdd_1706 : BOOLEAN;
signal reg_705 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_1716 : BOOLEAN;
signal ap_sig_cseq_ST_st85_fsm_84 : STD_LOGIC;
signal ap_sig_bdd_1724 : BOOLEAN;
signal ap_sig_cseq_ST_st100_fsm_99 : STD_LOGIC;
signal ap_sig_bdd_1733 : BOOLEAN;
signal ap_sig_cseq_ST_st115_fsm_114 : STD_LOGIC;
signal ap_sig_bdd_1742 : BOOLEAN;
signal ap_sig_cseq_ST_st130_fsm_129 : STD_LOGIC;
signal ap_sig_bdd_1751 : BOOLEAN;
signal ap_sig_cseq_ST_st145_fsm_144 : STD_LOGIC;
signal ap_sig_bdd_1760 : BOOLEAN;
signal ap_sig_cseq_ST_st160_fsm_159 : STD_LOGIC;
signal ap_sig_bdd_1769 : BOOLEAN;
signal ap_sig_cseq_ST_st175_fsm_174 : STD_LOGIC;
signal ap_sig_bdd_1778 : BOOLEAN;
signal ap_sig_cseq_ST_st190_fsm_189 : STD_LOGIC;
signal ap_sig_bdd_1787 : BOOLEAN;
signal ap_sig_cseq_ST_st205_fsm_204 : STD_LOGIC;
signal ap_sig_bdd_1796 : BOOLEAN;
signal ap_sig_cseq_ST_st220_fsm_219 : STD_LOGIC;
signal ap_sig_bdd_1805 : BOOLEAN;
signal ap_sig_cseq_ST_st235_fsm_234 : STD_LOGIC;
signal ap_sig_bdd_1814 : BOOLEAN;
signal ap_sig_cseq_ST_st250_fsm_249 : STD_LOGIC;
signal ap_sig_bdd_1823 : BOOLEAN;
signal ap_sig_cseq_ST_st265_fsm_264 : STD_LOGIC;
signal ap_sig_bdd_1832 : BOOLEAN;
signal ap_sig_cseq_ST_st280_fsm_279 : STD_LOGIC;
signal ap_sig_bdd_1841 : BOOLEAN;
signal ap_sig_cseq_ST_st295_fsm_294 : STD_LOGIC;
signal ap_sig_bdd_1850 : BOOLEAN;
signal reg_709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_1860 : BOOLEAN;
signal ap_sig_cseq_ST_st86_fsm_85 : STD_LOGIC;
signal ap_sig_bdd_1868 : BOOLEAN;
signal ap_sig_cseq_ST_st101_fsm_100 : STD_LOGIC;
signal ap_sig_bdd_1877 : BOOLEAN;
signal ap_sig_cseq_ST_st116_fsm_115 : STD_LOGIC;
signal ap_sig_bdd_1886 : BOOLEAN;
signal ap_sig_cseq_ST_st131_fsm_130 : STD_LOGIC;
signal ap_sig_bdd_1895 : BOOLEAN;
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_1904 : BOOLEAN;
signal ap_sig_cseq_ST_st161_fsm_160 : STD_LOGIC;
signal ap_sig_bdd_1913 : BOOLEAN;
signal ap_sig_cseq_ST_st176_fsm_175 : STD_LOGIC;
signal ap_sig_bdd_1922 : BOOLEAN;
signal ap_sig_cseq_ST_st191_fsm_190 : STD_LOGIC;
signal ap_sig_bdd_1931 : BOOLEAN;
signal ap_sig_cseq_ST_st206_fsm_205 : STD_LOGIC;
signal ap_sig_bdd_1940 : BOOLEAN;
signal ap_sig_cseq_ST_st221_fsm_220 : STD_LOGIC;
signal ap_sig_bdd_1949 : BOOLEAN;
signal ap_sig_cseq_ST_st236_fsm_235 : STD_LOGIC;
signal ap_sig_bdd_1958 : BOOLEAN;
signal ap_sig_cseq_ST_st251_fsm_250 : STD_LOGIC;
signal ap_sig_bdd_1967 : BOOLEAN;
signal ap_sig_cseq_ST_st266_fsm_265 : STD_LOGIC;
signal ap_sig_bdd_1976 : BOOLEAN;
signal ap_sig_cseq_ST_st281_fsm_280 : STD_LOGIC;
signal ap_sig_bdd_1985 : BOOLEAN;
signal ap_sig_cseq_ST_st296_fsm_295 : STD_LOGIC;
signal ap_sig_bdd_1994 : BOOLEAN;
signal reg_713 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_2004 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_2012 : BOOLEAN;
signal ap_sig_cseq_ST_st102_fsm_101 : STD_LOGIC;
signal ap_sig_bdd_2021 : BOOLEAN;
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_2030 : BOOLEAN;
signal ap_sig_cseq_ST_st132_fsm_131 : STD_LOGIC;
signal ap_sig_bdd_2039 : BOOLEAN;
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_2048 : BOOLEAN;
signal ap_sig_cseq_ST_st162_fsm_161 : STD_LOGIC;
signal ap_sig_bdd_2057 : BOOLEAN;
signal ap_sig_cseq_ST_st177_fsm_176 : STD_LOGIC;
signal ap_sig_bdd_2066 : BOOLEAN;
signal ap_sig_cseq_ST_st192_fsm_191 : STD_LOGIC;
signal ap_sig_bdd_2075 : BOOLEAN;
signal ap_sig_cseq_ST_st207_fsm_206 : STD_LOGIC;
signal ap_sig_bdd_2084 : BOOLEAN;
signal ap_sig_cseq_ST_st222_fsm_221 : STD_LOGIC;
signal ap_sig_bdd_2093 : BOOLEAN;
signal ap_sig_cseq_ST_st237_fsm_236 : STD_LOGIC;
signal ap_sig_bdd_2102 : BOOLEAN;
signal ap_sig_cseq_ST_st252_fsm_251 : STD_LOGIC;
signal ap_sig_bdd_2111 : BOOLEAN;
signal ap_sig_cseq_ST_st267_fsm_266 : STD_LOGIC;
signal ap_sig_bdd_2120 : BOOLEAN;
signal ap_sig_cseq_ST_st282_fsm_281 : STD_LOGIC;
signal ap_sig_bdd_2129 : BOOLEAN;
signal ap_sig_cseq_ST_st297_fsm_296 : STD_LOGIC;
signal ap_sig_bdd_2138 : BOOLEAN;
signal reg_717 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_2148 : BOOLEAN;
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_2156 : BOOLEAN;
signal ap_sig_cseq_ST_st103_fsm_102 : STD_LOGIC;
signal ap_sig_bdd_2165 : BOOLEAN;
signal ap_sig_cseq_ST_st118_fsm_117 : STD_LOGIC;
signal ap_sig_bdd_2174 : BOOLEAN;
signal ap_sig_cseq_ST_st133_fsm_132 : STD_LOGIC;
signal ap_sig_bdd_2183 : BOOLEAN;
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_2192 : BOOLEAN;
signal ap_sig_cseq_ST_st163_fsm_162 : STD_LOGIC;
signal ap_sig_bdd_2201 : BOOLEAN;
signal ap_sig_cseq_ST_st178_fsm_177 : STD_LOGIC;
signal ap_sig_bdd_2210 : BOOLEAN;
signal ap_sig_cseq_ST_st193_fsm_192 : STD_LOGIC;
signal ap_sig_bdd_2219 : BOOLEAN;
signal ap_sig_cseq_ST_st208_fsm_207 : STD_LOGIC;
signal ap_sig_bdd_2228 : BOOLEAN;
signal ap_sig_cseq_ST_st223_fsm_222 : STD_LOGIC;
signal ap_sig_bdd_2237 : BOOLEAN;
signal ap_sig_cseq_ST_st238_fsm_237 : STD_LOGIC;
signal ap_sig_bdd_2246 : BOOLEAN;
signal ap_sig_cseq_ST_st253_fsm_252 : STD_LOGIC;
signal ap_sig_bdd_2255 : BOOLEAN;
signal ap_sig_cseq_ST_st268_fsm_267 : STD_LOGIC;
signal ap_sig_bdd_2264 : BOOLEAN;
signal ap_sig_cseq_ST_st283_fsm_282 : STD_LOGIC;
signal ap_sig_bdd_2273 : BOOLEAN;
signal ap_sig_cseq_ST_st298_fsm_297 : STD_LOGIC;
signal ap_sig_bdd_2282 : BOOLEAN;
signal reg_721 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_2292 : BOOLEAN;
signal ap_sig_cseq_ST_st89_fsm_88 : STD_LOGIC;
signal ap_sig_bdd_2300 : BOOLEAN;
signal ap_sig_cseq_ST_st104_fsm_103 : STD_LOGIC;
signal ap_sig_bdd_2309 : BOOLEAN;
signal ap_sig_cseq_ST_st119_fsm_118 : STD_LOGIC;
signal ap_sig_bdd_2318 : BOOLEAN;
signal ap_sig_cseq_ST_st134_fsm_133 : STD_LOGIC;
signal ap_sig_bdd_2327 : BOOLEAN;
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_2336 : BOOLEAN;
signal ap_sig_cseq_ST_st164_fsm_163 : STD_LOGIC;
signal ap_sig_bdd_2345 : BOOLEAN;
signal ap_sig_cseq_ST_st179_fsm_178 : STD_LOGIC;
signal ap_sig_bdd_2354 : BOOLEAN;
signal ap_sig_cseq_ST_st194_fsm_193 : STD_LOGIC;
signal ap_sig_bdd_2363 : BOOLEAN;
signal ap_sig_cseq_ST_st209_fsm_208 : STD_LOGIC;
signal ap_sig_bdd_2372 : BOOLEAN;
signal ap_sig_cseq_ST_st224_fsm_223 : STD_LOGIC;
signal ap_sig_bdd_2381 : BOOLEAN;
signal ap_sig_cseq_ST_st239_fsm_238 : STD_LOGIC;
signal ap_sig_bdd_2390 : BOOLEAN;
signal ap_sig_cseq_ST_st254_fsm_253 : STD_LOGIC;
signal ap_sig_bdd_2399 : BOOLEAN;
signal ap_sig_cseq_ST_st269_fsm_268 : STD_LOGIC;
signal ap_sig_bdd_2408 : BOOLEAN;
signal ap_sig_cseq_ST_st284_fsm_283 : STD_LOGIC;
signal ap_sig_bdd_2417 : BOOLEAN;
signal ap_sig_cseq_ST_st299_fsm_298 : STD_LOGIC;
signal ap_sig_bdd_2426 : BOOLEAN;
signal data_array_q0 : STD_LOGIC_VECTOR (575 downto 0);
signal reg_725 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_sig_cseq_ST_st72_fsm_71 : STD_LOGIC;
signal ap_sig_bdd_2437 : BOOLEAN;
signal ap_reg_ppstg_reg_725_pp0_it2 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it23 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it24 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it25 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it26 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it27 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it28 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it29 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it30 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it31 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it32 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it33 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it34 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it35 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it36 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it37 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it38 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it39 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it40 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it41 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it42 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it43 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it44 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it45 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it46 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it47 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it48 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it49 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it50 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it51 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it52 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it53 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it54 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it55 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it56 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it57 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it58 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it59 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it60 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it61 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it62 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it63 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it64 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it65 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it66 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it67 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it68 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it69 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it70 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it71 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it72 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it73 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it74 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it75 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it76 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it77 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it78 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it79 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it80 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it81 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it82 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it83 : STD_LOGIC := '0';
signal ap_reg_ppstg_reg_725_pp0_it3 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it4 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it5 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it6 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it7 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it8 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it9 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it10 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it11 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it12 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it13 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it14 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it15 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it16 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it17 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it18 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it19 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it20 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it21 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it22 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it23 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it24 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it25 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it26 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it27 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it28 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it29 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it30 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it31 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it32 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it33 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it34 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it35 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it36 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it37 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it38 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it39 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it40 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it41 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it42 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it43 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it44 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it45 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it46 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it47 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it48 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it49 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it50 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it51 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it52 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it53 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it54 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it55 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it56 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it57 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it58 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it59 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it60 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it61 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it62 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it63 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it64 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it65 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it66 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it67 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it68 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it69 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it70 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it71 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it72 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it73 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it74 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it75 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it76 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it77 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it78 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it79 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it80 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_reg_725_pp0_it81 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_300 : STD_LOGIC;
signal ap_sig_bdd_2694 : BOOLEAN;
signal exitcond2_reg_3854 : STD_LOGIC_VECTOR (0 downto 0);
signal reg_729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st386_fsm_302 : STD_LOGIC;
signal ap_sig_bdd_2708 : BOOLEAN;
signal ap_sig_ioackin_outs_TREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st389_fsm_305 : STD_LOGIC;
signal ap_sig_bdd_2719 : BOOLEAN;
signal ap_sig_cseq_ST_st392_fsm_308 : STD_LOGIC;
signal ap_sig_bdd_2728 : BOOLEAN;
signal ap_sig_cseq_ST_st395_fsm_311 : STD_LOGIC;
signal ap_sig_bdd_2737 : BOOLEAN;
signal ap_sig_cseq_ST_st398_fsm_314 : STD_LOGIC;
signal ap_sig_bdd_2746 : BOOLEAN;
signal ap_sig_cseq_ST_st401_fsm_317 : STD_LOGIC;
signal ap_sig_bdd_2755 : BOOLEAN;
signal ap_sig_cseq_ST_st404_fsm_320 : STD_LOGIC;
signal ap_sig_bdd_2764 : BOOLEAN;
signal ap_sig_cseq_ST_st407_fsm_323 : STD_LOGIC;
signal ap_sig_bdd_2773 : BOOLEAN;
signal ap_sig_cseq_ST_st410_fsm_326 : STD_LOGIC;
signal ap_sig_bdd_2782 : BOOLEAN;
signal ap_sig_cseq_ST_st413_fsm_329 : STD_LOGIC;
signal ap_sig_bdd_2791 : BOOLEAN;
signal ap_sig_cseq_ST_st416_fsm_332 : STD_LOGIC;
signal ap_sig_bdd_2800 : BOOLEAN;
signal ap_sig_cseq_ST_st419_fsm_335 : STD_LOGIC;
signal ap_sig_bdd_2809 : BOOLEAN;
signal ap_sig_cseq_ST_st422_fsm_338 : STD_LOGIC;
signal ap_sig_bdd_2818 : BOOLEAN;
signal ap_sig_cseq_ST_st425_fsm_341 : STD_LOGIC;
signal ap_sig_bdd_2827 : BOOLEAN;
signal ap_sig_cseq_ST_st428_fsm_344 : STD_LOGIC;
signal ap_sig_bdd_2836 : BOOLEAN;
signal ap_sig_cseq_ST_st431_fsm_347 : STD_LOGIC;
signal ap_sig_bdd_2845 : BOOLEAN;
signal ap_sig_cseq_ST_st434_fsm_350 : STD_LOGIC;
signal ap_sig_bdd_2854 : BOOLEAN;
signal ap_sig_cseq_ST_st437_fsm_353 : STD_LOGIC;
signal ap_sig_bdd_2863 : BOOLEAN;
signal ap_sig_cseq_ST_st440_fsm_356 : STD_LOGIC;
signal ap_sig_bdd_2872 : BOOLEAN;
signal ap_sig_cseq_ST_st443_fsm_359 : STD_LOGIC;
signal ap_sig_bdd_2881 : BOOLEAN;
signal reg_733 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_val14_reg_3415 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_2893 : BOOLEAN;
signal ins_data_val15_reg_3420 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_2902 : BOOLEAN;
signal ins_data_val16_reg_3425 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_2911 : BOOLEAN;
signal ins_data_val17_reg_3430 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_2920 : BOOLEAN;
signal ins_data_val18_reg_3435 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_2929 : BOOLEAN;
signal ins_data_val19_reg_3440 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_2938 : BOOLEAN;
signal ins_data_val20_reg_3445 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_2947 : BOOLEAN;
signal ins_data_val21_reg_3450 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_2956 : BOOLEAN;
signal ins_data_val22_reg_3455 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_2965 : BOOLEAN;
signal ins_data_val23_reg_3460 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_2974 : BOOLEAN;
signal ins_data_val24_reg_3465 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_2983 : BOOLEAN;
signal ins_data_val25_reg_3470 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st26_fsm_25 : STD_LOGIC;
signal ap_sig_bdd_2992 : BOOLEAN;
signal ins_data_val26_reg_3475 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st27_fsm_26 : STD_LOGIC;
signal ap_sig_bdd_3001 : BOOLEAN;
signal ins_data_val27_reg_3480 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st28_fsm_27 : STD_LOGIC;
signal ap_sig_bdd_3010 : BOOLEAN;
signal ins_data_val28_reg_3485 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_3019 : BOOLEAN;
signal ins_data_val29_reg_3490 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_3028 : BOOLEAN;
signal ins_data_val30_reg_3495 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st31_fsm_30 : STD_LOGIC;
signal ap_sig_bdd_3037 : BOOLEAN;
signal ins_data_val31_reg_3500 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st32_fsm_31 : STD_LOGIC;
signal ap_sig_bdd_3046 : BOOLEAN;
signal ins_data_val32_reg_3505 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st33_fsm_32 : STD_LOGIC;
signal ap_sig_bdd_3055 : BOOLEAN;
signal ins_data_val33_reg_3510 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st34_fsm_33 : STD_LOGIC;
signal ap_sig_bdd_3064 : BOOLEAN;
signal ins_data_val34_reg_3515 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st35_fsm_34 : STD_LOGIC;
signal ap_sig_bdd_3073 : BOOLEAN;
signal ins_data_val35_reg_3520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st36_fsm_35 : STD_LOGIC;
signal ap_sig_bdd_3082 : BOOLEAN;
signal ins_data_val36_reg_3525 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st37_fsm_36 : STD_LOGIC;
signal ap_sig_bdd_3091 : BOOLEAN;
signal ins_data_val37_reg_3530 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st38_fsm_37 : STD_LOGIC;
signal ap_sig_bdd_3100 : BOOLEAN;
signal ins_data_val38_reg_3535 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st39_fsm_38 : STD_LOGIC;
signal ap_sig_bdd_3109 : BOOLEAN;
signal ins_data_val39_reg_3540 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st40_fsm_39 : STD_LOGIC;
signal ap_sig_bdd_3118 : BOOLEAN;
signal ins_data_val40_reg_3545 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st41_fsm_40 : STD_LOGIC;
signal ap_sig_bdd_3127 : BOOLEAN;
signal ins_data_val41_reg_3550 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st42_fsm_41 : STD_LOGIC;
signal ap_sig_bdd_3136 : BOOLEAN;
signal ins_data_val42_reg_3555 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st43_fsm_42 : STD_LOGIC;
signal ap_sig_bdd_3145 : BOOLEAN;
signal ins_data_val43_reg_3560 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st44_fsm_43 : STD_LOGIC;
signal ap_sig_bdd_3154 : BOOLEAN;
signal ins_data_val44_reg_3565 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st45_fsm_44 : STD_LOGIC;
signal ap_sig_bdd_3163 : BOOLEAN;
signal ins_data_val45_reg_3570 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st46_fsm_45 : STD_LOGIC;
signal ap_sig_bdd_3172 : BOOLEAN;
signal ins_data_val46_reg_3575 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st47_fsm_46 : STD_LOGIC;
signal ap_sig_bdd_3181 : BOOLEAN;
signal ins_data_val47_reg_3580 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st48_fsm_47 : STD_LOGIC;
signal ap_sig_bdd_3190 : BOOLEAN;
signal ins_data_val48_reg_3585 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st49_fsm_48 : STD_LOGIC;
signal ap_sig_bdd_3199 : BOOLEAN;
signal ins_data_val49_reg_3590 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st50_fsm_49 : STD_LOGIC;
signal ap_sig_bdd_3208 : BOOLEAN;
signal ins_data_val50_reg_3595 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st51_fsm_50 : STD_LOGIC;
signal ap_sig_bdd_3217 : BOOLEAN;
signal ins_data_val51_reg_3600 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st52_fsm_51 : STD_LOGIC;
signal ap_sig_bdd_3226 : BOOLEAN;
signal ins_data_val52_reg_3605 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st53_fsm_52 : STD_LOGIC;
signal ap_sig_bdd_3235 : BOOLEAN;
signal ins_data_val53_reg_3610 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st54_fsm_53 : STD_LOGIC;
signal ap_sig_bdd_3244 : BOOLEAN;
signal ins_data_val54_reg_3615 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st55_fsm_54 : STD_LOGIC;
signal ap_sig_bdd_3253 : BOOLEAN;
signal ins_data_val55_reg_3620 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st56_fsm_55 : STD_LOGIC;
signal ap_sig_bdd_3262 : BOOLEAN;
signal ins_data_val56_reg_3625 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st57_fsm_56 : STD_LOGIC;
signal ap_sig_bdd_3271 : BOOLEAN;
signal ins_data_val57_reg_3630 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st58_fsm_57 : STD_LOGIC;
signal ap_sig_bdd_3280 : BOOLEAN;
signal ins_data_val58_reg_3635 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st59_fsm_58 : STD_LOGIC;
signal ap_sig_bdd_3289 : BOOLEAN;
signal ins_data_val59_reg_3640 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st60_fsm_59 : STD_LOGIC;
signal ap_sig_bdd_3298 : BOOLEAN;
signal ins_data_val60_reg_3645 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st61_fsm_60 : STD_LOGIC;
signal ap_sig_bdd_3307 : BOOLEAN;
signal ins_data_val61_reg_3650 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st62_fsm_61 : STD_LOGIC;
signal ap_sig_bdd_3316 : BOOLEAN;
signal ins_data_val62_reg_3655 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st63_fsm_62 : STD_LOGIC;
signal ap_sig_bdd_3325 : BOOLEAN;
signal ins_data_val63_reg_3660 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st64_fsm_63 : STD_LOGIC;
signal ap_sig_bdd_3334 : BOOLEAN;
signal ins_data_val64_reg_3665 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st65_fsm_64 : STD_LOGIC;
signal ap_sig_bdd_3343 : BOOLEAN;
signal ins_data_val65_reg_3670 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st66_fsm_65 : STD_LOGIC;
signal ap_sig_bdd_3352 : BOOLEAN;
signal ins_data_val66_reg_3675 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st67_fsm_66 : STD_LOGIC;
signal ap_sig_bdd_3361 : BOOLEAN;
signal ins_data_val67_reg_3680 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st68_fsm_67 : STD_LOGIC;
signal ap_sig_bdd_3370 : BOOLEAN;
signal ins_data_val68_reg_3685 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st69_fsm_68 : STD_LOGIC;
signal ap_sig_bdd_3379 : BOOLEAN;
signal ins_data_val69_reg_3690 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st70_fsm_69 : STD_LOGIC;
signal ap_sig_bdd_3388 : BOOLEAN;
signal ins_data_val70_reg_3695 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st71_fsm_70 : STD_LOGIC;
signal ap_sig_bdd_3397 : BOOLEAN;
signal data_array_addr_16_gep_fu_244_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_16_reg_3700 : STD_LOGIC_VECTOR (4 downto 0);
signal ins_data_val71_reg_3706 : STD_LOGIC_VECTOR (31 downto 0);
signal data_array_addr_18_gep_fu_256_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_18_reg_3711 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_gep_fu_264_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_reg_3717 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_load_2_reg_3722 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_addr_2_gep_fu_272_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_2_reg_3727 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_4_gep_fu_280_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_4_reg_3732 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st75_fsm_74 : STD_LOGIC;
signal ap_sig_bdd_3417 : BOOLEAN;
signal data_array_addr_17_gep_fu_288_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_17_reg_3737 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_load_1_reg_3743 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_addr_19_gep_fu_296_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_19_reg_3748 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_1_gep_fu_304_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_1_reg_3754 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_load_3_reg_3759 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_addr_3_gep_fu_312_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_3_reg_3764 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_5_gep_fu_320_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_5_reg_3769 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st90_fsm_89 : STD_LOGIC;
signal ap_sig_bdd_3437 : BOOLEAN;
signal data_array_addr_6_gep_fu_328_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_6_reg_3774 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st105_fsm_104 : STD_LOGIC;
signal ap_sig_bdd_3447 : BOOLEAN;
signal data_array_addr_7_gep_fu_336_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_7_reg_3779 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st120_fsm_119 : STD_LOGIC;
signal ap_sig_bdd_3457 : BOOLEAN;
signal data_array_addr_8_gep_fu_344_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_8_reg_3784 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st135_fsm_134 : STD_LOGIC;
signal ap_sig_bdd_3467 : BOOLEAN;
signal data_array_addr_9_gep_fu_352_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_9_reg_3789 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st150_fsm_149 : STD_LOGIC;
signal ap_sig_bdd_3477 : BOOLEAN;
signal data_array_addr_10_gep_fu_360_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_10_reg_3794 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st165_fsm_164 : STD_LOGIC;
signal ap_sig_bdd_3487 : BOOLEAN;
signal data_array_addr_11_gep_fu_368_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_11_reg_3799 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st180_fsm_179 : STD_LOGIC;
signal ap_sig_bdd_3497 : BOOLEAN;
signal data_array_addr_12_gep_fu_376_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_12_reg_3804 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st195_fsm_194 : STD_LOGIC;
signal ap_sig_bdd_3507 : BOOLEAN;
signal data_array_addr_13_gep_fu_384_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_13_reg_3809 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st210_fsm_209 : STD_LOGIC;
signal ap_sig_bdd_3517 : BOOLEAN;
signal data_array_addr_14_gep_fu_392_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_14_reg_3814 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st225_fsm_224 : STD_LOGIC;
signal ap_sig_bdd_3527 : BOOLEAN;
signal data_array_addr_15_gep_fu_400_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_15_reg_3819 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_sig_cseq_ST_st240_fsm_239 : STD_LOGIC;
signal ap_sig_bdd_3537 : BOOLEAN;
signal ins_keep_V_val_reg_3824 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_sig_cseq_ST_st300_fsm_299 : STD_LOGIC;
signal ap_sig_bdd_3547 : BOOLEAN;
signal ins_strb_V_val_reg_3829 : STD_LOGIC_VECTOR (3 downto 0);
signal ins_user_V_val_reg_3834 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_last_V_val_reg_3839 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_id_V_val_reg_3844 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_dest_V_val_reg_3849 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_fu_2840_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it35 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it36 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it37 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it38 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it39 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it40 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it41 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it42 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it43 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it44 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it45 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it46 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it47 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it48 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it49 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it50 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it51 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it52 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it53 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it54 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it55 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it56 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it57 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it58 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it59 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it60 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it61 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it62 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it63 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it64 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it65 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it66 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it67 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it68 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it69 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it70 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it71 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it72 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it73 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it74 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it75 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it76 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it77 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it78 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it79 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it80 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it81 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_3854_pp0_it82 : STD_LOGIC_VECTOR (0 downto 0);
signal i_fu_2846_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_addr_20_reg_3863 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_22_fu_2857_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_reg_3869 : STD_LOGIC_VECTOR (31 downto 0);
signal v0y_assign_new_reg_3874 : STD_LOGIC_VECTOR (31 downto 0);
signal v0z_assign_new_reg_3879 : STD_LOGIC_VECTOR (31 downto 0);
signal v1x_assign_new_reg_3884 : STD_LOGIC_VECTOR (31 downto 0);
signal v1y_assign_new_reg_3889 : STD_LOGIC_VECTOR (31 downto 0);
signal v1z_assign_new_reg_3894 : STD_LOGIC_VECTOR (31 downto 0);
signal v2x_assign_new_reg_3899 : STD_LOGIC_VECTOR (31 downto 0);
signal v2y_assign_new_reg_3904 : STD_LOGIC_VECTOR (31 downto 0);
signal v2z_assign_new_reg_3909 : STD_LOGIC_VECTOR (31 downto 0);
signal rdx_assign_new_reg_3914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rdy_assign_new_reg_3919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rdz_assign_new_reg_3924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rex_assign_new_reg_3929 : STD_LOGIC_VECTOR (31 downto 0);
signal rey_assign_new_reg_3934 : STD_LOGIC_VECTOR (31 downto 0);
signal rez_assign_new_reg_3939 : STD_LOGIC_VECTOR (31 downto 0);
signal v0x_assign4_fu_3001_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal v0y_assign_fu_3007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal v0z_assign_fu_3013_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal a_reg_4010 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_4010_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal b_reg_4017 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_4017_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_reg_4024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_4024_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal d_reg_4031 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_4031_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal e_reg_4038 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_4038_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal f_reg_4045 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_4045_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_454_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_reg_4052 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_4052_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_4059 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_4059_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_462_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal l_reg_4066 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_4066_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal g_fu_3055_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal g_reg_4073 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_4073_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal h_fu_3059_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal h_reg_4080 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_4080_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_fu_3063_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_4087 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_4087_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_522_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_reg_4094 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_526_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_311_reg_4099 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_530_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_i_reg_4104 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_534_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_i_reg_4109 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_538_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_i_reg_4114 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_542_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_i_reg_4119 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_546_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_i_reg_4124 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_550_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_i_reg_4129 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_466_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_i_reg_4134 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_470_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_i_reg_4140 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_554_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_i_reg_4146 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_558_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_i_reg_4151 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_474_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_i_reg_4156 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_478_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_i_reg_4162 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_562_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_i_reg_4168 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_566_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_i_reg_4173 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_570_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_i_reg_4178 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_574_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_i_reg_4183 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_578_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_i_reg_4188 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_582_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_i_reg_4193 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_586_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_i_reg_4198 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_590_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_28_i_reg_4203 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_594_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_32_i_reg_4208 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_598_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_i_reg_4213 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_482_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_i_reg_4218 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_486_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_i_reg_4224 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_490_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_i_reg_4230 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_602_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_i_reg_4235 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_494_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_i_reg_4240 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_606_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_i_reg_4245 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_498_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_i_reg_4250 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_610_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_i_reg_4255 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_502_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_i_reg_4260 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_614_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_i_reg_4265 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal m_reg_4270 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_510_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_i_reg_4275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_514_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_i_reg_4280 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_518_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_i_reg_4285 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_630_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal im_reg_4290 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_neg_i_fu_3071_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_neg_i_reg_4297 : STD_LOGIC_VECTOR (31 downto 0);
signal beta_addr_111281129_part_set_fu_3103_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal beta_addr_111281129_part_set_reg_4307 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_address0 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_ce0 : STD_LOGIC;
signal data_array_we0 : STD_LOGIC;
signal data_array_d0 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_address1 : STD_LOGIC_VECTOR (4 downto 0);
signal data_array_ce1 : STD_LOGIC;
signal data_array_we1 : STD_LOGIC;
signal data_array_d1 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_q1 : STD_LOGIC_VECTOR (575 downto 0);
signal tmp_1_fu_2852_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st255_fsm_254 : STD_LOGIC;
signal ap_sig_bdd_5023 : BOOLEAN;
signal ap_sig_cseq_ST_st270_fsm_269 : STD_LOGIC;
signal ap_sig_bdd_5046 : BOOLEAN;
signal ap_sig_cseq_ST_st285_fsm_284 : STD_LOGIC;
signal ap_sig_bdd_5069 : BOOLEAN;
signal t_load_fu_3115_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_fu_3120_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st387_fsm_303 : STD_LOGIC;
signal ap_sig_bdd_5096 : BOOLEAN;
signal beta_load_fu_3125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st388_fsm_304 : STD_LOGIC;
signal ap_sig_bdd_5104 : BOOLEAN;
signal t_load_s_fu_3130_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_s_fu_3135_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st390_fsm_306 : STD_LOGIC;
signal ap_sig_bdd_5113 : BOOLEAN;
signal beta_load_s_fu_3140_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st391_fsm_307 : STD_LOGIC;
signal ap_sig_bdd_5121 : BOOLEAN;
signal t_load_1_fu_3145_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_1_fu_3150_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st393_fsm_309 : STD_LOGIC;
signal ap_sig_bdd_5130 : BOOLEAN;
signal beta_load_1_fu_3155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st394_fsm_310 : STD_LOGIC;
signal ap_sig_bdd_5138 : BOOLEAN;
signal t_load_2_fu_3160_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_2_fu_3165_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st396_fsm_312 : STD_LOGIC;
signal ap_sig_bdd_5147 : BOOLEAN;
signal beta_load_2_fu_3170_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st397_fsm_313 : STD_LOGIC;
signal ap_sig_bdd_5155 : BOOLEAN;
signal t_load_3_fu_3175_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_3_fu_3180_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st399_fsm_315 : STD_LOGIC;
signal ap_sig_bdd_5164 : BOOLEAN;
signal beta_load_3_fu_3185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st400_fsm_316 : STD_LOGIC;
signal ap_sig_bdd_5172 : BOOLEAN;
signal t_load_4_fu_3190_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_4_fu_3195_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st402_fsm_318 : STD_LOGIC;
signal ap_sig_bdd_5181 : BOOLEAN;
signal beta_load_4_fu_3200_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st403_fsm_319 : STD_LOGIC;
signal ap_sig_bdd_5189 : BOOLEAN;
signal t_load_5_fu_3205_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_5_fu_3210_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st405_fsm_321 : STD_LOGIC;
signal ap_sig_bdd_5198 : BOOLEAN;
signal beta_load_5_fu_3215_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st406_fsm_322 : STD_LOGIC;
signal ap_sig_bdd_5206 : BOOLEAN;
signal t_load_6_fu_3220_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_6_fu_3225_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st408_fsm_324 : STD_LOGIC;
signal ap_sig_bdd_5215 : BOOLEAN;
signal beta_load_6_fu_3230_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st409_fsm_325 : STD_LOGIC;
signal ap_sig_bdd_5223 : BOOLEAN;
signal t_load_7_fu_3235_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_7_fu_3240_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st411_fsm_327 : STD_LOGIC;
signal ap_sig_bdd_5232 : BOOLEAN;
signal beta_load_7_fu_3245_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st412_fsm_328 : STD_LOGIC;
signal ap_sig_bdd_5240 : BOOLEAN;
signal t_load_8_fu_3250_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_8_fu_3255_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st414_fsm_330 : STD_LOGIC;
signal ap_sig_bdd_5249 : BOOLEAN;
signal beta_load_8_fu_3260_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st415_fsm_331 : STD_LOGIC;
signal ap_sig_bdd_5257 : BOOLEAN;
signal t_load_9_fu_3265_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_9_fu_3270_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st417_fsm_333 : STD_LOGIC;
signal ap_sig_bdd_5266 : BOOLEAN;
signal beta_load_9_fu_3275_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st418_fsm_334 : STD_LOGIC;
signal ap_sig_bdd_5274 : BOOLEAN;
signal t_load_10_fu_3280_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_10_fu_3285_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st420_fsm_336 : STD_LOGIC;
signal ap_sig_bdd_5283 : BOOLEAN;
signal beta_load_10_fu_3290_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st421_fsm_337 : STD_LOGIC;
signal ap_sig_bdd_5291 : BOOLEAN;
signal t_load_11_fu_3295_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_11_fu_3300_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st423_fsm_339 : STD_LOGIC;
signal ap_sig_bdd_5300 : BOOLEAN;
signal beta_load_11_fu_3305_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st424_fsm_340 : STD_LOGIC;
signal ap_sig_bdd_5308 : BOOLEAN;
signal t_load_12_fu_3310_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_12_fu_3315_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st426_fsm_342 : STD_LOGIC;
signal ap_sig_bdd_5317 : BOOLEAN;
signal beta_load_12_fu_3320_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st427_fsm_343 : STD_LOGIC;
signal ap_sig_bdd_5325 : BOOLEAN;
signal t_load_13_fu_3325_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_13_fu_3330_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st429_fsm_345 : STD_LOGIC;
signal ap_sig_bdd_5334 : BOOLEAN;
signal beta_load_13_fu_3335_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st430_fsm_346 : STD_LOGIC;
signal ap_sig_bdd_5342 : BOOLEAN;
signal t_load_14_fu_3340_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_14_fu_3345_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st432_fsm_348 : STD_LOGIC;
signal ap_sig_bdd_5351 : BOOLEAN;
signal beta_load_14_fu_3350_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st433_fsm_349 : STD_LOGIC;
signal ap_sig_bdd_5359 : BOOLEAN;
signal t_load_15_fu_3355_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_15_fu_3360_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st435_fsm_351 : STD_LOGIC;
signal ap_sig_bdd_5368 : BOOLEAN;
signal beta_load_15_fu_3365_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st436_fsm_352 : STD_LOGIC;
signal ap_sig_bdd_5376 : BOOLEAN;
signal t_load_16_fu_3370_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_16_fu_3375_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st438_fsm_354 : STD_LOGIC;
signal ap_sig_bdd_5385 : BOOLEAN;
signal beta_load_16_fu_3380_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st439_fsm_355 : STD_LOGIC;
signal ap_sig_bdd_5393 : BOOLEAN;
signal t_load_17_fu_3385_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_17_fu_3390_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st441_fsm_357 : STD_LOGIC;
signal ap_sig_bdd_5402 : BOOLEAN;
signal beta_load_17_fu_3395_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st442_fsm_358 : STD_LOGIC;
signal ap_sig_bdd_5410 : BOOLEAN;
signal t_load_18_fu_3400_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_18_fu_3405_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st444_fsm_360 : STD_LOGIC;
signal ap_sig_bdd_5419 : BOOLEAN;
signal beta_load_18_fu_3410_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st445_fsm_361 : STD_LOGIC;
signal ap_sig_bdd_5427 : BOOLEAN;
signal ap_reg_ioackin_outs_TREADY : STD_LOGIC := '0';
signal rez_addr959960_part_set_fu_830_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_3953954_part_set_fu_922_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_5947948_part_set_fu_1017_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_1956957_part_set_fu_1109_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_4950951_part_set_fu_1201_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_6944945_part_set_fu_1308_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_7941942_part_set_fu_1415_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_8938939_part_set_fu_1522_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_9935936_part_set_fu_1629_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_10932933_part_set_fu_1736_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_11929930_part_set_fu_1843_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_12926927_part_set_fu_1950_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_13923924_part_set_fu_2057_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_14920921_part_set_fu_2164_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_15917918_part_set_fu_2271_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_16914915_part_set_fu_2378_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_17911912_part_set_fu_2485_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_18908909_part_set_fu_2592_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_19905906_part_set_fu_2698_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_20902903_part_set_fu_2828_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_sig_cseq_ST_st385_fsm_301 : STD_LOGIC;
signal ap_sig_bdd_5902 : BOOLEAN;
signal grp_fu_430_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_454_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_454_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_462_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_462_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_466_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_466_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_470_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_470_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_474_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_474_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_478_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_478_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_482_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_482_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_486_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_486_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_490_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_490_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_494_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_494_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_498_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_498_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_502_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_502_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_506_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_510_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_510_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_514_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_514_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_518_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_518_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_522_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_522_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_526_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_526_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_530_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_530_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_534_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_534_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_538_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_538_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_542_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_542_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_546_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_546_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_550_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_550_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_554_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_554_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_558_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_558_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_562_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_562_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_566_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_566_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_570_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_570_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_574_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_574_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_578_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_578_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_582_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_582_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_586_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_586_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_590_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_590_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_594_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_594_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_598_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_598_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_602_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_602_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_606_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_606_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_610_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_610_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_614_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_614_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_618_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_618_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_622_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_622_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_626_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_626_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_630_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_630_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_14_toint_fu_793_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_13_toint_fu_789_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_12_toint_fu_785_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_11_toint_fu_781_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_10_toint_fu_777_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_9_toint_fu_773_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_8_toint_fu_769_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_7_toint_fu_765_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_6_toint_fu_761_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_5_toint_fu_757_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_4_toint_fu_753_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_3_toint_fu_749_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_2_toint_fu_745_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_1_toint_fu_741_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_toint_fu_737_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_796_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_44_toint_fu_885_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_43_toint_fu_882_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_42_toint_fu_879_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_41_toint_fu_876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_40_toint_fu_873_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_39_toint_fu_870_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_38_toint_fu_867_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_37_toint_fu_864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_36_toint_fu_861_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_35_toint_fu_858_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_34_toint_fu_855_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_33_toint_fu_852_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_32_toint_fu_849_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_31_toint_fu_846_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_30_toint_fu_843_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_fu_888_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_74_toint_fu_979_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_73_toint_fu_975_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_72_toint_fu_971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_71_toint_fu_968_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_70_toint_fu_965_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_69_toint_fu_962_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_68_toint_fu_959_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_67_toint_fu_956_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_66_toint_fu_953_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_65_toint_fu_950_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_64_toint_fu_947_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_63_toint_fu_944_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_62_toint_fu_941_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_61_toint_fu_938_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_60_toint_fu_935_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_983_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_29_toint_fu_1072_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_28_toint_fu_1069_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_27_toint_fu_1066_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_26_toint_fu_1063_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_25_toint_fu_1060_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_24_toint_fu_1057_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_23_toint_fu_1054_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_22_toint_fu_1051_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_21_toint_fu_1048_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_20_toint_fu_1045_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_19_toint_fu_1042_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_18_toint_fu_1039_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_17_toint_fu_1036_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_16_toint_fu_1033_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_15_toint_fu_1030_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_1075_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_59_toint_fu_1164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_58_toint_fu_1161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_57_toint_fu_1158_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_56_toint_fu_1155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_55_toint_fu_1152_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_54_toint_fu_1149_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_53_toint_fu_1146_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_52_toint_fu_1143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_51_toint_fu_1140_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_50_toint_fu_1137_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_49_toint_fu_1134_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_48_toint_fu_1131_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_47_toint_fu_1128_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_46_toint_fu_1125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_45_toint_fu_1122_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_1167_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_89_toint_fu_1270_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_88_toint_fu_1266_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_87_toint_fu_1262_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_86_toint_fu_1258_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_85_toint_fu_1254_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_84_toint_fu_1250_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_83_toint_fu_1246_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_82_toint_fu_1242_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_81_toint_fu_1238_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_80_toint_fu_1234_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_79_toint_fu_1230_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_78_toint_fu_1226_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_77_toint_fu_1222_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_76_toint_fu_1218_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_75_toint_fu_1214_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_1274_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_104_toint_fu_1377_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_103_toint_fu_1373_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_102_toint_fu_1369_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_101_toint_fu_1365_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_100_toint_fu_1361_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_99_toint_fu_1357_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_98_toint_fu_1353_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_97_toint_fu_1349_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_96_toint_fu_1345_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_95_toint_fu_1341_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_94_toint_fu_1337_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_93_toint_fu_1333_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_92_toint_fu_1329_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_91_toint_fu_1325_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_90_toint_fu_1321_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_1381_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_119_toint_fu_1484_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_118_toint_fu_1480_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_117_toint_fu_1476_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_116_toint_fu_1472_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_115_toint_fu_1468_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_114_toint_fu_1464_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_113_toint_fu_1460_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_112_toint_fu_1456_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_111_toint_fu_1452_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_110_toint_fu_1448_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_109_toint_fu_1444_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_108_toint_fu_1440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_107_toint_fu_1436_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_106_toint_fu_1432_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_105_toint_fu_1428_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_1488_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_134_toint_fu_1591_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_133_toint_fu_1587_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_132_toint_fu_1583_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_131_toint_fu_1579_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_130_toint_fu_1575_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_129_toint_fu_1571_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_128_toint_fu_1567_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_127_toint_fu_1563_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_126_toint_fu_1559_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_125_toint_fu_1555_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_124_toint_fu_1551_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_123_toint_fu_1547_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_122_toint_fu_1543_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_121_toint_fu_1539_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_120_toint_fu_1535_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_fu_1595_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_149_toint_fu_1698_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_148_toint_fu_1694_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_147_toint_fu_1690_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_146_toint_fu_1686_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_145_toint_fu_1682_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_144_toint_fu_1678_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_143_toint_fu_1674_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_142_toint_fu_1670_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_141_toint_fu_1666_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_140_toint_fu_1662_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_139_toint_fu_1658_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_138_toint_fu_1654_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_137_toint_fu_1650_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_136_toint_fu_1646_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_135_toint_fu_1642_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_fu_1702_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_164_toint_fu_1805_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_163_toint_fu_1801_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_162_toint_fu_1797_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_161_toint_fu_1793_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_160_toint_fu_1789_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_159_toint_fu_1785_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_158_toint_fu_1781_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_157_toint_fu_1777_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_156_toint_fu_1773_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_155_toint_fu_1769_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_154_toint_fu_1765_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_153_toint_fu_1761_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_152_toint_fu_1757_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_151_toint_fu_1753_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_150_toint_fu_1749_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_fu_1809_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_179_toint_fu_1912_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_178_toint_fu_1908_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_177_toint_fu_1904_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_176_toint_fu_1900_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_175_toint_fu_1896_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_174_toint_fu_1892_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_173_toint_fu_1888_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_172_toint_fu_1884_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_171_toint_fu_1880_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_170_toint_fu_1876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_169_toint_fu_1872_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_168_toint_fu_1868_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_167_toint_fu_1864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_166_toint_fu_1860_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_165_toint_fu_1856_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_fu_1916_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_194_toint_fu_2019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_193_toint_fu_2015_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_192_toint_fu_2011_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_191_toint_fu_2007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_190_toint_fu_2003_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_189_toint_fu_1999_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_188_toint_fu_1995_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_187_toint_fu_1991_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_186_toint_fu_1987_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_185_toint_fu_1983_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_184_toint_fu_1979_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_183_toint_fu_1975_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_182_toint_fu_1971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_181_toint_fu_1967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_180_toint_fu_1963_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_fu_2023_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_209_toint_fu_2126_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_208_toint_fu_2122_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_207_toint_fu_2118_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_206_toint_fu_2114_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_205_toint_fu_2110_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_204_toint_fu_2106_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_203_toint_fu_2102_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_202_toint_fu_2098_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_201_toint_fu_2094_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_200_toint_fu_2090_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_199_toint_fu_2086_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_198_toint_fu_2082_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_197_toint_fu_2078_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_196_toint_fu_2074_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_195_toint_fu_2070_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_fu_2130_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_224_toint_fu_2233_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_223_toint_fu_2229_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_222_toint_fu_2225_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_221_toint_fu_2221_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_220_toint_fu_2217_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_219_toint_fu_2213_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_218_toint_fu_2209_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_217_toint_fu_2205_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_216_toint_fu_2201_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_215_toint_fu_2197_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_214_toint_fu_2193_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_213_toint_fu_2189_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_212_toint_fu_2185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_211_toint_fu_2181_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_210_toint_fu_2177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_2237_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_239_toint_fu_2340_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_238_toint_fu_2336_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_237_toint_fu_2332_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_236_toint_fu_2328_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_235_toint_fu_2324_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_234_toint_fu_2320_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_233_toint_fu_2316_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_232_toint_fu_2312_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_231_toint_fu_2308_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_230_toint_fu_2304_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_229_toint_fu_2300_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_228_toint_fu_2296_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_227_toint_fu_2292_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_226_toint_fu_2288_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_225_toint_fu_2284_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_2344_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_254_toint_fu_2447_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_253_toint_fu_2443_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_252_toint_fu_2439_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_251_toint_fu_2435_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_250_toint_fu_2431_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_249_toint_fu_2427_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_248_toint_fu_2423_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_247_toint_fu_2419_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_246_toint_fu_2415_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_245_toint_fu_2411_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_244_toint_fu_2407_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_243_toint_fu_2403_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_242_toint_fu_2399_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_241_toint_fu_2395_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_240_toint_fu_2391_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_fu_2451_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_269_toint_fu_2554_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_268_toint_fu_2550_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_267_toint_fu_2546_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_266_toint_fu_2542_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_265_toint_fu_2538_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_264_toint_fu_2534_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_263_toint_fu_2530_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_262_toint_fu_2526_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_261_toint_fu_2522_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_260_toint_fu_2518_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_259_toint_fu_2514_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_258_toint_fu_2510_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_257_toint_fu_2506_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_256_toint_fu_2502_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_255_toint_fu_2498_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_2558_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_284_toint_fu_2660_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_283_toint_fu_2656_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_282_toint_fu_2652_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_281_toint_fu_2648_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_280_toint_fu_2644_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_279_toint_fu_2640_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_278_toint_fu_2636_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_277_toint_fu_2632_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_276_toint_fu_2628_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_275_toint_fu_2624_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_274_toint_fu_2620_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_273_toint_fu_2616_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_272_toint_fu_2612_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_271_toint_fu_2608_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_270_toint_fu_2604_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_fu_2664_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_299_toint_fu_2790_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_298_toint_fu_2762_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_297_toint_fu_2758_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_296_toint_fu_2754_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_295_toint_fu_2750_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_294_toint_fu_2746_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_293_toint_fu_2742_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_292_toint_fu_2738_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_291_toint_fu_2734_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_290_toint_fu_2730_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_289_toint_fu_2726_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_288_toint_fu_2722_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_287_toint_fu_2718_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_286_toint_fu_2714_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_285_toint_fu_2710_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_2794_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal tmp_61_to_int_i_fu_3068_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_618_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_622_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_626_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal beta_write_assign_toint_fu_3089_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_write_assign_toint_fu_3085_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal t_write_assign_toint_fu_3081_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_fu_3093_p4 : STD_LOGIC_VECTOR (95 downto 0);
signal grp_fu_639_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_ce : STD_LOGIC;
signal grp_fu_434_ce : STD_LOGIC;
signal grp_fu_438_ce : STD_LOGIC;
signal grp_fu_442_ce : STD_LOGIC;
signal grp_fu_446_ce : STD_LOGIC;
signal grp_fu_450_ce : STD_LOGIC;
signal grp_fu_454_ce : STD_LOGIC;
signal grp_fu_458_ce : STD_LOGIC;
signal grp_fu_462_ce : STD_LOGIC;
signal grp_fu_466_ce : STD_LOGIC;
signal grp_fu_470_ce : STD_LOGIC;
signal grp_fu_474_ce : STD_LOGIC;
signal grp_fu_478_ce : STD_LOGIC;
signal grp_fu_482_ce : STD_LOGIC;
signal grp_fu_486_ce : STD_LOGIC;
signal grp_fu_490_ce : STD_LOGIC;
signal grp_fu_494_ce : STD_LOGIC;
signal grp_fu_498_ce : STD_LOGIC;
signal grp_fu_502_ce : STD_LOGIC;
signal grp_fu_506_ce : STD_LOGIC;
signal grp_fu_510_ce : STD_LOGIC;
signal grp_fu_514_ce : STD_LOGIC;
signal grp_fu_518_ce : STD_LOGIC;
signal grp_fu_522_ce : STD_LOGIC;
signal grp_fu_526_ce : STD_LOGIC;
signal grp_fu_530_ce : STD_LOGIC;
signal grp_fu_534_ce : STD_LOGIC;
signal grp_fu_538_ce : STD_LOGIC;
signal grp_fu_542_ce : STD_LOGIC;
signal grp_fu_546_ce : STD_LOGIC;
signal grp_fu_550_ce : STD_LOGIC;
signal grp_fu_554_ce : STD_LOGIC;
signal grp_fu_558_ce : STD_LOGIC;
signal grp_fu_562_ce : STD_LOGIC;
signal grp_fu_566_ce : STD_LOGIC;
signal grp_fu_570_ce : STD_LOGIC;
signal grp_fu_574_ce : STD_LOGIC;
signal grp_fu_578_ce : STD_LOGIC;
signal grp_fu_582_ce : STD_LOGIC;
signal grp_fu_586_ce : STD_LOGIC;
signal grp_fu_590_ce : STD_LOGIC;
signal grp_fu_594_ce : STD_LOGIC;
signal grp_fu_598_ce : STD_LOGIC;
signal grp_fu_602_ce : STD_LOGIC;
signal grp_fu_606_ce : STD_LOGIC;
signal grp_fu_610_ce : STD_LOGIC;
signal grp_fu_614_ce : STD_LOGIC;
signal grp_fu_618_ce : STD_LOGIC;
signal grp_fu_622_ce : STD_LOGIC;
signal grp_fu_626_ce : STD_LOGIC;
signal grp_fu_630_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (361 downto 0);
component tri_intersect_fsub_32ns_32ns_32_9_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fadd_32ns_32ns_32_9_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fmul_32ns_32ns_32_5_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fdiv_32ns_32ns_32_30 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_data_array IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (4 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (575 downto 0);
q0 : OUT STD_LOGIC_VECTOR (575 downto 0);
address1 : IN STD_LOGIC_VECTOR (4 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (575 downto 0);
q1 : OUT STD_LOGIC_VECTOR (575 downto 0) );
end component;
begin
data_array_U : component tri_intersect_data_array
generic map (
DataWidth => 576,
AddressRange => 20,
AddressWidth => 5)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => data_array_address0,
ce0 => data_array_ce0,
we0 => data_array_we0,
d0 => data_array_d0,
q0 => data_array_q0,
address1 => data_array_address1,
ce1 => data_array_ce1,
we1 => data_array_we1,
d1 => data_array_d1,
q1 => data_array_q1);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U0 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_430_p0,
din1 => grp_fu_430_p1,
ce => grp_fu_430_ce,
dout => grp_fu_430_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U1 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_434_p0,
din1 => grp_fu_434_p1,
ce => grp_fu_434_ce,
dout => grp_fu_434_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U2 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_438_p0,
din1 => grp_fu_438_p1,
ce => grp_fu_438_ce,
dout => grp_fu_438_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U3 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_442_p0,
din1 => grp_fu_442_p1,
ce => grp_fu_442_ce,
dout => grp_fu_442_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U4 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_446_p0,
din1 => grp_fu_446_p1,
ce => grp_fu_446_ce,
dout => grp_fu_446_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U5 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_450_p0,
din1 => grp_fu_450_p1,
ce => grp_fu_450_ce,
dout => grp_fu_450_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U6 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_454_p0,
din1 => grp_fu_454_p1,
ce => grp_fu_454_ce,
dout => grp_fu_454_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U7 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_458_p0,
din1 => grp_fu_458_p1,
ce => grp_fu_458_ce,
dout => grp_fu_458_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U8 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_462_p0,
din1 => grp_fu_462_p1,
ce => grp_fu_462_ce,
dout => grp_fu_462_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U9 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_466_p0,
din1 => grp_fu_466_p1,
ce => grp_fu_466_ce,
dout => grp_fu_466_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U10 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_470_p0,
din1 => grp_fu_470_p1,
ce => grp_fu_470_ce,
dout => grp_fu_470_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U11 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_474_p0,
din1 => grp_fu_474_p1,
ce => grp_fu_474_ce,
dout => grp_fu_474_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U12 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_478_p0,
din1 => grp_fu_478_p1,
ce => grp_fu_478_ce,
dout => grp_fu_478_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U13 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_482_p0,
din1 => grp_fu_482_p1,
ce => grp_fu_482_ce,
dout => grp_fu_482_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U14 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_486_p0,
din1 => grp_fu_486_p1,
ce => grp_fu_486_ce,
dout => grp_fu_486_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U15 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_490_p0,
din1 => grp_fu_490_p1,
ce => grp_fu_490_ce,
dout => grp_fu_490_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U16 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_494_p0,
din1 => grp_fu_494_p1,
ce => grp_fu_494_ce,
dout => grp_fu_494_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U17 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_498_p0,
din1 => grp_fu_498_p1,
ce => grp_fu_498_ce,
dout => grp_fu_498_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U18 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_502_p0,
din1 => grp_fu_502_p1,
ce => grp_fu_502_ce,
dout => grp_fu_502_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U19 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_506_p0,
din1 => grp_fu_506_p1,
ce => grp_fu_506_ce,
dout => grp_fu_506_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U20 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_510_p0,
din1 => grp_fu_510_p1,
ce => grp_fu_510_ce,
dout => grp_fu_510_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U21 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_514_p0,
din1 => grp_fu_514_p1,
ce => grp_fu_514_ce,
dout => grp_fu_514_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U22 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_518_p0,
din1 => grp_fu_518_p1,
ce => grp_fu_518_ce,
dout => grp_fu_518_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U23 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_522_p0,
din1 => grp_fu_522_p1,
ce => grp_fu_522_ce,
dout => grp_fu_522_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U24 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_526_p0,
din1 => grp_fu_526_p1,
ce => grp_fu_526_ce,
dout => grp_fu_526_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U25 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_530_p0,
din1 => grp_fu_530_p1,
ce => grp_fu_530_ce,
dout => grp_fu_530_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U26 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_534_p0,
din1 => grp_fu_534_p1,
ce => grp_fu_534_ce,
dout => grp_fu_534_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U27 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_538_p0,
din1 => grp_fu_538_p1,
ce => grp_fu_538_ce,
dout => grp_fu_538_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U28 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_542_p0,
din1 => grp_fu_542_p1,
ce => grp_fu_542_ce,
dout => grp_fu_542_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U29 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_546_p0,
din1 => grp_fu_546_p1,
ce => grp_fu_546_ce,
dout => grp_fu_546_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U30 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_550_p0,
din1 => grp_fu_550_p1,
ce => grp_fu_550_ce,
dout => grp_fu_550_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U31 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_554_p0,
din1 => grp_fu_554_p1,
ce => grp_fu_554_ce,
dout => grp_fu_554_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U32 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_558_p0,
din1 => grp_fu_558_p1,
ce => grp_fu_558_ce,
dout => grp_fu_558_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U33 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_562_p0,
din1 => grp_fu_562_p1,
ce => grp_fu_562_ce,
dout => grp_fu_562_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U34 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_566_p0,
din1 => grp_fu_566_p1,
ce => grp_fu_566_ce,
dout => grp_fu_566_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U35 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_570_p0,
din1 => grp_fu_570_p1,
ce => grp_fu_570_ce,
dout => grp_fu_570_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U36 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_574_p0,
din1 => grp_fu_574_p1,
ce => grp_fu_574_ce,
dout => grp_fu_574_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U37 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_578_p0,
din1 => grp_fu_578_p1,
ce => grp_fu_578_ce,
dout => grp_fu_578_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U38 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_582_p0,
din1 => grp_fu_582_p1,
ce => grp_fu_582_ce,
dout => grp_fu_582_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U39 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_586_p0,
din1 => grp_fu_586_p1,
ce => grp_fu_586_ce,
dout => grp_fu_586_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U40 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_590_p0,
din1 => grp_fu_590_p1,
ce => grp_fu_590_ce,
dout => grp_fu_590_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U41 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_594_p0,
din1 => grp_fu_594_p1,
ce => grp_fu_594_ce,
dout => grp_fu_594_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U42 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_598_p0,
din1 => grp_fu_598_p1,
ce => grp_fu_598_ce,
dout => grp_fu_598_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U43 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_602_p0,
din1 => grp_fu_602_p1,
ce => grp_fu_602_ce,
dout => grp_fu_602_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U44 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_606_p0,
din1 => grp_fu_606_p1,
ce => grp_fu_606_ce,
dout => grp_fu_606_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U45 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_610_p0,
din1 => grp_fu_610_p1,
ce => grp_fu_610_ce,
dout => grp_fu_610_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U46 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_614_p0,
din1 => grp_fu_614_p1,
ce => grp_fu_614_ce,
dout => grp_fu_614_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U47 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_618_p0,
din1 => grp_fu_618_p1,
ce => grp_fu_618_ce,
dout => grp_fu_618_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U48 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_622_p0,
din1 => grp_fu_622_p1,
ce => grp_fu_622_ce,
dout => grp_fu_622_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U49 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_626_p0,
din1 => grp_fu_626_p1,
ce => grp_fu_626_ce,
dout => grp_fu_626_p2);
tri_intersect_fdiv_32ns_32ns_32_30_U50 : component tri_intersect_fdiv_32ns_32ns_32_30
generic map (
ID => 1,
NUM_STAGE => 30,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_630_p0,
din1 => grp_fu_630_p1,
ce => grp_fu_630_ce,
dout => grp_fu_630_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_outs_TREADY assign process. --
ap_reg_ioackin_outs_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) and not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361)))) then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361) and (ap_const_logic_1 = outs_TREADY)))) then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and not((ap_const_lv1_0 = exitcond2_fu_2840_p2)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (ap_const_lv1_0 = exitcond2_fu_2840_p2))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and not((ap_const_lv1_0 = exitcond2_fu_2840_p2))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it19 assign process. --
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it20 assign process. --
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it21 assign process. --
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it22 assign process. --
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it23 assign process. --
ap_reg_ppiten_pp0_it23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it24 assign process. --
ap_reg_ppiten_pp0_it24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it25 assign process. --
ap_reg_ppiten_pp0_it25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it26 assign process. --
ap_reg_ppiten_pp0_it26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it27 assign process. --
ap_reg_ppiten_pp0_it27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it28 assign process. --
ap_reg_ppiten_pp0_it28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it29 assign process. --
ap_reg_ppiten_pp0_it29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it30 assign process. --
ap_reg_ppiten_pp0_it30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it31 assign process. --
ap_reg_ppiten_pp0_it31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it32 assign process. --
ap_reg_ppiten_pp0_it32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it33 assign process. --
ap_reg_ppiten_pp0_it33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it34 assign process. --
ap_reg_ppiten_pp0_it34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it35 assign process. --
ap_reg_ppiten_pp0_it35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it36 assign process. --
ap_reg_ppiten_pp0_it36_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it36 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it36 <= ap_reg_ppiten_pp0_it35;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it37 assign process. --
ap_reg_ppiten_pp0_it37_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it37 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it37 <= ap_reg_ppiten_pp0_it36;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it38 assign process. --
ap_reg_ppiten_pp0_it38_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it38 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it38 <= ap_reg_ppiten_pp0_it37;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it39 assign process. --
ap_reg_ppiten_pp0_it39_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it39 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it39 <= ap_reg_ppiten_pp0_it38;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it40 assign process. --
ap_reg_ppiten_pp0_it40_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it40 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it40 <= ap_reg_ppiten_pp0_it39;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it41 assign process. --
ap_reg_ppiten_pp0_it41_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it41 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it41 <= ap_reg_ppiten_pp0_it40;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it42 assign process. --
ap_reg_ppiten_pp0_it42_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it42 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it42 <= ap_reg_ppiten_pp0_it41;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it43 assign process. --
ap_reg_ppiten_pp0_it43_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it43 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it43 <= ap_reg_ppiten_pp0_it42;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it44 assign process. --
ap_reg_ppiten_pp0_it44_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it44 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it44 <= ap_reg_ppiten_pp0_it43;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it45 assign process. --
ap_reg_ppiten_pp0_it45_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it45 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it45 <= ap_reg_ppiten_pp0_it44;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it46 assign process. --
ap_reg_ppiten_pp0_it46_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it46 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it46 <= ap_reg_ppiten_pp0_it45;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it47 assign process. --
ap_reg_ppiten_pp0_it47_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it47 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it47 <= ap_reg_ppiten_pp0_it46;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it48 assign process. --
ap_reg_ppiten_pp0_it48_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it48 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it48 <= ap_reg_ppiten_pp0_it47;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it49 assign process. --
ap_reg_ppiten_pp0_it49_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it49 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it49 <= ap_reg_ppiten_pp0_it48;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it50 assign process. --
ap_reg_ppiten_pp0_it50_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it50 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it50 <= ap_reg_ppiten_pp0_it49;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it51 assign process. --
ap_reg_ppiten_pp0_it51_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it51 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it51 <= ap_reg_ppiten_pp0_it50;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it52 assign process. --
ap_reg_ppiten_pp0_it52_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it52 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it52 <= ap_reg_ppiten_pp0_it51;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it53 assign process. --
ap_reg_ppiten_pp0_it53_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it53 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it53 <= ap_reg_ppiten_pp0_it52;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it54 assign process. --
ap_reg_ppiten_pp0_it54_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it54 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it54 <= ap_reg_ppiten_pp0_it53;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it55 assign process. --
ap_reg_ppiten_pp0_it55_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it55 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it55 <= ap_reg_ppiten_pp0_it54;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it56 assign process. --
ap_reg_ppiten_pp0_it56_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it56 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it56 <= ap_reg_ppiten_pp0_it55;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it57 assign process. --
ap_reg_ppiten_pp0_it57_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it57 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it57 <= ap_reg_ppiten_pp0_it56;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it58 assign process. --
ap_reg_ppiten_pp0_it58_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it58 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it58 <= ap_reg_ppiten_pp0_it57;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it59 assign process. --
ap_reg_ppiten_pp0_it59_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it59 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it59 <= ap_reg_ppiten_pp0_it58;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it60 assign process. --
ap_reg_ppiten_pp0_it60_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it60 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it60 <= ap_reg_ppiten_pp0_it59;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it61 assign process. --
ap_reg_ppiten_pp0_it61_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it61 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it61 <= ap_reg_ppiten_pp0_it60;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it62 assign process. --
ap_reg_ppiten_pp0_it62_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it62 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it62 <= ap_reg_ppiten_pp0_it61;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it63 assign process. --
ap_reg_ppiten_pp0_it63_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it63 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it63 <= ap_reg_ppiten_pp0_it62;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it64 assign process. --
ap_reg_ppiten_pp0_it64_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it64 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it64 <= ap_reg_ppiten_pp0_it63;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it65 assign process. --
ap_reg_ppiten_pp0_it65_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it65 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it65 <= ap_reg_ppiten_pp0_it64;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it66 assign process. --
ap_reg_ppiten_pp0_it66_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it66 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it66 <= ap_reg_ppiten_pp0_it65;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it67 assign process. --
ap_reg_ppiten_pp0_it67_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it67 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it67 <= ap_reg_ppiten_pp0_it66;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it68 assign process. --
ap_reg_ppiten_pp0_it68_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it68 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it68 <= ap_reg_ppiten_pp0_it67;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it69 assign process. --
ap_reg_ppiten_pp0_it69_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it69 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it69 <= ap_reg_ppiten_pp0_it68;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it70 assign process. --
ap_reg_ppiten_pp0_it70_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it70 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it70 <= ap_reg_ppiten_pp0_it69;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it71 assign process. --
ap_reg_ppiten_pp0_it71_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it71 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it71 <= ap_reg_ppiten_pp0_it70;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it72 assign process. --
ap_reg_ppiten_pp0_it72_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it72 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it72 <= ap_reg_ppiten_pp0_it71;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it73 assign process. --
ap_reg_ppiten_pp0_it73_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it73 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it73 <= ap_reg_ppiten_pp0_it72;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it74 assign process. --
ap_reg_ppiten_pp0_it74_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it74 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it74 <= ap_reg_ppiten_pp0_it73;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it75 assign process. --
ap_reg_ppiten_pp0_it75_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it75 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it75 <= ap_reg_ppiten_pp0_it74;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it76 assign process. --
ap_reg_ppiten_pp0_it76_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it76 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it76 <= ap_reg_ppiten_pp0_it75;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it77 assign process. --
ap_reg_ppiten_pp0_it77_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it77 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it77 <= ap_reg_ppiten_pp0_it76;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it78 assign process. --
ap_reg_ppiten_pp0_it78_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it78 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it78 <= ap_reg_ppiten_pp0_it77;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it79 assign process. --
ap_reg_ppiten_pp0_it79_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it79 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it79 <= ap_reg_ppiten_pp0_it78;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it80 assign process. --
ap_reg_ppiten_pp0_it80_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it80 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it80 <= ap_reg_ppiten_pp0_it79;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it81 assign process. --
ap_reg_ppiten_pp0_it81_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it81 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it81 <= ap_reg_ppiten_pp0_it80;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it82 assign process. --
ap_reg_ppiten_pp0_it82_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it82 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it82 <= ap_reg_ppiten_pp0_it81;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it83 assign process. --
ap_reg_ppiten_pp0_it83_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it83 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it83 <= ap_reg_ppiten_pp0_it82;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end process;
-- i1_reg_418 assign process. --
i1_reg_418_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299))) then
i1_reg_418 <= ap_const_lv5_0;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (ap_const_lv1_0 = exitcond2_fu_2840_p2))) then
i1_reg_418 <= i_fu_2846_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it9)) then
a_reg_4010 <= grp_fu_430_p2;
b_reg_4017 <= grp_fu_434_p2;
c_reg_4024 <= grp_fu_438_p2;
d_reg_4031 <= grp_fu_442_p2;
e_reg_4038 <= grp_fu_446_p2;
f_reg_4045 <= grp_fu_450_p2;
j_reg_4052 <= grp_fu_454_p2;
k_reg_4059 <= grp_fu_458_p2;
l_reg_4066 <= grp_fu_462_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_true = ap_true)) then
ap_reg_ppstg_a_reg_4010_pp0_it11 <= a_reg_4010;
ap_reg_ppstg_a_reg_4010_pp0_it12 <= ap_reg_ppstg_a_reg_4010_pp0_it11;
ap_reg_ppstg_a_reg_4010_pp0_it13 <= ap_reg_ppstg_a_reg_4010_pp0_it12;
ap_reg_ppstg_a_reg_4010_pp0_it14 <= ap_reg_ppstg_a_reg_4010_pp0_it13;
ap_reg_ppstg_a_reg_4010_pp0_it15 <= ap_reg_ppstg_a_reg_4010_pp0_it14;
ap_reg_ppstg_a_reg_4010_pp0_it16 <= ap_reg_ppstg_a_reg_4010_pp0_it15;
ap_reg_ppstg_a_reg_4010_pp0_it17 <= ap_reg_ppstg_a_reg_4010_pp0_it16;
ap_reg_ppstg_a_reg_4010_pp0_it18 <= ap_reg_ppstg_a_reg_4010_pp0_it17;
ap_reg_ppstg_a_reg_4010_pp0_it19 <= ap_reg_ppstg_a_reg_4010_pp0_it18;
ap_reg_ppstg_a_reg_4010_pp0_it20 <= ap_reg_ppstg_a_reg_4010_pp0_it19;
ap_reg_ppstg_a_reg_4010_pp0_it21 <= ap_reg_ppstg_a_reg_4010_pp0_it20;
ap_reg_ppstg_a_reg_4010_pp0_it22 <= ap_reg_ppstg_a_reg_4010_pp0_it21;
ap_reg_ppstg_a_reg_4010_pp0_it23 <= ap_reg_ppstg_a_reg_4010_pp0_it22;
ap_reg_ppstg_a_reg_4010_pp0_it24 <= ap_reg_ppstg_a_reg_4010_pp0_it23;
ap_reg_ppstg_b_reg_4017_pp0_it11 <= b_reg_4017;
ap_reg_ppstg_b_reg_4017_pp0_it12 <= ap_reg_ppstg_b_reg_4017_pp0_it11;
ap_reg_ppstg_b_reg_4017_pp0_it13 <= ap_reg_ppstg_b_reg_4017_pp0_it12;
ap_reg_ppstg_b_reg_4017_pp0_it14 <= ap_reg_ppstg_b_reg_4017_pp0_it13;
ap_reg_ppstg_b_reg_4017_pp0_it15 <= ap_reg_ppstg_b_reg_4017_pp0_it14;
ap_reg_ppstg_b_reg_4017_pp0_it16 <= ap_reg_ppstg_b_reg_4017_pp0_it15;
ap_reg_ppstg_b_reg_4017_pp0_it17 <= ap_reg_ppstg_b_reg_4017_pp0_it16;
ap_reg_ppstg_b_reg_4017_pp0_it18 <= ap_reg_ppstg_b_reg_4017_pp0_it17;
ap_reg_ppstg_b_reg_4017_pp0_it19 <= ap_reg_ppstg_b_reg_4017_pp0_it18;
ap_reg_ppstg_b_reg_4017_pp0_it20 <= ap_reg_ppstg_b_reg_4017_pp0_it19;
ap_reg_ppstg_b_reg_4017_pp0_it21 <= ap_reg_ppstg_b_reg_4017_pp0_it20;
ap_reg_ppstg_b_reg_4017_pp0_it22 <= ap_reg_ppstg_b_reg_4017_pp0_it21;
ap_reg_ppstg_b_reg_4017_pp0_it23 <= ap_reg_ppstg_b_reg_4017_pp0_it22;
ap_reg_ppstg_b_reg_4017_pp0_it24 <= ap_reg_ppstg_b_reg_4017_pp0_it23;
ap_reg_ppstg_c_reg_4024_pp0_it11 <= c_reg_4024;
ap_reg_ppstg_c_reg_4024_pp0_it12 <= ap_reg_ppstg_c_reg_4024_pp0_it11;
ap_reg_ppstg_c_reg_4024_pp0_it13 <= ap_reg_ppstg_c_reg_4024_pp0_it12;
ap_reg_ppstg_c_reg_4024_pp0_it14 <= ap_reg_ppstg_c_reg_4024_pp0_it13;
ap_reg_ppstg_c_reg_4024_pp0_it15 <= ap_reg_ppstg_c_reg_4024_pp0_it14;
ap_reg_ppstg_c_reg_4024_pp0_it16 <= ap_reg_ppstg_c_reg_4024_pp0_it15;
ap_reg_ppstg_c_reg_4024_pp0_it17 <= ap_reg_ppstg_c_reg_4024_pp0_it16;
ap_reg_ppstg_c_reg_4024_pp0_it18 <= ap_reg_ppstg_c_reg_4024_pp0_it17;
ap_reg_ppstg_c_reg_4024_pp0_it19 <= ap_reg_ppstg_c_reg_4024_pp0_it18;
ap_reg_ppstg_c_reg_4024_pp0_it20 <= ap_reg_ppstg_c_reg_4024_pp0_it19;
ap_reg_ppstg_c_reg_4024_pp0_it21 <= ap_reg_ppstg_c_reg_4024_pp0_it20;
ap_reg_ppstg_c_reg_4024_pp0_it22 <= ap_reg_ppstg_c_reg_4024_pp0_it21;
ap_reg_ppstg_c_reg_4024_pp0_it23 <= ap_reg_ppstg_c_reg_4024_pp0_it22;
ap_reg_ppstg_c_reg_4024_pp0_it24 <= ap_reg_ppstg_c_reg_4024_pp0_it23;
ap_reg_ppstg_c_reg_4024_pp0_it25 <= ap_reg_ppstg_c_reg_4024_pp0_it24;
ap_reg_ppstg_c_reg_4024_pp0_it26 <= ap_reg_ppstg_c_reg_4024_pp0_it25;
ap_reg_ppstg_c_reg_4024_pp0_it27 <= ap_reg_ppstg_c_reg_4024_pp0_it26;
ap_reg_ppstg_c_reg_4024_pp0_it28 <= ap_reg_ppstg_c_reg_4024_pp0_it27;
ap_reg_ppstg_c_reg_4024_pp0_it29 <= ap_reg_ppstg_c_reg_4024_pp0_it28;
ap_reg_ppstg_c_reg_4024_pp0_it30 <= ap_reg_ppstg_c_reg_4024_pp0_it29;
ap_reg_ppstg_c_reg_4024_pp0_it31 <= ap_reg_ppstg_c_reg_4024_pp0_it30;
ap_reg_ppstg_c_reg_4024_pp0_it32 <= ap_reg_ppstg_c_reg_4024_pp0_it31;
ap_reg_ppstg_c_reg_4024_pp0_it33 <= ap_reg_ppstg_c_reg_4024_pp0_it32;
ap_reg_ppstg_d_reg_4031_pp0_it11 <= d_reg_4031;
ap_reg_ppstg_d_reg_4031_pp0_it12 <= ap_reg_ppstg_d_reg_4031_pp0_it11;
ap_reg_ppstg_d_reg_4031_pp0_it13 <= ap_reg_ppstg_d_reg_4031_pp0_it12;
ap_reg_ppstg_d_reg_4031_pp0_it14 <= ap_reg_ppstg_d_reg_4031_pp0_it13;
ap_reg_ppstg_d_reg_4031_pp0_it15 <= ap_reg_ppstg_d_reg_4031_pp0_it14;
ap_reg_ppstg_d_reg_4031_pp0_it16 <= ap_reg_ppstg_d_reg_4031_pp0_it15;
ap_reg_ppstg_d_reg_4031_pp0_it17 <= ap_reg_ppstg_d_reg_4031_pp0_it16;
ap_reg_ppstg_d_reg_4031_pp0_it18 <= ap_reg_ppstg_d_reg_4031_pp0_it17;
ap_reg_ppstg_d_reg_4031_pp0_it19 <= ap_reg_ppstg_d_reg_4031_pp0_it18;
ap_reg_ppstg_d_reg_4031_pp0_it20 <= ap_reg_ppstg_d_reg_4031_pp0_it19;
ap_reg_ppstg_d_reg_4031_pp0_it21 <= ap_reg_ppstg_d_reg_4031_pp0_it20;
ap_reg_ppstg_d_reg_4031_pp0_it22 <= ap_reg_ppstg_d_reg_4031_pp0_it21;
ap_reg_ppstg_d_reg_4031_pp0_it23 <= ap_reg_ppstg_d_reg_4031_pp0_it22;
ap_reg_ppstg_d_reg_4031_pp0_it24 <= ap_reg_ppstg_d_reg_4031_pp0_it23;
ap_reg_ppstg_d_reg_4031_pp0_it25 <= ap_reg_ppstg_d_reg_4031_pp0_it24;
ap_reg_ppstg_d_reg_4031_pp0_it26 <= ap_reg_ppstg_d_reg_4031_pp0_it25;
ap_reg_ppstg_d_reg_4031_pp0_it27 <= ap_reg_ppstg_d_reg_4031_pp0_it26;
ap_reg_ppstg_d_reg_4031_pp0_it28 <= ap_reg_ppstg_d_reg_4031_pp0_it27;
ap_reg_ppstg_d_reg_4031_pp0_it29 <= ap_reg_ppstg_d_reg_4031_pp0_it28;
ap_reg_ppstg_d_reg_4031_pp0_it30 <= ap_reg_ppstg_d_reg_4031_pp0_it29;
ap_reg_ppstg_d_reg_4031_pp0_it31 <= ap_reg_ppstg_d_reg_4031_pp0_it30;
ap_reg_ppstg_d_reg_4031_pp0_it32 <= ap_reg_ppstg_d_reg_4031_pp0_it31;
ap_reg_ppstg_d_reg_4031_pp0_it33 <= ap_reg_ppstg_d_reg_4031_pp0_it32;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8;
ap_reg_ppstg_e_reg_4038_pp0_it11 <= e_reg_4038;
ap_reg_ppstg_e_reg_4038_pp0_it12 <= ap_reg_ppstg_e_reg_4038_pp0_it11;
ap_reg_ppstg_e_reg_4038_pp0_it13 <= ap_reg_ppstg_e_reg_4038_pp0_it12;
ap_reg_ppstg_e_reg_4038_pp0_it14 <= ap_reg_ppstg_e_reg_4038_pp0_it13;
ap_reg_ppstg_e_reg_4038_pp0_it15 <= ap_reg_ppstg_e_reg_4038_pp0_it14;
ap_reg_ppstg_e_reg_4038_pp0_it16 <= ap_reg_ppstg_e_reg_4038_pp0_it15;
ap_reg_ppstg_e_reg_4038_pp0_it17 <= ap_reg_ppstg_e_reg_4038_pp0_it16;
ap_reg_ppstg_e_reg_4038_pp0_it18 <= ap_reg_ppstg_e_reg_4038_pp0_it17;
ap_reg_ppstg_e_reg_4038_pp0_it19 <= ap_reg_ppstg_e_reg_4038_pp0_it18;
ap_reg_ppstg_e_reg_4038_pp0_it20 <= ap_reg_ppstg_e_reg_4038_pp0_it19;
ap_reg_ppstg_e_reg_4038_pp0_it21 <= ap_reg_ppstg_e_reg_4038_pp0_it20;
ap_reg_ppstg_e_reg_4038_pp0_it22 <= ap_reg_ppstg_e_reg_4038_pp0_it21;
ap_reg_ppstg_e_reg_4038_pp0_it23 <= ap_reg_ppstg_e_reg_4038_pp0_it22;
ap_reg_ppstg_e_reg_4038_pp0_it24 <= ap_reg_ppstg_e_reg_4038_pp0_it23;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it10 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it9;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it11 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it10;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it12 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it11;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it13 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it12;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it14 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it13;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it15 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it14;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it16 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it15;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it17 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it16;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it18 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it17;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it19 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it18;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it2 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it1;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it20 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it19;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it21 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it20;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it22 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it21;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it23 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it22;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it24 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it23;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it25 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it24;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it26 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it25;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it27 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it26;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it28 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it27;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it29 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it28;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it3 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it2;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it30 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it29;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it31 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it30;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it32 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it31;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it33 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it32;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it34 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it33;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it35 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it34;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it36 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it35;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it37 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it36;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it38 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it37;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it39 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it38;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it4 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it3;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it40 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it39;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it41 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it40;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it42 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it41;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it43 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it42;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it44 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it43;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it45 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it44;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it46 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it45;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it47 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it46;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it48 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it47;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it49 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it48;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it5 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it4;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it50 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it49;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it51 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it50;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it52 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it51;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it53 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it52;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it54 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it53;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it55 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it54;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it56 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it55;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it57 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it56;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it58 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it57;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it59 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it58;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it6 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it5;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it60 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it59;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it61 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it60;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it62 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it61;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it63 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it62;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it64 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it63;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it65 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it64;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it66 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it65;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it67 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it66;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it68 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it67;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it69 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it68;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it7 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it6;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it70 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it69;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it71 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it70;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it72 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it71;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it73 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it72;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it74 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it73;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it75 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it74;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it76 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it75;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it77 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it76;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it78 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it77;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it79 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it78;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it8 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it7;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it80 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it79;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it81 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it80;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it82 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it81;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it9 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it8;
ap_reg_ppstg_f_reg_4045_pp0_it11 <= f_reg_4045;
ap_reg_ppstg_f_reg_4045_pp0_it12 <= ap_reg_ppstg_f_reg_4045_pp0_it11;
ap_reg_ppstg_f_reg_4045_pp0_it13 <= ap_reg_ppstg_f_reg_4045_pp0_it12;
ap_reg_ppstg_f_reg_4045_pp0_it14 <= ap_reg_ppstg_f_reg_4045_pp0_it13;
ap_reg_ppstg_f_reg_4045_pp0_it15 <= ap_reg_ppstg_f_reg_4045_pp0_it14;
ap_reg_ppstg_f_reg_4045_pp0_it16 <= ap_reg_ppstg_f_reg_4045_pp0_it15;
ap_reg_ppstg_f_reg_4045_pp0_it17 <= ap_reg_ppstg_f_reg_4045_pp0_it16;
ap_reg_ppstg_f_reg_4045_pp0_it18 <= ap_reg_ppstg_f_reg_4045_pp0_it17;
ap_reg_ppstg_f_reg_4045_pp0_it19 <= ap_reg_ppstg_f_reg_4045_pp0_it18;
ap_reg_ppstg_f_reg_4045_pp0_it20 <= ap_reg_ppstg_f_reg_4045_pp0_it19;
ap_reg_ppstg_f_reg_4045_pp0_it21 <= ap_reg_ppstg_f_reg_4045_pp0_it20;
ap_reg_ppstg_f_reg_4045_pp0_it22 <= ap_reg_ppstg_f_reg_4045_pp0_it21;
ap_reg_ppstg_f_reg_4045_pp0_it23 <= ap_reg_ppstg_f_reg_4045_pp0_it22;
ap_reg_ppstg_f_reg_4045_pp0_it24 <= ap_reg_ppstg_f_reg_4045_pp0_it23;
ap_reg_ppstg_g_reg_4073_pp0_it12 <= g_reg_4073;
ap_reg_ppstg_g_reg_4073_pp0_it13 <= ap_reg_ppstg_g_reg_4073_pp0_it12;
ap_reg_ppstg_g_reg_4073_pp0_it14 <= ap_reg_ppstg_g_reg_4073_pp0_it13;
ap_reg_ppstg_g_reg_4073_pp0_it15 <= ap_reg_ppstg_g_reg_4073_pp0_it14;
ap_reg_ppstg_g_reg_4073_pp0_it16 <= ap_reg_ppstg_g_reg_4073_pp0_it15;
ap_reg_ppstg_g_reg_4073_pp0_it17 <= ap_reg_ppstg_g_reg_4073_pp0_it16;
ap_reg_ppstg_g_reg_4073_pp0_it18 <= ap_reg_ppstg_g_reg_4073_pp0_it17;
ap_reg_ppstg_g_reg_4073_pp0_it19 <= ap_reg_ppstg_g_reg_4073_pp0_it18;
ap_reg_ppstg_g_reg_4073_pp0_it20 <= ap_reg_ppstg_g_reg_4073_pp0_it19;
ap_reg_ppstg_g_reg_4073_pp0_it21 <= ap_reg_ppstg_g_reg_4073_pp0_it20;
ap_reg_ppstg_g_reg_4073_pp0_it22 <= ap_reg_ppstg_g_reg_4073_pp0_it21;
ap_reg_ppstg_g_reg_4073_pp0_it23 <= ap_reg_ppstg_g_reg_4073_pp0_it22;
ap_reg_ppstg_g_reg_4073_pp0_it24 <= ap_reg_ppstg_g_reg_4073_pp0_it23;
ap_reg_ppstg_g_reg_4073_pp0_it25 <= ap_reg_ppstg_g_reg_4073_pp0_it24;
ap_reg_ppstg_g_reg_4073_pp0_it26 <= ap_reg_ppstg_g_reg_4073_pp0_it25;
ap_reg_ppstg_g_reg_4073_pp0_it27 <= ap_reg_ppstg_g_reg_4073_pp0_it26;
ap_reg_ppstg_g_reg_4073_pp0_it28 <= ap_reg_ppstg_g_reg_4073_pp0_it27;
ap_reg_ppstg_g_reg_4073_pp0_it29 <= ap_reg_ppstg_g_reg_4073_pp0_it28;
ap_reg_ppstg_g_reg_4073_pp0_it30 <= ap_reg_ppstg_g_reg_4073_pp0_it29;
ap_reg_ppstg_g_reg_4073_pp0_it31 <= ap_reg_ppstg_g_reg_4073_pp0_it30;
ap_reg_ppstg_g_reg_4073_pp0_it32 <= ap_reg_ppstg_g_reg_4073_pp0_it31;
ap_reg_ppstg_g_reg_4073_pp0_it33 <= ap_reg_ppstg_g_reg_4073_pp0_it32;
ap_reg_ppstg_h_reg_4080_pp0_it12 <= h_reg_4080;
ap_reg_ppstg_h_reg_4080_pp0_it13 <= ap_reg_ppstg_h_reg_4080_pp0_it12;
ap_reg_ppstg_h_reg_4080_pp0_it14 <= ap_reg_ppstg_h_reg_4080_pp0_it13;
ap_reg_ppstg_h_reg_4080_pp0_it15 <= ap_reg_ppstg_h_reg_4080_pp0_it14;
ap_reg_ppstg_h_reg_4080_pp0_it16 <= ap_reg_ppstg_h_reg_4080_pp0_it15;
ap_reg_ppstg_h_reg_4080_pp0_it17 <= ap_reg_ppstg_h_reg_4080_pp0_it16;
ap_reg_ppstg_h_reg_4080_pp0_it18 <= ap_reg_ppstg_h_reg_4080_pp0_it17;
ap_reg_ppstg_h_reg_4080_pp0_it19 <= ap_reg_ppstg_h_reg_4080_pp0_it18;
ap_reg_ppstg_h_reg_4080_pp0_it20 <= ap_reg_ppstg_h_reg_4080_pp0_it19;
ap_reg_ppstg_h_reg_4080_pp0_it21 <= ap_reg_ppstg_h_reg_4080_pp0_it20;
ap_reg_ppstg_h_reg_4080_pp0_it22 <= ap_reg_ppstg_h_reg_4080_pp0_it21;
ap_reg_ppstg_h_reg_4080_pp0_it23 <= ap_reg_ppstg_h_reg_4080_pp0_it22;
ap_reg_ppstg_h_reg_4080_pp0_it24 <= ap_reg_ppstg_h_reg_4080_pp0_it23;
ap_reg_ppstg_i_1_reg_4087_pp0_it12 <= i_1_reg_4087;
ap_reg_ppstg_i_1_reg_4087_pp0_it13 <= ap_reg_ppstg_i_1_reg_4087_pp0_it12;
ap_reg_ppstg_i_1_reg_4087_pp0_it14 <= ap_reg_ppstg_i_1_reg_4087_pp0_it13;
ap_reg_ppstg_i_1_reg_4087_pp0_it15 <= ap_reg_ppstg_i_1_reg_4087_pp0_it14;
ap_reg_ppstg_i_1_reg_4087_pp0_it16 <= ap_reg_ppstg_i_1_reg_4087_pp0_it15;
ap_reg_ppstg_i_1_reg_4087_pp0_it17 <= ap_reg_ppstg_i_1_reg_4087_pp0_it16;
ap_reg_ppstg_i_1_reg_4087_pp0_it18 <= ap_reg_ppstg_i_1_reg_4087_pp0_it17;
ap_reg_ppstg_i_1_reg_4087_pp0_it19 <= ap_reg_ppstg_i_1_reg_4087_pp0_it18;
ap_reg_ppstg_i_1_reg_4087_pp0_it20 <= ap_reg_ppstg_i_1_reg_4087_pp0_it19;
ap_reg_ppstg_i_1_reg_4087_pp0_it21 <= ap_reg_ppstg_i_1_reg_4087_pp0_it20;
ap_reg_ppstg_i_1_reg_4087_pp0_it22 <= ap_reg_ppstg_i_1_reg_4087_pp0_it21;
ap_reg_ppstg_i_1_reg_4087_pp0_it23 <= ap_reg_ppstg_i_1_reg_4087_pp0_it22;
ap_reg_ppstg_i_1_reg_4087_pp0_it24 <= ap_reg_ppstg_i_1_reg_4087_pp0_it23;
ap_reg_ppstg_j_reg_4052_pp0_it11 <= j_reg_4052;
ap_reg_ppstg_j_reg_4052_pp0_it12 <= ap_reg_ppstg_j_reg_4052_pp0_it11;
ap_reg_ppstg_j_reg_4052_pp0_it13 <= ap_reg_ppstg_j_reg_4052_pp0_it12;
ap_reg_ppstg_j_reg_4052_pp0_it14 <= ap_reg_ppstg_j_reg_4052_pp0_it13;
ap_reg_ppstg_j_reg_4052_pp0_it15 <= ap_reg_ppstg_j_reg_4052_pp0_it14;
ap_reg_ppstg_j_reg_4052_pp0_it16 <= ap_reg_ppstg_j_reg_4052_pp0_it15;
ap_reg_ppstg_j_reg_4052_pp0_it17 <= ap_reg_ppstg_j_reg_4052_pp0_it16;
ap_reg_ppstg_j_reg_4052_pp0_it18 <= ap_reg_ppstg_j_reg_4052_pp0_it17;
ap_reg_ppstg_j_reg_4052_pp0_it19 <= ap_reg_ppstg_j_reg_4052_pp0_it18;
ap_reg_ppstg_j_reg_4052_pp0_it20 <= ap_reg_ppstg_j_reg_4052_pp0_it19;
ap_reg_ppstg_j_reg_4052_pp0_it21 <= ap_reg_ppstg_j_reg_4052_pp0_it20;
ap_reg_ppstg_j_reg_4052_pp0_it22 <= ap_reg_ppstg_j_reg_4052_pp0_it21;
ap_reg_ppstg_j_reg_4052_pp0_it23 <= ap_reg_ppstg_j_reg_4052_pp0_it22;
ap_reg_ppstg_j_reg_4052_pp0_it24 <= ap_reg_ppstg_j_reg_4052_pp0_it23;
ap_reg_ppstg_k_reg_4059_pp0_it11 <= k_reg_4059;
ap_reg_ppstg_k_reg_4059_pp0_it12 <= ap_reg_ppstg_k_reg_4059_pp0_it11;
ap_reg_ppstg_k_reg_4059_pp0_it13 <= ap_reg_ppstg_k_reg_4059_pp0_it12;
ap_reg_ppstg_k_reg_4059_pp0_it14 <= ap_reg_ppstg_k_reg_4059_pp0_it13;
ap_reg_ppstg_k_reg_4059_pp0_it15 <= ap_reg_ppstg_k_reg_4059_pp0_it14;
ap_reg_ppstg_k_reg_4059_pp0_it16 <= ap_reg_ppstg_k_reg_4059_pp0_it15;
ap_reg_ppstg_k_reg_4059_pp0_it17 <= ap_reg_ppstg_k_reg_4059_pp0_it16;
ap_reg_ppstg_k_reg_4059_pp0_it18 <= ap_reg_ppstg_k_reg_4059_pp0_it17;
ap_reg_ppstg_k_reg_4059_pp0_it19 <= ap_reg_ppstg_k_reg_4059_pp0_it18;
ap_reg_ppstg_k_reg_4059_pp0_it20 <= ap_reg_ppstg_k_reg_4059_pp0_it19;
ap_reg_ppstg_k_reg_4059_pp0_it21 <= ap_reg_ppstg_k_reg_4059_pp0_it20;
ap_reg_ppstg_k_reg_4059_pp0_it22 <= ap_reg_ppstg_k_reg_4059_pp0_it21;
ap_reg_ppstg_k_reg_4059_pp0_it23 <= ap_reg_ppstg_k_reg_4059_pp0_it22;
ap_reg_ppstg_k_reg_4059_pp0_it24 <= ap_reg_ppstg_k_reg_4059_pp0_it23;
ap_reg_ppstg_l_reg_4066_pp0_it11 <= l_reg_4066;
ap_reg_ppstg_l_reg_4066_pp0_it12 <= ap_reg_ppstg_l_reg_4066_pp0_it11;
ap_reg_ppstg_l_reg_4066_pp0_it13 <= ap_reg_ppstg_l_reg_4066_pp0_it12;
ap_reg_ppstg_l_reg_4066_pp0_it14 <= ap_reg_ppstg_l_reg_4066_pp0_it13;
ap_reg_ppstg_l_reg_4066_pp0_it15 <= ap_reg_ppstg_l_reg_4066_pp0_it14;
ap_reg_ppstg_l_reg_4066_pp0_it16 <= ap_reg_ppstg_l_reg_4066_pp0_it15;
ap_reg_ppstg_l_reg_4066_pp0_it17 <= ap_reg_ppstg_l_reg_4066_pp0_it16;
ap_reg_ppstg_l_reg_4066_pp0_it18 <= ap_reg_ppstg_l_reg_4066_pp0_it17;
ap_reg_ppstg_l_reg_4066_pp0_it19 <= ap_reg_ppstg_l_reg_4066_pp0_it18;
ap_reg_ppstg_l_reg_4066_pp0_it20 <= ap_reg_ppstg_l_reg_4066_pp0_it19;
ap_reg_ppstg_l_reg_4066_pp0_it21 <= ap_reg_ppstg_l_reg_4066_pp0_it20;
ap_reg_ppstg_l_reg_4066_pp0_it22 <= ap_reg_ppstg_l_reg_4066_pp0_it21;
ap_reg_ppstg_l_reg_4066_pp0_it23 <= ap_reg_ppstg_l_reg_4066_pp0_it22;
ap_reg_ppstg_l_reg_4066_pp0_it24 <= ap_reg_ppstg_l_reg_4066_pp0_it23;
ap_reg_ppstg_l_reg_4066_pp0_it25 <= ap_reg_ppstg_l_reg_4066_pp0_it24;
ap_reg_ppstg_l_reg_4066_pp0_it26 <= ap_reg_ppstg_l_reg_4066_pp0_it25;
ap_reg_ppstg_l_reg_4066_pp0_it27 <= ap_reg_ppstg_l_reg_4066_pp0_it26;
ap_reg_ppstg_l_reg_4066_pp0_it28 <= ap_reg_ppstg_l_reg_4066_pp0_it27;
ap_reg_ppstg_l_reg_4066_pp0_it29 <= ap_reg_ppstg_l_reg_4066_pp0_it28;
ap_reg_ppstg_l_reg_4066_pp0_it30 <= ap_reg_ppstg_l_reg_4066_pp0_it29;
ap_reg_ppstg_l_reg_4066_pp0_it31 <= ap_reg_ppstg_l_reg_4066_pp0_it30;
ap_reg_ppstg_l_reg_4066_pp0_it32 <= ap_reg_ppstg_l_reg_4066_pp0_it31;
ap_reg_ppstg_l_reg_4066_pp0_it33 <= ap_reg_ppstg_l_reg_4066_pp0_it32;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2 <= rdx_assign_new_reg_3914;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2 <= rdy_assign_new_reg_3919;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2 <= rdz_assign_new_reg_3924;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8;
ap_reg_ppstg_reg_725_pp0_it10 <= ap_reg_ppstg_reg_725_pp0_it9;
ap_reg_ppstg_reg_725_pp0_it11 <= ap_reg_ppstg_reg_725_pp0_it10;
ap_reg_ppstg_reg_725_pp0_it12 <= ap_reg_ppstg_reg_725_pp0_it11;
ap_reg_ppstg_reg_725_pp0_it13 <= ap_reg_ppstg_reg_725_pp0_it12;
ap_reg_ppstg_reg_725_pp0_it14 <= ap_reg_ppstg_reg_725_pp0_it13;
ap_reg_ppstg_reg_725_pp0_it15 <= ap_reg_ppstg_reg_725_pp0_it14;
ap_reg_ppstg_reg_725_pp0_it16 <= ap_reg_ppstg_reg_725_pp0_it15;
ap_reg_ppstg_reg_725_pp0_it17 <= ap_reg_ppstg_reg_725_pp0_it16;
ap_reg_ppstg_reg_725_pp0_it18 <= ap_reg_ppstg_reg_725_pp0_it17;
ap_reg_ppstg_reg_725_pp0_it19 <= ap_reg_ppstg_reg_725_pp0_it18;
ap_reg_ppstg_reg_725_pp0_it2 <= reg_725;
ap_reg_ppstg_reg_725_pp0_it20 <= ap_reg_ppstg_reg_725_pp0_it19;
ap_reg_ppstg_reg_725_pp0_it21 <= ap_reg_ppstg_reg_725_pp0_it20;
ap_reg_ppstg_reg_725_pp0_it22 <= ap_reg_ppstg_reg_725_pp0_it21;
ap_reg_ppstg_reg_725_pp0_it23 <= ap_reg_ppstg_reg_725_pp0_it22;
ap_reg_ppstg_reg_725_pp0_it24 <= ap_reg_ppstg_reg_725_pp0_it23;
ap_reg_ppstg_reg_725_pp0_it25 <= ap_reg_ppstg_reg_725_pp0_it24;
ap_reg_ppstg_reg_725_pp0_it26 <= ap_reg_ppstg_reg_725_pp0_it25;
ap_reg_ppstg_reg_725_pp0_it27 <= ap_reg_ppstg_reg_725_pp0_it26;
ap_reg_ppstg_reg_725_pp0_it28 <= ap_reg_ppstg_reg_725_pp0_it27;
ap_reg_ppstg_reg_725_pp0_it29 <= ap_reg_ppstg_reg_725_pp0_it28;
ap_reg_ppstg_reg_725_pp0_it3 <= ap_reg_ppstg_reg_725_pp0_it2;
ap_reg_ppstg_reg_725_pp0_it30 <= ap_reg_ppstg_reg_725_pp0_it29;
ap_reg_ppstg_reg_725_pp0_it31 <= ap_reg_ppstg_reg_725_pp0_it30;
ap_reg_ppstg_reg_725_pp0_it32 <= ap_reg_ppstg_reg_725_pp0_it31;
ap_reg_ppstg_reg_725_pp0_it33 <= ap_reg_ppstg_reg_725_pp0_it32;
ap_reg_ppstg_reg_725_pp0_it34 <= ap_reg_ppstg_reg_725_pp0_it33;
ap_reg_ppstg_reg_725_pp0_it35 <= ap_reg_ppstg_reg_725_pp0_it34;
ap_reg_ppstg_reg_725_pp0_it36 <= ap_reg_ppstg_reg_725_pp0_it35;
ap_reg_ppstg_reg_725_pp0_it37 <= ap_reg_ppstg_reg_725_pp0_it36;
ap_reg_ppstg_reg_725_pp0_it38 <= ap_reg_ppstg_reg_725_pp0_it37;
ap_reg_ppstg_reg_725_pp0_it39 <= ap_reg_ppstg_reg_725_pp0_it38;
ap_reg_ppstg_reg_725_pp0_it4 <= ap_reg_ppstg_reg_725_pp0_it3;
ap_reg_ppstg_reg_725_pp0_it40 <= ap_reg_ppstg_reg_725_pp0_it39;
ap_reg_ppstg_reg_725_pp0_it41 <= ap_reg_ppstg_reg_725_pp0_it40;
ap_reg_ppstg_reg_725_pp0_it42 <= ap_reg_ppstg_reg_725_pp0_it41;
ap_reg_ppstg_reg_725_pp0_it43 <= ap_reg_ppstg_reg_725_pp0_it42;
ap_reg_ppstg_reg_725_pp0_it44 <= ap_reg_ppstg_reg_725_pp0_it43;
ap_reg_ppstg_reg_725_pp0_it45 <= ap_reg_ppstg_reg_725_pp0_it44;
ap_reg_ppstg_reg_725_pp0_it46 <= ap_reg_ppstg_reg_725_pp0_it45;
ap_reg_ppstg_reg_725_pp0_it47 <= ap_reg_ppstg_reg_725_pp0_it46;
ap_reg_ppstg_reg_725_pp0_it48 <= ap_reg_ppstg_reg_725_pp0_it47;
ap_reg_ppstg_reg_725_pp0_it49 <= ap_reg_ppstg_reg_725_pp0_it48;
ap_reg_ppstg_reg_725_pp0_it5 <= ap_reg_ppstg_reg_725_pp0_it4;
ap_reg_ppstg_reg_725_pp0_it50 <= ap_reg_ppstg_reg_725_pp0_it49;
ap_reg_ppstg_reg_725_pp0_it51 <= ap_reg_ppstg_reg_725_pp0_it50;
ap_reg_ppstg_reg_725_pp0_it52 <= ap_reg_ppstg_reg_725_pp0_it51;
ap_reg_ppstg_reg_725_pp0_it53 <= ap_reg_ppstg_reg_725_pp0_it52;
ap_reg_ppstg_reg_725_pp0_it54 <= ap_reg_ppstg_reg_725_pp0_it53;
ap_reg_ppstg_reg_725_pp0_it55 <= ap_reg_ppstg_reg_725_pp0_it54;
ap_reg_ppstg_reg_725_pp0_it56 <= ap_reg_ppstg_reg_725_pp0_it55;
ap_reg_ppstg_reg_725_pp0_it57 <= ap_reg_ppstg_reg_725_pp0_it56;
ap_reg_ppstg_reg_725_pp0_it58 <= ap_reg_ppstg_reg_725_pp0_it57;
ap_reg_ppstg_reg_725_pp0_it59 <= ap_reg_ppstg_reg_725_pp0_it58;
ap_reg_ppstg_reg_725_pp0_it6 <= ap_reg_ppstg_reg_725_pp0_it5;
ap_reg_ppstg_reg_725_pp0_it60 <= ap_reg_ppstg_reg_725_pp0_it59;
ap_reg_ppstg_reg_725_pp0_it61 <= ap_reg_ppstg_reg_725_pp0_it60;
ap_reg_ppstg_reg_725_pp0_it62 <= ap_reg_ppstg_reg_725_pp0_it61;
ap_reg_ppstg_reg_725_pp0_it63 <= ap_reg_ppstg_reg_725_pp0_it62;
ap_reg_ppstg_reg_725_pp0_it64 <= ap_reg_ppstg_reg_725_pp0_it63;
ap_reg_ppstg_reg_725_pp0_it65 <= ap_reg_ppstg_reg_725_pp0_it64;
ap_reg_ppstg_reg_725_pp0_it66 <= ap_reg_ppstg_reg_725_pp0_it65;
ap_reg_ppstg_reg_725_pp0_it67 <= ap_reg_ppstg_reg_725_pp0_it66;
ap_reg_ppstg_reg_725_pp0_it68 <= ap_reg_ppstg_reg_725_pp0_it67;
ap_reg_ppstg_reg_725_pp0_it69 <= ap_reg_ppstg_reg_725_pp0_it68;
ap_reg_ppstg_reg_725_pp0_it7 <= ap_reg_ppstg_reg_725_pp0_it6;
ap_reg_ppstg_reg_725_pp0_it70 <= ap_reg_ppstg_reg_725_pp0_it69;
ap_reg_ppstg_reg_725_pp0_it71 <= ap_reg_ppstg_reg_725_pp0_it70;
ap_reg_ppstg_reg_725_pp0_it72 <= ap_reg_ppstg_reg_725_pp0_it71;
ap_reg_ppstg_reg_725_pp0_it73 <= ap_reg_ppstg_reg_725_pp0_it72;
ap_reg_ppstg_reg_725_pp0_it74 <= ap_reg_ppstg_reg_725_pp0_it73;
ap_reg_ppstg_reg_725_pp0_it75 <= ap_reg_ppstg_reg_725_pp0_it74;
ap_reg_ppstg_reg_725_pp0_it76 <= ap_reg_ppstg_reg_725_pp0_it75;
ap_reg_ppstg_reg_725_pp0_it77 <= ap_reg_ppstg_reg_725_pp0_it76;
ap_reg_ppstg_reg_725_pp0_it78 <= ap_reg_ppstg_reg_725_pp0_it77;
ap_reg_ppstg_reg_725_pp0_it79 <= ap_reg_ppstg_reg_725_pp0_it78;
ap_reg_ppstg_reg_725_pp0_it8 <= ap_reg_ppstg_reg_725_pp0_it7;
ap_reg_ppstg_reg_725_pp0_it80 <= ap_reg_ppstg_reg_725_pp0_it79;
ap_reg_ppstg_reg_725_pp0_it81 <= ap_reg_ppstg_reg_725_pp0_it80;
ap_reg_ppstg_reg_725_pp0_it9 <= ap_reg_ppstg_reg_725_pp0_it8;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48 <= tmp_25_i_reg_4275;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48 <= tmp_31_i_reg_4280;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48 <= tmp_36_i_reg_4285;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300)) then
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1 <= data_array_addr_20_reg_3863;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it1 <= exitcond2_reg_3854;
exitcond2_reg_3854 <= exitcond2_fu_2840_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it81)) then
beta_addr_111281129_part_set_reg_4307 <= beta_addr_111281129_part_set_fu_3103_p5;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (ap_const_lv1_0 = exitcond2_fu_2840_p2))) then
data_array_addr_20_reg_3863 <= tmp_1_fu_2852_p1(5 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
data_array_load_1_reg_3743 <= data_array_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72))) then
data_array_load_2_reg_3722 <= data_array_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87))) then
data_array_load_3_reg_3759 <= data_array_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it10)) then
g_reg_4073 <= g_fu_3055_p1;
h_reg_4080 <= h_fu_3059_p1;
i_1_reg_4087 <= i_1_fu_3063_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it76)) then
im_reg_4290 <= grp_fu_630_p2;
tmp_61_neg_i_reg_4297 <= tmp_61_neg_i_fu_3071_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14))) then
ins_data_val14_reg_3415 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15))) then
ins_data_val15_reg_3420 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16))) then
ins_data_val16_reg_3425 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
ins_data_val17_reg_3430 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18))) then
ins_data_val18_reg_3435 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19))) then
ins_data_val19_reg_3440 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20))) then
ins_data_val20_reg_3445 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21))) then
ins_data_val21_reg_3450 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22))) then
ins_data_val22_reg_3455 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23))) then
ins_data_val23_reg_3460 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24))) then
ins_data_val24_reg_3465 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25))) then
ins_data_val25_reg_3470 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26))) then
ins_data_val26_reg_3475 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27))) then
ins_data_val27_reg_3480 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28))) then
ins_data_val28_reg_3485 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
ins_data_val29_reg_3490 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30))) then
ins_data_val30_reg_3495 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31))) then
ins_data_val31_reg_3500 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32))) then
ins_data_val32_reg_3505 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33))) then
ins_data_val33_reg_3510 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34))) then
ins_data_val34_reg_3515 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st36_fsm_35))) then
ins_data_val35_reg_3520 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st37_fsm_36))) then
ins_data_val36_reg_3525 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st38_fsm_37))) then
ins_data_val37_reg_3530 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38))) then
ins_data_val38_reg_3535 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39))) then
ins_data_val39_reg_3540 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40))) then
ins_data_val40_reg_3545 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41))) then
ins_data_val41_reg_3550 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42))) then
ins_data_val42_reg_3555 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43))) then
ins_data_val43_reg_3560 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st45_fsm_44))) then
ins_data_val44_reg_3565 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45))) then
ins_data_val45_reg_3570 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46))) then
ins_data_val46_reg_3575 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47))) then
ins_data_val47_reg_3580 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48))) then
ins_data_val48_reg_3585 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st50_fsm_49))) then
ins_data_val49_reg_3590 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st51_fsm_50))) then
ins_data_val50_reg_3595 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st52_fsm_51))) then
ins_data_val51_reg_3600 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52))) then
ins_data_val52_reg_3605 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st54_fsm_53))) then
ins_data_val53_reg_3610 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st55_fsm_54))) then
ins_data_val54_reg_3615 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st56_fsm_55))) then
ins_data_val55_reg_3620 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st57_fsm_56))) then
ins_data_val56_reg_3625 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st58_fsm_57))) then
ins_data_val57_reg_3630 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st59_fsm_58))) then
ins_data_val58_reg_3635 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st60_fsm_59))) then
ins_data_val59_reg_3640 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st61_fsm_60))) then
ins_data_val60_reg_3645 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st62_fsm_61))) then
ins_data_val61_reg_3650 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st63_fsm_62))) then
ins_data_val62_reg_3655 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st64_fsm_63))) then
ins_data_val63_reg_3660 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st65_fsm_64))) then
ins_data_val64_reg_3665 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st66_fsm_65))) then
ins_data_val65_reg_3670 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st67_fsm_66))) then
ins_data_val66_reg_3675 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st68_fsm_67))) then
ins_data_val67_reg_3680 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st69_fsm_68))) then
ins_data_val68_reg_3685 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st70_fsm_69))) then
ins_data_val69_reg_3690 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st71_fsm_70))) then
ins_data_val70_reg_3695 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71))) then
ins_data_val71_reg_3706 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299))) then
ins_dest_V_val_reg_3849 <= ins_TDEST;
ins_id_V_val_reg_3844 <= ins_TID;
ins_keep_V_val_reg_3824 <= ins_TKEEP;
ins_last_V_val_reg_3839 <= ins_TLAST;
ins_strb_V_val_reg_3829 <= ins_TSTRB;
ins_user_V_val_reg_3834 <= ins_TUSER;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it46)) then
m_reg_4270 <= grp_fu_506_p2;
tmp_25_i_reg_4275 <= grp_fu_510_p2;
tmp_31_i_reg_4280 <= grp_fu_514_p2;
tmp_36_i_reg_4285 <= grp_fu_518_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (exitcond2_reg_3854 = ap_const_lv1_0))) then
rdx_assign_new_reg_3914 <= data_array_q0(319 downto 288);
rdy_assign_new_reg_3919 <= data_array_q0(351 downto 320);
rdz_assign_new_reg_3924 <= data_array_q0(383 downto 352);
rex_assign_new_reg_3929 <= data_array_q0(415 downto 384);
rey_assign_new_reg_3934 <= data_array_q0(447 downto 416);
rez_assign_new_reg_3939 <= data_array_q0(479 downto 448);
tmp_22_reg_3869 <= tmp_22_fu_2857_p1;
v0y_assign_new_reg_3874 <= data_array_q0(63 downto 32);
v0z_assign_new_reg_3879 <= data_array_q0(95 downto 64);
v1x_assign_new_reg_3884 <= data_array_q0(127 downto 96);
v1y_assign_new_reg_3889 <= data_array_q0(159 downto 128);
v1z_assign_new_reg_3894 <= data_array_q0(191 downto 160);
v2x_assign_new_reg_3899 <= data_array_q0(223 downto 192);
v2y_assign_new_reg_3904 <= data_array_q0(255 downto 224);
v2z_assign_new_reg_3909 <= data_array_q0(287 downto 256);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ins_TVALID = ap_const_logic_0))) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st76_fsm_75)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st91_fsm_90)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st106_fsm_105)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st136_fsm_135)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st181_fsm_180)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st196_fsm_195)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st211_fsm_210)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st226_fsm_225)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st241_fsm_240)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st256_fsm_255)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st271_fsm_270)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st286_fsm_285)))) then
reg_669 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st107_fsm_106)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st137_fsm_136)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st167_fsm_166)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st182_fsm_181)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st197_fsm_196)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st212_fsm_211)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st227_fsm_226)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st242_fsm_241)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st257_fsm_256)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st272_fsm_271)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st287_fsm_286)))) then
reg_673 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st108_fsm_107)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st168_fsm_167)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st183_fsm_182)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st198_fsm_197)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st213_fsm_212)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st228_fsm_227)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st243_fsm_242)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st258_fsm_257)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st273_fsm_272)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st288_fsm_287)))) then
reg_677 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st109_fsm_108)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st169_fsm_168)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st184_fsm_183)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st199_fsm_198)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st214_fsm_213)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st229_fsm_228)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st244_fsm_243)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st259_fsm_258)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st274_fsm_273)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st289_fsm_288)))) then
reg_681 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st95_fsm_94)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st110_fsm_109)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st125_fsm_124)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st170_fsm_169)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st185_fsm_184)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st200_fsm_199)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st215_fsm_214)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st230_fsm_229)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st245_fsm_244)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st260_fsm_259)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st275_fsm_274)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st290_fsm_289)))) then
reg_685 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st96_fsm_95)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st111_fsm_110)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st126_fsm_125)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st171_fsm_170)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st186_fsm_185)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st201_fsm_200)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st216_fsm_215)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st231_fsm_230)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st246_fsm_245)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st261_fsm_260)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st276_fsm_275)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st291_fsm_290)))) then
reg_689 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st112_fsm_111)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st127_fsm_126)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st157_fsm_156)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st172_fsm_171)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st187_fsm_186)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st202_fsm_201)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st217_fsm_216)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st232_fsm_231)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st247_fsm_246)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st262_fsm_261)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st277_fsm_276)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st292_fsm_291)))) then
reg_693 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st113_fsm_112)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st128_fsm_127)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st158_fsm_157)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st173_fsm_172)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st188_fsm_187)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st203_fsm_202)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st218_fsm_217)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st233_fsm_232)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st248_fsm_247)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st263_fsm_262)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st278_fsm_277)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st293_fsm_292)))) then
reg_697 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st114_fsm_113)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st159_fsm_158)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st174_fsm_173)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st189_fsm_188)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st204_fsm_203)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st219_fsm_218)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st234_fsm_233)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st249_fsm_248)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st264_fsm_263)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st279_fsm_278)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st294_fsm_293)))) then
reg_701 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st85_fsm_84)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st100_fsm_99)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st130_fsm_129)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st175_fsm_174)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st190_fsm_189)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st205_fsm_204)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st220_fsm_219)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st235_fsm_234)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st250_fsm_249)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st265_fsm_264)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st280_fsm_279)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st295_fsm_294)))) then
reg_705 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st101_fsm_100)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_115)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st131_fsm_130)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st176_fsm_175)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st191_fsm_190)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st206_fsm_205)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st221_fsm_220)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st236_fsm_235)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st251_fsm_250)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st266_fsm_265)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st281_fsm_280)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st296_fsm_295)))) then
reg_709 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st102_fsm_101)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st132_fsm_131)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st177_fsm_176)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st192_fsm_191)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st207_fsm_206)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st222_fsm_221)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st237_fsm_236)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st252_fsm_251)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st267_fsm_266)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st282_fsm_281)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st297_fsm_296)))) then
reg_713 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st103_fsm_102)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st133_fsm_132)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st178_fsm_177)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st193_fsm_192)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st208_fsm_207)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st223_fsm_222)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st238_fsm_237)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st253_fsm_252)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st268_fsm_267)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st283_fsm_282)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st298_fsm_297)))) then
reg_717 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st104_fsm_103)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st134_fsm_133)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st179_fsm_178)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st194_fsm_193)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st209_fsm_208)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st224_fsm_223)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st239_fsm_238)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st254_fsm_253)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st269_fsm_268)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st284_fsm_283)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st299_fsm_298)))) then
reg_721 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300) and (exitcond2_reg_3854 = ap_const_lv1_0)))) then
reg_725 <= data_array_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) and not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359)))) then
reg_729 <= data_array_q1(543 downto 512);
reg_733 <= data_array_q1(575 downto 544);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it32)) then
tmp_10_i_reg_4218 <= grp_fu_482_p2;
tmp_23_i_reg_4224 <= grp_fu_486_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it37)) then
tmp_11_i_reg_4235 <= grp_fu_602_p2;
tmp_20_i_reg_4240 <= grp_fu_494_p2;
tmp_24_i_reg_4245 <= grp_fu_606_p2;
tmp_29_i_reg_4250 <= grp_fu_498_p2;
tmp_30_i_reg_4255 <= grp_fu_610_p2;
tmp_34_i_reg_4260 <= grp_fu_502_p2;
tmp_35_i_reg_4265 <= grp_fu_614_p2;
tmp_7_i_reg_4230 <= grp_fu_490_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it14)) then
tmp_12_i_reg_4114 <= grp_fu_538_p2;
tmp_13_i_reg_4119 <= grp_fu_542_p2;
tmp_16_i_reg_4124 <= grp_fu_546_p2;
tmp_17_i_reg_4129 <= grp_fu_550_p2;
tmp_3_i_reg_4104 <= grp_fu_530_p2;
tmp_4_i_reg_4109 <= grp_fu_534_p2;
tmp_i_311_reg_4099 <= grp_fu_526_p2;
tmp_i_reg_4094 <= grp_fu_522_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it23)) then
tmp_14_i_reg_4156 <= grp_fu_474_p2;
tmp_18_i_reg_4162 <= grp_fu_478_p2;
tmp_1_i_reg_4134 <= grp_fu_466_p2;
tmp_21_i_reg_4168 <= grp_fu_562_p2;
tmp_22_i_reg_4173 <= grp_fu_566_p2;
tmp_5_i_reg_4140 <= grp_fu_470_p2;
tmp_8_i_reg_4146 <= grp_fu_554_p2;
tmp_9_i_reg_4151 <= grp_fu_558_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it28)) then
tmp_15_i_reg_4188 <= grp_fu_578_p2;
tmp_19_i_reg_4193 <= grp_fu_582_p2;
tmp_27_i_reg_4198 <= grp_fu_586_p2;
tmp_28_i_reg_4203 <= grp_fu_590_p2;
tmp_2_i_reg_4178 <= grp_fu_570_p2;
tmp_32_i_reg_4208 <= grp_fu_594_p2;
tmp_33_i_reg_4213 <= grp_fu_598_p2;
tmp_6_i_reg_4183 <= grp_fu_574_p2;
end if;
end if;
end process;
data_array_addr_16_reg_3700(4 downto 0) <= "10000";
data_array_addr_18_reg_3711(4 downto 0) <= "10010";
data_array_addr_reg_3717(4 downto 0) <= "00000";
data_array_addr_2_reg_3727(4 downto 0) <= "00010";
data_array_addr_4_reg_3732(4 downto 0) <= "00100";
data_array_addr_17_reg_3737(4 downto 0) <= "10001";
data_array_addr_19_reg_3748(4 downto 0) <= "10011";
data_array_addr_1_reg_3754(4 downto 0) <= "00001";
data_array_addr_3_reg_3764(4 downto 0) <= "00011";
data_array_addr_5_reg_3769(4 downto 0) <= "00101";
data_array_addr_6_reg_3774(4 downto 0) <= "00110";
data_array_addr_7_reg_3779(4 downto 0) <= "00111";
data_array_addr_8_reg_3784(4 downto 0) <= "01000";
data_array_addr_9_reg_3789(4 downto 0) <= "01001";
data_array_addr_10_reg_3794(4 downto 0) <= "01010";
data_array_addr_11_reg_3799(4 downto 0) <= "01011";
data_array_addr_12_reg_3804(4 downto 0) <= "01100";
data_array_addr_13_reg_3809(4 downto 0) <= "01101";
data_array_addr_14_reg_3814(4 downto 0) <= "01110";
data_array_addr_15_reg_3819(4 downto 0) <= "01111";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ins_TVALID, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it82, ap_reg_ppiten_pp0_it83, ap_sig_ioackin_outs_TREADY, exitcond2_fu_2840_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st7_fsm_6;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st7_fsm_6 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st8_fsm_7 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st10_fsm_9 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st11_fsm_10;
else
ap_NS_fsm <= ap_ST_st10_fsm_9;
end if;
when ap_ST_st11_fsm_10 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
else
ap_NS_fsm <= ap_ST_st11_fsm_10;
end if;
when ap_ST_st12_fsm_11 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st13_fsm_12;
else
ap_NS_fsm <= ap_ST_st12_fsm_11;
end if;
when ap_ST_st13_fsm_12 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st14_fsm_13;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st14_fsm_13 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
else
ap_NS_fsm <= ap_ST_st14_fsm_13;
end if;
when ap_ST_st15_fsm_14 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st16_fsm_15;
else
ap_NS_fsm <= ap_ST_st15_fsm_14;
end if;
when ap_ST_st16_fsm_15 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st16_fsm_15;
end if;
when ap_ST_st17_fsm_16 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st17_fsm_16;
end if;
when ap_ST_st18_fsm_17 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st19_fsm_18;
else
ap_NS_fsm <= ap_ST_st18_fsm_17;
end if;
when ap_ST_st19_fsm_18 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st19_fsm_18;
end if;
when ap_ST_st20_fsm_19 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st21_fsm_20;
else
ap_NS_fsm <= ap_ST_st20_fsm_19;
end if;
when ap_ST_st21_fsm_20 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st22_fsm_21;
else
ap_NS_fsm <= ap_ST_st21_fsm_20;
end if;
when ap_ST_st22_fsm_21 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st23_fsm_22;
else
ap_NS_fsm <= ap_ST_st22_fsm_21;
end if;
when ap_ST_st23_fsm_22 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st23_fsm_22;
end if;
when ap_ST_st24_fsm_23 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st25_fsm_24;
else
ap_NS_fsm <= ap_ST_st24_fsm_23;
end if;
when ap_ST_st25_fsm_24 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st26_fsm_25;
else
ap_NS_fsm <= ap_ST_st25_fsm_24;
end if;
when ap_ST_st26_fsm_25 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st27_fsm_26;
else
ap_NS_fsm <= ap_ST_st26_fsm_25;
end if;
when ap_ST_st27_fsm_26 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st28_fsm_27;
else
ap_NS_fsm <= ap_ST_st27_fsm_26;
end if;
when ap_ST_st28_fsm_27 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st29_fsm_28;
else
ap_NS_fsm <= ap_ST_st28_fsm_27;
end if;
when ap_ST_st29_fsm_28 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st30_fsm_29;
else
ap_NS_fsm <= ap_ST_st29_fsm_28;
end if;
when ap_ST_st30_fsm_29 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st31_fsm_30;
else
ap_NS_fsm <= ap_ST_st30_fsm_29;
end if;
when ap_ST_st31_fsm_30 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st32_fsm_31;
else
ap_NS_fsm <= ap_ST_st31_fsm_30;
end if;
when ap_ST_st32_fsm_31 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st33_fsm_32;
else
ap_NS_fsm <= ap_ST_st32_fsm_31;
end if;
when ap_ST_st33_fsm_32 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st34_fsm_33;
else
ap_NS_fsm <= ap_ST_st33_fsm_32;
end if;
when ap_ST_st34_fsm_33 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st35_fsm_34;
else
ap_NS_fsm <= ap_ST_st34_fsm_33;
end if;
when ap_ST_st35_fsm_34 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st36_fsm_35;
else
ap_NS_fsm <= ap_ST_st35_fsm_34;
end if;
when ap_ST_st36_fsm_35 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st37_fsm_36;
else
ap_NS_fsm <= ap_ST_st36_fsm_35;
end if;
when ap_ST_st37_fsm_36 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st38_fsm_37;
else
ap_NS_fsm <= ap_ST_st37_fsm_36;
end if;
when ap_ST_st38_fsm_37 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st39_fsm_38;
else
ap_NS_fsm <= ap_ST_st38_fsm_37;
end if;
when ap_ST_st39_fsm_38 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st40_fsm_39;
else
ap_NS_fsm <= ap_ST_st39_fsm_38;
end if;
when ap_ST_st40_fsm_39 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st41_fsm_40;
else
ap_NS_fsm <= ap_ST_st40_fsm_39;
end if;
when ap_ST_st41_fsm_40 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st42_fsm_41;
else
ap_NS_fsm <= ap_ST_st41_fsm_40;
end if;
when ap_ST_st42_fsm_41 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st43_fsm_42;
else
ap_NS_fsm <= ap_ST_st42_fsm_41;
end if;
when ap_ST_st43_fsm_42 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st44_fsm_43;
else
ap_NS_fsm <= ap_ST_st43_fsm_42;
end if;
when ap_ST_st44_fsm_43 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st45_fsm_44;
else
ap_NS_fsm <= ap_ST_st44_fsm_43;
end if;
when ap_ST_st45_fsm_44 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st46_fsm_45;
else
ap_NS_fsm <= ap_ST_st45_fsm_44;
end if;
when ap_ST_st46_fsm_45 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st47_fsm_46;
else
ap_NS_fsm <= ap_ST_st46_fsm_45;
end if;
when ap_ST_st47_fsm_46 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st48_fsm_47;
else
ap_NS_fsm <= ap_ST_st47_fsm_46;
end if;
when ap_ST_st48_fsm_47 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st49_fsm_48;
else
ap_NS_fsm <= ap_ST_st48_fsm_47;
end if;
when ap_ST_st49_fsm_48 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st50_fsm_49;
else
ap_NS_fsm <= ap_ST_st49_fsm_48;
end if;
when ap_ST_st50_fsm_49 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st51_fsm_50;
else
ap_NS_fsm <= ap_ST_st50_fsm_49;
end if;
when ap_ST_st51_fsm_50 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st52_fsm_51;
else
ap_NS_fsm <= ap_ST_st51_fsm_50;
end if;
when ap_ST_st52_fsm_51 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st53_fsm_52;
else
ap_NS_fsm <= ap_ST_st52_fsm_51;
end if;
when ap_ST_st53_fsm_52 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st54_fsm_53;
else
ap_NS_fsm <= ap_ST_st53_fsm_52;
end if;
when ap_ST_st54_fsm_53 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st55_fsm_54;
else
ap_NS_fsm <= ap_ST_st54_fsm_53;
end if;
when ap_ST_st55_fsm_54 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st56_fsm_55;
else
ap_NS_fsm <= ap_ST_st55_fsm_54;
end if;
when ap_ST_st56_fsm_55 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st57_fsm_56;
else
ap_NS_fsm <= ap_ST_st56_fsm_55;
end if;
when ap_ST_st57_fsm_56 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st58_fsm_57;
else
ap_NS_fsm <= ap_ST_st57_fsm_56;
end if;
when ap_ST_st58_fsm_57 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st59_fsm_58;
else
ap_NS_fsm <= ap_ST_st58_fsm_57;
end if;
when ap_ST_st59_fsm_58 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st60_fsm_59;
else
ap_NS_fsm <= ap_ST_st59_fsm_58;
end if;
when ap_ST_st60_fsm_59 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st61_fsm_60;
else
ap_NS_fsm <= ap_ST_st60_fsm_59;
end if;
when ap_ST_st61_fsm_60 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st62_fsm_61;
else
ap_NS_fsm <= ap_ST_st61_fsm_60;
end if;
when ap_ST_st62_fsm_61 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st63_fsm_62;
else
ap_NS_fsm <= ap_ST_st62_fsm_61;
end if;
when ap_ST_st63_fsm_62 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st64_fsm_63;
else
ap_NS_fsm <= ap_ST_st63_fsm_62;
end if;
when ap_ST_st64_fsm_63 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st65_fsm_64;
else
ap_NS_fsm <= ap_ST_st64_fsm_63;
end if;
when ap_ST_st65_fsm_64 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st66_fsm_65;
else
ap_NS_fsm <= ap_ST_st65_fsm_64;
end if;
when ap_ST_st66_fsm_65 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st67_fsm_66;
else
ap_NS_fsm <= ap_ST_st66_fsm_65;
end if;
when ap_ST_st67_fsm_66 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st68_fsm_67;
else
ap_NS_fsm <= ap_ST_st67_fsm_66;
end if;
when ap_ST_st68_fsm_67 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st69_fsm_68;
else
ap_NS_fsm <= ap_ST_st68_fsm_67;
end if;
when ap_ST_st69_fsm_68 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st70_fsm_69;
else
ap_NS_fsm <= ap_ST_st69_fsm_68;
end if;
when ap_ST_st70_fsm_69 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st71_fsm_70;
else
ap_NS_fsm <= ap_ST_st70_fsm_69;
end if;
when ap_ST_st71_fsm_70 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st72_fsm_71;
else
ap_NS_fsm <= ap_ST_st71_fsm_70;
end if;
when ap_ST_st72_fsm_71 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st73_fsm_72;
else
ap_NS_fsm <= ap_ST_st72_fsm_71;
end if;
when ap_ST_st73_fsm_72 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st74_fsm_73;
else
ap_NS_fsm <= ap_ST_st73_fsm_72;
end if;
when ap_ST_st74_fsm_73 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st75_fsm_74;
else
ap_NS_fsm <= ap_ST_st74_fsm_73;
end if;
when ap_ST_st75_fsm_74 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st76_fsm_75;
else
ap_NS_fsm <= ap_ST_st75_fsm_74;
end if;
when ap_ST_st76_fsm_75 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st77_fsm_76;
else
ap_NS_fsm <= ap_ST_st76_fsm_75;
end if;
when ap_ST_st77_fsm_76 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st78_fsm_77;
else
ap_NS_fsm <= ap_ST_st77_fsm_76;
end if;
when ap_ST_st78_fsm_77 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st79_fsm_78;
else
ap_NS_fsm <= ap_ST_st78_fsm_77;
end if;
when ap_ST_st79_fsm_78 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st80_fsm_79;
else
ap_NS_fsm <= ap_ST_st79_fsm_78;
end if;
when ap_ST_st80_fsm_79 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st81_fsm_80;
else
ap_NS_fsm <= ap_ST_st80_fsm_79;
end if;
when ap_ST_st81_fsm_80 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st82_fsm_81;
else
ap_NS_fsm <= ap_ST_st81_fsm_80;
end if;
when ap_ST_st82_fsm_81 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st83_fsm_82;
else
ap_NS_fsm <= ap_ST_st82_fsm_81;
end if;
when ap_ST_st83_fsm_82 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st84_fsm_83;
else
ap_NS_fsm <= ap_ST_st83_fsm_82;
end if;
when ap_ST_st84_fsm_83 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st85_fsm_84;
else
ap_NS_fsm <= ap_ST_st84_fsm_83;
end if;
when ap_ST_st85_fsm_84 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st86_fsm_85;
else
ap_NS_fsm <= ap_ST_st85_fsm_84;
end if;
when ap_ST_st86_fsm_85 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st87_fsm_86;
else
ap_NS_fsm <= ap_ST_st86_fsm_85;
end if;
when ap_ST_st87_fsm_86 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st88_fsm_87;
else
ap_NS_fsm <= ap_ST_st87_fsm_86;
end if;
when ap_ST_st88_fsm_87 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st89_fsm_88;
else
ap_NS_fsm <= ap_ST_st88_fsm_87;
end if;
when ap_ST_st89_fsm_88 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st90_fsm_89;
else
ap_NS_fsm <= ap_ST_st89_fsm_88;
end if;
when ap_ST_st90_fsm_89 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st91_fsm_90;
else
ap_NS_fsm <= ap_ST_st90_fsm_89;
end if;
when ap_ST_st91_fsm_90 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st92_fsm_91;
else
ap_NS_fsm <= ap_ST_st91_fsm_90;
end if;
when ap_ST_st92_fsm_91 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st93_fsm_92;
else
ap_NS_fsm <= ap_ST_st92_fsm_91;
end if;
when ap_ST_st93_fsm_92 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st94_fsm_93;
else
ap_NS_fsm <= ap_ST_st93_fsm_92;
end if;
when ap_ST_st94_fsm_93 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st95_fsm_94;
else
ap_NS_fsm <= ap_ST_st94_fsm_93;
end if;
when ap_ST_st95_fsm_94 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st96_fsm_95;
else
ap_NS_fsm <= ap_ST_st95_fsm_94;
end if;
when ap_ST_st96_fsm_95 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st97_fsm_96;
else
ap_NS_fsm <= ap_ST_st96_fsm_95;
end if;
when ap_ST_st97_fsm_96 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st98_fsm_97;
else
ap_NS_fsm <= ap_ST_st97_fsm_96;
end if;
when ap_ST_st98_fsm_97 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st99_fsm_98;
else
ap_NS_fsm <= ap_ST_st98_fsm_97;
end if;
when ap_ST_st99_fsm_98 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st100_fsm_99;
else
ap_NS_fsm <= ap_ST_st99_fsm_98;
end if;
when ap_ST_st100_fsm_99 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st101_fsm_100;
else
ap_NS_fsm <= ap_ST_st100_fsm_99;
end if;
when ap_ST_st101_fsm_100 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st102_fsm_101;
else
ap_NS_fsm <= ap_ST_st101_fsm_100;
end if;
when ap_ST_st102_fsm_101 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st103_fsm_102;
else
ap_NS_fsm <= ap_ST_st102_fsm_101;
end if;
when ap_ST_st103_fsm_102 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st104_fsm_103;
else
ap_NS_fsm <= ap_ST_st103_fsm_102;
end if;
when ap_ST_st104_fsm_103 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st105_fsm_104;
else
ap_NS_fsm <= ap_ST_st104_fsm_103;
end if;
when ap_ST_st105_fsm_104 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st106_fsm_105;
else
ap_NS_fsm <= ap_ST_st105_fsm_104;
end if;
when ap_ST_st106_fsm_105 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st107_fsm_106;
else
ap_NS_fsm <= ap_ST_st106_fsm_105;
end if;
when ap_ST_st107_fsm_106 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st108_fsm_107;
else
ap_NS_fsm <= ap_ST_st107_fsm_106;
end if;
when ap_ST_st108_fsm_107 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st109_fsm_108;
else
ap_NS_fsm <= ap_ST_st108_fsm_107;
end if;
when ap_ST_st109_fsm_108 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st110_fsm_109;
else
ap_NS_fsm <= ap_ST_st109_fsm_108;
end if;
when ap_ST_st110_fsm_109 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st111_fsm_110;
else
ap_NS_fsm <= ap_ST_st110_fsm_109;
end if;
when ap_ST_st111_fsm_110 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st112_fsm_111;
else
ap_NS_fsm <= ap_ST_st111_fsm_110;
end if;
when ap_ST_st112_fsm_111 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st113_fsm_112;
else
ap_NS_fsm <= ap_ST_st112_fsm_111;
end if;
when ap_ST_st113_fsm_112 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st114_fsm_113;
else
ap_NS_fsm <= ap_ST_st113_fsm_112;
end if;
when ap_ST_st114_fsm_113 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st115_fsm_114;
else
ap_NS_fsm <= ap_ST_st114_fsm_113;
end if;
when ap_ST_st115_fsm_114 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st116_fsm_115;
else
ap_NS_fsm <= ap_ST_st115_fsm_114;
end if;
when ap_ST_st116_fsm_115 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st117_fsm_116;
else
ap_NS_fsm <= ap_ST_st116_fsm_115;
end if;
when ap_ST_st117_fsm_116 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st118_fsm_117;
else
ap_NS_fsm <= ap_ST_st117_fsm_116;
end if;
when ap_ST_st118_fsm_117 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st119_fsm_118;
else
ap_NS_fsm <= ap_ST_st118_fsm_117;
end if;
when ap_ST_st119_fsm_118 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st120_fsm_119;
else
ap_NS_fsm <= ap_ST_st119_fsm_118;
end if;
when ap_ST_st120_fsm_119 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st121_fsm_120;
else
ap_NS_fsm <= ap_ST_st120_fsm_119;
end if;
when ap_ST_st121_fsm_120 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st122_fsm_121;
else
ap_NS_fsm <= ap_ST_st121_fsm_120;
end if;
when ap_ST_st122_fsm_121 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st123_fsm_122;
else
ap_NS_fsm <= ap_ST_st122_fsm_121;
end if;
when ap_ST_st123_fsm_122 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st124_fsm_123;
else
ap_NS_fsm <= ap_ST_st123_fsm_122;
end if;
when ap_ST_st124_fsm_123 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st125_fsm_124;
else
ap_NS_fsm <= ap_ST_st124_fsm_123;
end if;
when ap_ST_st125_fsm_124 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st126_fsm_125;
else
ap_NS_fsm <= ap_ST_st125_fsm_124;
end if;
when ap_ST_st126_fsm_125 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st127_fsm_126;
else
ap_NS_fsm <= ap_ST_st126_fsm_125;
end if;
when ap_ST_st127_fsm_126 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st128_fsm_127;
else
ap_NS_fsm <= ap_ST_st127_fsm_126;
end if;
when ap_ST_st128_fsm_127 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st129_fsm_128;
else
ap_NS_fsm <= ap_ST_st128_fsm_127;
end if;
when ap_ST_st129_fsm_128 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st130_fsm_129;
else
ap_NS_fsm <= ap_ST_st129_fsm_128;
end if;
when ap_ST_st130_fsm_129 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st131_fsm_130;
else
ap_NS_fsm <= ap_ST_st130_fsm_129;
end if;
when ap_ST_st131_fsm_130 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st132_fsm_131;
else
ap_NS_fsm <= ap_ST_st131_fsm_130;
end if;
when ap_ST_st132_fsm_131 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st133_fsm_132;
else
ap_NS_fsm <= ap_ST_st132_fsm_131;
end if;
when ap_ST_st133_fsm_132 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st134_fsm_133;
else
ap_NS_fsm <= ap_ST_st133_fsm_132;
end if;
when ap_ST_st134_fsm_133 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st135_fsm_134;
else
ap_NS_fsm <= ap_ST_st134_fsm_133;
end if;
when ap_ST_st135_fsm_134 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st136_fsm_135;
else
ap_NS_fsm <= ap_ST_st135_fsm_134;
end if;
when ap_ST_st136_fsm_135 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st137_fsm_136;
else
ap_NS_fsm <= ap_ST_st136_fsm_135;
end if;
when ap_ST_st137_fsm_136 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st138_fsm_137;
else
ap_NS_fsm <= ap_ST_st137_fsm_136;
end if;
when ap_ST_st138_fsm_137 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st139_fsm_138;
else
ap_NS_fsm <= ap_ST_st138_fsm_137;
end if;
when ap_ST_st139_fsm_138 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st140_fsm_139;
else
ap_NS_fsm <= ap_ST_st139_fsm_138;
end if;
when ap_ST_st140_fsm_139 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st141_fsm_140;
else
ap_NS_fsm <= ap_ST_st140_fsm_139;
end if;
when ap_ST_st141_fsm_140 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st142_fsm_141;
else
ap_NS_fsm <= ap_ST_st141_fsm_140;
end if;
when ap_ST_st142_fsm_141 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st143_fsm_142;
else
ap_NS_fsm <= ap_ST_st142_fsm_141;
end if;
when ap_ST_st143_fsm_142 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st144_fsm_143;
else
ap_NS_fsm <= ap_ST_st143_fsm_142;
end if;
when ap_ST_st144_fsm_143 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st145_fsm_144;
else
ap_NS_fsm <= ap_ST_st144_fsm_143;
end if;
when ap_ST_st145_fsm_144 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st146_fsm_145;
else
ap_NS_fsm <= ap_ST_st145_fsm_144;
end if;
when ap_ST_st146_fsm_145 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st147_fsm_146;
else
ap_NS_fsm <= ap_ST_st146_fsm_145;
end if;
when ap_ST_st147_fsm_146 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
else
ap_NS_fsm <= ap_ST_st147_fsm_146;
end if;
when ap_ST_st148_fsm_147 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st149_fsm_148;
else
ap_NS_fsm <= ap_ST_st148_fsm_147;
end if;
when ap_ST_st149_fsm_148 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
else
ap_NS_fsm <= ap_ST_st149_fsm_148;
end if;
when ap_ST_st150_fsm_149 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st151_fsm_150;
else
ap_NS_fsm <= ap_ST_st150_fsm_149;
end if;
when ap_ST_st151_fsm_150 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st152_fsm_151;
else
ap_NS_fsm <= ap_ST_st151_fsm_150;
end if;
when ap_ST_st152_fsm_151 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st153_fsm_152;
else
ap_NS_fsm <= ap_ST_st152_fsm_151;
end if;
when ap_ST_st153_fsm_152 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st154_fsm_153;
else
ap_NS_fsm <= ap_ST_st153_fsm_152;
end if;
when ap_ST_st154_fsm_153 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st155_fsm_154;
else
ap_NS_fsm <= ap_ST_st154_fsm_153;
end if;
when ap_ST_st155_fsm_154 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st156_fsm_155;
else
ap_NS_fsm <= ap_ST_st155_fsm_154;
end if;
when ap_ST_st156_fsm_155 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st157_fsm_156;
else
ap_NS_fsm <= ap_ST_st156_fsm_155;
end if;
when ap_ST_st157_fsm_156 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st158_fsm_157;
else
ap_NS_fsm <= ap_ST_st157_fsm_156;
end if;
when ap_ST_st158_fsm_157 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st159_fsm_158;
else
ap_NS_fsm <= ap_ST_st158_fsm_157;
end if;
when ap_ST_st159_fsm_158 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st160_fsm_159;
else
ap_NS_fsm <= ap_ST_st159_fsm_158;
end if;
when ap_ST_st160_fsm_159 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st161_fsm_160;
else
ap_NS_fsm <= ap_ST_st160_fsm_159;
end if;
when ap_ST_st161_fsm_160 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st162_fsm_161;
else
ap_NS_fsm <= ap_ST_st161_fsm_160;
end if;
when ap_ST_st162_fsm_161 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st163_fsm_162;
else
ap_NS_fsm <= ap_ST_st162_fsm_161;
end if;
when ap_ST_st163_fsm_162 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st164_fsm_163;
else
ap_NS_fsm <= ap_ST_st163_fsm_162;
end if;
when ap_ST_st164_fsm_163 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st165_fsm_164;
else
ap_NS_fsm <= ap_ST_st164_fsm_163;
end if;
when ap_ST_st165_fsm_164 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st166_fsm_165;
else
ap_NS_fsm <= ap_ST_st165_fsm_164;
end if;
when ap_ST_st166_fsm_165 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st167_fsm_166;
else
ap_NS_fsm <= ap_ST_st166_fsm_165;
end if;
when ap_ST_st167_fsm_166 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st168_fsm_167;
else
ap_NS_fsm <= ap_ST_st167_fsm_166;
end if;
when ap_ST_st168_fsm_167 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st169_fsm_168;
else
ap_NS_fsm <= ap_ST_st168_fsm_167;
end if;
when ap_ST_st169_fsm_168 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st170_fsm_169;
else
ap_NS_fsm <= ap_ST_st169_fsm_168;
end if;
when ap_ST_st170_fsm_169 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st171_fsm_170;
else
ap_NS_fsm <= ap_ST_st170_fsm_169;
end if;
when ap_ST_st171_fsm_170 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st172_fsm_171;
else
ap_NS_fsm <= ap_ST_st171_fsm_170;
end if;
when ap_ST_st172_fsm_171 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st173_fsm_172;
else
ap_NS_fsm <= ap_ST_st172_fsm_171;
end if;
when ap_ST_st173_fsm_172 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st174_fsm_173;
else
ap_NS_fsm <= ap_ST_st173_fsm_172;
end if;
when ap_ST_st174_fsm_173 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st175_fsm_174;
else
ap_NS_fsm <= ap_ST_st174_fsm_173;
end if;
when ap_ST_st175_fsm_174 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st176_fsm_175;
else
ap_NS_fsm <= ap_ST_st175_fsm_174;
end if;
when ap_ST_st176_fsm_175 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st177_fsm_176;
else
ap_NS_fsm <= ap_ST_st176_fsm_175;
end if;
when ap_ST_st177_fsm_176 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st178_fsm_177;
else
ap_NS_fsm <= ap_ST_st177_fsm_176;
end if;
when ap_ST_st178_fsm_177 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st179_fsm_178;
else
ap_NS_fsm <= ap_ST_st178_fsm_177;
end if;
when ap_ST_st179_fsm_178 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st180_fsm_179;
else
ap_NS_fsm <= ap_ST_st179_fsm_178;
end if;
when ap_ST_st180_fsm_179 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st181_fsm_180;
else
ap_NS_fsm <= ap_ST_st180_fsm_179;
end if;
when ap_ST_st181_fsm_180 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st182_fsm_181;
else
ap_NS_fsm <= ap_ST_st181_fsm_180;
end if;
when ap_ST_st182_fsm_181 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st183_fsm_182;
else
ap_NS_fsm <= ap_ST_st182_fsm_181;
end if;
when ap_ST_st183_fsm_182 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st184_fsm_183;
else
ap_NS_fsm <= ap_ST_st183_fsm_182;
end if;
when ap_ST_st184_fsm_183 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st185_fsm_184;
else
ap_NS_fsm <= ap_ST_st184_fsm_183;
end if;
when ap_ST_st185_fsm_184 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st186_fsm_185;
else
ap_NS_fsm <= ap_ST_st185_fsm_184;
end if;
when ap_ST_st186_fsm_185 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st187_fsm_186;
else
ap_NS_fsm <= ap_ST_st186_fsm_185;
end if;
when ap_ST_st187_fsm_186 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st188_fsm_187;
else
ap_NS_fsm <= ap_ST_st187_fsm_186;
end if;
when ap_ST_st188_fsm_187 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st189_fsm_188;
else
ap_NS_fsm <= ap_ST_st188_fsm_187;
end if;
when ap_ST_st189_fsm_188 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st190_fsm_189;
else
ap_NS_fsm <= ap_ST_st189_fsm_188;
end if;
when ap_ST_st190_fsm_189 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st191_fsm_190;
else
ap_NS_fsm <= ap_ST_st190_fsm_189;
end if;
when ap_ST_st191_fsm_190 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st192_fsm_191;
else
ap_NS_fsm <= ap_ST_st191_fsm_190;
end if;
when ap_ST_st192_fsm_191 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st193_fsm_192;
else
ap_NS_fsm <= ap_ST_st192_fsm_191;
end if;
when ap_ST_st193_fsm_192 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st194_fsm_193;
else
ap_NS_fsm <= ap_ST_st193_fsm_192;
end if;
when ap_ST_st194_fsm_193 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st195_fsm_194;
else
ap_NS_fsm <= ap_ST_st194_fsm_193;
end if;
when ap_ST_st195_fsm_194 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st196_fsm_195;
else
ap_NS_fsm <= ap_ST_st195_fsm_194;
end if;
when ap_ST_st196_fsm_195 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st197_fsm_196;
else
ap_NS_fsm <= ap_ST_st196_fsm_195;
end if;
when ap_ST_st197_fsm_196 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st198_fsm_197;
else
ap_NS_fsm <= ap_ST_st197_fsm_196;
end if;
when ap_ST_st198_fsm_197 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st199_fsm_198;
else
ap_NS_fsm <= ap_ST_st198_fsm_197;
end if;
when ap_ST_st199_fsm_198 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st200_fsm_199;
else
ap_NS_fsm <= ap_ST_st199_fsm_198;
end if;
when ap_ST_st200_fsm_199 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st201_fsm_200;
else
ap_NS_fsm <= ap_ST_st200_fsm_199;
end if;
when ap_ST_st201_fsm_200 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st202_fsm_201;
else
ap_NS_fsm <= ap_ST_st201_fsm_200;
end if;
when ap_ST_st202_fsm_201 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st203_fsm_202;
else
ap_NS_fsm <= ap_ST_st202_fsm_201;
end if;
when ap_ST_st203_fsm_202 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st204_fsm_203;
else
ap_NS_fsm <= ap_ST_st203_fsm_202;
end if;
when ap_ST_st204_fsm_203 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st205_fsm_204;
else
ap_NS_fsm <= ap_ST_st204_fsm_203;
end if;
when ap_ST_st205_fsm_204 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st206_fsm_205;
else
ap_NS_fsm <= ap_ST_st205_fsm_204;
end if;
when ap_ST_st206_fsm_205 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st207_fsm_206;
else
ap_NS_fsm <= ap_ST_st206_fsm_205;
end if;
when ap_ST_st207_fsm_206 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st208_fsm_207;
else
ap_NS_fsm <= ap_ST_st207_fsm_206;
end if;
when ap_ST_st208_fsm_207 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st209_fsm_208;
else
ap_NS_fsm <= ap_ST_st208_fsm_207;
end if;
when ap_ST_st209_fsm_208 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st210_fsm_209;
else
ap_NS_fsm <= ap_ST_st209_fsm_208;
end if;
when ap_ST_st210_fsm_209 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st211_fsm_210;
else
ap_NS_fsm <= ap_ST_st210_fsm_209;
end if;
when ap_ST_st211_fsm_210 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st212_fsm_211;
else
ap_NS_fsm <= ap_ST_st211_fsm_210;
end if;
when ap_ST_st212_fsm_211 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st213_fsm_212;
else
ap_NS_fsm <= ap_ST_st212_fsm_211;
end if;
when ap_ST_st213_fsm_212 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st214_fsm_213;
else
ap_NS_fsm <= ap_ST_st213_fsm_212;
end if;
when ap_ST_st214_fsm_213 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st215_fsm_214;
else
ap_NS_fsm <= ap_ST_st214_fsm_213;
end if;
when ap_ST_st215_fsm_214 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st216_fsm_215;
else
ap_NS_fsm <= ap_ST_st215_fsm_214;
end if;
when ap_ST_st216_fsm_215 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st217_fsm_216;
else
ap_NS_fsm <= ap_ST_st216_fsm_215;
end if;
when ap_ST_st217_fsm_216 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st218_fsm_217;
else
ap_NS_fsm <= ap_ST_st217_fsm_216;
end if;
when ap_ST_st218_fsm_217 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st219_fsm_218;
else
ap_NS_fsm <= ap_ST_st218_fsm_217;
end if;
when ap_ST_st219_fsm_218 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st220_fsm_219;
else
ap_NS_fsm <= ap_ST_st219_fsm_218;
end if;
when ap_ST_st220_fsm_219 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st221_fsm_220;
else
ap_NS_fsm <= ap_ST_st220_fsm_219;
end if;
when ap_ST_st221_fsm_220 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st222_fsm_221;
else
ap_NS_fsm <= ap_ST_st221_fsm_220;
end if;
when ap_ST_st222_fsm_221 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st223_fsm_222;
else
ap_NS_fsm <= ap_ST_st222_fsm_221;
end if;
when ap_ST_st223_fsm_222 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st224_fsm_223;
else
ap_NS_fsm <= ap_ST_st223_fsm_222;
end if;
when ap_ST_st224_fsm_223 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st225_fsm_224;
else
ap_NS_fsm <= ap_ST_st224_fsm_223;
end if;
when ap_ST_st225_fsm_224 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st226_fsm_225;
else
ap_NS_fsm <= ap_ST_st225_fsm_224;
end if;
when ap_ST_st226_fsm_225 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st227_fsm_226;
else
ap_NS_fsm <= ap_ST_st226_fsm_225;
end if;
when ap_ST_st227_fsm_226 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st228_fsm_227;
else
ap_NS_fsm <= ap_ST_st227_fsm_226;
end if;
when ap_ST_st228_fsm_227 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st229_fsm_228;
else
ap_NS_fsm <= ap_ST_st228_fsm_227;
end if;
when ap_ST_st229_fsm_228 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st230_fsm_229;
else
ap_NS_fsm <= ap_ST_st229_fsm_228;
end if;
when ap_ST_st230_fsm_229 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st231_fsm_230;
else
ap_NS_fsm <= ap_ST_st230_fsm_229;
end if;
when ap_ST_st231_fsm_230 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st232_fsm_231;
else
ap_NS_fsm <= ap_ST_st231_fsm_230;
end if;
when ap_ST_st232_fsm_231 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st233_fsm_232;
else
ap_NS_fsm <= ap_ST_st232_fsm_231;
end if;
when ap_ST_st233_fsm_232 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st234_fsm_233;
else
ap_NS_fsm <= ap_ST_st233_fsm_232;
end if;
when ap_ST_st234_fsm_233 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st235_fsm_234;
else
ap_NS_fsm <= ap_ST_st234_fsm_233;
end if;
when ap_ST_st235_fsm_234 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st236_fsm_235;
else
ap_NS_fsm <= ap_ST_st235_fsm_234;
end if;
when ap_ST_st236_fsm_235 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st237_fsm_236;
else
ap_NS_fsm <= ap_ST_st236_fsm_235;
end if;
when ap_ST_st237_fsm_236 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st238_fsm_237;
else
ap_NS_fsm <= ap_ST_st237_fsm_236;
end if;
when ap_ST_st238_fsm_237 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st239_fsm_238;
else
ap_NS_fsm <= ap_ST_st238_fsm_237;
end if;
when ap_ST_st239_fsm_238 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st240_fsm_239;
else
ap_NS_fsm <= ap_ST_st239_fsm_238;
end if;
when ap_ST_st240_fsm_239 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st241_fsm_240;
else
ap_NS_fsm <= ap_ST_st240_fsm_239;
end if;
when ap_ST_st241_fsm_240 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st242_fsm_241;
else
ap_NS_fsm <= ap_ST_st241_fsm_240;
end if;
when ap_ST_st242_fsm_241 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st243_fsm_242;
else
ap_NS_fsm <= ap_ST_st242_fsm_241;
end if;
when ap_ST_st243_fsm_242 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st244_fsm_243;
else
ap_NS_fsm <= ap_ST_st243_fsm_242;
end if;
when ap_ST_st244_fsm_243 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st245_fsm_244;
else
ap_NS_fsm <= ap_ST_st244_fsm_243;
end if;
when ap_ST_st245_fsm_244 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st246_fsm_245;
else
ap_NS_fsm <= ap_ST_st245_fsm_244;
end if;
when ap_ST_st246_fsm_245 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st247_fsm_246;
else
ap_NS_fsm <= ap_ST_st246_fsm_245;
end if;
when ap_ST_st247_fsm_246 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st248_fsm_247;
else
ap_NS_fsm <= ap_ST_st247_fsm_246;
end if;
when ap_ST_st248_fsm_247 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st249_fsm_248;
else
ap_NS_fsm <= ap_ST_st248_fsm_247;
end if;
when ap_ST_st249_fsm_248 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st250_fsm_249;
else
ap_NS_fsm <= ap_ST_st249_fsm_248;
end if;
when ap_ST_st250_fsm_249 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st251_fsm_250;
else
ap_NS_fsm <= ap_ST_st250_fsm_249;
end if;
when ap_ST_st251_fsm_250 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st252_fsm_251;
else
ap_NS_fsm <= ap_ST_st251_fsm_250;
end if;
when ap_ST_st252_fsm_251 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st253_fsm_252;
else
ap_NS_fsm <= ap_ST_st252_fsm_251;
end if;
when ap_ST_st253_fsm_252 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st254_fsm_253;
else
ap_NS_fsm <= ap_ST_st253_fsm_252;
end if;
when ap_ST_st254_fsm_253 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st255_fsm_254;
else
ap_NS_fsm <= ap_ST_st254_fsm_253;
end if;
when ap_ST_st255_fsm_254 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st256_fsm_255;
else
ap_NS_fsm <= ap_ST_st255_fsm_254;
end if;
when ap_ST_st256_fsm_255 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st257_fsm_256;
else
ap_NS_fsm <= ap_ST_st256_fsm_255;
end if;
when ap_ST_st257_fsm_256 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st258_fsm_257;
else
ap_NS_fsm <= ap_ST_st257_fsm_256;
end if;
when ap_ST_st258_fsm_257 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st259_fsm_258;
else
ap_NS_fsm <= ap_ST_st258_fsm_257;
end if;
when ap_ST_st259_fsm_258 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st260_fsm_259;
else
ap_NS_fsm <= ap_ST_st259_fsm_258;
end if;
when ap_ST_st260_fsm_259 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st261_fsm_260;
else
ap_NS_fsm <= ap_ST_st260_fsm_259;
end if;
when ap_ST_st261_fsm_260 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st262_fsm_261;
else
ap_NS_fsm <= ap_ST_st261_fsm_260;
end if;
when ap_ST_st262_fsm_261 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st263_fsm_262;
else
ap_NS_fsm <= ap_ST_st262_fsm_261;
end if;
when ap_ST_st263_fsm_262 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st264_fsm_263;
else
ap_NS_fsm <= ap_ST_st263_fsm_262;
end if;
when ap_ST_st264_fsm_263 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st265_fsm_264;
else
ap_NS_fsm <= ap_ST_st264_fsm_263;
end if;
when ap_ST_st265_fsm_264 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st266_fsm_265;
else
ap_NS_fsm <= ap_ST_st265_fsm_264;
end if;
when ap_ST_st266_fsm_265 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st267_fsm_266;
else
ap_NS_fsm <= ap_ST_st266_fsm_265;
end if;
when ap_ST_st267_fsm_266 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st268_fsm_267;
else
ap_NS_fsm <= ap_ST_st267_fsm_266;
end if;
when ap_ST_st268_fsm_267 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st269_fsm_268;
else
ap_NS_fsm <= ap_ST_st268_fsm_267;
end if;
when ap_ST_st269_fsm_268 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st270_fsm_269;
else
ap_NS_fsm <= ap_ST_st269_fsm_268;
end if;
when ap_ST_st270_fsm_269 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st271_fsm_270;
else
ap_NS_fsm <= ap_ST_st270_fsm_269;
end if;
when ap_ST_st271_fsm_270 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st272_fsm_271;
else
ap_NS_fsm <= ap_ST_st271_fsm_270;
end if;
when ap_ST_st272_fsm_271 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st273_fsm_272;
else
ap_NS_fsm <= ap_ST_st272_fsm_271;
end if;
when ap_ST_st273_fsm_272 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st274_fsm_273;
else
ap_NS_fsm <= ap_ST_st273_fsm_272;
end if;
when ap_ST_st274_fsm_273 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st275_fsm_274;
else
ap_NS_fsm <= ap_ST_st274_fsm_273;
end if;
when ap_ST_st275_fsm_274 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st276_fsm_275;
else
ap_NS_fsm <= ap_ST_st275_fsm_274;
end if;
when ap_ST_st276_fsm_275 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st277_fsm_276;
else
ap_NS_fsm <= ap_ST_st276_fsm_275;
end if;
when ap_ST_st277_fsm_276 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st278_fsm_277;
else
ap_NS_fsm <= ap_ST_st277_fsm_276;
end if;
when ap_ST_st278_fsm_277 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st279_fsm_278;
else
ap_NS_fsm <= ap_ST_st278_fsm_277;
end if;
when ap_ST_st279_fsm_278 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st280_fsm_279;
else
ap_NS_fsm <= ap_ST_st279_fsm_278;
end if;
when ap_ST_st280_fsm_279 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st281_fsm_280;
else
ap_NS_fsm <= ap_ST_st280_fsm_279;
end if;
when ap_ST_st281_fsm_280 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st282_fsm_281;
else
ap_NS_fsm <= ap_ST_st281_fsm_280;
end if;
when ap_ST_st282_fsm_281 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st283_fsm_282;
else
ap_NS_fsm <= ap_ST_st282_fsm_281;
end if;
when ap_ST_st283_fsm_282 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st284_fsm_283;
else
ap_NS_fsm <= ap_ST_st283_fsm_282;
end if;
when ap_ST_st284_fsm_283 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st285_fsm_284;
else
ap_NS_fsm <= ap_ST_st284_fsm_283;
end if;
when ap_ST_st285_fsm_284 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st286_fsm_285;
else
ap_NS_fsm <= ap_ST_st285_fsm_284;
end if;
when ap_ST_st286_fsm_285 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st287_fsm_286;
else
ap_NS_fsm <= ap_ST_st286_fsm_285;
end if;
when ap_ST_st287_fsm_286 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st288_fsm_287;
else
ap_NS_fsm <= ap_ST_st287_fsm_286;
end if;
when ap_ST_st288_fsm_287 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st289_fsm_288;
else
ap_NS_fsm <= ap_ST_st288_fsm_287;
end if;
when ap_ST_st289_fsm_288 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st290_fsm_289;
else
ap_NS_fsm <= ap_ST_st289_fsm_288;
end if;
when ap_ST_st290_fsm_289 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st291_fsm_290;
else
ap_NS_fsm <= ap_ST_st290_fsm_289;
end if;
when ap_ST_st291_fsm_290 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st292_fsm_291;
else
ap_NS_fsm <= ap_ST_st291_fsm_290;
end if;
when ap_ST_st292_fsm_291 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st293_fsm_292;
else
ap_NS_fsm <= ap_ST_st292_fsm_291;
end if;
when ap_ST_st293_fsm_292 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st294_fsm_293;
else
ap_NS_fsm <= ap_ST_st293_fsm_292;
end if;
when ap_ST_st294_fsm_293 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st295_fsm_294;
else
ap_NS_fsm <= ap_ST_st294_fsm_293;
end if;
when ap_ST_st295_fsm_294 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st296_fsm_295;
else
ap_NS_fsm <= ap_ST_st295_fsm_294;
end if;
when ap_ST_st296_fsm_295 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st297_fsm_296;
else
ap_NS_fsm <= ap_ST_st296_fsm_295;
end if;
when ap_ST_st297_fsm_296 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st298_fsm_297;
else
ap_NS_fsm <= ap_ST_st297_fsm_296;
end if;
when ap_ST_st298_fsm_297 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st299_fsm_298;
else
ap_NS_fsm <= ap_ST_st298_fsm_297;
end if;
when ap_ST_st299_fsm_298 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st300_fsm_299;
else
ap_NS_fsm <= ap_ST_st299_fsm_298;
end if;
when ap_ST_st300_fsm_299 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_300;
else
ap_NS_fsm <= ap_ST_st300_fsm_299;
end if;
when ap_ST_pp0_stg0_fsm_300 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it82)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond2_fu_2840_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_300;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond2_fu_2840_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) then
ap_NS_fsm <= ap_ST_st385_fsm_301;
else
ap_NS_fsm <= ap_ST_st385_fsm_301;
end if;
when ap_ST_st385_fsm_301 =>
ap_NS_fsm <= ap_ST_st386_fsm_302;
when ap_ST_st386_fsm_302 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st387_fsm_303;
else
ap_NS_fsm <= ap_ST_st386_fsm_302;
end if;
when ap_ST_st387_fsm_303 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st388_fsm_304;
else
ap_NS_fsm <= ap_ST_st387_fsm_303;
end if;
when ap_ST_st388_fsm_304 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st389_fsm_305;
else
ap_NS_fsm <= ap_ST_st388_fsm_304;
end if;
when ap_ST_st389_fsm_305 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st390_fsm_306;
else
ap_NS_fsm <= ap_ST_st389_fsm_305;
end if;
when ap_ST_st390_fsm_306 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st391_fsm_307;
else
ap_NS_fsm <= ap_ST_st390_fsm_306;
end if;
when ap_ST_st391_fsm_307 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st392_fsm_308;
else
ap_NS_fsm <= ap_ST_st391_fsm_307;
end if;
when ap_ST_st392_fsm_308 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st393_fsm_309;
else
ap_NS_fsm <= ap_ST_st392_fsm_308;
end if;
when ap_ST_st393_fsm_309 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st394_fsm_310;
else
ap_NS_fsm <= ap_ST_st393_fsm_309;
end if;
when ap_ST_st394_fsm_310 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st395_fsm_311;
else
ap_NS_fsm <= ap_ST_st394_fsm_310;
end if;
when ap_ST_st395_fsm_311 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st396_fsm_312;
else
ap_NS_fsm <= ap_ST_st395_fsm_311;
end if;
when ap_ST_st396_fsm_312 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st397_fsm_313;
else
ap_NS_fsm <= ap_ST_st396_fsm_312;
end if;
when ap_ST_st397_fsm_313 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st398_fsm_314;
else
ap_NS_fsm <= ap_ST_st397_fsm_313;
end if;
when ap_ST_st398_fsm_314 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st399_fsm_315;
else
ap_NS_fsm <= ap_ST_st398_fsm_314;
end if;
when ap_ST_st399_fsm_315 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st400_fsm_316;
else
ap_NS_fsm <= ap_ST_st399_fsm_315;
end if;
when ap_ST_st400_fsm_316 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st401_fsm_317;
else
ap_NS_fsm <= ap_ST_st400_fsm_316;
end if;
when ap_ST_st401_fsm_317 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st402_fsm_318;
else
ap_NS_fsm <= ap_ST_st401_fsm_317;
end if;
when ap_ST_st402_fsm_318 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st403_fsm_319;
else
ap_NS_fsm <= ap_ST_st402_fsm_318;
end if;
when ap_ST_st403_fsm_319 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st404_fsm_320;
else
ap_NS_fsm <= ap_ST_st403_fsm_319;
end if;
when ap_ST_st404_fsm_320 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st405_fsm_321;
else
ap_NS_fsm <= ap_ST_st404_fsm_320;
end if;
when ap_ST_st405_fsm_321 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st406_fsm_322;
else
ap_NS_fsm <= ap_ST_st405_fsm_321;
end if;
when ap_ST_st406_fsm_322 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st407_fsm_323;
else
ap_NS_fsm <= ap_ST_st406_fsm_322;
end if;
when ap_ST_st407_fsm_323 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st408_fsm_324;
else
ap_NS_fsm <= ap_ST_st407_fsm_323;
end if;
when ap_ST_st408_fsm_324 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st409_fsm_325;
else
ap_NS_fsm <= ap_ST_st408_fsm_324;
end if;
when ap_ST_st409_fsm_325 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st410_fsm_326;
else
ap_NS_fsm <= ap_ST_st409_fsm_325;
end if;
when ap_ST_st410_fsm_326 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st411_fsm_327;
else
ap_NS_fsm <= ap_ST_st410_fsm_326;
end if;
when ap_ST_st411_fsm_327 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st412_fsm_328;
else
ap_NS_fsm <= ap_ST_st411_fsm_327;
end if;
when ap_ST_st412_fsm_328 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st413_fsm_329;
else
ap_NS_fsm <= ap_ST_st412_fsm_328;
end if;
when ap_ST_st413_fsm_329 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st414_fsm_330;
else
ap_NS_fsm <= ap_ST_st413_fsm_329;
end if;
when ap_ST_st414_fsm_330 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st415_fsm_331;
else
ap_NS_fsm <= ap_ST_st414_fsm_330;
end if;
when ap_ST_st415_fsm_331 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st416_fsm_332;
else
ap_NS_fsm <= ap_ST_st415_fsm_331;
end if;
when ap_ST_st416_fsm_332 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st417_fsm_333;
else
ap_NS_fsm <= ap_ST_st416_fsm_332;
end if;
when ap_ST_st417_fsm_333 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st418_fsm_334;
else
ap_NS_fsm <= ap_ST_st417_fsm_333;
end if;
when ap_ST_st418_fsm_334 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st419_fsm_335;
else
ap_NS_fsm <= ap_ST_st418_fsm_334;
end if;
when ap_ST_st419_fsm_335 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st420_fsm_336;
else
ap_NS_fsm <= ap_ST_st419_fsm_335;
end if;
when ap_ST_st420_fsm_336 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st421_fsm_337;
else
ap_NS_fsm <= ap_ST_st420_fsm_336;
end if;
when ap_ST_st421_fsm_337 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st422_fsm_338;
else
ap_NS_fsm <= ap_ST_st421_fsm_337;
end if;
when ap_ST_st422_fsm_338 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st423_fsm_339;
else
ap_NS_fsm <= ap_ST_st422_fsm_338;
end if;
when ap_ST_st423_fsm_339 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st424_fsm_340;
else
ap_NS_fsm <= ap_ST_st423_fsm_339;
end if;
when ap_ST_st424_fsm_340 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st425_fsm_341;
else
ap_NS_fsm <= ap_ST_st424_fsm_340;
end if;
when ap_ST_st425_fsm_341 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st426_fsm_342;
else
ap_NS_fsm <= ap_ST_st425_fsm_341;
end if;
when ap_ST_st426_fsm_342 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st427_fsm_343;
else
ap_NS_fsm <= ap_ST_st426_fsm_342;
end if;
when ap_ST_st427_fsm_343 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st428_fsm_344;
else
ap_NS_fsm <= ap_ST_st427_fsm_343;
end if;
when ap_ST_st428_fsm_344 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st429_fsm_345;
else
ap_NS_fsm <= ap_ST_st428_fsm_344;
end if;
when ap_ST_st429_fsm_345 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st430_fsm_346;
else
ap_NS_fsm <= ap_ST_st429_fsm_345;
end if;
when ap_ST_st430_fsm_346 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st431_fsm_347;
else
ap_NS_fsm <= ap_ST_st430_fsm_346;
end if;
when ap_ST_st431_fsm_347 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st432_fsm_348;
else
ap_NS_fsm <= ap_ST_st431_fsm_347;
end if;
when ap_ST_st432_fsm_348 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st433_fsm_349;
else
ap_NS_fsm <= ap_ST_st432_fsm_348;
end if;
when ap_ST_st433_fsm_349 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st434_fsm_350;
else
ap_NS_fsm <= ap_ST_st433_fsm_349;
end if;
when ap_ST_st434_fsm_350 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st435_fsm_351;
else
ap_NS_fsm <= ap_ST_st434_fsm_350;
end if;
when ap_ST_st435_fsm_351 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st436_fsm_352;
else
ap_NS_fsm <= ap_ST_st435_fsm_351;
end if;
when ap_ST_st436_fsm_352 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st437_fsm_353;
else
ap_NS_fsm <= ap_ST_st436_fsm_352;
end if;
when ap_ST_st437_fsm_353 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st438_fsm_354;
else
ap_NS_fsm <= ap_ST_st437_fsm_353;
end if;
when ap_ST_st438_fsm_354 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st439_fsm_355;
else
ap_NS_fsm <= ap_ST_st438_fsm_354;
end if;
when ap_ST_st439_fsm_355 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st440_fsm_356;
else
ap_NS_fsm <= ap_ST_st439_fsm_355;
end if;
when ap_ST_st440_fsm_356 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st441_fsm_357;
else
ap_NS_fsm <= ap_ST_st440_fsm_356;
end if;
when ap_ST_st441_fsm_357 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st442_fsm_358;
else
ap_NS_fsm <= ap_ST_st441_fsm_357;
end if;
when ap_ST_st442_fsm_358 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st443_fsm_359;
else
ap_NS_fsm <= ap_ST_st442_fsm_358;
end if;
when ap_ST_st443_fsm_359 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st444_fsm_360;
else
ap_NS_fsm <= ap_ST_st443_fsm_359;
end if;
when ap_ST_st444_fsm_360 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st445_fsm_361;
else
ap_NS_fsm <= ap_ST_st444_fsm_360;
end if;
when ap_ST_st445_fsm_361 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st445_fsm_361;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1004 assign process. --
ap_sig_bdd_1004_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1004 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_1013 assign process. --
ap_sig_bdd_1013_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1013 <= (ap_const_lv1_1 = ap_CS_fsm(94 downto 94));
end process;
-- ap_sig_bdd_1022 assign process. --
ap_sig_bdd_1022_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1022 <= (ap_const_lv1_1 = ap_CS_fsm(109 downto 109));
end process;
-- ap_sig_bdd_1031 assign process. --
ap_sig_bdd_1031_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1031 <= (ap_const_lv1_1 = ap_CS_fsm(124 downto 124));
end process;
-- ap_sig_bdd_1040 assign process. --
ap_sig_bdd_1040_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1040 <= (ap_const_lv1_1 = ap_CS_fsm(139 downto 139));
end process;
-- ap_sig_bdd_1049 assign process. --
ap_sig_bdd_1049_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1049 <= (ap_const_lv1_1 = ap_CS_fsm(154 downto 154));
end process;
-- ap_sig_bdd_1058 assign process. --
ap_sig_bdd_1058_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1058 <= (ap_const_lv1_1 = ap_CS_fsm(169 downto 169));
end process;
-- ap_sig_bdd_1067 assign process. --
ap_sig_bdd_1067_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1067 <= (ap_const_lv1_1 = ap_CS_fsm(184 downto 184));
end process;
-- ap_sig_bdd_1076 assign process. --
ap_sig_bdd_1076_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1076 <= (ap_const_lv1_1 = ap_CS_fsm(199 downto 199));
end process;
-- ap_sig_bdd_1085 assign process. --
ap_sig_bdd_1085_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1085 <= (ap_const_lv1_1 = ap_CS_fsm(214 downto 214));
end process;
-- ap_sig_bdd_1094 assign process. --
ap_sig_bdd_1094_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1094 <= (ap_const_lv1_1 = ap_CS_fsm(229 downto 229));
end process;
-- ap_sig_bdd_1103 assign process. --
ap_sig_bdd_1103_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1103 <= (ap_const_lv1_1 = ap_CS_fsm(244 downto 244));
end process;
-- ap_sig_bdd_1112 assign process. --
ap_sig_bdd_1112_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1112 <= (ap_const_lv1_1 = ap_CS_fsm(259 downto 259));
end process;
-- ap_sig_bdd_1121 assign process. --
ap_sig_bdd_1121_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1121 <= (ap_const_lv1_1 = ap_CS_fsm(274 downto 274));
end process;
-- ap_sig_bdd_1130 assign process. --
ap_sig_bdd_1130_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1130 <= (ap_const_lv1_1 = ap_CS_fsm(289 downto 289));
end process;
-- ap_sig_bdd_1140 assign process. --
ap_sig_bdd_1140_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1140 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_1148 assign process. --
ap_sig_bdd_1148_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1148 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_1157 assign process. --
ap_sig_bdd_1157_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1157 <= (ap_const_lv1_1 = ap_CS_fsm(95 downto 95));
end process;
-- ap_sig_bdd_1166 assign process. --
ap_sig_bdd_1166_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1166 <= (ap_const_lv1_1 = ap_CS_fsm(110 downto 110));
end process;
-- ap_sig_bdd_1175 assign process. --
ap_sig_bdd_1175_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1175 <= (ap_const_lv1_1 = ap_CS_fsm(125 downto 125));
end process;
-- ap_sig_bdd_1184 assign process. --
ap_sig_bdd_1184_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1184 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_1193 assign process. --
ap_sig_bdd_1193_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1193 <= (ap_const_lv1_1 = ap_CS_fsm(155 downto 155));
end process;
-- ap_sig_bdd_1202 assign process. --
ap_sig_bdd_1202_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1202 <= (ap_const_lv1_1 = ap_CS_fsm(170 downto 170));
end process;
-- ap_sig_bdd_1211 assign process. --
ap_sig_bdd_1211_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1211 <= (ap_const_lv1_1 = ap_CS_fsm(185 downto 185));
end process;
-- ap_sig_bdd_1220 assign process. --
ap_sig_bdd_1220_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1220 <= (ap_const_lv1_1 = ap_CS_fsm(200 downto 200));
end process;
-- ap_sig_bdd_1229 assign process. --
ap_sig_bdd_1229_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1229 <= (ap_const_lv1_1 = ap_CS_fsm(215 downto 215));
end process;
-- ap_sig_bdd_1238 assign process. --
ap_sig_bdd_1238_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1238 <= (ap_const_lv1_1 = ap_CS_fsm(230 downto 230));
end process;
-- ap_sig_bdd_1247 assign process. --
ap_sig_bdd_1247_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1247 <= (ap_const_lv1_1 = ap_CS_fsm(245 downto 245));
end process;
-- ap_sig_bdd_1256 assign process. --
ap_sig_bdd_1256_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1256 <= (ap_const_lv1_1 = ap_CS_fsm(260 downto 260));
end process;
-- ap_sig_bdd_1265 assign process. --
ap_sig_bdd_1265_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1265 <= (ap_const_lv1_1 = ap_CS_fsm(275 downto 275));
end process;
-- ap_sig_bdd_1274 assign process. --
ap_sig_bdd_1274_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1274 <= (ap_const_lv1_1 = ap_CS_fsm(290 downto 290));
end process;
-- ap_sig_bdd_1284 assign process. --
ap_sig_bdd_1284_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1284 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_1292 assign process. --
ap_sig_bdd_1292_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1292 <= (ap_const_lv1_1 = ap_CS_fsm(81 downto 81));
end process;
-- ap_sig_bdd_1301 assign process. --
ap_sig_bdd_1301_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1301 <= (ap_const_lv1_1 = ap_CS_fsm(96 downto 96));
end process;
-- ap_sig_bdd_1310 assign process. --
ap_sig_bdd_1310_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1310 <= (ap_const_lv1_1 = ap_CS_fsm(111 downto 111));
end process;
-- ap_sig_bdd_1319 assign process. --
ap_sig_bdd_1319_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1319 <= (ap_const_lv1_1 = ap_CS_fsm(126 downto 126));
end process;
-- ap_sig_bdd_1328 assign process. --
ap_sig_bdd_1328_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1328 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_1337 assign process. --
ap_sig_bdd_1337_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1337 <= (ap_const_lv1_1 = ap_CS_fsm(156 downto 156));
end process;
-- ap_sig_bdd_1346 assign process. --
ap_sig_bdd_1346_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1346 <= (ap_const_lv1_1 = ap_CS_fsm(171 downto 171));
end process;
-- ap_sig_bdd_1355 assign process. --
ap_sig_bdd_1355_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1355 <= (ap_const_lv1_1 = ap_CS_fsm(186 downto 186));
end process;
-- ap_sig_bdd_1364 assign process. --
ap_sig_bdd_1364_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1364 <= (ap_const_lv1_1 = ap_CS_fsm(201 downto 201));
end process;
-- ap_sig_bdd_1373 assign process. --
ap_sig_bdd_1373_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1373 <= (ap_const_lv1_1 = ap_CS_fsm(216 downto 216));
end process;
-- ap_sig_bdd_1382 assign process. --
ap_sig_bdd_1382_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1382 <= (ap_const_lv1_1 = ap_CS_fsm(231 downto 231));
end process;
-- ap_sig_bdd_1391 assign process. --
ap_sig_bdd_1391_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1391 <= (ap_const_lv1_1 = ap_CS_fsm(246 downto 246));
end process;
-- ap_sig_bdd_1400 assign process. --
ap_sig_bdd_1400_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1400 <= (ap_const_lv1_1 = ap_CS_fsm(261 downto 261));
end process;
-- ap_sig_bdd_1409 assign process. --
ap_sig_bdd_1409_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1409 <= (ap_const_lv1_1 = ap_CS_fsm(276 downto 276));
end process;
-- ap_sig_bdd_1418 assign process. --
ap_sig_bdd_1418_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1418 <= (ap_const_lv1_1 = ap_CS_fsm(291 downto 291));
end process;
-- ap_sig_bdd_1428 assign process. --
ap_sig_bdd_1428_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1428 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_1436 assign process. --
ap_sig_bdd_1436_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1436 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_1445 assign process. --
ap_sig_bdd_1445_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1445 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_1454 assign process. --
ap_sig_bdd_1454_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1454 <= (ap_const_lv1_1 = ap_CS_fsm(112 downto 112));
end process;
-- ap_sig_bdd_1463 assign process. --
ap_sig_bdd_1463_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1463 <= (ap_const_lv1_1 = ap_CS_fsm(127 downto 127));
end process;
-- ap_sig_bdd_1472 assign process. --
ap_sig_bdd_1472_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1472 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_1481 assign process. --
ap_sig_bdd_1481_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1481 <= (ap_const_lv1_1 = ap_CS_fsm(157 downto 157));
end process;
-- ap_sig_bdd_1490 assign process. --
ap_sig_bdd_1490_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1490 <= (ap_const_lv1_1 = ap_CS_fsm(172 downto 172));
end process;
-- ap_sig_bdd_1499 assign process. --
ap_sig_bdd_1499_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1499 <= (ap_const_lv1_1 = ap_CS_fsm(187 downto 187));
end process;
-- ap_sig_bdd_1508 assign process. --
ap_sig_bdd_1508_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1508 <= (ap_const_lv1_1 = ap_CS_fsm(202 downto 202));
end process;
-- ap_sig_bdd_1517 assign process. --
ap_sig_bdd_1517_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1517 <= (ap_const_lv1_1 = ap_CS_fsm(217 downto 217));
end process;
-- ap_sig_bdd_1526 assign process. --
ap_sig_bdd_1526_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1526 <= (ap_const_lv1_1 = ap_CS_fsm(232 downto 232));
end process;
-- ap_sig_bdd_1535 assign process. --
ap_sig_bdd_1535_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1535 <= (ap_const_lv1_1 = ap_CS_fsm(247 downto 247));
end process;
-- ap_sig_bdd_1544 assign process. --
ap_sig_bdd_1544_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1544 <= (ap_const_lv1_1 = ap_CS_fsm(262 downto 262));
end process;
-- ap_sig_bdd_1553 assign process. --
ap_sig_bdd_1553_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1553 <= (ap_const_lv1_1 = ap_CS_fsm(277 downto 277));
end process;
-- ap_sig_bdd_1562 assign process. --
ap_sig_bdd_1562_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1562 <= (ap_const_lv1_1 = ap_CS_fsm(292 downto 292));
end process;
-- ap_sig_bdd_1572 assign process. --
ap_sig_bdd_1572_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1572 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_1580 assign process. --
ap_sig_bdd_1580_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1580 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_1589 assign process. --
ap_sig_bdd_1589_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1589 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_bdd_1598 assign process. --
ap_sig_bdd_1598_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1598 <= (ap_const_lv1_1 = ap_CS_fsm(113 downto 113));
end process;
-- ap_sig_bdd_1607 assign process. --
ap_sig_bdd_1607_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1607 <= (ap_const_lv1_1 = ap_CS_fsm(128 downto 128));
end process;
-- ap_sig_bdd_1616 assign process. --
ap_sig_bdd_1616_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1616 <= (ap_const_lv1_1 = ap_CS_fsm(143 downto 143));
end process;
-- ap_sig_bdd_1625 assign process. --
ap_sig_bdd_1625_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1625 <= (ap_const_lv1_1 = ap_CS_fsm(158 downto 158));
end process;
-- ap_sig_bdd_1634 assign process. --
ap_sig_bdd_1634_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1634 <= (ap_const_lv1_1 = ap_CS_fsm(173 downto 173));
end process;
-- ap_sig_bdd_1643 assign process. --
ap_sig_bdd_1643_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1643 <= (ap_const_lv1_1 = ap_CS_fsm(188 downto 188));
end process;
-- ap_sig_bdd_1652 assign process. --
ap_sig_bdd_1652_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1652 <= (ap_const_lv1_1 = ap_CS_fsm(203 downto 203));
end process;
-- ap_sig_bdd_1661 assign process. --
ap_sig_bdd_1661_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1661 <= (ap_const_lv1_1 = ap_CS_fsm(218 downto 218));
end process;
-- ap_sig_bdd_1670 assign process. --
ap_sig_bdd_1670_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1670 <= (ap_const_lv1_1 = ap_CS_fsm(233 downto 233));
end process;
-- ap_sig_bdd_1679 assign process. --
ap_sig_bdd_1679_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1679 <= (ap_const_lv1_1 = ap_CS_fsm(248 downto 248));
end process;
-- ap_sig_bdd_1688 assign process. --
ap_sig_bdd_1688_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1688 <= (ap_const_lv1_1 = ap_CS_fsm(263 downto 263));
end process;
-- ap_sig_bdd_1697 assign process. --
ap_sig_bdd_1697_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1697 <= (ap_const_lv1_1 = ap_CS_fsm(278 downto 278));
end process;
-- ap_sig_bdd_1706 assign process. --
ap_sig_bdd_1706_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1706 <= (ap_const_lv1_1 = ap_CS_fsm(293 downto 293));
end process;
-- ap_sig_bdd_1716 assign process. --
ap_sig_bdd_1716_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1716 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_1724 assign process. --
ap_sig_bdd_1724_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1724 <= (ap_const_lv1_1 = ap_CS_fsm(84 downto 84));
end process;
-- ap_sig_bdd_1733 assign process. --
ap_sig_bdd_1733_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1733 <= (ap_const_lv1_1 = ap_CS_fsm(99 downto 99));
end process;
-- ap_sig_bdd_1742 assign process. --
ap_sig_bdd_1742_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1742 <= (ap_const_lv1_1 = ap_CS_fsm(114 downto 114));
end process;
-- ap_sig_bdd_1751 assign process. --
ap_sig_bdd_1751_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1751 <= (ap_const_lv1_1 = ap_CS_fsm(129 downto 129));
end process;
-- ap_sig_bdd_1760 assign process. --
ap_sig_bdd_1760_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1760 <= (ap_const_lv1_1 = ap_CS_fsm(144 downto 144));
end process;
-- ap_sig_bdd_1769 assign process. --
ap_sig_bdd_1769_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1769 <= (ap_const_lv1_1 = ap_CS_fsm(159 downto 159));
end process;
-- ap_sig_bdd_1778 assign process. --
ap_sig_bdd_1778_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1778 <= (ap_const_lv1_1 = ap_CS_fsm(174 downto 174));
end process;
-- ap_sig_bdd_1787 assign process. --
ap_sig_bdd_1787_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1787 <= (ap_const_lv1_1 = ap_CS_fsm(189 downto 189));
end process;
-- ap_sig_bdd_1796 assign process. --
ap_sig_bdd_1796_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1796 <= (ap_const_lv1_1 = ap_CS_fsm(204 downto 204));
end process;
-- ap_sig_bdd_1805 assign process. --
ap_sig_bdd_1805_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1805 <= (ap_const_lv1_1 = ap_CS_fsm(219 downto 219));
end process;
-- ap_sig_bdd_1814 assign process. --
ap_sig_bdd_1814_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1814 <= (ap_const_lv1_1 = ap_CS_fsm(234 downto 234));
end process;
-- ap_sig_bdd_1823 assign process. --
ap_sig_bdd_1823_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1823 <= (ap_const_lv1_1 = ap_CS_fsm(249 downto 249));
end process;
-- ap_sig_bdd_1832 assign process. --
ap_sig_bdd_1832_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1832 <= (ap_const_lv1_1 = ap_CS_fsm(264 downto 264));
end process;
-- ap_sig_bdd_1841 assign process. --
ap_sig_bdd_1841_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1841 <= (ap_const_lv1_1 = ap_CS_fsm(279 downto 279));
end process;
-- ap_sig_bdd_1850 assign process. --
ap_sig_bdd_1850_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1850 <= (ap_const_lv1_1 = ap_CS_fsm(294 downto 294));
end process;
-- ap_sig_bdd_1860 assign process. --
ap_sig_bdd_1860_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1860 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_1868 assign process. --
ap_sig_bdd_1868_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1868 <= (ap_const_lv1_1 = ap_CS_fsm(85 downto 85));
end process;
-- ap_sig_bdd_1877 assign process. --
ap_sig_bdd_1877_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1877 <= (ap_const_lv1_1 = ap_CS_fsm(100 downto 100));
end process;
-- ap_sig_bdd_1886 assign process. --
ap_sig_bdd_1886_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1886 <= (ap_const_lv1_1 = ap_CS_fsm(115 downto 115));
end process;
-- ap_sig_bdd_1895 assign process. --
ap_sig_bdd_1895_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1895 <= (ap_const_lv1_1 = ap_CS_fsm(130 downto 130));
end process;
-- ap_sig_bdd_1904 assign process. --
ap_sig_bdd_1904_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1904 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_1913 assign process. --
ap_sig_bdd_1913_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1913 <= (ap_const_lv1_1 = ap_CS_fsm(160 downto 160));
end process;
-- ap_sig_bdd_1922 assign process. --
ap_sig_bdd_1922_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1922 <= (ap_const_lv1_1 = ap_CS_fsm(175 downto 175));
end process;
-- ap_sig_bdd_1931 assign process. --
ap_sig_bdd_1931_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1931 <= (ap_const_lv1_1 = ap_CS_fsm(190 downto 190));
end process;
-- ap_sig_bdd_1940 assign process. --
ap_sig_bdd_1940_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1940 <= (ap_const_lv1_1 = ap_CS_fsm(205 downto 205));
end process;
-- ap_sig_bdd_1949 assign process. --
ap_sig_bdd_1949_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1949 <= (ap_const_lv1_1 = ap_CS_fsm(220 downto 220));
end process;
-- ap_sig_bdd_1958 assign process. --
ap_sig_bdd_1958_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1958 <= (ap_const_lv1_1 = ap_CS_fsm(235 downto 235));
end process;
-- ap_sig_bdd_1967 assign process. --
ap_sig_bdd_1967_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1967 <= (ap_const_lv1_1 = ap_CS_fsm(250 downto 250));
end process;
-- ap_sig_bdd_1976 assign process. --
ap_sig_bdd_1976_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1976 <= (ap_const_lv1_1 = ap_CS_fsm(265 downto 265));
end process;
-- ap_sig_bdd_1985 assign process. --
ap_sig_bdd_1985_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1985 <= (ap_const_lv1_1 = ap_CS_fsm(280 downto 280));
end process;
-- ap_sig_bdd_1994 assign process. --
ap_sig_bdd_1994_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1994 <= (ap_const_lv1_1 = ap_CS_fsm(295 downto 295));
end process;
-- ap_sig_bdd_2004 assign process. --
ap_sig_bdd_2004_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2004 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_2012 assign process. --
ap_sig_bdd_2012_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2012 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_2021 assign process. --
ap_sig_bdd_2021_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2021 <= (ap_const_lv1_1 = ap_CS_fsm(101 downto 101));
end process;
-- ap_sig_bdd_2030 assign process. --
ap_sig_bdd_2030_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2030 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_2039 assign process. --
ap_sig_bdd_2039_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2039 <= (ap_const_lv1_1 = ap_CS_fsm(131 downto 131));
end process;
-- ap_sig_bdd_2048 assign process. --
ap_sig_bdd_2048_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2048 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_2057 assign process. --
ap_sig_bdd_2057_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2057 <= (ap_const_lv1_1 = ap_CS_fsm(161 downto 161));
end process;
-- ap_sig_bdd_2066 assign process. --
ap_sig_bdd_2066_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2066 <= (ap_const_lv1_1 = ap_CS_fsm(176 downto 176));
end process;
-- ap_sig_bdd_2075 assign process. --
ap_sig_bdd_2075_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2075 <= (ap_const_lv1_1 = ap_CS_fsm(191 downto 191));
end process;
-- ap_sig_bdd_2084 assign process. --
ap_sig_bdd_2084_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2084 <= (ap_const_lv1_1 = ap_CS_fsm(206 downto 206));
end process;
-- ap_sig_bdd_2093 assign process. --
ap_sig_bdd_2093_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2093 <= (ap_const_lv1_1 = ap_CS_fsm(221 downto 221));
end process;
-- ap_sig_bdd_2102 assign process. --
ap_sig_bdd_2102_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2102 <= (ap_const_lv1_1 = ap_CS_fsm(236 downto 236));
end process;
-- ap_sig_bdd_2111 assign process. --
ap_sig_bdd_2111_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2111 <= (ap_const_lv1_1 = ap_CS_fsm(251 downto 251));
end process;
-- ap_sig_bdd_2120 assign process. --
ap_sig_bdd_2120_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2120 <= (ap_const_lv1_1 = ap_CS_fsm(266 downto 266));
end process;
-- ap_sig_bdd_2129 assign process. --
ap_sig_bdd_2129_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2129 <= (ap_const_lv1_1 = ap_CS_fsm(281 downto 281));
end process;
-- ap_sig_bdd_2138 assign process. --
ap_sig_bdd_2138_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2138 <= (ap_const_lv1_1 = ap_CS_fsm(296 downto 296));
end process;
-- ap_sig_bdd_2148 assign process. --
ap_sig_bdd_2148_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2148 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_2156 assign process. --
ap_sig_bdd_2156_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2156 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_2165 assign process. --
ap_sig_bdd_2165_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2165 <= (ap_const_lv1_1 = ap_CS_fsm(102 downto 102));
end process;
-- ap_sig_bdd_2174 assign process. --
ap_sig_bdd_2174_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2174 <= (ap_const_lv1_1 = ap_CS_fsm(117 downto 117));
end process;
-- ap_sig_bdd_2183 assign process. --
ap_sig_bdd_2183_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2183 <= (ap_const_lv1_1 = ap_CS_fsm(132 downto 132));
end process;
-- ap_sig_bdd_2192 assign process. --
ap_sig_bdd_2192_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2192 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_2201 assign process. --
ap_sig_bdd_2201_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2201 <= (ap_const_lv1_1 = ap_CS_fsm(162 downto 162));
end process;
-- ap_sig_bdd_2210 assign process. --
ap_sig_bdd_2210_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2210 <= (ap_const_lv1_1 = ap_CS_fsm(177 downto 177));
end process;
-- ap_sig_bdd_2219 assign process. --
ap_sig_bdd_2219_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2219 <= (ap_const_lv1_1 = ap_CS_fsm(192 downto 192));
end process;
-- ap_sig_bdd_2228 assign process. --
ap_sig_bdd_2228_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2228 <= (ap_const_lv1_1 = ap_CS_fsm(207 downto 207));
end process;
-- ap_sig_bdd_2237 assign process. --
ap_sig_bdd_2237_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2237 <= (ap_const_lv1_1 = ap_CS_fsm(222 downto 222));
end process;
-- ap_sig_bdd_2246 assign process. --
ap_sig_bdd_2246_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2246 <= (ap_const_lv1_1 = ap_CS_fsm(237 downto 237));
end process;
-- ap_sig_bdd_2255 assign process. --
ap_sig_bdd_2255_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2255 <= (ap_const_lv1_1 = ap_CS_fsm(252 downto 252));
end process;
-- ap_sig_bdd_2264 assign process. --
ap_sig_bdd_2264_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2264 <= (ap_const_lv1_1 = ap_CS_fsm(267 downto 267));
end process;
-- ap_sig_bdd_2273 assign process. --
ap_sig_bdd_2273_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2273 <= (ap_const_lv1_1 = ap_CS_fsm(282 downto 282));
end process;
-- ap_sig_bdd_2282 assign process. --
ap_sig_bdd_2282_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2282 <= (ap_const_lv1_1 = ap_CS_fsm(297 downto 297));
end process;
-- ap_sig_bdd_2292 assign process. --
ap_sig_bdd_2292_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2292 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_2300 assign process. --
ap_sig_bdd_2300_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2300 <= (ap_const_lv1_1 = ap_CS_fsm(88 downto 88));
end process;
-- ap_sig_bdd_2309 assign process. --
ap_sig_bdd_2309_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2309 <= (ap_const_lv1_1 = ap_CS_fsm(103 downto 103));
end process;
-- ap_sig_bdd_2318 assign process. --
ap_sig_bdd_2318_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2318 <= (ap_const_lv1_1 = ap_CS_fsm(118 downto 118));
end process;
-- ap_sig_bdd_2327 assign process. --
ap_sig_bdd_2327_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2327 <= (ap_const_lv1_1 = ap_CS_fsm(133 downto 133));
end process;
-- ap_sig_bdd_2336 assign process. --
ap_sig_bdd_2336_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2336 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_2345 assign process. --
ap_sig_bdd_2345_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2345 <= (ap_const_lv1_1 = ap_CS_fsm(163 downto 163));
end process;
-- ap_sig_bdd_2354 assign process. --
ap_sig_bdd_2354_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2354 <= (ap_const_lv1_1 = ap_CS_fsm(178 downto 178));
end process;
-- ap_sig_bdd_2363 assign process. --
ap_sig_bdd_2363_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2363 <= (ap_const_lv1_1 = ap_CS_fsm(193 downto 193));
end process;
-- ap_sig_bdd_2372 assign process. --
ap_sig_bdd_2372_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2372 <= (ap_const_lv1_1 = ap_CS_fsm(208 downto 208));
end process;
-- ap_sig_bdd_2381 assign process. --
ap_sig_bdd_2381_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2381 <= (ap_const_lv1_1 = ap_CS_fsm(223 downto 223));
end process;
-- ap_sig_bdd_2390 assign process. --
ap_sig_bdd_2390_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2390 <= (ap_const_lv1_1 = ap_CS_fsm(238 downto 238));
end process;
-- ap_sig_bdd_2399 assign process. --
ap_sig_bdd_2399_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2399 <= (ap_const_lv1_1 = ap_CS_fsm(253 downto 253));
end process;
-- ap_sig_bdd_2408 assign process. --
ap_sig_bdd_2408_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2408 <= (ap_const_lv1_1 = ap_CS_fsm(268 downto 268));
end process;
-- ap_sig_bdd_2417 assign process. --
ap_sig_bdd_2417_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2417 <= (ap_const_lv1_1 = ap_CS_fsm(283 downto 283));
end process;
-- ap_sig_bdd_2426 assign process. --
ap_sig_bdd_2426_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2426 <= (ap_const_lv1_1 = ap_CS_fsm(298 downto 298));
end process;
-- ap_sig_bdd_2437 assign process. --
ap_sig_bdd_2437_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2437 <= (ap_const_lv1_1 = ap_CS_fsm(71 downto 71));
end process;
-- ap_sig_bdd_2694 assign process. --
ap_sig_bdd_2694_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2694 <= (ap_const_lv1_1 = ap_CS_fsm(300 downto 300));
end process;
-- ap_sig_bdd_2708 assign process. --
ap_sig_bdd_2708_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2708 <= (ap_const_lv1_1 = ap_CS_fsm(302 downto 302));
end process;
-- ap_sig_bdd_2719 assign process. --
ap_sig_bdd_2719_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2719 <= (ap_const_lv1_1 = ap_CS_fsm(305 downto 305));
end process;
-- ap_sig_bdd_2728 assign process. --
ap_sig_bdd_2728_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2728 <= (ap_const_lv1_1 = ap_CS_fsm(308 downto 308));
end process;
-- ap_sig_bdd_2737 assign process. --
ap_sig_bdd_2737_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2737 <= (ap_const_lv1_1 = ap_CS_fsm(311 downto 311));
end process;
-- ap_sig_bdd_2746 assign process. --
ap_sig_bdd_2746_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2746 <= (ap_const_lv1_1 = ap_CS_fsm(314 downto 314));
end process;
-- ap_sig_bdd_2755 assign process. --
ap_sig_bdd_2755_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2755 <= (ap_const_lv1_1 = ap_CS_fsm(317 downto 317));
end process;
-- ap_sig_bdd_2764 assign process. --
ap_sig_bdd_2764_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2764 <= (ap_const_lv1_1 = ap_CS_fsm(320 downto 320));
end process;
-- ap_sig_bdd_2773 assign process. --
ap_sig_bdd_2773_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2773 <= (ap_const_lv1_1 = ap_CS_fsm(323 downto 323));
end process;
-- ap_sig_bdd_2782 assign process. --
ap_sig_bdd_2782_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2782 <= (ap_const_lv1_1 = ap_CS_fsm(326 downto 326));
end process;
-- ap_sig_bdd_2791 assign process. --
ap_sig_bdd_2791_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2791 <= (ap_const_lv1_1 = ap_CS_fsm(329 downto 329));
end process;
-- ap_sig_bdd_2800 assign process. --
ap_sig_bdd_2800_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2800 <= (ap_const_lv1_1 = ap_CS_fsm(332 downto 332));
end process;
-- ap_sig_bdd_2809 assign process. --
ap_sig_bdd_2809_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2809 <= (ap_const_lv1_1 = ap_CS_fsm(335 downto 335));
end process;
-- ap_sig_bdd_2818 assign process. --
ap_sig_bdd_2818_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2818 <= (ap_const_lv1_1 = ap_CS_fsm(338 downto 338));
end process;
-- ap_sig_bdd_2827 assign process. --
ap_sig_bdd_2827_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2827 <= (ap_const_lv1_1 = ap_CS_fsm(341 downto 341));
end process;
-- ap_sig_bdd_2836 assign process. --
ap_sig_bdd_2836_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2836 <= (ap_const_lv1_1 = ap_CS_fsm(344 downto 344));
end process;
-- ap_sig_bdd_2845 assign process. --
ap_sig_bdd_2845_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2845 <= (ap_const_lv1_1 = ap_CS_fsm(347 downto 347));
end process;
-- ap_sig_bdd_2854 assign process. --
ap_sig_bdd_2854_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2854 <= (ap_const_lv1_1 = ap_CS_fsm(350 downto 350));
end process;
-- ap_sig_bdd_2863 assign process. --
ap_sig_bdd_2863_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2863 <= (ap_const_lv1_1 = ap_CS_fsm(353 downto 353));
end process;
-- ap_sig_bdd_2872 assign process. --
ap_sig_bdd_2872_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2872 <= (ap_const_lv1_1 = ap_CS_fsm(356 downto 356));
end process;
-- ap_sig_bdd_2881 assign process. --
ap_sig_bdd_2881_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2881 <= (ap_const_lv1_1 = ap_CS_fsm(359 downto 359));
end process;
-- ap_sig_bdd_2893 assign process. --
ap_sig_bdd_2893_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2893 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_2902 assign process. --
ap_sig_bdd_2902_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2902 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_2911 assign process. --
ap_sig_bdd_2911_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2911 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_2920 assign process. --
ap_sig_bdd_2920_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2920 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_2929 assign process. --
ap_sig_bdd_2929_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2929 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_2938 assign process. --
ap_sig_bdd_2938_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2938 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_2947 assign process. --
ap_sig_bdd_2947_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2947 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_2956 assign process. --
ap_sig_bdd_2956_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2956 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_2965 assign process. --
ap_sig_bdd_2965_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2965 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_2974 assign process. --
ap_sig_bdd_2974_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2974 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_2983 assign process. --
ap_sig_bdd_2983_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2983 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_2992 assign process. --
ap_sig_bdd_2992_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_2992 <= (ap_const_lv1_1 = ap_CS_fsm(25 downto 25));
end process;
-- ap_sig_bdd_3001 assign process. --
ap_sig_bdd_3001_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3001 <= (ap_const_lv1_1 = ap_CS_fsm(26 downto 26));
end process;
-- ap_sig_bdd_3010 assign process. --
ap_sig_bdd_3010_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3010 <= (ap_const_lv1_1 = ap_CS_fsm(27 downto 27));
end process;
-- ap_sig_bdd_3019 assign process. --
ap_sig_bdd_3019_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3019 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_3028 assign process. --
ap_sig_bdd_3028_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3028 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_3037 assign process. --
ap_sig_bdd_3037_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3037 <= (ap_const_lv1_1 = ap_CS_fsm(30 downto 30));
end process;
-- ap_sig_bdd_3046 assign process. --
ap_sig_bdd_3046_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3046 <= (ap_const_lv1_1 = ap_CS_fsm(31 downto 31));
end process;
-- ap_sig_bdd_3055 assign process. --
ap_sig_bdd_3055_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3055 <= (ap_const_lv1_1 = ap_CS_fsm(32 downto 32));
end process;
-- ap_sig_bdd_3064 assign process. --
ap_sig_bdd_3064_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3064 <= (ap_const_lv1_1 = ap_CS_fsm(33 downto 33));
end process;
-- ap_sig_bdd_3073 assign process. --
ap_sig_bdd_3073_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3073 <= (ap_const_lv1_1 = ap_CS_fsm(34 downto 34));
end process;
-- ap_sig_bdd_3082 assign process. --
ap_sig_bdd_3082_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3082 <= (ap_const_lv1_1 = ap_CS_fsm(35 downto 35));
end process;
-- ap_sig_bdd_3091 assign process. --
ap_sig_bdd_3091_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3091 <= (ap_const_lv1_1 = ap_CS_fsm(36 downto 36));
end process;
-- ap_sig_bdd_3100 assign process. --
ap_sig_bdd_3100_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3100 <= (ap_const_lv1_1 = ap_CS_fsm(37 downto 37));
end process;
-- ap_sig_bdd_3109 assign process. --
ap_sig_bdd_3109_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3109 <= (ap_const_lv1_1 = ap_CS_fsm(38 downto 38));
end process;
-- ap_sig_bdd_3118 assign process. --
ap_sig_bdd_3118_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3118 <= (ap_const_lv1_1 = ap_CS_fsm(39 downto 39));
end process;
-- ap_sig_bdd_3127 assign process. --
ap_sig_bdd_3127_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3127 <= (ap_const_lv1_1 = ap_CS_fsm(40 downto 40));
end process;
-- ap_sig_bdd_3136 assign process. --
ap_sig_bdd_3136_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3136 <= (ap_const_lv1_1 = ap_CS_fsm(41 downto 41));
end process;
-- ap_sig_bdd_3145 assign process. --
ap_sig_bdd_3145_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3145 <= (ap_const_lv1_1 = ap_CS_fsm(42 downto 42));
end process;
-- ap_sig_bdd_3154 assign process. --
ap_sig_bdd_3154_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3154 <= (ap_const_lv1_1 = ap_CS_fsm(43 downto 43));
end process;
-- ap_sig_bdd_3163 assign process. --
ap_sig_bdd_3163_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3163 <= (ap_const_lv1_1 = ap_CS_fsm(44 downto 44));
end process;
-- ap_sig_bdd_3172 assign process. --
ap_sig_bdd_3172_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3172 <= (ap_const_lv1_1 = ap_CS_fsm(45 downto 45));
end process;
-- ap_sig_bdd_3181 assign process. --
ap_sig_bdd_3181_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3181 <= (ap_const_lv1_1 = ap_CS_fsm(46 downto 46));
end process;
-- ap_sig_bdd_3190 assign process. --
ap_sig_bdd_3190_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3190 <= (ap_const_lv1_1 = ap_CS_fsm(47 downto 47));
end process;
-- ap_sig_bdd_3199 assign process. --
ap_sig_bdd_3199_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3199 <= (ap_const_lv1_1 = ap_CS_fsm(48 downto 48));
end process;
-- ap_sig_bdd_3208 assign process. --
ap_sig_bdd_3208_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3208 <= (ap_const_lv1_1 = ap_CS_fsm(49 downto 49));
end process;
-- ap_sig_bdd_3217 assign process. --
ap_sig_bdd_3217_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3217 <= (ap_const_lv1_1 = ap_CS_fsm(50 downto 50));
end process;
-- ap_sig_bdd_3226 assign process. --
ap_sig_bdd_3226_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3226 <= (ap_const_lv1_1 = ap_CS_fsm(51 downto 51));
end process;
-- ap_sig_bdd_3235 assign process. --
ap_sig_bdd_3235_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3235 <= (ap_const_lv1_1 = ap_CS_fsm(52 downto 52));
end process;
-- ap_sig_bdd_3244 assign process. --
ap_sig_bdd_3244_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3244 <= (ap_const_lv1_1 = ap_CS_fsm(53 downto 53));
end process;
-- ap_sig_bdd_3253 assign process. --
ap_sig_bdd_3253_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3253 <= (ap_const_lv1_1 = ap_CS_fsm(54 downto 54));
end process;
-- ap_sig_bdd_3262 assign process. --
ap_sig_bdd_3262_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3262 <= (ap_const_lv1_1 = ap_CS_fsm(55 downto 55));
end process;
-- ap_sig_bdd_3271 assign process. --
ap_sig_bdd_3271_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3271 <= (ap_const_lv1_1 = ap_CS_fsm(56 downto 56));
end process;
-- ap_sig_bdd_3280 assign process. --
ap_sig_bdd_3280_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3280 <= (ap_const_lv1_1 = ap_CS_fsm(57 downto 57));
end process;
-- ap_sig_bdd_3289 assign process. --
ap_sig_bdd_3289_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3289 <= (ap_const_lv1_1 = ap_CS_fsm(58 downto 58));
end process;
-- ap_sig_bdd_3298 assign process. --
ap_sig_bdd_3298_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3298 <= (ap_const_lv1_1 = ap_CS_fsm(59 downto 59));
end process;
-- ap_sig_bdd_3307 assign process. --
ap_sig_bdd_3307_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3307 <= (ap_const_lv1_1 = ap_CS_fsm(60 downto 60));
end process;
-- ap_sig_bdd_3316 assign process. --
ap_sig_bdd_3316_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3316 <= (ap_const_lv1_1 = ap_CS_fsm(61 downto 61));
end process;
-- ap_sig_bdd_3325 assign process. --
ap_sig_bdd_3325_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3325 <= (ap_const_lv1_1 = ap_CS_fsm(62 downto 62));
end process;
-- ap_sig_bdd_3334 assign process. --
ap_sig_bdd_3334_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3334 <= (ap_const_lv1_1 = ap_CS_fsm(63 downto 63));
end process;
-- ap_sig_bdd_3343 assign process. --
ap_sig_bdd_3343_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3343 <= (ap_const_lv1_1 = ap_CS_fsm(64 downto 64));
end process;
-- ap_sig_bdd_3352 assign process. --
ap_sig_bdd_3352_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3352 <= (ap_const_lv1_1 = ap_CS_fsm(65 downto 65));
end process;
-- ap_sig_bdd_3361 assign process. --
ap_sig_bdd_3361_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3361 <= (ap_const_lv1_1 = ap_CS_fsm(66 downto 66));
end process;
-- ap_sig_bdd_3370 assign process. --
ap_sig_bdd_3370_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3370 <= (ap_const_lv1_1 = ap_CS_fsm(67 downto 67));
end process;
-- ap_sig_bdd_3379 assign process. --
ap_sig_bdd_3379_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3379 <= (ap_const_lv1_1 = ap_CS_fsm(68 downto 68));
end process;
-- ap_sig_bdd_3388 assign process. --
ap_sig_bdd_3388_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3388 <= (ap_const_lv1_1 = ap_CS_fsm(69 downto 69));
end process;
-- ap_sig_bdd_3397 assign process. --
ap_sig_bdd_3397_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3397 <= (ap_const_lv1_1 = ap_CS_fsm(70 downto 70));
end process;
-- ap_sig_bdd_3417 assign process. --
ap_sig_bdd_3417_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3417 <= (ap_const_lv1_1 = ap_CS_fsm(74 downto 74));
end process;
-- ap_sig_bdd_3437 assign process. --
ap_sig_bdd_3437_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3437 <= (ap_const_lv1_1 = ap_CS_fsm(89 downto 89));
end process;
-- ap_sig_bdd_3447 assign process. --
ap_sig_bdd_3447_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3447 <= (ap_const_lv1_1 = ap_CS_fsm(104 downto 104));
end process;
-- ap_sig_bdd_3457 assign process. --
ap_sig_bdd_3457_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3457 <= (ap_const_lv1_1 = ap_CS_fsm(119 downto 119));
end process;
-- ap_sig_bdd_3467 assign process. --
ap_sig_bdd_3467_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3467 <= (ap_const_lv1_1 = ap_CS_fsm(134 downto 134));
end process;
-- ap_sig_bdd_3477 assign process. --
ap_sig_bdd_3477_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3477 <= (ap_const_lv1_1 = ap_CS_fsm(149 downto 149));
end process;
-- ap_sig_bdd_3487 assign process. --
ap_sig_bdd_3487_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3487 <= (ap_const_lv1_1 = ap_CS_fsm(164 downto 164));
end process;
-- ap_sig_bdd_3497 assign process. --
ap_sig_bdd_3497_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3497 <= (ap_const_lv1_1 = ap_CS_fsm(179 downto 179));
end process;
-- ap_sig_bdd_3507 assign process. --
ap_sig_bdd_3507_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3507 <= (ap_const_lv1_1 = ap_CS_fsm(194 downto 194));
end process;
-- ap_sig_bdd_3517 assign process. --
ap_sig_bdd_3517_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3517 <= (ap_const_lv1_1 = ap_CS_fsm(209 downto 209));
end process;
-- ap_sig_bdd_3527 assign process. --
ap_sig_bdd_3527_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3527 <= (ap_const_lv1_1 = ap_CS_fsm(224 downto 224));
end process;
-- ap_sig_bdd_3537 assign process. --
ap_sig_bdd_3537_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3537 <= (ap_const_lv1_1 = ap_CS_fsm(239 downto 239));
end process;
-- ap_sig_bdd_3547 assign process. --
ap_sig_bdd_3547_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_3547 <= (ap_const_lv1_1 = ap_CS_fsm(299 downto 299));
end process;
-- ap_sig_bdd_399 assign process. --
ap_sig_bdd_399_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_399 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_410 assign process. --
ap_sig_bdd_410_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_410 <= (ap_const_lv1_1 = ap_CS_fsm(72 downto 72));
end process;
-- ap_sig_bdd_419 assign process. --
ap_sig_bdd_419_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_419 <= (ap_const_lv1_1 = ap_CS_fsm(75 downto 75));
end process;
-- ap_sig_bdd_428 assign process. --
ap_sig_bdd_428_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_428 <= (ap_const_lv1_1 = ap_CS_fsm(90 downto 90));
end process;
-- ap_sig_bdd_437 assign process. --
ap_sig_bdd_437_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_437 <= (ap_const_lv1_1 = ap_CS_fsm(105 downto 105));
end process;
-- ap_sig_bdd_446 assign process. --
ap_sig_bdd_446_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_446 <= (ap_const_lv1_1 = ap_CS_fsm(120 downto 120));
end process;
-- ap_sig_bdd_455 assign process. --
ap_sig_bdd_455_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_455 <= (ap_const_lv1_1 = ap_CS_fsm(135 downto 135));
end process;
-- ap_sig_bdd_464 assign process. --
ap_sig_bdd_464_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_464 <= (ap_const_lv1_1 = ap_CS_fsm(150 downto 150));
end process;
-- ap_sig_bdd_473 assign process. --
ap_sig_bdd_473_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_473 <= (ap_const_lv1_1 = ap_CS_fsm(165 downto 165));
end process;
-- ap_sig_bdd_482 assign process. --
ap_sig_bdd_482_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_482 <= (ap_const_lv1_1 = ap_CS_fsm(180 downto 180));
end process;
-- ap_sig_bdd_491 assign process. --
ap_sig_bdd_491_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_491 <= (ap_const_lv1_1 = ap_CS_fsm(195 downto 195));
end process;
-- ap_sig_bdd_500 assign process. --
ap_sig_bdd_500_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_500 <= (ap_const_lv1_1 = ap_CS_fsm(210 downto 210));
end process;
-- ap_sig_bdd_5023 assign process. --
ap_sig_bdd_5023_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5023 <= (ap_const_lv1_1 = ap_CS_fsm(254 downto 254));
end process;
-- ap_sig_bdd_5046 assign process. --
ap_sig_bdd_5046_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5046 <= (ap_const_lv1_1 = ap_CS_fsm(269 downto 269));
end process;
-- ap_sig_bdd_5069 assign process. --
ap_sig_bdd_5069_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5069 <= (ap_const_lv1_1 = ap_CS_fsm(284 downto 284));
end process;
-- ap_sig_bdd_509 assign process. --
ap_sig_bdd_509_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_509 <= (ap_const_lv1_1 = ap_CS_fsm(225 downto 225));
end process;
-- ap_sig_bdd_5096 assign process. --
ap_sig_bdd_5096_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5096 <= (ap_const_lv1_1 = ap_CS_fsm(303 downto 303));
end process;
-- ap_sig_bdd_5104 assign process. --
ap_sig_bdd_5104_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5104 <= (ap_const_lv1_1 = ap_CS_fsm(304 downto 304));
end process;
-- ap_sig_bdd_5113 assign process. --
ap_sig_bdd_5113_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5113 <= (ap_const_lv1_1 = ap_CS_fsm(306 downto 306));
end process;
-- ap_sig_bdd_5121 assign process. --
ap_sig_bdd_5121_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5121 <= (ap_const_lv1_1 = ap_CS_fsm(307 downto 307));
end process;
-- ap_sig_bdd_5130 assign process. --
ap_sig_bdd_5130_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5130 <= (ap_const_lv1_1 = ap_CS_fsm(309 downto 309));
end process;
-- ap_sig_bdd_5138 assign process. --
ap_sig_bdd_5138_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5138 <= (ap_const_lv1_1 = ap_CS_fsm(310 downto 310));
end process;
-- ap_sig_bdd_5147 assign process. --
ap_sig_bdd_5147_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5147 <= (ap_const_lv1_1 = ap_CS_fsm(312 downto 312));
end process;
-- ap_sig_bdd_5155 assign process. --
ap_sig_bdd_5155_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5155 <= (ap_const_lv1_1 = ap_CS_fsm(313 downto 313));
end process;
-- ap_sig_bdd_5164 assign process. --
ap_sig_bdd_5164_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5164 <= (ap_const_lv1_1 = ap_CS_fsm(315 downto 315));
end process;
-- ap_sig_bdd_5172 assign process. --
ap_sig_bdd_5172_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5172 <= (ap_const_lv1_1 = ap_CS_fsm(316 downto 316));
end process;
-- ap_sig_bdd_518 assign process. --
ap_sig_bdd_518_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_518 <= (ap_const_lv1_1 = ap_CS_fsm(240 downto 240));
end process;
-- ap_sig_bdd_5181 assign process. --
ap_sig_bdd_5181_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5181 <= (ap_const_lv1_1 = ap_CS_fsm(318 downto 318));
end process;
-- ap_sig_bdd_5189 assign process. --
ap_sig_bdd_5189_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5189 <= (ap_const_lv1_1 = ap_CS_fsm(319 downto 319));
end process;
-- ap_sig_bdd_5198 assign process. --
ap_sig_bdd_5198_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5198 <= (ap_const_lv1_1 = ap_CS_fsm(321 downto 321));
end process;
-- ap_sig_bdd_5206 assign process. --
ap_sig_bdd_5206_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5206 <= (ap_const_lv1_1 = ap_CS_fsm(322 downto 322));
end process;
-- ap_sig_bdd_5215 assign process. --
ap_sig_bdd_5215_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5215 <= (ap_const_lv1_1 = ap_CS_fsm(324 downto 324));
end process;
-- ap_sig_bdd_5223 assign process. --
ap_sig_bdd_5223_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5223 <= (ap_const_lv1_1 = ap_CS_fsm(325 downto 325));
end process;
-- ap_sig_bdd_5232 assign process. --
ap_sig_bdd_5232_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5232 <= (ap_const_lv1_1 = ap_CS_fsm(327 downto 327));
end process;
-- ap_sig_bdd_5240 assign process. --
ap_sig_bdd_5240_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5240 <= (ap_const_lv1_1 = ap_CS_fsm(328 downto 328));
end process;
-- ap_sig_bdd_5249 assign process. --
ap_sig_bdd_5249_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5249 <= (ap_const_lv1_1 = ap_CS_fsm(330 downto 330));
end process;
-- ap_sig_bdd_5257 assign process. --
ap_sig_bdd_5257_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5257 <= (ap_const_lv1_1 = ap_CS_fsm(331 downto 331));
end process;
-- ap_sig_bdd_5266 assign process. --
ap_sig_bdd_5266_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5266 <= (ap_const_lv1_1 = ap_CS_fsm(333 downto 333));
end process;
-- ap_sig_bdd_527 assign process. --
ap_sig_bdd_527_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_527 <= (ap_const_lv1_1 = ap_CS_fsm(255 downto 255));
end process;
-- ap_sig_bdd_5274 assign process. --
ap_sig_bdd_5274_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5274 <= (ap_const_lv1_1 = ap_CS_fsm(334 downto 334));
end process;
-- ap_sig_bdd_5283 assign process. --
ap_sig_bdd_5283_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5283 <= (ap_const_lv1_1 = ap_CS_fsm(336 downto 336));
end process;
-- ap_sig_bdd_5291 assign process. --
ap_sig_bdd_5291_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5291 <= (ap_const_lv1_1 = ap_CS_fsm(337 downto 337));
end process;
-- ap_sig_bdd_5300 assign process. --
ap_sig_bdd_5300_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5300 <= (ap_const_lv1_1 = ap_CS_fsm(339 downto 339));
end process;
-- ap_sig_bdd_5308 assign process. --
ap_sig_bdd_5308_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5308 <= (ap_const_lv1_1 = ap_CS_fsm(340 downto 340));
end process;
-- ap_sig_bdd_5317 assign process. --
ap_sig_bdd_5317_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5317 <= (ap_const_lv1_1 = ap_CS_fsm(342 downto 342));
end process;
-- ap_sig_bdd_5325 assign process. --
ap_sig_bdd_5325_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5325 <= (ap_const_lv1_1 = ap_CS_fsm(343 downto 343));
end process;
-- ap_sig_bdd_5334 assign process. --
ap_sig_bdd_5334_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5334 <= (ap_const_lv1_1 = ap_CS_fsm(345 downto 345));
end process;
-- ap_sig_bdd_5342 assign process. --
ap_sig_bdd_5342_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5342 <= (ap_const_lv1_1 = ap_CS_fsm(346 downto 346));
end process;
-- ap_sig_bdd_5351 assign process. --
ap_sig_bdd_5351_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5351 <= (ap_const_lv1_1 = ap_CS_fsm(348 downto 348));
end process;
-- ap_sig_bdd_5359 assign process. --
ap_sig_bdd_5359_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5359 <= (ap_const_lv1_1 = ap_CS_fsm(349 downto 349));
end process;
-- ap_sig_bdd_536 assign process. --
ap_sig_bdd_536_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_536 <= (ap_const_lv1_1 = ap_CS_fsm(270 downto 270));
end process;
-- ap_sig_bdd_5368 assign process. --
ap_sig_bdd_5368_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5368 <= (ap_const_lv1_1 = ap_CS_fsm(351 downto 351));
end process;
-- ap_sig_bdd_5376 assign process. --
ap_sig_bdd_5376_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5376 <= (ap_const_lv1_1 = ap_CS_fsm(352 downto 352));
end process;
-- ap_sig_bdd_5385 assign process. --
ap_sig_bdd_5385_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5385 <= (ap_const_lv1_1 = ap_CS_fsm(354 downto 354));
end process;
-- ap_sig_bdd_5393 assign process. --
ap_sig_bdd_5393_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5393 <= (ap_const_lv1_1 = ap_CS_fsm(355 downto 355));
end process;
-- ap_sig_bdd_5402 assign process. --
ap_sig_bdd_5402_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5402 <= (ap_const_lv1_1 = ap_CS_fsm(357 downto 357));
end process;
-- ap_sig_bdd_5410 assign process. --
ap_sig_bdd_5410_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5410 <= (ap_const_lv1_1 = ap_CS_fsm(358 downto 358));
end process;
-- ap_sig_bdd_5419 assign process. --
ap_sig_bdd_5419_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5419 <= (ap_const_lv1_1 = ap_CS_fsm(360 downto 360));
end process;
-- ap_sig_bdd_5427 assign process. --
ap_sig_bdd_5427_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5427 <= (ap_const_lv1_1 = ap_CS_fsm(361 downto 361));
end process;
-- ap_sig_bdd_545 assign process. --
ap_sig_bdd_545_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_545 <= (ap_const_lv1_1 = ap_CS_fsm(285 downto 285));
end process;
-- ap_sig_bdd_555 assign process. --
ap_sig_bdd_555_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_555 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_563 assign process. --
ap_sig_bdd_563_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_563 <= (ap_const_lv1_1 = ap_CS_fsm(73 downto 73));
end process;
-- ap_sig_bdd_572 assign process. --
ap_sig_bdd_572_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_572 <= (ap_const_lv1_1 = ap_CS_fsm(76 downto 76));
end process;
-- ap_sig_bdd_581 assign process. --
ap_sig_bdd_581_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_581 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_590 assign process. --
ap_sig_bdd_590_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_590 <= (ap_const_lv1_1 = ap_CS_fsm(106 downto 106));
end process;
-- ap_sig_bdd_5902 assign process. --
ap_sig_bdd_5902_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_5902 <= (ap_const_lv1_1 = ap_CS_fsm(301 downto 301));
end process;
-- ap_sig_bdd_599 assign process. --
ap_sig_bdd_599_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_599 <= (ap_const_lv1_1 = ap_CS_fsm(121 downto 121));
end process;
-- ap_sig_bdd_608 assign process. --
ap_sig_bdd_608_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_608 <= (ap_const_lv1_1 = ap_CS_fsm(136 downto 136));
end process;
-- ap_sig_bdd_617 assign process. --
ap_sig_bdd_617_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_617 <= (ap_const_lv1_1 = ap_CS_fsm(151 downto 151));
end process;
-- ap_sig_bdd_626 assign process. --
ap_sig_bdd_626_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_626 <= (ap_const_lv1_1 = ap_CS_fsm(166 downto 166));
end process;
-- ap_sig_bdd_635 assign process. --
ap_sig_bdd_635_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_635 <= (ap_const_lv1_1 = ap_CS_fsm(181 downto 181));
end process;
-- ap_sig_bdd_644 assign process. --
ap_sig_bdd_644_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_644 <= (ap_const_lv1_1 = ap_CS_fsm(196 downto 196));
end process;
-- ap_sig_bdd_653 assign process. --
ap_sig_bdd_653_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_653 <= (ap_const_lv1_1 = ap_CS_fsm(211 downto 211));
end process;
-- ap_sig_bdd_662 assign process. --
ap_sig_bdd_662_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_662 <= (ap_const_lv1_1 = ap_CS_fsm(226 downto 226));
end process;
-- ap_sig_bdd_671 assign process. --
ap_sig_bdd_671_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_671 <= (ap_const_lv1_1 = ap_CS_fsm(241 downto 241));
end process;
-- ap_sig_bdd_680 assign process. --
ap_sig_bdd_680_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_680 <= (ap_const_lv1_1 = ap_CS_fsm(256 downto 256));
end process;
-- ap_sig_bdd_689 assign process. --
ap_sig_bdd_689_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_689 <= (ap_const_lv1_1 = ap_CS_fsm(271 downto 271));
end process;
-- ap_sig_bdd_698 assign process. --
ap_sig_bdd_698_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_698 <= (ap_const_lv1_1 = ap_CS_fsm(286 downto 286));
end process;
-- ap_sig_bdd_708 assign process. --
ap_sig_bdd_708_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_708 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_716 assign process. --
ap_sig_bdd_716_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_716 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_725 assign process. --
ap_sig_bdd_725_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_725 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_734 assign process. --
ap_sig_bdd_734_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_734 <= (ap_const_lv1_1 = ap_CS_fsm(107 downto 107));
end process;
-- ap_sig_bdd_743 assign process. --
ap_sig_bdd_743_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_743 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_752 assign process. --
ap_sig_bdd_752_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_752 <= (ap_const_lv1_1 = ap_CS_fsm(137 downto 137));
end process;
-- ap_sig_bdd_761 assign process. --
ap_sig_bdd_761_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_761 <= (ap_const_lv1_1 = ap_CS_fsm(152 downto 152));
end process;
-- ap_sig_bdd_770 assign process. --
ap_sig_bdd_770_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_770 <= (ap_const_lv1_1 = ap_CS_fsm(167 downto 167));
end process;
-- ap_sig_bdd_779 assign process. --
ap_sig_bdd_779_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_779 <= (ap_const_lv1_1 = ap_CS_fsm(182 downto 182));
end process;
-- ap_sig_bdd_788 assign process. --
ap_sig_bdd_788_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_788 <= (ap_const_lv1_1 = ap_CS_fsm(197 downto 197));
end process;
-- ap_sig_bdd_797 assign process. --
ap_sig_bdd_797_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_797 <= (ap_const_lv1_1 = ap_CS_fsm(212 downto 212));
end process;
-- ap_sig_bdd_806 assign process. --
ap_sig_bdd_806_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_806 <= (ap_const_lv1_1 = ap_CS_fsm(227 downto 227));
end process;
-- ap_sig_bdd_815 assign process. --
ap_sig_bdd_815_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_815 <= (ap_const_lv1_1 = ap_CS_fsm(242 downto 242));
end process;
-- ap_sig_bdd_824 assign process. --
ap_sig_bdd_824_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_824 <= (ap_const_lv1_1 = ap_CS_fsm(257 downto 257));
end process;
-- ap_sig_bdd_833 assign process. --
ap_sig_bdd_833_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_833 <= (ap_const_lv1_1 = ap_CS_fsm(272 downto 272));
end process;
-- ap_sig_bdd_842 assign process. --
ap_sig_bdd_842_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_842 <= (ap_const_lv1_1 = ap_CS_fsm(287 downto 287));
end process;
-- ap_sig_bdd_852 assign process. --
ap_sig_bdd_852_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_852 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_860 assign process. --
ap_sig_bdd_860_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_860 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_869 assign process. --
ap_sig_bdd_869_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_869 <= (ap_const_lv1_1 = ap_CS_fsm(93 downto 93));
end process;
-- ap_sig_bdd_878 assign process. --
ap_sig_bdd_878_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_878 <= (ap_const_lv1_1 = ap_CS_fsm(108 downto 108));
end process;
-- ap_sig_bdd_887 assign process. --
ap_sig_bdd_887_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_887 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_896 assign process. --
ap_sig_bdd_896_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_896 <= (ap_const_lv1_1 = ap_CS_fsm(138 downto 138));
end process;
-- ap_sig_bdd_905 assign process. --
ap_sig_bdd_905_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_905 <= (ap_const_lv1_1 = ap_CS_fsm(153 downto 153));
end process;
-- ap_sig_bdd_914 assign process. --
ap_sig_bdd_914_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_914 <= (ap_const_lv1_1 = ap_CS_fsm(168 downto 168));
end process;
-- ap_sig_bdd_923 assign process. --
ap_sig_bdd_923_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_923 <= (ap_const_lv1_1 = ap_CS_fsm(183 downto 183));
end process;
-- ap_sig_bdd_932 assign process. --
ap_sig_bdd_932_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_932 <= (ap_const_lv1_1 = ap_CS_fsm(198 downto 198));
end process;
-- ap_sig_bdd_941 assign process. --
ap_sig_bdd_941_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_941 <= (ap_const_lv1_1 = ap_CS_fsm(213 downto 213));
end process;
-- ap_sig_bdd_950 assign process. --
ap_sig_bdd_950_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_950 <= (ap_const_lv1_1 = ap_CS_fsm(228 downto 228));
end process;
-- ap_sig_bdd_959 assign process. --
ap_sig_bdd_959_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_959 <= (ap_const_lv1_1 = ap_CS_fsm(243 downto 243));
end process;
-- ap_sig_bdd_968 assign process. --
ap_sig_bdd_968_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_968 <= (ap_const_lv1_1 = ap_CS_fsm(258 downto 258));
end process;
-- ap_sig_bdd_977 assign process. --
ap_sig_bdd_977_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_977 <= (ap_const_lv1_1 = ap_CS_fsm(273 downto 273));
end process;
-- ap_sig_bdd_986 assign process. --
ap_sig_bdd_986_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_986 <= (ap_const_lv1_1 = ap_CS_fsm(288 downto 288));
end process;
-- ap_sig_bdd_996 assign process. --
ap_sig_bdd_996_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_996 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_300 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_300_assign_proc : process(ap_sig_bdd_2694)
begin
if (ap_sig_bdd_2694) then
ap_sig_cseq_ST_pp0_stg0_fsm_300 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_300 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st100_fsm_99 assign process. --
ap_sig_cseq_ST_st100_fsm_99_assign_proc : process(ap_sig_bdd_1733)
begin
if (ap_sig_bdd_1733) then
ap_sig_cseq_ST_st100_fsm_99 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st100_fsm_99 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st101_fsm_100 assign process. --
ap_sig_cseq_ST_st101_fsm_100_assign_proc : process(ap_sig_bdd_1877)
begin
if (ap_sig_bdd_1877) then
ap_sig_cseq_ST_st101_fsm_100 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st101_fsm_100 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st102_fsm_101 assign process. --
ap_sig_cseq_ST_st102_fsm_101_assign_proc : process(ap_sig_bdd_2021)
begin
if (ap_sig_bdd_2021) then
ap_sig_cseq_ST_st102_fsm_101 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st102_fsm_101 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st103_fsm_102 assign process. --
ap_sig_cseq_ST_st103_fsm_102_assign_proc : process(ap_sig_bdd_2165)
begin
if (ap_sig_bdd_2165) then
ap_sig_cseq_ST_st103_fsm_102 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st103_fsm_102 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st104_fsm_103 assign process. --
ap_sig_cseq_ST_st104_fsm_103_assign_proc : process(ap_sig_bdd_2309)
begin
if (ap_sig_bdd_2309) then
ap_sig_cseq_ST_st104_fsm_103 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st104_fsm_103 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st105_fsm_104 assign process. --
ap_sig_cseq_ST_st105_fsm_104_assign_proc : process(ap_sig_bdd_3447)
begin
if (ap_sig_bdd_3447) then
ap_sig_cseq_ST_st105_fsm_104 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st105_fsm_104 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st106_fsm_105 assign process. --
ap_sig_cseq_ST_st106_fsm_105_assign_proc : process(ap_sig_bdd_437)
begin
if (ap_sig_bdd_437) then
ap_sig_cseq_ST_st106_fsm_105 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st106_fsm_105 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st107_fsm_106 assign process. --
ap_sig_cseq_ST_st107_fsm_106_assign_proc : process(ap_sig_bdd_590)
begin
if (ap_sig_bdd_590) then
ap_sig_cseq_ST_st107_fsm_106 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st107_fsm_106 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st108_fsm_107 assign process. --
ap_sig_cseq_ST_st108_fsm_107_assign_proc : process(ap_sig_bdd_734)
begin
if (ap_sig_bdd_734) then
ap_sig_cseq_ST_st108_fsm_107 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st108_fsm_107 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st109_fsm_108 assign process. --
ap_sig_cseq_ST_st109_fsm_108_assign_proc : process(ap_sig_bdd_878)
begin
if (ap_sig_bdd_878) then
ap_sig_cseq_ST_st109_fsm_108 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st109_fsm_108 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_1716)
begin
if (ap_sig_bdd_1716) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st110_fsm_109 assign process. --
ap_sig_cseq_ST_st110_fsm_109_assign_proc : process(ap_sig_bdd_1022)
begin
if (ap_sig_bdd_1022) then
ap_sig_cseq_ST_st110_fsm_109 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st110_fsm_109 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st111_fsm_110 assign process. --
ap_sig_cseq_ST_st111_fsm_110_assign_proc : process(ap_sig_bdd_1166)
begin
if (ap_sig_bdd_1166) then
ap_sig_cseq_ST_st111_fsm_110 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st111_fsm_110 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st112_fsm_111 assign process. --
ap_sig_cseq_ST_st112_fsm_111_assign_proc : process(ap_sig_bdd_1310)
begin
if (ap_sig_bdd_1310) then
ap_sig_cseq_ST_st112_fsm_111 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st112_fsm_111 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st113_fsm_112 assign process. --
ap_sig_cseq_ST_st113_fsm_112_assign_proc : process(ap_sig_bdd_1454)
begin
if (ap_sig_bdd_1454) then
ap_sig_cseq_ST_st113_fsm_112 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st113_fsm_112 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st114_fsm_113 assign process. --
ap_sig_cseq_ST_st114_fsm_113_assign_proc : process(ap_sig_bdd_1598)
begin
if (ap_sig_bdd_1598) then
ap_sig_cseq_ST_st114_fsm_113 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st114_fsm_113 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st115_fsm_114 assign process. --
ap_sig_cseq_ST_st115_fsm_114_assign_proc : process(ap_sig_bdd_1742)
begin
if (ap_sig_bdd_1742) then
ap_sig_cseq_ST_st115_fsm_114 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st115_fsm_114 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st116_fsm_115 assign process. --
ap_sig_cseq_ST_st116_fsm_115_assign_proc : process(ap_sig_bdd_1886)
begin
if (ap_sig_bdd_1886) then
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_2030)
begin
if (ap_sig_bdd_2030) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_117 assign process. --
ap_sig_cseq_ST_st118_fsm_117_assign_proc : process(ap_sig_bdd_2174)
begin
if (ap_sig_bdd_2174) then
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_118 assign process. --
ap_sig_cseq_ST_st119_fsm_118_assign_proc : process(ap_sig_bdd_2318)
begin
if (ap_sig_bdd_2318) then
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_118 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_1860)
begin
if (ap_sig_bdd_1860) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st120_fsm_119 assign process. --
ap_sig_cseq_ST_st120_fsm_119_assign_proc : process(ap_sig_bdd_3457)
begin
if (ap_sig_bdd_3457) then
ap_sig_cseq_ST_st120_fsm_119 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st120_fsm_119 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st121_fsm_120 assign process. --
ap_sig_cseq_ST_st121_fsm_120_assign_proc : process(ap_sig_bdd_446)
begin
if (ap_sig_bdd_446) then
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st121_fsm_120 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st122_fsm_121 assign process. --
ap_sig_cseq_ST_st122_fsm_121_assign_proc : process(ap_sig_bdd_599)
begin
if (ap_sig_bdd_599) then
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_743)
begin
if (ap_sig_bdd_743) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_887)
begin
if (ap_sig_bdd_887) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st125_fsm_124 assign process. --
ap_sig_cseq_ST_st125_fsm_124_assign_proc : process(ap_sig_bdd_1031)
begin
if (ap_sig_bdd_1031) then
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st125_fsm_124 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st126_fsm_125 assign process. --
ap_sig_cseq_ST_st126_fsm_125_assign_proc : process(ap_sig_bdd_1175)
begin
if (ap_sig_bdd_1175) then
ap_sig_cseq_ST_st126_fsm_125 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st126_fsm_125 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st127_fsm_126 assign process. --
ap_sig_cseq_ST_st127_fsm_126_assign_proc : process(ap_sig_bdd_1319)
begin
if (ap_sig_bdd_1319) then
ap_sig_cseq_ST_st127_fsm_126 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st127_fsm_126 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st128_fsm_127 assign process. --
ap_sig_cseq_ST_st128_fsm_127_assign_proc : process(ap_sig_bdd_1463)
begin
if (ap_sig_bdd_1463) then
ap_sig_cseq_ST_st128_fsm_127 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st128_fsm_127 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st129_fsm_128 assign process. --
ap_sig_cseq_ST_st129_fsm_128_assign_proc : process(ap_sig_bdd_1607)
begin
if (ap_sig_bdd_1607) then
ap_sig_cseq_ST_st129_fsm_128 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st129_fsm_128 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_2004)
begin
if (ap_sig_bdd_2004) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st130_fsm_129 assign process. --
ap_sig_cseq_ST_st130_fsm_129_assign_proc : process(ap_sig_bdd_1751)
begin
if (ap_sig_bdd_1751) then
ap_sig_cseq_ST_st130_fsm_129 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st130_fsm_129 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st131_fsm_130 assign process. --
ap_sig_cseq_ST_st131_fsm_130_assign_proc : process(ap_sig_bdd_1895)
begin
if (ap_sig_bdd_1895) then
ap_sig_cseq_ST_st131_fsm_130 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st131_fsm_130 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st132_fsm_131 assign process. --
ap_sig_cseq_ST_st132_fsm_131_assign_proc : process(ap_sig_bdd_2039)
begin
if (ap_sig_bdd_2039) then
ap_sig_cseq_ST_st132_fsm_131 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st132_fsm_131 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st133_fsm_132 assign process. --
ap_sig_cseq_ST_st133_fsm_132_assign_proc : process(ap_sig_bdd_2183)
begin
if (ap_sig_bdd_2183) then
ap_sig_cseq_ST_st133_fsm_132 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st133_fsm_132 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st134_fsm_133 assign process. --
ap_sig_cseq_ST_st134_fsm_133_assign_proc : process(ap_sig_bdd_2327)
begin
if (ap_sig_bdd_2327) then
ap_sig_cseq_ST_st134_fsm_133 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st134_fsm_133 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st135_fsm_134 assign process. --
ap_sig_cseq_ST_st135_fsm_134_assign_proc : process(ap_sig_bdd_3467)
begin
if (ap_sig_bdd_3467) then
ap_sig_cseq_ST_st135_fsm_134 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st135_fsm_134 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st136_fsm_135 assign process. --
ap_sig_cseq_ST_st136_fsm_135_assign_proc : process(ap_sig_bdd_455)
begin
if (ap_sig_bdd_455) then
ap_sig_cseq_ST_st136_fsm_135 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st136_fsm_135 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st137_fsm_136 assign process. --
ap_sig_cseq_ST_st137_fsm_136_assign_proc : process(ap_sig_bdd_608)
begin
if (ap_sig_bdd_608) then
ap_sig_cseq_ST_st137_fsm_136 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st137_fsm_136 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st138_fsm_137 assign process. --
ap_sig_cseq_ST_st138_fsm_137_assign_proc : process(ap_sig_bdd_752)
begin
if (ap_sig_bdd_752) then
ap_sig_cseq_ST_st138_fsm_137 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st138_fsm_137 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st139_fsm_138 assign process. --
ap_sig_cseq_ST_st139_fsm_138_assign_proc : process(ap_sig_bdd_896)
begin
if (ap_sig_bdd_896) then
ap_sig_cseq_ST_st139_fsm_138 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st139_fsm_138 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_2148)
begin
if (ap_sig_bdd_2148) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st140_fsm_139 assign process. --
ap_sig_cseq_ST_st140_fsm_139_assign_proc : process(ap_sig_bdd_1040)
begin
if (ap_sig_bdd_1040) then
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_1184)
begin
if (ap_sig_bdd_1184) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_1328)
begin
if (ap_sig_bdd_1328) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_1472)
begin
if (ap_sig_bdd_1472) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st144_fsm_143 assign process. --
ap_sig_cseq_ST_st144_fsm_143_assign_proc : process(ap_sig_bdd_1616)
begin
if (ap_sig_bdd_1616) then
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st144_fsm_143 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st145_fsm_144 assign process. --
ap_sig_cseq_ST_st145_fsm_144_assign_proc : process(ap_sig_bdd_1760)
begin
if (ap_sig_bdd_1760) then
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st145_fsm_144 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_1904)
begin
if (ap_sig_bdd_1904) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_2048)
begin
if (ap_sig_bdd_2048) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_2192)
begin
if (ap_sig_bdd_2192) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_2336)
begin
if (ap_sig_bdd_2336) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_2292)
begin
if (ap_sig_bdd_2292) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st150_fsm_149 assign process. --
ap_sig_cseq_ST_st150_fsm_149_assign_proc : process(ap_sig_bdd_3477)
begin
if (ap_sig_bdd_3477) then
ap_sig_cseq_ST_st150_fsm_149 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st150_fsm_149 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st151_fsm_150 assign process. --
ap_sig_cseq_ST_st151_fsm_150_assign_proc : process(ap_sig_bdd_464)
begin
if (ap_sig_bdd_464) then
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st151_fsm_150 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st152_fsm_151 assign process. --
ap_sig_cseq_ST_st152_fsm_151_assign_proc : process(ap_sig_bdd_617)
begin
if (ap_sig_bdd_617) then
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st152_fsm_151 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st153_fsm_152 assign process. --
ap_sig_cseq_ST_st153_fsm_152_assign_proc : process(ap_sig_bdd_761)
begin
if (ap_sig_bdd_761) then
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st153_fsm_152 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st154_fsm_153 assign process. --
ap_sig_cseq_ST_st154_fsm_153_assign_proc : process(ap_sig_bdd_905)
begin
if (ap_sig_bdd_905) then
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st154_fsm_153 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st155_fsm_154 assign process. --
ap_sig_cseq_ST_st155_fsm_154_assign_proc : process(ap_sig_bdd_1049)
begin
if (ap_sig_bdd_1049) then
ap_sig_cseq_ST_st155_fsm_154 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st155_fsm_154 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st156_fsm_155 assign process. --
ap_sig_cseq_ST_st156_fsm_155_assign_proc : process(ap_sig_bdd_1193)
begin
if (ap_sig_bdd_1193) then
ap_sig_cseq_ST_st156_fsm_155 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st156_fsm_155 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st157_fsm_156 assign process. --
ap_sig_cseq_ST_st157_fsm_156_assign_proc : process(ap_sig_bdd_1337)
begin
if (ap_sig_bdd_1337) then
ap_sig_cseq_ST_st157_fsm_156 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st157_fsm_156 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st158_fsm_157 assign process. --
ap_sig_cseq_ST_st158_fsm_157_assign_proc : process(ap_sig_bdd_1481)
begin
if (ap_sig_bdd_1481) then
ap_sig_cseq_ST_st158_fsm_157 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st158_fsm_157 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st159_fsm_158 assign process. --
ap_sig_cseq_ST_st159_fsm_158_assign_proc : process(ap_sig_bdd_1625)
begin
if (ap_sig_bdd_1625) then
ap_sig_cseq_ST_st159_fsm_158 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st159_fsm_158 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_2893)
begin
if (ap_sig_bdd_2893) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st160_fsm_159 assign process. --
ap_sig_cseq_ST_st160_fsm_159_assign_proc : process(ap_sig_bdd_1769)
begin
if (ap_sig_bdd_1769) then
ap_sig_cseq_ST_st160_fsm_159 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st160_fsm_159 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st161_fsm_160 assign process. --
ap_sig_cseq_ST_st161_fsm_160_assign_proc : process(ap_sig_bdd_1913)
begin
if (ap_sig_bdd_1913) then
ap_sig_cseq_ST_st161_fsm_160 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st161_fsm_160 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st162_fsm_161 assign process. --
ap_sig_cseq_ST_st162_fsm_161_assign_proc : process(ap_sig_bdd_2057)
begin
if (ap_sig_bdd_2057) then
ap_sig_cseq_ST_st162_fsm_161 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st162_fsm_161 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st163_fsm_162 assign process. --
ap_sig_cseq_ST_st163_fsm_162_assign_proc : process(ap_sig_bdd_2201)
begin
if (ap_sig_bdd_2201) then
ap_sig_cseq_ST_st163_fsm_162 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st163_fsm_162 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st164_fsm_163 assign process. --
ap_sig_cseq_ST_st164_fsm_163_assign_proc : process(ap_sig_bdd_2345)
begin
if (ap_sig_bdd_2345) then
ap_sig_cseq_ST_st164_fsm_163 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st164_fsm_163 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st165_fsm_164 assign process. --
ap_sig_cseq_ST_st165_fsm_164_assign_proc : process(ap_sig_bdd_3487)
begin
if (ap_sig_bdd_3487) then
ap_sig_cseq_ST_st165_fsm_164 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st165_fsm_164 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st166_fsm_165 assign process. --
ap_sig_cseq_ST_st166_fsm_165_assign_proc : process(ap_sig_bdd_473)
begin
if (ap_sig_bdd_473) then
ap_sig_cseq_ST_st166_fsm_165 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st166_fsm_165 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st167_fsm_166 assign process. --
ap_sig_cseq_ST_st167_fsm_166_assign_proc : process(ap_sig_bdd_626)
begin
if (ap_sig_bdd_626) then
ap_sig_cseq_ST_st167_fsm_166 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st167_fsm_166 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st168_fsm_167 assign process. --
ap_sig_cseq_ST_st168_fsm_167_assign_proc : process(ap_sig_bdd_770)
begin
if (ap_sig_bdd_770) then
ap_sig_cseq_ST_st168_fsm_167 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st168_fsm_167 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st169_fsm_168 assign process. --
ap_sig_cseq_ST_st169_fsm_168_assign_proc : process(ap_sig_bdd_914)
begin
if (ap_sig_bdd_914) then
ap_sig_cseq_ST_st169_fsm_168 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st169_fsm_168 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_2902)
begin
if (ap_sig_bdd_2902) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st170_fsm_169 assign process. --
ap_sig_cseq_ST_st170_fsm_169_assign_proc : process(ap_sig_bdd_1058)
begin
if (ap_sig_bdd_1058) then
ap_sig_cseq_ST_st170_fsm_169 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st170_fsm_169 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st171_fsm_170 assign process. --
ap_sig_cseq_ST_st171_fsm_170_assign_proc : process(ap_sig_bdd_1202)
begin
if (ap_sig_bdd_1202) then
ap_sig_cseq_ST_st171_fsm_170 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st171_fsm_170 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st172_fsm_171 assign process. --
ap_sig_cseq_ST_st172_fsm_171_assign_proc : process(ap_sig_bdd_1346)
begin
if (ap_sig_bdd_1346) then
ap_sig_cseq_ST_st172_fsm_171 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st172_fsm_171 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st173_fsm_172 assign process. --
ap_sig_cseq_ST_st173_fsm_172_assign_proc : process(ap_sig_bdd_1490)
begin
if (ap_sig_bdd_1490) then
ap_sig_cseq_ST_st173_fsm_172 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st173_fsm_172 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st174_fsm_173 assign process. --
ap_sig_cseq_ST_st174_fsm_173_assign_proc : process(ap_sig_bdd_1634)
begin
if (ap_sig_bdd_1634) then
ap_sig_cseq_ST_st174_fsm_173 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st174_fsm_173 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st175_fsm_174 assign process. --
ap_sig_cseq_ST_st175_fsm_174_assign_proc : process(ap_sig_bdd_1778)
begin
if (ap_sig_bdd_1778) then
ap_sig_cseq_ST_st175_fsm_174 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st175_fsm_174 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st176_fsm_175 assign process. --
ap_sig_cseq_ST_st176_fsm_175_assign_proc : process(ap_sig_bdd_1922)
begin
if (ap_sig_bdd_1922) then
ap_sig_cseq_ST_st176_fsm_175 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st176_fsm_175 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st177_fsm_176 assign process. --
ap_sig_cseq_ST_st177_fsm_176_assign_proc : process(ap_sig_bdd_2066)
begin
if (ap_sig_bdd_2066) then
ap_sig_cseq_ST_st177_fsm_176 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st177_fsm_176 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st178_fsm_177 assign process. --
ap_sig_cseq_ST_st178_fsm_177_assign_proc : process(ap_sig_bdd_2210)
begin
if (ap_sig_bdd_2210) then
ap_sig_cseq_ST_st178_fsm_177 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st178_fsm_177 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st179_fsm_178 assign process. --
ap_sig_cseq_ST_st179_fsm_178_assign_proc : process(ap_sig_bdd_2354)
begin
if (ap_sig_bdd_2354) then
ap_sig_cseq_ST_st179_fsm_178 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st179_fsm_178 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_2911)
begin
if (ap_sig_bdd_2911) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st180_fsm_179 assign process. --
ap_sig_cseq_ST_st180_fsm_179_assign_proc : process(ap_sig_bdd_3497)
begin
if (ap_sig_bdd_3497) then
ap_sig_cseq_ST_st180_fsm_179 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st180_fsm_179 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st181_fsm_180 assign process. --
ap_sig_cseq_ST_st181_fsm_180_assign_proc : process(ap_sig_bdd_482)
begin
if (ap_sig_bdd_482) then
ap_sig_cseq_ST_st181_fsm_180 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st181_fsm_180 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st182_fsm_181 assign process. --
ap_sig_cseq_ST_st182_fsm_181_assign_proc : process(ap_sig_bdd_635)
begin
if (ap_sig_bdd_635) then
ap_sig_cseq_ST_st182_fsm_181 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st182_fsm_181 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st183_fsm_182 assign process. --
ap_sig_cseq_ST_st183_fsm_182_assign_proc : process(ap_sig_bdd_779)
begin
if (ap_sig_bdd_779) then
ap_sig_cseq_ST_st183_fsm_182 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st183_fsm_182 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st184_fsm_183 assign process. --
ap_sig_cseq_ST_st184_fsm_183_assign_proc : process(ap_sig_bdd_923)
begin
if (ap_sig_bdd_923) then
ap_sig_cseq_ST_st184_fsm_183 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st184_fsm_183 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st185_fsm_184 assign process. --
ap_sig_cseq_ST_st185_fsm_184_assign_proc : process(ap_sig_bdd_1067)
begin
if (ap_sig_bdd_1067) then
ap_sig_cseq_ST_st185_fsm_184 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st185_fsm_184 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st186_fsm_185 assign process. --
ap_sig_cseq_ST_st186_fsm_185_assign_proc : process(ap_sig_bdd_1211)
begin
if (ap_sig_bdd_1211) then
ap_sig_cseq_ST_st186_fsm_185 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st186_fsm_185 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st187_fsm_186 assign process. --
ap_sig_cseq_ST_st187_fsm_186_assign_proc : process(ap_sig_bdd_1355)
begin
if (ap_sig_bdd_1355) then
ap_sig_cseq_ST_st187_fsm_186 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st187_fsm_186 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st188_fsm_187 assign process. --
ap_sig_cseq_ST_st188_fsm_187_assign_proc : process(ap_sig_bdd_1499)
begin
if (ap_sig_bdd_1499) then
ap_sig_cseq_ST_st188_fsm_187 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st188_fsm_187 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st189_fsm_188 assign process. --
ap_sig_cseq_ST_st189_fsm_188_assign_proc : process(ap_sig_bdd_1643)
begin
if (ap_sig_bdd_1643) then
ap_sig_cseq_ST_st189_fsm_188 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st189_fsm_188 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_2920)
begin
if (ap_sig_bdd_2920) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st190_fsm_189 assign process. --
ap_sig_cseq_ST_st190_fsm_189_assign_proc : process(ap_sig_bdd_1787)
begin
if (ap_sig_bdd_1787) then
ap_sig_cseq_ST_st190_fsm_189 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st190_fsm_189 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st191_fsm_190 assign process. --
ap_sig_cseq_ST_st191_fsm_190_assign_proc : process(ap_sig_bdd_1931)
begin
if (ap_sig_bdd_1931) then
ap_sig_cseq_ST_st191_fsm_190 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st191_fsm_190 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st192_fsm_191 assign process. --
ap_sig_cseq_ST_st192_fsm_191_assign_proc : process(ap_sig_bdd_2075)
begin
if (ap_sig_bdd_2075) then
ap_sig_cseq_ST_st192_fsm_191 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st192_fsm_191 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st193_fsm_192 assign process. --
ap_sig_cseq_ST_st193_fsm_192_assign_proc : process(ap_sig_bdd_2219)
begin
if (ap_sig_bdd_2219) then
ap_sig_cseq_ST_st193_fsm_192 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st193_fsm_192 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st194_fsm_193 assign process. --
ap_sig_cseq_ST_st194_fsm_193_assign_proc : process(ap_sig_bdd_2363)
begin
if (ap_sig_bdd_2363) then
ap_sig_cseq_ST_st194_fsm_193 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st194_fsm_193 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st195_fsm_194 assign process. --
ap_sig_cseq_ST_st195_fsm_194_assign_proc : process(ap_sig_bdd_3507)
begin
if (ap_sig_bdd_3507) then
ap_sig_cseq_ST_st195_fsm_194 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st195_fsm_194 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st196_fsm_195 assign process. --
ap_sig_cseq_ST_st196_fsm_195_assign_proc : process(ap_sig_bdd_491)
begin
if (ap_sig_bdd_491) then
ap_sig_cseq_ST_st196_fsm_195 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st196_fsm_195 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st197_fsm_196 assign process. --
ap_sig_cseq_ST_st197_fsm_196_assign_proc : process(ap_sig_bdd_644)
begin
if (ap_sig_bdd_644) then
ap_sig_cseq_ST_st197_fsm_196 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st197_fsm_196 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st198_fsm_197 assign process. --
ap_sig_cseq_ST_st198_fsm_197_assign_proc : process(ap_sig_bdd_788)
begin
if (ap_sig_bdd_788) then
ap_sig_cseq_ST_st198_fsm_197 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st198_fsm_197 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st199_fsm_198 assign process. --
ap_sig_cseq_ST_st199_fsm_198_assign_proc : process(ap_sig_bdd_932)
begin
if (ap_sig_bdd_932) then
ap_sig_cseq_ST_st199_fsm_198 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st199_fsm_198 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_2929)
begin
if (ap_sig_bdd_2929) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_399)
begin
if (ap_sig_bdd_399) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st200_fsm_199 assign process. --
ap_sig_cseq_ST_st200_fsm_199_assign_proc : process(ap_sig_bdd_1076)
begin
if (ap_sig_bdd_1076) then
ap_sig_cseq_ST_st200_fsm_199 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st200_fsm_199 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st201_fsm_200 assign process. --
ap_sig_cseq_ST_st201_fsm_200_assign_proc : process(ap_sig_bdd_1220)
begin
if (ap_sig_bdd_1220) then
ap_sig_cseq_ST_st201_fsm_200 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st201_fsm_200 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st202_fsm_201 assign process. --
ap_sig_cseq_ST_st202_fsm_201_assign_proc : process(ap_sig_bdd_1364)
begin
if (ap_sig_bdd_1364) then
ap_sig_cseq_ST_st202_fsm_201 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st202_fsm_201 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st203_fsm_202 assign process. --
ap_sig_cseq_ST_st203_fsm_202_assign_proc : process(ap_sig_bdd_1508)
begin
if (ap_sig_bdd_1508) then
ap_sig_cseq_ST_st203_fsm_202 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st203_fsm_202 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st204_fsm_203 assign process. --
ap_sig_cseq_ST_st204_fsm_203_assign_proc : process(ap_sig_bdd_1652)
begin
if (ap_sig_bdd_1652) then
ap_sig_cseq_ST_st204_fsm_203 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st204_fsm_203 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st205_fsm_204 assign process. --
ap_sig_cseq_ST_st205_fsm_204_assign_proc : process(ap_sig_bdd_1796)
begin
if (ap_sig_bdd_1796) then
ap_sig_cseq_ST_st205_fsm_204 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st205_fsm_204 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st206_fsm_205 assign process. --
ap_sig_cseq_ST_st206_fsm_205_assign_proc : process(ap_sig_bdd_1940)
begin
if (ap_sig_bdd_1940) then
ap_sig_cseq_ST_st206_fsm_205 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st206_fsm_205 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st207_fsm_206 assign process. --
ap_sig_cseq_ST_st207_fsm_206_assign_proc : process(ap_sig_bdd_2084)
begin
if (ap_sig_bdd_2084) then
ap_sig_cseq_ST_st207_fsm_206 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st207_fsm_206 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st208_fsm_207 assign process. --
ap_sig_cseq_ST_st208_fsm_207_assign_proc : process(ap_sig_bdd_2228)
begin
if (ap_sig_bdd_2228) then
ap_sig_cseq_ST_st208_fsm_207 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st208_fsm_207 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st209_fsm_208 assign process. --
ap_sig_cseq_ST_st209_fsm_208_assign_proc : process(ap_sig_bdd_2372)
begin
if (ap_sig_bdd_2372) then
ap_sig_cseq_ST_st209_fsm_208 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st209_fsm_208 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_2938)
begin
if (ap_sig_bdd_2938) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st210_fsm_209 assign process. --
ap_sig_cseq_ST_st210_fsm_209_assign_proc : process(ap_sig_bdd_3517)
begin
if (ap_sig_bdd_3517) then
ap_sig_cseq_ST_st210_fsm_209 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st210_fsm_209 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st211_fsm_210 assign process. --
ap_sig_cseq_ST_st211_fsm_210_assign_proc : process(ap_sig_bdd_500)
begin
if (ap_sig_bdd_500) then
ap_sig_cseq_ST_st211_fsm_210 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st211_fsm_210 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st212_fsm_211 assign process. --
ap_sig_cseq_ST_st212_fsm_211_assign_proc : process(ap_sig_bdd_653)
begin
if (ap_sig_bdd_653) then
ap_sig_cseq_ST_st212_fsm_211 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st212_fsm_211 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st213_fsm_212 assign process. --
ap_sig_cseq_ST_st213_fsm_212_assign_proc : process(ap_sig_bdd_797)
begin
if (ap_sig_bdd_797) then
ap_sig_cseq_ST_st213_fsm_212 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st213_fsm_212 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st214_fsm_213 assign process. --
ap_sig_cseq_ST_st214_fsm_213_assign_proc : process(ap_sig_bdd_941)
begin
if (ap_sig_bdd_941) then
ap_sig_cseq_ST_st214_fsm_213 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st214_fsm_213 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st215_fsm_214 assign process. --
ap_sig_cseq_ST_st215_fsm_214_assign_proc : process(ap_sig_bdd_1085)
begin
if (ap_sig_bdd_1085) then
ap_sig_cseq_ST_st215_fsm_214 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st215_fsm_214 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st216_fsm_215 assign process. --
ap_sig_cseq_ST_st216_fsm_215_assign_proc : process(ap_sig_bdd_1229)
begin
if (ap_sig_bdd_1229) then
ap_sig_cseq_ST_st216_fsm_215 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st216_fsm_215 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st217_fsm_216 assign process. --
ap_sig_cseq_ST_st217_fsm_216_assign_proc : process(ap_sig_bdd_1373)
begin
if (ap_sig_bdd_1373) then
ap_sig_cseq_ST_st217_fsm_216 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st217_fsm_216 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st218_fsm_217 assign process. --
ap_sig_cseq_ST_st218_fsm_217_assign_proc : process(ap_sig_bdd_1517)
begin
if (ap_sig_bdd_1517) then
ap_sig_cseq_ST_st218_fsm_217 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st218_fsm_217 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st219_fsm_218 assign process. --
ap_sig_cseq_ST_st219_fsm_218_assign_proc : process(ap_sig_bdd_1661)
begin
if (ap_sig_bdd_1661) then
ap_sig_cseq_ST_st219_fsm_218 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st219_fsm_218 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_2947)
begin
if (ap_sig_bdd_2947) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st220_fsm_219 assign process. --
ap_sig_cseq_ST_st220_fsm_219_assign_proc : process(ap_sig_bdd_1805)
begin
if (ap_sig_bdd_1805) then
ap_sig_cseq_ST_st220_fsm_219 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st220_fsm_219 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st221_fsm_220 assign process. --
ap_sig_cseq_ST_st221_fsm_220_assign_proc : process(ap_sig_bdd_1949)
begin
if (ap_sig_bdd_1949) then
ap_sig_cseq_ST_st221_fsm_220 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st221_fsm_220 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st222_fsm_221 assign process. --
ap_sig_cseq_ST_st222_fsm_221_assign_proc : process(ap_sig_bdd_2093)
begin
if (ap_sig_bdd_2093) then
ap_sig_cseq_ST_st222_fsm_221 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st222_fsm_221 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st223_fsm_222 assign process. --
ap_sig_cseq_ST_st223_fsm_222_assign_proc : process(ap_sig_bdd_2237)
begin
if (ap_sig_bdd_2237) then
ap_sig_cseq_ST_st223_fsm_222 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st223_fsm_222 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st224_fsm_223 assign process. --
ap_sig_cseq_ST_st224_fsm_223_assign_proc : process(ap_sig_bdd_2381)
begin
if (ap_sig_bdd_2381) then
ap_sig_cseq_ST_st224_fsm_223 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st224_fsm_223 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st225_fsm_224 assign process. --
ap_sig_cseq_ST_st225_fsm_224_assign_proc : process(ap_sig_bdd_3527)
begin
if (ap_sig_bdd_3527) then
ap_sig_cseq_ST_st225_fsm_224 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st225_fsm_224 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st226_fsm_225 assign process. --
ap_sig_cseq_ST_st226_fsm_225_assign_proc : process(ap_sig_bdd_509)
begin
if (ap_sig_bdd_509) then
ap_sig_cseq_ST_st226_fsm_225 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st226_fsm_225 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st227_fsm_226 assign process. --
ap_sig_cseq_ST_st227_fsm_226_assign_proc : process(ap_sig_bdd_662)
begin
if (ap_sig_bdd_662) then
ap_sig_cseq_ST_st227_fsm_226 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st227_fsm_226 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st228_fsm_227 assign process. --
ap_sig_cseq_ST_st228_fsm_227_assign_proc : process(ap_sig_bdd_806)
begin
if (ap_sig_bdd_806) then
ap_sig_cseq_ST_st228_fsm_227 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st228_fsm_227 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st229_fsm_228 assign process. --
ap_sig_cseq_ST_st229_fsm_228_assign_proc : process(ap_sig_bdd_950)
begin
if (ap_sig_bdd_950) then
ap_sig_cseq_ST_st229_fsm_228 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st229_fsm_228 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_2956)
begin
if (ap_sig_bdd_2956) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st230_fsm_229 assign process. --
ap_sig_cseq_ST_st230_fsm_229_assign_proc : process(ap_sig_bdd_1094)
begin
if (ap_sig_bdd_1094) then
ap_sig_cseq_ST_st230_fsm_229 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st230_fsm_229 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st231_fsm_230 assign process. --
ap_sig_cseq_ST_st231_fsm_230_assign_proc : process(ap_sig_bdd_1238)
begin
if (ap_sig_bdd_1238) then
ap_sig_cseq_ST_st231_fsm_230 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st231_fsm_230 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st232_fsm_231 assign process. --
ap_sig_cseq_ST_st232_fsm_231_assign_proc : process(ap_sig_bdd_1382)
begin
if (ap_sig_bdd_1382) then
ap_sig_cseq_ST_st232_fsm_231 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st232_fsm_231 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st233_fsm_232 assign process. --
ap_sig_cseq_ST_st233_fsm_232_assign_proc : process(ap_sig_bdd_1526)
begin
if (ap_sig_bdd_1526) then
ap_sig_cseq_ST_st233_fsm_232 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st233_fsm_232 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st234_fsm_233 assign process. --
ap_sig_cseq_ST_st234_fsm_233_assign_proc : process(ap_sig_bdd_1670)
begin
if (ap_sig_bdd_1670) then
ap_sig_cseq_ST_st234_fsm_233 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st234_fsm_233 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st235_fsm_234 assign process. --
ap_sig_cseq_ST_st235_fsm_234_assign_proc : process(ap_sig_bdd_1814)
begin
if (ap_sig_bdd_1814) then
ap_sig_cseq_ST_st235_fsm_234 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st235_fsm_234 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st236_fsm_235 assign process. --
ap_sig_cseq_ST_st236_fsm_235_assign_proc : process(ap_sig_bdd_1958)
begin
if (ap_sig_bdd_1958) then
ap_sig_cseq_ST_st236_fsm_235 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st236_fsm_235 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st237_fsm_236 assign process. --
ap_sig_cseq_ST_st237_fsm_236_assign_proc : process(ap_sig_bdd_2102)
begin
if (ap_sig_bdd_2102) then
ap_sig_cseq_ST_st237_fsm_236 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st237_fsm_236 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st238_fsm_237 assign process. --
ap_sig_cseq_ST_st238_fsm_237_assign_proc : process(ap_sig_bdd_2246)
begin
if (ap_sig_bdd_2246) then
ap_sig_cseq_ST_st238_fsm_237 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st238_fsm_237 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st239_fsm_238 assign process. --
ap_sig_cseq_ST_st239_fsm_238_assign_proc : process(ap_sig_bdd_2390)
begin
if (ap_sig_bdd_2390) then
ap_sig_cseq_ST_st239_fsm_238 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st239_fsm_238 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_2965)
begin
if (ap_sig_bdd_2965) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st240_fsm_239 assign process. --
ap_sig_cseq_ST_st240_fsm_239_assign_proc : process(ap_sig_bdd_3537)
begin
if (ap_sig_bdd_3537) then
ap_sig_cseq_ST_st240_fsm_239 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st240_fsm_239 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st241_fsm_240 assign process. --
ap_sig_cseq_ST_st241_fsm_240_assign_proc : process(ap_sig_bdd_518)
begin
if (ap_sig_bdd_518) then
ap_sig_cseq_ST_st241_fsm_240 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st241_fsm_240 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st242_fsm_241 assign process. --
ap_sig_cseq_ST_st242_fsm_241_assign_proc : process(ap_sig_bdd_671)
begin
if (ap_sig_bdd_671) then
ap_sig_cseq_ST_st242_fsm_241 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st242_fsm_241 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st243_fsm_242 assign process. --
ap_sig_cseq_ST_st243_fsm_242_assign_proc : process(ap_sig_bdd_815)
begin
if (ap_sig_bdd_815) then
ap_sig_cseq_ST_st243_fsm_242 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st243_fsm_242 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st244_fsm_243 assign process. --
ap_sig_cseq_ST_st244_fsm_243_assign_proc : process(ap_sig_bdd_959)
begin
if (ap_sig_bdd_959) then
ap_sig_cseq_ST_st244_fsm_243 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st244_fsm_243 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st245_fsm_244 assign process. --
ap_sig_cseq_ST_st245_fsm_244_assign_proc : process(ap_sig_bdd_1103)
begin
if (ap_sig_bdd_1103) then
ap_sig_cseq_ST_st245_fsm_244 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st245_fsm_244 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st246_fsm_245 assign process. --
ap_sig_cseq_ST_st246_fsm_245_assign_proc : process(ap_sig_bdd_1247)
begin
if (ap_sig_bdd_1247) then
ap_sig_cseq_ST_st246_fsm_245 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st246_fsm_245 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st247_fsm_246 assign process. --
ap_sig_cseq_ST_st247_fsm_246_assign_proc : process(ap_sig_bdd_1391)
begin
if (ap_sig_bdd_1391) then
ap_sig_cseq_ST_st247_fsm_246 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st247_fsm_246 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st248_fsm_247 assign process. --
ap_sig_cseq_ST_st248_fsm_247_assign_proc : process(ap_sig_bdd_1535)
begin
if (ap_sig_bdd_1535) then
ap_sig_cseq_ST_st248_fsm_247 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st248_fsm_247 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st249_fsm_248 assign process. --
ap_sig_cseq_ST_st249_fsm_248_assign_proc : process(ap_sig_bdd_1679)
begin
if (ap_sig_bdd_1679) then
ap_sig_cseq_ST_st249_fsm_248 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st249_fsm_248 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_2974)
begin
if (ap_sig_bdd_2974) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st250_fsm_249 assign process. --
ap_sig_cseq_ST_st250_fsm_249_assign_proc : process(ap_sig_bdd_1823)
begin
if (ap_sig_bdd_1823) then
ap_sig_cseq_ST_st250_fsm_249 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st250_fsm_249 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st251_fsm_250 assign process. --
ap_sig_cseq_ST_st251_fsm_250_assign_proc : process(ap_sig_bdd_1967)
begin
if (ap_sig_bdd_1967) then
ap_sig_cseq_ST_st251_fsm_250 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st251_fsm_250 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st252_fsm_251 assign process. --
ap_sig_cseq_ST_st252_fsm_251_assign_proc : process(ap_sig_bdd_2111)
begin
if (ap_sig_bdd_2111) then
ap_sig_cseq_ST_st252_fsm_251 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st252_fsm_251 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st253_fsm_252 assign process. --
ap_sig_cseq_ST_st253_fsm_252_assign_proc : process(ap_sig_bdd_2255)
begin
if (ap_sig_bdd_2255) then
ap_sig_cseq_ST_st253_fsm_252 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st253_fsm_252 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st254_fsm_253 assign process. --
ap_sig_cseq_ST_st254_fsm_253_assign_proc : process(ap_sig_bdd_2399)
begin
if (ap_sig_bdd_2399) then
ap_sig_cseq_ST_st254_fsm_253 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st254_fsm_253 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st255_fsm_254 assign process. --
ap_sig_cseq_ST_st255_fsm_254_assign_proc : process(ap_sig_bdd_5023)
begin
if (ap_sig_bdd_5023) then
ap_sig_cseq_ST_st255_fsm_254 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st255_fsm_254 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st256_fsm_255 assign process. --
ap_sig_cseq_ST_st256_fsm_255_assign_proc : process(ap_sig_bdd_527)
begin
if (ap_sig_bdd_527) then
ap_sig_cseq_ST_st256_fsm_255 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st256_fsm_255 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st257_fsm_256 assign process. --
ap_sig_cseq_ST_st257_fsm_256_assign_proc : process(ap_sig_bdd_680)
begin
if (ap_sig_bdd_680) then
ap_sig_cseq_ST_st257_fsm_256 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st257_fsm_256 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st258_fsm_257 assign process. --
ap_sig_cseq_ST_st258_fsm_257_assign_proc : process(ap_sig_bdd_824)
begin
if (ap_sig_bdd_824) then
ap_sig_cseq_ST_st258_fsm_257 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st258_fsm_257 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st259_fsm_258 assign process. --
ap_sig_cseq_ST_st259_fsm_258_assign_proc : process(ap_sig_bdd_968)
begin
if (ap_sig_bdd_968) then
ap_sig_cseq_ST_st259_fsm_258 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st259_fsm_258 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_2983)
begin
if (ap_sig_bdd_2983) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st260_fsm_259 assign process. --
ap_sig_cseq_ST_st260_fsm_259_assign_proc : process(ap_sig_bdd_1112)
begin
if (ap_sig_bdd_1112) then
ap_sig_cseq_ST_st260_fsm_259 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st260_fsm_259 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st261_fsm_260 assign process. --
ap_sig_cseq_ST_st261_fsm_260_assign_proc : process(ap_sig_bdd_1256)
begin
if (ap_sig_bdd_1256) then
ap_sig_cseq_ST_st261_fsm_260 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st261_fsm_260 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st262_fsm_261 assign process. --
ap_sig_cseq_ST_st262_fsm_261_assign_proc : process(ap_sig_bdd_1400)
begin
if (ap_sig_bdd_1400) then
ap_sig_cseq_ST_st262_fsm_261 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st262_fsm_261 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st263_fsm_262 assign process. --
ap_sig_cseq_ST_st263_fsm_262_assign_proc : process(ap_sig_bdd_1544)
begin
if (ap_sig_bdd_1544) then
ap_sig_cseq_ST_st263_fsm_262 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st263_fsm_262 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st264_fsm_263 assign process. --
ap_sig_cseq_ST_st264_fsm_263_assign_proc : process(ap_sig_bdd_1688)
begin
if (ap_sig_bdd_1688) then
ap_sig_cseq_ST_st264_fsm_263 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st264_fsm_263 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st265_fsm_264 assign process. --
ap_sig_cseq_ST_st265_fsm_264_assign_proc : process(ap_sig_bdd_1832)
begin
if (ap_sig_bdd_1832) then
ap_sig_cseq_ST_st265_fsm_264 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st265_fsm_264 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st266_fsm_265 assign process. --
ap_sig_cseq_ST_st266_fsm_265_assign_proc : process(ap_sig_bdd_1976)
begin
if (ap_sig_bdd_1976) then
ap_sig_cseq_ST_st266_fsm_265 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st266_fsm_265 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st267_fsm_266 assign process. --
ap_sig_cseq_ST_st267_fsm_266_assign_proc : process(ap_sig_bdd_2120)
begin
if (ap_sig_bdd_2120) then
ap_sig_cseq_ST_st267_fsm_266 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st267_fsm_266 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st268_fsm_267 assign process. --
ap_sig_cseq_ST_st268_fsm_267_assign_proc : process(ap_sig_bdd_2264)
begin
if (ap_sig_bdd_2264) then
ap_sig_cseq_ST_st268_fsm_267 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st268_fsm_267 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st269_fsm_268 assign process. --
ap_sig_cseq_ST_st269_fsm_268_assign_proc : process(ap_sig_bdd_2408)
begin
if (ap_sig_bdd_2408) then
ap_sig_cseq_ST_st269_fsm_268 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st269_fsm_268 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st26_fsm_25 assign process. --
ap_sig_cseq_ST_st26_fsm_25_assign_proc : process(ap_sig_bdd_2992)
begin
if (ap_sig_bdd_2992) then
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st270_fsm_269 assign process. --
ap_sig_cseq_ST_st270_fsm_269_assign_proc : process(ap_sig_bdd_5046)
begin
if (ap_sig_bdd_5046) then
ap_sig_cseq_ST_st270_fsm_269 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st270_fsm_269 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st271_fsm_270 assign process. --
ap_sig_cseq_ST_st271_fsm_270_assign_proc : process(ap_sig_bdd_536)
begin
if (ap_sig_bdd_536) then
ap_sig_cseq_ST_st271_fsm_270 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st271_fsm_270 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st272_fsm_271 assign process. --
ap_sig_cseq_ST_st272_fsm_271_assign_proc : process(ap_sig_bdd_689)
begin
if (ap_sig_bdd_689) then
ap_sig_cseq_ST_st272_fsm_271 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st272_fsm_271 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st273_fsm_272 assign process. --
ap_sig_cseq_ST_st273_fsm_272_assign_proc : process(ap_sig_bdd_833)
begin
if (ap_sig_bdd_833) then
ap_sig_cseq_ST_st273_fsm_272 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st273_fsm_272 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st274_fsm_273 assign process. --
ap_sig_cseq_ST_st274_fsm_273_assign_proc : process(ap_sig_bdd_977)
begin
if (ap_sig_bdd_977) then
ap_sig_cseq_ST_st274_fsm_273 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st274_fsm_273 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st275_fsm_274 assign process. --
ap_sig_cseq_ST_st275_fsm_274_assign_proc : process(ap_sig_bdd_1121)
begin
if (ap_sig_bdd_1121) then
ap_sig_cseq_ST_st275_fsm_274 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st275_fsm_274 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st276_fsm_275 assign process. --
ap_sig_cseq_ST_st276_fsm_275_assign_proc : process(ap_sig_bdd_1265)
begin
if (ap_sig_bdd_1265) then
ap_sig_cseq_ST_st276_fsm_275 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st276_fsm_275 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st277_fsm_276 assign process. --
ap_sig_cseq_ST_st277_fsm_276_assign_proc : process(ap_sig_bdd_1409)
begin
if (ap_sig_bdd_1409) then
ap_sig_cseq_ST_st277_fsm_276 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st277_fsm_276 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st278_fsm_277 assign process. --
ap_sig_cseq_ST_st278_fsm_277_assign_proc : process(ap_sig_bdd_1553)
begin
if (ap_sig_bdd_1553) then
ap_sig_cseq_ST_st278_fsm_277 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st278_fsm_277 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st279_fsm_278 assign process. --
ap_sig_cseq_ST_st279_fsm_278_assign_proc : process(ap_sig_bdd_1697)
begin
if (ap_sig_bdd_1697) then
ap_sig_cseq_ST_st279_fsm_278 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st279_fsm_278 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st27_fsm_26 assign process. --
ap_sig_cseq_ST_st27_fsm_26_assign_proc : process(ap_sig_bdd_3001)
begin
if (ap_sig_bdd_3001) then
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st280_fsm_279 assign process. --
ap_sig_cseq_ST_st280_fsm_279_assign_proc : process(ap_sig_bdd_1841)
begin
if (ap_sig_bdd_1841) then
ap_sig_cseq_ST_st280_fsm_279 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st280_fsm_279 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st281_fsm_280 assign process. --
ap_sig_cseq_ST_st281_fsm_280_assign_proc : process(ap_sig_bdd_1985)
begin
if (ap_sig_bdd_1985) then
ap_sig_cseq_ST_st281_fsm_280 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st281_fsm_280 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st282_fsm_281 assign process. --
ap_sig_cseq_ST_st282_fsm_281_assign_proc : process(ap_sig_bdd_2129)
begin
if (ap_sig_bdd_2129) then
ap_sig_cseq_ST_st282_fsm_281 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st282_fsm_281 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st283_fsm_282 assign process. --
ap_sig_cseq_ST_st283_fsm_282_assign_proc : process(ap_sig_bdd_2273)
begin
if (ap_sig_bdd_2273) then
ap_sig_cseq_ST_st283_fsm_282 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st283_fsm_282 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st284_fsm_283 assign process. --
ap_sig_cseq_ST_st284_fsm_283_assign_proc : process(ap_sig_bdd_2417)
begin
if (ap_sig_bdd_2417) then
ap_sig_cseq_ST_st284_fsm_283 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st284_fsm_283 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st285_fsm_284 assign process. --
ap_sig_cseq_ST_st285_fsm_284_assign_proc : process(ap_sig_bdd_5069)
begin
if (ap_sig_bdd_5069) then
ap_sig_cseq_ST_st285_fsm_284 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st285_fsm_284 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st286_fsm_285 assign process. --
ap_sig_cseq_ST_st286_fsm_285_assign_proc : process(ap_sig_bdd_545)
begin
if (ap_sig_bdd_545) then
ap_sig_cseq_ST_st286_fsm_285 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st286_fsm_285 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st287_fsm_286 assign process. --
ap_sig_cseq_ST_st287_fsm_286_assign_proc : process(ap_sig_bdd_698)
begin
if (ap_sig_bdd_698) then
ap_sig_cseq_ST_st287_fsm_286 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st287_fsm_286 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st288_fsm_287 assign process. --
ap_sig_cseq_ST_st288_fsm_287_assign_proc : process(ap_sig_bdd_842)
begin
if (ap_sig_bdd_842) then
ap_sig_cseq_ST_st288_fsm_287 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st288_fsm_287 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st289_fsm_288 assign process. --
ap_sig_cseq_ST_st289_fsm_288_assign_proc : process(ap_sig_bdd_986)
begin
if (ap_sig_bdd_986) then
ap_sig_cseq_ST_st289_fsm_288 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st289_fsm_288 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st28_fsm_27 assign process. --
ap_sig_cseq_ST_st28_fsm_27_assign_proc : process(ap_sig_bdd_3010)
begin
if (ap_sig_bdd_3010) then
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st290_fsm_289 assign process. --
ap_sig_cseq_ST_st290_fsm_289_assign_proc : process(ap_sig_bdd_1130)
begin
if (ap_sig_bdd_1130) then
ap_sig_cseq_ST_st290_fsm_289 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st290_fsm_289 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st291_fsm_290 assign process. --
ap_sig_cseq_ST_st291_fsm_290_assign_proc : process(ap_sig_bdd_1274)
begin
if (ap_sig_bdd_1274) then
ap_sig_cseq_ST_st291_fsm_290 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st291_fsm_290 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st292_fsm_291 assign process. --
ap_sig_cseq_ST_st292_fsm_291_assign_proc : process(ap_sig_bdd_1418)
begin
if (ap_sig_bdd_1418) then
ap_sig_cseq_ST_st292_fsm_291 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st292_fsm_291 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st293_fsm_292 assign process. --
ap_sig_cseq_ST_st293_fsm_292_assign_proc : process(ap_sig_bdd_1562)
begin
if (ap_sig_bdd_1562) then
ap_sig_cseq_ST_st293_fsm_292 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st293_fsm_292 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st294_fsm_293 assign process. --
ap_sig_cseq_ST_st294_fsm_293_assign_proc : process(ap_sig_bdd_1706)
begin
if (ap_sig_bdd_1706) then
ap_sig_cseq_ST_st294_fsm_293 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st294_fsm_293 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st295_fsm_294 assign process. --
ap_sig_cseq_ST_st295_fsm_294_assign_proc : process(ap_sig_bdd_1850)
begin
if (ap_sig_bdd_1850) then
ap_sig_cseq_ST_st295_fsm_294 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st295_fsm_294 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st296_fsm_295 assign process. --
ap_sig_cseq_ST_st296_fsm_295_assign_proc : process(ap_sig_bdd_1994)
begin
if (ap_sig_bdd_1994) then
ap_sig_cseq_ST_st296_fsm_295 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st296_fsm_295 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st297_fsm_296 assign process. --
ap_sig_cseq_ST_st297_fsm_296_assign_proc : process(ap_sig_bdd_2138)
begin
if (ap_sig_bdd_2138) then
ap_sig_cseq_ST_st297_fsm_296 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st297_fsm_296 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st298_fsm_297 assign process. --
ap_sig_cseq_ST_st298_fsm_297_assign_proc : process(ap_sig_bdd_2282)
begin
if (ap_sig_bdd_2282) then
ap_sig_cseq_ST_st298_fsm_297 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st298_fsm_297 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st299_fsm_298 assign process. --
ap_sig_cseq_ST_st299_fsm_298_assign_proc : process(ap_sig_bdd_2426)
begin
if (ap_sig_bdd_2426) then
ap_sig_cseq_ST_st299_fsm_298 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st299_fsm_298 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_3019)
begin
if (ap_sig_bdd_3019) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_555)
begin
if (ap_sig_bdd_555) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st300_fsm_299 assign process. --
ap_sig_cseq_ST_st300_fsm_299_assign_proc : process(ap_sig_bdd_3547)
begin
if (ap_sig_bdd_3547) then
ap_sig_cseq_ST_st300_fsm_299 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st300_fsm_299 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_3028)
begin
if (ap_sig_bdd_3028) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st31_fsm_30 assign process. --
ap_sig_cseq_ST_st31_fsm_30_assign_proc : process(ap_sig_bdd_3037)
begin
if (ap_sig_bdd_3037) then
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st31_fsm_30 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st32_fsm_31 assign process. --
ap_sig_cseq_ST_st32_fsm_31_assign_proc : process(ap_sig_bdd_3046)
begin
if (ap_sig_bdd_3046) then
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st32_fsm_31 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st33_fsm_32 assign process. --
ap_sig_cseq_ST_st33_fsm_32_assign_proc : process(ap_sig_bdd_3055)
begin
if (ap_sig_bdd_3055) then
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st33_fsm_32 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st34_fsm_33 assign process. --
ap_sig_cseq_ST_st34_fsm_33_assign_proc : process(ap_sig_bdd_3064)
begin
if (ap_sig_bdd_3064) then
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st34_fsm_33 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st35_fsm_34 assign process. --
ap_sig_cseq_ST_st35_fsm_34_assign_proc : process(ap_sig_bdd_3073)
begin
if (ap_sig_bdd_3073) then
ap_sig_cseq_ST_st35_fsm_34 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st35_fsm_34 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st36_fsm_35 assign process. --
ap_sig_cseq_ST_st36_fsm_35_assign_proc : process(ap_sig_bdd_3082)
begin
if (ap_sig_bdd_3082) then
ap_sig_cseq_ST_st36_fsm_35 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st36_fsm_35 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st37_fsm_36 assign process. --
ap_sig_cseq_ST_st37_fsm_36_assign_proc : process(ap_sig_bdd_3091)
begin
if (ap_sig_bdd_3091) then
ap_sig_cseq_ST_st37_fsm_36 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st37_fsm_36 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st385_fsm_301 assign process. --
ap_sig_cseq_ST_st385_fsm_301_assign_proc : process(ap_sig_bdd_5902)
begin
if (ap_sig_bdd_5902) then
ap_sig_cseq_ST_st385_fsm_301 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st385_fsm_301 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st386_fsm_302 assign process. --
ap_sig_cseq_ST_st386_fsm_302_assign_proc : process(ap_sig_bdd_2708)
begin
if (ap_sig_bdd_2708) then
ap_sig_cseq_ST_st386_fsm_302 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st386_fsm_302 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st387_fsm_303 assign process. --
ap_sig_cseq_ST_st387_fsm_303_assign_proc : process(ap_sig_bdd_5096)
begin
if (ap_sig_bdd_5096) then
ap_sig_cseq_ST_st387_fsm_303 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st387_fsm_303 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st388_fsm_304 assign process. --
ap_sig_cseq_ST_st388_fsm_304_assign_proc : process(ap_sig_bdd_5104)
begin
if (ap_sig_bdd_5104) then
ap_sig_cseq_ST_st388_fsm_304 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st388_fsm_304 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st389_fsm_305 assign process. --
ap_sig_cseq_ST_st389_fsm_305_assign_proc : process(ap_sig_bdd_2719)
begin
if (ap_sig_bdd_2719) then
ap_sig_cseq_ST_st389_fsm_305 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st389_fsm_305 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st38_fsm_37 assign process. --
ap_sig_cseq_ST_st38_fsm_37_assign_proc : process(ap_sig_bdd_3100)
begin
if (ap_sig_bdd_3100) then
ap_sig_cseq_ST_st38_fsm_37 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st38_fsm_37 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st390_fsm_306 assign process. --
ap_sig_cseq_ST_st390_fsm_306_assign_proc : process(ap_sig_bdd_5113)
begin
if (ap_sig_bdd_5113) then
ap_sig_cseq_ST_st390_fsm_306 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st390_fsm_306 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st391_fsm_307 assign process. --
ap_sig_cseq_ST_st391_fsm_307_assign_proc : process(ap_sig_bdd_5121)
begin
if (ap_sig_bdd_5121) then
ap_sig_cseq_ST_st391_fsm_307 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st391_fsm_307 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st392_fsm_308 assign process. --
ap_sig_cseq_ST_st392_fsm_308_assign_proc : process(ap_sig_bdd_2728)
begin
if (ap_sig_bdd_2728) then
ap_sig_cseq_ST_st392_fsm_308 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st392_fsm_308 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st393_fsm_309 assign process. --
ap_sig_cseq_ST_st393_fsm_309_assign_proc : process(ap_sig_bdd_5130)
begin
if (ap_sig_bdd_5130) then
ap_sig_cseq_ST_st393_fsm_309 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st393_fsm_309 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st394_fsm_310 assign process. --
ap_sig_cseq_ST_st394_fsm_310_assign_proc : process(ap_sig_bdd_5138)
begin
if (ap_sig_bdd_5138) then
ap_sig_cseq_ST_st394_fsm_310 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st394_fsm_310 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st395_fsm_311 assign process. --
ap_sig_cseq_ST_st395_fsm_311_assign_proc : process(ap_sig_bdd_2737)
begin
if (ap_sig_bdd_2737) then
ap_sig_cseq_ST_st395_fsm_311 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st395_fsm_311 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st396_fsm_312 assign process. --
ap_sig_cseq_ST_st396_fsm_312_assign_proc : process(ap_sig_bdd_5147)
begin
if (ap_sig_bdd_5147) then
ap_sig_cseq_ST_st396_fsm_312 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st396_fsm_312 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st397_fsm_313 assign process. --
ap_sig_cseq_ST_st397_fsm_313_assign_proc : process(ap_sig_bdd_5155)
begin
if (ap_sig_bdd_5155) then
ap_sig_cseq_ST_st397_fsm_313 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st397_fsm_313 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st398_fsm_314 assign process. --
ap_sig_cseq_ST_st398_fsm_314_assign_proc : process(ap_sig_bdd_2746)
begin
if (ap_sig_bdd_2746) then
ap_sig_cseq_ST_st398_fsm_314 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st398_fsm_314 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st399_fsm_315 assign process. --
ap_sig_cseq_ST_st399_fsm_315_assign_proc : process(ap_sig_bdd_5164)
begin
if (ap_sig_bdd_5164) then
ap_sig_cseq_ST_st399_fsm_315 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st399_fsm_315 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st39_fsm_38 assign process. --
ap_sig_cseq_ST_st39_fsm_38_assign_proc : process(ap_sig_bdd_3109)
begin
if (ap_sig_bdd_3109) then
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st39_fsm_38 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_708)
begin
if (ap_sig_bdd_708) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st400_fsm_316 assign process. --
ap_sig_cseq_ST_st400_fsm_316_assign_proc : process(ap_sig_bdd_5172)
begin
if (ap_sig_bdd_5172) then
ap_sig_cseq_ST_st400_fsm_316 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st400_fsm_316 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st401_fsm_317 assign process. --
ap_sig_cseq_ST_st401_fsm_317_assign_proc : process(ap_sig_bdd_2755)
begin
if (ap_sig_bdd_2755) then
ap_sig_cseq_ST_st401_fsm_317 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st401_fsm_317 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st402_fsm_318 assign process. --
ap_sig_cseq_ST_st402_fsm_318_assign_proc : process(ap_sig_bdd_5181)
begin
if (ap_sig_bdd_5181) then
ap_sig_cseq_ST_st402_fsm_318 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st402_fsm_318 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st403_fsm_319 assign process. --
ap_sig_cseq_ST_st403_fsm_319_assign_proc : process(ap_sig_bdd_5189)
begin
if (ap_sig_bdd_5189) then
ap_sig_cseq_ST_st403_fsm_319 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st403_fsm_319 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st404_fsm_320 assign process. --
ap_sig_cseq_ST_st404_fsm_320_assign_proc : process(ap_sig_bdd_2764)
begin
if (ap_sig_bdd_2764) then
ap_sig_cseq_ST_st404_fsm_320 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st404_fsm_320 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st405_fsm_321 assign process. --
ap_sig_cseq_ST_st405_fsm_321_assign_proc : process(ap_sig_bdd_5198)
begin
if (ap_sig_bdd_5198) then
ap_sig_cseq_ST_st405_fsm_321 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st405_fsm_321 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st406_fsm_322 assign process. --
ap_sig_cseq_ST_st406_fsm_322_assign_proc : process(ap_sig_bdd_5206)
begin
if (ap_sig_bdd_5206) then
ap_sig_cseq_ST_st406_fsm_322 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st406_fsm_322 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st407_fsm_323 assign process. --
ap_sig_cseq_ST_st407_fsm_323_assign_proc : process(ap_sig_bdd_2773)
begin
if (ap_sig_bdd_2773) then
ap_sig_cseq_ST_st407_fsm_323 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st407_fsm_323 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st408_fsm_324 assign process. --
ap_sig_cseq_ST_st408_fsm_324_assign_proc : process(ap_sig_bdd_5215)
begin
if (ap_sig_bdd_5215) then
ap_sig_cseq_ST_st408_fsm_324 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st408_fsm_324 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st409_fsm_325 assign process. --
ap_sig_cseq_ST_st409_fsm_325_assign_proc : process(ap_sig_bdd_5223)
begin
if (ap_sig_bdd_5223) then
ap_sig_cseq_ST_st409_fsm_325 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st409_fsm_325 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st40_fsm_39 assign process. --
ap_sig_cseq_ST_st40_fsm_39_assign_proc : process(ap_sig_bdd_3118)
begin
if (ap_sig_bdd_3118) then
ap_sig_cseq_ST_st40_fsm_39 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st40_fsm_39 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st410_fsm_326 assign process. --
ap_sig_cseq_ST_st410_fsm_326_assign_proc : process(ap_sig_bdd_2782)
begin
if (ap_sig_bdd_2782) then
ap_sig_cseq_ST_st410_fsm_326 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st410_fsm_326 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st411_fsm_327 assign process. --
ap_sig_cseq_ST_st411_fsm_327_assign_proc : process(ap_sig_bdd_5232)
begin
if (ap_sig_bdd_5232) then
ap_sig_cseq_ST_st411_fsm_327 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st411_fsm_327 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st412_fsm_328 assign process. --
ap_sig_cseq_ST_st412_fsm_328_assign_proc : process(ap_sig_bdd_5240)
begin
if (ap_sig_bdd_5240) then
ap_sig_cseq_ST_st412_fsm_328 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st412_fsm_328 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st413_fsm_329 assign process. --
ap_sig_cseq_ST_st413_fsm_329_assign_proc : process(ap_sig_bdd_2791)
begin
if (ap_sig_bdd_2791) then
ap_sig_cseq_ST_st413_fsm_329 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st413_fsm_329 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st414_fsm_330 assign process. --
ap_sig_cseq_ST_st414_fsm_330_assign_proc : process(ap_sig_bdd_5249)
begin
if (ap_sig_bdd_5249) then
ap_sig_cseq_ST_st414_fsm_330 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st414_fsm_330 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st415_fsm_331 assign process. --
ap_sig_cseq_ST_st415_fsm_331_assign_proc : process(ap_sig_bdd_5257)
begin
if (ap_sig_bdd_5257) then
ap_sig_cseq_ST_st415_fsm_331 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st415_fsm_331 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st416_fsm_332 assign process. --
ap_sig_cseq_ST_st416_fsm_332_assign_proc : process(ap_sig_bdd_2800)
begin
if (ap_sig_bdd_2800) then
ap_sig_cseq_ST_st416_fsm_332 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st416_fsm_332 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st417_fsm_333 assign process. --
ap_sig_cseq_ST_st417_fsm_333_assign_proc : process(ap_sig_bdd_5266)
begin
if (ap_sig_bdd_5266) then
ap_sig_cseq_ST_st417_fsm_333 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st417_fsm_333 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st418_fsm_334 assign process. --
ap_sig_cseq_ST_st418_fsm_334_assign_proc : process(ap_sig_bdd_5274)
begin
if (ap_sig_bdd_5274) then
ap_sig_cseq_ST_st418_fsm_334 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st418_fsm_334 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st419_fsm_335 assign process. --
ap_sig_cseq_ST_st419_fsm_335_assign_proc : process(ap_sig_bdd_2809)
begin
if (ap_sig_bdd_2809) then
ap_sig_cseq_ST_st419_fsm_335 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st419_fsm_335 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st41_fsm_40 assign process. --
ap_sig_cseq_ST_st41_fsm_40_assign_proc : process(ap_sig_bdd_3127)
begin
if (ap_sig_bdd_3127) then
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st41_fsm_40 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st420_fsm_336 assign process. --
ap_sig_cseq_ST_st420_fsm_336_assign_proc : process(ap_sig_bdd_5283)
begin
if (ap_sig_bdd_5283) then
ap_sig_cseq_ST_st420_fsm_336 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st420_fsm_336 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st421_fsm_337 assign process. --
ap_sig_cseq_ST_st421_fsm_337_assign_proc : process(ap_sig_bdd_5291)
begin
if (ap_sig_bdd_5291) then
ap_sig_cseq_ST_st421_fsm_337 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st421_fsm_337 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st422_fsm_338 assign process. --
ap_sig_cseq_ST_st422_fsm_338_assign_proc : process(ap_sig_bdd_2818)
begin
if (ap_sig_bdd_2818) then
ap_sig_cseq_ST_st422_fsm_338 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st422_fsm_338 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st423_fsm_339 assign process. --
ap_sig_cseq_ST_st423_fsm_339_assign_proc : process(ap_sig_bdd_5300)
begin
if (ap_sig_bdd_5300) then
ap_sig_cseq_ST_st423_fsm_339 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st423_fsm_339 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st424_fsm_340 assign process. --
ap_sig_cseq_ST_st424_fsm_340_assign_proc : process(ap_sig_bdd_5308)
begin
if (ap_sig_bdd_5308) then
ap_sig_cseq_ST_st424_fsm_340 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st424_fsm_340 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st425_fsm_341 assign process. --
ap_sig_cseq_ST_st425_fsm_341_assign_proc : process(ap_sig_bdd_2827)
begin
if (ap_sig_bdd_2827) then
ap_sig_cseq_ST_st425_fsm_341 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st425_fsm_341 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st426_fsm_342 assign process. --
ap_sig_cseq_ST_st426_fsm_342_assign_proc : process(ap_sig_bdd_5317)
begin
if (ap_sig_bdd_5317) then
ap_sig_cseq_ST_st426_fsm_342 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st426_fsm_342 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st427_fsm_343 assign process. --
ap_sig_cseq_ST_st427_fsm_343_assign_proc : process(ap_sig_bdd_5325)
begin
if (ap_sig_bdd_5325) then
ap_sig_cseq_ST_st427_fsm_343 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st427_fsm_343 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st428_fsm_344 assign process. --
ap_sig_cseq_ST_st428_fsm_344_assign_proc : process(ap_sig_bdd_2836)
begin
if (ap_sig_bdd_2836) then
ap_sig_cseq_ST_st428_fsm_344 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st428_fsm_344 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st429_fsm_345 assign process. --
ap_sig_cseq_ST_st429_fsm_345_assign_proc : process(ap_sig_bdd_5334)
begin
if (ap_sig_bdd_5334) then
ap_sig_cseq_ST_st429_fsm_345 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st429_fsm_345 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st42_fsm_41 assign process. --
ap_sig_cseq_ST_st42_fsm_41_assign_proc : process(ap_sig_bdd_3136)
begin
if (ap_sig_bdd_3136) then
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st430_fsm_346 assign process. --
ap_sig_cseq_ST_st430_fsm_346_assign_proc : process(ap_sig_bdd_5342)
begin
if (ap_sig_bdd_5342) then
ap_sig_cseq_ST_st430_fsm_346 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st430_fsm_346 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st431_fsm_347 assign process. --
ap_sig_cseq_ST_st431_fsm_347_assign_proc : process(ap_sig_bdd_2845)
begin
if (ap_sig_bdd_2845) then
ap_sig_cseq_ST_st431_fsm_347 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st431_fsm_347 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st432_fsm_348 assign process. --
ap_sig_cseq_ST_st432_fsm_348_assign_proc : process(ap_sig_bdd_5351)
begin
if (ap_sig_bdd_5351) then
ap_sig_cseq_ST_st432_fsm_348 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st432_fsm_348 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st433_fsm_349 assign process. --
ap_sig_cseq_ST_st433_fsm_349_assign_proc : process(ap_sig_bdd_5359)
begin
if (ap_sig_bdd_5359) then
ap_sig_cseq_ST_st433_fsm_349 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st433_fsm_349 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st434_fsm_350 assign process. --
ap_sig_cseq_ST_st434_fsm_350_assign_proc : process(ap_sig_bdd_2854)
begin
if (ap_sig_bdd_2854) then
ap_sig_cseq_ST_st434_fsm_350 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st434_fsm_350 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st435_fsm_351 assign process. --
ap_sig_cseq_ST_st435_fsm_351_assign_proc : process(ap_sig_bdd_5368)
begin
if (ap_sig_bdd_5368) then
ap_sig_cseq_ST_st435_fsm_351 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st435_fsm_351 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st436_fsm_352 assign process. --
ap_sig_cseq_ST_st436_fsm_352_assign_proc : process(ap_sig_bdd_5376)
begin
if (ap_sig_bdd_5376) then
ap_sig_cseq_ST_st436_fsm_352 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st436_fsm_352 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st437_fsm_353 assign process. --
ap_sig_cseq_ST_st437_fsm_353_assign_proc : process(ap_sig_bdd_2863)
begin
if (ap_sig_bdd_2863) then
ap_sig_cseq_ST_st437_fsm_353 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st437_fsm_353 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st438_fsm_354 assign process. --
ap_sig_cseq_ST_st438_fsm_354_assign_proc : process(ap_sig_bdd_5385)
begin
if (ap_sig_bdd_5385) then
ap_sig_cseq_ST_st438_fsm_354 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st438_fsm_354 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st439_fsm_355 assign process. --
ap_sig_cseq_ST_st439_fsm_355_assign_proc : process(ap_sig_bdd_5393)
begin
if (ap_sig_bdd_5393) then
ap_sig_cseq_ST_st439_fsm_355 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st439_fsm_355 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st43_fsm_42 assign process. --
ap_sig_cseq_ST_st43_fsm_42_assign_proc : process(ap_sig_bdd_3145)
begin
if (ap_sig_bdd_3145) then
ap_sig_cseq_ST_st43_fsm_42 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st43_fsm_42 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st440_fsm_356 assign process. --
ap_sig_cseq_ST_st440_fsm_356_assign_proc : process(ap_sig_bdd_2872)
begin
if (ap_sig_bdd_2872) then
ap_sig_cseq_ST_st440_fsm_356 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st440_fsm_356 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st441_fsm_357 assign process. --
ap_sig_cseq_ST_st441_fsm_357_assign_proc : process(ap_sig_bdd_5402)
begin
if (ap_sig_bdd_5402) then
ap_sig_cseq_ST_st441_fsm_357 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st441_fsm_357 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st442_fsm_358 assign process. --
ap_sig_cseq_ST_st442_fsm_358_assign_proc : process(ap_sig_bdd_5410)
begin
if (ap_sig_bdd_5410) then
ap_sig_cseq_ST_st442_fsm_358 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st442_fsm_358 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st443_fsm_359 assign process. --
ap_sig_cseq_ST_st443_fsm_359_assign_proc : process(ap_sig_bdd_2881)
begin
if (ap_sig_bdd_2881) then
ap_sig_cseq_ST_st443_fsm_359 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st443_fsm_359 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st444_fsm_360 assign process. --
ap_sig_cseq_ST_st444_fsm_360_assign_proc : process(ap_sig_bdd_5419)
begin
if (ap_sig_bdd_5419) then
ap_sig_cseq_ST_st444_fsm_360 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st444_fsm_360 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st445_fsm_361 assign process. --
ap_sig_cseq_ST_st445_fsm_361_assign_proc : process(ap_sig_bdd_5427)
begin
if (ap_sig_bdd_5427) then
ap_sig_cseq_ST_st445_fsm_361 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st445_fsm_361 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st44_fsm_43 assign process. --
ap_sig_cseq_ST_st44_fsm_43_assign_proc : process(ap_sig_bdd_3154)
begin
if (ap_sig_bdd_3154) then
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st44_fsm_43 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st45_fsm_44 assign process. --
ap_sig_cseq_ST_st45_fsm_44_assign_proc : process(ap_sig_bdd_3163)
begin
if (ap_sig_bdd_3163) then
ap_sig_cseq_ST_st45_fsm_44 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st45_fsm_44 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st46_fsm_45 assign process. --
ap_sig_cseq_ST_st46_fsm_45_assign_proc : process(ap_sig_bdd_3172)
begin
if (ap_sig_bdd_3172) then
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st46_fsm_45 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st47_fsm_46 assign process. --
ap_sig_cseq_ST_st47_fsm_46_assign_proc : process(ap_sig_bdd_3181)
begin
if (ap_sig_bdd_3181) then
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st48_fsm_47 assign process. --
ap_sig_cseq_ST_st48_fsm_47_assign_proc : process(ap_sig_bdd_3190)
begin
if (ap_sig_bdd_3190) then
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st49_fsm_48 assign process. --
ap_sig_cseq_ST_st49_fsm_48_assign_proc : process(ap_sig_bdd_3199)
begin
if (ap_sig_bdd_3199) then
ap_sig_cseq_ST_st49_fsm_48 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st49_fsm_48 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_852)
begin
if (ap_sig_bdd_852) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st50_fsm_49 assign process. --
ap_sig_cseq_ST_st50_fsm_49_assign_proc : process(ap_sig_bdd_3208)
begin
if (ap_sig_bdd_3208) then
ap_sig_cseq_ST_st50_fsm_49 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st50_fsm_49 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st51_fsm_50 assign process. --
ap_sig_cseq_ST_st51_fsm_50_assign_proc : process(ap_sig_bdd_3217)
begin
if (ap_sig_bdd_3217) then
ap_sig_cseq_ST_st51_fsm_50 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st51_fsm_50 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st52_fsm_51 assign process. --
ap_sig_cseq_ST_st52_fsm_51_assign_proc : process(ap_sig_bdd_3226)
begin
if (ap_sig_bdd_3226) then
ap_sig_cseq_ST_st52_fsm_51 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st52_fsm_51 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st53_fsm_52 assign process. --
ap_sig_cseq_ST_st53_fsm_52_assign_proc : process(ap_sig_bdd_3235)
begin
if (ap_sig_bdd_3235) then
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st54_fsm_53 assign process. --
ap_sig_cseq_ST_st54_fsm_53_assign_proc : process(ap_sig_bdd_3244)
begin
if (ap_sig_bdd_3244) then
ap_sig_cseq_ST_st54_fsm_53 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st54_fsm_53 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st55_fsm_54 assign process. --
ap_sig_cseq_ST_st55_fsm_54_assign_proc : process(ap_sig_bdd_3253)
begin
if (ap_sig_bdd_3253) then
ap_sig_cseq_ST_st55_fsm_54 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st55_fsm_54 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st56_fsm_55 assign process. --
ap_sig_cseq_ST_st56_fsm_55_assign_proc : process(ap_sig_bdd_3262)
begin
if (ap_sig_bdd_3262) then
ap_sig_cseq_ST_st56_fsm_55 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st56_fsm_55 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st57_fsm_56 assign process. --
ap_sig_cseq_ST_st57_fsm_56_assign_proc : process(ap_sig_bdd_3271)
begin
if (ap_sig_bdd_3271) then
ap_sig_cseq_ST_st57_fsm_56 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st57_fsm_56 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st58_fsm_57 assign process. --
ap_sig_cseq_ST_st58_fsm_57_assign_proc : process(ap_sig_bdd_3280)
begin
if (ap_sig_bdd_3280) then
ap_sig_cseq_ST_st58_fsm_57 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st58_fsm_57 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st59_fsm_58 assign process. --
ap_sig_cseq_ST_st59_fsm_58_assign_proc : process(ap_sig_bdd_3289)
begin
if (ap_sig_bdd_3289) then
ap_sig_cseq_ST_st59_fsm_58 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st59_fsm_58 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_996)
begin
if (ap_sig_bdd_996) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st60_fsm_59 assign process. --
ap_sig_cseq_ST_st60_fsm_59_assign_proc : process(ap_sig_bdd_3298)
begin
if (ap_sig_bdd_3298) then
ap_sig_cseq_ST_st60_fsm_59 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st60_fsm_59 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st61_fsm_60 assign process. --
ap_sig_cseq_ST_st61_fsm_60_assign_proc : process(ap_sig_bdd_3307)
begin
if (ap_sig_bdd_3307) then
ap_sig_cseq_ST_st61_fsm_60 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st61_fsm_60 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st62_fsm_61 assign process. --
ap_sig_cseq_ST_st62_fsm_61_assign_proc : process(ap_sig_bdd_3316)
begin
if (ap_sig_bdd_3316) then
ap_sig_cseq_ST_st62_fsm_61 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st62_fsm_61 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st63_fsm_62 assign process. --
ap_sig_cseq_ST_st63_fsm_62_assign_proc : process(ap_sig_bdd_3325)
begin
if (ap_sig_bdd_3325) then
ap_sig_cseq_ST_st63_fsm_62 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st63_fsm_62 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st64_fsm_63 assign process. --
ap_sig_cseq_ST_st64_fsm_63_assign_proc : process(ap_sig_bdd_3334)
begin
if (ap_sig_bdd_3334) then
ap_sig_cseq_ST_st64_fsm_63 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st64_fsm_63 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st65_fsm_64 assign process. --
ap_sig_cseq_ST_st65_fsm_64_assign_proc : process(ap_sig_bdd_3343)
begin
if (ap_sig_bdd_3343) then
ap_sig_cseq_ST_st65_fsm_64 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st65_fsm_64 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st66_fsm_65 assign process. --
ap_sig_cseq_ST_st66_fsm_65_assign_proc : process(ap_sig_bdd_3352)
begin
if (ap_sig_bdd_3352) then
ap_sig_cseq_ST_st66_fsm_65 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st66_fsm_65 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st67_fsm_66 assign process. --
ap_sig_cseq_ST_st67_fsm_66_assign_proc : process(ap_sig_bdd_3361)
begin
if (ap_sig_bdd_3361) then
ap_sig_cseq_ST_st67_fsm_66 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st67_fsm_66 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st68_fsm_67 assign process. --
ap_sig_cseq_ST_st68_fsm_67_assign_proc : process(ap_sig_bdd_3370)
begin
if (ap_sig_bdd_3370) then
ap_sig_cseq_ST_st68_fsm_67 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st68_fsm_67 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st69_fsm_68 assign process. --
ap_sig_cseq_ST_st69_fsm_68_assign_proc : process(ap_sig_bdd_3379)
begin
if (ap_sig_bdd_3379) then
ap_sig_cseq_ST_st69_fsm_68 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st69_fsm_68 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_1140)
begin
if (ap_sig_bdd_1140) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st70_fsm_69 assign process. --
ap_sig_cseq_ST_st70_fsm_69_assign_proc : process(ap_sig_bdd_3388)
begin
if (ap_sig_bdd_3388) then
ap_sig_cseq_ST_st70_fsm_69 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st70_fsm_69 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st71_fsm_70 assign process. --
ap_sig_cseq_ST_st71_fsm_70_assign_proc : process(ap_sig_bdd_3397)
begin
if (ap_sig_bdd_3397) then
ap_sig_cseq_ST_st71_fsm_70 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st71_fsm_70 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st72_fsm_71 assign process. --
ap_sig_cseq_ST_st72_fsm_71_assign_proc : process(ap_sig_bdd_2437)
begin
if (ap_sig_bdd_2437) then
ap_sig_cseq_ST_st72_fsm_71 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st72_fsm_71 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st73_fsm_72 assign process. --
ap_sig_cseq_ST_st73_fsm_72_assign_proc : process(ap_sig_bdd_410)
begin
if (ap_sig_bdd_410) then
ap_sig_cseq_ST_st73_fsm_72 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st73_fsm_72 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st74_fsm_73 assign process. --
ap_sig_cseq_ST_st74_fsm_73_assign_proc : process(ap_sig_bdd_563)
begin
if (ap_sig_bdd_563) then
ap_sig_cseq_ST_st74_fsm_73 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st74_fsm_73 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st75_fsm_74 assign process. --
ap_sig_cseq_ST_st75_fsm_74_assign_proc : process(ap_sig_bdd_3417)
begin
if (ap_sig_bdd_3417) then
ap_sig_cseq_ST_st75_fsm_74 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st75_fsm_74 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st76_fsm_75 assign process. --
ap_sig_cseq_ST_st76_fsm_75_assign_proc : process(ap_sig_bdd_419)
begin
if (ap_sig_bdd_419) then
ap_sig_cseq_ST_st76_fsm_75 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st76_fsm_75 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st77_fsm_76 assign process. --
ap_sig_cseq_ST_st77_fsm_76_assign_proc : process(ap_sig_bdd_572)
begin
if (ap_sig_bdd_572) then
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st77_fsm_76 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_716)
begin
if (ap_sig_bdd_716) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_860)
begin
if (ap_sig_bdd_860) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_1284)
begin
if (ap_sig_bdd_1284) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_1004)
begin
if (ap_sig_bdd_1004) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_1148)
begin
if (ap_sig_bdd_1148) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st82_fsm_81 assign process. --
ap_sig_cseq_ST_st82_fsm_81_assign_proc : process(ap_sig_bdd_1292)
begin
if (ap_sig_bdd_1292) then
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_1436)
begin
if (ap_sig_bdd_1436) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_1580)
begin
if (ap_sig_bdd_1580) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st85_fsm_84 assign process. --
ap_sig_cseq_ST_st85_fsm_84_assign_proc : process(ap_sig_bdd_1724)
begin
if (ap_sig_bdd_1724) then
ap_sig_cseq_ST_st85_fsm_84 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st85_fsm_84 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st86_fsm_85 assign process. --
ap_sig_cseq_ST_st86_fsm_85_assign_proc : process(ap_sig_bdd_1868)
begin
if (ap_sig_bdd_1868) then
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_2012)
begin
if (ap_sig_bdd_2012) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_2156)
begin
if (ap_sig_bdd_2156) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st89_fsm_88 assign process. --
ap_sig_cseq_ST_st89_fsm_88_assign_proc : process(ap_sig_bdd_2300)
begin
if (ap_sig_bdd_2300) then
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_1428)
begin
if (ap_sig_bdd_1428) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st90_fsm_89 assign process. --
ap_sig_cseq_ST_st90_fsm_89_assign_proc : process(ap_sig_bdd_3437)
begin
if (ap_sig_bdd_3437) then
ap_sig_cseq_ST_st90_fsm_89 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st90_fsm_89 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st91_fsm_90 assign process. --
ap_sig_cseq_ST_st91_fsm_90_assign_proc : process(ap_sig_bdd_428)
begin
if (ap_sig_bdd_428) then
ap_sig_cseq_ST_st91_fsm_90 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st91_fsm_90 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_581)
begin
if (ap_sig_bdd_581) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_725)
begin
if (ap_sig_bdd_725) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st94_fsm_93 assign process. --
ap_sig_cseq_ST_st94_fsm_93_assign_proc : process(ap_sig_bdd_869)
begin
if (ap_sig_bdd_869) then
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st94_fsm_93 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st95_fsm_94 assign process. --
ap_sig_cseq_ST_st95_fsm_94_assign_proc : process(ap_sig_bdd_1013)
begin
if (ap_sig_bdd_1013) then
ap_sig_cseq_ST_st95_fsm_94 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st95_fsm_94 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st96_fsm_95 assign process. --
ap_sig_cseq_ST_st96_fsm_95_assign_proc : process(ap_sig_bdd_1157)
begin
if (ap_sig_bdd_1157) then
ap_sig_cseq_ST_st96_fsm_95 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st96_fsm_95 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st97_fsm_96 assign process. --
ap_sig_cseq_ST_st97_fsm_96_assign_proc : process(ap_sig_bdd_1301)
begin
if (ap_sig_bdd_1301) then
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_1445)
begin
if (ap_sig_bdd_1445) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_1589)
begin
if (ap_sig_bdd_1589) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_1572)
begin
if (ap_sig_bdd_1572) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_outs_TREADY assign process. --
ap_sig_ioackin_outs_TREADY_assign_proc : process(outs_TREADY, ap_reg_ioackin_outs_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) then
ap_sig_ioackin_outs_TREADY <= outs_TREADY;
else
ap_sig_ioackin_outs_TREADY <= ap_const_logic_1;
end if;
end process;
beta_addr_111281129_part_set_fu_3103_p5 <= (tmp_21_fu_3093_p4 & ap_reg_ppstg_reg_725_pp0_it81(479 downto 0));
beta_load_10_fu_3290_p1 <= reg_733;
beta_load_11_fu_3305_p1 <= reg_733;
beta_load_12_fu_3320_p1 <= reg_733;
beta_load_13_fu_3335_p1 <= reg_733;
beta_load_14_fu_3350_p1 <= reg_733;
beta_load_15_fu_3365_p1 <= reg_733;
beta_load_16_fu_3380_p1 <= reg_733;
beta_load_17_fu_3395_p1 <= reg_733;
beta_load_18_fu_3410_p1 <= reg_733;
beta_load_1_fu_3155_p1 <= reg_733;
beta_load_2_fu_3170_p1 <= reg_733;
beta_load_3_fu_3185_p1 <= reg_733;
beta_load_4_fu_3200_p1 <= reg_733;
beta_load_5_fu_3215_p1 <= reg_733;
beta_load_6_fu_3230_p1 <= reg_733;
beta_load_7_fu_3245_p1 <= reg_733;
beta_load_8_fu_3260_p1 <= reg_733;
beta_load_9_fu_3275_p1 <= reg_733;
beta_load_fu_3125_p1 <= reg_733;
beta_load_s_fu_3140_p1 <= reg_733;
beta_write_assign_toint_fu_3089_p1 <= grp_fu_626_p2;
data_array_addr_10_gep_fu_360_p3 <= ap_const_lv64_A(5 - 1 downto 0);
data_array_addr_11_gep_fu_368_p3 <= ap_const_lv64_B(5 - 1 downto 0);
data_array_addr_12_gep_fu_376_p3 <= ap_const_lv64_C(5 - 1 downto 0);
data_array_addr_13_gep_fu_384_p3 <= ap_const_lv64_D(5 - 1 downto 0);
data_array_addr_14_gep_fu_392_p3 <= ap_const_lv64_E(5 - 1 downto 0);
data_array_addr_15_gep_fu_400_p3 <= ap_const_lv64_F(5 - 1 downto 0);
data_array_addr_16_gep_fu_244_p3 <= ap_const_lv64_10(5 - 1 downto 0);
data_array_addr_17_gep_fu_288_p3 <= ap_const_lv64_11(5 - 1 downto 0);
data_array_addr_18_gep_fu_256_p3 <= ap_const_lv64_12(5 - 1 downto 0);
data_array_addr_19_gep_fu_296_p3 <= ap_const_lv64_13(5 - 1 downto 0);
data_array_addr_1_gep_fu_304_p3 <= ap_const_lv64_1(5 - 1 downto 0);
data_array_addr_2_gep_fu_272_p3 <= ap_const_lv64_2(5 - 1 downto 0);
data_array_addr_3_gep_fu_312_p3 <= ap_const_lv64_3(5 - 1 downto 0);
data_array_addr_4_gep_fu_280_p3 <= ap_const_lv64_4(5 - 1 downto 0);
data_array_addr_5_gep_fu_320_p3 <= ap_const_lv64_5(5 - 1 downto 0);
data_array_addr_6_gep_fu_328_p3 <= ap_const_lv64_6(5 - 1 downto 0);
data_array_addr_7_gep_fu_336_p3 <= ap_const_lv64_7(5 - 1 downto 0);
data_array_addr_8_gep_fu_344_p3 <= ap_const_lv64_8(5 - 1 downto 0);
data_array_addr_9_gep_fu_352_p3 <= ap_const_lv64_9(5 - 1 downto 0);
data_array_addr_gep_fu_264_p3 <= ap_const_lv64_0(5 - 1 downto 0);
-- data_array_address0 assign process. --
data_array_address0_assign_proc : process(ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st72_fsm_71, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg0_fsm_300, ap_sig_cseq_ST_st71_fsm_70, data_array_addr_16_reg_3700, data_array_addr_18_reg_3711, ap_sig_cseq_ST_st75_fsm_74, data_array_addr_17_reg_3737, data_array_addr_19_reg_3748, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, tmp_1_fu_2852_p1, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) then
data_array_address0 <= data_array_addr_19_reg_3748;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)) then
data_array_address0 <= data_array_addr_18_reg_3711;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) then
data_array_address0 <= data_array_addr_17_reg_3737;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) then
data_array_address0 <= data_array_addr_16_reg_3700;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) then
data_array_address0 <= ap_const_lv64_F(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) then
data_array_address0 <= ap_const_lv64_E(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) then
data_array_address0 <= ap_const_lv64_D(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) then
data_array_address0 <= ap_const_lv64_C(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) then
data_array_address0 <= ap_const_lv64_B(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) then
data_array_address0 <= ap_const_lv64_A(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) then
data_array_address0 <= ap_const_lv64_9(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) then
data_array_address0 <= ap_const_lv64_8(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) then
data_array_address0 <= ap_const_lv64_7(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) then
data_array_address0 <= ap_const_lv64_6(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) then
data_array_address0 <= ap_const_lv64_5(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) then
data_array_address0 <= ap_const_lv64_3(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
data_array_address0 <= ap_const_lv64_1(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) then
data_array_address0 <= ap_const_lv64_4(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) then
data_array_address0 <= ap_const_lv64_2(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) then
data_array_address0 <= ap_const_lv64_0(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300))) then
data_array_address0 <= tmp_1_fu_2852_p1(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) then
data_array_address0 <= ap_const_lv64_13(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) then
data_array_address0 <= ap_const_lv64_11(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71)) then
data_array_address0 <= ap_const_lv64_12(5 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st71_fsm_70)) then
data_array_address0 <= ap_const_lv64_10(5 - 1 downto 0);
else
data_array_address0 <= "XXXXX";
end if;
end process;
-- data_array_address1 assign process. --
data_array_address1_assign_proc : process(ap_reg_ppiten_pp0_it83, data_array_addr_16_reg_3700, data_array_addr_18_reg_3711, data_array_addr_reg_3717, data_array_addr_2_reg_3727, data_array_addr_4_reg_3732, data_array_addr_17_reg_3737, data_array_addr_19_reg_3748, data_array_addr_1_reg_3754, data_array_addr_3_reg_3764, data_array_addr_5_reg_3769, data_array_addr_6_reg_3774, data_array_addr_7_reg_3779, data_array_addr_8_reg_3784, data_array_addr_9_reg_3789, data_array_addr_10_reg_3794, data_array_addr_11_reg_3799, data_array_addr_12_reg_3804, data_array_addr_13_reg_3809, data_array_addr_14_reg_3814, data_array_addr_15_reg_3819, ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82, ap_sig_cseq_ST_st388_fsm_304, ap_sig_cseq_ST_st391_fsm_307, ap_sig_cseq_ST_st394_fsm_310, ap_sig_cseq_ST_st397_fsm_313, ap_sig_cseq_ST_st400_fsm_316, ap_sig_cseq_ST_st403_fsm_319, ap_sig_cseq_ST_st406_fsm_322, ap_sig_cseq_ST_st409_fsm_325, ap_sig_cseq_ST_st412_fsm_328, ap_sig_cseq_ST_st415_fsm_331, ap_sig_cseq_ST_st418_fsm_334, ap_sig_cseq_ST_st421_fsm_337, ap_sig_cseq_ST_st424_fsm_340, ap_sig_cseq_ST_st427_fsm_343, ap_sig_cseq_ST_st430_fsm_346, ap_sig_cseq_ST_st433_fsm_349, ap_sig_cseq_ST_st436_fsm_352, ap_sig_cseq_ST_st439_fsm_355, ap_sig_cseq_ST_st442_fsm_358, ap_sig_cseq_ST_st385_fsm_301)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it83)) then
data_array_address1 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358)) then
data_array_address1 <= data_array_addr_19_reg_3748;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355)) then
data_array_address1 <= data_array_addr_18_reg_3711;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352)) then
data_array_address1 <= data_array_addr_17_reg_3737;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349)) then
data_array_address1 <= data_array_addr_16_reg_3700;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346)) then
data_array_address1 <= data_array_addr_15_reg_3819;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343)) then
data_array_address1 <= data_array_addr_14_reg_3814;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340)) then
data_array_address1 <= data_array_addr_13_reg_3809;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337)) then
data_array_address1 <= data_array_addr_12_reg_3804;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334)) then
data_array_address1 <= data_array_addr_11_reg_3799;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331)) then
data_array_address1 <= data_array_addr_10_reg_3794;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328)) then
data_array_address1 <= data_array_addr_9_reg_3789;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325)) then
data_array_address1 <= data_array_addr_8_reg_3784;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322)) then
data_array_address1 <= data_array_addr_7_reg_3779;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319)) then
data_array_address1 <= data_array_addr_6_reg_3774;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316)) then
data_array_address1 <= data_array_addr_5_reg_3769;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313)) then
data_array_address1 <= data_array_addr_4_reg_3732;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310)) then
data_array_address1 <= data_array_addr_3_reg_3764;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307)) then
data_array_address1 <= data_array_addr_2_reg_3727;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304)) then
data_array_address1 <= data_array_addr_1_reg_3754;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st385_fsm_301)) then
data_array_address1 <= data_array_addr_reg_3717;
else
data_array_address1 <= "XXXXX";
end if;
end process;
-- data_array_ce0 assign process. --
data_array_ce0_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st72_fsm_71, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg0_fsm_300, ap_sig_cseq_ST_st71_fsm_70, ap_sig_cseq_ST_st75_fsm_74, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284)
begin
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st71_fsm_70)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_300)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)))) then
data_array_ce0 <= ap_const_logic_1;
else
data_array_ce0 <= ap_const_logic_0;
end if;
end process;
-- data_array_ce1 assign process. --
data_array_ce1_assign_proc : process(ap_reg_ppiten_pp0_it83, ap_sig_ioackin_outs_TREADY, ap_sig_cseq_ST_st388_fsm_304, ap_sig_cseq_ST_st391_fsm_307, ap_sig_cseq_ST_st394_fsm_310, ap_sig_cseq_ST_st397_fsm_313, ap_sig_cseq_ST_st400_fsm_316, ap_sig_cseq_ST_st403_fsm_319, ap_sig_cseq_ST_st406_fsm_322, ap_sig_cseq_ST_st409_fsm_325, ap_sig_cseq_ST_st412_fsm_328, ap_sig_cseq_ST_st415_fsm_331, ap_sig_cseq_ST_st418_fsm_334, ap_sig_cseq_ST_st421_fsm_337, ap_sig_cseq_ST_st424_fsm_340, ap_sig_cseq_ST_st427_fsm_343, ap_sig_cseq_ST_st430_fsm_346, ap_sig_cseq_ST_st433_fsm_349, ap_sig_cseq_ST_st436_fsm_352, ap_sig_cseq_ST_st439_fsm_355, ap_sig_cseq_ST_st442_fsm_358, ap_sig_cseq_ST_st385_fsm_301)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358)) or (ap_const_logic_1 = ap_sig_cseq_ST_st385_fsm_301))) then
data_array_ce1 <= ap_const_logic_1;
else
data_array_ce1 <= ap_const_logic_0;
end if;
end process;
-- data_array_d0 assign process. --
data_array_d0_assign_proc : process(ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st75_fsm_74, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284, rez_addr959960_part_set_fu_830_p5, rez_addr_3953954_part_set_fu_922_p5, rez_addr_5947948_part_set_fu_1017_p5, rez_addr_1956957_part_set_fu_1109_p5, rez_addr_4950951_part_set_fu_1201_p5, rez_addr_6944945_part_set_fu_1308_p5, rez_addr_7941942_part_set_fu_1415_p5, rez_addr_8938939_part_set_fu_1522_p5, rez_addr_9935936_part_set_fu_1629_p5, rez_addr_10932933_part_set_fu_1736_p5, rez_addr_11929930_part_set_fu_1843_p5, rez_addr_12926927_part_set_fu_1950_p5, rez_addr_13923924_part_set_fu_2057_p5, rez_addr_14920921_part_set_fu_2164_p5, rez_addr_15917918_part_set_fu_2271_p5, rez_addr_16914915_part_set_fu_2378_p5, rez_addr_17911912_part_set_fu_2485_p5, rez_addr_18908909_part_set_fu_2592_p5, rez_addr_19905906_part_set_fu_2698_p5, rez_addr_20902903_part_set_fu_2828_p5)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) then
data_array_d0 <= rez_addr_20902903_part_set_fu_2828_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)) then
data_array_d0 <= rez_addr_19905906_part_set_fu_2698_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) then
data_array_d0 <= rez_addr_18908909_part_set_fu_2592_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) then
data_array_d0 <= rez_addr_17911912_part_set_fu_2485_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) then
data_array_d0 <= rez_addr_16914915_part_set_fu_2378_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) then
data_array_d0 <= rez_addr_15917918_part_set_fu_2271_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) then
data_array_d0 <= rez_addr_14920921_part_set_fu_2164_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) then
data_array_d0 <= rez_addr_13923924_part_set_fu_2057_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) then
data_array_d0 <= rez_addr_12926927_part_set_fu_1950_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) then
data_array_d0 <= rez_addr_11929930_part_set_fu_1843_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) then
data_array_d0 <= rez_addr_10932933_part_set_fu_1736_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) then
data_array_d0 <= rez_addr_9935936_part_set_fu_1629_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) then
data_array_d0 <= rez_addr_8938939_part_set_fu_1522_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) then
data_array_d0 <= rez_addr_7941942_part_set_fu_1415_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) then
data_array_d0 <= rez_addr_6944945_part_set_fu_1308_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) then
data_array_d0 <= rez_addr_4950951_part_set_fu_1201_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
data_array_d0 <= rez_addr_1956957_part_set_fu_1109_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) then
data_array_d0 <= rez_addr_5947948_part_set_fu_1017_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) then
data_array_d0 <= rez_addr_3953954_part_set_fu_922_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) then
data_array_d0 <= rez_addr959960_part_set_fu_830_p5;
else
data_array_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
data_array_d1 <= beta_addr_111281129_part_set_reg_4307;
-- data_array_we0 assign process. --
data_array_we0_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st75_fsm_74, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284)
begin
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)))) then
data_array_we0 <= ap_const_logic_1;
else
data_array_we0 <= ap_const_logic_0;
end if;
end process;
-- data_array_we1 assign process. --
data_array_we1_assign_proc : process(ap_reg_ppiten_pp0_it83, ap_reg_ppstg_exitcond2_reg_3854_pp0_it82)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond2_reg_3854_pp0_it82)))) then
data_array_we1 <= ap_const_logic_1;
else
data_array_we1 <= ap_const_logic_0;
end if;
end process;
exitcond2_fu_2840_p2 <= "1" when (i1_reg_418 = ap_const_lv5_14) else "0";
g_fu_3055_p1 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10;
gamma_load_10_fu_3285_p1 <= reg_729;
gamma_load_11_fu_3300_p1 <= reg_729;
gamma_load_12_fu_3315_p1 <= reg_729;
gamma_load_13_fu_3330_p1 <= reg_729;
gamma_load_14_fu_3345_p1 <= reg_729;
gamma_load_15_fu_3360_p1 <= reg_729;
gamma_load_16_fu_3375_p1 <= reg_729;
gamma_load_17_fu_3390_p1 <= reg_729;
gamma_load_18_fu_3405_p1 <= reg_729;
gamma_load_1_fu_3150_p1 <= reg_729;
gamma_load_2_fu_3165_p1 <= reg_729;
gamma_load_3_fu_3180_p1 <= reg_729;
gamma_load_4_fu_3195_p1 <= reg_729;
gamma_load_5_fu_3210_p1 <= reg_729;
gamma_load_6_fu_3225_p1 <= reg_729;
gamma_load_7_fu_3240_p1 <= reg_729;
gamma_load_8_fu_3255_p1 <= reg_729;
gamma_load_9_fu_3270_p1 <= reg_729;
gamma_load_fu_3120_p1 <= reg_729;
gamma_load_s_fu_3135_p1 <= reg_729;
gamma_write_assign_toint_fu_3085_p1 <= grp_fu_622_p2;
grp_fu_430_ce <= ap_const_logic_1;
grp_fu_430_p0 <= v0x_assign4_fu_3001_p1;
grp_fu_430_p1 <= v1x_assign_new_reg_3884;
grp_fu_434_ce <= ap_const_logic_1;
grp_fu_434_p0 <= v0y_assign_fu_3007_p1;
grp_fu_434_p1 <= v1y_assign_new_reg_3889;
grp_fu_438_ce <= ap_const_logic_1;
grp_fu_438_p0 <= v0z_assign_fu_3013_p1;
grp_fu_438_p1 <= v1z_assign_new_reg_3894;
grp_fu_442_ce <= ap_const_logic_1;
grp_fu_442_p0 <= v0x_assign4_fu_3001_p1;
grp_fu_442_p1 <= v2x_assign_new_reg_3899;
grp_fu_446_ce <= ap_const_logic_1;
grp_fu_446_p0 <= v0y_assign_fu_3007_p1;
grp_fu_446_p1 <= v2y_assign_new_reg_3904;
grp_fu_450_ce <= ap_const_logic_1;
grp_fu_450_p0 <= v0z_assign_fu_3013_p1;
grp_fu_450_p1 <= v2z_assign_new_reg_3909;
grp_fu_454_ce <= ap_const_logic_1;
grp_fu_454_p0 <= v0x_assign4_fu_3001_p1;
grp_fu_454_p1 <= rex_assign_new_reg_3929;
grp_fu_458_ce <= ap_const_logic_1;
grp_fu_458_p0 <= v0y_assign_fu_3007_p1;
grp_fu_458_p1 <= rey_assign_new_reg_3934;
grp_fu_462_ce <= ap_const_logic_1;
grp_fu_462_p0 <= v0z_assign_fu_3013_p1;
grp_fu_462_p1 <= rez_assign_new_reg_3939;
grp_fu_466_ce <= ap_const_logic_1;
grp_fu_466_p0 <= tmp_i_reg_4094;
grp_fu_466_p1 <= tmp_i_311_reg_4099;
grp_fu_470_ce <= ap_const_logic_1;
grp_fu_470_p0 <= tmp_3_i_reg_4104;
grp_fu_470_p1 <= tmp_4_i_reg_4109;
grp_fu_474_ce <= ap_const_logic_1;
grp_fu_474_p0 <= tmp_12_i_reg_4114;
grp_fu_474_p1 <= tmp_13_i_reg_4119;
grp_fu_478_ce <= ap_const_logic_1;
grp_fu_478_p0 <= tmp_16_i_reg_4124;
grp_fu_478_p1 <= tmp_17_i_reg_4129;
grp_fu_482_ce <= ap_const_logic_1;
grp_fu_482_p0 <= tmp_8_i_reg_4146;
grp_fu_482_p1 <= tmp_9_i_reg_4151;
grp_fu_486_ce <= ap_const_logic_1;
grp_fu_486_p0 <= tmp_21_i_reg_4168;
grp_fu_486_p1 <= tmp_22_i_reg_4173;
grp_fu_490_ce <= ap_const_logic_1;
grp_fu_490_p0 <= tmp_2_i_reg_4178;
grp_fu_490_p1 <= tmp_6_i_reg_4183;
grp_fu_494_ce <= ap_const_logic_1;
grp_fu_494_p0 <= tmp_15_i_reg_4188;
grp_fu_494_p1 <= tmp_19_i_reg_4193;
grp_fu_498_ce <= ap_const_logic_1;
grp_fu_498_p0 <= tmp_27_i_reg_4198;
grp_fu_498_p1 <= tmp_28_i_reg_4203;
grp_fu_502_ce <= ap_const_logic_1;
grp_fu_502_p0 <= tmp_32_i_reg_4208;
grp_fu_502_p1 <= tmp_33_i_reg_4213;
grp_fu_506_ce <= ap_const_logic_1;
grp_fu_506_p0 <= tmp_7_i_reg_4230;
grp_fu_506_p1 <= tmp_11_i_reg_4235;
grp_fu_510_ce <= ap_const_logic_1;
grp_fu_510_p0 <= tmp_20_i_reg_4240;
grp_fu_510_p1 <= tmp_24_i_reg_4245;
grp_fu_514_ce <= ap_const_logic_1;
grp_fu_514_p0 <= tmp_29_i_reg_4250;
grp_fu_514_p1 <= tmp_30_i_reg_4255;
grp_fu_518_ce <= ap_const_logic_1;
grp_fu_518_p0 <= tmp_34_i_reg_4260;
grp_fu_518_p1 <= tmp_35_i_reg_4265;
grp_fu_522_ce <= ap_const_logic_1;
grp_fu_522_p0 <= e_reg_4038;
grp_fu_522_p1 <= i_1_fu_3063_p1;
grp_fu_526_ce <= ap_const_logic_1;
grp_fu_526_p0 <= f_reg_4045;
grp_fu_526_p1 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10;
grp_fu_530_ce <= ap_const_logic_1;
grp_fu_530_p0 <= f_reg_4045;
grp_fu_530_p1 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10;
grp_fu_534_ce <= ap_const_logic_1;
grp_fu_534_p0 <= d_reg_4031;
grp_fu_534_p1 <= i_1_fu_3063_p1;
grp_fu_538_ce <= ap_const_logic_1;
grp_fu_538_p0 <= a_reg_4010;
grp_fu_538_p1 <= k_reg_4059;
grp_fu_542_ce <= ap_const_logic_1;
grp_fu_542_p0 <= j_reg_4052;
grp_fu_542_p1 <= b_reg_4017;
grp_fu_546_ce <= ap_const_logic_1;
grp_fu_546_p0 <= j_reg_4052;
grp_fu_546_p1 <= c_reg_4024;
grp_fu_550_ce <= ap_const_logic_1;
grp_fu_550_p0 <= a_reg_4010;
grp_fu_550_p1 <= l_reg_4066;
grp_fu_554_ce <= ap_const_logic_1;
grp_fu_554_p0 <= ap_reg_ppstg_d_reg_4031_pp0_it19;
grp_fu_554_p1 <= ap_reg_ppstg_h_reg_4080_pp0_it19;
grp_fu_558_ce <= ap_const_logic_1;
grp_fu_558_p0 <= ap_reg_ppstg_e_reg_4038_pp0_it19;
grp_fu_558_p1 <= ap_reg_ppstg_g_reg_4073_pp0_it19;
grp_fu_562_ce <= ap_const_logic_1;
grp_fu_562_p0 <= ap_reg_ppstg_b_reg_4017_pp0_it19;
grp_fu_562_p1 <= ap_reg_ppstg_l_reg_4066_pp0_it19;
grp_fu_566_ce <= ap_const_logic_1;
grp_fu_566_p0 <= ap_reg_ppstg_k_reg_4059_pp0_it19;
grp_fu_566_p1 <= ap_reg_ppstg_c_reg_4024_pp0_it19;
grp_fu_570_ce <= ap_const_logic_1;
grp_fu_570_p0 <= ap_reg_ppstg_a_reg_4010_pp0_it24;
grp_fu_570_p1 <= tmp_1_i_reg_4134;
grp_fu_574_ce <= ap_const_logic_1;
grp_fu_574_p0 <= ap_reg_ppstg_b_reg_4017_pp0_it24;
grp_fu_574_p1 <= tmp_5_i_reg_4140;
grp_fu_578_ce <= ap_const_logic_1;
grp_fu_578_p0 <= ap_reg_ppstg_f_reg_4045_pp0_it24;
grp_fu_578_p1 <= tmp_14_i_reg_4156;
grp_fu_582_ce <= ap_const_logic_1;
grp_fu_582_p0 <= ap_reg_ppstg_e_reg_4038_pp0_it24;
grp_fu_582_p1 <= tmp_18_i_reg_4162;
grp_fu_586_ce <= ap_const_logic_1;
grp_fu_586_p0 <= tmp_14_i_reg_4156;
grp_fu_586_p1 <= ap_reg_ppstg_i_1_reg_4087_pp0_it24;
grp_fu_590_ce <= ap_const_logic_1;
grp_fu_590_p0 <= tmp_18_i_reg_4162;
grp_fu_590_p1 <= ap_reg_ppstg_h_reg_4080_pp0_it24;
grp_fu_594_ce <= ap_const_logic_1;
grp_fu_594_p0 <= ap_reg_ppstg_j_reg_4052_pp0_it24;
grp_fu_594_p1 <= tmp_1_i_reg_4134;
grp_fu_598_ce <= ap_const_logic_1;
grp_fu_598_p0 <= ap_reg_ppstg_k_reg_4059_pp0_it24;
grp_fu_598_p1 <= tmp_5_i_reg_4140;
grp_fu_602_ce <= ap_const_logic_1;
grp_fu_602_p0 <= ap_reg_ppstg_c_reg_4024_pp0_it33;
grp_fu_602_p1 <= tmp_10_i_reg_4218;
grp_fu_606_ce <= ap_const_logic_1;
grp_fu_606_p0 <= ap_reg_ppstg_d_reg_4031_pp0_it33;
grp_fu_606_p1 <= tmp_23_i_reg_4224;
grp_fu_610_ce <= ap_const_logic_1;
grp_fu_610_p0 <= tmp_23_i_reg_4224;
grp_fu_610_p1 <= ap_reg_ppstg_g_reg_4073_pp0_it33;
grp_fu_614_ce <= ap_const_logic_1;
grp_fu_614_p0 <= ap_reg_ppstg_l_reg_4066_pp0_it33;
grp_fu_614_p1 <= tmp_10_i_reg_4218;
grp_fu_618_ce <= ap_const_logic_1;
grp_fu_618_p0 <= tmp_61_neg_i_reg_4297;
grp_fu_618_p1 <= im_reg_4290;
grp_fu_622_ce <= ap_const_logic_1;
grp_fu_622_p0 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77;
grp_fu_622_p1 <= im_reg_4290;
grp_fu_626_ce <= ap_const_logic_1;
grp_fu_626_p0 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77;
grp_fu_626_p1 <= im_reg_4290;
grp_fu_630_ce <= ap_const_logic_1;
grp_fu_630_p0 <= ap_const_lv32_3F800000;
grp_fu_630_p1 <= m_reg_4270;
grp_fu_639_p4 <= data_array_q1(511 downto 480);
h_fu_3059_p1 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10;
i_1_fu_3063_p1 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10;
i_fu_2846_p2 <= std_logic_vector(unsigned(i1_reg_418) + unsigned(ap_const_lv5_1));
-- ins_TREADY assign process. --
ins_TREADY_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st73_fsm_72, ap_sig_cseq_ST_st76_fsm_75, ap_sig_cseq_ST_st91_fsm_90, ap_sig_cseq_ST_st106_fsm_105, ap_sig_cseq_ST_st121_fsm_120, ap_sig_cseq_ST_st136_fsm_135, ap_sig_cseq_ST_st151_fsm_150, ap_sig_cseq_ST_st166_fsm_165, ap_sig_cseq_ST_st181_fsm_180, ap_sig_cseq_ST_st196_fsm_195, ap_sig_cseq_ST_st211_fsm_210, ap_sig_cseq_ST_st226_fsm_225, ap_sig_cseq_ST_st241_fsm_240, ap_sig_cseq_ST_st256_fsm_255, ap_sig_cseq_ST_st271_fsm_270, ap_sig_cseq_ST_st286_fsm_285, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st74_fsm_73, ap_sig_cseq_ST_st77_fsm_76, ap_sig_cseq_ST_st92_fsm_91, ap_sig_cseq_ST_st107_fsm_106, ap_sig_cseq_ST_st122_fsm_121, ap_sig_cseq_ST_st137_fsm_136, ap_sig_cseq_ST_st152_fsm_151, ap_sig_cseq_ST_st167_fsm_166, ap_sig_cseq_ST_st182_fsm_181, ap_sig_cseq_ST_st197_fsm_196, ap_sig_cseq_ST_st212_fsm_211, ap_sig_cseq_ST_st227_fsm_226, ap_sig_cseq_ST_st242_fsm_241, ap_sig_cseq_ST_st257_fsm_256, ap_sig_cseq_ST_st272_fsm_271, ap_sig_cseq_ST_st287_fsm_286, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st78_fsm_77, ap_sig_cseq_ST_st93_fsm_92, ap_sig_cseq_ST_st108_fsm_107, ap_sig_cseq_ST_st123_fsm_122, ap_sig_cseq_ST_st138_fsm_137, ap_sig_cseq_ST_st153_fsm_152, ap_sig_cseq_ST_st168_fsm_167, ap_sig_cseq_ST_st183_fsm_182, ap_sig_cseq_ST_st198_fsm_197, ap_sig_cseq_ST_st213_fsm_212, ap_sig_cseq_ST_st228_fsm_227, ap_sig_cseq_ST_st243_fsm_242, ap_sig_cseq_ST_st258_fsm_257, ap_sig_cseq_ST_st273_fsm_272, ap_sig_cseq_ST_st288_fsm_287, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st94_fsm_93, ap_sig_cseq_ST_st109_fsm_108, ap_sig_cseq_ST_st124_fsm_123, ap_sig_cseq_ST_st139_fsm_138, ap_sig_cseq_ST_st154_fsm_153, ap_sig_cseq_ST_st169_fsm_168, ap_sig_cseq_ST_st184_fsm_183, ap_sig_cseq_ST_st199_fsm_198, ap_sig_cseq_ST_st214_fsm_213, ap_sig_cseq_ST_st229_fsm_228, ap_sig_cseq_ST_st244_fsm_243, ap_sig_cseq_ST_st259_fsm_258, ap_sig_cseq_ST_st274_fsm_273, ap_sig_cseq_ST_st289_fsm_288, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st95_fsm_94, ap_sig_cseq_ST_st110_fsm_109, ap_sig_cseq_ST_st125_fsm_124, ap_sig_cseq_ST_st140_fsm_139, ap_sig_cseq_ST_st155_fsm_154, ap_sig_cseq_ST_st170_fsm_169, ap_sig_cseq_ST_st185_fsm_184, ap_sig_cseq_ST_st200_fsm_199, ap_sig_cseq_ST_st215_fsm_214, ap_sig_cseq_ST_st230_fsm_229, ap_sig_cseq_ST_st245_fsm_244, ap_sig_cseq_ST_st260_fsm_259, ap_sig_cseq_ST_st275_fsm_274, ap_sig_cseq_ST_st290_fsm_289, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st81_fsm_80, ap_sig_cseq_ST_st96_fsm_95, ap_sig_cseq_ST_st111_fsm_110, ap_sig_cseq_ST_st126_fsm_125, ap_sig_cseq_ST_st141_fsm_140, ap_sig_cseq_ST_st156_fsm_155, ap_sig_cseq_ST_st171_fsm_170, ap_sig_cseq_ST_st186_fsm_185, ap_sig_cseq_ST_st201_fsm_200, ap_sig_cseq_ST_st216_fsm_215, ap_sig_cseq_ST_st231_fsm_230, ap_sig_cseq_ST_st246_fsm_245, ap_sig_cseq_ST_st261_fsm_260, ap_sig_cseq_ST_st276_fsm_275, ap_sig_cseq_ST_st291_fsm_290, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st82_fsm_81, ap_sig_cseq_ST_st97_fsm_96, ap_sig_cseq_ST_st112_fsm_111, ap_sig_cseq_ST_st127_fsm_126, ap_sig_cseq_ST_st142_fsm_141, ap_sig_cseq_ST_st157_fsm_156, ap_sig_cseq_ST_st172_fsm_171, ap_sig_cseq_ST_st187_fsm_186, ap_sig_cseq_ST_st202_fsm_201, ap_sig_cseq_ST_st217_fsm_216, ap_sig_cseq_ST_st232_fsm_231, ap_sig_cseq_ST_st247_fsm_246, ap_sig_cseq_ST_st262_fsm_261, ap_sig_cseq_ST_st277_fsm_276, ap_sig_cseq_ST_st292_fsm_291, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st83_fsm_82, ap_sig_cseq_ST_st98_fsm_97, ap_sig_cseq_ST_st113_fsm_112, ap_sig_cseq_ST_st128_fsm_127, ap_sig_cseq_ST_st143_fsm_142, ap_sig_cseq_ST_st158_fsm_157, ap_sig_cseq_ST_st173_fsm_172, ap_sig_cseq_ST_st188_fsm_187, ap_sig_cseq_ST_st203_fsm_202, ap_sig_cseq_ST_st218_fsm_217, ap_sig_cseq_ST_st233_fsm_232, ap_sig_cseq_ST_st248_fsm_247, ap_sig_cseq_ST_st263_fsm_262, ap_sig_cseq_ST_st278_fsm_277, ap_sig_cseq_ST_st293_fsm_292, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st84_fsm_83, ap_sig_cseq_ST_st99_fsm_98, ap_sig_cseq_ST_st114_fsm_113, ap_sig_cseq_ST_st129_fsm_128, ap_sig_cseq_ST_st144_fsm_143, ap_sig_cseq_ST_st159_fsm_158, ap_sig_cseq_ST_st174_fsm_173, ap_sig_cseq_ST_st189_fsm_188, ap_sig_cseq_ST_st204_fsm_203, ap_sig_cseq_ST_st219_fsm_218, ap_sig_cseq_ST_st234_fsm_233, ap_sig_cseq_ST_st249_fsm_248, ap_sig_cseq_ST_st264_fsm_263, ap_sig_cseq_ST_st279_fsm_278, ap_sig_cseq_ST_st294_fsm_293, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st85_fsm_84, ap_sig_cseq_ST_st100_fsm_99, ap_sig_cseq_ST_st115_fsm_114, ap_sig_cseq_ST_st130_fsm_129, ap_sig_cseq_ST_st145_fsm_144, ap_sig_cseq_ST_st160_fsm_159, ap_sig_cseq_ST_st175_fsm_174, ap_sig_cseq_ST_st190_fsm_189, ap_sig_cseq_ST_st205_fsm_204, ap_sig_cseq_ST_st220_fsm_219, ap_sig_cseq_ST_st235_fsm_234, ap_sig_cseq_ST_st250_fsm_249, ap_sig_cseq_ST_st265_fsm_264, ap_sig_cseq_ST_st280_fsm_279, ap_sig_cseq_ST_st295_fsm_294, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st101_fsm_100, ap_sig_cseq_ST_st116_fsm_115, ap_sig_cseq_ST_st131_fsm_130, ap_sig_cseq_ST_st146_fsm_145, ap_sig_cseq_ST_st161_fsm_160, ap_sig_cseq_ST_st176_fsm_175, ap_sig_cseq_ST_st191_fsm_190, ap_sig_cseq_ST_st206_fsm_205, ap_sig_cseq_ST_st221_fsm_220, ap_sig_cseq_ST_st236_fsm_235, ap_sig_cseq_ST_st251_fsm_250, ap_sig_cseq_ST_st266_fsm_265, ap_sig_cseq_ST_st281_fsm_280, ap_sig_cseq_ST_st296_fsm_295, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st102_fsm_101, ap_sig_cseq_ST_st117_fsm_116, ap_sig_cseq_ST_st132_fsm_131, ap_sig_cseq_ST_st147_fsm_146, ap_sig_cseq_ST_st162_fsm_161, ap_sig_cseq_ST_st177_fsm_176, ap_sig_cseq_ST_st192_fsm_191, ap_sig_cseq_ST_st207_fsm_206, ap_sig_cseq_ST_st222_fsm_221, ap_sig_cseq_ST_st237_fsm_236, ap_sig_cseq_ST_st252_fsm_251, ap_sig_cseq_ST_st267_fsm_266, ap_sig_cseq_ST_st282_fsm_281, ap_sig_cseq_ST_st297_fsm_296, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st103_fsm_102, ap_sig_cseq_ST_st118_fsm_117, ap_sig_cseq_ST_st133_fsm_132, ap_sig_cseq_ST_st148_fsm_147, ap_sig_cseq_ST_st163_fsm_162, ap_sig_cseq_ST_st178_fsm_177, ap_sig_cseq_ST_st193_fsm_192, ap_sig_cseq_ST_st208_fsm_207, ap_sig_cseq_ST_st223_fsm_222, ap_sig_cseq_ST_st238_fsm_237, ap_sig_cseq_ST_st253_fsm_252, ap_sig_cseq_ST_st268_fsm_267, ap_sig_cseq_ST_st283_fsm_282, ap_sig_cseq_ST_st298_fsm_297, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st89_fsm_88, ap_sig_cseq_ST_st104_fsm_103, ap_sig_cseq_ST_st119_fsm_118, ap_sig_cseq_ST_st134_fsm_133, ap_sig_cseq_ST_st149_fsm_148, ap_sig_cseq_ST_st164_fsm_163, ap_sig_cseq_ST_st179_fsm_178, ap_sig_cseq_ST_st194_fsm_193, ap_sig_cseq_ST_st209_fsm_208, ap_sig_cseq_ST_st224_fsm_223, ap_sig_cseq_ST_st239_fsm_238, ap_sig_cseq_ST_st254_fsm_253, ap_sig_cseq_ST_st269_fsm_268, ap_sig_cseq_ST_st284_fsm_283, ap_sig_cseq_ST_st299_fsm_298, ap_sig_cseq_ST_st72_fsm_71, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st25_fsm_24, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st31_fsm_30, ap_sig_cseq_ST_st32_fsm_31, ap_sig_cseq_ST_st33_fsm_32, ap_sig_cseq_ST_st34_fsm_33, ap_sig_cseq_ST_st35_fsm_34, ap_sig_cseq_ST_st36_fsm_35, ap_sig_cseq_ST_st37_fsm_36, ap_sig_cseq_ST_st38_fsm_37, ap_sig_cseq_ST_st39_fsm_38, ap_sig_cseq_ST_st40_fsm_39, ap_sig_cseq_ST_st41_fsm_40, ap_sig_cseq_ST_st42_fsm_41, ap_sig_cseq_ST_st43_fsm_42, ap_sig_cseq_ST_st44_fsm_43, ap_sig_cseq_ST_st45_fsm_44, ap_sig_cseq_ST_st46_fsm_45, ap_sig_cseq_ST_st47_fsm_46, ap_sig_cseq_ST_st48_fsm_47, ap_sig_cseq_ST_st49_fsm_48, ap_sig_cseq_ST_st50_fsm_49, ap_sig_cseq_ST_st51_fsm_50, ap_sig_cseq_ST_st52_fsm_51, ap_sig_cseq_ST_st53_fsm_52, ap_sig_cseq_ST_st54_fsm_53, ap_sig_cseq_ST_st55_fsm_54, ap_sig_cseq_ST_st56_fsm_55, ap_sig_cseq_ST_st57_fsm_56, ap_sig_cseq_ST_st58_fsm_57, ap_sig_cseq_ST_st59_fsm_58, ap_sig_cseq_ST_st60_fsm_59, ap_sig_cseq_ST_st61_fsm_60, ap_sig_cseq_ST_st62_fsm_61, ap_sig_cseq_ST_st63_fsm_62, ap_sig_cseq_ST_st64_fsm_63, ap_sig_cseq_ST_st65_fsm_64, ap_sig_cseq_ST_st66_fsm_65, ap_sig_cseq_ST_st67_fsm_66, ap_sig_cseq_ST_st68_fsm_67, ap_sig_cseq_ST_st69_fsm_68, ap_sig_cseq_ST_st70_fsm_69, ap_sig_cseq_ST_st71_fsm_70, ap_sig_cseq_ST_st75_fsm_74, ap_sig_cseq_ST_st90_fsm_89, ap_sig_cseq_ST_st105_fsm_104, ap_sig_cseq_ST_st120_fsm_119, ap_sig_cseq_ST_st135_fsm_134, ap_sig_cseq_ST_st150_fsm_149, ap_sig_cseq_ST_st165_fsm_164, ap_sig_cseq_ST_st180_fsm_179, ap_sig_cseq_ST_st195_fsm_194, ap_sig_cseq_ST_st210_fsm_209, ap_sig_cseq_ST_st225_fsm_224, ap_sig_cseq_ST_st240_fsm_239, ap_sig_cseq_ST_st300_fsm_299, ap_sig_cseq_ST_st255_fsm_254, ap_sig_cseq_ST_st270_fsm_269, ap_sig_cseq_ST_st285_fsm_284)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ins_TVALID = ap_const_logic_0))) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st73_fsm_72)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st76_fsm_75)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st91_fsm_90)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st106_fsm_105)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_120)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st136_fsm_135)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st151_fsm_150)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st166_fsm_165)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st181_fsm_180)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st196_fsm_195)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st211_fsm_210)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st226_fsm_225)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st241_fsm_240)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st256_fsm_255)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st271_fsm_270)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st286_fsm_285)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st74_fsm_73)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st77_fsm_76)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st107_fsm_106)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st137_fsm_136)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st152_fsm_151)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st167_fsm_166)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st182_fsm_181)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st197_fsm_196)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st212_fsm_211)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st227_fsm_226)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st242_fsm_241)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st257_fsm_256)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st272_fsm_271)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st287_fsm_286)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st108_fsm_107)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st138_fsm_137)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st153_fsm_152)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st168_fsm_167)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st183_fsm_182)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st198_fsm_197)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st213_fsm_212)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st228_fsm_227)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st243_fsm_242)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st258_fsm_257)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st273_fsm_272)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st288_fsm_287)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st94_fsm_93)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st109_fsm_108)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st139_fsm_138)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st154_fsm_153)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st169_fsm_168)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st184_fsm_183)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st199_fsm_198)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st214_fsm_213)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st229_fsm_228)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st244_fsm_243)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st259_fsm_258)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st274_fsm_273)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st289_fsm_288)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st95_fsm_94)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st110_fsm_109)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st125_fsm_124)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st155_fsm_154)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st170_fsm_169)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st185_fsm_184)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st200_fsm_199)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st215_fsm_214)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st230_fsm_229)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st245_fsm_244)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st260_fsm_259)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st275_fsm_274)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st290_fsm_289)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st96_fsm_95)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st111_fsm_110)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st126_fsm_125)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st156_fsm_155)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st171_fsm_170)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st186_fsm_185)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st201_fsm_200)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st216_fsm_215)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st231_fsm_230)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st246_fsm_245)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st261_fsm_260)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st276_fsm_275)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st291_fsm_290)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st112_fsm_111)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st127_fsm_126)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st157_fsm_156)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st172_fsm_171)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st187_fsm_186)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st202_fsm_201)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st217_fsm_216)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st232_fsm_231)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st247_fsm_246)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st262_fsm_261)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st277_fsm_276)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st292_fsm_291)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st113_fsm_112)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st128_fsm_127)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st158_fsm_157)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st173_fsm_172)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st188_fsm_187)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st203_fsm_202)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st218_fsm_217)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st233_fsm_232)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st248_fsm_247)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st263_fsm_262)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st278_fsm_277)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st293_fsm_292)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st114_fsm_113)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st144_fsm_143)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st159_fsm_158)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st174_fsm_173)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st189_fsm_188)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st204_fsm_203)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st219_fsm_218)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st234_fsm_233)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st249_fsm_248)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st264_fsm_263)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st279_fsm_278)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st294_fsm_293)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st85_fsm_84)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st100_fsm_99)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_114)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st130_fsm_129)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st145_fsm_144)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st160_fsm_159)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st175_fsm_174)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st190_fsm_189)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st205_fsm_204)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st220_fsm_219)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st235_fsm_234)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st250_fsm_249)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st265_fsm_264)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st280_fsm_279)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st295_fsm_294)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st101_fsm_100)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_115)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st131_fsm_130)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st161_fsm_160)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st176_fsm_175)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st191_fsm_190)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st206_fsm_205)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st221_fsm_220)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st236_fsm_235)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st251_fsm_250)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st266_fsm_265)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st281_fsm_280)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st296_fsm_295)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st102_fsm_101)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st132_fsm_131)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st162_fsm_161)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st177_fsm_176)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st192_fsm_191)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st207_fsm_206)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st222_fsm_221)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st237_fsm_236)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st252_fsm_251)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st267_fsm_266)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st282_fsm_281)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st297_fsm_296)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st103_fsm_102)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st133_fsm_132)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st163_fsm_162)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st178_fsm_177)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st193_fsm_192)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st208_fsm_207)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st223_fsm_222)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st238_fsm_237)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st253_fsm_252)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st268_fsm_267)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st283_fsm_282)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st298_fsm_297)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st104_fsm_103)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_118)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st134_fsm_133)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st164_fsm_163)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st179_fsm_178)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st194_fsm_193)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st209_fsm_208)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st224_fsm_223)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st239_fsm_238)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st254_fsm_253)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st269_fsm_268)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st284_fsm_283)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st299_fsm_298)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st72_fsm_71)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st31_fsm_30)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st32_fsm_31)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st33_fsm_32)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st34_fsm_33)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st35_fsm_34)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st36_fsm_35)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st37_fsm_36)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st38_fsm_37)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st39_fsm_38)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st40_fsm_39)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st41_fsm_40)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st43_fsm_42)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st44_fsm_43)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st45_fsm_44)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st46_fsm_45)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st49_fsm_48)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st50_fsm_49)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st51_fsm_50)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st52_fsm_51)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st54_fsm_53)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st55_fsm_54)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st56_fsm_55)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st57_fsm_56)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st58_fsm_57)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st59_fsm_58)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st60_fsm_59)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st61_fsm_60)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st62_fsm_61)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st63_fsm_62)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st64_fsm_63)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st65_fsm_64)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st66_fsm_65)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st67_fsm_66)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st68_fsm_67)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st69_fsm_68)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st70_fsm_69)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st71_fsm_70)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st75_fsm_74)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st90_fsm_89)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st105_fsm_104)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_119)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st135_fsm_134)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st165_fsm_164)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st180_fsm_179)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st195_fsm_194)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st210_fsm_209)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st225_fsm_224)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st240_fsm_239)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st300_fsm_299)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st255_fsm_254)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st270_fsm_269)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st285_fsm_284)))) then
ins_TREADY <= ap_const_logic_1;
else
ins_TREADY <= ap_const_logic_0;
end if;
end process;
ins_data_tmp_load_100_toint_fu_1361_p1 <= reg_709;
ins_data_tmp_load_101_toint_fu_1365_p1 <= reg_713;
ins_data_tmp_load_102_toint_fu_1369_p1 <= reg_717;
ins_data_tmp_load_103_toint_fu_1373_p1 <= reg_721;
ins_data_tmp_load_104_toint_fu_1377_p1 <= ins_TDATA;
ins_data_tmp_load_105_toint_fu_1428_p1 <= reg_669;
ins_data_tmp_load_106_toint_fu_1432_p1 <= reg_673;
ins_data_tmp_load_107_toint_fu_1436_p1 <= reg_677;
ins_data_tmp_load_108_toint_fu_1440_p1 <= reg_681;
ins_data_tmp_load_109_toint_fu_1444_p1 <= reg_685;
ins_data_tmp_load_10_toint_fu_777_p1 <= reg_709;
ins_data_tmp_load_110_toint_fu_1448_p1 <= reg_689;
ins_data_tmp_load_111_toint_fu_1452_p1 <= reg_693;
ins_data_tmp_load_112_toint_fu_1456_p1 <= reg_697;
ins_data_tmp_load_113_toint_fu_1460_p1 <= reg_701;
ins_data_tmp_load_114_toint_fu_1464_p1 <= reg_705;
ins_data_tmp_load_115_toint_fu_1468_p1 <= reg_709;
ins_data_tmp_load_116_toint_fu_1472_p1 <= reg_713;
ins_data_tmp_load_117_toint_fu_1476_p1 <= reg_717;
ins_data_tmp_load_118_toint_fu_1480_p1 <= reg_721;
ins_data_tmp_load_119_toint_fu_1484_p1 <= ins_TDATA;
ins_data_tmp_load_11_toint_fu_781_p1 <= reg_713;
ins_data_tmp_load_120_toint_fu_1535_p1 <= reg_669;
ins_data_tmp_load_121_toint_fu_1539_p1 <= reg_673;
ins_data_tmp_load_122_toint_fu_1543_p1 <= reg_677;
ins_data_tmp_load_123_toint_fu_1547_p1 <= reg_681;
ins_data_tmp_load_124_toint_fu_1551_p1 <= reg_685;
ins_data_tmp_load_125_toint_fu_1555_p1 <= reg_689;
ins_data_tmp_load_126_toint_fu_1559_p1 <= reg_693;
ins_data_tmp_load_127_toint_fu_1563_p1 <= reg_697;
ins_data_tmp_load_128_toint_fu_1567_p1 <= reg_701;
ins_data_tmp_load_129_toint_fu_1571_p1 <= reg_705;
ins_data_tmp_load_12_toint_fu_785_p1 <= reg_717;
ins_data_tmp_load_130_toint_fu_1575_p1 <= reg_709;
ins_data_tmp_load_131_toint_fu_1579_p1 <= reg_713;
ins_data_tmp_load_132_toint_fu_1583_p1 <= reg_717;
ins_data_tmp_load_133_toint_fu_1587_p1 <= reg_721;
ins_data_tmp_load_134_toint_fu_1591_p1 <= ins_TDATA;
ins_data_tmp_load_135_toint_fu_1642_p1 <= reg_669;
ins_data_tmp_load_136_toint_fu_1646_p1 <= reg_673;
ins_data_tmp_load_137_toint_fu_1650_p1 <= reg_677;
ins_data_tmp_load_138_toint_fu_1654_p1 <= reg_681;
ins_data_tmp_load_139_toint_fu_1658_p1 <= reg_685;
ins_data_tmp_load_13_toint_fu_789_p1 <= reg_721;
ins_data_tmp_load_140_toint_fu_1662_p1 <= reg_689;
ins_data_tmp_load_141_toint_fu_1666_p1 <= reg_693;
ins_data_tmp_load_142_toint_fu_1670_p1 <= reg_697;
ins_data_tmp_load_143_toint_fu_1674_p1 <= reg_701;
ins_data_tmp_load_144_toint_fu_1678_p1 <= reg_705;
ins_data_tmp_load_145_toint_fu_1682_p1 <= reg_709;
ins_data_tmp_load_146_toint_fu_1686_p1 <= reg_713;
ins_data_tmp_load_147_toint_fu_1690_p1 <= reg_717;
ins_data_tmp_load_148_toint_fu_1694_p1 <= reg_721;
ins_data_tmp_load_149_toint_fu_1698_p1 <= ins_TDATA;
ins_data_tmp_load_14_toint_fu_793_p1 <= ins_data_val14_reg_3415;
ins_data_tmp_load_150_toint_fu_1749_p1 <= reg_669;
ins_data_tmp_load_151_toint_fu_1753_p1 <= reg_673;
ins_data_tmp_load_152_toint_fu_1757_p1 <= reg_677;
ins_data_tmp_load_153_toint_fu_1761_p1 <= reg_681;
ins_data_tmp_load_154_toint_fu_1765_p1 <= reg_685;
ins_data_tmp_load_155_toint_fu_1769_p1 <= reg_689;
ins_data_tmp_load_156_toint_fu_1773_p1 <= reg_693;
ins_data_tmp_load_157_toint_fu_1777_p1 <= reg_697;
ins_data_tmp_load_158_toint_fu_1781_p1 <= reg_701;
ins_data_tmp_load_159_toint_fu_1785_p1 <= reg_705;
ins_data_tmp_load_15_toint_fu_1030_p1 <= ins_data_val15_reg_3420;
ins_data_tmp_load_160_toint_fu_1789_p1 <= reg_709;
ins_data_tmp_load_161_toint_fu_1793_p1 <= reg_713;
ins_data_tmp_load_162_toint_fu_1797_p1 <= reg_717;
ins_data_tmp_load_163_toint_fu_1801_p1 <= reg_721;
ins_data_tmp_load_164_toint_fu_1805_p1 <= ins_TDATA;
ins_data_tmp_load_165_toint_fu_1856_p1 <= reg_669;
ins_data_tmp_load_166_toint_fu_1860_p1 <= reg_673;
ins_data_tmp_load_167_toint_fu_1864_p1 <= reg_677;
ins_data_tmp_load_168_toint_fu_1868_p1 <= reg_681;
ins_data_tmp_load_169_toint_fu_1872_p1 <= reg_685;
ins_data_tmp_load_16_toint_fu_1033_p1 <= ins_data_val16_reg_3425;
ins_data_tmp_load_170_toint_fu_1876_p1 <= reg_689;
ins_data_tmp_load_171_toint_fu_1880_p1 <= reg_693;
ins_data_tmp_load_172_toint_fu_1884_p1 <= reg_697;
ins_data_tmp_load_173_toint_fu_1888_p1 <= reg_701;
ins_data_tmp_load_174_toint_fu_1892_p1 <= reg_705;
ins_data_tmp_load_175_toint_fu_1896_p1 <= reg_709;
ins_data_tmp_load_176_toint_fu_1900_p1 <= reg_713;
ins_data_tmp_load_177_toint_fu_1904_p1 <= reg_717;
ins_data_tmp_load_178_toint_fu_1908_p1 <= reg_721;
ins_data_tmp_load_179_toint_fu_1912_p1 <= ins_TDATA;
ins_data_tmp_load_17_toint_fu_1036_p1 <= ins_data_val17_reg_3430;
ins_data_tmp_load_180_toint_fu_1963_p1 <= reg_669;
ins_data_tmp_load_181_toint_fu_1967_p1 <= reg_673;
ins_data_tmp_load_182_toint_fu_1971_p1 <= reg_677;
ins_data_tmp_load_183_toint_fu_1975_p1 <= reg_681;
ins_data_tmp_load_184_toint_fu_1979_p1 <= reg_685;
ins_data_tmp_load_185_toint_fu_1983_p1 <= reg_689;
ins_data_tmp_load_186_toint_fu_1987_p1 <= reg_693;
ins_data_tmp_load_187_toint_fu_1991_p1 <= reg_697;
ins_data_tmp_load_188_toint_fu_1995_p1 <= reg_701;
ins_data_tmp_load_189_toint_fu_1999_p1 <= reg_705;
ins_data_tmp_load_18_toint_fu_1039_p1 <= ins_data_val18_reg_3435;
ins_data_tmp_load_190_toint_fu_2003_p1 <= reg_709;
ins_data_tmp_load_191_toint_fu_2007_p1 <= reg_713;
ins_data_tmp_load_192_toint_fu_2011_p1 <= reg_717;
ins_data_tmp_load_193_toint_fu_2015_p1 <= reg_721;
ins_data_tmp_load_194_toint_fu_2019_p1 <= ins_TDATA;
ins_data_tmp_load_195_toint_fu_2070_p1 <= reg_669;
ins_data_tmp_load_196_toint_fu_2074_p1 <= reg_673;
ins_data_tmp_load_197_toint_fu_2078_p1 <= reg_677;
ins_data_tmp_load_198_toint_fu_2082_p1 <= reg_681;
ins_data_tmp_load_199_toint_fu_2086_p1 <= reg_685;
ins_data_tmp_load_19_toint_fu_1042_p1 <= ins_data_val19_reg_3440;
ins_data_tmp_load_1_toint_fu_741_p1 <= reg_673;
ins_data_tmp_load_200_toint_fu_2090_p1 <= reg_689;
ins_data_tmp_load_201_toint_fu_2094_p1 <= reg_693;
ins_data_tmp_load_202_toint_fu_2098_p1 <= reg_697;
ins_data_tmp_load_203_toint_fu_2102_p1 <= reg_701;
ins_data_tmp_load_204_toint_fu_2106_p1 <= reg_705;
ins_data_tmp_load_205_toint_fu_2110_p1 <= reg_709;
ins_data_tmp_load_206_toint_fu_2114_p1 <= reg_713;
ins_data_tmp_load_207_toint_fu_2118_p1 <= reg_717;
ins_data_tmp_load_208_toint_fu_2122_p1 <= reg_721;
ins_data_tmp_load_209_toint_fu_2126_p1 <= ins_TDATA;
ins_data_tmp_load_20_toint_fu_1045_p1 <= ins_data_val20_reg_3445;
ins_data_tmp_load_210_toint_fu_2177_p1 <= reg_669;
ins_data_tmp_load_211_toint_fu_2181_p1 <= reg_673;
ins_data_tmp_load_212_toint_fu_2185_p1 <= reg_677;
ins_data_tmp_load_213_toint_fu_2189_p1 <= reg_681;
ins_data_tmp_load_214_toint_fu_2193_p1 <= reg_685;
ins_data_tmp_load_215_toint_fu_2197_p1 <= reg_689;
ins_data_tmp_load_216_toint_fu_2201_p1 <= reg_693;
ins_data_tmp_load_217_toint_fu_2205_p1 <= reg_697;
ins_data_tmp_load_218_toint_fu_2209_p1 <= reg_701;
ins_data_tmp_load_219_toint_fu_2213_p1 <= reg_705;
ins_data_tmp_load_21_toint_fu_1048_p1 <= ins_data_val21_reg_3450;
ins_data_tmp_load_220_toint_fu_2217_p1 <= reg_709;
ins_data_tmp_load_221_toint_fu_2221_p1 <= reg_713;
ins_data_tmp_load_222_toint_fu_2225_p1 <= reg_717;
ins_data_tmp_load_223_toint_fu_2229_p1 <= reg_721;
ins_data_tmp_load_224_toint_fu_2233_p1 <= ins_TDATA;
ins_data_tmp_load_225_toint_fu_2284_p1 <= reg_669;
ins_data_tmp_load_226_toint_fu_2288_p1 <= reg_673;
ins_data_tmp_load_227_toint_fu_2292_p1 <= reg_677;
ins_data_tmp_load_228_toint_fu_2296_p1 <= reg_681;
ins_data_tmp_load_229_toint_fu_2300_p1 <= reg_685;
ins_data_tmp_load_22_toint_fu_1051_p1 <= ins_data_val22_reg_3455;
ins_data_tmp_load_230_toint_fu_2304_p1 <= reg_689;
ins_data_tmp_load_231_toint_fu_2308_p1 <= reg_693;
ins_data_tmp_load_232_toint_fu_2312_p1 <= reg_697;
ins_data_tmp_load_233_toint_fu_2316_p1 <= reg_701;
ins_data_tmp_load_234_toint_fu_2320_p1 <= reg_705;
ins_data_tmp_load_235_toint_fu_2324_p1 <= reg_709;
ins_data_tmp_load_236_toint_fu_2328_p1 <= reg_713;
ins_data_tmp_load_237_toint_fu_2332_p1 <= reg_717;
ins_data_tmp_load_238_toint_fu_2336_p1 <= reg_721;
ins_data_tmp_load_239_toint_fu_2340_p1 <= ins_TDATA;
ins_data_tmp_load_23_toint_fu_1054_p1 <= ins_data_val23_reg_3460;
ins_data_tmp_load_240_toint_fu_2391_p1 <= reg_669;
ins_data_tmp_load_241_toint_fu_2395_p1 <= reg_673;
ins_data_tmp_load_242_toint_fu_2399_p1 <= reg_677;
ins_data_tmp_load_243_toint_fu_2403_p1 <= reg_681;
ins_data_tmp_load_244_toint_fu_2407_p1 <= reg_685;
ins_data_tmp_load_245_toint_fu_2411_p1 <= reg_689;
ins_data_tmp_load_246_toint_fu_2415_p1 <= reg_693;
ins_data_tmp_load_247_toint_fu_2419_p1 <= reg_697;
ins_data_tmp_load_248_toint_fu_2423_p1 <= reg_701;
ins_data_tmp_load_249_toint_fu_2427_p1 <= reg_705;
ins_data_tmp_load_24_toint_fu_1057_p1 <= ins_data_val24_reg_3465;
ins_data_tmp_load_250_toint_fu_2431_p1 <= reg_709;
ins_data_tmp_load_251_toint_fu_2435_p1 <= reg_713;
ins_data_tmp_load_252_toint_fu_2439_p1 <= reg_717;
ins_data_tmp_load_253_toint_fu_2443_p1 <= reg_721;
ins_data_tmp_load_254_toint_fu_2447_p1 <= ins_TDATA;
ins_data_tmp_load_255_toint_fu_2498_p1 <= reg_669;
ins_data_tmp_load_256_toint_fu_2502_p1 <= reg_673;
ins_data_tmp_load_257_toint_fu_2506_p1 <= reg_677;
ins_data_tmp_load_258_toint_fu_2510_p1 <= reg_681;
ins_data_tmp_load_259_toint_fu_2514_p1 <= reg_685;
ins_data_tmp_load_25_toint_fu_1060_p1 <= ins_data_val25_reg_3470;
ins_data_tmp_load_260_toint_fu_2518_p1 <= reg_689;
ins_data_tmp_load_261_toint_fu_2522_p1 <= reg_693;
ins_data_tmp_load_262_toint_fu_2526_p1 <= reg_697;
ins_data_tmp_load_263_toint_fu_2530_p1 <= reg_701;
ins_data_tmp_load_264_toint_fu_2534_p1 <= reg_705;
ins_data_tmp_load_265_toint_fu_2538_p1 <= reg_709;
ins_data_tmp_load_266_toint_fu_2542_p1 <= reg_713;
ins_data_tmp_load_267_toint_fu_2546_p1 <= reg_717;
ins_data_tmp_load_268_toint_fu_2550_p1 <= reg_721;
ins_data_tmp_load_269_toint_fu_2554_p1 <= ins_TDATA;
ins_data_tmp_load_26_toint_fu_1063_p1 <= ins_data_val26_reg_3475;
ins_data_tmp_load_270_toint_fu_2604_p1 <= reg_669;
ins_data_tmp_load_271_toint_fu_2608_p1 <= reg_673;
ins_data_tmp_load_272_toint_fu_2612_p1 <= reg_677;
ins_data_tmp_load_273_toint_fu_2616_p1 <= reg_681;
ins_data_tmp_load_274_toint_fu_2620_p1 <= reg_685;
ins_data_tmp_load_275_toint_fu_2624_p1 <= reg_689;
ins_data_tmp_load_276_toint_fu_2628_p1 <= reg_693;
ins_data_tmp_load_277_toint_fu_2632_p1 <= reg_697;
ins_data_tmp_load_278_toint_fu_2636_p1 <= reg_701;
ins_data_tmp_load_279_toint_fu_2640_p1 <= reg_705;
ins_data_tmp_load_27_toint_fu_1066_p1 <= ins_data_val27_reg_3480;
ins_data_tmp_load_280_toint_fu_2644_p1 <= reg_709;
ins_data_tmp_load_281_toint_fu_2648_p1 <= reg_713;
ins_data_tmp_load_282_toint_fu_2652_p1 <= reg_717;
ins_data_tmp_load_283_toint_fu_2656_p1 <= reg_721;
ins_data_tmp_load_284_toint_fu_2660_p1 <= ins_TDATA;
ins_data_tmp_load_285_toint_fu_2710_p1 <= reg_669;
ins_data_tmp_load_286_toint_fu_2714_p1 <= reg_673;
ins_data_tmp_load_287_toint_fu_2718_p1 <= reg_677;
ins_data_tmp_load_288_toint_fu_2722_p1 <= reg_681;
ins_data_tmp_load_289_toint_fu_2726_p1 <= reg_685;
ins_data_tmp_load_28_toint_fu_1069_p1 <= ins_data_val28_reg_3485;
ins_data_tmp_load_290_toint_fu_2730_p1 <= reg_689;
ins_data_tmp_load_291_toint_fu_2734_p1 <= reg_693;
ins_data_tmp_load_292_toint_fu_2738_p1 <= reg_697;
ins_data_tmp_load_293_toint_fu_2742_p1 <= reg_701;
ins_data_tmp_load_294_toint_fu_2746_p1 <= reg_705;
ins_data_tmp_load_295_toint_fu_2750_p1 <= reg_709;
ins_data_tmp_load_296_toint_fu_2754_p1 <= reg_713;
ins_data_tmp_load_297_toint_fu_2758_p1 <= reg_717;
ins_data_tmp_load_298_toint_fu_2762_p1 <= reg_721;
ins_data_tmp_load_299_toint_fu_2790_p1 <= ins_TDATA;
ins_data_tmp_load_29_toint_fu_1072_p1 <= ins_data_val29_reg_3490;
ins_data_tmp_load_2_toint_fu_745_p1 <= reg_677;
ins_data_tmp_load_30_toint_fu_843_p1 <= ins_data_val30_reg_3495;
ins_data_tmp_load_31_toint_fu_846_p1 <= ins_data_val31_reg_3500;
ins_data_tmp_load_32_toint_fu_849_p1 <= ins_data_val32_reg_3505;
ins_data_tmp_load_33_toint_fu_852_p1 <= ins_data_val33_reg_3510;
ins_data_tmp_load_34_toint_fu_855_p1 <= ins_data_val34_reg_3515;
ins_data_tmp_load_35_toint_fu_858_p1 <= ins_data_val35_reg_3520;
ins_data_tmp_load_36_toint_fu_861_p1 <= ins_data_val36_reg_3525;
ins_data_tmp_load_37_toint_fu_864_p1 <= ins_data_val37_reg_3530;
ins_data_tmp_load_38_toint_fu_867_p1 <= ins_data_val38_reg_3535;
ins_data_tmp_load_39_toint_fu_870_p1 <= ins_data_val39_reg_3540;
ins_data_tmp_load_3_toint_fu_749_p1 <= reg_681;
ins_data_tmp_load_40_toint_fu_873_p1 <= ins_data_val40_reg_3545;
ins_data_tmp_load_41_toint_fu_876_p1 <= ins_data_val41_reg_3550;
ins_data_tmp_load_42_toint_fu_879_p1 <= ins_data_val42_reg_3555;
ins_data_tmp_load_43_toint_fu_882_p1 <= ins_data_val43_reg_3560;
ins_data_tmp_load_44_toint_fu_885_p1 <= ins_data_val44_reg_3565;
ins_data_tmp_load_45_toint_fu_1122_p1 <= ins_data_val45_reg_3570;
ins_data_tmp_load_46_toint_fu_1125_p1 <= ins_data_val46_reg_3575;
ins_data_tmp_load_47_toint_fu_1128_p1 <= ins_data_val47_reg_3580;
ins_data_tmp_load_48_toint_fu_1131_p1 <= ins_data_val48_reg_3585;
ins_data_tmp_load_49_toint_fu_1134_p1 <= ins_data_val49_reg_3590;
ins_data_tmp_load_4_toint_fu_753_p1 <= reg_685;
ins_data_tmp_load_50_toint_fu_1137_p1 <= ins_data_val50_reg_3595;
ins_data_tmp_load_51_toint_fu_1140_p1 <= ins_data_val51_reg_3600;
ins_data_tmp_load_52_toint_fu_1143_p1 <= ins_data_val52_reg_3605;
ins_data_tmp_load_53_toint_fu_1146_p1 <= ins_data_val53_reg_3610;
ins_data_tmp_load_54_toint_fu_1149_p1 <= ins_data_val54_reg_3615;
ins_data_tmp_load_55_toint_fu_1152_p1 <= ins_data_val55_reg_3620;
ins_data_tmp_load_56_toint_fu_1155_p1 <= ins_data_val56_reg_3625;
ins_data_tmp_load_57_toint_fu_1158_p1 <= ins_data_val57_reg_3630;
ins_data_tmp_load_58_toint_fu_1161_p1 <= ins_data_val58_reg_3635;
ins_data_tmp_load_59_toint_fu_1164_p1 <= ins_data_val59_reg_3640;
ins_data_tmp_load_5_toint_fu_757_p1 <= reg_689;
ins_data_tmp_load_60_toint_fu_935_p1 <= ins_data_val60_reg_3645;
ins_data_tmp_load_61_toint_fu_938_p1 <= ins_data_val61_reg_3650;
ins_data_tmp_load_62_toint_fu_941_p1 <= ins_data_val62_reg_3655;
ins_data_tmp_load_63_toint_fu_944_p1 <= ins_data_val63_reg_3660;
ins_data_tmp_load_64_toint_fu_947_p1 <= ins_data_val64_reg_3665;
ins_data_tmp_load_65_toint_fu_950_p1 <= ins_data_val65_reg_3670;
ins_data_tmp_load_66_toint_fu_953_p1 <= ins_data_val66_reg_3675;
ins_data_tmp_load_67_toint_fu_956_p1 <= ins_data_val67_reg_3680;
ins_data_tmp_load_68_toint_fu_959_p1 <= ins_data_val68_reg_3685;
ins_data_tmp_load_69_toint_fu_962_p1 <= ins_data_val69_reg_3690;
ins_data_tmp_load_6_toint_fu_761_p1 <= reg_693;
ins_data_tmp_load_70_toint_fu_965_p1 <= ins_data_val70_reg_3695;
ins_data_tmp_load_71_toint_fu_968_p1 <= ins_data_val71_reg_3706;
ins_data_tmp_load_72_toint_fu_971_p1 <= reg_669;
ins_data_tmp_load_73_toint_fu_975_p1 <= reg_673;
ins_data_tmp_load_74_toint_fu_979_p1 <= ins_TDATA;
ins_data_tmp_load_75_toint_fu_1214_p1 <= reg_669;
ins_data_tmp_load_76_toint_fu_1218_p1 <= reg_673;
ins_data_tmp_load_77_toint_fu_1222_p1 <= reg_677;
ins_data_tmp_load_78_toint_fu_1226_p1 <= reg_681;
ins_data_tmp_load_79_toint_fu_1230_p1 <= reg_685;
ins_data_tmp_load_7_toint_fu_765_p1 <= reg_697;
ins_data_tmp_load_80_toint_fu_1234_p1 <= reg_689;
ins_data_tmp_load_81_toint_fu_1238_p1 <= reg_693;
ins_data_tmp_load_82_toint_fu_1242_p1 <= reg_697;
ins_data_tmp_load_83_toint_fu_1246_p1 <= reg_701;
ins_data_tmp_load_84_toint_fu_1250_p1 <= reg_705;
ins_data_tmp_load_85_toint_fu_1254_p1 <= reg_709;
ins_data_tmp_load_86_toint_fu_1258_p1 <= reg_713;
ins_data_tmp_load_87_toint_fu_1262_p1 <= reg_717;
ins_data_tmp_load_88_toint_fu_1266_p1 <= reg_721;
ins_data_tmp_load_89_toint_fu_1270_p1 <= ins_TDATA;
ins_data_tmp_load_8_toint_fu_769_p1 <= reg_701;
ins_data_tmp_load_90_toint_fu_1321_p1 <= reg_669;
ins_data_tmp_load_91_toint_fu_1325_p1 <= reg_673;
ins_data_tmp_load_92_toint_fu_1329_p1 <= reg_677;
ins_data_tmp_load_93_toint_fu_1333_p1 <= reg_681;
ins_data_tmp_load_94_toint_fu_1337_p1 <= reg_685;
ins_data_tmp_load_95_toint_fu_1341_p1 <= reg_689;
ins_data_tmp_load_96_toint_fu_1345_p1 <= reg_693;
ins_data_tmp_load_97_toint_fu_1349_p1 <= reg_697;
ins_data_tmp_load_98_toint_fu_1353_p1 <= reg_701;
ins_data_tmp_load_99_toint_fu_1357_p1 <= reg_705;
ins_data_tmp_load_9_toint_fu_773_p1 <= reg_705;
ins_data_tmp_load_toint_fu_737_p1 <= reg_669;
-- outs_TDATA assign process. --
outs_TDATA_assign_proc : process(ap_sig_cseq_ST_st386_fsm_302, ap_sig_cseq_ST_st389_fsm_305, ap_sig_cseq_ST_st392_fsm_308, ap_sig_cseq_ST_st395_fsm_311, ap_sig_cseq_ST_st398_fsm_314, ap_sig_cseq_ST_st401_fsm_317, ap_sig_cseq_ST_st404_fsm_320, ap_sig_cseq_ST_st407_fsm_323, ap_sig_cseq_ST_st410_fsm_326, ap_sig_cseq_ST_st413_fsm_329, ap_sig_cseq_ST_st416_fsm_332, ap_sig_cseq_ST_st419_fsm_335, ap_sig_cseq_ST_st422_fsm_338, ap_sig_cseq_ST_st425_fsm_341, ap_sig_cseq_ST_st428_fsm_344, ap_sig_cseq_ST_st431_fsm_347, ap_sig_cseq_ST_st434_fsm_350, ap_sig_cseq_ST_st437_fsm_353, ap_sig_cseq_ST_st440_fsm_356, ap_sig_cseq_ST_st443_fsm_359, t_load_fu_3115_p1, gamma_load_fu_3120_p1, ap_sig_cseq_ST_st387_fsm_303, beta_load_fu_3125_p1, ap_sig_cseq_ST_st388_fsm_304, t_load_s_fu_3130_p1, gamma_load_s_fu_3135_p1, ap_sig_cseq_ST_st390_fsm_306, beta_load_s_fu_3140_p1, ap_sig_cseq_ST_st391_fsm_307, t_load_1_fu_3145_p1, gamma_load_1_fu_3150_p1, ap_sig_cseq_ST_st393_fsm_309, beta_load_1_fu_3155_p1, ap_sig_cseq_ST_st394_fsm_310, t_load_2_fu_3160_p1, gamma_load_2_fu_3165_p1, ap_sig_cseq_ST_st396_fsm_312, beta_load_2_fu_3170_p1, ap_sig_cseq_ST_st397_fsm_313, t_load_3_fu_3175_p1, gamma_load_3_fu_3180_p1, ap_sig_cseq_ST_st399_fsm_315, beta_load_3_fu_3185_p1, ap_sig_cseq_ST_st400_fsm_316, t_load_4_fu_3190_p1, gamma_load_4_fu_3195_p1, ap_sig_cseq_ST_st402_fsm_318, beta_load_4_fu_3200_p1, ap_sig_cseq_ST_st403_fsm_319, t_load_5_fu_3205_p1, gamma_load_5_fu_3210_p1, ap_sig_cseq_ST_st405_fsm_321, beta_load_5_fu_3215_p1, ap_sig_cseq_ST_st406_fsm_322, t_load_6_fu_3220_p1, gamma_load_6_fu_3225_p1, ap_sig_cseq_ST_st408_fsm_324, beta_load_6_fu_3230_p1, ap_sig_cseq_ST_st409_fsm_325, t_load_7_fu_3235_p1, gamma_load_7_fu_3240_p1, ap_sig_cseq_ST_st411_fsm_327, beta_load_7_fu_3245_p1, ap_sig_cseq_ST_st412_fsm_328, t_load_8_fu_3250_p1, gamma_load_8_fu_3255_p1, ap_sig_cseq_ST_st414_fsm_330, beta_load_8_fu_3260_p1, ap_sig_cseq_ST_st415_fsm_331, t_load_9_fu_3265_p1, gamma_load_9_fu_3270_p1, ap_sig_cseq_ST_st417_fsm_333, beta_load_9_fu_3275_p1, ap_sig_cseq_ST_st418_fsm_334, t_load_10_fu_3280_p1, gamma_load_10_fu_3285_p1, ap_sig_cseq_ST_st420_fsm_336, beta_load_10_fu_3290_p1, ap_sig_cseq_ST_st421_fsm_337, t_load_11_fu_3295_p1, gamma_load_11_fu_3300_p1, ap_sig_cseq_ST_st423_fsm_339, beta_load_11_fu_3305_p1, ap_sig_cseq_ST_st424_fsm_340, t_load_12_fu_3310_p1, gamma_load_12_fu_3315_p1, ap_sig_cseq_ST_st426_fsm_342, beta_load_12_fu_3320_p1, ap_sig_cseq_ST_st427_fsm_343, t_load_13_fu_3325_p1, gamma_load_13_fu_3330_p1, ap_sig_cseq_ST_st429_fsm_345, beta_load_13_fu_3335_p1, ap_sig_cseq_ST_st430_fsm_346, t_load_14_fu_3340_p1, gamma_load_14_fu_3345_p1, ap_sig_cseq_ST_st432_fsm_348, beta_load_14_fu_3350_p1, ap_sig_cseq_ST_st433_fsm_349, t_load_15_fu_3355_p1, gamma_load_15_fu_3360_p1, ap_sig_cseq_ST_st435_fsm_351, beta_load_15_fu_3365_p1, ap_sig_cseq_ST_st436_fsm_352, t_load_16_fu_3370_p1, gamma_load_16_fu_3375_p1, ap_sig_cseq_ST_st438_fsm_354, beta_load_16_fu_3380_p1, ap_sig_cseq_ST_st439_fsm_355, t_load_17_fu_3385_p1, gamma_load_17_fu_3390_p1, ap_sig_cseq_ST_st441_fsm_357, beta_load_17_fu_3395_p1, ap_sig_cseq_ST_st442_fsm_358, t_load_18_fu_3400_p1, gamma_load_18_fu_3405_p1, ap_sig_cseq_ST_st444_fsm_360, beta_load_18_fu_3410_p1, ap_sig_cseq_ST_st445_fsm_361)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361)) then
outs_TDATA <= beta_load_18_fu_3410_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360)) then
outs_TDATA <= gamma_load_18_fu_3405_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359)) then
outs_TDATA <= t_load_18_fu_3400_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358)) then
outs_TDATA <= beta_load_17_fu_3395_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357)) then
outs_TDATA <= gamma_load_17_fu_3390_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356)) then
outs_TDATA <= t_load_17_fu_3385_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355)) then
outs_TDATA <= beta_load_16_fu_3380_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354)) then
outs_TDATA <= gamma_load_16_fu_3375_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353)) then
outs_TDATA <= t_load_16_fu_3370_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352)) then
outs_TDATA <= beta_load_15_fu_3365_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351)) then
outs_TDATA <= gamma_load_15_fu_3360_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350)) then
outs_TDATA <= t_load_15_fu_3355_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349)) then
outs_TDATA <= beta_load_14_fu_3350_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348)) then
outs_TDATA <= gamma_load_14_fu_3345_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347)) then
outs_TDATA <= t_load_14_fu_3340_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346)) then
outs_TDATA <= beta_load_13_fu_3335_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345)) then
outs_TDATA <= gamma_load_13_fu_3330_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344)) then
outs_TDATA <= t_load_13_fu_3325_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343)) then
outs_TDATA <= beta_load_12_fu_3320_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342)) then
outs_TDATA <= gamma_load_12_fu_3315_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341)) then
outs_TDATA <= t_load_12_fu_3310_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340)) then
outs_TDATA <= beta_load_11_fu_3305_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339)) then
outs_TDATA <= gamma_load_11_fu_3300_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338)) then
outs_TDATA <= t_load_11_fu_3295_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337)) then
outs_TDATA <= beta_load_10_fu_3290_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336)) then
outs_TDATA <= gamma_load_10_fu_3285_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335)) then
outs_TDATA <= t_load_10_fu_3280_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334)) then
outs_TDATA <= beta_load_9_fu_3275_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333)) then
outs_TDATA <= gamma_load_9_fu_3270_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332)) then
outs_TDATA <= t_load_9_fu_3265_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331)) then
outs_TDATA <= beta_load_8_fu_3260_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330)) then
outs_TDATA <= gamma_load_8_fu_3255_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329)) then
outs_TDATA <= t_load_8_fu_3250_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328)) then
outs_TDATA <= beta_load_7_fu_3245_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327)) then
outs_TDATA <= gamma_load_7_fu_3240_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326)) then
outs_TDATA <= t_load_7_fu_3235_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325)) then
outs_TDATA <= beta_load_6_fu_3230_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324)) then
outs_TDATA <= gamma_load_6_fu_3225_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323)) then
outs_TDATA <= t_load_6_fu_3220_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322)) then
outs_TDATA <= beta_load_5_fu_3215_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321)) then
outs_TDATA <= gamma_load_5_fu_3210_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320)) then
outs_TDATA <= t_load_5_fu_3205_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319)) then
outs_TDATA <= beta_load_4_fu_3200_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318)) then
outs_TDATA <= gamma_load_4_fu_3195_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317)) then
outs_TDATA <= t_load_4_fu_3190_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316)) then
outs_TDATA <= beta_load_3_fu_3185_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315)) then
outs_TDATA <= gamma_load_3_fu_3180_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314)) then
outs_TDATA <= t_load_3_fu_3175_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313)) then
outs_TDATA <= beta_load_2_fu_3170_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312)) then
outs_TDATA <= gamma_load_2_fu_3165_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311)) then
outs_TDATA <= t_load_2_fu_3160_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310)) then
outs_TDATA <= beta_load_1_fu_3155_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309)) then
outs_TDATA <= gamma_load_1_fu_3150_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308)) then
outs_TDATA <= t_load_1_fu_3145_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307)) then
outs_TDATA <= beta_load_s_fu_3140_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306)) then
outs_TDATA <= gamma_load_s_fu_3135_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305)) then
outs_TDATA <= t_load_s_fu_3130_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304)) then
outs_TDATA <= beta_load_fu_3125_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303)) then
outs_TDATA <= gamma_load_fu_3120_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302)) then
outs_TDATA <= t_load_fu_3115_p1;
else
outs_TDATA <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
outs_TDEST <= ins_dest_V_val_reg_3849;
outs_TID <= ins_id_V_val_reg_3844;
outs_TKEEP <= ins_keep_V_val_reg_3824;
-- outs_TLAST assign process. --
outs_TLAST_assign_proc : process(ap_sig_cseq_ST_st386_fsm_302, ap_sig_cseq_ST_st389_fsm_305, ap_sig_cseq_ST_st392_fsm_308, ap_sig_cseq_ST_st395_fsm_311, ap_sig_cseq_ST_st398_fsm_314, ap_sig_cseq_ST_st401_fsm_317, ap_sig_cseq_ST_st404_fsm_320, ap_sig_cseq_ST_st407_fsm_323, ap_sig_cseq_ST_st410_fsm_326, ap_sig_cseq_ST_st413_fsm_329, ap_sig_cseq_ST_st416_fsm_332, ap_sig_cseq_ST_st419_fsm_335, ap_sig_cseq_ST_st422_fsm_338, ap_sig_cseq_ST_st425_fsm_341, ap_sig_cseq_ST_st428_fsm_344, ap_sig_cseq_ST_st431_fsm_347, ap_sig_cseq_ST_st434_fsm_350, ap_sig_cseq_ST_st437_fsm_353, ap_sig_cseq_ST_st440_fsm_356, ap_sig_cseq_ST_st443_fsm_359, ins_last_V_val_reg_3839, ap_sig_cseq_ST_st387_fsm_303, ap_sig_cseq_ST_st388_fsm_304, ap_sig_cseq_ST_st390_fsm_306, ap_sig_cseq_ST_st391_fsm_307, ap_sig_cseq_ST_st393_fsm_309, ap_sig_cseq_ST_st394_fsm_310, ap_sig_cseq_ST_st396_fsm_312, ap_sig_cseq_ST_st397_fsm_313, ap_sig_cseq_ST_st399_fsm_315, ap_sig_cseq_ST_st400_fsm_316, ap_sig_cseq_ST_st402_fsm_318, ap_sig_cseq_ST_st403_fsm_319, ap_sig_cseq_ST_st405_fsm_321, ap_sig_cseq_ST_st406_fsm_322, ap_sig_cseq_ST_st408_fsm_324, ap_sig_cseq_ST_st409_fsm_325, ap_sig_cseq_ST_st411_fsm_327, ap_sig_cseq_ST_st412_fsm_328, ap_sig_cseq_ST_st414_fsm_330, ap_sig_cseq_ST_st415_fsm_331, ap_sig_cseq_ST_st417_fsm_333, ap_sig_cseq_ST_st418_fsm_334, ap_sig_cseq_ST_st420_fsm_336, ap_sig_cseq_ST_st421_fsm_337, ap_sig_cseq_ST_st423_fsm_339, ap_sig_cseq_ST_st424_fsm_340, ap_sig_cseq_ST_st426_fsm_342, ap_sig_cseq_ST_st427_fsm_343, ap_sig_cseq_ST_st429_fsm_345, ap_sig_cseq_ST_st430_fsm_346, ap_sig_cseq_ST_st432_fsm_348, ap_sig_cseq_ST_st433_fsm_349, ap_sig_cseq_ST_st435_fsm_351, ap_sig_cseq_ST_st436_fsm_352, ap_sig_cseq_ST_st438_fsm_354, ap_sig_cseq_ST_st439_fsm_355, ap_sig_cseq_ST_st441_fsm_357, ap_sig_cseq_ST_st442_fsm_358, ap_sig_cseq_ST_st444_fsm_360, ap_sig_cseq_ST_st445_fsm_361)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361)) then
outs_TLAST <= ins_last_V_val_reg_3839;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) or (ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305) or (ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308) or (ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311) or (ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314) or (ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317) or (ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320) or (ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323) or (ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326) or (ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329) or (ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332) or (ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335) or (ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338) or (ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341) or (ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344) or (ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347) or (ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350) or (ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353) or (ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356) or (ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359) or (ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303) or (ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304) or (ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306) or (ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307) or (ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309) or (ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310) or (ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312) or (ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313) or (ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315) or (ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316) or (ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318) or (ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319) or (ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321) or (ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322) or (ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324) or (ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325) or (ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327) or (ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328) or (ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330) or (ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331) or (ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333) or (ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334) or (ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336) or (ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337) or (ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339) or (ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340) or (ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342) or (ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343) or (ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345) or (ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346) or (ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348) or (ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349) or (ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351) or (ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352) or (ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354) or (ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355) or (ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357) or (ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358) or (ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360))) then
outs_TLAST <= ap_const_lv1_0;
else
outs_TLAST <= "X";
end if;
end process;
outs_TSTRB <= ins_strb_V_val_reg_3829;
outs_TUSER <= ins_user_V_val_reg_3834;
-- outs_TVALID assign process. --
outs_TVALID_assign_proc : process(ap_sig_cseq_ST_st386_fsm_302, ap_sig_cseq_ST_st389_fsm_305, ap_sig_cseq_ST_st392_fsm_308, ap_sig_cseq_ST_st395_fsm_311, ap_sig_cseq_ST_st398_fsm_314, ap_sig_cseq_ST_st401_fsm_317, ap_sig_cseq_ST_st404_fsm_320, ap_sig_cseq_ST_st407_fsm_323, ap_sig_cseq_ST_st410_fsm_326, ap_sig_cseq_ST_st413_fsm_329, ap_sig_cseq_ST_st416_fsm_332, ap_sig_cseq_ST_st419_fsm_335, ap_sig_cseq_ST_st422_fsm_338, ap_sig_cseq_ST_st425_fsm_341, ap_sig_cseq_ST_st428_fsm_344, ap_sig_cseq_ST_st431_fsm_347, ap_sig_cseq_ST_st434_fsm_350, ap_sig_cseq_ST_st437_fsm_353, ap_sig_cseq_ST_st440_fsm_356, ap_sig_cseq_ST_st443_fsm_359, ap_sig_cseq_ST_st387_fsm_303, ap_sig_cseq_ST_st388_fsm_304, ap_sig_cseq_ST_st390_fsm_306, ap_sig_cseq_ST_st391_fsm_307, ap_sig_cseq_ST_st393_fsm_309, ap_sig_cseq_ST_st394_fsm_310, ap_sig_cseq_ST_st396_fsm_312, ap_sig_cseq_ST_st397_fsm_313, ap_sig_cseq_ST_st399_fsm_315, ap_sig_cseq_ST_st400_fsm_316, ap_sig_cseq_ST_st402_fsm_318, ap_sig_cseq_ST_st403_fsm_319, ap_sig_cseq_ST_st405_fsm_321, ap_sig_cseq_ST_st406_fsm_322, ap_sig_cseq_ST_st408_fsm_324, ap_sig_cseq_ST_st409_fsm_325, ap_sig_cseq_ST_st411_fsm_327, ap_sig_cseq_ST_st412_fsm_328, ap_sig_cseq_ST_st414_fsm_330, ap_sig_cseq_ST_st415_fsm_331, ap_sig_cseq_ST_st417_fsm_333, ap_sig_cseq_ST_st418_fsm_334, ap_sig_cseq_ST_st420_fsm_336, ap_sig_cseq_ST_st421_fsm_337, ap_sig_cseq_ST_st423_fsm_339, ap_sig_cseq_ST_st424_fsm_340, ap_sig_cseq_ST_st426_fsm_342, ap_sig_cseq_ST_st427_fsm_343, ap_sig_cseq_ST_st429_fsm_345, ap_sig_cseq_ST_st430_fsm_346, ap_sig_cseq_ST_st432_fsm_348, ap_sig_cseq_ST_st433_fsm_349, ap_sig_cseq_ST_st435_fsm_351, ap_sig_cseq_ST_st436_fsm_352, ap_sig_cseq_ST_st438_fsm_354, ap_sig_cseq_ST_st439_fsm_355, ap_sig_cseq_ST_st441_fsm_357, ap_sig_cseq_ST_st442_fsm_358, ap_sig_cseq_ST_st444_fsm_360, ap_sig_cseq_ST_st445_fsm_361, ap_reg_ioackin_outs_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st386_fsm_302) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st387_fsm_303) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st388_fsm_304) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st389_fsm_305) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st390_fsm_306) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st391_fsm_307) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st392_fsm_308) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st393_fsm_309) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st394_fsm_310) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st395_fsm_311) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st396_fsm_312) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st397_fsm_313) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st398_fsm_314) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st399_fsm_315) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st400_fsm_316) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st401_fsm_317) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st402_fsm_318) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st403_fsm_319) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st404_fsm_320) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st405_fsm_321) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st406_fsm_322) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st407_fsm_323) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st408_fsm_324) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st409_fsm_325) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st410_fsm_326) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st411_fsm_327) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st412_fsm_328) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st413_fsm_329) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st414_fsm_330) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st415_fsm_331) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st416_fsm_332) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st417_fsm_333) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st418_fsm_334) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st419_fsm_335) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st420_fsm_336) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st421_fsm_337) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st422_fsm_338) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st423_fsm_339) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st424_fsm_340) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st425_fsm_341) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st426_fsm_342) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st427_fsm_343) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st428_fsm_344) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st429_fsm_345) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st430_fsm_346) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st431_fsm_347) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st432_fsm_348) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st433_fsm_349) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st434_fsm_350) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st435_fsm_351) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st436_fsm_352) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st437_fsm_353) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st438_fsm_354) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st439_fsm_355) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st440_fsm_356) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st441_fsm_357) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st442_fsm_358) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st443_fsm_359) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st444_fsm_360) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st445_fsm_361) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)))) then
outs_TVALID <= ap_const_logic_1;
else
outs_TVALID <= ap_const_logic_0;
end if;
end process;
rez_addr959960_part_set_fu_830_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_fu_796_p16);
rez_addr_10932933_part_set_fu_1736_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_10_fu_1702_p16);
rez_addr_11929930_part_set_fu_1843_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_11_fu_1809_p16);
rez_addr_12926927_part_set_fu_1950_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_12_fu_1916_p16);
rez_addr_13923924_part_set_fu_2057_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_13_fu_2023_p16);
rez_addr_14920921_part_set_fu_2164_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_14_fu_2130_p16);
rez_addr_15917918_part_set_fu_2271_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_15_fu_2237_p16);
rez_addr_16914915_part_set_fu_2378_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_16_fu_2344_p16);
rez_addr_17911912_part_set_fu_2485_p5 <= (reg_725(575 downto 480) & tmp_17_fu_2451_p16);
rez_addr_18908909_part_set_fu_2592_p5 <= (data_array_load_1_reg_3743(575 downto 480) & tmp_18_fu_2558_p16);
rez_addr_1956957_part_set_fu_1109_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_2_fu_1075_p16);
rez_addr_19905906_part_set_fu_2698_p5 <= (data_array_load_2_reg_3722(575 downto 480) & tmp_19_fu_2664_p16);
rez_addr_20902903_part_set_fu_2828_p5 <= (data_array_load_3_reg_3759(575 downto 480) & tmp_20_fu_2794_p16);
rez_addr_3953954_part_set_fu_922_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_3_fu_888_p16);
rez_addr_4950951_part_set_fu_1201_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_4_fu_1167_p16);
rez_addr_5947948_part_set_fu_1017_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_5_fu_983_p16);
rez_addr_6944945_part_set_fu_1308_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_6_fu_1274_p16);
rez_addr_7941942_part_set_fu_1415_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_7_fu_1381_p16);
rez_addr_8938939_part_set_fu_1522_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_8_fu_1488_p16);
rez_addr_9935936_part_set_fu_1629_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_9_fu_1595_p16);
t_load_10_fu_3280_p1 <= grp_fu_639_p4;
t_load_11_fu_3295_p1 <= grp_fu_639_p4;
t_load_12_fu_3310_p1 <= grp_fu_639_p4;
t_load_13_fu_3325_p1 <= grp_fu_639_p4;
t_load_14_fu_3340_p1 <= grp_fu_639_p4;
t_load_15_fu_3355_p1 <= grp_fu_639_p4;
t_load_16_fu_3370_p1 <= grp_fu_639_p4;
t_load_17_fu_3385_p1 <= grp_fu_639_p4;
t_load_18_fu_3400_p1 <= grp_fu_639_p4;
t_load_1_fu_3145_p1 <= grp_fu_639_p4;
t_load_2_fu_3160_p1 <= grp_fu_639_p4;
t_load_3_fu_3175_p1 <= grp_fu_639_p4;
t_load_4_fu_3190_p1 <= grp_fu_639_p4;
t_load_5_fu_3205_p1 <= grp_fu_639_p4;
t_load_6_fu_3220_p1 <= grp_fu_639_p4;
t_load_7_fu_3235_p1 <= grp_fu_639_p4;
t_load_8_fu_3250_p1 <= grp_fu_639_p4;
t_load_9_fu_3265_p1 <= grp_fu_639_p4;
t_load_fu_3115_p1 <= grp_fu_639_p4;
t_load_s_fu_3130_p1 <= grp_fu_639_p4;
t_write_assign_toint_fu_3081_p1 <= grp_fu_618_p2;
tmp_10_fu_1702_p16 <= ((((((((((((((ins_data_tmp_load_149_toint_fu_1698_p1 & ins_data_tmp_load_148_toint_fu_1694_p1) & ins_data_tmp_load_147_toint_fu_1690_p1) & ins_data_tmp_load_146_toint_fu_1686_p1) & ins_data_tmp_load_145_toint_fu_1682_p1) & ins_data_tmp_load_144_toint_fu_1678_p1) & ins_data_tmp_load_143_toint_fu_1674_p1) & ins_data_tmp_load_142_toint_fu_1670_p1) & ins_data_tmp_load_141_toint_fu_1666_p1) & ins_data_tmp_load_140_toint_fu_1662_p1) & ins_data_tmp_load_139_toint_fu_1658_p1) & ins_data_tmp_load_138_toint_fu_1654_p1) & ins_data_tmp_load_137_toint_fu_1650_p1) & ins_data_tmp_load_136_toint_fu_1646_p1) & ins_data_tmp_load_135_toint_fu_1642_p1);
tmp_11_fu_1809_p16 <= ((((((((((((((ins_data_tmp_load_164_toint_fu_1805_p1 & ins_data_tmp_load_163_toint_fu_1801_p1) & ins_data_tmp_load_162_toint_fu_1797_p1) & ins_data_tmp_load_161_toint_fu_1793_p1) & ins_data_tmp_load_160_toint_fu_1789_p1) & ins_data_tmp_load_159_toint_fu_1785_p1) & ins_data_tmp_load_158_toint_fu_1781_p1) & ins_data_tmp_load_157_toint_fu_1777_p1) & ins_data_tmp_load_156_toint_fu_1773_p1) & ins_data_tmp_load_155_toint_fu_1769_p1) & ins_data_tmp_load_154_toint_fu_1765_p1) & ins_data_tmp_load_153_toint_fu_1761_p1) & ins_data_tmp_load_152_toint_fu_1757_p1) & ins_data_tmp_load_151_toint_fu_1753_p1) & ins_data_tmp_load_150_toint_fu_1749_p1);
tmp_12_fu_1916_p16 <= ((((((((((((((ins_data_tmp_load_179_toint_fu_1912_p1 & ins_data_tmp_load_178_toint_fu_1908_p1) & ins_data_tmp_load_177_toint_fu_1904_p1) & ins_data_tmp_load_176_toint_fu_1900_p1) & ins_data_tmp_load_175_toint_fu_1896_p1) & ins_data_tmp_load_174_toint_fu_1892_p1) & ins_data_tmp_load_173_toint_fu_1888_p1) & ins_data_tmp_load_172_toint_fu_1884_p1) & ins_data_tmp_load_171_toint_fu_1880_p1) & ins_data_tmp_load_170_toint_fu_1876_p1) & ins_data_tmp_load_169_toint_fu_1872_p1) & ins_data_tmp_load_168_toint_fu_1868_p1) & ins_data_tmp_load_167_toint_fu_1864_p1) & ins_data_tmp_load_166_toint_fu_1860_p1) & ins_data_tmp_load_165_toint_fu_1856_p1);
tmp_13_fu_2023_p16 <= ((((((((((((((ins_data_tmp_load_194_toint_fu_2019_p1 & ins_data_tmp_load_193_toint_fu_2015_p1) & ins_data_tmp_load_192_toint_fu_2011_p1) & ins_data_tmp_load_191_toint_fu_2007_p1) & ins_data_tmp_load_190_toint_fu_2003_p1) & ins_data_tmp_load_189_toint_fu_1999_p1) & ins_data_tmp_load_188_toint_fu_1995_p1) & ins_data_tmp_load_187_toint_fu_1991_p1) & ins_data_tmp_load_186_toint_fu_1987_p1) & ins_data_tmp_load_185_toint_fu_1983_p1) & ins_data_tmp_load_184_toint_fu_1979_p1) & ins_data_tmp_load_183_toint_fu_1975_p1) & ins_data_tmp_load_182_toint_fu_1971_p1) & ins_data_tmp_load_181_toint_fu_1967_p1) & ins_data_tmp_load_180_toint_fu_1963_p1);
tmp_14_fu_2130_p16 <= ((((((((((((((ins_data_tmp_load_209_toint_fu_2126_p1 & ins_data_tmp_load_208_toint_fu_2122_p1) & ins_data_tmp_load_207_toint_fu_2118_p1) & ins_data_tmp_load_206_toint_fu_2114_p1) & ins_data_tmp_load_205_toint_fu_2110_p1) & ins_data_tmp_load_204_toint_fu_2106_p1) & ins_data_tmp_load_203_toint_fu_2102_p1) & ins_data_tmp_load_202_toint_fu_2098_p1) & ins_data_tmp_load_201_toint_fu_2094_p1) & ins_data_tmp_load_200_toint_fu_2090_p1) & ins_data_tmp_load_199_toint_fu_2086_p1) & ins_data_tmp_load_198_toint_fu_2082_p1) & ins_data_tmp_load_197_toint_fu_2078_p1) & ins_data_tmp_load_196_toint_fu_2074_p1) & ins_data_tmp_load_195_toint_fu_2070_p1);
tmp_15_fu_2237_p16 <= ((((((((((((((ins_data_tmp_load_224_toint_fu_2233_p1 & ins_data_tmp_load_223_toint_fu_2229_p1) & ins_data_tmp_load_222_toint_fu_2225_p1) & ins_data_tmp_load_221_toint_fu_2221_p1) & ins_data_tmp_load_220_toint_fu_2217_p1) & ins_data_tmp_load_219_toint_fu_2213_p1) & ins_data_tmp_load_218_toint_fu_2209_p1) & ins_data_tmp_load_217_toint_fu_2205_p1) & ins_data_tmp_load_216_toint_fu_2201_p1) & ins_data_tmp_load_215_toint_fu_2197_p1) & ins_data_tmp_load_214_toint_fu_2193_p1) & ins_data_tmp_load_213_toint_fu_2189_p1) & ins_data_tmp_load_212_toint_fu_2185_p1) & ins_data_tmp_load_211_toint_fu_2181_p1) & ins_data_tmp_load_210_toint_fu_2177_p1);
tmp_16_fu_2344_p16 <= ((((((((((((((ins_data_tmp_load_239_toint_fu_2340_p1 & ins_data_tmp_load_238_toint_fu_2336_p1) & ins_data_tmp_load_237_toint_fu_2332_p1) & ins_data_tmp_load_236_toint_fu_2328_p1) & ins_data_tmp_load_235_toint_fu_2324_p1) & ins_data_tmp_load_234_toint_fu_2320_p1) & ins_data_tmp_load_233_toint_fu_2316_p1) & ins_data_tmp_load_232_toint_fu_2312_p1) & ins_data_tmp_load_231_toint_fu_2308_p1) & ins_data_tmp_load_230_toint_fu_2304_p1) & ins_data_tmp_load_229_toint_fu_2300_p1) & ins_data_tmp_load_228_toint_fu_2296_p1) & ins_data_tmp_load_227_toint_fu_2292_p1) & ins_data_tmp_load_226_toint_fu_2288_p1) & ins_data_tmp_load_225_toint_fu_2284_p1);
tmp_17_fu_2451_p16 <= ((((((((((((((ins_data_tmp_load_254_toint_fu_2447_p1 & ins_data_tmp_load_253_toint_fu_2443_p1) & ins_data_tmp_load_252_toint_fu_2439_p1) & ins_data_tmp_load_251_toint_fu_2435_p1) & ins_data_tmp_load_250_toint_fu_2431_p1) & ins_data_tmp_load_249_toint_fu_2427_p1) & ins_data_tmp_load_248_toint_fu_2423_p1) & ins_data_tmp_load_247_toint_fu_2419_p1) & ins_data_tmp_load_246_toint_fu_2415_p1) & ins_data_tmp_load_245_toint_fu_2411_p1) & ins_data_tmp_load_244_toint_fu_2407_p1) & ins_data_tmp_load_243_toint_fu_2403_p1) & ins_data_tmp_load_242_toint_fu_2399_p1) & ins_data_tmp_load_241_toint_fu_2395_p1) & ins_data_tmp_load_240_toint_fu_2391_p1);
tmp_18_fu_2558_p16 <= ((((((((((((((ins_data_tmp_load_269_toint_fu_2554_p1 & ins_data_tmp_load_268_toint_fu_2550_p1) & ins_data_tmp_load_267_toint_fu_2546_p1) & ins_data_tmp_load_266_toint_fu_2542_p1) & ins_data_tmp_load_265_toint_fu_2538_p1) & ins_data_tmp_load_264_toint_fu_2534_p1) & ins_data_tmp_load_263_toint_fu_2530_p1) & ins_data_tmp_load_262_toint_fu_2526_p1) & ins_data_tmp_load_261_toint_fu_2522_p1) & ins_data_tmp_load_260_toint_fu_2518_p1) & ins_data_tmp_load_259_toint_fu_2514_p1) & ins_data_tmp_load_258_toint_fu_2510_p1) & ins_data_tmp_load_257_toint_fu_2506_p1) & ins_data_tmp_load_256_toint_fu_2502_p1) & ins_data_tmp_load_255_toint_fu_2498_p1);
tmp_19_fu_2664_p16 <= ((((((((((((((ins_data_tmp_load_284_toint_fu_2660_p1 & ins_data_tmp_load_283_toint_fu_2656_p1) & ins_data_tmp_load_282_toint_fu_2652_p1) & ins_data_tmp_load_281_toint_fu_2648_p1) & ins_data_tmp_load_280_toint_fu_2644_p1) & ins_data_tmp_load_279_toint_fu_2640_p1) & ins_data_tmp_load_278_toint_fu_2636_p1) & ins_data_tmp_load_277_toint_fu_2632_p1) & ins_data_tmp_load_276_toint_fu_2628_p1) & ins_data_tmp_load_275_toint_fu_2624_p1) & ins_data_tmp_load_274_toint_fu_2620_p1) & ins_data_tmp_load_273_toint_fu_2616_p1) & ins_data_tmp_load_272_toint_fu_2612_p1) & ins_data_tmp_load_271_toint_fu_2608_p1) & ins_data_tmp_load_270_toint_fu_2604_p1);
tmp_1_fu_2852_p1 <= std_logic_vector(resize(unsigned(i1_reg_418),64));
tmp_20_fu_2794_p16 <= ((((((((((((((ins_data_tmp_load_299_toint_fu_2790_p1 & ins_data_tmp_load_298_toint_fu_2762_p1) & ins_data_tmp_load_297_toint_fu_2758_p1) & ins_data_tmp_load_296_toint_fu_2754_p1) & ins_data_tmp_load_295_toint_fu_2750_p1) & ins_data_tmp_load_294_toint_fu_2746_p1) & ins_data_tmp_load_293_toint_fu_2742_p1) & ins_data_tmp_load_292_toint_fu_2738_p1) & ins_data_tmp_load_291_toint_fu_2734_p1) & ins_data_tmp_load_290_toint_fu_2730_p1) & ins_data_tmp_load_289_toint_fu_2726_p1) & ins_data_tmp_load_288_toint_fu_2722_p1) & ins_data_tmp_load_287_toint_fu_2718_p1) & ins_data_tmp_load_286_toint_fu_2714_p1) & ins_data_tmp_load_285_toint_fu_2710_p1);
tmp_21_fu_3093_p4 <= ((beta_write_assign_toint_fu_3089_p1 & gamma_write_assign_toint_fu_3085_p1) & t_write_assign_toint_fu_3081_p1);
tmp_22_fu_2857_p1 <= data_array_q0(32 - 1 downto 0);
tmp_2_fu_1075_p16 <= ((((((((((((((ins_data_tmp_load_29_toint_fu_1072_p1 & ins_data_tmp_load_28_toint_fu_1069_p1) & ins_data_tmp_load_27_toint_fu_1066_p1) & ins_data_tmp_load_26_toint_fu_1063_p1) & ins_data_tmp_load_25_toint_fu_1060_p1) & ins_data_tmp_load_24_toint_fu_1057_p1) & ins_data_tmp_load_23_toint_fu_1054_p1) & ins_data_tmp_load_22_toint_fu_1051_p1) & ins_data_tmp_load_21_toint_fu_1048_p1) & ins_data_tmp_load_20_toint_fu_1045_p1) & ins_data_tmp_load_19_toint_fu_1042_p1) & ins_data_tmp_load_18_toint_fu_1039_p1) & ins_data_tmp_load_17_toint_fu_1036_p1) & ins_data_tmp_load_16_toint_fu_1033_p1) & ins_data_tmp_load_15_toint_fu_1030_p1);
tmp_3_fu_888_p16 <= ((((((((((((((ins_data_tmp_load_44_toint_fu_885_p1 & ins_data_tmp_load_43_toint_fu_882_p1) & ins_data_tmp_load_42_toint_fu_879_p1) & ins_data_tmp_load_41_toint_fu_876_p1) & ins_data_tmp_load_40_toint_fu_873_p1) & ins_data_tmp_load_39_toint_fu_870_p1) & ins_data_tmp_load_38_toint_fu_867_p1) & ins_data_tmp_load_37_toint_fu_864_p1) & ins_data_tmp_load_36_toint_fu_861_p1) & ins_data_tmp_load_35_toint_fu_858_p1) & ins_data_tmp_load_34_toint_fu_855_p1) & ins_data_tmp_load_33_toint_fu_852_p1) & ins_data_tmp_load_32_toint_fu_849_p1) & ins_data_tmp_load_31_toint_fu_846_p1) & ins_data_tmp_load_30_toint_fu_843_p1);
tmp_4_fu_1167_p16 <= ((((((((((((((ins_data_tmp_load_59_toint_fu_1164_p1 & ins_data_tmp_load_58_toint_fu_1161_p1) & ins_data_tmp_load_57_toint_fu_1158_p1) & ins_data_tmp_load_56_toint_fu_1155_p1) & ins_data_tmp_load_55_toint_fu_1152_p1) & ins_data_tmp_load_54_toint_fu_1149_p1) & ins_data_tmp_load_53_toint_fu_1146_p1) & ins_data_tmp_load_52_toint_fu_1143_p1) & ins_data_tmp_load_51_toint_fu_1140_p1) & ins_data_tmp_load_50_toint_fu_1137_p1) & ins_data_tmp_load_49_toint_fu_1134_p1) & ins_data_tmp_load_48_toint_fu_1131_p1) & ins_data_tmp_load_47_toint_fu_1128_p1) & ins_data_tmp_load_46_toint_fu_1125_p1) & ins_data_tmp_load_45_toint_fu_1122_p1);
tmp_5_fu_983_p16 <= ((((((((((((((ins_data_tmp_load_74_toint_fu_979_p1 & ins_data_tmp_load_73_toint_fu_975_p1) & ins_data_tmp_load_72_toint_fu_971_p1) & ins_data_tmp_load_71_toint_fu_968_p1) & ins_data_tmp_load_70_toint_fu_965_p1) & ins_data_tmp_load_69_toint_fu_962_p1) & ins_data_tmp_load_68_toint_fu_959_p1) & ins_data_tmp_load_67_toint_fu_956_p1) & ins_data_tmp_load_66_toint_fu_953_p1) & ins_data_tmp_load_65_toint_fu_950_p1) & ins_data_tmp_load_64_toint_fu_947_p1) & ins_data_tmp_load_63_toint_fu_944_p1) & ins_data_tmp_load_62_toint_fu_941_p1) & ins_data_tmp_load_61_toint_fu_938_p1) & ins_data_tmp_load_60_toint_fu_935_p1);
tmp_61_neg_i_fu_3071_p2 <= (tmp_61_to_int_i_fu_3068_p1 xor ap_const_lv32_80000000);
tmp_61_to_int_i_fu_3068_p1 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76;
tmp_6_fu_1274_p16 <= ((((((((((((((ins_data_tmp_load_89_toint_fu_1270_p1 & ins_data_tmp_load_88_toint_fu_1266_p1) & ins_data_tmp_load_87_toint_fu_1262_p1) & ins_data_tmp_load_86_toint_fu_1258_p1) & ins_data_tmp_load_85_toint_fu_1254_p1) & ins_data_tmp_load_84_toint_fu_1250_p1) & ins_data_tmp_load_83_toint_fu_1246_p1) & ins_data_tmp_load_82_toint_fu_1242_p1) & ins_data_tmp_load_81_toint_fu_1238_p1) & ins_data_tmp_load_80_toint_fu_1234_p1) & ins_data_tmp_load_79_toint_fu_1230_p1) & ins_data_tmp_load_78_toint_fu_1226_p1) & ins_data_tmp_load_77_toint_fu_1222_p1) & ins_data_tmp_load_76_toint_fu_1218_p1) & ins_data_tmp_load_75_toint_fu_1214_p1);
tmp_7_fu_1381_p16 <= ((((((((((((((ins_data_tmp_load_104_toint_fu_1377_p1 & ins_data_tmp_load_103_toint_fu_1373_p1) & ins_data_tmp_load_102_toint_fu_1369_p1) & ins_data_tmp_load_101_toint_fu_1365_p1) & ins_data_tmp_load_100_toint_fu_1361_p1) & ins_data_tmp_load_99_toint_fu_1357_p1) & ins_data_tmp_load_98_toint_fu_1353_p1) & ins_data_tmp_load_97_toint_fu_1349_p1) & ins_data_tmp_load_96_toint_fu_1345_p1) & ins_data_tmp_load_95_toint_fu_1341_p1) & ins_data_tmp_load_94_toint_fu_1337_p1) & ins_data_tmp_load_93_toint_fu_1333_p1) & ins_data_tmp_load_92_toint_fu_1329_p1) & ins_data_tmp_load_91_toint_fu_1325_p1) & ins_data_tmp_load_90_toint_fu_1321_p1);
tmp_8_fu_1488_p16 <= ((((((((((((((ins_data_tmp_load_119_toint_fu_1484_p1 & ins_data_tmp_load_118_toint_fu_1480_p1) & ins_data_tmp_load_117_toint_fu_1476_p1) & ins_data_tmp_load_116_toint_fu_1472_p1) & ins_data_tmp_load_115_toint_fu_1468_p1) & ins_data_tmp_load_114_toint_fu_1464_p1) & ins_data_tmp_load_113_toint_fu_1460_p1) & ins_data_tmp_load_112_toint_fu_1456_p1) & ins_data_tmp_load_111_toint_fu_1452_p1) & ins_data_tmp_load_110_toint_fu_1448_p1) & ins_data_tmp_load_109_toint_fu_1444_p1) & ins_data_tmp_load_108_toint_fu_1440_p1) & ins_data_tmp_load_107_toint_fu_1436_p1) & ins_data_tmp_load_106_toint_fu_1432_p1) & ins_data_tmp_load_105_toint_fu_1428_p1);
tmp_9_fu_1595_p16 <= ((((((((((((((ins_data_tmp_load_134_toint_fu_1591_p1 & ins_data_tmp_load_133_toint_fu_1587_p1) & ins_data_tmp_load_132_toint_fu_1583_p1) & ins_data_tmp_load_131_toint_fu_1579_p1) & ins_data_tmp_load_130_toint_fu_1575_p1) & ins_data_tmp_load_129_toint_fu_1571_p1) & ins_data_tmp_load_128_toint_fu_1567_p1) & ins_data_tmp_load_127_toint_fu_1563_p1) & ins_data_tmp_load_126_toint_fu_1559_p1) & ins_data_tmp_load_125_toint_fu_1555_p1) & ins_data_tmp_load_124_toint_fu_1551_p1) & ins_data_tmp_load_123_toint_fu_1547_p1) & ins_data_tmp_load_122_toint_fu_1543_p1) & ins_data_tmp_load_121_toint_fu_1539_p1) & ins_data_tmp_load_120_toint_fu_1535_p1);
tmp_fu_796_p16 <= ((((((((((((((ins_data_tmp_load_14_toint_fu_793_p1 & ins_data_tmp_load_13_toint_fu_789_p1) & ins_data_tmp_load_12_toint_fu_785_p1) & ins_data_tmp_load_11_toint_fu_781_p1) & ins_data_tmp_load_10_toint_fu_777_p1) & ins_data_tmp_load_9_toint_fu_773_p1) & ins_data_tmp_load_8_toint_fu_769_p1) & ins_data_tmp_load_7_toint_fu_765_p1) & ins_data_tmp_load_6_toint_fu_761_p1) & ins_data_tmp_load_5_toint_fu_757_p1) & ins_data_tmp_load_4_toint_fu_753_p1) & ins_data_tmp_load_3_toint_fu_749_p1) & ins_data_tmp_load_2_toint_fu_745_p1) & ins_data_tmp_load_1_toint_fu_741_p1) & ins_data_tmp_load_toint_fu_737_p1);
v0x_assign4_fu_3001_p1 <= tmp_22_reg_3869;
v0y_assign_fu_3007_p1 <= v0y_assign_new_reg_3874;
v0z_assign_fu_3013_p1 <= v0z_assign_new_reg_3879;
end behav;
| mit | cd0d56f1ab4c03c7645651b1a5cff2e1 | 0.653754 | 3.204452 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth.vhd | 3 | 10,215 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen
GENERIC MAP (
C_DIN_WIDTH => 1,
C_DOUT_WIDTH => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif
GENERIC MAP (
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 1,
C_DIN_WIDTH => 1,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_inst : system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-3-clause | 6087e0921d82f0239f843768b952c29c | 0.474107 | 4.087635 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/vhdl/tri_intersect_fadd_32ns_32ns_32_9_full_dsp.vhd | 4 | 3,391 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity tri_intersect_fadd_32ns_32ns_32_9_full_dsp is
generic (
ID : integer := 15;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of tri_intersect_fadd_32ns_32ns_32_9_full_dsp is
--------------------- Component ---------------------
component tri_intersect_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
tri_intersect_ap_fadd_7_full_dsp_32_u : component tri_intersect_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | 29b1080b1e385598b52dcd3fa7e060ca | 0.490711 | 3.492276 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/MurmurHash_SearchBRAMImplementation.vhdl | 1 | 1,950 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
entity BinarySearchBRAM is
generic(
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 10
);
port(
clk : in std_logic;-- un solo reloj para ambos puertos de la BRAM
--Puerto de escritura en el cual se vana grabar los datos en la tabla
porta_wr : in std_logic;
porta_waddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
porta_din : in std_logic_vector( (DATA_WIDTH-1) downto 0);
porta_rd : in std_logic;
porta_raddr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
porta_dout : out std_logic_vector( (DATA_WIDTH-1) downto 0);
--puerto de lectura, desde el cual se van a leer los 0
--datos para la comparación
portb_rd : in std_logic;
portb_addr : in std_logic_vector( (ADDR_WIDTH-1) downto 0);
portb_dout : out std_logic_vector( (DATA_WIDTH-1) downto 0)
);
end entity BinarySearchBRAM;
architecture Inferral of BinarySearchBRAM is
type mem_type is array ( (2**ADDR_WIDTH)-1 downto 0 ) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable mem : mem_type;
begin
portA:process (clk, porta_wr, porta_waddr, porta_raddr, porta_din, porta_rd)
begin
if rising_edge(clk) then
if ( porta_wr = '1' ) then
mem(conv_integer(porta_waddr)) := porta_din;
elsif ( porta_rd = '1' ) then
porta_dout <= mem(conv_integer(porta_raddr));
end if;
end if;
end process portA;
portB:process (clk, portb_rd, portb_addr)
begin
if rising_edge(clk) then
if ( portb_rd = '1' ) then
portb_dout <= mem(conv_integer(portb_addr));
end if;
end if;
end process portB;
end architecture Inferral;
| bsd-3-clause | e81388afbe7cc39ee5ee40f831cf0a8d | 0.594664 | 3.505396 | false | false | false | false |
alemedeiros/flappy_vhdl | colision/colision_detection.vhd | 1 | 1,413 | -- file: colision/colision_detection.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Check for colision between first obstacle with player.
library ieee ;
use ieee.std_logic_1164.all ;
use IEEE.std_logic_arith.all;
entity colision_detection is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 ; -- Number of obstacles
P_POS : natural := 20 -- Player Horizontal position
) ;
port (
player : in integer range 0 to V_RES - 1 ;
position : in integer range 0 to H_RES / N_OBST - 1;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
game_over : out std_logic ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end colision_detection ;
architecture behavior of colision_detection is
begin
-- Reading values process
process(clock)
variable tmp : std_logic := '0' ;
begin
if (reset = '0' and enable = '1' and rising_edge(clock)) then
tmp := '0' ;
if (player >= V_RES or player < 0 or (((V_RES - 1 - obst_low) < player or obst_high > player) and position = P_POS) ) then
tmp := '1' ;
end if;
end if ;
game_over <= tmp ;
end process ;
end behavior ;
| bsd-3-clause | d9ca7841ba6ee5da5b9848bfefd9fe41 | 0.624204 | 3.278422 | false | false | false | false |
shameerpt/sata_2_host_controller | sata_2_core_and_test_app/XPS/pcores/sata_test_logic_v1_00_a/hdl/vhdl/sata_test_logic.vhd | 1 | 24,992 | ------------------------------------------------------------------------------
-- sata_test_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: sata_test_logic.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Aug 01 11:43:44 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity sata_test_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex6";
C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM0_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
MB2IP_Clk : out std_logic;
MB2IP_Reset : out std_logic;
MB2IP_Addr : out std_logic_vector(0 to 31);
MB2IP_CS : out std_logic_vector(0 to 0) ;
MB2IP_RNW : out std_logic;
MB2IP_Data : out std_logic_vector(0 to 31);
MB2IP_BE : out std_logic_vector(0 to 3);
IP2mb_Data : in std_logic_vector(0 to 31);
IP2MB_RdAck : in std_logic;
IP2MB_WrAck : in std_logic;
IP2MB_Error : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity sata_test_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of sata_test_logic is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address
ZERO_ADDR_PAD & C_MEM0_HIGHADDR -- user logic memory space 0 high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_NUM_MEM : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1 -- number of ce for user logic memory space 0 (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_MEM0_CS_INDEX : integer := 0;
constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
-- component user_logic is
-- generic
-- (
-- -- ADD USER GENERICS BELOW THIS LINE ---------------
-- --USER generics added here
-- -- ADD USER GENERICS ABOVE THIS LINE ---------------
--
-- -- DO NOT EDIT BELOW THIS LINE ---------------------
-- -- Bus protocol parameters, do not add to or delete
-- C_SLV_AWIDTH : integer := 32;
-- C_SLV_DWIDTH : integer := 32;
-- C_NUM_MEM : integer := 1
-- -- DO NOT EDIT ABOVE THIS LINE ---------------------
-- );
-- port
-- (
-- -- ADD USER PORTS BELOW THIS LINE ------------------
-- --USER ports added here
-- -- ADD USER PORTS ABOVE THIS LINE ------------------
--
-- -- DO NOT EDIT BELOW THIS LINE ---------------------
-- -- Bus protocol ports, do not add to or delete
-- Bus2IP_Clk : in std_logic;
-- Bus2IP_Reset : in std_logic;
-- Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1);
-- Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1);
-- Bus2IP_RNW : in std_logic;
-- Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
-- Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
-- IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
-- IP2Bus_RdAck : out std_logic;
-- IP2Bus_WrAck : out std_logic;
-- IP2Bus_Error : out std_logic
-- -- DO NOT EDIT ABOVE THIS LINE ---------------------
-- );
-- end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
MB2IP_Clk <= ipif_Bus2IP_Clk;
MB2IP_Reset <= ipif_Bus2IP_Reset;
MB2IP_Addr <= ipif_Bus2IP_Addr;
MB2IP_CS <= ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1);
MB2IP_RNW <= ipif_Bus2IP_RNW;
MB2IP_Data <= ipif_Bus2IP_Data;
MB2IP_BE <= ipif_Bus2IP_BE;
user_IP2Bus_Data <= IP2MB_Data;
user_IP2Bus_RdAck <= IP2MB_RdAck;
user_IP2Bus_WrAck <= IP2MB_WrAck;
user_IP2Bus_Error <= IP2MB_Error;
-- USER_LOGIC_I : component user_logic
-- generic map
-- (
-- -- MAP USER GENERICS BELOW THIS LINE ---------------
-- --USER generics mapped here
-- -- MAP USER GENERICS ABOVE THIS LINE ---------------
--
-- C_SLV_AWIDTH => USER_SLV_AWIDTH,
-- C_SLV_DWIDTH => USER_SLV_DWIDTH,
-- C_NUM_MEM => USER_NUM_MEM
-- )
-- port map
-- (
-- -- MAP USER PORTS BELOW THIS LINE ------------------
-- --USER ports mapped here
-- -- MAP USER PORTS ABOVE THIS LINE ------------------
--
-- Bus2IP_Clk => ipif_Bus2IP_Clk,
-- Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => ipif_Bus2IP_Addr,
-- Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
-- Bus2IP_RNW => ipif_Bus2IP_RNW,
-- Bus2IP_Data => ipif_Bus2IP_Data,
-- Bus2IP_BE => ipif_Bus2IP_BE,
-- IP2Bus_Data => user_IP2Bus_Data,
-- IP2Bus_RdAck => user_IP2Bus_RdAck,
-- IP2Bus_WrAck => user_IP2Bus_WrAck,
-- IP2Bus_Error => user_IP2Bus_Error
-- );
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
end IMP;
| gpl-3.0 | 813594776d26125b4fba1b8ddd010598 | 0.428737 | 4.351733 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth.vhd | 3 | 11,096 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL wr_ack : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(67-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(67-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(67-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(67-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
fg_dg_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 67,
C_DOUT_WIDTH => 67,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 67,
C_DIN_WIDTH => 67,
C_USE_EMBEDDED_REG => 1,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 67,
C_DIN_WIDTH => 67,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_vdma_0_wrapper_fifo_generator_v9_3_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-3-clause | bbc24d008d8f5e70939de1df7720dd55 | 0.467376 | 4.06894 | false | false | false | false |
fumyuun/tasty | src/platform/nexys4ddr/top.vhd | 1 | 3,055 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity top_nexys4ddr is
port (
clk_i : in std_logic;
nrst_i : in std_logic;
-- push buttons
btnu_i : in std_logic;
btnl_i : in std_logic;
btnr_i : in std_logic;
btnd_i : in std_logic;
btnc_i : in std_logic;
-- pmods
pmod_a_io_1 : in std_logic;
pmod_a_io_2 : in std_logic;
pmod_a_io_3 : out std_logic;
pmod_b_io : in std_logic_vector(10 downto 0);
led_o : out std_logic_vector(15 downto 0);
switch_i : in std_logic_vector(15 downto 0);
sseg_c_o : out std_logic_vector(7 downto 0);
sseg_an_o : out std_logic_vector(7 downto 0)
);
end entity top_nexys4ddr;
architecture behavioral of top_nexys4ddr is
signal rst_s : std_logic;
signal snes_js_btn_s : snes_js_btn_r;
signal snes_js_bus_i_s : snes_js_bus_i_r;
signal snes_js_bus_o_s : snes_js_bus_o_r;
signal snes_js_btn_leds_s : snes_js_btn_r;
signal pc_s : std_logic_vector(15 downto 0);
begin
rst_s <= not nrst_i;
clock_proc: process(clk_i)
begin
if rising_edge(clk_i) then
snes_js_btn_s.up <= btnu_i;
snes_js_btn_s.down <= btnd_i;
snes_js_btn_s.left <= btnl_i;
snes_js_btn_s.right <= btnr_i;
snes_js_btn_s.a <= pmod_b_io(2);
snes_js_btn_s.b <= pmod_b_io(4);
snes_js_btn_s.x <= pmod_b_io(1);
snes_js_btn_s.y <= pmod_b_io(3);
snes_js_btn_s.l <= '0';
snes_js_btn_s.r <= '0';
snes_js_btn_s.start <= btnc_i;
snes_js_btn_s.sel <= '0';
snes_js_bus_i_s.latch <= pmod_a_io_1;
snes_js_bus_i_s.clock <= pmod_a_io_2;
pmod_a_io_3 <= snes_js_bus_o_s.data;
end if;
end process;
led_o(0) <= snes_js_btn_leds_s.up;
led_o(1) <= snes_js_btn_leds_s.down;
led_o(2) <= snes_js_btn_leds_s.left;
led_o(3) <= snes_js_btn_leds_s.right;
led_o(4) <= snes_js_btn_leds_s.a;
led_o(5) <= snes_js_btn_leds_s.b;
led_o(6) <= snes_js_btn_leds_s.x;
led_o(7) <= snes_js_btn_leds_s.y;
led_o(8) <= snes_js_btn_leds_s.l;
led_o(9) <= snes_js_btn_leds_s.r;
led_o(10) <= snes_js_btn_leds_s.start;
led_o(11) <= snes_js_btn_leds_s.sel;
tasty: entity work.tasty_snes
port map (
clk_i => clk_i,
rst_i => rst_s,
snes_js_btn_i => snes_js_btn_s,
snes_js_bus_i => snes_js_bus_i_s,
snes_js_bus_o => snes_js_bus_o_s,
debug_enabled_i => switch_i(15),
clock_indicator_o => led_o(14),
latch_indicator_o => led_o(15),
btn_indicator_o => snes_js_btn_leds_s,
switch_i => switch_i,
pc_o => pc_s
);
seven_segment_ctrl0: entity work.seven_segment_ctrl
port map (
clk_i => clk_i,
num_i => pc_s,
c_o => sseg_c_o,
an_o => sseg_an_o
);
end;
| mit | f10370714b18da31c40158eabbda0b40 | 0.513584 | 2.595582 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_reg_module.vhd | 1 | 87,127 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
| mit | 322e847613a1b48d7f2cb9b66775e4c3 | 0.438796 | 3.704537 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_tb.vhd | 3 | 6,128 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth
system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth_inst:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| bsd-3-clause | 322eefb755340dfe161e7fd941155c27 | 0.63267 | 4.050231 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/syn/vhdl/tri_intersect.vhd | 1 | 280,403 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tri_intersect is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ins_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
ins_TVALID : IN STD_LOGIC;
ins_TREADY : OUT STD_LOGIC;
ins_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
ins_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
ins_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TID : IN STD_LOGIC_VECTOR (0 downto 0);
ins_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
outs_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
outs_TVALID : OUT STD_LOGIC;
outs_TREADY : IN STD_LOGIC;
outs_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
outs_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
outs_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
outs_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of tri_intersect is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"tri_intersect,hls_ip_2015_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=121,HLS_SYN_TPT=none,HLS_SYN_MEM=32,HLS_SYN_DSP=127,HLS_SYN_FF=16912,HLS_SYN_LUT=22657}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (37 downto 0) := "00000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (37 downto 0) := "00000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (37 downto 0) := "00000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (37 downto 0) := "00000000100000000000000000000000000000";
constant ap_ST_pp0_stg0_fsm_30 : STD_LOGIC_VECTOR (37 downto 0) := "00000001000000000000000000000000000000";
constant ap_ST_st115_fsm_31 : STD_LOGIC_VECTOR (37 downto 0) := "00000010000000000000000000000000000000";
constant ap_ST_st116_fsm_32 : STD_LOGIC_VECTOR (37 downto 0) := "00000100000000000000000000000000000000";
constant ap_ST_st117_fsm_33 : STD_LOGIC_VECTOR (37 downto 0) := "00001000000000000000000000000000000000";
constant ap_ST_st118_fsm_34 : STD_LOGIC_VECTOR (37 downto 0) := "00010000000000000000000000000000000000";
constant ap_ST_st119_fsm_35 : STD_LOGIC_VECTOR (37 downto 0) := "00100000000000000000000000000000000000";
constant ap_ST_st120_fsm_36 : STD_LOGIC_VECTOR (37 downto 0) := "01000000000000000000000000000000000000";
constant ap_ST_st121_fsm_37 : STD_LOGIC_VECTOR (37 downto 0) := "10000000000000000000000000000000000000";
constant ap_true : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_3F800000 : STD_LOGIC_VECTOR (31 downto 0) := "00111111100000000000000000000000";
constant ap_const_lv32_1E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111100000";
constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111";
constant ap_const_lv32_200 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000000000";
constant ap_const_lv32_21F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000011111";
constant ap_const_lv32_220 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000100000";
constant ap_const_lv32_23F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000001000111111";
constant ap_const_lv576_lc_1 : STD_LOGIC_VECTOR (575 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_1DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111011111";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv32_1A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110100000";
constant ap_const_lv32_1BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110111111";
constant ap_const_lv32_1C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111000000";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal i1_reg_238 : STD_LOGIC_VECTOR (1 downto 0);
signal reg_489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (37 downto 0) := "00000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_75 : BOOLEAN;
signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC;
signal ap_sig_bdd_86 : BOOLEAN;
signal reg_493 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_96 : BOOLEAN;
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_104 : BOOLEAN;
signal reg_497 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_114 : BOOLEAN;
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_122 : BOOLEAN;
signal reg_501 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_132 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_140 : BOOLEAN;
signal reg_505 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_150 : BOOLEAN;
signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC;
signal ap_sig_bdd_158 : BOOLEAN;
signal reg_509 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_168 : BOOLEAN;
signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC;
signal ap_sig_bdd_176 : BOOLEAN;
signal reg_513 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_186 : BOOLEAN;
signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC;
signal ap_sig_bdd_194 : BOOLEAN;
signal reg_517 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_204 : BOOLEAN;
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_212 : BOOLEAN;
signal reg_521 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_222 : BOOLEAN;
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal reg_525 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_240 : BOOLEAN;
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_248 : BOOLEAN;
signal reg_529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_258 : BOOLEAN;
signal ap_sig_cseq_ST_st26_fsm_25 : STD_LOGIC;
signal ap_sig_bdd_266 : BOOLEAN;
signal reg_533 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_276 : BOOLEAN;
signal ap_sig_cseq_ST_st27_fsm_26 : STD_LOGIC;
signal ap_sig_bdd_284 : BOOLEAN;
signal reg_537 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_294 : BOOLEAN;
signal ap_sig_cseq_ST_st28_fsm_27 : STD_LOGIC;
signal ap_sig_bdd_302 : BOOLEAN;
signal reg_541 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_312 : BOOLEAN;
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_320 : BOOLEAN;
signal reg_545 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st116_fsm_32 : STD_LOGIC;
signal ap_sig_bdd_331 : BOOLEAN;
signal ap_sig_ioackin_outs_TREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st119_fsm_35 : STD_LOGIC;
signal ap_sig_bdd_342 : BOOLEAN;
signal reg_549 : STD_LOGIC_VECTOR (31 downto 0);
signal data_array_addr_gep_fu_208_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_addr_reg_1095 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_355 : BOOLEAN;
signal data_array_addr_1_gep_fu_220_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_addr_1_reg_1100 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_365 : BOOLEAN;
signal ins_keep_V_val_reg_1105 : STD_LOGIC_VECTOR (3 downto 0);
signal ins_strb_V_val_reg_1110 : STD_LOGIC_VECTOR (3 downto 0);
signal ins_user_V_val_reg_1115 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_last_V_val_reg_1120 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_id_V_val_reg_1125 : STD_LOGIC_VECTOR (0 downto 0);
signal ins_dest_V_val_reg_1130 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_fu_791_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_reg_1135 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_30 : STD_LOGIC;
signal ap_sig_bdd_387 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it18 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it19 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it20 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it21 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it22 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it23 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it24 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it25 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it26 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it27 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it28 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it29 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it30 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it31 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it32 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it33 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it34 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it35 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it36 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it37 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it38 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it39 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it40 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it41 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it42 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it43 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it44 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it45 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it46 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it47 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it48 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it49 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it50 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it51 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it52 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it53 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it54 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it55 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it56 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it57 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it58 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it59 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it60 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it61 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it62 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it63 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it64 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it65 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it66 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it67 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it68 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it69 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it70 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it71 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it72 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it73 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it74 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it75 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it76 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it77 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it78 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it79 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it80 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it81 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it82 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it83 : STD_LOGIC := '0';
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it35 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it36 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it37 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it38 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it39 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it40 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it41 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it42 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it43 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it44 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it45 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it46 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it47 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it48 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it49 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it50 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it51 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it52 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it53 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it54 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it55 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it56 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it57 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it58 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it59 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it60 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it61 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it62 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it63 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it64 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it65 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it66 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it67 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it68 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it69 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it70 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it71 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it72 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it73 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it74 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it75 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it76 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it77 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it78 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it79 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it80 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it81 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond2_reg_1135_pp0_it82 : STD_LOGIC_VECTOR (0 downto 0);
signal i_fu_797_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal data_array_addr_2_reg_1144 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it7 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it8 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it9 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it10 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it11 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it12 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it13 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it14 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it15 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it16 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it17 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it18 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it19 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it20 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it21 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it22 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it23 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it24 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it25 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it26 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it27 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it28 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it29 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it30 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it31 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it32 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it33 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it34 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it35 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it36 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it37 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it38 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it39 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it40 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it41 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it42 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it43 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it44 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it45 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it46 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it47 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it48 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it49 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it50 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it51 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it52 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it53 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it54 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it55 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it56 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it57 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it58 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it59 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it60 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it61 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it62 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it63 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it64 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it65 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it66 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it67 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it68 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it69 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it70 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it71 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it72 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it73 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it74 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it75 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it76 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it77 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it78 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it79 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it80 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it81 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it82 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_q0 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_load_2_reg_1150 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it2 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it3 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it4 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it5 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it6 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it7 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it8 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it9 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it10 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it11 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it12 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it13 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it14 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it15 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it16 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it17 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it18 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it19 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it20 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it21 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it22 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it23 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it24 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it25 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it26 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it27 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it28 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it29 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it30 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it31 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it32 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it33 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it34 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it35 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it36 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it37 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it38 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it39 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it40 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it41 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it42 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it43 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it44 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it45 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it46 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it47 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it48 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it49 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it50 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it51 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it52 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it53 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it54 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it55 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it56 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it57 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it58 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it59 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it60 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it61 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it62 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it63 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it64 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it65 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it66 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it67 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it68 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it69 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it70 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it71 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it72 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it73 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it74 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it75 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it76 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it77 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it78 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it79 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it80 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it81 : STD_LOGIC_VECTOR (575 downto 0);
signal tmp_3_fu_808_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_reg_1155 : STD_LOGIC_VECTOR (31 downto 0);
signal v0y_assign_new_reg_1160 : STD_LOGIC_VECTOR (31 downto 0);
signal v0z_assign_new_reg_1165 : STD_LOGIC_VECTOR (31 downto 0);
signal v1x_assign_new_reg_1170 : STD_LOGIC_VECTOR (31 downto 0);
signal v1y_assign_new_reg_1175 : STD_LOGIC_VECTOR (31 downto 0);
signal v1z_assign_new_reg_1180 : STD_LOGIC_VECTOR (31 downto 0);
signal v2x_assign_new_reg_1185 : STD_LOGIC_VECTOR (31 downto 0);
signal v2y_assign_new_reg_1190 : STD_LOGIC_VECTOR (31 downto 0);
signal v2z_assign_new_reg_1195 : STD_LOGIC_VECTOR (31 downto 0);
signal rdx_assign_new_reg_1200 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rdy_assign_new_reg_1205 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rdz_assign_new_reg_1210 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it5 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it6 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it7 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it8 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it9 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it10 : STD_LOGIC_VECTOR (31 downto 0);
signal rex_assign_new_reg_1215 : STD_LOGIC_VECTOR (31 downto 0);
signal rey_assign_new_reg_1220 : STD_LOGIC_VECTOR (31 downto 0);
signal rez_assign_new_reg_1225 : STD_LOGIC_VECTOR (31 downto 0);
signal v0x_assign4_fu_952_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal v0y_assign_fu_958_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal v0z_assign_fu_964_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal a_reg_1296 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_a_reg_1296_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_254_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal b_reg_1303 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_b_reg_1303_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_258_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_reg_1310 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_c_reg_1310_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_262_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal d_reg_1317 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_d_reg_1317_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_266_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal e_reg_1324 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_e_reg_1324_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_270_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal f_reg_1331 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_f_reg_1331_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_274_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_reg_1338 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_j_reg_1338_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_278_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_1345 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_k_reg_1345_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_282_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal l_reg_1352 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it11 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_l_reg_1352_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal g_fu_1006_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal g_reg_1359 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it25 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it26 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it27 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it28 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it29 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it30 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it31 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it32 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_g_reg_1359_pp0_it33 : STD_LOGIC_VECTOR (31 downto 0);
signal h_fu_1010_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal h_reg_1366 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_h_reg_1366_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_fu_1014_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_1373 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it12 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it13 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it14 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it15 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it16 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it17 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it18 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it19 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it20 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it21 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it22 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it23 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_i_1_reg_1373_pp0_it24 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_342_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_reg_1380 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_346_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_i_41_reg_1385 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_350_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_i_reg_1390 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_354_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_i_reg_1395 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_358_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_i_reg_1400 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_362_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_i_reg_1405 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_366_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_i_reg_1410 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_370_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_i_reg_1415 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_286_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_i_reg_1420 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_290_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_i_reg_1426 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_374_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_i_reg_1432 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_378_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_9_i_reg_1437 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_294_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_i_reg_1442 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_298_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_i_reg_1448 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_382_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_i_reg_1454 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_386_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_i_reg_1459 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_390_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_i_reg_1464 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_394_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_i_reg_1469 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_398_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_i_reg_1474 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_402_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_i_reg_1479 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_406_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_i_reg_1484 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_410_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_28_i_reg_1489 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_32_i_reg_1494 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_418_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_i_reg_1499 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_302_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_10_i_reg_1504 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_306_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_i_reg_1510 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_310_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_i_reg_1516 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_422_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_i_reg_1521 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_314_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_i_reg_1526 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_426_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_i_reg_1531 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_318_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_i_reg_1536 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_i_reg_1541 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_322_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_i_reg_1546 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_i_reg_1551 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_326_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal m_reg_1556 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_330_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_i_reg_1561 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_334_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_i_reg_1566 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it77 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_338_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_i_reg_1571 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it48 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it49 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it50 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it51 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it52 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it53 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it54 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it55 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it56 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it57 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it58 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it60 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it61 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it62 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it63 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it64 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it65 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it66 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it67 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it69 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it70 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it71 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it72 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it74 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it75 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it76 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it77 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal im_reg_1576 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_neg_i_fu_1022_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_neg_i_reg_1583 : STD_LOGIC_VECTOR (31 downto 0);
signal beta_addr_1174175_part_set_fu_1054_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal beta_addr_1174175_part_set_reg_1593 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_address0 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_ce0 : STD_LOGIC;
signal data_array_we0 : STD_LOGIC;
signal data_array_d0 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_address1 : STD_LOGIC_VECTOR (0 downto 0);
signal data_array_ce1 : STD_LOGIC;
signal data_array_we1 : STD_LOGIC;
signal data_array_d1 : STD_LOGIC_VECTOR (575 downto 0);
signal data_array_q1 : STD_LOGIC_VECTOR (575 downto 0);
signal tmp_s_fu_803_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal t_load_fu_1065_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_fu_1070_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st117_fsm_33 : STD_LOGIC;
signal ap_sig_bdd_1866 : BOOLEAN;
signal beta_load_fu_1075_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st118_fsm_34 : STD_LOGIC;
signal ap_sig_bdd_1874 : BOOLEAN;
signal t_load_s_fu_1080_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_load_s_fu_1085_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st120_fsm_36 : STD_LOGIC;
signal ap_sig_bdd_1883 : BOOLEAN;
signal beta_load_s_fu_1090_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st121_fsm_37 : STD_LOGIC;
signal ap_sig_bdd_1891 : BOOLEAN;
signal ap_reg_ioackin_outs_TREADY : STD_LOGIC := '0';
signal rez_addr149150_part_set_fu_647_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal rez_addr_1146147_part_set_fu_778_p5 : STD_LOGIC_VECTOR (575 downto 0);
signal ap_sig_cseq_ST_st115_fsm_31 : STD_LOGIC;
signal ap_sig_bdd_1948 : BOOLEAN;
signal grp_fu_250_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_254_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_254_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_258_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_258_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_262_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_262_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_266_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_266_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_270_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_270_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_274_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_274_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_278_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_278_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_282_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_282_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_286_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_286_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_290_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_290_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_294_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_294_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_298_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_298_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_302_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_302_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_306_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_306_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_310_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_310_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_314_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_314_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_318_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_318_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_322_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_322_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_326_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_326_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_330_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_330_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_334_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_334_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_338_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_338_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_342_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_342_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_346_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_346_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_350_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_350_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_354_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_354_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_358_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_358_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_362_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_362_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_366_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_366_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_370_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_370_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_374_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_374_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_378_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_378_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_382_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_382_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_386_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_386_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_390_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_390_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_394_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_394_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_398_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_398_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_402_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_402_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_406_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_406_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_410_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_410_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_418_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_418_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_422_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_422_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_426_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_426_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_430_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_434_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_450_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_14_toint_fu_609_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_13_toint_fu_605_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_12_toint_fu_601_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_11_toint_fu_597_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_10_toint_fu_593_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_9_toint_fu_589_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_8_toint_fu_585_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_7_toint_fu_581_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_6_toint_fu_577_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_5_toint_fu_573_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_4_toint_fu_569_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_3_toint_fu_565_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_2_toint_fu_561_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_1_toint_fu_557_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_toint_fu_553_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_613_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal ins_data_tmp_load_29_toint_fu_740_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_28_toint_fu_712_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_27_toint_fu_708_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_26_toint_fu_704_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_25_toint_fu_700_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_24_toint_fu_696_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_23_toint_fu_692_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_22_toint_fu_688_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_21_toint_fu_684_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_20_toint_fu_680_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_19_toint_fu_676_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_18_toint_fu_672_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_17_toint_fu_668_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_16_toint_fu_664_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ins_data_tmp_load_15_toint_fu_660_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_744_p16 : STD_LOGIC_VECTOR (479 downto 0);
signal tmp_61_to_int_i_fu_1019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_438_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_442_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_446_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal beta_write_assign_toint_fu_1040_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal gamma_write_assign_toint_fu_1036_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal t_write_assign_toint_fu_1032_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_1044_p4 : STD_LOGIC_VECTOR (95 downto 0);
signal grp_fu_459_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_250_ce : STD_LOGIC;
signal grp_fu_254_ce : STD_LOGIC;
signal grp_fu_258_ce : STD_LOGIC;
signal grp_fu_262_ce : STD_LOGIC;
signal grp_fu_266_ce : STD_LOGIC;
signal grp_fu_270_ce : STD_LOGIC;
signal grp_fu_274_ce : STD_LOGIC;
signal grp_fu_278_ce : STD_LOGIC;
signal grp_fu_282_ce : STD_LOGIC;
signal grp_fu_286_ce : STD_LOGIC;
signal grp_fu_290_ce : STD_LOGIC;
signal grp_fu_294_ce : STD_LOGIC;
signal grp_fu_298_ce : STD_LOGIC;
signal grp_fu_302_ce : STD_LOGIC;
signal grp_fu_306_ce : STD_LOGIC;
signal grp_fu_310_ce : STD_LOGIC;
signal grp_fu_314_ce : STD_LOGIC;
signal grp_fu_318_ce : STD_LOGIC;
signal grp_fu_322_ce : STD_LOGIC;
signal grp_fu_326_ce : STD_LOGIC;
signal grp_fu_330_ce : STD_LOGIC;
signal grp_fu_334_ce : STD_LOGIC;
signal grp_fu_338_ce : STD_LOGIC;
signal grp_fu_342_ce : STD_LOGIC;
signal grp_fu_346_ce : STD_LOGIC;
signal grp_fu_350_ce : STD_LOGIC;
signal grp_fu_354_ce : STD_LOGIC;
signal grp_fu_358_ce : STD_LOGIC;
signal grp_fu_362_ce : STD_LOGIC;
signal grp_fu_366_ce : STD_LOGIC;
signal grp_fu_370_ce : STD_LOGIC;
signal grp_fu_374_ce : STD_LOGIC;
signal grp_fu_378_ce : STD_LOGIC;
signal grp_fu_382_ce : STD_LOGIC;
signal grp_fu_386_ce : STD_LOGIC;
signal grp_fu_390_ce : STD_LOGIC;
signal grp_fu_394_ce : STD_LOGIC;
signal grp_fu_398_ce : STD_LOGIC;
signal grp_fu_402_ce : STD_LOGIC;
signal grp_fu_406_ce : STD_LOGIC;
signal grp_fu_410_ce : STD_LOGIC;
signal grp_fu_414_ce : STD_LOGIC;
signal grp_fu_418_ce : STD_LOGIC;
signal grp_fu_422_ce : STD_LOGIC;
signal grp_fu_426_ce : STD_LOGIC;
signal grp_fu_430_ce : STD_LOGIC;
signal grp_fu_434_ce : STD_LOGIC;
signal grp_fu_438_ce : STD_LOGIC;
signal grp_fu_442_ce : STD_LOGIC;
signal grp_fu_446_ce : STD_LOGIC;
signal grp_fu_450_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (37 downto 0);
component tri_intersect_fsub_32ns_32ns_32_9_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fadd_32ns_32ns_32_9_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fmul_32ns_32ns_32_5_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_fdiv_32ns_32ns_32_30 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component tri_intersect_data_array IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (0 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (575 downto 0);
q0 : OUT STD_LOGIC_VECTOR (575 downto 0);
address1 : IN STD_LOGIC_VECTOR (0 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (575 downto 0);
q1 : OUT STD_LOGIC_VECTOR (575 downto 0) );
end component;
begin
data_array_U : component tri_intersect_data_array
generic map (
DataWidth => 576,
AddressRange => 2,
AddressWidth => 1)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => data_array_address0,
ce0 => data_array_ce0,
we0 => data_array_we0,
d0 => data_array_d0,
q0 => data_array_q0,
address1 => data_array_address1,
ce1 => data_array_ce1,
we1 => data_array_we1,
d1 => data_array_d1,
q1 => data_array_q1);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U0 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_250_p0,
din1 => grp_fu_250_p1,
ce => grp_fu_250_ce,
dout => grp_fu_250_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U1 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_254_p0,
din1 => grp_fu_254_p1,
ce => grp_fu_254_ce,
dout => grp_fu_254_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U2 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_258_p0,
din1 => grp_fu_258_p1,
ce => grp_fu_258_ce,
dout => grp_fu_258_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U3 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_262_p0,
din1 => grp_fu_262_p1,
ce => grp_fu_262_ce,
dout => grp_fu_262_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U4 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_266_p0,
din1 => grp_fu_266_p1,
ce => grp_fu_266_ce,
dout => grp_fu_266_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U5 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_270_p0,
din1 => grp_fu_270_p1,
ce => grp_fu_270_ce,
dout => grp_fu_270_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U6 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_274_p0,
din1 => grp_fu_274_p1,
ce => grp_fu_274_ce,
dout => grp_fu_274_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U7 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_278_p0,
din1 => grp_fu_278_p1,
ce => grp_fu_278_ce,
dout => grp_fu_278_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U8 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_282_p0,
din1 => grp_fu_282_p1,
ce => grp_fu_282_ce,
dout => grp_fu_282_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U9 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_286_p0,
din1 => grp_fu_286_p1,
ce => grp_fu_286_ce,
dout => grp_fu_286_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U10 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_290_p0,
din1 => grp_fu_290_p1,
ce => grp_fu_290_ce,
dout => grp_fu_290_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U11 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_294_p0,
din1 => grp_fu_294_p1,
ce => grp_fu_294_ce,
dout => grp_fu_294_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U12 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_298_p0,
din1 => grp_fu_298_p1,
ce => grp_fu_298_ce,
dout => grp_fu_298_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U13 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_302_p0,
din1 => grp_fu_302_p1,
ce => grp_fu_302_ce,
dout => grp_fu_302_p2);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U14 : component tri_intersect_fsub_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_306_p0,
din1 => grp_fu_306_p1,
ce => grp_fu_306_ce,
dout => grp_fu_306_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U15 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_310_p0,
din1 => grp_fu_310_p1,
ce => grp_fu_310_ce,
dout => grp_fu_310_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U16 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_314_p0,
din1 => grp_fu_314_p1,
ce => grp_fu_314_ce,
dout => grp_fu_314_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U17 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_318_p0,
din1 => grp_fu_318_p1,
ce => grp_fu_318_ce,
dout => grp_fu_318_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U18 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_322_p0,
din1 => grp_fu_322_p1,
ce => grp_fu_322_ce,
dout => grp_fu_322_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U19 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_326_p0,
din1 => grp_fu_326_p1,
ce => grp_fu_326_ce,
dout => grp_fu_326_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U20 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_330_p0,
din1 => grp_fu_330_p1,
ce => grp_fu_330_ce,
dout => grp_fu_330_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U21 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_334_p0,
din1 => grp_fu_334_p1,
ce => grp_fu_334_ce,
dout => grp_fu_334_p2);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U22 : component tri_intersect_fadd_32ns_32ns_32_9_full_dsp
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_338_p0,
din1 => grp_fu_338_p1,
ce => grp_fu_338_ce,
dout => grp_fu_338_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U23 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_342_p0,
din1 => grp_fu_342_p1,
ce => grp_fu_342_ce,
dout => grp_fu_342_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U24 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_346_p0,
din1 => grp_fu_346_p1,
ce => grp_fu_346_ce,
dout => grp_fu_346_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U25 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_350_p0,
din1 => grp_fu_350_p1,
ce => grp_fu_350_ce,
dout => grp_fu_350_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U26 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_354_p0,
din1 => grp_fu_354_p1,
ce => grp_fu_354_ce,
dout => grp_fu_354_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U27 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_358_p0,
din1 => grp_fu_358_p1,
ce => grp_fu_358_ce,
dout => grp_fu_358_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U28 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_362_p0,
din1 => grp_fu_362_p1,
ce => grp_fu_362_ce,
dout => grp_fu_362_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U29 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_366_p0,
din1 => grp_fu_366_p1,
ce => grp_fu_366_ce,
dout => grp_fu_366_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U30 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_370_p0,
din1 => grp_fu_370_p1,
ce => grp_fu_370_ce,
dout => grp_fu_370_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U31 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_374_p0,
din1 => grp_fu_374_p1,
ce => grp_fu_374_ce,
dout => grp_fu_374_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U32 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_378_p0,
din1 => grp_fu_378_p1,
ce => grp_fu_378_ce,
dout => grp_fu_378_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U33 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_382_p0,
din1 => grp_fu_382_p1,
ce => grp_fu_382_ce,
dout => grp_fu_382_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U34 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_386_p0,
din1 => grp_fu_386_p1,
ce => grp_fu_386_ce,
dout => grp_fu_386_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U35 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_390_p0,
din1 => grp_fu_390_p1,
ce => grp_fu_390_ce,
dout => grp_fu_390_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U36 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_394_p0,
din1 => grp_fu_394_p1,
ce => grp_fu_394_ce,
dout => grp_fu_394_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U37 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_398_p0,
din1 => grp_fu_398_p1,
ce => grp_fu_398_ce,
dout => grp_fu_398_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U38 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_402_p0,
din1 => grp_fu_402_p1,
ce => grp_fu_402_ce,
dout => grp_fu_402_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U39 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_406_p0,
din1 => grp_fu_406_p1,
ce => grp_fu_406_ce,
dout => grp_fu_406_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U40 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_410_p0,
din1 => grp_fu_410_p1,
ce => grp_fu_410_ce,
dout => grp_fu_410_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U41 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_414_p0,
din1 => grp_fu_414_p1,
ce => grp_fu_414_ce,
dout => grp_fu_414_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U42 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_418_p0,
din1 => grp_fu_418_p1,
ce => grp_fu_418_ce,
dout => grp_fu_418_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U43 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_422_p0,
din1 => grp_fu_422_p1,
ce => grp_fu_422_ce,
dout => grp_fu_422_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U44 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_426_p0,
din1 => grp_fu_426_p1,
ce => grp_fu_426_ce,
dout => grp_fu_426_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U45 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_430_p0,
din1 => grp_fu_430_p1,
ce => grp_fu_430_ce,
dout => grp_fu_430_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U46 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_434_p0,
din1 => grp_fu_434_p1,
ce => grp_fu_434_ce,
dout => grp_fu_434_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U47 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_438_p0,
din1 => grp_fu_438_p1,
ce => grp_fu_438_ce,
dout => grp_fu_438_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U48 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_442_p0,
din1 => grp_fu_442_p1,
ce => grp_fu_442_ce,
dout => grp_fu_442_p2);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U49 : component tri_intersect_fmul_32ns_32ns_32_5_max_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_446_p0,
din1 => grp_fu_446_p1,
ce => grp_fu_446_ce,
dout => grp_fu_446_p2);
tri_intersect_fdiv_32ns_32ns_32_30_U50 : component tri_intersect_fdiv_32ns_32ns_32_30
generic map (
ID => 1,
NUM_STAGE => 30,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_450_p0,
din1 => grp_fu_450_p1,
ce => grp_fu_450_ce,
dout => grp_fu_450_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_outs_TREADY assign process. --
ap_reg_ioackin_outs_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) and not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36)) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37)))) then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36) and (ap_const_logic_1 = outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37) and (ap_const_logic_1 = outs_TREADY)))) then
ap_reg_ioackin_outs_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and not((exitcond2_fu_791_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (exitcond2_fu_791_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and not((exitcond2_fu_791_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it18 assign process. --
ap_reg_ppiten_pp0_it18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it19 assign process. --
ap_reg_ppiten_pp0_it19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it20 assign process. --
ap_reg_ppiten_pp0_it20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it21 assign process. --
ap_reg_ppiten_pp0_it21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it22 assign process. --
ap_reg_ppiten_pp0_it22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it23 assign process. --
ap_reg_ppiten_pp0_it23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it24 assign process. --
ap_reg_ppiten_pp0_it24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it25 assign process. --
ap_reg_ppiten_pp0_it25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it26 assign process. --
ap_reg_ppiten_pp0_it26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it27 assign process. --
ap_reg_ppiten_pp0_it27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it28 assign process. --
ap_reg_ppiten_pp0_it28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it29 assign process. --
ap_reg_ppiten_pp0_it29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it30 assign process. --
ap_reg_ppiten_pp0_it30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it31 assign process. --
ap_reg_ppiten_pp0_it31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it32 assign process. --
ap_reg_ppiten_pp0_it32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it33 assign process. --
ap_reg_ppiten_pp0_it33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it34 assign process. --
ap_reg_ppiten_pp0_it34_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it35 assign process. --
ap_reg_ppiten_pp0_it35_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it36 assign process. --
ap_reg_ppiten_pp0_it36_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it36 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it36 <= ap_reg_ppiten_pp0_it35;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it37 assign process. --
ap_reg_ppiten_pp0_it37_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it37 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it37 <= ap_reg_ppiten_pp0_it36;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it38 assign process. --
ap_reg_ppiten_pp0_it38_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it38 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it38 <= ap_reg_ppiten_pp0_it37;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it39 assign process. --
ap_reg_ppiten_pp0_it39_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it39 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it39 <= ap_reg_ppiten_pp0_it38;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it40 assign process. --
ap_reg_ppiten_pp0_it40_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it40 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it40 <= ap_reg_ppiten_pp0_it39;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it41 assign process. --
ap_reg_ppiten_pp0_it41_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it41 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it41 <= ap_reg_ppiten_pp0_it40;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it42 assign process. --
ap_reg_ppiten_pp0_it42_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it42 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it42 <= ap_reg_ppiten_pp0_it41;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it43 assign process. --
ap_reg_ppiten_pp0_it43_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it43 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it43 <= ap_reg_ppiten_pp0_it42;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it44 assign process. --
ap_reg_ppiten_pp0_it44_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it44 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it44 <= ap_reg_ppiten_pp0_it43;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it45 assign process. --
ap_reg_ppiten_pp0_it45_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it45 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it45 <= ap_reg_ppiten_pp0_it44;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it46 assign process. --
ap_reg_ppiten_pp0_it46_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it46 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it46 <= ap_reg_ppiten_pp0_it45;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it47 assign process. --
ap_reg_ppiten_pp0_it47_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it47 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it47 <= ap_reg_ppiten_pp0_it46;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it48 assign process. --
ap_reg_ppiten_pp0_it48_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it48 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it48 <= ap_reg_ppiten_pp0_it47;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it49 assign process. --
ap_reg_ppiten_pp0_it49_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it49 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it49 <= ap_reg_ppiten_pp0_it48;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it50 assign process. --
ap_reg_ppiten_pp0_it50_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it50 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it50 <= ap_reg_ppiten_pp0_it49;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it51 assign process. --
ap_reg_ppiten_pp0_it51_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it51 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it51 <= ap_reg_ppiten_pp0_it50;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it52 assign process. --
ap_reg_ppiten_pp0_it52_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it52 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it52 <= ap_reg_ppiten_pp0_it51;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it53 assign process. --
ap_reg_ppiten_pp0_it53_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it53 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it53 <= ap_reg_ppiten_pp0_it52;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it54 assign process. --
ap_reg_ppiten_pp0_it54_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it54 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it54 <= ap_reg_ppiten_pp0_it53;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it55 assign process. --
ap_reg_ppiten_pp0_it55_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it55 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it55 <= ap_reg_ppiten_pp0_it54;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it56 assign process. --
ap_reg_ppiten_pp0_it56_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it56 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it56 <= ap_reg_ppiten_pp0_it55;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it57 assign process. --
ap_reg_ppiten_pp0_it57_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it57 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it57 <= ap_reg_ppiten_pp0_it56;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it58 assign process. --
ap_reg_ppiten_pp0_it58_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it58 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it58 <= ap_reg_ppiten_pp0_it57;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it59 assign process. --
ap_reg_ppiten_pp0_it59_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it59 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it59 <= ap_reg_ppiten_pp0_it58;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it60 assign process. --
ap_reg_ppiten_pp0_it60_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it60 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it60 <= ap_reg_ppiten_pp0_it59;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it61 assign process. --
ap_reg_ppiten_pp0_it61_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it61 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it61 <= ap_reg_ppiten_pp0_it60;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it62 assign process. --
ap_reg_ppiten_pp0_it62_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it62 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it62 <= ap_reg_ppiten_pp0_it61;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it63 assign process. --
ap_reg_ppiten_pp0_it63_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it63 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it63 <= ap_reg_ppiten_pp0_it62;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it64 assign process. --
ap_reg_ppiten_pp0_it64_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it64 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it64 <= ap_reg_ppiten_pp0_it63;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it65 assign process. --
ap_reg_ppiten_pp0_it65_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it65 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it65 <= ap_reg_ppiten_pp0_it64;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it66 assign process. --
ap_reg_ppiten_pp0_it66_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it66 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it66 <= ap_reg_ppiten_pp0_it65;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it67 assign process. --
ap_reg_ppiten_pp0_it67_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it67 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it67 <= ap_reg_ppiten_pp0_it66;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it68 assign process. --
ap_reg_ppiten_pp0_it68_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it68 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it68 <= ap_reg_ppiten_pp0_it67;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it69 assign process. --
ap_reg_ppiten_pp0_it69_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it69 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it69 <= ap_reg_ppiten_pp0_it68;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it70 assign process. --
ap_reg_ppiten_pp0_it70_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it70 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it70 <= ap_reg_ppiten_pp0_it69;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it71 assign process. --
ap_reg_ppiten_pp0_it71_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it71 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it71 <= ap_reg_ppiten_pp0_it70;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it72 assign process. --
ap_reg_ppiten_pp0_it72_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it72 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it72 <= ap_reg_ppiten_pp0_it71;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it73 assign process. --
ap_reg_ppiten_pp0_it73_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it73 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it73 <= ap_reg_ppiten_pp0_it72;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it74 assign process. --
ap_reg_ppiten_pp0_it74_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it74 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it74 <= ap_reg_ppiten_pp0_it73;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it75 assign process. --
ap_reg_ppiten_pp0_it75_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it75 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it75 <= ap_reg_ppiten_pp0_it74;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it76 assign process. --
ap_reg_ppiten_pp0_it76_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it76 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it76 <= ap_reg_ppiten_pp0_it75;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it77 assign process. --
ap_reg_ppiten_pp0_it77_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it77 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it77 <= ap_reg_ppiten_pp0_it76;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it78 assign process. --
ap_reg_ppiten_pp0_it78_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it78 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it78 <= ap_reg_ppiten_pp0_it77;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it79 assign process. --
ap_reg_ppiten_pp0_it79_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it79 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it79 <= ap_reg_ppiten_pp0_it78;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it80 assign process. --
ap_reg_ppiten_pp0_it80_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it80 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it80 <= ap_reg_ppiten_pp0_it79;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it81 assign process. --
ap_reg_ppiten_pp0_it81_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it81 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it81 <= ap_reg_ppiten_pp0_it80;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it82 assign process. --
ap_reg_ppiten_pp0_it82_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it82 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it82 <= ap_reg_ppiten_pp0_it81;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it83 assign process. --
ap_reg_ppiten_pp0_it83_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it83 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it83 <= ap_reg_ppiten_pp0_it82;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end process;
-- i1_reg_238 assign process. --
i1_reg_238_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
i1_reg_238 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond2_fu_791_p2 = ap_const_lv1_0))) then
i1_reg_238 <= i_fu_797_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it9 = ap_const_lv1_0)) then
a_reg_1296 <= grp_fu_250_p2;
b_reg_1303 <= grp_fu_254_p2;
c_reg_1310 <= grp_fu_258_p2;
d_reg_1317 <= grp_fu_262_p2;
e_reg_1324 <= grp_fu_266_p2;
f_reg_1331 <= grp_fu_270_p2;
j_reg_1338 <= grp_fu_274_p2;
k_reg_1345 <= grp_fu_278_p2;
l_reg_1352 <= grp_fu_282_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_true = ap_true)) then
ap_reg_ppstg_a_reg_1296_pp0_it11 <= a_reg_1296;
ap_reg_ppstg_a_reg_1296_pp0_it12 <= ap_reg_ppstg_a_reg_1296_pp0_it11;
ap_reg_ppstg_a_reg_1296_pp0_it13 <= ap_reg_ppstg_a_reg_1296_pp0_it12;
ap_reg_ppstg_a_reg_1296_pp0_it14 <= ap_reg_ppstg_a_reg_1296_pp0_it13;
ap_reg_ppstg_a_reg_1296_pp0_it15 <= ap_reg_ppstg_a_reg_1296_pp0_it14;
ap_reg_ppstg_a_reg_1296_pp0_it16 <= ap_reg_ppstg_a_reg_1296_pp0_it15;
ap_reg_ppstg_a_reg_1296_pp0_it17 <= ap_reg_ppstg_a_reg_1296_pp0_it16;
ap_reg_ppstg_a_reg_1296_pp0_it18 <= ap_reg_ppstg_a_reg_1296_pp0_it17;
ap_reg_ppstg_a_reg_1296_pp0_it19 <= ap_reg_ppstg_a_reg_1296_pp0_it18;
ap_reg_ppstg_a_reg_1296_pp0_it20 <= ap_reg_ppstg_a_reg_1296_pp0_it19;
ap_reg_ppstg_a_reg_1296_pp0_it21 <= ap_reg_ppstg_a_reg_1296_pp0_it20;
ap_reg_ppstg_a_reg_1296_pp0_it22 <= ap_reg_ppstg_a_reg_1296_pp0_it21;
ap_reg_ppstg_a_reg_1296_pp0_it23 <= ap_reg_ppstg_a_reg_1296_pp0_it22;
ap_reg_ppstg_a_reg_1296_pp0_it24 <= ap_reg_ppstg_a_reg_1296_pp0_it23;
ap_reg_ppstg_b_reg_1303_pp0_it11 <= b_reg_1303;
ap_reg_ppstg_b_reg_1303_pp0_it12 <= ap_reg_ppstg_b_reg_1303_pp0_it11;
ap_reg_ppstg_b_reg_1303_pp0_it13 <= ap_reg_ppstg_b_reg_1303_pp0_it12;
ap_reg_ppstg_b_reg_1303_pp0_it14 <= ap_reg_ppstg_b_reg_1303_pp0_it13;
ap_reg_ppstg_b_reg_1303_pp0_it15 <= ap_reg_ppstg_b_reg_1303_pp0_it14;
ap_reg_ppstg_b_reg_1303_pp0_it16 <= ap_reg_ppstg_b_reg_1303_pp0_it15;
ap_reg_ppstg_b_reg_1303_pp0_it17 <= ap_reg_ppstg_b_reg_1303_pp0_it16;
ap_reg_ppstg_b_reg_1303_pp0_it18 <= ap_reg_ppstg_b_reg_1303_pp0_it17;
ap_reg_ppstg_b_reg_1303_pp0_it19 <= ap_reg_ppstg_b_reg_1303_pp0_it18;
ap_reg_ppstg_b_reg_1303_pp0_it20 <= ap_reg_ppstg_b_reg_1303_pp0_it19;
ap_reg_ppstg_b_reg_1303_pp0_it21 <= ap_reg_ppstg_b_reg_1303_pp0_it20;
ap_reg_ppstg_b_reg_1303_pp0_it22 <= ap_reg_ppstg_b_reg_1303_pp0_it21;
ap_reg_ppstg_b_reg_1303_pp0_it23 <= ap_reg_ppstg_b_reg_1303_pp0_it22;
ap_reg_ppstg_b_reg_1303_pp0_it24 <= ap_reg_ppstg_b_reg_1303_pp0_it23;
ap_reg_ppstg_c_reg_1310_pp0_it11 <= c_reg_1310;
ap_reg_ppstg_c_reg_1310_pp0_it12 <= ap_reg_ppstg_c_reg_1310_pp0_it11;
ap_reg_ppstg_c_reg_1310_pp0_it13 <= ap_reg_ppstg_c_reg_1310_pp0_it12;
ap_reg_ppstg_c_reg_1310_pp0_it14 <= ap_reg_ppstg_c_reg_1310_pp0_it13;
ap_reg_ppstg_c_reg_1310_pp0_it15 <= ap_reg_ppstg_c_reg_1310_pp0_it14;
ap_reg_ppstg_c_reg_1310_pp0_it16 <= ap_reg_ppstg_c_reg_1310_pp0_it15;
ap_reg_ppstg_c_reg_1310_pp0_it17 <= ap_reg_ppstg_c_reg_1310_pp0_it16;
ap_reg_ppstg_c_reg_1310_pp0_it18 <= ap_reg_ppstg_c_reg_1310_pp0_it17;
ap_reg_ppstg_c_reg_1310_pp0_it19 <= ap_reg_ppstg_c_reg_1310_pp0_it18;
ap_reg_ppstg_c_reg_1310_pp0_it20 <= ap_reg_ppstg_c_reg_1310_pp0_it19;
ap_reg_ppstg_c_reg_1310_pp0_it21 <= ap_reg_ppstg_c_reg_1310_pp0_it20;
ap_reg_ppstg_c_reg_1310_pp0_it22 <= ap_reg_ppstg_c_reg_1310_pp0_it21;
ap_reg_ppstg_c_reg_1310_pp0_it23 <= ap_reg_ppstg_c_reg_1310_pp0_it22;
ap_reg_ppstg_c_reg_1310_pp0_it24 <= ap_reg_ppstg_c_reg_1310_pp0_it23;
ap_reg_ppstg_c_reg_1310_pp0_it25 <= ap_reg_ppstg_c_reg_1310_pp0_it24;
ap_reg_ppstg_c_reg_1310_pp0_it26 <= ap_reg_ppstg_c_reg_1310_pp0_it25;
ap_reg_ppstg_c_reg_1310_pp0_it27 <= ap_reg_ppstg_c_reg_1310_pp0_it26;
ap_reg_ppstg_c_reg_1310_pp0_it28 <= ap_reg_ppstg_c_reg_1310_pp0_it27;
ap_reg_ppstg_c_reg_1310_pp0_it29 <= ap_reg_ppstg_c_reg_1310_pp0_it28;
ap_reg_ppstg_c_reg_1310_pp0_it30 <= ap_reg_ppstg_c_reg_1310_pp0_it29;
ap_reg_ppstg_c_reg_1310_pp0_it31 <= ap_reg_ppstg_c_reg_1310_pp0_it30;
ap_reg_ppstg_c_reg_1310_pp0_it32 <= ap_reg_ppstg_c_reg_1310_pp0_it31;
ap_reg_ppstg_c_reg_1310_pp0_it33 <= ap_reg_ppstg_c_reg_1310_pp0_it32;
ap_reg_ppstg_d_reg_1317_pp0_it11 <= d_reg_1317;
ap_reg_ppstg_d_reg_1317_pp0_it12 <= ap_reg_ppstg_d_reg_1317_pp0_it11;
ap_reg_ppstg_d_reg_1317_pp0_it13 <= ap_reg_ppstg_d_reg_1317_pp0_it12;
ap_reg_ppstg_d_reg_1317_pp0_it14 <= ap_reg_ppstg_d_reg_1317_pp0_it13;
ap_reg_ppstg_d_reg_1317_pp0_it15 <= ap_reg_ppstg_d_reg_1317_pp0_it14;
ap_reg_ppstg_d_reg_1317_pp0_it16 <= ap_reg_ppstg_d_reg_1317_pp0_it15;
ap_reg_ppstg_d_reg_1317_pp0_it17 <= ap_reg_ppstg_d_reg_1317_pp0_it16;
ap_reg_ppstg_d_reg_1317_pp0_it18 <= ap_reg_ppstg_d_reg_1317_pp0_it17;
ap_reg_ppstg_d_reg_1317_pp0_it19 <= ap_reg_ppstg_d_reg_1317_pp0_it18;
ap_reg_ppstg_d_reg_1317_pp0_it20 <= ap_reg_ppstg_d_reg_1317_pp0_it19;
ap_reg_ppstg_d_reg_1317_pp0_it21 <= ap_reg_ppstg_d_reg_1317_pp0_it20;
ap_reg_ppstg_d_reg_1317_pp0_it22 <= ap_reg_ppstg_d_reg_1317_pp0_it21;
ap_reg_ppstg_d_reg_1317_pp0_it23 <= ap_reg_ppstg_d_reg_1317_pp0_it22;
ap_reg_ppstg_d_reg_1317_pp0_it24 <= ap_reg_ppstg_d_reg_1317_pp0_it23;
ap_reg_ppstg_d_reg_1317_pp0_it25 <= ap_reg_ppstg_d_reg_1317_pp0_it24;
ap_reg_ppstg_d_reg_1317_pp0_it26 <= ap_reg_ppstg_d_reg_1317_pp0_it25;
ap_reg_ppstg_d_reg_1317_pp0_it27 <= ap_reg_ppstg_d_reg_1317_pp0_it26;
ap_reg_ppstg_d_reg_1317_pp0_it28 <= ap_reg_ppstg_d_reg_1317_pp0_it27;
ap_reg_ppstg_d_reg_1317_pp0_it29 <= ap_reg_ppstg_d_reg_1317_pp0_it28;
ap_reg_ppstg_d_reg_1317_pp0_it30 <= ap_reg_ppstg_d_reg_1317_pp0_it29;
ap_reg_ppstg_d_reg_1317_pp0_it31 <= ap_reg_ppstg_d_reg_1317_pp0_it30;
ap_reg_ppstg_d_reg_1317_pp0_it32 <= ap_reg_ppstg_d_reg_1317_pp0_it31;
ap_reg_ppstg_d_reg_1317_pp0_it33 <= ap_reg_ppstg_d_reg_1317_pp0_it32;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it10 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it9;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it11 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it10;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it12 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it11;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it13 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it12;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it14 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it13;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it15 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it14;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it16 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it15;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it17 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it16;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it18 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it17;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it19 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it18;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it2 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it1;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it20 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it19;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it21 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it20;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it22 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it21;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it23 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it22;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it24 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it23;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it25 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it24;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it26 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it25;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it27 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it26;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it28 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it27;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it29 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it28;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it3 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it2;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it30 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it29;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it31 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it30;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it32 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it31;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it33 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it32;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it34 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it33;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it35 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it34;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it36 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it35;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it37 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it36;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it38 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it37;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it39 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it38;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it4 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it3;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it40 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it39;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it41 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it40;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it42 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it41;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it43 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it42;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it44 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it43;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it45 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it44;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it46 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it45;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it47 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it46;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it48 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it47;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it49 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it48;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it5 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it4;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it50 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it49;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it51 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it50;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it52 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it51;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it53 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it52;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it54 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it53;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it55 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it54;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it56 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it55;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it57 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it56;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it58 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it57;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it59 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it58;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it6 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it5;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it60 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it59;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it61 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it60;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it62 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it61;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it63 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it62;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it64 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it63;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it65 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it64;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it66 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it65;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it67 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it66;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it68 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it67;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it69 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it68;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it7 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it6;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it70 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it69;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it71 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it70;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it72 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it71;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it73 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it72;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it74 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it73;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it75 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it74;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it76 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it75;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it77 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it76;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it78 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it77;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it79 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it78;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it8 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it7;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it80 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it79;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it81 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it80;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it82 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it81;
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it9 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it8;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it10 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it9;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it11 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it10;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it12 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it11;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it13 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it12;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it14 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it13;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it15 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it14;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it16 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it15;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it17 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it16;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it18 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it17;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it19 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it18;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it2 <= data_array_load_2_reg_1150;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it20 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it19;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it21 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it20;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it22 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it21;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it23 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it22;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it24 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it23;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it25 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it24;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it26 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it25;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it27 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it26;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it28 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it27;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it29 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it28;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it3 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it2;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it30 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it29;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it31 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it30;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it32 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it31;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it33 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it32;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it34 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it33;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it35 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it34;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it36 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it35;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it37 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it36;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it38 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it37;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it39 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it38;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it4 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it3;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it40 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it39;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it41 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it40;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it42 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it41;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it43 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it42;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it44 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it43;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it45 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it44;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it46 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it45;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it47 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it46;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it48 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it47;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it49 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it48;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it5 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it4;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it50 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it49;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it51 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it50;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it52 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it51;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it53 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it52;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it54 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it53;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it55 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it54;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it56 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it55;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it57 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it56;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it58 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it57;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it59 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it58;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it6 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it5;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it60 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it59;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it61 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it60;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it62 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it61;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it63 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it62;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it64 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it63;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it65 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it64;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it66 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it65;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it67 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it66;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it68 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it67;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it69 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it68;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it7 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it6;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it70 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it69;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it71 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it70;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it72 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it71;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it73 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it72;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it74 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it73;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it75 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it74;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it76 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it75;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it77 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it76;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it78 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it77;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it79 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it78;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it8 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it7;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it80 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it79;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it81 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it80;
ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it9 <= ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it8;
ap_reg_ppstg_e_reg_1324_pp0_it11 <= e_reg_1324;
ap_reg_ppstg_e_reg_1324_pp0_it12 <= ap_reg_ppstg_e_reg_1324_pp0_it11;
ap_reg_ppstg_e_reg_1324_pp0_it13 <= ap_reg_ppstg_e_reg_1324_pp0_it12;
ap_reg_ppstg_e_reg_1324_pp0_it14 <= ap_reg_ppstg_e_reg_1324_pp0_it13;
ap_reg_ppstg_e_reg_1324_pp0_it15 <= ap_reg_ppstg_e_reg_1324_pp0_it14;
ap_reg_ppstg_e_reg_1324_pp0_it16 <= ap_reg_ppstg_e_reg_1324_pp0_it15;
ap_reg_ppstg_e_reg_1324_pp0_it17 <= ap_reg_ppstg_e_reg_1324_pp0_it16;
ap_reg_ppstg_e_reg_1324_pp0_it18 <= ap_reg_ppstg_e_reg_1324_pp0_it17;
ap_reg_ppstg_e_reg_1324_pp0_it19 <= ap_reg_ppstg_e_reg_1324_pp0_it18;
ap_reg_ppstg_e_reg_1324_pp0_it20 <= ap_reg_ppstg_e_reg_1324_pp0_it19;
ap_reg_ppstg_e_reg_1324_pp0_it21 <= ap_reg_ppstg_e_reg_1324_pp0_it20;
ap_reg_ppstg_e_reg_1324_pp0_it22 <= ap_reg_ppstg_e_reg_1324_pp0_it21;
ap_reg_ppstg_e_reg_1324_pp0_it23 <= ap_reg_ppstg_e_reg_1324_pp0_it22;
ap_reg_ppstg_e_reg_1324_pp0_it24 <= ap_reg_ppstg_e_reg_1324_pp0_it23;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it10 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it9;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it11 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it10;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it12 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it11;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it13 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it12;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it14 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it13;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it15 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it14;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it16 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it15;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it17 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it16;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it18 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it17;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it19 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it18;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it2 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it1;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it20 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it19;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it21 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it20;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it22 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it21;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it23 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it22;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it24 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it23;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it25 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it24;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it26 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it25;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it27 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it26;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it28 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it27;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it29 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it28;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it3 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it2;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it30 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it29;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it31 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it30;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it32 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it31;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it33 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it32;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it34 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it33;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it35 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it34;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it36 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it35;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it37 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it36;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it38 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it37;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it39 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it38;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it4 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it3;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it40 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it39;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it41 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it40;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it42 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it41;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it43 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it42;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it44 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it43;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it45 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it44;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it46 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it45;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it47 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it46;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it48 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it47;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it49 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it48;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it5 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it4;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it50 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it49;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it51 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it50;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it52 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it51;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it53 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it52;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it54 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it53;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it55 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it54;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it56 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it55;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it57 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it56;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it58 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it57;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it59 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it58;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it6 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it5;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it60 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it59;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it61 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it60;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it62 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it61;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it63 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it62;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it64 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it63;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it65 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it64;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it66 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it65;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it67 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it66;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it68 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it67;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it69 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it68;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it7 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it6;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it70 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it69;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it71 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it70;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it72 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it71;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it73 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it72;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it74 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it73;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it75 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it74;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it76 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it75;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it77 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it76;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it78 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it77;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it79 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it78;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it8 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it7;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it80 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it79;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it81 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it80;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it82 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it81;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it9 <= ap_reg_ppstg_exitcond2_reg_1135_pp0_it8;
ap_reg_ppstg_f_reg_1331_pp0_it11 <= f_reg_1331;
ap_reg_ppstg_f_reg_1331_pp0_it12 <= ap_reg_ppstg_f_reg_1331_pp0_it11;
ap_reg_ppstg_f_reg_1331_pp0_it13 <= ap_reg_ppstg_f_reg_1331_pp0_it12;
ap_reg_ppstg_f_reg_1331_pp0_it14 <= ap_reg_ppstg_f_reg_1331_pp0_it13;
ap_reg_ppstg_f_reg_1331_pp0_it15 <= ap_reg_ppstg_f_reg_1331_pp0_it14;
ap_reg_ppstg_f_reg_1331_pp0_it16 <= ap_reg_ppstg_f_reg_1331_pp0_it15;
ap_reg_ppstg_f_reg_1331_pp0_it17 <= ap_reg_ppstg_f_reg_1331_pp0_it16;
ap_reg_ppstg_f_reg_1331_pp0_it18 <= ap_reg_ppstg_f_reg_1331_pp0_it17;
ap_reg_ppstg_f_reg_1331_pp0_it19 <= ap_reg_ppstg_f_reg_1331_pp0_it18;
ap_reg_ppstg_f_reg_1331_pp0_it20 <= ap_reg_ppstg_f_reg_1331_pp0_it19;
ap_reg_ppstg_f_reg_1331_pp0_it21 <= ap_reg_ppstg_f_reg_1331_pp0_it20;
ap_reg_ppstg_f_reg_1331_pp0_it22 <= ap_reg_ppstg_f_reg_1331_pp0_it21;
ap_reg_ppstg_f_reg_1331_pp0_it23 <= ap_reg_ppstg_f_reg_1331_pp0_it22;
ap_reg_ppstg_f_reg_1331_pp0_it24 <= ap_reg_ppstg_f_reg_1331_pp0_it23;
ap_reg_ppstg_g_reg_1359_pp0_it12 <= g_reg_1359;
ap_reg_ppstg_g_reg_1359_pp0_it13 <= ap_reg_ppstg_g_reg_1359_pp0_it12;
ap_reg_ppstg_g_reg_1359_pp0_it14 <= ap_reg_ppstg_g_reg_1359_pp0_it13;
ap_reg_ppstg_g_reg_1359_pp0_it15 <= ap_reg_ppstg_g_reg_1359_pp0_it14;
ap_reg_ppstg_g_reg_1359_pp0_it16 <= ap_reg_ppstg_g_reg_1359_pp0_it15;
ap_reg_ppstg_g_reg_1359_pp0_it17 <= ap_reg_ppstg_g_reg_1359_pp0_it16;
ap_reg_ppstg_g_reg_1359_pp0_it18 <= ap_reg_ppstg_g_reg_1359_pp0_it17;
ap_reg_ppstg_g_reg_1359_pp0_it19 <= ap_reg_ppstg_g_reg_1359_pp0_it18;
ap_reg_ppstg_g_reg_1359_pp0_it20 <= ap_reg_ppstg_g_reg_1359_pp0_it19;
ap_reg_ppstg_g_reg_1359_pp0_it21 <= ap_reg_ppstg_g_reg_1359_pp0_it20;
ap_reg_ppstg_g_reg_1359_pp0_it22 <= ap_reg_ppstg_g_reg_1359_pp0_it21;
ap_reg_ppstg_g_reg_1359_pp0_it23 <= ap_reg_ppstg_g_reg_1359_pp0_it22;
ap_reg_ppstg_g_reg_1359_pp0_it24 <= ap_reg_ppstg_g_reg_1359_pp0_it23;
ap_reg_ppstg_g_reg_1359_pp0_it25 <= ap_reg_ppstg_g_reg_1359_pp0_it24;
ap_reg_ppstg_g_reg_1359_pp0_it26 <= ap_reg_ppstg_g_reg_1359_pp0_it25;
ap_reg_ppstg_g_reg_1359_pp0_it27 <= ap_reg_ppstg_g_reg_1359_pp0_it26;
ap_reg_ppstg_g_reg_1359_pp0_it28 <= ap_reg_ppstg_g_reg_1359_pp0_it27;
ap_reg_ppstg_g_reg_1359_pp0_it29 <= ap_reg_ppstg_g_reg_1359_pp0_it28;
ap_reg_ppstg_g_reg_1359_pp0_it30 <= ap_reg_ppstg_g_reg_1359_pp0_it29;
ap_reg_ppstg_g_reg_1359_pp0_it31 <= ap_reg_ppstg_g_reg_1359_pp0_it30;
ap_reg_ppstg_g_reg_1359_pp0_it32 <= ap_reg_ppstg_g_reg_1359_pp0_it31;
ap_reg_ppstg_g_reg_1359_pp0_it33 <= ap_reg_ppstg_g_reg_1359_pp0_it32;
ap_reg_ppstg_h_reg_1366_pp0_it12 <= h_reg_1366;
ap_reg_ppstg_h_reg_1366_pp0_it13 <= ap_reg_ppstg_h_reg_1366_pp0_it12;
ap_reg_ppstg_h_reg_1366_pp0_it14 <= ap_reg_ppstg_h_reg_1366_pp0_it13;
ap_reg_ppstg_h_reg_1366_pp0_it15 <= ap_reg_ppstg_h_reg_1366_pp0_it14;
ap_reg_ppstg_h_reg_1366_pp0_it16 <= ap_reg_ppstg_h_reg_1366_pp0_it15;
ap_reg_ppstg_h_reg_1366_pp0_it17 <= ap_reg_ppstg_h_reg_1366_pp0_it16;
ap_reg_ppstg_h_reg_1366_pp0_it18 <= ap_reg_ppstg_h_reg_1366_pp0_it17;
ap_reg_ppstg_h_reg_1366_pp0_it19 <= ap_reg_ppstg_h_reg_1366_pp0_it18;
ap_reg_ppstg_h_reg_1366_pp0_it20 <= ap_reg_ppstg_h_reg_1366_pp0_it19;
ap_reg_ppstg_h_reg_1366_pp0_it21 <= ap_reg_ppstg_h_reg_1366_pp0_it20;
ap_reg_ppstg_h_reg_1366_pp0_it22 <= ap_reg_ppstg_h_reg_1366_pp0_it21;
ap_reg_ppstg_h_reg_1366_pp0_it23 <= ap_reg_ppstg_h_reg_1366_pp0_it22;
ap_reg_ppstg_h_reg_1366_pp0_it24 <= ap_reg_ppstg_h_reg_1366_pp0_it23;
ap_reg_ppstg_i_1_reg_1373_pp0_it12 <= i_1_reg_1373;
ap_reg_ppstg_i_1_reg_1373_pp0_it13 <= ap_reg_ppstg_i_1_reg_1373_pp0_it12;
ap_reg_ppstg_i_1_reg_1373_pp0_it14 <= ap_reg_ppstg_i_1_reg_1373_pp0_it13;
ap_reg_ppstg_i_1_reg_1373_pp0_it15 <= ap_reg_ppstg_i_1_reg_1373_pp0_it14;
ap_reg_ppstg_i_1_reg_1373_pp0_it16 <= ap_reg_ppstg_i_1_reg_1373_pp0_it15;
ap_reg_ppstg_i_1_reg_1373_pp0_it17 <= ap_reg_ppstg_i_1_reg_1373_pp0_it16;
ap_reg_ppstg_i_1_reg_1373_pp0_it18 <= ap_reg_ppstg_i_1_reg_1373_pp0_it17;
ap_reg_ppstg_i_1_reg_1373_pp0_it19 <= ap_reg_ppstg_i_1_reg_1373_pp0_it18;
ap_reg_ppstg_i_1_reg_1373_pp0_it20 <= ap_reg_ppstg_i_1_reg_1373_pp0_it19;
ap_reg_ppstg_i_1_reg_1373_pp0_it21 <= ap_reg_ppstg_i_1_reg_1373_pp0_it20;
ap_reg_ppstg_i_1_reg_1373_pp0_it22 <= ap_reg_ppstg_i_1_reg_1373_pp0_it21;
ap_reg_ppstg_i_1_reg_1373_pp0_it23 <= ap_reg_ppstg_i_1_reg_1373_pp0_it22;
ap_reg_ppstg_i_1_reg_1373_pp0_it24 <= ap_reg_ppstg_i_1_reg_1373_pp0_it23;
ap_reg_ppstg_j_reg_1338_pp0_it11 <= j_reg_1338;
ap_reg_ppstg_j_reg_1338_pp0_it12 <= ap_reg_ppstg_j_reg_1338_pp0_it11;
ap_reg_ppstg_j_reg_1338_pp0_it13 <= ap_reg_ppstg_j_reg_1338_pp0_it12;
ap_reg_ppstg_j_reg_1338_pp0_it14 <= ap_reg_ppstg_j_reg_1338_pp0_it13;
ap_reg_ppstg_j_reg_1338_pp0_it15 <= ap_reg_ppstg_j_reg_1338_pp0_it14;
ap_reg_ppstg_j_reg_1338_pp0_it16 <= ap_reg_ppstg_j_reg_1338_pp0_it15;
ap_reg_ppstg_j_reg_1338_pp0_it17 <= ap_reg_ppstg_j_reg_1338_pp0_it16;
ap_reg_ppstg_j_reg_1338_pp0_it18 <= ap_reg_ppstg_j_reg_1338_pp0_it17;
ap_reg_ppstg_j_reg_1338_pp0_it19 <= ap_reg_ppstg_j_reg_1338_pp0_it18;
ap_reg_ppstg_j_reg_1338_pp0_it20 <= ap_reg_ppstg_j_reg_1338_pp0_it19;
ap_reg_ppstg_j_reg_1338_pp0_it21 <= ap_reg_ppstg_j_reg_1338_pp0_it20;
ap_reg_ppstg_j_reg_1338_pp0_it22 <= ap_reg_ppstg_j_reg_1338_pp0_it21;
ap_reg_ppstg_j_reg_1338_pp0_it23 <= ap_reg_ppstg_j_reg_1338_pp0_it22;
ap_reg_ppstg_j_reg_1338_pp0_it24 <= ap_reg_ppstg_j_reg_1338_pp0_it23;
ap_reg_ppstg_k_reg_1345_pp0_it11 <= k_reg_1345;
ap_reg_ppstg_k_reg_1345_pp0_it12 <= ap_reg_ppstg_k_reg_1345_pp0_it11;
ap_reg_ppstg_k_reg_1345_pp0_it13 <= ap_reg_ppstg_k_reg_1345_pp0_it12;
ap_reg_ppstg_k_reg_1345_pp0_it14 <= ap_reg_ppstg_k_reg_1345_pp0_it13;
ap_reg_ppstg_k_reg_1345_pp0_it15 <= ap_reg_ppstg_k_reg_1345_pp0_it14;
ap_reg_ppstg_k_reg_1345_pp0_it16 <= ap_reg_ppstg_k_reg_1345_pp0_it15;
ap_reg_ppstg_k_reg_1345_pp0_it17 <= ap_reg_ppstg_k_reg_1345_pp0_it16;
ap_reg_ppstg_k_reg_1345_pp0_it18 <= ap_reg_ppstg_k_reg_1345_pp0_it17;
ap_reg_ppstg_k_reg_1345_pp0_it19 <= ap_reg_ppstg_k_reg_1345_pp0_it18;
ap_reg_ppstg_k_reg_1345_pp0_it20 <= ap_reg_ppstg_k_reg_1345_pp0_it19;
ap_reg_ppstg_k_reg_1345_pp0_it21 <= ap_reg_ppstg_k_reg_1345_pp0_it20;
ap_reg_ppstg_k_reg_1345_pp0_it22 <= ap_reg_ppstg_k_reg_1345_pp0_it21;
ap_reg_ppstg_k_reg_1345_pp0_it23 <= ap_reg_ppstg_k_reg_1345_pp0_it22;
ap_reg_ppstg_k_reg_1345_pp0_it24 <= ap_reg_ppstg_k_reg_1345_pp0_it23;
ap_reg_ppstg_l_reg_1352_pp0_it11 <= l_reg_1352;
ap_reg_ppstg_l_reg_1352_pp0_it12 <= ap_reg_ppstg_l_reg_1352_pp0_it11;
ap_reg_ppstg_l_reg_1352_pp0_it13 <= ap_reg_ppstg_l_reg_1352_pp0_it12;
ap_reg_ppstg_l_reg_1352_pp0_it14 <= ap_reg_ppstg_l_reg_1352_pp0_it13;
ap_reg_ppstg_l_reg_1352_pp0_it15 <= ap_reg_ppstg_l_reg_1352_pp0_it14;
ap_reg_ppstg_l_reg_1352_pp0_it16 <= ap_reg_ppstg_l_reg_1352_pp0_it15;
ap_reg_ppstg_l_reg_1352_pp0_it17 <= ap_reg_ppstg_l_reg_1352_pp0_it16;
ap_reg_ppstg_l_reg_1352_pp0_it18 <= ap_reg_ppstg_l_reg_1352_pp0_it17;
ap_reg_ppstg_l_reg_1352_pp0_it19 <= ap_reg_ppstg_l_reg_1352_pp0_it18;
ap_reg_ppstg_l_reg_1352_pp0_it20 <= ap_reg_ppstg_l_reg_1352_pp0_it19;
ap_reg_ppstg_l_reg_1352_pp0_it21 <= ap_reg_ppstg_l_reg_1352_pp0_it20;
ap_reg_ppstg_l_reg_1352_pp0_it22 <= ap_reg_ppstg_l_reg_1352_pp0_it21;
ap_reg_ppstg_l_reg_1352_pp0_it23 <= ap_reg_ppstg_l_reg_1352_pp0_it22;
ap_reg_ppstg_l_reg_1352_pp0_it24 <= ap_reg_ppstg_l_reg_1352_pp0_it23;
ap_reg_ppstg_l_reg_1352_pp0_it25 <= ap_reg_ppstg_l_reg_1352_pp0_it24;
ap_reg_ppstg_l_reg_1352_pp0_it26 <= ap_reg_ppstg_l_reg_1352_pp0_it25;
ap_reg_ppstg_l_reg_1352_pp0_it27 <= ap_reg_ppstg_l_reg_1352_pp0_it26;
ap_reg_ppstg_l_reg_1352_pp0_it28 <= ap_reg_ppstg_l_reg_1352_pp0_it27;
ap_reg_ppstg_l_reg_1352_pp0_it29 <= ap_reg_ppstg_l_reg_1352_pp0_it28;
ap_reg_ppstg_l_reg_1352_pp0_it30 <= ap_reg_ppstg_l_reg_1352_pp0_it29;
ap_reg_ppstg_l_reg_1352_pp0_it31 <= ap_reg_ppstg_l_reg_1352_pp0_it30;
ap_reg_ppstg_l_reg_1352_pp0_it32 <= ap_reg_ppstg_l_reg_1352_pp0_it31;
ap_reg_ppstg_l_reg_1352_pp0_it33 <= ap_reg_ppstg_l_reg_1352_pp0_it32;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it10 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it9;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it2 <= rdx_assign_new_reg_1200;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it3 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it2;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it4 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it3;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it5 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it4;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it6 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it5;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it7 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it6;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it8 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it7;
ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it9 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it8;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it10 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it9;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it2 <= rdy_assign_new_reg_1205;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it3 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it2;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it4 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it3;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it5 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it4;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it6 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it5;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it7 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it6;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it8 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it7;
ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it9 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it8;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it10 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it9;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it2 <= rdz_assign_new_reg_1210;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it3 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it2;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it4 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it3;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it5 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it4;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it6 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it5;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it7 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it6;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it8 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it7;
ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it9 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it8;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it48 <= tmp_25_i_reg_1561;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it49 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it48;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it50 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it49;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it51 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it50;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it52 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it51;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it53 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it52;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it54 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it53;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it55 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it54;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it56 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it55;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it57 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it56;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it58 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it57;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it59 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it58;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it60 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it59;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it61 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it60;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it62 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it61;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it63 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it62;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it64 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it63;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it65 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it64;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it66 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it65;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it67 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it66;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it68 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it67;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it69 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it68;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it70 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it69;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it71 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it70;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it72 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it71;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it73 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it72;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it74 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it73;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it75 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it74;
ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it76 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it48 <= tmp_31_i_reg_1566;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it49 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it48;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it50 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it49;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it51 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it50;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it52 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it51;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it53 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it52;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it54 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it53;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it55 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it54;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it56 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it55;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it57 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it56;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it58 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it57;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it59 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it58;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it60 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it59;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it61 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it60;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it62 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it61;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it63 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it62;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it64 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it63;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it65 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it64;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it66 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it65;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it67 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it66;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it68 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it67;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it69 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it68;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it70 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it69;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it71 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it70;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it72 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it71;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it73 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it72;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it74 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it73;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it75 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it74;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it76 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it77 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it76;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it48 <= tmp_36_i_reg_1571;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it49 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it48;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it50 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it49;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it51 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it50;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it52 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it51;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it53 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it52;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it54 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it53;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it55 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it54;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it56 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it55;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it57 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it56;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it58 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it57;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it59 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it58;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it60 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it59;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it61 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it60;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it62 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it61;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it63 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it62;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it64 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it63;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it65 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it64;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it66 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it65;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it67 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it66;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it68 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it67;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it69 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it68;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it70 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it69;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it71 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it70;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it72 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it71;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it73 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it72;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it74 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it73;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it75 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it74;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it76 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it75;
ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it77 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it76;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30)) then
ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it1 <= data_array_addr_2_reg_1144;
ap_reg_ppstg_exitcond2_reg_1135_pp0_it1 <= exitcond2_reg_1135;
exitcond2_reg_1135 <= exitcond2_fu_791_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it81 = ap_const_lv1_0)) then
beta_addr_1174175_part_set_reg_1593 <= beta_addr_1174175_part_set_fu_1054_p5;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (exitcond2_fu_791_p2 = ap_const_lv1_0))) then
data_array_addr_2_reg_1144 <= tmp_s_fu_803_p1(1 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (exitcond2_reg_1135 = ap_const_lv1_0))) then
data_array_load_2_reg_1150 <= data_array_q0;
rdx_assign_new_reg_1200 <= data_array_q0(319 downto 288);
rdy_assign_new_reg_1205 <= data_array_q0(351 downto 320);
rdz_assign_new_reg_1210 <= data_array_q0(383 downto 352);
rex_assign_new_reg_1215 <= data_array_q0(415 downto 384);
rey_assign_new_reg_1220 <= data_array_q0(447 downto 416);
rez_assign_new_reg_1225 <= data_array_q0(479 downto 448);
tmp_3_reg_1155 <= tmp_3_fu_808_p1;
v0y_assign_new_reg_1160 <= data_array_q0(63 downto 32);
v0z_assign_new_reg_1165 <= data_array_q0(95 downto 64);
v1x_assign_new_reg_1170 <= data_array_q0(127 downto 96);
v1y_assign_new_reg_1175 <= data_array_q0(159 downto 128);
v1z_assign_new_reg_1180 <= data_array_q0(191 downto 160);
v2x_assign_new_reg_1185 <= data_array_q0(223 downto 192);
v2y_assign_new_reg_1190 <= data_array_q0(255 downto 224);
v2z_assign_new_reg_1195 <= data_array_q0(287 downto 256);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it10 = ap_const_lv1_0)) then
g_reg_1359 <= g_fu_1006_p1;
h_reg_1366 <= h_fu_1010_p1;
i_1_reg_1373 <= i_1_fu_1014_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it76 = ap_const_lv1_0)) then
im_reg_1576 <= grp_fu_450_p2;
tmp_61_neg_i_reg_1583 <= tmp_61_neg_i_fu_1022_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29))) then
ins_dest_V_val_reg_1130 <= ins_TDEST;
ins_id_V_val_reg_1125 <= ins_TID;
ins_keep_V_val_reg_1105 <= ins_TKEEP;
ins_last_V_val_reg_1120 <= ins_TLAST;
ins_strb_V_val_reg_1110 <= ins_TSTRB;
ins_user_V_val_reg_1115 <= ins_TUSER;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it46 = ap_const_lv1_0)) then
m_reg_1556 <= grp_fu_326_p2;
tmp_25_i_reg_1561 <= grp_fu_330_p2;
tmp_31_i_reg_1566 <= grp_fu_334_p2;
tmp_36_i_reg_1571 <= grp_fu_338_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ins_TVALID = ap_const_logic_0))) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)))) then
reg_489 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)))) then
reg_493 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)))) then
reg_497 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)))) then
reg_501 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)))) then
reg_505 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)))) then
reg_509 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)))) then
reg_513 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)))) then
reg_517 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)))) then
reg_521 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)))) then
reg_525 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)))) then
reg_529 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)))) then
reg_533 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)))) then
reg_537 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)))) then
reg_541 <= ins_TDATA;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) and not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35)))) then
reg_545 <= data_array_q1(543 downto 512);
reg_549 <= data_array_q1(575 downto 544);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it32 = ap_const_lv1_0)) then
tmp_10_i_reg_1504 <= grp_fu_302_p2;
tmp_23_i_reg_1510 <= grp_fu_306_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it37 = ap_const_lv1_0)) then
tmp_11_i_reg_1521 <= grp_fu_422_p2;
tmp_20_i_reg_1526 <= grp_fu_314_p2;
tmp_24_i_reg_1531 <= grp_fu_426_p2;
tmp_29_i_reg_1536 <= grp_fu_318_p2;
tmp_30_i_reg_1541 <= grp_fu_430_p2;
tmp_34_i_reg_1546 <= grp_fu_322_p2;
tmp_35_i_reg_1551 <= grp_fu_434_p2;
tmp_7_i_reg_1516 <= grp_fu_310_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it14 = ap_const_lv1_0)) then
tmp_12_i_reg_1400 <= grp_fu_358_p2;
tmp_13_i_reg_1405 <= grp_fu_362_p2;
tmp_16_i_reg_1410 <= grp_fu_366_p2;
tmp_17_i_reg_1415 <= grp_fu_370_p2;
tmp_3_i_reg_1390 <= grp_fu_350_p2;
tmp_4_i_reg_1395 <= grp_fu_354_p2;
tmp_i_41_reg_1385 <= grp_fu_346_p2;
tmp_i_reg_1380 <= grp_fu_342_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it23 = ap_const_lv1_0)) then
tmp_14_i_reg_1442 <= grp_fu_294_p2;
tmp_18_i_reg_1448 <= grp_fu_298_p2;
tmp_1_i_reg_1420 <= grp_fu_286_p2;
tmp_21_i_reg_1454 <= grp_fu_382_p2;
tmp_22_i_reg_1459 <= grp_fu_386_p2;
tmp_5_i_reg_1426 <= grp_fu_290_p2;
tmp_8_i_reg_1432 <= grp_fu_374_p2;
tmp_9_i_reg_1437 <= grp_fu_378_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond2_reg_1135_pp0_it28 = ap_const_lv1_0)) then
tmp_15_i_reg_1474 <= grp_fu_398_p2;
tmp_19_i_reg_1479 <= grp_fu_402_p2;
tmp_27_i_reg_1484 <= grp_fu_406_p2;
tmp_28_i_reg_1489 <= grp_fu_410_p2;
tmp_2_i_reg_1464 <= grp_fu_390_p2;
tmp_32_i_reg_1494 <= grp_fu_414_p2;
tmp_33_i_reg_1499 <= grp_fu_418_p2;
tmp_6_i_reg_1469 <= grp_fu_394_p2;
end if;
end if;
end process;
data_array_addr_reg_1095(0) <= '0';
data_array_addr_1_reg_1100(0) <= '1';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ins_TVALID, ap_CS_fsm, ap_sig_ioackin_outs_TREADY, exitcond2_fu_791_p2, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it82, ap_reg_ppiten_pp0_it83)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st7_fsm_6;
else
ap_NS_fsm <= ap_ST_st6_fsm_5;
end if;
when ap_ST_st7_fsm_6 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st8_fsm_7 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st10_fsm_9;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st10_fsm_9 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st11_fsm_10;
else
ap_NS_fsm <= ap_ST_st10_fsm_9;
end if;
when ap_ST_st11_fsm_10 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
else
ap_NS_fsm <= ap_ST_st11_fsm_10;
end if;
when ap_ST_st12_fsm_11 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st13_fsm_12;
else
ap_NS_fsm <= ap_ST_st12_fsm_11;
end if;
when ap_ST_st13_fsm_12 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st14_fsm_13;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st14_fsm_13 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st15_fsm_14;
else
ap_NS_fsm <= ap_ST_st14_fsm_13;
end if;
when ap_ST_st15_fsm_14 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st16_fsm_15;
else
ap_NS_fsm <= ap_ST_st15_fsm_14;
end if;
when ap_ST_st16_fsm_15 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st17_fsm_16;
else
ap_NS_fsm <= ap_ST_st16_fsm_15;
end if;
when ap_ST_st17_fsm_16 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st17_fsm_16;
end if;
when ap_ST_st18_fsm_17 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st19_fsm_18;
else
ap_NS_fsm <= ap_ST_st18_fsm_17;
end if;
when ap_ST_st19_fsm_18 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st19_fsm_18;
end if;
when ap_ST_st20_fsm_19 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st21_fsm_20;
else
ap_NS_fsm <= ap_ST_st20_fsm_19;
end if;
when ap_ST_st21_fsm_20 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st22_fsm_21;
else
ap_NS_fsm <= ap_ST_st21_fsm_20;
end if;
when ap_ST_st22_fsm_21 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st23_fsm_22;
else
ap_NS_fsm <= ap_ST_st22_fsm_21;
end if;
when ap_ST_st23_fsm_22 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st23_fsm_22;
end if;
when ap_ST_st24_fsm_23 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st25_fsm_24;
else
ap_NS_fsm <= ap_ST_st24_fsm_23;
end if;
when ap_ST_st25_fsm_24 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st26_fsm_25;
else
ap_NS_fsm <= ap_ST_st25_fsm_24;
end if;
when ap_ST_st26_fsm_25 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st27_fsm_26;
else
ap_NS_fsm <= ap_ST_st26_fsm_25;
end if;
when ap_ST_st27_fsm_26 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st28_fsm_27;
else
ap_NS_fsm <= ap_ST_st27_fsm_26;
end if;
when ap_ST_st28_fsm_27 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st29_fsm_28;
else
ap_NS_fsm <= ap_ST_st28_fsm_27;
end if;
when ap_ST_st29_fsm_28 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st30_fsm_29;
else
ap_NS_fsm <= ap_ST_st29_fsm_28;
end if;
when ap_ST_st30_fsm_29 =>
if (not((ins_TVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_30;
else
ap_NS_fsm <= ap_ST_st30_fsm_29;
end if;
when ap_ST_pp0_stg0_fsm_30 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it82)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((exitcond2_fu_791_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_30;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((exitcond2_fu_791_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) then
ap_NS_fsm <= ap_ST_st115_fsm_31;
else
ap_NS_fsm <= ap_ST_st115_fsm_31;
end if;
when ap_ST_st115_fsm_31 =>
ap_NS_fsm <= ap_ST_st116_fsm_32;
when ap_ST_st116_fsm_32 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st117_fsm_33;
else
ap_NS_fsm <= ap_ST_st116_fsm_32;
end if;
when ap_ST_st117_fsm_33 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st118_fsm_34;
else
ap_NS_fsm <= ap_ST_st117_fsm_33;
end if;
when ap_ST_st118_fsm_34 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st119_fsm_35;
else
ap_NS_fsm <= ap_ST_st118_fsm_34;
end if;
when ap_ST_st119_fsm_35 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st120_fsm_36;
else
ap_NS_fsm <= ap_ST_st119_fsm_35;
end if;
when ap_ST_st120_fsm_36 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st121_fsm_37;
else
ap_NS_fsm <= ap_ST_st120_fsm_36;
end if;
when ap_ST_st121_fsm_37 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st121_fsm_37;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_104 assign process. --
ap_sig_bdd_104_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_104 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_114 assign process. --
ap_sig_bdd_114_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_114 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_122 assign process. --
ap_sig_bdd_122_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_122 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_132 assign process. --
ap_sig_bdd_132_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_132 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_140 assign process. --
ap_sig_bdd_140_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_140 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_150 assign process. --
ap_sig_bdd_150_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_150 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_158 assign process. --
ap_sig_bdd_158_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19));
end process;
-- ap_sig_bdd_168 assign process. --
ap_sig_bdd_168_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_168 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_176 assign process. --
ap_sig_bdd_176_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_176 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20));
end process;
-- ap_sig_bdd_186 assign process. --
ap_sig_bdd_186_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_186 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_1866 assign process. --
ap_sig_bdd_1866_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1866 <= (ap_const_lv1_1 = ap_CS_fsm(33 downto 33));
end process;
-- ap_sig_bdd_1874 assign process. --
ap_sig_bdd_1874_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1874 <= (ap_const_lv1_1 = ap_CS_fsm(34 downto 34));
end process;
-- ap_sig_bdd_1883 assign process. --
ap_sig_bdd_1883_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1883 <= (ap_const_lv1_1 = ap_CS_fsm(36 downto 36));
end process;
-- ap_sig_bdd_1891 assign process. --
ap_sig_bdd_1891_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1891 <= (ap_const_lv1_1 = ap_CS_fsm(37 downto 37));
end process;
-- ap_sig_bdd_194 assign process. --
ap_sig_bdd_194_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_194 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21));
end process;
-- ap_sig_bdd_1948 assign process. --
ap_sig_bdd_1948_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1948 <= (ap_const_lv1_1 = ap_CS_fsm(31 downto 31));
end process;
-- ap_sig_bdd_204 assign process. --
ap_sig_bdd_204_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_204 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_212 assign process. --
ap_sig_bdd_212_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_212 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_222 assign process. --
ap_sig_bdd_222_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_222 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_240 assign process. --
ap_sig_bdd_240_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_240 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_248 assign process. --
ap_sig_bdd_248_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_248 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_258 assign process. --
ap_sig_bdd_258_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_258 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_266 assign process. --
ap_sig_bdd_266_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_266 <= (ap_const_lv1_1 = ap_CS_fsm(25 downto 25));
end process;
-- ap_sig_bdd_276 assign process. --
ap_sig_bdd_276_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_276 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_284 assign process. --
ap_sig_bdd_284_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_284 <= (ap_const_lv1_1 = ap_CS_fsm(26 downto 26));
end process;
-- ap_sig_bdd_294 assign process. --
ap_sig_bdd_294_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_294 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_302 assign process. --
ap_sig_bdd_302_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_302 <= (ap_const_lv1_1 = ap_CS_fsm(27 downto 27));
end process;
-- ap_sig_bdd_312 assign process. --
ap_sig_bdd_312_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_312 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_320 assign process. --
ap_sig_bdd_320_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_320 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_331 assign process. --
ap_sig_bdd_331_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_331 <= (ap_const_lv1_1 = ap_CS_fsm(32 downto 32));
end process;
-- ap_sig_bdd_342 assign process. --
ap_sig_bdd_342_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_342 <= (ap_const_lv1_1 = ap_CS_fsm(35 downto 35));
end process;
-- ap_sig_bdd_355 assign process. --
ap_sig_bdd_355_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_355 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_365 assign process. --
ap_sig_bdd_365_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_365 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_387 assign process. --
ap_sig_bdd_387_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_387 <= (ap_const_lv1_1 = ap_CS_fsm(30 downto 30));
end process;
-- ap_sig_bdd_75 assign process. --
ap_sig_bdd_75_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_75 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_86 assign process. --
ap_sig_bdd_86_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_86 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15));
end process;
-- ap_sig_bdd_96 assign process. --
ap_sig_bdd_96_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_96 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_30 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_30_assign_proc : process(ap_sig_bdd_387)
begin
if (ap_sig_bdd_387) then
ap_sig_cseq_ST_pp0_stg0_fsm_30 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_30 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_240)
begin
if (ap_sig_bdd_240) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st115_fsm_31 assign process. --
ap_sig_cseq_ST_st115_fsm_31_assign_proc : process(ap_sig_bdd_1948)
begin
if (ap_sig_bdd_1948) then
ap_sig_cseq_ST_st115_fsm_31 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st115_fsm_31 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st116_fsm_32 assign process. --
ap_sig_cseq_ST_st116_fsm_32_assign_proc : process(ap_sig_bdd_331)
begin
if (ap_sig_bdd_331) then
ap_sig_cseq_ST_st116_fsm_32 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st116_fsm_32 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st117_fsm_33 assign process. --
ap_sig_cseq_ST_st117_fsm_33_assign_proc : process(ap_sig_bdd_1866)
begin
if (ap_sig_bdd_1866) then
ap_sig_cseq_ST_st117_fsm_33 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_33 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_34 assign process. --
ap_sig_cseq_ST_st118_fsm_34_assign_proc : process(ap_sig_bdd_1874)
begin
if (ap_sig_bdd_1874) then
ap_sig_cseq_ST_st118_fsm_34 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_34 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st119_fsm_35 assign process. --
ap_sig_cseq_ST_st119_fsm_35_assign_proc : process(ap_sig_bdd_342)
begin
if (ap_sig_bdd_342) then
ap_sig_cseq_ST_st119_fsm_35 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st119_fsm_35 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_258)
begin
if (ap_sig_bdd_258) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st120_fsm_36 assign process. --
ap_sig_cseq_ST_st120_fsm_36_assign_proc : process(ap_sig_bdd_1883)
begin
if (ap_sig_bdd_1883) then
ap_sig_cseq_ST_st120_fsm_36 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st120_fsm_36 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st121_fsm_37 assign process. --
ap_sig_cseq_ST_st121_fsm_37_assign_proc : process(ap_sig_bdd_1891)
begin
if (ap_sig_bdd_1891) then
ap_sig_cseq_ST_st121_fsm_37 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st121_fsm_37 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_276)
begin
if (ap_sig_bdd_276) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_294)
begin
if (ap_sig_bdd_294) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_312)
begin
if (ap_sig_bdd_312) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_355)
begin
if (ap_sig_bdd_355) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st16_fsm_15 assign process. --
ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_bdd_86)
begin
if (ap_sig_bdd_86) then
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_104)
begin
if (ap_sig_bdd_104) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_122)
begin
if (ap_sig_bdd_122) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_140)
begin
if (ap_sig_bdd_140) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_75)
begin
if (ap_sig_bdd_75) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st20_fsm_19 assign process. --
ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) then
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st21_fsm_20 assign process. --
ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_bdd_176)
begin
if (ap_sig_bdd_176) then
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st22_fsm_21 assign process. --
ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_bdd_194)
begin
if (ap_sig_bdd_194) then
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_212)
begin
if (ap_sig_bdd_212) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_248)
begin
if (ap_sig_bdd_248) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st26_fsm_25 assign process. --
ap_sig_cseq_ST_st26_fsm_25_assign_proc : process(ap_sig_bdd_266)
begin
if (ap_sig_bdd_266) then
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st26_fsm_25 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st27_fsm_26 assign process. --
ap_sig_cseq_ST_st27_fsm_26_assign_proc : process(ap_sig_bdd_284)
begin
if (ap_sig_bdd_284) then
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st27_fsm_26 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st28_fsm_27 assign process. --
ap_sig_cseq_ST_st28_fsm_27_assign_proc : process(ap_sig_bdd_302)
begin
if (ap_sig_bdd_302) then
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st28_fsm_27 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_320)
begin
if (ap_sig_bdd_320) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_96)
begin
if (ap_sig_bdd_96) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_365)
begin
if (ap_sig_bdd_365) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_114)
begin
if (ap_sig_bdd_114) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_132)
begin
if (ap_sig_bdd_132) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_150)
begin
if (ap_sig_bdd_150) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_168)
begin
if (ap_sig_bdd_168) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_186)
begin
if (ap_sig_bdd_186) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_204)
begin
if (ap_sig_bdd_204) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_222)
begin
if (ap_sig_bdd_222) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_outs_TREADY assign process. --
ap_sig_ioackin_outs_TREADY_assign_proc : process(outs_TREADY, ap_reg_ioackin_outs_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) then
ap_sig_ioackin_outs_TREADY <= outs_TREADY;
else
ap_sig_ioackin_outs_TREADY <= ap_const_logic_1;
end if;
end process;
beta_addr_1174175_part_set_fu_1054_p5 <= (tmp_2_fu_1044_p4 & ap_reg_ppstg_data_array_load_2_reg_1150_pp0_it81(479 downto 0));
beta_load_fu_1075_p1 <= reg_549;
beta_load_s_fu_1090_p1 <= reg_549;
beta_write_assign_toint_fu_1040_p1 <= grp_fu_446_p2;
data_array_addr_1_gep_fu_220_p3 <= ap_const_lv64_1(1 - 1 downto 0);
data_array_addr_gep_fu_208_p3 <= ap_const_lv64_0(1 - 1 downto 0);
-- data_array_address0 assign process. --
data_array_address0_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_pp0_stg0_fsm_30, ap_reg_ppiten_pp0_it0, tmp_s_fu_803_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
data_array_address0 <= ap_const_lv64_1(1 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
data_array_address0 <= ap_const_lv64_0(1 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
data_array_address0 <= tmp_s_fu_803_p1(1 - 1 downto 0);
else
data_array_address0 <= "X";
end if;
end process;
-- data_array_address1 assign process. --
data_array_address1_assign_proc : process(data_array_addr_reg_1095, data_array_addr_1_reg_1100, ap_reg_ppiten_pp0_it83, ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it82, ap_sig_cseq_ST_st118_fsm_34, ap_sig_cseq_ST_st115_fsm_31)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it83)) then
data_array_address1 <= ap_reg_ppstg_data_array_addr_2_reg_1144_pp0_it82;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34)) then
data_array_address1 <= data_array_addr_1_reg_1100;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_31)) then
data_array_address1 <= data_array_addr_reg_1095;
else
data_array_address1 <= "X";
end if;
end process;
-- data_array_ce0 assign process. --
data_array_ce0_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_pp0_stg0_fsm_30, ap_reg_ppiten_pp0_it0)
begin
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_30) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
data_array_ce0 <= ap_const_logic_1;
else
data_array_ce0 <= ap_const_logic_0;
end if;
end process;
-- data_array_ce1 assign process. --
data_array_ce1_assign_proc : process(ap_sig_ioackin_outs_TREADY, ap_reg_ppiten_pp0_it83, ap_sig_cseq_ST_st118_fsm_34, ap_sig_cseq_ST_st115_fsm_31)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) or (not((ap_const_logic_0 = ap_sig_ioackin_outs_TREADY)) and (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34)) or (ap_const_logic_1 = ap_sig_cseq_ST_st115_fsm_31))) then
data_array_ce1 <= ap_const_logic_1;
else
data_array_ce1 <= ap_const_logic_0;
end if;
end process;
-- data_array_d0 assign process. --
data_array_d0_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29, rez_addr149150_part_set_fu_647_p5, rez_addr_1146147_part_set_fu_778_p5)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
data_array_d0 <= rez_addr_1146147_part_set_fu_778_p5;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
data_array_d0 <= rez_addr149150_part_set_fu_647_p5;
else
data_array_d0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
data_array_d1 <= beta_addr_1174175_part_set_reg_1593;
-- data_array_we0 assign process. --
data_array_we0_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29)
begin
if (((not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)))) then
data_array_we0 <= ap_const_logic_1;
else
data_array_we0 <= ap_const_logic_0;
end if;
end process;
-- data_array_we1 assign process. --
data_array_we1_assign_proc : process(ap_reg_ppiten_pp0_it83, ap_reg_ppstg_exitcond2_reg_1135_pp0_it82)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it83) and (ap_reg_ppstg_exitcond2_reg_1135_pp0_it82 = ap_const_lv1_0)))) then
data_array_we1 <= ap_const_logic_1;
else
data_array_we1 <= ap_const_logic_0;
end if;
end process;
exitcond2_fu_791_p2 <= "1" when (i1_reg_238 = ap_const_lv2_2) else "0";
g_fu_1006_p1 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it10;
gamma_load_fu_1070_p1 <= reg_545;
gamma_load_s_fu_1085_p1 <= reg_545;
gamma_write_assign_toint_fu_1036_p1 <= grp_fu_442_p2;
grp_fu_250_ce <= ap_const_logic_1;
grp_fu_250_p0 <= v0x_assign4_fu_952_p1;
grp_fu_250_p1 <= v1x_assign_new_reg_1170;
grp_fu_254_ce <= ap_const_logic_1;
grp_fu_254_p0 <= v0y_assign_fu_958_p1;
grp_fu_254_p1 <= v1y_assign_new_reg_1175;
grp_fu_258_ce <= ap_const_logic_1;
grp_fu_258_p0 <= v0z_assign_fu_964_p1;
grp_fu_258_p1 <= v1z_assign_new_reg_1180;
grp_fu_262_ce <= ap_const_logic_1;
grp_fu_262_p0 <= v0x_assign4_fu_952_p1;
grp_fu_262_p1 <= v2x_assign_new_reg_1185;
grp_fu_266_ce <= ap_const_logic_1;
grp_fu_266_p0 <= v0y_assign_fu_958_p1;
grp_fu_266_p1 <= v2y_assign_new_reg_1190;
grp_fu_270_ce <= ap_const_logic_1;
grp_fu_270_p0 <= v0z_assign_fu_964_p1;
grp_fu_270_p1 <= v2z_assign_new_reg_1195;
grp_fu_274_ce <= ap_const_logic_1;
grp_fu_274_p0 <= v0x_assign4_fu_952_p1;
grp_fu_274_p1 <= rex_assign_new_reg_1215;
grp_fu_278_ce <= ap_const_logic_1;
grp_fu_278_p0 <= v0y_assign_fu_958_p1;
grp_fu_278_p1 <= rey_assign_new_reg_1220;
grp_fu_282_ce <= ap_const_logic_1;
grp_fu_282_p0 <= v0z_assign_fu_964_p1;
grp_fu_282_p1 <= rez_assign_new_reg_1225;
grp_fu_286_ce <= ap_const_logic_1;
grp_fu_286_p0 <= tmp_i_reg_1380;
grp_fu_286_p1 <= tmp_i_41_reg_1385;
grp_fu_290_ce <= ap_const_logic_1;
grp_fu_290_p0 <= tmp_3_i_reg_1390;
grp_fu_290_p1 <= tmp_4_i_reg_1395;
grp_fu_294_ce <= ap_const_logic_1;
grp_fu_294_p0 <= tmp_12_i_reg_1400;
grp_fu_294_p1 <= tmp_13_i_reg_1405;
grp_fu_298_ce <= ap_const_logic_1;
grp_fu_298_p0 <= tmp_16_i_reg_1410;
grp_fu_298_p1 <= tmp_17_i_reg_1415;
grp_fu_302_ce <= ap_const_logic_1;
grp_fu_302_p0 <= tmp_8_i_reg_1432;
grp_fu_302_p1 <= tmp_9_i_reg_1437;
grp_fu_306_ce <= ap_const_logic_1;
grp_fu_306_p0 <= tmp_21_i_reg_1454;
grp_fu_306_p1 <= tmp_22_i_reg_1459;
grp_fu_310_ce <= ap_const_logic_1;
grp_fu_310_p0 <= tmp_2_i_reg_1464;
grp_fu_310_p1 <= tmp_6_i_reg_1469;
grp_fu_314_ce <= ap_const_logic_1;
grp_fu_314_p0 <= tmp_15_i_reg_1474;
grp_fu_314_p1 <= tmp_19_i_reg_1479;
grp_fu_318_ce <= ap_const_logic_1;
grp_fu_318_p0 <= tmp_27_i_reg_1484;
grp_fu_318_p1 <= tmp_28_i_reg_1489;
grp_fu_322_ce <= ap_const_logic_1;
grp_fu_322_p0 <= tmp_32_i_reg_1494;
grp_fu_322_p1 <= tmp_33_i_reg_1499;
grp_fu_326_ce <= ap_const_logic_1;
grp_fu_326_p0 <= tmp_7_i_reg_1516;
grp_fu_326_p1 <= tmp_11_i_reg_1521;
grp_fu_330_ce <= ap_const_logic_1;
grp_fu_330_p0 <= tmp_20_i_reg_1526;
grp_fu_330_p1 <= tmp_24_i_reg_1531;
grp_fu_334_ce <= ap_const_logic_1;
grp_fu_334_p0 <= tmp_29_i_reg_1536;
grp_fu_334_p1 <= tmp_30_i_reg_1541;
grp_fu_338_ce <= ap_const_logic_1;
grp_fu_338_p0 <= tmp_34_i_reg_1546;
grp_fu_338_p1 <= tmp_35_i_reg_1551;
grp_fu_342_ce <= ap_const_logic_1;
grp_fu_342_p0 <= e_reg_1324;
grp_fu_342_p1 <= i_1_fu_1014_p1;
grp_fu_346_ce <= ap_const_logic_1;
grp_fu_346_p0 <= f_reg_1331;
grp_fu_346_p1 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it10;
grp_fu_350_ce <= ap_const_logic_1;
grp_fu_350_p0 <= f_reg_1331;
grp_fu_350_p1 <= ap_reg_ppstg_rdx_assign_new_reg_1200_pp0_it10;
grp_fu_354_ce <= ap_const_logic_1;
grp_fu_354_p0 <= d_reg_1317;
grp_fu_354_p1 <= i_1_fu_1014_p1;
grp_fu_358_ce <= ap_const_logic_1;
grp_fu_358_p0 <= a_reg_1296;
grp_fu_358_p1 <= k_reg_1345;
grp_fu_362_ce <= ap_const_logic_1;
grp_fu_362_p0 <= j_reg_1338;
grp_fu_362_p1 <= b_reg_1303;
grp_fu_366_ce <= ap_const_logic_1;
grp_fu_366_p0 <= j_reg_1338;
grp_fu_366_p1 <= c_reg_1310;
grp_fu_370_ce <= ap_const_logic_1;
grp_fu_370_p0 <= a_reg_1296;
grp_fu_370_p1 <= l_reg_1352;
grp_fu_374_ce <= ap_const_logic_1;
grp_fu_374_p0 <= ap_reg_ppstg_d_reg_1317_pp0_it19;
grp_fu_374_p1 <= ap_reg_ppstg_h_reg_1366_pp0_it19;
grp_fu_378_ce <= ap_const_logic_1;
grp_fu_378_p0 <= ap_reg_ppstg_e_reg_1324_pp0_it19;
grp_fu_378_p1 <= ap_reg_ppstg_g_reg_1359_pp0_it19;
grp_fu_382_ce <= ap_const_logic_1;
grp_fu_382_p0 <= ap_reg_ppstg_b_reg_1303_pp0_it19;
grp_fu_382_p1 <= ap_reg_ppstg_l_reg_1352_pp0_it19;
grp_fu_386_ce <= ap_const_logic_1;
grp_fu_386_p0 <= ap_reg_ppstg_k_reg_1345_pp0_it19;
grp_fu_386_p1 <= ap_reg_ppstg_c_reg_1310_pp0_it19;
grp_fu_390_ce <= ap_const_logic_1;
grp_fu_390_p0 <= ap_reg_ppstg_a_reg_1296_pp0_it24;
grp_fu_390_p1 <= tmp_1_i_reg_1420;
grp_fu_394_ce <= ap_const_logic_1;
grp_fu_394_p0 <= ap_reg_ppstg_b_reg_1303_pp0_it24;
grp_fu_394_p1 <= tmp_5_i_reg_1426;
grp_fu_398_ce <= ap_const_logic_1;
grp_fu_398_p0 <= ap_reg_ppstg_f_reg_1331_pp0_it24;
grp_fu_398_p1 <= tmp_14_i_reg_1442;
grp_fu_402_ce <= ap_const_logic_1;
grp_fu_402_p0 <= ap_reg_ppstg_e_reg_1324_pp0_it24;
grp_fu_402_p1 <= tmp_18_i_reg_1448;
grp_fu_406_ce <= ap_const_logic_1;
grp_fu_406_p0 <= tmp_14_i_reg_1442;
grp_fu_406_p1 <= ap_reg_ppstg_i_1_reg_1373_pp0_it24;
grp_fu_410_ce <= ap_const_logic_1;
grp_fu_410_p0 <= tmp_18_i_reg_1448;
grp_fu_410_p1 <= ap_reg_ppstg_h_reg_1366_pp0_it24;
grp_fu_414_ce <= ap_const_logic_1;
grp_fu_414_p0 <= ap_reg_ppstg_j_reg_1338_pp0_it24;
grp_fu_414_p1 <= tmp_1_i_reg_1420;
grp_fu_418_ce <= ap_const_logic_1;
grp_fu_418_p0 <= ap_reg_ppstg_k_reg_1345_pp0_it24;
grp_fu_418_p1 <= tmp_5_i_reg_1426;
grp_fu_422_ce <= ap_const_logic_1;
grp_fu_422_p0 <= ap_reg_ppstg_c_reg_1310_pp0_it33;
grp_fu_422_p1 <= tmp_10_i_reg_1504;
grp_fu_426_ce <= ap_const_logic_1;
grp_fu_426_p0 <= ap_reg_ppstg_d_reg_1317_pp0_it33;
grp_fu_426_p1 <= tmp_23_i_reg_1510;
grp_fu_430_ce <= ap_const_logic_1;
grp_fu_430_p0 <= tmp_23_i_reg_1510;
grp_fu_430_p1 <= ap_reg_ppstg_g_reg_1359_pp0_it33;
grp_fu_434_ce <= ap_const_logic_1;
grp_fu_434_p0 <= ap_reg_ppstg_l_reg_1352_pp0_it33;
grp_fu_434_p1 <= tmp_10_i_reg_1504;
grp_fu_438_ce <= ap_const_logic_1;
grp_fu_438_p0 <= tmp_61_neg_i_reg_1583;
grp_fu_438_p1 <= im_reg_1576;
grp_fu_442_ce <= ap_const_logic_1;
grp_fu_442_p0 <= ap_reg_ppstg_tmp_31_i_reg_1566_pp0_it77;
grp_fu_442_p1 <= im_reg_1576;
grp_fu_446_ce <= ap_const_logic_1;
grp_fu_446_p0 <= ap_reg_ppstg_tmp_36_i_reg_1571_pp0_it77;
grp_fu_446_p1 <= im_reg_1576;
grp_fu_450_ce <= ap_const_logic_1;
grp_fu_450_p0 <= ap_const_lv32_3F800000;
grp_fu_450_p1 <= m_reg_1556;
grp_fu_459_p4 <= data_array_q1(511 downto 480);
h_fu_1010_p1 <= ap_reg_ppstg_rdy_assign_new_reg_1205_pp0_it10;
i_1_fu_1014_p1 <= ap_reg_ppstg_rdz_assign_new_reg_1210_pp0_it10;
i_fu_797_p2 <= std_logic_vector(unsigned(i1_reg_238) + unsigned(ap_const_lv2_1));
-- ins_TREADY assign process. --
ins_TREADY_assign_proc : process(ins_TVALID, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st16_fsm_15, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st18_fsm_17, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st20_fsm_19, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st22_fsm_21, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st23_fsm_22, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st25_fsm_24, ap_sig_cseq_ST_st11_fsm_10, ap_sig_cseq_ST_st26_fsm_25, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st27_fsm_26, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st28_fsm_27, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st29_fsm_28, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st30_fsm_29)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ins_TVALID = ap_const_logic_0))) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st26_fsm_25)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st27_fsm_26)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st28_fsm_27)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) or (not((ins_TVALID = ap_const_logic_0)) and (ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)))) then
ins_TREADY <= ap_const_logic_1;
else
ins_TREADY <= ap_const_logic_0;
end if;
end process;
ins_data_tmp_load_10_toint_fu_593_p1 <= reg_529;
ins_data_tmp_load_11_toint_fu_597_p1 <= reg_533;
ins_data_tmp_load_12_toint_fu_601_p1 <= reg_537;
ins_data_tmp_load_13_toint_fu_605_p1 <= reg_541;
ins_data_tmp_load_14_toint_fu_609_p1 <= ins_TDATA;
ins_data_tmp_load_15_toint_fu_660_p1 <= reg_489;
ins_data_tmp_load_16_toint_fu_664_p1 <= reg_493;
ins_data_tmp_load_17_toint_fu_668_p1 <= reg_497;
ins_data_tmp_load_18_toint_fu_672_p1 <= reg_501;
ins_data_tmp_load_19_toint_fu_676_p1 <= reg_505;
ins_data_tmp_load_1_toint_fu_557_p1 <= reg_493;
ins_data_tmp_load_20_toint_fu_680_p1 <= reg_509;
ins_data_tmp_load_21_toint_fu_684_p1 <= reg_513;
ins_data_tmp_load_22_toint_fu_688_p1 <= reg_517;
ins_data_tmp_load_23_toint_fu_692_p1 <= reg_521;
ins_data_tmp_load_24_toint_fu_696_p1 <= reg_525;
ins_data_tmp_load_25_toint_fu_700_p1 <= reg_529;
ins_data_tmp_load_26_toint_fu_704_p1 <= reg_533;
ins_data_tmp_load_27_toint_fu_708_p1 <= reg_537;
ins_data_tmp_load_28_toint_fu_712_p1 <= reg_541;
ins_data_tmp_load_29_toint_fu_740_p1 <= ins_TDATA;
ins_data_tmp_load_2_toint_fu_561_p1 <= reg_497;
ins_data_tmp_load_3_toint_fu_565_p1 <= reg_501;
ins_data_tmp_load_4_toint_fu_569_p1 <= reg_505;
ins_data_tmp_load_5_toint_fu_573_p1 <= reg_509;
ins_data_tmp_load_6_toint_fu_577_p1 <= reg_513;
ins_data_tmp_load_7_toint_fu_581_p1 <= reg_517;
ins_data_tmp_load_8_toint_fu_585_p1 <= reg_521;
ins_data_tmp_load_9_toint_fu_589_p1 <= reg_525;
ins_data_tmp_load_toint_fu_553_p1 <= reg_489;
-- outs_TDATA assign process. --
outs_TDATA_assign_proc : process(ap_sig_cseq_ST_st116_fsm_32, ap_sig_cseq_ST_st119_fsm_35, t_load_fu_1065_p1, gamma_load_fu_1070_p1, ap_sig_cseq_ST_st117_fsm_33, beta_load_fu_1075_p1, ap_sig_cseq_ST_st118_fsm_34, t_load_s_fu_1080_p1, gamma_load_s_fu_1085_p1, ap_sig_cseq_ST_st120_fsm_36, beta_load_s_fu_1090_p1, ap_sig_cseq_ST_st121_fsm_37)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37)) then
outs_TDATA <= beta_load_s_fu_1090_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36)) then
outs_TDATA <= gamma_load_s_fu_1085_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35)) then
outs_TDATA <= t_load_s_fu_1080_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34)) then
outs_TDATA <= beta_load_fu_1075_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33)) then
outs_TDATA <= gamma_load_fu_1070_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32)) then
outs_TDATA <= t_load_fu_1065_p1;
else
outs_TDATA <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
outs_TDEST <= ins_dest_V_val_reg_1130;
outs_TID <= ins_id_V_val_reg_1125;
outs_TKEEP <= ins_keep_V_val_reg_1105;
-- outs_TLAST assign process. --
outs_TLAST_assign_proc : process(ap_sig_cseq_ST_st116_fsm_32, ap_sig_cseq_ST_st119_fsm_35, ins_last_V_val_reg_1120, ap_sig_cseq_ST_st117_fsm_33, ap_sig_cseq_ST_st118_fsm_34, ap_sig_cseq_ST_st120_fsm_36, ap_sig_cseq_ST_st121_fsm_37)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37)) then
outs_TLAST <= ins_last_V_val_reg_1120;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) or (ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34) or (ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36))) then
outs_TLAST <= ap_const_lv1_0;
else
outs_TLAST <= "X";
end if;
end process;
outs_TSTRB <= ins_strb_V_val_reg_1110;
outs_TUSER <= ins_user_V_val_reg_1115;
-- outs_TVALID assign process. --
outs_TVALID_assign_proc : process(ap_sig_cseq_ST_st116_fsm_32, ap_sig_cseq_ST_st119_fsm_35, ap_sig_cseq_ST_st117_fsm_33, ap_sig_cseq_ST_st118_fsm_34, ap_sig_cseq_ST_st120_fsm_36, ap_sig_cseq_ST_st121_fsm_37, ap_reg_ioackin_outs_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_32) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_33) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_34) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st119_fsm_35) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st120_fsm_36) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st121_fsm_37) and (ap_const_logic_0 = ap_reg_ioackin_outs_TREADY)))) then
outs_TVALID <= ap_const_logic_1;
else
outs_TVALID <= ap_const_logic_0;
end if;
end process;
rez_addr149150_part_set_fu_647_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_fu_613_p16);
rez_addr_1146147_part_set_fu_778_p5 <= (ap_const_lv576_lc_1(575 downto 480) & tmp_1_fu_744_p16);
t_load_fu_1065_p1 <= grp_fu_459_p4;
t_load_s_fu_1080_p1 <= grp_fu_459_p4;
t_write_assign_toint_fu_1032_p1 <= grp_fu_438_p2;
tmp_1_fu_744_p16 <= ((((((((((((((ins_data_tmp_load_29_toint_fu_740_p1 & ins_data_tmp_load_28_toint_fu_712_p1) & ins_data_tmp_load_27_toint_fu_708_p1) & ins_data_tmp_load_26_toint_fu_704_p1) & ins_data_tmp_load_25_toint_fu_700_p1) & ins_data_tmp_load_24_toint_fu_696_p1) & ins_data_tmp_load_23_toint_fu_692_p1) & ins_data_tmp_load_22_toint_fu_688_p1) & ins_data_tmp_load_21_toint_fu_684_p1) & ins_data_tmp_load_20_toint_fu_680_p1) & ins_data_tmp_load_19_toint_fu_676_p1) & ins_data_tmp_load_18_toint_fu_672_p1) & ins_data_tmp_load_17_toint_fu_668_p1) & ins_data_tmp_load_16_toint_fu_664_p1) & ins_data_tmp_load_15_toint_fu_660_p1);
tmp_2_fu_1044_p4 <= ((beta_write_assign_toint_fu_1040_p1 & gamma_write_assign_toint_fu_1036_p1) & t_write_assign_toint_fu_1032_p1);
tmp_3_fu_808_p1 <= data_array_q0(32 - 1 downto 0);
tmp_61_neg_i_fu_1022_p2 <= (tmp_61_to_int_i_fu_1019_p1 xor ap_const_lv32_80000000);
tmp_61_to_int_i_fu_1019_p1 <= ap_reg_ppstg_tmp_25_i_reg_1561_pp0_it76;
tmp_fu_613_p16 <= ((((((((((((((ins_data_tmp_load_14_toint_fu_609_p1 & ins_data_tmp_load_13_toint_fu_605_p1) & ins_data_tmp_load_12_toint_fu_601_p1) & ins_data_tmp_load_11_toint_fu_597_p1) & ins_data_tmp_load_10_toint_fu_593_p1) & ins_data_tmp_load_9_toint_fu_589_p1) & ins_data_tmp_load_8_toint_fu_585_p1) & ins_data_tmp_load_7_toint_fu_581_p1) & ins_data_tmp_load_6_toint_fu_577_p1) & ins_data_tmp_load_5_toint_fu_573_p1) & ins_data_tmp_load_4_toint_fu_569_p1) & ins_data_tmp_load_3_toint_fu_565_p1) & ins_data_tmp_load_2_toint_fu_561_p1) & ins_data_tmp_load_1_toint_fu_557_p1) & ins_data_tmp_load_toint_fu_553_p1);
tmp_s_fu_803_p1 <= std_logic_vector(resize(unsigned(i1_reg_238),64));
v0x_assign4_fu_952_p1 <= tmp_3_reg_1155;
v0y_assign_fu_958_p1 <= v0y_assign_new_reg_1160;
v0z_assign_fu_964_p1 <= v0z_assign_new_reg_1165;
end behav;
| mit | ec187ce1fb6c40f7d3c99a61068adcf2 | 0.604052 | 2.713429 | false | false | false | false |
davewebb8211/ghdl | libraries/vital95/vital_primitives.vhdl | 6 | 68,265 | -- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
--
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
CONSTANT Data : IN std_logic_vector);
END VITAL_Primitives;
| gpl-2.0 | bf9174c9fe240dd6ac9c4dc31e22d575 | 0.468732 | 5.733182 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/Barra3.vhd | 1 | 2,183 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:59:10 12/04/2017
-- Design Name:
-- Module Name: Barra3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Barra3 is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
a18in : in STD_LOGIC_VECTOR (31 downto 0);
aluresultin : in STD_LOGIC_VECTOR (31 downto 0);
wrenmenin : in STD_LOGIC;
PCCin : in STD_LOGIC_VECTOR (31 downto 0);
PCCout : out STD_LOGIC_VECTOR (31 downto 0);
rfsource : in STD_LOGIC_VECTOR (1 downto 0);
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
a18inout : out STD_LOGIC_VECTOR (31 downto 0);
aluresultout : out STD_LOGIC_VECTOR (31 downto 0);
wrenmeninout : out STD_LOGIC;
rfsourceout : out STD_LOGIC_VECTOR (1 downto 0));
end Barra3;
architecture Behavioral of Barra3 is
begin
process(Clk,Reset,a18in,aluresultin,wrenmenin,PCCin,rfsource,RD )
begin
if reset='1' then
a18inout <= "00000000000000000000000000000000";
aluresultout <= "00000000000000000000000000000000";
wrenmeninout <= '0';
rfsourceout <= "00";
PCCout<= "00000000000000000000000000000000";
RDout <= "000000";
elsif(rising_edge(Clk)) then
RDout<= RD;
a18inout <= a18in;
aluresultout <= aluresultin;
wrenmeninout <= wrenmenin;
rfsourceout <= rfsource;
PCCout<=PCCin;
end if;
end process;
end Behavioral;
| gpl-3.0 | 66bd59ca78a947c8f53d0b442ca08526 | 0.585433 | 4.042593 | false | false | false | false |
louis-bonicel/VHDL | Porte_AND/adder_tb.vhd | 2 | 1,527 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:05:11 02/06/2015
-- Design Name:
-- Module Name: adder_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder_tb is
end adder_tb;
architecture archi of adder_tb is
signal entree1, entree2, sortie: std_logic_vector(3 downto 0);
signal carry, overflow: std_logic;
component adder
port (a,b: in std_logic_vector (3 downto 0);
s: out std_logic_vector (3 downto 0);
cf, ovf: out std_logic);
end component;
begin
-- de la même manière que l'on fait un port map, on va faire un generic map pour
-- attribuer une valeur au paramètre N de AddN
uut: adder port map (a=> entree1, b => entree2, s => sortie, cf => carry, ovf => overflow);
stimuli_entree1: process
begin
entree1 <= (others => '0');
wait for 10 ns;
loop
entree1 <= entree1 + 1;
wait for 10 ns;
end loop;
end process;
stimuli_entree2: process
begin
entree2<= (others => '0') ;
loop
if entree1=0 then
entree2 <= entree2 + 1;
end if;
wait for 10 ns ;
end loop ;
end process;
end archi; | gpl-2.0 | a79e2310f6ab10a5da3a93790abf7c7a | 0.547479 | 3.334061 | false | false | false | false |
loetlab-jena/das-atv | hdl/src/timing_gen.vhd | 1 | 1,739 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timing_gen is
port
(
clk : in std_logic;
de : in std_logic;
vs : in std_logic;
hs : in std_logic;
sync : out std_logic;
burst : out std_logic
);
end entity;
architecture rtl of timing_gen is
signal de_d : std_logic;
signal vs_d : std_logic;
signal hs_d : std_logic;
signal hcnt : unsigned(10 downto 0);
signal vcnt : integer range 0 to 1023;
signal ss : std_logic; -- short sync
signal ns : std_logic; -- normal sync
signal bs : std_logic; -- burst sync
signal ls : std_logic; -- long sync
begin
counter : process
begin
wait until rising_edge(clk);
vs_d <= vs;
hs_d <= hs;
hcnt <= hcnt + 1;
if hs_d = '1' and hs = '0' then
hcnt <= (others => '0');
vcnt <= vcnt + 1;
end if;
if vs_d = '1' and vs = '0' and hs_d = '1' and hs = '0' then
vcnt <= 0;
end if;
end process;
sync_generator : process
begin
wait until rising_edge(clk);
if hcnt = 0 then
case vcnt is
when 0|1|2|313|314 =>
ls <= '1';
bs <= '0';
when 3|4|310|311|312|315|316|622|623|624 =>
ss <= '1';
bs <= '0';
when others =>
ns <= '1';
bs <= '1';
end case;
end if;
if hcnt = 863 then
case vcnt is
when 0|1|312|313|314 =>
ls <= '1';
when 2|3|4|310|311|315|316|622|623|624 =>
ss <= '1';
when others =>
end case;
end if;
if hcnt = 54 or hcnt = 918 then
ss <= '0';
end if;
if hcnt = 127 then
ns <= '0';
end if;
if hcnt = 810 or hcnt = 1674 then
ls <= '0';
end if;
if hcnt = 151 and bs = '1' then
burst <= '1';
end if;
if hcnt = 212 and bs = '1' then
burst <= '0';
end if;
end process;
sync <= ss or ns or ls;
end rtl;
| gpl-2.0 | 81aee75bd816a50ef5b206b25ec72b6b | 0.557217 | 2.484286 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/SearchRowTestbench.vhd | 1 | 4,247 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
entity SearchRowTestbench is
end SearchRowTestbench;
architecture Behavioral of SearchRowTestbench is
constant DATA_WIDTH_A_USAR : integer := 32;
constant ADDR_WIDTH_A_USAR : integer := 10;
signal clk : std_logic;-- un solo reloj para ambos puertos de la BRAM
signal dataToCompare : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0);
signal operationID : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0);
signal previousIndex : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0);
signal compare : std_logic := '0';--El dato actual se debe comparar
signal previousResult : std_logic;--El resultado es encontrado'1' o no
signal porta_wr : std_logic;
signal porta_waddr : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0);
signal porta_din : std_logic_vector( (DATA_WIDTH_A_USAR-1) downto 0);
--valores de saldia de esta columna
signal result : std_logic;--El resultado es encontrado'1' o no
signal nextIndex : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0);
signal compareFinished : std_logic; --Resultado de una comparación listo
signal dataReadDuringIOTest : std_logic_vector( (DATA_WIDTH_A_USAR-1) downto 0);
signal dataCompared : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0);
signal valorLeido_dbg : ieee.numeric_std.unsigned( (DATA_WIDTH_A_USAR-1) downto 0);
constant clk_period : time := 10 ns;
constant radioTest : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0):="0100000000";
begin
uut : entity work.BinarySearch_ComparingRow
generic map (
DATA_WIDTH => DATA_WIDTH_A_USAR,
ADDR_WIDTH => ADDR_WIDTH_A_USAR
)
port map(
clk => clk,
radio => radioTest,
dataToCompare => dataToCompare,
operationID => operationID,
previousIndex => previousIndex,
compare => compare,
previousResult => previousResult,
porta_wr => porta_wr,
porta_waddr => porta_waddr,
porta_din => porta_din,
result => result,
nextIndex => nextIndex,
compareFinished => compareFinished,
dataCompared => dataCompared,
valorLeido_dbg => valorLeido_dbg
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test : process
variable readWriteCounter : integer := 0;
variable dataToWrite : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := ( others => '0');
variable addrToWrite : std_logic_vector((ADDR_WIDTH_A_USAR-1) downto 0) := ( others => '0');
begin
-- Primero grabar los datos en la memoria
porta_wr <= '0';
porta_waddr <= addrToWrite;
porta_din <= dataToWrite;
previousResult <= '0';
wait for clk_period;
porta_wr <= '1';
while readWriteCounter < (2**ADDR_WIDTH_A_USAR) loop
porta_waddr <= addrToWrite;
porta_din <= dataToWrite;
wait for clk_period;
dataToWrite := dataToWrite+1;
addrToWrite := addrToWrite+1;
readWriteCounter := readWriteCounter+1;
end loop;
-- Ahora comparar un dato de prueba
porta_wr <= '0';
wait for clk_period;
dataToCompare <= x"00000001";
operationID <= (others=>'1');
previousIndex <= "1000000000";
compare<= '0';
previousResult <= '0';
wait for clk_period;
compare<= '1';
wait for clk_period;
compare<= '0';
wait;
end process;
end Behavioral;
| bsd-3-clause | 1d3b5e183499ae5399e35a042fa3b449 | 0.544041 | 4.31066 | false | true | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng.vhd | 3 | 4,028 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| bsd-3-clause | 3e95d54c7eba1d8071d579e44a079ddc | 0.643992 | 4.266949 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen.vhd | 4 | 4,710 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| bsd-3-clause | 23c8b36003a6d0d3bf176b3261736765 | 0.607856 | 4.109948 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/sim/tri_intersect_ap_fsub_7_full_dsp_32.vhd | 1 | 10,725 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fsub_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fsub_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fsub_7_full_dsp_32_arch OF tri_intersect_ap_fsub_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fsub_7_full_dsp_32_arch;
| mit | 88f438d31eb563dabd62a811e3f3d09d | 0.632727 | 3.216857 | false | false | false | false |
davewebb8211/ghdl | libraries/vital2000/timing_p.vhdl | 7 | 65,467 | -------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- v98.0 |TAG | 03/27/98 | Initial ballot draft 1998
-- | #IR225 - Negative Premptive Glitch
-- **Pkg_effected=VitalPathDelay,
-- VitalPathDelay01,VitalPathDelay01z.
-- #IR105 - Skew timing check needed
-- **Pkg_effected=NONE, New code added!!
-- #IR248 - Allows VPD to use a default timing
-- delay
-- **Pkg_effected=VitalPathDelay,
-- VitalPathDelay01,VitalPathDelay01z,
-- #IR250 - Corrects fastpath condition in VPD
-- **Pkg_effected=VitalPathDelay01,
-- VitalPathDelay01z,
-- #IR252 - Corrects cancelled timing check call if
-- condition expires.
-- **Pkg_effected=VitalSetupHoldCheck,
-- VitalRecoveryRemovalCheck.
-- #IR105 - Skew timing check
-- **Pkg_effected=NONE, New code added
-- v98.1 | jdc | 03/25/99 | Changed UseDefaultDelay to IgnoreDefaultDelay
-- and set default to FALSE in VitalPathDelay()
-- v00.7 | dbb | 07/18/00 | Removed "maximum" from VitalPeriodPulse()
-- comments
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- Addition of Vital Skew Type Information
-- March 14, 1998
---------------------------------------------------------------------------
-- Procedures and Type Definitions for Defining Skews
---------------------------------------------------------------------------
TYPE VitalSkewExpectedType IS (none, s1r, s1f, s2r, s2f);
TYPE VitalSkewDataType IS RECORD
ExpectedType : VitalSkewExpectedType;
Signal1Old1 : TIME;
Signal2Old1 : TIME;
Signal1Old2 : TIME;
Signal2Old2 : TIME;
END RECORD;
CONSTANT VitalSkewDataInit : VitalSkewDataType := ( none, 0 ns, 0 ns, 0 ns, 0 ns );
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set
-- VitalDelayType01Z of values.
--
-- IgnoreDefaultDelay BOOLEAN If TRUE, the default delay will
-- be used when no paths are
-- selected. If false, no event
-- will be scheduled if no paths are
-- selected.
--
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- IgnoreDefaultDelay BOOLEAN Tells the VPD whether to use the
-- default delay value in the absense
-- of a valid delay for input conditions 3/14/98 MG
--
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE --IR248 3/14/98
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98
CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98
CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0".
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
-- EnableSetupOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no setup check will be performed.
-- EnableSetupOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no setup check will be performed.
-- EnableHoldOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no hold check will be performed.
-- EnableHoldOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no hold check will be performed.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
-- EnableRecOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no recovery check will be performed.
-- EnableRecOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no recovery check will be performed.
-- EnableRemOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no removal check will be performed.
-- EnableRemOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no removal check will be performed.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableRecOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRecOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRemOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRemOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0".
-- XOnChecks is a global that allows for
-- only timing checks to be turned on.
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgOnChecks allows for only timing
-- check messages to be turned on.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalInPhaseSkewCheck
--
-- Description: The VitalInPhaseSkewCheck procedure detects an in-phase
-- skew violation between input signals Signal1 and Signal2.
-- This is a timer based skew check in which a
-- violation is detected if Signal1 and Signal2 are in
-- different logic states longer than the specified skew
-- interval.
--
-- The timing constraints are specified through parameters
-- representing the skew values for the different states
-- of Signal1 and Signal2.
--
--
-- Signal2 XXXXXXXXXXXX___________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| |<--
-- : Signal2 should go low in this region
-- :
--
-- ____________
-- Signal1 \_________________________________________________
-- : | |
-- : |<-------- tskew -------->|
--
-- Arguments:
--
-- IN Type Description
-- Signal1 std_ulogic Value of first signal
-- Signal1Name STRING Name of first signal
-- Signal1Delay TIME Model's internal delay associated
-- with Signal1
-- Signal2 std_ulogic Value of second signal
-- Signal2Name STRING Name of second signal
-- Signal2Delay TIME Model's internal delay associated
-- with Signal2
-- SkewS1S2RiseRise TIME Absolute maximum time duration for
-- which Signal2 can remain at "0"
-- after Signal1 goes to the "1" state,
-- without causing a skew violation.
-- SkewS2S1RiseRise TIME Absolute maximum time duration for
-- which Signal1 can remain at "0"
-- after Signal2 goes to the "1" state,
-- without causing a skew violation.
-- SkewS1S2FallFall TIME Absolute maximum time duration for
-- which Signal2 can remain at "1"
-- after Signal1 goes to the "0" state,
-- without causing a skew violation.
-- SkewS2S1FallFall TIME Absolute maximum time duration for
-- which Signal1 can remain at "1"
-- after Signal2 goes to the "0" state,
-- without causing a skew violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, skew timing violation
-- messages will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- SkewData VitalSkewDataType
-- VitalInPhaseSkewCheck information
-- storage area. This is used
-- internally to detect signal edges
-- and record the time of the last edge.
--
--
-- Trigger std_ulogic This signal is used to trigger the
-- process in which the timing check
-- occurs upon expiry of the skew
-- interval.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalInPhaseSkewCheck (
VARIABLE Violation : OUT X01;
VARIABLE SkewData : INOUT VitalSkewDataType;
SIGNAL Signal1 : IN std_ulogic;
CONSTANT Signal1Name : IN STRING := "";
CONSTANT Signal1Delay : IN TIME := 0 ns;
SIGNAL Signal2 : IN std_ulogic;
CONSTANT Signal2Name : IN STRING := "";
CONSTANT Signal2Delay : IN TIME := 0 ns;
CONSTANT SkewS1S2RiseRise : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1RiseRise : IN TIME := TIME'HIGH;
CONSTANT SkewS1S2FallFall : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1FallFall : IN TIME := TIME'HIGH;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT HeaderMsg : IN STRING := "";
SIGNAL Trigger : INOUT std_ulogic
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalOutPhaseSkewCheck
--
-- Description: The VitalOutPhaseSkewCheck procedure detects an
-- out-of-phase skew violation between input signals Signal1
-- and Signal2. This is a timer based skew check in
-- which a violation is detected if Signal1 and Signal2 are
-- in the same logic state longer than the specified skew
-- interval.
--
-- The timing constraints are specified through parameters
-- representing the skew values for the different states
-- of Signal1 and Signal2.
--
--
-- Signal2 XXXXXXXXXXXX___________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| |<--
-- : Signal2 should go high in this region
-- :
--
-- ____________
-- Signal1 \_________________________________________________
-- : | |
-- : |<-------- tskew -------->|
--
-- Arguments:
--
-- IN Type Description
-- Signal1 std_ulogic Value of first signal
-- Signal1Name STRING Name of first signal
-- Signal1Delay TIME Model's internal delay associated
-- with Signal1
-- Signal2 std_ulogic Value of second signal
-- Signal2Name STRING Name of second signal
-- Signal2Delay TIME Model's internal delay associated
-- with Signal2
-- SkewS1S2RiseFall TIME Absolute maximum time duration for
-- which Signal2 can remain at "1"
-- after Signal1 goes to the "1" state,
-- without causing a skew violation.
-- SkewS2S1RiseFall TIME Absolute maximum time duration for
-- which Signal1 can remain at "1"
-- after Signal2 goes to the "1" state,
-- without causing a skew violation.
-- SkewS1S2FallRise TIME Absolute maximum time duration for
-- which Signal2 can remain at "0"
-- after Signal1 goes to the "0" state,
-- without causing a skew violation.
-- SkewS2S1FallRise TIME Absolute maximum time duration for
-- which Signal1 can remain at "0"
-- after Signal2 goes to the "0" state,
-- without causing a skew violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, skew timing violation
-- messages will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- SkewData VitalSkewDataType
-- VitalInPhaseSkewCheck information
-- storage area. This is used
-- internally to detect signal edges
-- and record the time of the last edge.
--
-- Trigger std_ulogic This signal is used to trigger the
-- process in which the timing check
-- occurs upon expiry of the skew
-- interval.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalOutPhaseSkewCheck (
VARIABLE Violation : OUT X01;
VARIABLE SkewData : INOUT VitalSkewDataType;
SIGNAL Signal1 : IN std_ulogic;
CONSTANT Signal1Name : IN STRING := "";
CONSTANT Signal1Delay : IN TIME := 0 ns;
SIGNAL Signal2 : IN std_ulogic;
CONSTANT Signal2Name : IN STRING := "";
CONSTANT Signal2Delay : IN TIME := 0 ns;
CONSTANT SkewS1S2RiseFall : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1RiseFall : IN TIME := TIME'HIGH;
CONSTANT SkewS1S2FallRise : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1FallRise : IN TIME := TIME'HIGH;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT HeaderMsg : IN STRING := "";
SIGNAL Trigger : INOUT std_ulogic
);
END VITAL_Timing;
| gpl-2.0 | 1a474e9af8f3e23210cb66f422ae9fdd | 0.444071 | 6.024386 | false | true | false | false |
kennethlyn/parallella-lcd-fpga | system/system_top.vhd | 3 | 7,527 | -------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_top is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
I2C_SCL : inout std_logic;
I2C_SDA : inout std_logic;
I2C_INT_N : in std_logic;
HSYNC : out std_logic;
VSYNC : out std_logic;
PXL_CLK : out std_logic;
DE : out std_logic;
RED : out std_logic_vector(5 downto 0);
GREEN : out std_logic_vector(5 downto 0);
BLUE : out std_logic_vector(5 downto 0);
brigthness_pin : out std_logic;
tft_ena : out std_logic;
tft_wake_n : out std_logic
);
end system_top;
architecture STRUCTURE of system_top is
component system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
processing_system7_0_I2C0_SCL_pin :inout std_logic;
processing_system7_0_I2C0_SDA_pin :inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
signal axi_dispctrl_0_HSYNC_O_pin : std_logic;
signal axi_dispctrl_0_VSYNC_O_pin : std_logic;
signal axi_dispctrl_0_PXL_CLK_O_pin : std_logic;
signal axi_dispctrl_0_DE_O_pin : std_logic;
signal axi_dispctrl_0_RED_O_pin : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_GREEN_O_pin : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_BLUE_O_pin : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_ENABLE_O_pin : std_logic;
signal clk_100MHz : std_logic;
begin
brigthness_pin <= '1';
tft_ena <= axi_dispctrl_0_ENABLE_O_pin;
HSYNC <= axi_dispctrl_0_HSYNC_O_pin;
VSYNC <= axi_dispctrl_0_VSYNC_O_pin;
PXL_CLK <= axi_dispctrl_0_PXL_CLK_O_pin;
DE <= axi_dispctrl_0_DE_O_pin;
RED <= axi_dispctrl_0_RED_O_pin (7 downto 2);
GREEN <= axi_dispctrl_0_GREEN_O_pin (7 downto 2);
BLUE <= axi_dispctrl_0_BLUE_O_pin (7 downto 2);
lcd_reset: process (clk_100MHz)
variable rst_count: integer range 0 to 1_000_000 := 0;
begin
if( rising_edge(clk_100MHz) ) then
if( rst_count = 1_000_000 ) then
tft_wake_n <= '1';
else
tft_wake_n <= '0';
rst_count := rst_count + 1;
end if;
end if;
end process;
system_i : system
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
processing_system7_0_I2C0_SCL_pin => I2C_SCL,
processing_system7_0_I2C0_SDA_pin => I2C_SDA,
processing_system7_0_I2C0_INT_N_pin => I2C_INT_N,
processing_system7_0_FCLK_CLK0_pin => clk_100MHz,
axi_dispctrl_0_HSYNC_O_pin => axi_dispctrl_0_HSYNC_O_pin,
axi_dispctrl_0_VSYNC_O_pin => axi_dispctrl_0_VSYNC_O_pin,
axi_dispctrl_0_PXL_CLK_O_pin => axi_dispctrl_0_PXL_CLK_O_pin,
axi_dispctrl_0_DE_O_pin => axi_dispctrl_0_DE_O_pin,
axi_dispctrl_0_RED_O_pin => axi_dispctrl_0_RED_O_pin,
axi_dispctrl_0_GREEN_O_pin => axi_dispctrl_0_GREEN_O_pin,
axi_dispctrl_0_BLUE_O_pin => axi_dispctrl_0_BLUE_O_pin,
axi_dispctrl_0_ENABLE_O_pin => axi_dispctrl_0_ENABLE_O_pin
);
end architecture STRUCTURE;
| bsd-3-clause | b69b117bdff9d358ca5e5f561d12a286 | 0.671981 | 2.875095 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl.vhd | 4 | 16,627 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND FULL = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-3-clause | a705c641ed22deb6af944f68f11c1a7c | 0.524027 | 3.338755 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen.vhd | 4 | 4,710 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| bsd-3-clause | 44741d9f6d5d5545022c5d6f8ae4b0a6 | 0.607856 | 4.109948 | false | false | false | false |
alemedeiros/flappy_vhdl | obstacles/update_obstacles.vhd | 1 | 1,501 | -- file: obstacles/update_obstacles.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Update and generate new obstacles for game.
library ieee ;
use ieee.std_logic_1164.all ;
library modules;
use modules.obstacles.all;
entity update_obstacles is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
new_obst : in std_logic ;
obst_count : buffer integer range -2 to 255 ;
low_obst : out integer range 0 to V_RES - 1 ;
high_obst : out integer range 0 to V_RES - 1 ;
obst_rem : out std_logic ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end update_obstacles ;
architecture behavior of update_obstacles is
signal pos : integer range 0 to H_RES / N_OBST - 1 ;
signal low_aux : integer range 0 to V_RES - 1 ;
begin
process (new_obst)
begin
if reset = '1' then
obst_count <= -2 ;
elsif enable = '1' and rising_edge(new_obst) then
obst_count <= obst_count + 1 ;
end if;
end process ;
qlow1: generate_random
generic map (V_RES => V_RES)
port map (seed => "10011",
clock => new_obst,
rand => low_aux) ;
high_obst <= V_RES - low_aux - 35 ;
low_obst <= low_aux ;
obst_rem <= new_obst ;
end behavior;
| bsd-3-clause | 2af208fc548c86c22a3feb77747b8c38 | 0.61026 | 3.380631 | false | false | false | false |
davewebb8211/ghdl | libraries/vital2000/prmtvs_p.vhdl | 7 | 68,530 | -- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
| gpl-2.0 | 2aac9391fbf9015d854bc2a41daa5345 | 0.468102 | 5.723712 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/hdl/system_axi_vdma_0_wrapper.vhd | 3 | 17,777 | -------------------------------------------------------------------------------
-- system_axi_vdma_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_vdma_v5_04_a;
use axi_vdma_v5_04_a.all;
entity system_axi_vdma_0_wrapper is
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(8 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(31 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(8 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(31 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(31 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(31 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(31 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(63 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(31 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector(3 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(0 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(31 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(31 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector(3 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(31 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector(3 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(0 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector(5 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector(5 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_axi_vdma_0_wrapper : entity is "axi_vdma_v5_04_a";
end system_axi_vdma_0_wrapper;
architecture STRUCTURE of system_axi_vdma_0_wrapper is
component axi_vdma is
generic (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_INCLUDE_SG : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING
);
port (
s_axi_lite_aclk : in std_logic;
m_axi_sg_aclk : in std_logic;
m_axi_mm2s_aclk : in std_logic;
m_axi_s2mm_aclk : in std_logic;
m_axis_mm2s_aclk : in std_logic;
s_axis_s2mm_aclk : in std_logic;
axi_resetn : in std_logic;
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
m_axi_sg_araddr : out std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
m_axi_sg_arlen : out std_logic_vector(7 downto 0);
m_axi_sg_arsize : out std_logic_vector(2 downto 0);
m_axi_sg_arburst : out std_logic_vector(1 downto 0);
m_axi_sg_arprot : out std_logic_vector(2 downto 0);
m_axi_sg_arcache : out std_logic_vector(3 downto 0);
m_axi_sg_arvalid : out std_logic;
m_axi_sg_arready : in std_logic;
m_axi_sg_rdata : in std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0);
m_axi_sg_rresp : in std_logic_vector(1 downto 0);
m_axi_sg_rlast : in std_logic;
m_axi_sg_rvalid : in std_logic;
m_axi_sg_rready : out std_logic;
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0);
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0);
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0);
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0);
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0);
m_axi_mm2s_arvalid : out std_logic;
m_axi_mm2s_arready : in std_logic;
m_axi_mm2s_rdata : in std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0);
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0);
m_axi_mm2s_rlast : in std_logic;
m_axi_mm2s_rvalid : in std_logic;
m_axi_mm2s_rready : out std_logic;
mm2s_prmry_reset_out_n : out std_logic;
m_axis_mm2s_tdata : out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
m_axis_mm2s_tkeep : out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
m_axis_mm2s_tvalid : out std_logic;
m_axis_mm2s_tready : in std_logic;
m_axis_mm2s_tlast : out std_logic;
m_axis_mm2s_tuser : out std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS-1 to 0);
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0);
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0);
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0);
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0);
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0);
m_axi_s2mm_awvalid : out std_logic;
m_axi_s2mm_awready : in std_logic;
m_axi_s2mm_wdata : out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0);
m_axi_s2mm_wstrb : out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0);
m_axi_s2mm_wlast : out std_logic;
m_axi_s2mm_wvalid : out std_logic;
m_axi_s2mm_wready : in std_logic;
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0);
m_axi_s2mm_bvalid : in std_logic;
m_axi_s2mm_bready : out std_logic;
s2mm_prmry_reset_out_n : out std_logic;
s_axis_s2mm_tdata : in std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0);
s_axis_s2mm_tkeep : in std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0);
s_axis_s2mm_tvalid : in std_logic;
s_axis_s2mm_tready : out std_logic;
s_axis_s2mm_tlast : in std_logic;
s_axis_s2mm_tuser : in std_logic_vector(C_S_AXIS_S2MM_TUSER_BITS-1 to 0);
mm2s_fsync : in std_logic;
mm2s_frame_ptr_in : in std_logic_vector((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0);
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0);
mm2s_fsync_out : out std_logic;
mm2s_prmtr_update : out std_logic;
mm2s_buffer_empty : out std_logic;
mm2s_buffer_almost_empty : out std_logic;
s2mm_fsync : in std_logic;
s2mm_frame_ptr_in : in std_logic_vector((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0);
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0);
s2mm_fsync_out : out std_logic;
s2mm_buffer_full : out std_logic;
s2mm_buffer_almost_full : out std_logic;
s2mm_prmtr_update : out std_logic;
mm2s_introut : out std_logic;
s2mm_introut : out std_logic;
axi_vdma_tstvec : out std_logic_vector(63 downto 0)
);
end component;
begin
axi_vdma_0 : axi_vdma
generic map (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_FLUSH_ON_FSYNC => 1,
C_DYNAMIC_RESOLUTION => 1,
C_INCLUDE_SG => 0,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_INCLUDE_MM2S => 1,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_SOF_ENABLE => 1,
C_MM2S_MAX_BURST_LENGTH => 16,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 1000,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_SOF_ENABLE => 1,
C_S2MM_MAX_BURST_LENGTH => 16,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_LINEBUFFER_DEPTH => 128,
C_S2MM_LINEBUFFER_THRESH => 4,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_FAMILY => "zynq",
C_INSTANCE => "axi_vdma_0"
)
port map (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
mm2s_fsync_out => mm2s_fsync_out,
mm2s_prmtr_update => mm2s_prmtr_update,
mm2s_buffer_empty => mm2s_buffer_empty,
mm2s_buffer_almost_empty => mm2s_buffer_almost_empty,
s2mm_fsync => s2mm_fsync,
s2mm_frame_ptr_in => s2mm_frame_ptr_in,
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
s2mm_fsync_out => s2mm_fsync_out,
s2mm_buffer_full => s2mm_buffer_full,
s2mm_buffer_almost_full => s2mm_buffer_almost_full,
s2mm_prmtr_update => s2mm_prmtr_update,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_vdma_tstvec => axi_vdma_tstvec
);
end architecture STRUCTURE;
| bsd-3-clause | 5b69238bcfc94f9eac07a1e5896d7047 | 0.620577 | 2.60507 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_smple_sm.vhd | 1 | 16,873 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (31 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
| mit | d59a5795004f2c524a6839d757252816 | 0.382208 | 5.458751 | false | false | false | false |
alemedeiros/flappy_vhdl | input/input_parser.vhd | 1 | 1,329 | -- file: input/input_parser.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Parses input signals from switches and keys and attributes the adequate
-- values to the internal signals.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.numeric_std.all ;
entity input_parser is
generic (
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
key : in std_logic_vector(3 downto 0) ;
sw : in std_logic_vector(9 downto 0) ;
clock : in std_logic ;
jump : out std_logic ;
reset : out std_logic ;
pause : out std_logic ;
gravity : out integer range 0 to V_RES - 1
) ;
end input_parser ;
architecture behavior of input_parser is
begin
-- Syncronize input with circuit clock changes to minimize hazards.
process(clock)
variable tmp_key : std_logic_vector(3 downto 0) ;
variable tmp_sw : std_logic_vector(9 downto 0) ;
begin
if rising_edge(clock) then
-- Update output.
jump <= not tmp_key(3) ;
reset <= not tmp_key(2) ;
pause <= tmp_sw(9) ;
gravity <= to_integer(signed(tmp_sw(7 downto 0))) ;
-- Update local buffer.
tmp_key := key ;
tmp_sw := sw ;
end if ;
end process ;
end behavior ;
| bsd-3-clause | 08ba27976713091b75b5575520b6bd42 | 0.64936 | 3.194712 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/example_design/system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd | 3 | 5,689 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-3-clause | 765f13ffcc27f7f8fb5cbd9865a5235c | 0.517841 | 4.788721 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/synth/tri_intersect_ap_fdiv_28_no_dsp_32.vhd | 3 | 12,682 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fdiv_28_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fdiv_28_no_dsp_32;
ARCHITECTURE tri_intersect_ap_fdiv_28_no_dsp_32_arch OF tri_intersect_ap_fdiv_28_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fdiv_28_no_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fdiv_28_no_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fdiv_28_no_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=28,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fdiv_28_no_dsp_32_arch;
| mit | 8ccb3230cdc6bd37fbb26bd4a3204491 | 0.651948 | 3.021682 | false | false | false | false |
louis-bonicel/VHDL | Porte_AND/componant_1_tb.vhd | 2 | 1,440 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:55:04 01/15/2015
-- Design Name:
-- Module Name: componant_1_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity componant_1_tb is
end componant_1_tb;
architecture Behavioral of componant_1_tb is
signal entree1, entree2, sortie1, sortie2 : std_logic;
component componant_1
port (e1,e2 : in std_logic;
s1,s2 : out std_logic);
end component;
begin
uut: componant_1 port map (e1 => entree1, e2 => entree2, s1 => sortie1, s2 => sortie2);
stimuli:process
begin
entree1<='0';
entree2<='0';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
end process;
end Behavioral;
| gpl-2.0 | 47fe247d72f8ce14229a047248dddd72 | 0.572917 | 3.512195 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_xlconcat_0_0/synth/triangle_intersect_xlconcat_0_0.vhd | 1 | 8,960 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY triangle_intersect_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END triangle_intersect_xlconcat_0_0;
ARCHITECTURE triangle_intersect_xlconcat_0_0_arch OF triangle_intersect_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF triangle_intersect_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF triangle_intersect_xlconcat_0_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF triangle_intersect_xlconcat_0_0_arch : ARCHITECTURE IS "triangle_intersect_xlconcat_0_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF triangle_intersect_xlconcat_0_0_arch: ARCHITECTURE IS "triangle_intersect_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 2,
NUM_PORTS => 2
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END triangle_intersect_xlconcat_0_0_arch;
| mit | 708228c977aa6fbddbbe053dfd7e78b2 | 0.651339 | 3.267688 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/WindowsManager.vhd | 2 | 2,607 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity WindowsManager is
Port ( cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0'));
end WindowsManager;
architecture Behavioral of WindowsManager is
signal int_rs1, int_rs2, int_rd : integer range 0 to 39 := 0;
begin
process(cwp,rs1,rs2,rd,op,op3)
begin
--guardar instruccion save
if (op = "10" and op3 = "111100") then
cwpout <= '0';
--reset instruction
elsif (op = "10" and op3 = "111101") then
cwpout <= '1';
end if;
--registros goli rs1
if (rs1 >= "11000" and rs1 <= "11111") then
int_rs1 <= conv_integer(rs1) - conv_integer(cwp) * 16; --input
elsif (rs1 >= "10000" and rs1 <= "10111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --local
elsif (rs1 >= "01000" and rs1 <= "01111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --output
elsif (rs1 >= "00000" and rs1 <= "00111") then
int_rs1 <= conv_integer(rs1); --global
end if;
--registros goli rs2
if (rs2 >= "11000" and rs2 <= "11111") then
int_rs2 <= conv_integer(rs2) - conv_integer(cwp) * 16; --input
elsif (rs2 >= "10000" and rs2 <= "10111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --local
elsif (rs2 >= "01000" and rs2 <= "01111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --output
elsif (rs2 >= "00000" and rs2 <= "00111") then
int_rs2 <= conv_integer(rs2); --global
end if;
--registros goli rd
if (rd >= "11000" and rd <= "11111") then
int_rd <= conv_integer(rd) - conv_integer(cwp) * 16; --input
elsif (rd >= "10000" and rd <= "10111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --local
elsif (rd >= "01000" and rd <= "01111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --output
elsif (rd >= "00000" and rd <= "00111") then
int_rd <= conv_integer(rd); --global
end if;
end process;
rs1out <= conv_std_logic_vector(int_rs1, 6);
rs2out <= conv_std_logic_vector(int_rs2, 6);
rdout <= conv_std_logic_vector(int_rd, 6);
end Behavioral; | gpl-3.0 | 5e38a6ff9071246929948b6c8b482e55 | 0.591484 | 2.84607 | false | false | false | false |
RaulHuertas/rhpackageexporter | MurmurHashGenerator/ImplementationTest1.vhdl | 1 | 4,644 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
entity ImplementationTest1 is
port(
--entradas
clk : in std_logic;
inputData : in std_logic_vector(7 downto 0);
--salidas
canAccept_output : out std_logic;
resultReady_output : out std_logic;
result_output : out std_logic_vector(31 downto 0)
);
end entity ImplementationTest1;
architecture structural of ImplementationTest1 is
-- generar un registro de salto en la entrada para generar las entradas
-- al modulo
type registroEntradas is array (27 downto 0) of std_logic_vector(7 downto 0);
signal registro : registroEntradas;
signal resultID_output : std_logic_vector(31 downto 0);
-- signal dataStep1_dbg : std_logic_vector(31 downto 0);
-- signal dataStep2_dbg : std_logic_vector(31 downto 0);
-- signal dataStep3_dbg : std_logic_vector(31 downto 0);
-- signal dataStep4_dbg : std_logic_vector(31 downto 0);
-- signal dataStep5_dbg : std_logic_vector(31 downto 0);
-- signal dataStep1_ID_dbg : std_logic_vector(31 downto 0);
-- signal dataStep2_ID_dbg : std_logic_vector(31 downto 0);
-- signal dataStep3_ID_dbg : std_logic_vector(31 downto 0);
-- signal dataStep4_ID_dbg : std_logic_vector(31 downto 0);
-- signal dataStep5_ID_dbg : std_logic_vector(31 downto 0);
-- signal finalStep1_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep2_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep3_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep4_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep5_dbg : out std_logic_vector(31 downto 0)
-- signal finalStep1_ID_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep2_ID_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep3_ID_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep4_ID_dbg : out std_logic_vector(31 downto 0);
-- signal finalStep5_ID_dbg : out std_logic_vector(31 downto 0)
signal inputBlock : std_logic_vector(31 downto 0);
signal operationID : std_logic_vector(31 downto 0);
signal seed : std_logic_vector(31 downto 0);
begin
-- generar al logica del registro de salto
--EntradaDatos: process( clk, registro, inputData) begin
-- if rising_edge(clk) then
-- end if;--clk
--end process EntradaDatos;
salto: for i in 0 to 27 generate
first_reg: if i=0 generate
clk0: process(clk, inputData) begin
if rising_edge(clk)then
registro(0)<= inputData;
end if;
end process clk0;
end generate first_reg;
restOf_reg: if i>0 generate
clkall: process(clk, registro) begin
if rising_edge(clk)then
registro(i)<= registro(i-1);
end if;
end process clkall;
end generate restOf_reg;
end generate salto;
inputBlock <= registro(0)®istro(1)®istro(2)®istro(3);
operationID <= registro(8)®istro(9)®istro(10)®istro(11);
seed <= registro(12)®istro(13)®istro(14)®istro(15);
--instanciar el modulo a probar
hashGenerator: work.MurmurHashUtils.MurmurHash32Generator port map
(
--entradas
inputBlock => inputBlock ,
readInput => registro(4)(0),
blockLength => registro(5)(1 downto 0),
finalBlock => registro(6)(0),
start => registro(7)(0),
operationID => (others => '-'),
seed => seed,
--salidas
canAccept => canAccept_output,
resultReady => resultReady_output,
result => open,
resultID => open,
clk => clk,
dataStep1_dbg => open,
dataStep2_dbg => open,
dataStep3_dbg => open,
dataStep4_dbg => open,
dataStep5_dbg => open,
dataStep1_ID_dbg => open,
dataStep2_ID_dbg => open,
dataStep3_ID_dbg => open,
dataStep4_ID_dbg => open,
dataStep5_ID_dbg => open,
finalStep1_dbg => open,
finalStep2_dbg => open,
finalStep3_dbg => open,
finalStep4_dbg => open,
finalStep5_dbg => open,
finalStep1_ID_dbg => open,
finalStep2_ID_dbg => open,
finalStep3_ID_dbg => open,
finalStep4_ID_dbg => open,
finalStep5_ID_dbg => open
);
end architecture structural;
| bsd-3-clause | 238942f0d2c82b5bf8f6a163bef6ef36 | 0.601852 | 3.724138 | false | false | false | false |
makestuff/s3b_sdram | try1/memctrl/hexutil.vhdl | 1 | 2,992 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hexutil is
function to_1(c : character) return std_logic;
function to_2(c : character) return std_logic_vector;
function to_3(c : character) return std_logic_vector;
function to_4(c : character) return std_logic_vector;
end package;
package body hexutil is
-- Return the bits of the supplied hex nibble
function to_4(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
case c is
when '0' =>
nibble := "0000";
when '1' =>
nibble := "0001";
when '2' =>
nibble := "0010";
when '3' =>
nibble := "0011";
when '4' =>
nibble := "0100";
when '5' =>
nibble := "0101";
when '6' =>
nibble := "0110";
when '7' =>
nibble := "0111";
when '8' =>
nibble := "1000";
when '9' =>
nibble := "1001";
when 'a' =>
nibble := "1010";
when 'A' =>
nibble := "1010";
when 'b' =>
nibble := "1011";
when 'B' =>
nibble := "1011";
when 'c' =>
nibble := "1100";
when 'C' =>
nibble := "1100";
when 'd' =>
nibble := "1101";
when 'D' =>
nibble := "1101";
when 'e' =>
nibble := "1110";
when 'E' =>
nibble := "1110";
when 'f' =>
nibble := "1111";
when 'F' =>
nibble := "1111";
when 'X' =>
nibble := "XXXX";
when 'x' =>
nibble := "XXXX";
when 'Z' =>
nibble := "ZZZZ";
when 'z' =>
nibble := "ZZZZ";
when others =>
nibble := "UUUU";
end case;
return nibble;
end function;
-- Return the least-significant bit of the supplied hex nibble
function to_1(c : character) return std_logic is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(0);
end function;
-- Return two least-significant bits of the supplied hex nibble
function to_2(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(1 downto 0);
end function;
-- Return three least-significant bits of the supplied hex nibble
function to_3(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(2 downto 0);
end function;
end package body;
| gpl-3.0 | 4a8199fc11efb996e1ff4f1b1611dd1f | 0.624332 | 3.169492 | false | false | false | false |
Kalugy/Procesadorarquitectura | Primerprocesador17octubre/ALU.vhd | 1 | 1,690 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:19:49 10/04/2017
-- Design Name:
-- Module Name: ALU - ARQALU
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0));
end ALU;
architecture ARQALU of ALU is
begin
process(OPER1,OPER2,ALUOP)
begin
if(ALUOP = "000010")then
ALURESULT<= OPER1 OR OPER2;
elsif(ALUOP = "000011")then
ALURESULT<= OPER1 XOR OPER2;
elsif(ALUOP = "000000")then
ALURESULT<= OPER1 + OPER2;
elsif(ALUOP = "000100")then
ALURESULT<= OPER1 - OPER2;
elsif(ALUOP = "000001")then
ALURESULT<= OPER1 AND OPER2;
elsif(ALUOP = "000101")then
ALURESULT<= OPER1 AND (not OPER2);
elsif(ALUOP = "000110")then
ALURESULT<= OPER1 NOR OPER2;
elsif(ALUOP = "000111")then
ALURESULT<= OPER1 XNOR OPER2;
end if;
end process;
end ARQALU;
| gpl-3.0 | 601fd4ebfdc49cacdaea5317a1e4e26a | 0.60355 | 3.603412 | false | false | false | false |
Kalugy/Procesadorarquitectura | Terceryfullprocesador/RF.vhd | 1 | 1,688 | ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
wre : in STD_LOGIC;
cRd : out STD_LOGIC_VECTOR (31 downto 0);
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (39 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type;
begin
RAM(0)<= "00000000000000000000000000000000";--serciora g0
process (rst,rd,rs1,rs2,dwr,RAM,wre)
begin
if rst = '1' then
RAM <= (others=>"00000000000000000000000000000000");
crs1 <="00000000000000000000000000000000";
crs2 <="00000000000000000000000000000000";
cRd <= "00000000000000000000000000000000";
RAM(15)<= "00000000000000000000000000001101";--por el jmpl para que lea el main
elsif rd /= "000000" and wre='1' then
RAM(conv_integer(rd)) <= dwr;
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
cRd <= RAM(conv_integer(rd));
else
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
cRd <= RAM(conv_integer(rd));
end if;
end process;
end Behavioral;
| gpl-3.0 | c100e90abc0dfb07a4dad348bd3f63e6 | 0.543246 | 4.02864 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif.vhd | 3 | 5,736 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| bsd-3-clause | 42d4661cf635865600359eb759d5f9fd | 0.585251 | 4.02244 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_mm2s_sg_if.vhd | 1 | 47,006 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sg_if.vhd
-- Description: This entity is the MM2S Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_cdc_v1_0;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Master AXI Control Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 ;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
desc_fetch_done : out std_logic ; --
updt_pending : out std_logic ;
packet_in_progress : out std_logic ; --
--
-- MM2S Descriptor Update Request (from mm2s_sm) --
desc_update_done : out std_logic ; --
--
mm2s_sts_received_clr : out std_logic ; --
mm2s_sts_received : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_done : in std_logic ; --
mm2s_interr : in std_logic ; --
mm2s_slverr : in std_logic ; --
mm2s_decerr : in std_logic ; --
mm2s_tag : in std_logic_vector(3 downto 0) ; --
mm2s_halt : in std_logic ; --
--
-- Control Stream Output --
cntrlstrm_fifo_wren : out std_logic ; --
cntrlstrm_fifo_din : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : in std_logic ; --
--
--
-- MM2S Descriptor Field Output --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_new_curdesc_wren : out std_logic ; --
--
mm2s_desc_baddress : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : out std_logic ; --
mm2s_desc_sof : out std_logic ; --
mm2s_desc_cmplt : out std_logic ; --
mm2s_desc_info : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_mm2s_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(4 downto 0) := (others => '0');
-- Used to determine when Control word is coming, in order to check SOF bit.
-- This then indicates that the app fields need to be directed towards the
-- control stream fifo.
-- Word Five Count
-- Incrementing these counts by 2 as i am now sending two extra fields from BD
--constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "1011"; --"0111";
constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "0001";
-- Word Six Count
--constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0101"; --"1000";
constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0010";
-- Word Seven Count
--constant NINE_COUNT : std_logic_vector(3 downto 0) := "1010"; --"1001";
constant NINE_COUNT : std_logic_vector(3 downto 0) := "0011";
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal desc_fetch_done_i : std_logic := '0';
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Fetch control signals for driving out control app stream
signal analyze_control : std_logic := '0';
signal redirect_app : std_logic := '0';
signal redirect_app_d1 : std_logic := '0';
signal redirect_app_re : std_logic := '0';
signal redirect_app_hold : std_logic := '0';
signal mask_fifo_write : std_logic := '0';
-- Current descriptor control and fetch throttle control
signal mm2s_new_curdesc_wren_i : std_logic := '0';
signal mm2s_pending_update : std_logic := '0';
signal mm2s_pending_ptr_updt : std_logic := '0';
-- Descriptor Update Signals
signal mm2s_complete : std_logic := '0';
signal mm2s_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_xferd_bytes_int : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- Update Descriptor Pointer Holding Registers
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_64_reg0 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
-- Update Descriptor Status Holding Register
signal updt_desc_reg2 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
-- Pointer shift control
signal updt_shftenbl : std_logic := '0';
-- Update pointer stream
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Update status stream
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status control
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal packet_start : std_logic := '0';
signal packet_end : std_logic := '0';
signal mm2s_halt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cdc_d2 : std_logic := '0';
signal mm2s_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cdc_d2 : SIGNAL IS "true";
signal temp : std_logic := '0';
signal m_axis_mm2s_ftch_tlast_new : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
mm2s_desc_blength <= mm2s_desc_blength_i;
mm2s_desc_blength_v <= mm2s_desc_blength_v_i;
mm2s_desc_blength_s <= mm2s_desc_blength_s_i;
-- Drive fetch request done on tlast
desc_fetch_done_i <= m_axis_mm2s_ftch_tlast_new
and m_axis_mm2s_ftch_tvalid_new;
-- pass out of module
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_mm2s_ftch_tvalid_new
and ftch_tready
and desc_fetch_req
and not mm2s_pending_update;
-- Passed curdes write out to register module
mm2s_new_curdesc_wren <= desc_fetch_done_i; --mm2s_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch1_desc_available; --m_axis_mm2s_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_d1_cdc_tig <= '0';
-- -- mm2s_halt_d2 <= '0';
-- -- else
-- mm2s_halt_d1_cdc_tig <= mm2s_halt;
-- mm2s_halt_cdc_d2 <= mm2s_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_d2 <= mm2s_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_d2 <= mm2s_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
packet_start <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_SOF_BIT) = '1'
else '0';
packet_end <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_EOF_BIT) = '1'
else '0';
REG_PACKET_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or packet_end = '1')then
packet_in_progress <= '0';
elsif(packet_start = '1')then
packet_in_progress <= '1';
end if;
end if;
end process REG_PACKET_PROGRESS;
-- Status/Control stream enabled therefore APP fields are included
GEN_FTCHIF_WITH_APP : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
-- Control Stream Ethernet TAG
constant ETHERNET_CNTRL_TAG : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH - 1 downto 0)
:= X"A000_0000";
begin
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); -- downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65);
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- desc 5 are reserved and thus don't care
-- CR 583779, need to pass on tuser and cache information
mm2s_desc_info <= (others => '0'); --desc_reg4; -- this coincides with desc_fetch_done
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= desc_reg8;
mm2s_desc_app1 <= desc_reg9;
mm2s_desc_app2 <= desc_reg10;
mm2s_desc_app3 <= desc_reg11;
mm2s_desc_app4 <= desc_reg12;
-- Drive ready if descriptor fetch request is being made
-- If not redirecting app fields then drive ready based on sm request
-- If redirecting app fields then drive ready based on room in cntrl strm fifo
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
redirect_app <= '0';
cntrlstrm_fifo_din <= (others => '0');
cntrlstrm_fifo_wren <= '0';
end generate GEN_FTCHIF_WITH_APP;
-- Status/Control stream diabled therefore APP fields are NOT included
GEN_FTCHIF_WITHOUT_APP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7(DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
ADDR1_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR1_64BIT;
ADDR1_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR1_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- desc 4 and desc 5 are reserved and thus don't care
-- CR 583779, need to send the user and xchache info
mm2s_desc_info <= (others => '0'); --desc_reg4;
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_mm2s_ftch_tdata_mcdma_new (31 downto 0); --63 downto 32);
desc_reg5 <= m_axis_mm2s_ftch_tdata_mcdma_new (63 downto 32);
ADDR2_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR2_64BIT;
ADDR2_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR2_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- As per new MCDMA descriptor
mm2s_desc_info <= desc_reg4; -- (31 downto 24) & desc_reg7 (23 downto 0);
mm2s_desc_blength_s_i <= "0000000" & desc_reg5(15 downto 0);
mm2s_desc_blength_v_i <= "0000000000" & desc_reg5(31 downto 19);
mm2s_desc_blength_i <= "0000000" & desc_reg6(15 downto 0);
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= '0' ; --desc_reg7(DESC_STS_CMPLTD_BIT); -- we are not considering the completed bit
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_MCDMA;
-- Drive ready if descriptor fetch request is being made
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
end generate GEN_FTCHIF_WITHOUT_APP;
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH > 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_msb & mm2s_desc_baddr_lsb;
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH = 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_msb & mm2s_desc_curdesc_lsb;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_lsb;
end generate GEN_NEW_32BIT_CURDESC;
mm2s_new_curdesc_wren_i <= desc_fetch_done_i;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= mm2s_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
UPDT_ADDR_64BIT : if C_M_AXI_MM2S_ADDR_WIDTH > 32 generate
begin
UPDT_DESC_WRD0_1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= mm2s_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD0_1;
end generate UPDT_ADDR_64BIT;
-----------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg1 <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg1 <= DESC_LAST
& mm2s_desc_curdesc_msb;
-- Shift data out on shift enable
elsif(updt_shftenbl = '1')then
updt_desc_reg1 <= (others => '0');
end if;
end if;
end process UPDT_DESC_WRD1;
-- Shift in data from SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_mm2s_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1' and updtptr_tlast = '1'
and s_axis_mm2s_updtptr_tready = '1'
else '0';
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
--*****************************************************************************
--** Status Update Logic
--*****************************************************************************
mm2s_complete <= '1'; -- Fixed at '1'
---------------------------------------------------------------------------
-- Descriptor queuing turned on in sg engine therefore need to instantiate
-- fifo to hold fetch buffer lengths. Also need to throttle fetches
-- if pointer has not been updated yet or length fifo is full
---------------------------------------------------------------------------
GEN_UPDT_FOR_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic; -- xfer'ed bytes fifo reset
signal xb_fifo_full : std_logic; -- xfer'ed bytes fifo full
begin
-----------------------------------------------------------------------
-- Need to flag a pending pointer update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
mm2s_pending_ptr_updt <= '0';
elsif (desc_fetch_done_i = '1') then --(mm2s_new_curdesc_wren_i = '1')then
mm2s_pending_ptr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pointer pending update or xferred bytes fifo full
mm2s_pending_update <= mm2s_pending_ptr_updt or xb_fifo_full;
updt_pending <= mm2s_pending_update;
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
mm2s_xferd_bytes <= (others => '0');
xb_fifo_full <= '0';
end generate GEN_MICRO_DMA;
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => desc_fetch_done_i, --mm2s_new_curdesc_wren_i ,
Data_In => mm2s_desc_blength_i ,
FIFO_Read => sts_received_re ,
Data_Out => mm2s_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
end generate GEN_NO_MICRO_DMA;
xb_fifo_reset <= not m_axi_sg_aresetn;
-- clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
mm2s_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= mm2s_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= mm2s_sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_QUEUE;
---------------------------------------------------------------------------
-- If no queue in sg engine then do not need to instantiate a
-- fifo to hold buffer lengths. Also do not need to hold off
-- fetch based on if status has been updated or not because
-- descriptors are only processed one at a time
---------------------------------------------------------------------------
GEN_UPDT_FOR_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
mm2s_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
mm2s_pending_update <= '0'; -- Not needed for the No Queue configuration
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_xferd_bytes <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
mm2s_xferd_bytes <= mm2s_desc_blength_i;
end if;
end if;
end process REG_XFERRED_BYTES;
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= mm2s_done or mm2s_interr or mm2s_decerr or mm2s_slverr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_NO_QUEUE;
-----------------------------------------------------------------------
-- Receive Status SG Update Logic
-----------------------------------------------------------------------
-- clear flag when updating status and see a tlast and target
-- (i.e. sg engine) is ready
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tlast = '1'
and updtsts_tvalid = '1'
and s_axis_mm2s_updtsts_tready = '1'
else '0';
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done
-- or datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- -- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg2 <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_reg2 <= DESC_LAST
& mm2s_tag(DATAMOVER_STS_TAGLSB_BIT) -- Desc_IOC
& mm2s_complete
& mm2s_decerr
& mm2s_slverr
& mm2s_interr
& RESERVED_STS
& mm2s_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
updtsts_tdata <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- MSB asserts last on last word of update stream
updtsts_tlast <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive tvalid
updtsts_tvalid <= updt_sts;
-- Drive update done to mm2s sm for the no queue case to indicate
-- readyd to fetch next descriptor
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
-- Update Pointer Stream
s_axis_mm2s_updtptr_tvalid <= updtptr_tvalid;
s_axis_mm2s_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_mm2s_updtptr_tdata <= updtptr_tdata ;
-- Update Status Stream
s_axis_mm2s_updtsts_tvalid <= updtsts_tvalid;
s_axis_mm2s_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
s_axis_mm2s_updtsts_tdata <= updtsts_tdata ;
-----------------------------------------------------------------------
end implementation;
| mit | 193223305c2a0492ff2cc1ee5ff2628b | 0.468132 | 4.031044 | false | false | false | false |
fumyuun/tasty | src/tasty.vhd | 1 | 1,934 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.snes_lib.all;
entity tasty_snes is
port (
clk_i : in std_logic;
rst_i : in std_logic;
snes_js_btn_i : in snes_js_btn_r;
snes_js_bus_i : in snes_js_bus_i_r;
snes_js_bus_o : out snes_js_bus_o_r;
-- debug
debug_enabled_i : in std_logic; -- enable the buttons on the board
switch_i : in std_logic_vector(15 downto 0);
clock_indicator_o : out std_logic;
latch_indicator_o : out std_logic;
btn_indicator_o : out snes_js_btn_r;
pc_o : out std_logic_vector(15 downto 0)
);
end entity tasty_snes;
architecture behavioral of tasty_snes is
signal debug_js_inputs_s : snes_js_btn_r;
signal generated_js_inputs_s : snes_js_btn_r;
signal selected_js_inputs_s : snes_js_btn_r;
signal ctrl_pause_s : std_logic; -- controller is not done yet issuing current inputs
signal generator_pause_s : std_logic; -- goes to generator
begin
debug_js_inputs_s <= snes_js_btn_i;
selected_js_inputs_s <= debug_js_inputs_s when debug_enabled_i = '1'
else generated_js_inputs_s;
btn_indicator_o <= selected_js_inputs_s;
generator_pause_s <= '1' when debug_enabled_i = '1' or ctrl_pause_s = '1' else '0';
snes_btn_ctrl0: entity work.snes_btn_ctrl
port map (
clk_i => clk_i,
snes_js_btn_i => selected_js_inputs_s,
snes_js_bus_i => snes_js_bus_i,
snes_js_bus_o => snes_js_bus_o,
clock_indicator_o => clock_indicator_o,
latch_indicator_o => latch_indicator_o,
pause_o => ctrl_pause_s
);
js_generator0: entity work.js_generator
port map (
clk_i => clk_i,
rst_i => rst_i,
pause_i => generator_pause_s,
js_o => generated_js_inputs_s,
pc_o => pc_o
);
end;
| mit | 39dc44fef4c88453ad142162ad1baed8 | 0.579628 | 3.050473 | false | false | false | false |
nickdesaulniers/Omicron | instr_mem/inst_mem.vhd | 1 | 4,955 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file inst_mem.vhd when simulating
-- the core, inst_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY inst_mem IS
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(6 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END inst_mem;
ARCHITECTURE inst_mem_a OF inst_mem IS
-- synthesis translate_off
component wrapped_inst_mem
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(6 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_inst_mem use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 3,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3e",
c_write_depth_b => 128,
c_write_depth_a => 128,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 7,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 7,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 128,
c_read_depth_a => 128,
c_byte_size => 9,
c_sim_collision_check => "NONE",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_inst_mem
port map (
clka => clka,
addra => addra,
douta => douta);
-- synthesis translate_on
END inst_mem_a;
| gpl-3.0 | 7496d708cad8d13e17c45537d30a110d | 0.55217 | 3.71161 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.vhd | 3 | 11,907 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg;
| bsd-3-clause | c0ae52362a8655c061513a161012d827 | 0.515411 | 3.852151 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.vhd | 3 | 11,785 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg;
PACKAGE BODY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg;
| bsd-3-clause | 14cc9168f06b3c003efd022256c77898 | 0.519813 | 3.87537 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/hdl/triangle_intersect_wrapper.vhd | 1 | 3,551 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
--Date : Sun May 08 18:17:54 2016
--Host : Win10Desktop running 64-bit major release (build 9200)
--Command : generate_target triangle_intersect_wrapper.bd
--Design : triangle_intersect_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity triangle_intersect_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end triangle_intersect_wrapper;
architecture STRUCTURE of triangle_intersect_wrapper is
component triangle_intersect is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component triangle_intersect;
begin
triangle_intersect_i: component triangle_intersect
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
| mit | b38019a5d832ad8d80564bd20aef44f9 | 0.599549 | 3.156444 | false | false | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/axi_utils_v2_0/hdl/axi_utils_v2_0_vh_rfs.vhd | 9 | 291,505 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214048)
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| mit | b6e9264f686bb9b6fdf9546e77034077 | 0.954831 | 1.826724 | false | false | false | false |
alemedeiros/flappy_vhdl | obstacles/obst_regbank.vhd | 1 | 2,912 | -- file: obstacles/obst_regbank.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Set of n registers to save the obstacles positions (2 integers for each
-- obstacle), when an obstacle reaches the horizontal position 0, it is
-- automatically discarded and a new one is read from in_{low,high}.
library ieee ;
use ieee.std_logic_1164.all ;
entity obst_regbank is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
-- New obstacles input
in_low : in integer range 0 to V_RES - 1 ;
in_high : in integer range 0 to V_RES - 1 ;
up_clk : in std_logic ; -- Update clock
-- Read current values
id : in integer range 0 to N_OBST - 1 ;
low : out integer range 0 to V_RES - 1 ;
high : out integer range 0 to V_RES - 1 ;
pos : out integer range 0 to H_RES / N_OBST - 1 ;
f_low : out integer range 0 to V_RES - 1 ;
f_high : out integer range 0 to V_RES - 1 ;
-- Control signal
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic ;
obst_rem : out std_logic
) ;
end obst_regbank ;
architecture behavior of obst_regbank is
-- Declare a array type for the obstacles
type obst_t is array (0 to N_OBST - 1) of integer range 0 to V_RES - 1 ;
-- Obstacles array
signal obst_low : obst_t ;
signal obst_high : obst_t ;
signal updating : std_logic ;
signal tmp_pos : integer range 0 to H_RES / N_OBST - 1 := H_RES / N_OBST - 1 ;
signal tmp_obst_rem : std_logic ;
begin
-- Reading values process
process(clock)
begin
if rising_edge(clock) and updating = '0' then
low <= obst_low(id) ;
high <= obst_high(id) ;
f_low <= obst_low(0) ;
f_high <= obst_high(0) ;
pos <= tmp_pos ;
if tmp_pos = 0 then
obst_rem <= '1' ;
else
obst_rem <= '0' ;
end if ;
end if ;
end process ;
-- Update obstacle values
process(up_clk, reset, enable)
begin
if reset = '1' then
updating <= '1' ;
-- Reset
tmp_pos <= 0 ; -- H_RES / N_OBST - 1 ;
for i in 0 to N_OBST - 1 loop
obst_low(i) <= 0 ;
obst_high(i) <= 0 ;
end loop ;
updating <= '0' ;
elsif rising_edge(up_clk) and enable = '1' then
updating <= '1' ;
if tmp_pos = 0 then
-- Shift obstacles and read next obstacle
tmp_obst_rem <= '1' ;
tmp_pos <= H_RES / N_OBST - 1 ;
for i in 1 to N_OBST - 1 loop
obst_low(i-1) <= obst_low(i) ;
obst_high(i-1) <= obst_high(i) ;
end loop ;
obst_low(N_OBST - 1) <= in_low ;
obst_high(N_OBST - 1) <= in_high ;
else
tmp_obst_rem <= '0' ;
tmp_pos <= tmp_pos - 1 ;
end if ;
updating <= '0' ;
end if ;
end process ;
end behavior ;
| bsd-3-clause | 6c2e5022455b92c9f272a6ef9e8f1f9f | 0.583448 | 2.95935 | false | false | false | false |
alemedeiros/flappy_vhdl | output/frame_builder.vhd | 1 | 1,895 | -- file: output/draw_frame.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Generate a frame from the current game state.
library ieee ;
use ieee.std_logic_1164.all ;
entity frame_builder is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 ; -- Number of obstacles
P_POS : natural := 20 -- Player Horizontal position
) ;
port (
-- Game state data.
player : in integer range 0 to V_RES - 1 ;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
obst_pos : in integer range 0 to H_RES / N_OBST - 1;
obst_id : out integer range 0 to N_OBST - 1 ;
lin : in integer range 0 to V_RES - 1 ;
col : in integer range 0 to H_RES - 1 ;
enable : in std_logic ;
colour : out std_logic_vector(2 downto 0)
) ;
end frame_builder ;
architecture behavior of frame_builder is
signal c : std_logic_vector(2 downto 0) ;
signal id : integer range 0 to N_OBST - 1 ;
begin
-- Process that determines the colour of each pixel.
process(lin, col)
variable curr_id : integer range 0 to N_OBST - 1 ;
begin
-- Background colour is black
c <= "000" ;
-- Determine current obstacle.
curr_id := col / (H_RES / N_OBST) ;
id <= curr_id ;
if lin = player and col = P_POS then -- Player colour
c <= "110" ;
elsif col = curr_id * (H_RES / N_OBST) + obst_pos then -- Obstacles colour
if lin < obst_high then -- Top obstacle
c <= "010" ;
elsif lin > (V_RES - 1) - obst_low then -- Bottom obstacle
c <= "010" ;
end if ;
end if ;
end process ;
colour <= c when enable = '1' else "ZZZ" ;
obst_id <= id when enable = '1' else 0 ;
end behavior ;
| bsd-3-clause | ebf55c31509b1f21f718994992709f7b | 0.606332 | 3.17953 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/example_design/system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes.vhd | 3 | 5,702 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_1_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_1 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(34-1 DOWNTO 0);
DOUT : OUT std_logic_vector(34-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-3-clause | 6979c418c037730d2427fb8edb33ce2f | 0.527008 | 4.539809 | false | false | false | false |
kennethlyn/parallella-lcd-fpga | system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_1/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl.vhd | 3 | 18,499 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_1_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_1_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:system_axi_vdma_0_wrapper_fifo_generator_v9_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| bsd-3-clause | 3338f7501cbbe305edfa40436bb93534 | 0.51246 | 3.237487 | false | false | false | false |
alemedeiros/flappy_vhdl | control/game_control.vhd | 1 | 3,155 | -- file: control/game_control.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Main game Finite State machine.
library ieee ;
use ieee.std_logic_1164.all ;
entity game_control is
port (
game_over : in std_logic ;
reset : in std_logic ;
pause : in std_logic ;
jump : in std_logic ;
clock : in std_logic ;
obst_rem : in std_logic ;
new_obst : out std_logic ;
timer : in std_logic ;
-- Enable signals for each module.
calculate_speed : out std_logic ;
calculate_position : out std_logic ;
obst_regbank : out std_logic ;
update_obstacles : out std_logic ;
colision_detection : out std_logic ;
draw_frame : out std_logic ;
ledcon : out std_logic ;
internal_reset : out std_logic
) ;
end game_control ;
architecture behavior of game_control is
-- State type
type state_t is (start, update, draw, loser) ;
signal state : state_t := start ;
signal next_state : state_t := start ;
begin
process (reset, clock) --clock)
variable count : integer ;
begin
if reset = '1' then
internal_reset <= '1' ;
state <= start ;
elsif rising_edge(clock) then
case state is
when start =>
state <= update ;
calculate_speed <= '0' ;
calculate_position <= '0' ;
obst_regbank <= '0' ;
update_obstacles <= '0' ;
new_obst <= '0' ;
colision_detection <= '0' ;
draw_frame <= '0' ;
ledcon <= '0' ;
internal_reset <= '1' ;
when update =>
if game_over = '1' then
state <= loser ;
elsif pause = '1' then
state <= draw ;
else
state <= update ;
end if ;
--state <= draw ;
calculate_speed <= '1' ;
calculate_position <= '1' ;
obst_regbank <= '1' ;
update_obstacles <= '1' ;
new_obst <= '0' ; -- CHECK
colision_detection <= '1' ;
draw_frame <= '1' ;
ledcon <= '0' ;
internal_reset <= '0' ;
when draw =>
if game_over = '1' then
state <= loser ;
elsif pause = '1' then
state <= draw ;
else
state <= update ;
end if ;
calculate_speed <= '0' ;
calculate_position <= '0' ;
obst_regbank <= '0' ;
update_obstacles <= '0' ;
new_obst <= '0' ;
colision_detection <= '1' ;
draw_frame <= '1' ;
ledcon <= '1' ;
internal_reset <= '0' ;
when loser =>
state <= loser ;
calculate_speed <= '0' ;
calculate_position <= '0' ;
obst_regbank <= '0' ;
update_obstacles <= '0' ;
new_obst <= '0' ;
colision_detection <= '0' ;
draw_frame <= '1' ;
ledcon <= '1' ;
internal_reset <= '0' ;
when others =>
state <= start ;
end case ;
end if ;
end process ;
end behavior ;
| bsd-3-clause | 71de058fed827bdfc53a029947c1841c | 0.490967 | 3.342161 | false | false | false | false |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd | 1 | 50,576 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA S2MM
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
-- MM2S Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ;
s2mm_halted : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_ftch_err_early : in std_logic ; --
s2mm_ftch_stale_desc : in std_logic ; --
s2mm_halt : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_packet_eof_out : out std_logic ;
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic ; --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
s2mm_stop : out std_logic ; --
s2mm_desc_flush : out std_logic ; --
s2mm_all_idle : out std_logic ; --
s2mm_error : out std_logic ; --
mm2s_error : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
-- Simple DMA Mode Signals
s2mm_da : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : in std_logic ; --
s2mm_smple_done : out std_logic ; --
s2mm_interr_set : out std_logic ; --
s2mm_slverr_set : out std_logic ; --
s2mm_decerr_set : out std_logic ; --
s2mm_bytes_rcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : out std_logic ; --
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); --
s2mm_err : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : in std_logic ; --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal s2mm_cmnd_wr : std_logic := '0';
signal s2mm_cmnd_data : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s2mm_cmnd_pending : std_logic := '0';
attribute mark_debug of s2mm_cmnd_wr : signal is "true";
attribute mark_debug of s2mm_cmnd_data : signal is "true";
-- Primary DataMover Status signals
signal s2mm_done : std_logic := '0';
signal s2mm_stop_i : std_logic := '0';
signal s2mm_interr : std_logic := '0';
signal s2mm_slverr : std_logic := '0';
signal s2mm_decerr : std_logic := '0';
attribute mark_debug of s2mm_interr : signal is "true";
attribute mark_debug of s2mm_slverr : signal is "true";
attribute mark_debug of s2mm_decerr : signal is "true";
signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0');
signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal dma_s2mm_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal s2mm_error_i : std_logic := '0';
signal sts_strm_stop : std_logic := '0';
signal s2mm_halted_set_i : std_logic := '0';
signal s2mm_sts_received_clr : std_logic := '0';
signal s2mm_sts_received : std_logic := '0';
signal s2mm_cmnd_idle : std_logic := '0';
signal s2mm_sts_idle : std_logic := '0';
signal s2mm_eof_set : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_info : std_logic_vector(31 downto 0) := (others => '0');
signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_cmplt : std_logic := '0';
signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
-- S2MM Status Stream Signals
signal s2mm_rxlength_valid : std_logic := '0';
signal s2mm_rxlength_clr : std_logic := '0';
signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal stsstrm_fifo_rden : std_logic := '0';
signal stsstrm_fifo_empty : std_logic := '0';
signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal s2mm_desc_flush_i : std_logic := '0';
signal updt_pending : std_logic := '0';
signal s2mm_cmnd_wr_1 : std_logic := '0';
signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include S2MM (Received) Channel
-------------------------------------------------------------------------------
GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate
begin
-- pass out to register module
s2mm_halted_set <= s2mm_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM
or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down mm2s
s2mm_error <= s2mm_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- s2mm_stop_i <= s2mm_error -- Error
-- or soft_reset; -- Soft Reset issued
s2mm_stop_i <= s2mm_error_i -- Error on s2mm
or mm2s_error -- Error on mm2s
or soft_reset; -- Soft Reset issued
-- Register signals out
REG_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop <= '0';
s2mm_desc_flush_i <= '0';
else
s2mm_stop <= s2mm_stop_i;
-- Flush any fetch descriptors if error or if run stop cleared
s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop;
end if;
end if;
end process REG_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not used in Scatter Gather mode
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
-- Flush descriptors
s2mm_desc_flush <= s2mm_desc_flush_i;
OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_cmnd_wr <= s2mm_cmnd_wr_1;
end generate OLD_CMD_WR;
NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
begin
s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new;
end generate NEW_CMD_WR;
---------------------------------------------------------------------------
-- S2MM Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_S2MM_SM : entity axi_dma_v7_1.axi_dma_s2mm_sm
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_stop => s2mm_stop_i ,
-- Channel 1 Control and Status
s2mm_run_stop => s2mm_run_stop ,
s2mm_keyhole => s2mm_keyhole ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_desc_flush => s2mm_desc_flush_i ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Status Stream RX Length
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
desc_available => desc_available ,
-- DataMover Command
s2mm_cmnd_wr => s2mm_cmnd_wr_1 ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
-- Descriptor Fields
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_blength => s2mm_desc_blength,
s2mm_desc_blength_v => s2mm_desc_blength_v,
s2mm_desc_blength_s => s2mm_desc_blength_s
);
---------------------------------------------------------------------------
-- S2MM Scatter Gather State Machine
---------------------------------------------------------------------------
I_S2MM_SG_IF : entity axi_dma_v7_1.axi_dma_s2mm_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
-- S2MM Status Stream Interface
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data (
((1+C_ENABLE_MULTI_CHANNEL)*
C_M_AXI_S2MM_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- S2MM Descriptor Update Request (from s2mm_sm)
desc_update_done => desc_update_done ,
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
s2mm_done => s2mm_done ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag ,
s2mm_brcvd => s2mm_brcvd ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_packet_eof => s2mm_packet_eof ,
s2mm_halt => s2mm_halt ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Descriptor Field Output
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_blength => s2mm_desc_blength ,
s2mm_desc_blength_v => s2mm_desc_blength_v ,
s2mm_desc_blength_s => s2mm_desc_blength_s ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_app0 => s2mm_desc_app0 ,
s2mm_desc_app1 => s2mm_desc_app1 ,
s2mm_desc_app2 => s2mm_desc_app2 ,
s2mm_desc_app3 => s2mm_desc_app3 ,
s2mm_desc_app4 => s2mm_desc_app4
);
end generate GEN_SCATTER_GATHER_MODE;
s2mm_packet_eof_out <= s2mm_packet_eof;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
s2mm_desc_flush <= '0';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others => '0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others => '0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
desc_fetch_req <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
desc_update_done <= '0';
s2mm_rxlength_clr <= '0';
stsstrm_fifo_rden <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_desc_baddress <= (others => '0');
s2mm_desc_info <= (others => '0');
s2mm_desc_blength <= (others => '0');
s2mm_desc_blength_v <= (others => '0');
s2mm_desc_blength_s <= (others => '0');
s2mm_desc_cmplt <= '0';
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-- Simple DMA State Machine
I_S2MM_SMPL_SM : entity axi_dma_v7_1.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => s2mm_run_stop ,
keyhole => s2mm_keyhole ,
stop => s2mm_stop_i ,
cmnd_idle => s2mm_cmnd_idle ,
sts_idle => s2mm_sts_idle ,
-- DataMover Status
sts_received => s2mm_sts_received ,
sts_received_clr => s2mm_sts_received_clr ,
-- DataMover Command
cmnd_wr => s2mm_cmnd_wr ,
cmnd_data => s2mm_cmnd_data ,
cmnd_pending => s2mm_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => s2mm_length_wren ,
xfer_address => s2mm_da ,
xfer_length => s2mm_length
);
-- Pass Done/Error Status out to DMASR
s2mm_interr_set <= s2mm_interr;
s2mm_slverr_set <= s2mm_slverr;
s2mm_decerr_set <= s2mm_decerr;
s2mm_bytes_rcvd <= s2mm_brcvd;
s2mm_bytes_rcvd_wren <= s2mm_done;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0'
-- Else halt set prior to halted being set
else s2mm_halted_set_i when s2mm_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- S2MM DataMover Command / Status Interface
-------------------------------------------------------------------------------
I_S2MM_CMDSTS : entity axi_dma_v7_1.axi_dma_s2mm_cmdsts_if
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_tailpntr_enble => s2mm_tailpntr_enble ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
-- S2MM Primary DataMover Status
s2mm_brcvd => s2mm_brcvd ,
s2mm_err => s2mm_err ,
s2mm_done => s2mm_done ,
s2mm_error => dma_s2mm_error ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_S2MM_STS_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
s2mm_run_stop => s2mm_run_stop ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
-- stop and halt control/status
s2mm_stop => s2mm_stop_i ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-- system state and control
s2mm_all_idle => s2mm_all_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set_i ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr
);
-- S2MM Status Stream Included
GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Status Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to sts strm
-- skid buffer.
sts_strm_stop <= s2mm_error_i -- Error
or soft_reset_re; -- Soft Reset issued
I_S2MM_STS_STREAM : entity axi_dma_v7_1.axi_dma_s2mm_sts_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
axi_prmry_aclk => axi_prmry_aclk ,
p_reset_n => p_reset_n ,
s2mm_stop => sts_strm_stop ,
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Stream to Memory Map Status Stream Interface ,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
end generate GEN_STS_STREAM;
-- S2MM Status Stream Not Included
GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
stsstrm_fifo_empty <= '1';
stsstrm_fifo_dout <= (others => '0');
s_axis_s2mm_sts_tready <= '0';
end generate GEN_NO_STS_STREAM;
end generate GEN_S2MM_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Do Not Include S2MM Channel
-------------------------------------------------------------------------------
GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate
begin
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others =>'0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others =>'0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
s2mm_new_curdesc <= (others =>'0');
s2mm_new_curdesc_wren <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others =>'0');
m_axis_s2mm_sts_tready <= '0';
s2mm_halted_clr <= '0';
s2mm_halted_set <= '0';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s_axis_s2mm_sts_tready <= '0';
s2mm_stop <= '0';
s2mm_desc_flush <= '0';
s2mm_all_idle <= '1';
s2mm_error <= '0'; -- CR#570587
s2mm_packet_eof_out <= '0';
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
end generate GEN_NO_S2MM_DMA_CONTROL;
end implementation;
| mit | 7221c50618c2f8423aaedf17866ae67c | 0.400743 | 4.334962 | false | false | false | false |
louis-bonicel/VHDL | Porte_AND/componant_2.vhd | 2 | 1,478 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:01 01/15/2015
-- Design Name:
-- Module Name: componant_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity componant_2 is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
rin : in STD_LOGIC;
rout : out STD_LOGIC;
s1 : out STD_LOGIC);
end componant_2;
architecture Behavioral of componant_2 is
component componant_1 is
Port ( e1 : in STD_LOGIC;
e2 : in STD_LOGIC;
s1 : out STD_LOGIC;
s2 : out STD_LOGIC);
end component;
signal n1, n2, n3 : std_logic;
begin
inst1 : componant_1 port map (e1=>a1,e2=>b1,s1=>n1,s2=>n2);
inst2 : componant_1 port map (e1=>n1,e2=>rin,s1=>s1,s2=>n3);
rout <= n2 or n3;
end Behavioral;
| gpl-2.0 | f2935e82f9938f2e13173b68f02bca87 | 0.539242 | 3.437209 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/unionntb.vhd | 1 | 2,205 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:59:24 12/02/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/jummmmmmmm/unionntb.vhd
-- Project Name: jummmmmmmm
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Union
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY unionntb IS
END unionntb;
ARCHITECTURE behavior OF unionntb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Union
PORT(
Clk : IN std_logic;
reset : IN std_logic;
Salidaunion : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal Salidaunion : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Union PORT MAP (
Clk => Clk,
reset => reset,
Salidaunion => Salidaunion
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 15 ns;
reset <= '0';
wait for 15 ns;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | a9696a2b9e02168d83b7a4b3a48cd12d | 0.597732 | 3.987342 | false | true | false | false |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fadd_7_full_dsp_32/sim/tri_intersect_ap_fadd_7_full_dsp_32.vhd | 1 | 10,722 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fadd_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fadd_7_full_dsp_32_arch OF tri_intersect_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fadd_7_full_dsp_32_arch;
| mit | 31a9a797169a7fb5372a3415dbe0cf00 | 0.632625 | 3.216922 | false | false | false | false |
Kalugy/Procesadorarquitectura | Segmentado/UnidadControl.vhd | 1 | 7,569 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:49:14 10/20/2017
-- Design Name:
-- Module Name: UnidadControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UnidadControl is
Port ( Op : in STD_LOGIC_VECTOR (1 downto 0);
Op2 : in STD_LOGIC_VECTOR (2 downto 0);
Op3 : in STD_LOGIC_VECTOR (5 downto 0);
icc: in STD_LOGIC_VECTOR (3 downto 0);
cond: in STD_LOGIC_VECTOR (3 downto 0);
rfDest : out STD_LOGIC;
Reset : in STD_LOGIC;
rfSource : out STD_LOGIC_VECTOR (1 downto 0);
wrEnMem : out STD_LOGIC;
wrEnRF : out STD_LOGIC;
pcSource : out STD_LOGIC_VECTOR (1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0));
end UnidadControl;
architecture Behavioral of UnidadControl is
begin
process(Op, Op2, Op3, icc, cond,Reset)
begin
wrEnMem <= '0';
rfDest <= '0';
if(Reset = '1')then
rfDest <= '0';
rfSource <= "00";
wrEnRF <= '0';
pcSource <= "10";
AluOp <= "111111";
elsif(op = "01")then --CALL
rfDest <= '1';
rfSource <= "10";
wrEnRF <= '1';
pcSource <= "00";
AluOp <= "111111";
else
if(Op = "00")then
if(Op2 = "010")then
case cond is
when "1000" => --ba
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
when "1001" => --bne
if(not(icc(2)) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0001" => --be
if(icc(2) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "1010" => --bg
if((not(icc(2) or (icc(3) xor icc(1)))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0010" => --ble
if((icc(2) or (icc(3) xor icc(1))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <="111111";
else
rfSource <="01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "1011" => --bge
if((not(icc(3) xor icc(1))) = '1')then --sacado de manual
rfSource <= "01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when "0011" => --bl
if((icc(3) xor icc(1)) = '1')then --sacado de manual
rfSource <="01";
wrEnRF <= '0';
pcSource <="01";
AluOp <= "111111";
else
rfSource <="01" ;
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end if;
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
else
if(Op2 = "100")then -- NOP
rfSource <= "01";
wrEnRF <= '1';--oleacaloquesabe
pcSource <="10";
AluOp <= "111111";
end if;
end if;
else
if(Op = "10")then
case Op3 is
when "000000" => --Add
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when "010000" => --Addcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010000";
when "001000" => --Addx
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "001000";
when "011000" => --Addxcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "011000";
when "000100" => --Sub
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000100";
when "010100" => --Subcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010100";
when "001100" => --Subx
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "001100";
when "011100" => --Subxcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "011100";
when "000001" => --And
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000001";
when "010001" => --Andcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010001";
when "000101" => --AndN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000101";
when "010101" => --AndNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010101";
when "000010" => --Or
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000010";
rfDest <= '0';
when "010010" => --Orcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010010";
when "000110" => --OrN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000110";
when "010110" => --OrNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010110";
when "000011" => --Xor
rfSource <= "01";
wrEnRF <='1' ;
pcSource <="10";
AluOp <= "000011";
when "010011" => --Xorcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010011";
when "111000" => -- JMPL
rfSource <= "10";
wrEnRF <= '1';
pcSource <="11";
AluOp <= "000000";
when "000111" => --XorN
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000111";
when "010111" => --XnorNcc
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "010111";
when "111100" => -- SAVE
rfSource <= "01";
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when "111101" => -- RESTORE
rfSource <= "01";
wrEnRF <='1';
pcSource <="10";
AluOp <= "000000";
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
else
if(op = "11")then
case op3 is
when "000100" => -- STORE
rfSource <= "01"; -- leer
wrEnMem <= '1';
wrEnRF <= '0';
pcSource <="10";
AluOp <= "000000";
when "000000" => -- LOAD
rfSource <= "00"; --guardar
wrEnRF <= '1';
pcSource <="10";
AluOp <= "000000";
when others =>
rfSource <= "01";
wrEnRF <= '0';
pcSource <="10";
AluOp <= "111111";
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 83a282f2f714d5faa94f85119d675ca6 | 0.442463 | 3.350598 | false | false | false | false |
loetlab-jena/das-atv | hdl/src/rgb2yuv.vhd | 1 | 3,834 | -- RGB2YUV
-- transforms RGB to YUV
-- Y = 0.299 * R + 0.587 * G + 0.114 * B
-- U = 0.492 * (B - Y) = 0.436 * B - 0.147 * R + 0.289 * G
-- V = 0.877 * (R - Y) = 0.615 * R - 0.515 * G + 0.100 * B
--
-- delay: 2 clk cycles
--
-- file: rgb2yuv.vhd
-- author: Sebastian Weiss <[email protected]>
-- version: 0.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity rgb2yuv is
generic(
width : positive;
resolution : positive
);
port (
clk : in std_logic;
red : in std_logic_vector(width-1 downto 0);
green : in std_logic_vector(width-1 downto 0);
blue : in std_logic_vector(width-1 downto 0);
y : out std_logic_vector(width-1 downto 0);
u : out std_logic_vector(width-1 downto 0);
v : out std_logic_vector(width-1 downto 0)
);
end entity rgb2yuv;
architecture behavioral of rgb2yuv is
constant exp_width : integer := width+resolution;
signal RsY : unsigned(exp_width-1 downto 0);
signal GsY : unsigned(exp_width-1 downto 0);
signal BsY : unsigned(exp_width-1 downto 0);
signal Ys : unsigned(exp_width-1 downto 0);
signal RsU : unsigned(exp_width-1 downto 0);
signal GsU : unsigned(exp_width-1 downto 0);
signal BsU : unsigned(exp_width-1 downto 0);
signal Us : unsigned(exp_width-1 downto 0);
signal RsV : unsigned(exp_width-1 downto 0);
signal GsV : unsigned(exp_width-1 downto 0);
signal BsV : unsigned(exp_width-1 downto 0);
signal Vs : unsigned(exp_width-1 downto 0);
alias RY is RsY(exp_width-1 downto resolution);
alias GY is GsY(exp_width-1 downto resolution);
alias BY is BsY(exp_width-1 downto resolution);
alias Yrs is Ys(exp_width-1 downto resolution);
alias RU is RsU(exp_width-1 downto resolution);
alias GU is GsU(exp_width-1 downto resolution);
alias BU is BsU(exp_width-1 downto resolution);
alias Urs is Us(exp_width-1 downto resolution);
alias RV is RsV(exp_width-1 downto resolution);
alias GV is GsV(exp_width-1 downto resolution);
alias BV is BsV(exp_width-1 downto resolution);
alias Vrs is Vs(exp_width-1 downto resolution);
constant CrY : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.299 * real(2**resolution))),resolution);
constant CgY : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.587 * real(2**resolution))),resolution);
constant CbY : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.114 * real(2**resolution))),resolution);
constant CrU : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.147 * real(2**resolution))),resolution);
constant CgU : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.289 * real(2**resolution))),resolution);
constant CbU : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.436 * real(2**resolution))),resolution);
constant CrV : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.615 * real(2**resolution))),resolution);
constant CgV : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.515 * real(2**resolution))),resolution);
constant CbV : unsigned(resolution-1 downto 0) :=
to_unsigned(integer(round(0.100 * real(2**resolution))),resolution);
begin
process
begin
wait until rising_edge(clk);
RsY <= unsigned(red) * CrY;
GsY <= unsigned(green) * CgY;
BsY <= unsigned(blue) * CbY;
Ys <= RsY + GsY + BsY;
RsU <= unsigned(red) * CrU;
GsU <= unsigned(green) * CgU;
BsU <= unsigned(blue) * CbU;
Us <= BsU - GsU - RsU;
RsV <= unsigned(red) * CrV;
GsV <= unsigned(green) * CgV;
BsV <= unsigned(blue) * CbV;
Vs <= RsV - GsV - BsV;
if (GsU + RsU > BsU) then
Us <= (others => '0');
end if;
if (GsV + BsV > RsV) then
Vs <= (others => '0');
end if;
end process;
y <= std_logic_vector(Yrs);
u <= std_logic_vector(Urs);
v <= std_logic_vector(Vrs);
end architecture behavioral;
| gpl-2.0 | 107af1dafb887450cd5f4e2e827ffc3e | 0.67397 | 2.800584 | false | false | false | false |
Subsets and Splits