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gau-veldt/InsideTheBox | Progress_2017_12_21/c64.vhd | 3 | 20,988 | ----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library c64roms;
use c64roms.p_char_rom.all;
entity c64 is
port (
clk_125 : in std_logic;
-- audio configure
ac_scl : inout std_logic;
ac_sda : inout std_logic;
-- audio signal
ac_muten : out std_logic;
ac_mclk : out std_logic;
ac_bclk : out std_logic;
ac_pbdat : out std_logic;
ac_pblrc : out std_logic;
ac_recdat : in std_logic;
ac_reclrc : in std_logic;
-- report error in configuring audio
led : out std_logic_vector(3 downto 0);
-- to test waveforms
sw : in std_logic_vector(3 downto 0);
-- for freq/wvfm ramping tests
btn : in std_logic_vector(3 downto 0);
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end c64;
architecture c64_guts of c64 is
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv5 is std_logic_vector(4 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype slv7 is std_logic_vector(6 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype slv10 is std_logic_vector(9 downto 0);
subtype slv14 is std_logic_vector(13 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype s16 is signed(15 downto 0);
subtype slv20 is std_logic_vector(19 downto 0);
subtype slv24 is std_logic_vector(23 downto 0);
--
-- Master reset
--
signal res0 : std_logic;
signal res1 : std_logic; -- inverted slave of res0
--
-- Clocks,
-- timing signals,
-- and phase generators
--
-- VIC/CPU clock:
component clk_wiz_0
port
(-- output clock(s)
clk160 : out std_logic;
-- control signals
reset : in std_logic;
locked : out std_logic;
-- input clock(s)
clk_in1 : in std_logic
);
end component;
-- SSM2603 I2S audio clock:
component clk_wiz_1
port
(-- output clock(s)
clk12 : out std_logic;
-- control signals
reset : in std_logic;
locked : out std_logic;
-- input clock(s)
clk_in1 : in std_logic
);
end component;
signal clk12 : std_logic;
signal clk160 : std_logic;
signal clk_lk1 : std_logic;
signal clk_lk2 : std_logic;
signal clk20_ph1 : std_logic;
signal clk20_ph2 : std_logic;
-- 3-bit counter for dividing 160 MHz
-- into 8 20 MHz phases
signal clk20_ph : slv3;
function c20_next(src: slv3) return slv3 is
begin
case src is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end c20_next;
--
-- Memory units and control signals
--
-- 64k x 8 main system RAM:
component blk_ram_64k
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
signal ramen : std_logic := '1';
signal ramdr : byte;
signal ramdw : byte;
signal ram_r1w0 : std_logic := '1';
signal ram_r0w1 : std_logic; -- inverted slave of ram_r1w0
-- 1k x 4 color RAM
component blk_cram
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
signal cramen : std_logic := '1';
signal cramdr : nybble;
signal cramdw : nybble;
signal cram_r1w0 : std_logic := '1';
signal cram_r0w1 : std_logic; -- inverted slave of cram_r1w0
signal ram_clk : std_logic;
signal rama : word;
--
-- Memory addressing
--
signal bankctl : slv5 := "11111";
alias exrom : std_logic is bankctl(4);
alias game : std_logic is bankctl(3);
alias charen : std_logic is bankctl(2);
alias hiram : std_logic is bankctl(1);
alias loram : std_logic is bankctl(0);
type mbank_t is (
mbk_ram,
mbk_cram,
mbk_lorom,
mbk_hirom,
mbk_xio2,
mbk_xio1,
mbk_cia2,
mbk_cia1,
mbk_cgrom,
mbk_sid,
mbk_vic
);
signal bank_sel : mbank_t;
function cpu_bank(addr: u16; bsel: slv5) return mbank_t is
variable b3 : slv3;
variable bb0 : std_logic;
variable ce : std_logic;
variable n3 : nybble;
begin
b3 := bsel(2 downto 0);
bb0 := bsel(1) nor bsel(0);
ce := bsel(2);
n3 := nybble(addr(11 downto 8));
if (addr >= x"e000") then
if (bsel(1)='1') then
return mbk_hirom;
else
return mbk_ram;
end if;
elsif (addr >= x"d000" and addr < x"e000") then
if (bb0 = '1') then
return mbk_ram;
else
if (ce = '0') then
return mbk_cgrom;
else
case n3 is
when x"f" =>
return mbk_xio2;
when x"e" =>
return mbk_xio1;
when x"d" =>
return mbk_cia2;
when x"c" =>
return mbk_cia1;
when x"b" =>
return mbk_cram;
when x"a" =>
return mbk_cram;
when x"9" =>
return mbk_cram;
when x"8" =>
return mbk_cram;
when x"7" =>
return mbk_sid;
when x"6" =>
return mbk_sid;
when x"5" =>
return mbk_sid;
when x"4" =>
return mbk_sid;
when x"3" =>
return mbk_vic;
when x"2" =>
return mbk_vic;
when x"1" =>
return mbk_vic;
when x"0" =>
return mbk_vic;
when others =>
return mbk_ram;
end case;
end if;
end if;
elsif (addr >= x"a000" and addr < x"c000") then
if ((bsel(1) and bsel(0)) = '1') then
return mbk_lorom;
else
return mbk_ram;
end if;
else
return mbk_ram;
end if;
end cpu_bank;
--
-- Determine when writes should write to RAM
--
-- Includes any banking configurations that would
-- read RAM or ROM and excludes any that access I/O.
--
signal bank_wt : std_logic;
function bank_is_writethru(addr:word; bsel:slv5) return std_logic is
begin
case cpu_bank(u16(addr),bsel) is
when mbk_ram => return '1';
when mbk_cram => return '1';
when mbk_lorom => return '1';
when mbk_hirom => return '1';
when mbk_cgrom => return '1';
when others => return '0';
end case;
end bank_is_writethru;
--
-- 6510 processor (CPU)
--
component chip6502 is
port (
a : out word;
di : in byte;
do : out byte;
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end component;
signal cpu_nmi0 : std_logic:='1';
signal cpu_irq0 : std_logic:='1';
signal cpu_rdy : std_logic:='1';
signal cpu_so0 : std_logic:='1';
signal cpu_r1w0 : std_logic;
signal cpu_r0w1 : std_logic; -- inverted slave of cpu_r1w0
signal cpu_ph1 : std_logic;
signal cpu_ph2 : std_logic;
signal abus : word;
signal cpu_ioi : byte;
signal cpu_ioo : byte;
signal cpudo : byte;
signal cpudi : byte;
signal cpu_on : std_logic; -- inverted slave of vic_on
signal cpu_ph4x : std_logic;
--
-- Video
--
component vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end component;
signal vbank : pair := "00";
signal vic_rga : slv6;
signal vic_regw : byte;
signal vic_regr : byte;
signal vic_r1w0 : std_logic := '1'; -- write to VIC register
signal vic_va : slv14;
signal vic_cd : nybble;
signal vic_vd : byte;
signal vic_on : std_logic;
signal cgaddr : slv12;
signal cgdata : byte;
--
-- Audio path (SID/SSM2603)
--
-- Initialization data for SSM2603:
function dac_init(lin : ubyte) return slv20 is
begin
case lin is
when x"00" => return x"06" & x"010";
when x"01" => return x"02" & x"175";
when x"02" => return x"04" & x"010";
when x"03" => return x"05" & x"000";
when x"04" => return x"07" & x"000";
when x"05" => return x"09" & x"001";
when x"06" => return x"06" & x"000";
when others => return x"ff" & x"fff";
end case;
end dac_init;
-- I2C xcvr to send initialization data:
component i2c_xcvr port
(
-- with 1 MHz clock SSM2603 reg 9 delay step is 65.535 ms:
clk1M : in std_logic;
-- tie to system reset
res0 : in std_logic;
-- initialization line number
init_line : out unsigned(7 downto 0);
-- initialization data xRRRRRRRxxxxxxxDDDDDDDDD
init_data : in std_logic_vector(19 downto 0);
-- error status
error : out std_logic;
-- tie directly to ac_scl and ac_sda accordingly:
scl : inout std_logic;
sda : inout std_logic
);
end component;
signal ssm_init_line : ubyte;
signal ssm_init_data : slv20;
signal ssm_error : std_logic;
-- The 6581 SID chip:
component sid6581 is
port (
res0 : in std_logic;
ph2 : in std_logic;
rga : in std_logic_vector(4 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
s16audio : out signed(15 downto 0)
);
end component;
signal bclk_cnt : pair;
alias bclk_ref : std_logic is bclk_cnt(0);--1
signal audio_frame : unsigned(4 downto 0);
signal hold_sam : signed(15 downto 0);
signal sid1_rga : slv5;
signal sid1_dw : byte;
signal sid1_dr : byte;
signal sid1_out : s16;
signal sid1_r1w0 : std_logic;
--
-- When to map CGROM into VIC's address space:
--
function vbk_cgrom(bk: pair; adr: slv14) return std_logic is
variable vsel : slv3;
begin
vsel := bk(0) & adr(13 downto 12);
case vsel is
when "001" => return '1';
when others => return '0';
end case;
end vbk_cgrom;
--
-- For coldstart reset
--
subtype u12 is unsigned(11 downto 0);
signal reset_wait : u12 := x"000";
constant reset_delay : u12 := x"0fb"; -- number of 125 MHz clocks in 2000 ns
signal coldstart : std_logic;
--
-- Architectural implementation
--
begin
--
-- Coldstart reset for 2000 ns
--
initial_reset: process(clk_125, reset_wait) is -- counts up to 2000 ns
variable not_yet : boolean;
begin
not_yet := (reset_wait < reset_delay);
if rising_edge(clk_125) then
if not_yet then
reset_wait <= reset_wait + 1;
end if;
end if;
if not_yet then -- drive reset accordingly
coldstart <= '1';
else
coldstart <= '0';
end if;
end process initial_reset;
res0 <= coldstart nor btn(0);
pixclock: clk_wiz_0 port map (
-- Clock out ports
clk160 => clk160,
-- Status and control signals
reset => res1,
locked => clk_lk1,
-- Clock in ports
clk_in1 => clk_125
);
clk20gen: process(clk160) is
begin
if (rising_edge(clk160)) then
clk20_ph <= c20_next(clk20_ph);
end if;
end process clk20gen;
clk20_ph1 <= clk20_ph(2) and (clk20_ph(1) nor clk20_ph(0));
clk20_ph2 <= not (clk20_ph(2) or clk20_ph(1) or clk20_ph(0));
ram64: blk_ram_64k port map(
clka => ram_clk,
addra => rama,
dina => ramdw,
douta => ramdr,
wea(0) => ram_r0w1,
rsta => res1,
ena => ramen
);
color_ram: blk_cram port map(
clka => ram_clk,
addra => rama(9 downto 0),
dina => cramdw,
douta => cramdr,
wea(0) => cram_r0w1,
rsta => res1,
ena => cramen
);
res1 <= not res0;
cpu_r0w1 <= not cpu_r1w0;
ram_r0w1 <= not ram_r1w0;
cram_r0w1 <= not cram_r1w0;
bank_sel <= cpu_bank(u16(abus),bankctl);
bank_wt <= bank_is_writethru(abus,bankctl);
--
-- Determines character generator ROM source address
--
with cpu_on select cgaddr <=
abus(11 downto 0) when '1',
vic_va(11 downto 0) when others;
cgdata <= char_rom(cgaddr);
--
-- Determine write enables to RAMs
--
cram_wren: process(cpu_r1w0,cpu_on,bank_sel) is
begin
if (cpu_on='1' and bank_sel=mbk_cram) then
-- CPU only write to CRAM in CRAM bank
cram_r1w0 <= cpu_r1w0;
else
cram_r1w0 <= '1'; -- VIC never writes
end if;
end process cram_wren;
ram_wren: process(cpu_r1w0,cpu_on,bank_wt) is
begin
if (cpu_on='1' and bank_wt='1') then
-- writes to main RAM or write-thru ranges
ram_r1w0 <= cpu_r1w0;
else
ram_r1w0 <= '1'; -- VIC never writes
end if;
end process ram_wren;
-- Detemine write enable to VIC
vic_wren: process(cpu_r1w0,cpu_on,bank_sel) is
begin
if (cpu_on='1' and bank_sel=mbk_vic) then
vic_r1w0 <= cpu_r1w0;
else
vic_r1w0 <= '1';
end if;
end process vic_wren;
-- Detemine write enable to SID
sid1_wren: process(cpu_r1w0,cpu_on,bank_sel) is
begin
if (cpu_on='1' and bank_sel=mbk_sid) then
sid1_r1w0 <= cpu_r1w0;
else
sid1_r1w0 <= '1';
end if;
end process sid1_wren;
-- Only the CPU ever writes data
ramdw <= cpudo;
cramdw <= cpudo(3 downto 0);
--
-- Determine where the VIC reads from
--
vic_vd_sel: process(vbank,vic_va,cgdata,ramdr) is
begin
if (vbk_cgrom(vbank,vic_va) = '1') then
vic_vd <= cgdata;
else
vic_vd <= ramdr;
end if;
end process vic_vd_sel;
vic_cd <= cramdr; -- CRAM has no bank switching
--
-- Determine address given to RAMs
--
ram_a_sel: process(cpu_on,abus,vbank,vic_va) is
begin
if (cpu_on = '1') then
rama <= abus;
else
rama <= vbank & vic_va;
end if;
end process ram_a_sel;
-- For clocking RAM read/write cycles
with clk20_ph select ram_clk <=
'1' when "110",
'1' when "000",
'0' when others;
cpu: chip6502 port map (
nmi0 => cpu_nmi0,
irq0 => cpu_irq0,
so0 => '1',
rdy => '1',
a => abus,
do => cpudo,
di => cpudi,
r1w0 => cpu_r1w0,
pi => cpu_ioi,
po => cpu_ioo,
ph4Xin => cpu_ph4x,
res0 => res0
);
vic: vic_ii port map(
clk20_ph1 => clk20_ph1,
clk20_ph2 => clk20_ph2,
rga => vic_rga,
rgdi => vic_regw,
rgdo => vic_regr,
r1w0 => vic_r1w0,
cpu_clk => cpu_ph4x,
cpu_ben => cpu_on,
vic_ben => vic_on,
bus_ph1 => cpu_ph1,
bus_ph2 => cpu_ph2,
va => vic_va,
vd => vic_vd,
cd => vic_cd,
res0 => res0,
vhs => vga_hs,
vvs => vga_vs,
vr => vga_r,
vg => vga_g,
vb => vga_b
);
-- bank selection from CPU IO port
loram <= cpu_ioo(0);
hiram <= cpu_ioo(1);
charen <= cpu_ioo(2);
-- Connect data lines up
vic_regw <= cpudo;
sid1_dw <= cpudo;
-- Connect address lines
sid1_rga <= abus(4 downto 0);
vic_rga <= abus(5 downto 0);
-- Choose CPU data source (on reads)
with bank_sel select cpudi <=
ramdr when mbk_ram,
x"0" & cramdr when mbk_cram,
-- when mbk_lorom,
-- when mbk_hirom,
-- when mbk_xio2,
-- when mbk_xio1,
-- when mbk_cia2,
-- when mbk_cia1,
cgdata when mbk_cgrom,
vic_regr when mbk_sid,
sid1_dr when mbk_vic,
"ZZZZZZZZ" when others;
--
-- Audio section (including SID)
--
sndclock: clk_wiz_1 port map (
-- Clock out ports
clk12 => clk12,
-- Status and control signals
reset => res1,
locked => clk_lk2,
-- Clock in ports
clk_in1 => clk_125
);
sid_1: sid6581 port map (
res0 => res0,
ph2 => cpu_ph2,
rga => sid1_rga,
din => sid1_dw,
dout => sid1_dr,
r1w0 => sid1_r1w0,
s16audio => sid1_out
);
ac_muten <= res0;
ac_mclk <= clk12;
bclk_gen : process(clk12,bclk_cnt,res1) is
variable inc_0 : std_logic;
variable inc_1 : std_logic;
begin
inc_0 := not bclk_cnt(0);
inc_1 := bclk_cnt(1) xor bclk_cnt(0);
if (res1 = '1') then
bclk_cnt <= "00";
elsif (rising_edge(clk12)) then
bclk_cnt <= inc_1 & inc_0;
end if;
end process bclk_gen;
ac_bclk <= bclk_cnt(1);
audio_send : process(bclk_cnt,res1,hold_sam,sid1_out,audio_frame) is
variable apos : nybble;
begin
-- flipped frame index to send MSB first
apos := not nybble(audio_frame(3 downto 0));
if (res1 = '1') then
audio_frame <= "00000";
elsif (falling_edge(bclk_cnt(1))) then
if (audio_frame = "11111") then
hold_sam <= sid1_out;
end if;
ac_pbdat <= hold_sam(to_integer(unsigned(apos)));
ac_pblrc <= audio_frame(4);
audio_frame <= audio_frame + 1;
end if;
end process audio_send;
--
-- I2C config for SSM2603
--
i2c: component i2c_xcvr port map (
clk1M => cpu_ph2,
res0 => res0,
init_line => ssm_init_line,
init_data => ssm_init_data,
error => ssm_error,
scl => ac_scl,
sda => ac_sda
);
ssm_init_data <= dac_init(ssm_init_line);
led(0) <= ssm_error;
end c64_guts;
| gpl-3.0 | 08c73f434bb797e91268338ea96dd6e2 | 0.51377 | 3.251433 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/rtl/Eth1000BaseXRxSync.vhd | 1 | 5,537 | -------------------------------------------------------------------------------
-- Title : 1000 BASE X link initialization
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : Eth1000BaseXRxSync.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description:
-- Synchronization checker for 1000 BASE-X.
-------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
entity Eth1000BaseXRxSync is
generic (
GATE_DELAY_G : time := 1 ns;
PIPE_STAGES_G : integer range 1 to 8 := 2
);
port (
-- GT user clock and reset (62.5 MHz)
ethRx62Clk : in sl;
ethRx62Rst : in sl;
-- Local side has synchronization
rxLinkSync : out sl;
-- Incoming data from GT
phyRxData : in EthRxPhyLaneInType
);
end Eth1000BaseXRxSync;
-- Define architecture
architecture rtl of Eth1000BaseXRxSync is
-- LOS : loss of sync
-- CD : combined CommaDetect / AcquireSync state
-- SA : sync acquired state
type InitStateType is (S_LOS, S_CD, S_SA);
type PhyRxDataArray is array (PIPE_STAGES_G-1 downto 0) of EthRxPhyLaneInType;
type RegType is record
syncState : InitStateType;
rxDataPipe : PhyRxDataArray;
rxLinkSync : sl;
commaCnt : slv(1 downto 0);
cgGoodCnt : slv(1 downto 0);
cgBadCnt : slv(1 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
syncState => S_LOS,
rxDataPipe => (others => ETH_RX_PHY_LANE_IN_INIT_C),
rxLinkSync => '0',
commaCnt => (others => '0'),
cgGoodCnt => (others => '0'),
cgBadCnt => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,phyRxData,ethRx62Rst) is
variable v : RegType;
begin
v := r;
-- Pipeline for incoming data
for i in PIPE_STAGES_G-1 downto 0 loop
if (i /= 0) then
v.rxDataPipe(i) := v.rxDataPipe(i-1);
else
v.rxDataPipe(0) := phyRxData;
end if;
end loop;
-- Combinatorial state logic
case(r.syncState) is
-- Loss of Sync State
when S_LOS =>
v.rxLinkSync := '0';
v.commaCnt := (others => '0');
v.cgGoodCnt := (others => '0');
v.cgBadCnt := (others => '0');
if (r.rxDataPipe(PIPE_STAGES_G-1).dataK(0) = '1' and
r.rxDataPipe(PIPE_STAGES_G-1).data(7 downto 0) = K_COM_C) then
v.syncState := S_CD;
end if;
-- Comma detect state (should be aligned by GT to byte 0)
-- Sync success after 3 commas in the low byte without errors.
when S_CD =>
if (r.rxDataPipe(PIPE_STAGES_G-1).decErr /= "00" or
r.rxDataPipe(PIPE_STAGES_G-1).dispErr /= "00") then
v.syncState := S_LOS;
elsif (r.rxDataPipe(PIPE_STAGES_G-1).dataK(0) = '1' and
r.rxDataPipe(PIPE_STAGES_G-1).data(7 downto 0) = K_COM_C) then
v.commaCnt := r.commaCnt + 1;
if (r.commaCnt = "10") then
v.syncState := S_SA;
end if;
end if;
-- Sync acquired state
-- Monitor for: 1) cggood: valid data or a comma with rx false
-- 2) cgbad: !valid data or comma in wrong position
when S_SA =>
v.rxLinkSync := '1';
-- Bad code group conditions:
-- - decode error
-- - disparity error
-- - comma in wrong byte
if (r.rxDataPipe(PIPE_STAGES_G-1).decErr /= "00" or
r.rxDataPipe(PIPE_STAGES_G-1).dispErr /= "00" or
(r.rxDataPipe(PIPE_STAGES_G-1).dataK = "10" and
r.rxDataPipe(PIPE_STAGES_G-1).data(15 downto 8) = K_COM_C)) then
if (r.cgBadCnt = "11") then
v.syncState := S_LOS;
else
v.cgBadCnt := r.cgBadCnt + 1;
end if;
else
if (r.cgBadCnt > 0) then
if (r.cgGoodCnt = "11") then
v.cgBadCnt := r.cgBadCnt - 1;
v.cgGoodCnt := "00";
else
v.cgGoodCnt := r.cgGoodCnt + 1;
end if;
end if;
end if;
-- Others
when others =>
v.syncState := S_LOS;
end case;
if (ethRx62Rst = '1') then
v := REG_INIT_C;
end if;
rin <= v;
rxLinkSync <= r.rxLinkSync;
end process;
seq : process (ethRx62Clk) is
begin
if (rising_edge(ethRx62Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | e958775e666bebcc4796bf25b264a244 | 0.492866 | 3.974874 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/clockgen.vhd | 3 | 1,103 | ----------------------------------------------------------------------------------
--
-- Clock generation logic
--
-- Generates a phase 0 clock and non-overlapping
-- phase 1 and phase 2 clocks from a 4X input clock source
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clockgen is
port (
ph4Xin : in std_logic;
ph0 : out std_logic;
ph1 : out std_logic;
ph2 : out std_logic;
stg : out std_logic_vector(1 downto 0);
res0 : in std_logic
);
end clockgen;
architecture clock_impl of clockgen is
signal clkStg : std_logic_vector(1 downto 0) := "00";
begin
count: process(ph4Xin,res0) is
begin
if (res0 = '0') then
clkStg <= "01";
elsif (rising_edge(ph4xin)) then
clkStg <= ((clkStg(1) xor clkStg(0)) & (not clkStg(0)));
end if;
end process count;
ph0 <= clkStg(1);
ph1 <= clkStg(1) and (not clkStg(0));
ph2 <= not (clkStg(1) or clkStg(0));
stg <= clkStg;
end clock_impl;
| gpl-3.0 | 6b60737f2d70d8f8fed72bd6f256665d | 0.491387 | 3.640264 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/tb/CPU_tb.vhd | 1 | 4,789 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/13/2018 04:19:50 PM
-- Design Name:
-- Module Name: CPU_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU_tb is
-- Port ( );
end CPU_tb;
architecture Behavioral of CPU_tb is
component simpler_core is
Port(
status: out std_logic; -- LED blinkenlites
CLK: in std_logic; -- Tied to switch V10
RST: in std_logic; -- Tied to switch J15
LED: out std_logic_vector(15 downto 0);
PC_Switch: in std_logic;
-- UART Serial I/O
UART_RXD: in std_logic;
UART_TXD: out std_logic;
-- DDR2 signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
--pragma synthesis_off
address_out,instruction_out, instruction_address_out,load_wb_data : out STD_LOGIC_VECTOR(63 downto 0);
reggie: out regfile_arr;
opcode: out opcode_t;
o_load_type: out std_logic_vector(7 downto 0);
ALU_result: out doubleword;
MMU_state: out std_logic_vector(5 downto 0);
--pragma synthesis_on
--ROM signals
dq: inout STD_LOGIC_VECTOR(3 downto 0);
cs_n: out STD_LOGIC);
end component;
signal status, PC_Switch, clk, UART_RXD, UART_TXD, cs_n: std_logic := '0';
signal rst: std_logic := '1';
signal LED: std_logic_vector(15 downto 0) := (others => '0');
signal dq: std_logic_vector(3 downto 0) := (others => '0');
signal ddr2_addr : STD_LOGIC_VECTOR (12 downto 0);
signal ddr2_ba : STD_LOGIC_VECTOR (2 downto 0);
signal ddr2_ras_n : STD_LOGIC;
signal ddr2_cas_n : STD_LOGIC;
signal ddr2_we_n : STD_LOGIC;
signal ddr2_ck_p : std_logic_vector(0 downto 0);
signal ddr2_ck_n : std_logic_vector(0 downto 0);
signal ddr2_cke : std_logic_vector(0 downto 0);
signal ddr2_cs_n : std_logic_vector(0 downto 0);
signal ddr2_dm : STD_LOGIC_VECTOR (1 downto 0);
signal ddr2_odt : std_logic_vector(0 downto 0);
signal ddr2_dq : STD_LOGIC_VECTOR (15 downto 0);
signal ddr2_dqs_p : STD_LOGIC_VECTOR (1 downto 0);
signal ddr2_dqs_n : STD_LOGIC_VECTOR (1 downto 0);
signal address_out, load_wb_data,instruction_out, instruction_address_out: STD_LOGIC_VECTOR(63 downto 0);
signal reggie : regfile_arr;
signal counter: integer:= 0;
signal opcode: opcode_t;
signal load_type: std_logic_vector(7 downto 0);
signal ALU_result: doubleword;
signal MMU_state: std_logic_vector(5 downto 0);
begin
CPU: simpler_core port map( status => status,
CLK => clk,
RST => rst,
LED => LED,
PC_Switch => PC_Switch,
-- UART Serial I/O
UART_RXD => UART_RXD,
UART_TXD => UART_TXD,
-- DDR2 signals
ddr2_addr => ddr2_addr,
ddr2_ba =>ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n =>ddr2_cas_n ,
ddr2_we_n => ddr2_we_n ,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke ,
ddr2_cs_n => ddr2_cs_n ,
ddr2_dm => ddr2_dm ,
ddr2_odt => ddr2_odt ,
ddr2_dq => ddr2_dq ,
ddr2_dqs_p => ddr2_dqs_p ,
ddr2_dqs_n => ddr2_dqs_n ,
--pragma synthesis_off
address_out => address_out,
instruction_out => instruction_out,
instruction_address_out => instruction_address_out,
reggie => reggie,
load_wb_data => load_wb_data,
opcode => opcode,
o_load_type => load_type,
ALU_result => ALU_result,
MMU_state => MMU_state,
--pragma synthesis_on
--ROM signals
dq => dq,
cs_n => cs_n);
process begin
counter <= counter + 1;
clk <= clk xor '1';
wait for 10 ns;
if(counter < 10) then
rst <= '1';
else
rst <= '0';
end if;
end process;
end Behavioral;
| mit | efa2c7be0c87e377ab42ea95498dfb6d | 0.621006 | 3.091672 | false | false | false | false |
SLongofono/Senior_Design_Capstone | simple_core/fence.vhd | 2 | 3,189 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 01/11/2018 04:18:22 PM
-- Module Name: fence - Behavioral
-- Description: Shift register
--
-- Additional Comments:
-- This is a buffer to preserved the next instruction when the MMU is busy handling
-- a load or store instruction
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity fence is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
halt: in std_logic; -- Do nothing when high
ready_input: in std_logic; -- Previous stage has data to be written back
ready_output: in std_logic; -- Next stage is ready to accept data
output_OK: out std_logic; -- Write data and address are valid
input_OK: out std_logic; -- Read data and address recorded
input_data: in doubleword; -- Data from previous stage
input_address: in doubleword; -- Destination for input data
output_data: out doubleword; -- Data to be written to next stage
output_address: out doubleword -- Destination for output data
);
end fence;
architecture Behavioral of fence is
-- Two states represent waiting or not waiting to dump the registers
-- Moore machine with inputs read, write, and halt, synchronous reset
type state is (state_idle, state_writing);
signal curr_state: state;
signal next_state: state;
signal last_data: doubleword;
signal last_addr: doubleword;
signal s_output_ack: std_logic;
signal s_input_ack: std_logic;
begin
-- Advance State
process(clk, rst)
begin
if('1' = rst) then
curr_state <= state_idle;
elsif(rising_edge(clk)) then
curr_state <= next_state;
end if;
end process;
-- Compute outputs
-- Needs to be sensitive to new input in case MMU stalls
process(input_data, ready_input, rst, clk, curr_state)
begin
input_OK <= '0';
output_OK <= '0';
next_state <= curr_state;
if('1' = rst) then
last_data <= (others => '0');
last_addr <= (others => '0');
elsif('0' = halt) then -- Do nothing unless halt is low
case curr_state is
when state_writing => -- Case pending write
output_OK <= '1'; -- signal outbound data is valid
if('1' = ready_output) then -- Case outbound ready for data
next_state <= state_idle; -- Transition to idle state to get more input
end if;
when state_idle => -- Case no pending write
input_OK <= '1'; -- signal input that data is accepted
if('1' = ready_input) then -- Case input has new data
last_addr <= input_address; -- Update latches
last_data <= input_data;
next_state <= state_writing; -- Transition to write pending state
end if;
end case;
end if; -- rst/halt
end process;
output_address <= last_addr;
output_data <= last_data;
end Behavioral;
| mit | 3dc7857bda4b0d7d476f09e8aa16dc19 | 0.582941 | 4.088462 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/rtl/Eth1000BaseX16To8Mux.vhd | 1 | 4,712 | --------------------------------------------------------------------
-- Title : 1000 BASE X (16-bit) to 8-bit MAC width translation
--------------------------------------------------------------------
-- File : Eth1000BaseX16To8Mux.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description: Width translation for outgoing data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity Eth1000BaseX16To8Mux is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- Clocking to deal with the GT data out (62.5 MHz)
eth62Clk : in sl;
eth62Rst : in sl;
-- 125 MHz clock for 8 bit inputs
eth125Clk : in sl;
eth125Rst : in sl;
-- PHY (16 bit) data interface
ethPhyDataIn : in EthRxPhyLaneInType;
-- MAC (8 bit) data interface
ethMacDataOut : out EthMacDataType
);
end Eth1000BaseX16To8Mux;
-- Define architecture
architecture rtl of Eth1000BaseX16To8Mux is
type StateType is (SYNC_S, HIGH_S, LOW_S);
type RegType is record
state : StateType;
phyTxData : EthTxPhyLaneOutType;
rdEn : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => SYNC_S,
phyTxData => ETH_TX_PHY_LANE_OUT_INIT_C,
rdEn => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal localPhyData : EthRxPhyLaneInType;
signal validPipe : slv(1 downto 0);
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,eth125Rst,ethPhyDataIn,validPipe, localPhyData) is
variable v : RegType;
begin
v := r;
-- Clear any pulsed signals
ethMacDataOut.data <= (others => '0');
ethMacDataOut.dataK <= '0';
ethMacDataOut.dataValid <= '0';
-- Combinatorial state logic
case(r.state) is
-- Synchronize to last valid read of FIFO
when SYNC_S =>
v.rdEn := '1';
if validPipe(1) = '1' and validPipe(0) = '0' then
v.state := HIGH_S;
end if;
-- Grab high word
when HIGH_S =>
v.rdEn := '0';
ethMacDataOut.data <= localPhyData.data(15 downto 8);
ethMacDataOut.dataK <= localPhyData.dataK(1);
ethMacDataOut.dataValid <= '1';
v.state := LOW_S;
-- Grab low word
when LOW_S =>
v.rdEn := '1';
ethMacDataOut.data <= localPhyData.data(7 downto 0);
ethMacDataOut.dataK <= localPhyData.dataK(0);
ethMacDataOut.dataValid <= '1';
v.state := HIGH_S;
when others =>
v.state := SYNC_S;
end case;
-- Reset logic
if (eth125Rst = '1') then
v := REG_INIT_C;
end if;
-- Map to outputs
-- Assignment to signal
rin <= v;
end process;
seq : process (eth125Clk) is
begin
if (rising_edge(eth125Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
-- FIFO to cross the two clock domains
U_Fifo18x16 : entity work.fifo18x16
port map (
rst => eth62Rst,
wr_clk => eth62Clk,
rd_clk => eth125Clk,
din(17 downto 16) => ethPhyDataIn.dataK,
din(15 downto 0) => ethPhyDataIn.data,
wr_en => '1',
rd_en => r.rdEn,
dout(17 downto 16) => localPhyData.dataK,
dout(15 downto 0) => localPhyData.data,
full => open,
empty => open,
valid => validPipe(0)
);
-- Basic pipeline for the valid signal
process(eth125Clk) begin
if rising_edge(eth125Clk) then
if eth125Rst = '1' then
validPipe(1) <= '1';
else
validPipe(1) <= validPipe(0);
end if;
end if;
end process;
end rtl;
| lgpl-2.1 | 98df126ad5634616e5ee010e1a72265f | 0.502334 | 4.210903 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/remote_sources/_/lib/digilent/Touch.vhd | 1 | 733 | -- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package TouchR is
type Coordinate is
record
X : natural;
Y : natural;
end record;
type PanelCharacteristics is
record
TopLeft, TopRight, BottomLeft, BottomRight : Coordinate;
XPlateR, YPlateR : natural;
end record;
-- Declare constants
constant VmodTFT : PanelCharacteristics := (
TopLeft => (X => 150, Y => 300),
TopRight => (X => 3950, Y => 300),
BottomLeft => (X => 150, Y => 3800),
BottomRight => (X => 3950, Y => 3800),
XPlateR => 900,
YPlateR => 245
);
end TouchR;
package body TouchR is
end TouchR;
| gpl-3.0 | a73565b6cc0f12ef3b9f44184456b87f | 0.645293 | 3.132479 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/io/vgacon.vhd | 1 | 15,703 | -------------------------------------------------------------------------------
-- Title : VGA Controller for DE1 boards
-- Project :
-------------------------------------------------------------------------------
-- File : vgacontop.vhd
-- Author : Rafael Auler
-- Company :
-- Created : 2010-03-21
-- Last update: 2010-03-26
-- Platform :
-- Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-03-21 1.0 Rafael Auler Created
-- 2010-03-26 1.1 Rafael Auler Working 64x60 display w/ internal mem.
-- 2010-03-26 1.2 Rafael Auler Working with arbitrary res. (up to
-- 640x480, tied to on-chip memory
-- availability). Defaults to 128x96.
-------------------------------------------------------------------------------
-- How sync signals are generated for 640x480
-- Note: sync signals are active low
-------------------------------------------------------------------------------
-- Horizontal sync:
-- -------------------__--------
-- | | | |
-- <----------->
-- 640
-- <---------------->
-- 660
-- <------------------->
-- 756
-- <-------------------------->
-- 800
-------------------------------------------------------------------------------
-- Vertical sync:
-- -----------------__-------
--
-- | | | |
-- <--------->
-- 480
-- <-------------->
-- 494
-- <----------------->
-- 495
-- <----------------------->
-- 525
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Notes:
-- write_clk, write_addr, write_enable and data_in are input signals used to
-- write to this controller memory and thus altering the displayed image on VGA.
--
-- "data_in" has 3 bits and represents a single image pixel.
-- (high bit for RED, middle for GREEN and lower for BLUE - total of 8 colors).
--
-- These signals follow simple memory write protocol (we=1 writes
-- data_in to address (pixel number) write_addr. This last signal may assume
-- NUM_HORZ_PIXELS * NUM_VERT_PIXELS different values, corresponding to each
-- one of the displayable pixels.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity vgacon is
generic (
-- When changing this, remember to keep 4:3 aspect ratio
-- Must also keep in mind that our native resolution is 640x480, and
-- you can't cross these bounds (although you will seldom have enough
-- on-chip memory to instantiate this module with higher res).
NUM_HORZ_PIXELS : natural := 128; -- Number of horizontal pixels
NUM_VERT_PIXELS : natural := 96); -- Number of vertical pixels
port (
clk27M, rstn : in std_logic;
write_clk, write_enable : in std_logic;
write_addr : in integer range 0 to
NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1;
data_in : in std_logic_vector(2 downto 0);
vga_clk : buffer std_logic; -- Ideally 25.175 MHz
red, green, blue : out std_logic_vector(3 downto 0);
hsync, vsync : out std_logic);
end vgacon;
architecture behav of vgacon is
-- Two signals: one is delayed by one clock cycle. The monitor control uses
-- the delayed one. We need a counter 1 clock cycle earlier, relative
-- to the monitor signal, in order to index the memory contents
-- for the next cycle, when the pixel is in fact sent to the monitor.
signal h_count, h_count_d : integer range 0 to 799; -- horizontal counter
signal v_count, v_count_d : integer range 0 to 524; -- vertical counter
-- We only want to address HORZ*VERT pixels in memory
signal read_addr : integer range 0 to NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1;
signal h_drawarea, v_drawarea, drawarea : std_logic;
signal data_out : std_logic_vector(2 downto 0);
begin -- behav
-- This is our PLL (Phase Locked Loop) to divide the DE1 27 MHz
-- clock and produce a 25.2MHz clock adequate to our VGA controller
divider: work.vga_pll port map (clk27M, vga_clk);
-- This is our dual clock RAM. We use our VGA clock to read contents from
-- memory (pixel color value). The user of this module may use any clock
-- to write contents to this memory, modifying pixels individually.
vgamem : work.dual_clock_ram
generic map (
MEMSIZE => NUM_HORZ_PIXELS * NUM_VERT_PIXELS)
port map (
read_clk => vga_clk,
write_clk => write_clk,
read_address => read_addr,
write_address => write_addr,
data_in => data_in,
data_out => data_out,
we => write_enable);
-- purpose: Increments the current horizontal position counter
-- type : sequential
-- inputs : vga_clk, rstn
-- outputs: h_count, h_count_d
horz_counter: process (vga_clk, rstn)
begin -- process horz_counter
if rstn = '0' then -- asynchronous reset (active low)
h_count <= 0;
h_count_d <= 0;
elsif vga_clk'event and vga_clk = '1' then -- rising clock edge
h_count_d <= h_count; -- 1 clock cycle delayed counter
if h_count = 799 then
h_count <= 0;
else
h_count <= h_count + 1;
end if;
end if;
end process horz_counter;
-- purpose: Determines if we are in the horizontal "drawable" area
-- type : combinational
-- inputs : h_count_d
-- outputs: h_drawarea
horz_sync: process (h_count_d)
begin -- process horz_sync
if h_count_d < 640 then
h_drawarea <= '1';
else
h_drawarea <= '0';
end if;
end process horz_sync;
-- purpose: Increments the current vertical counter position
-- type : sequential
-- inputs : vga_clk, rstn
-- outputs: v_count, v_count_d
vert_counter: process (vga_clk, rstn)
begin -- process vert_counter
if rstn = '0' then -- asynchronous reset (active low)
v_count <= 0;
v_count_d <= 0;
elsif vga_clk'event and vga_clk = '1' then -- rising clock edge
v_count_d <= v_count; -- 1 clock cycle delayed counter
if h_count = 699 then
if v_count = 524 then
v_count <= 0;
else
v_count <= v_count + 1;
end if;
end if;
end if;
end process vert_counter;
-- purpose: Updates information based on vertical position
-- type : combinational
-- inputs : v_count_d
-- outputs: v_drawarea
vert_sync: process (v_count_d)
begin -- process vert_sync
if v_count_d < 480 then
v_drawarea <= '1';
else
v_drawarea <= '0';
end if;
end process vert_sync;
-- purpose: Generates synchronization signals
-- type : combinational
-- inputs : v_count_d, h_count_d
-- outputs: hsync, vsync
sync: process (v_count_d, h_count_d)
begin -- process sync
if (h_count_d >= 659) and (h_count_d <= 755) then
hsync <= '0';
else
hsync <= '1';
end if;
if (v_count_d >= 493) and (v_count_d <= 494) then
vsync <= '0';
else
vsync <= '1';
end if;
end process sync;
-- determines whether we are in drawable area on screen a.t.m.
drawarea <= v_drawarea and h_drawarea;
-- purpose: calculates the controller memory address to read pixel data
-- type : combinational
-- inputs : h_count, v_count
-- outputs: read_addr
gen_r_addr: process (h_count, v_count)
begin -- process gen_r_addr
read_addr <= h_count / (640 / NUM_HORZ_PIXELS)
+ ((v_count/(480 / NUM_VERT_PIXELS))
* NUM_HORZ_PIXELS);
end process gen_r_addr;
-- Build color signals based on memory output and "drawarea" signal
-- (if we are not in the drawable area of 640x480, must deassert all
-- color signals).
red <= (others => data_out(2) and drawarea);
green <= (others => data_out(1) and drawarea);
blue <= (others => data_out(0) and drawarea);
end behav;
-------------------------------------------------------------------------------
-- The following entity is a dual clock RAM (read operates at different
-- clock from write). This is used to isolate two clock domains. The first
-- is the 25.2 MHz clock domain in which our VGA controller needs to operate.
-- This is the read clock, because we read from this memory to determine
-- the color of a pixel. The second is the clock domain of the user of this
-- module, writing in the memory the contents it wants to display in the VGA.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dual_clock_ram is
generic (
MEMSIZE : natural);
port (
read_clk, write_clk : in std_logic; -- support different clocks
data_in : in std_logic_vector(2 downto 0);
write_address, read_address : in integer range 0 to MEMSIZE - 1;
we : in std_logic; -- write enable
data_out : out std_logic_vector(2 downto 0));
end dual_clock_ram;
architecture behav of dual_clock_ram is
-- we only want to address (store) MEMSIZE elements
subtype addr is integer range 0 to MEMSIZE - 1;
type mem is array (addr) of std_logic_vector(2 downto 0);
signal ram_block : mem;
-- we don't care with read after write behavior (whether ram reads
-- old or new data in the same cycle).
attribute ramstyle : string;
attribute ramstyle of dual_clock_ram : entity is "no_rw_check";
--attribute ram_init_file : string;
--attribute ram_init_file of ram_block : signal is "vga_mem.mif";
begin -- behav
-- purpose: Reads data from RAM
-- type : sequential
-- inputs : read_clk, read_address
-- outputs: data_out
read: process (read_clk)
begin -- process read
if read_clk'event and read_clk = '1' then -- rising clock edge
data_out <= ram_block(read_address);
end if;
end process read;
-- purpose: Writes data to RAM
-- type : sequential
-- inputs : write_clk, write_address
-- outputs: ram_block
write: process (write_clk)
begin -- process write
if write_clk'event and write_clk = '1' then -- rising clock edge
if we = '1' then
ram_block(write_address) <= data_in;
end if;
end if;
end process write;
end behav;
-------------------------------------------------------------------------------
-- The following entity is automatically generated by Quartus (a megafunction).
-- As Altera DE1 board does not have a 25.175 MHz, but a 27 Mhz, we
-- instantiate a PLL (Phase Locked Loop) to divide out 27 MHz clock
-- and reach a satisfiable 25.2MHz clock for our VGA controller (14/15 ratio)
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY vga_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END vga_pll;
ARCHITECTURE SYN OF vga_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 15,
clk0_duty_cycle => 50,
clk0_multiply_by => 14,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=vga_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
| mit | 2f0aac06a465ad8268339beb48b0a884 | 0.551805 | 3.617369 | false | false | false | false |
SLongofono/Senior_Design_Capstone | hdl/Ram2Ddr_RefComp/Source/Ram2DdrXadc_RefComp/ipcore_dir/ddr/example_design/rtl/example_top.vhd | 1 | 65,422 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1.9
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves both as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
generic
(
--***************************************************************************
-- Traffic Gen related parameters
--***************************************************************************
BL_WIDTH : integer := 10;
PORT_MODE : string := "BI_MODE";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
EYE_TEST : string := "FALSE";
-- set EYE_TEST = "TRUE" to probe memory
-- signals. Traffic Generator will only
-- write to one single location and no
-- read transactions will be generated.
DATA_PATTERN : string := "DGEN_ALL";
-- For small devices, choose one only.
-- For large device, choose "DGEN_ALL"
-- "DGEN_HAMMER", "DGEN_WALKING1",
-- "DGEN_WALKING0","DGEN_ADDR","
-- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
CMD_PATTERN : string := "CGEN_ALL";
-- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- "CGEN_SEQUENTIAL", "CGEN_ALL"
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
MEM_ADDR_ORDER
: string := "TG_TEST";
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
SEL_VICTIM_LINE : integer := 0;
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 4;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 8;
-- VCO output divisor for PLL output clock (CLKOUT3)
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "OFF";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IODELAY_HP_MODE : string := "ON";
-- to phy_top
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP : string := "IODELAY_MIG";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency.
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL";
-- # = "INTERNAL", "EXTERNAL"
RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port
(
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;function STR_TO_INT(BM : string) return integer is
begin
if(BM = "8") then
return 8;
elsif(BM = "4") then
return 4;
else
return 0;
end if;
end function;
constant DATA_WIDTH : integer := 16;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
constant ECC_WIDTH : integer := ECCWIDTH;
constant ECC_TEST : string := "OFF";
constant DATA_BUF_OFFSET_WIDTH : integer := 1;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--***************************************************************************
-- Traffic Gen related parameters (derived)
--***************************************************************************
constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant MASK_SIZE : integer := DATA_WIDTH/8;
-- Start of User Design top component
component ddr
generic(
BANK_WIDTH : integer;
CK_WIDTH : integer;
COL_WIDTH : integer;
CS_WIDTH : integer;
nCS_PER_RANK : integer;
CKE_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_PER_DM : integer;
DM_WIDTH : integer;
DQ_WIDTH : integer;
DQS_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DRAM_WIDTH : integer;
ECC : string;
DATA_WIDTH : integer;
ECC_TEST : string;
PAYLOAD_WIDTH : integer;
ECC_WIDTH : integer;
MC_ERR_ADDR_WIDTH : integer;
nBANK_MACHS : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
PHY_CONTROL_MASTER_BANK : integer;
AL : string;
nAL : integer;
BURST_MODE : string;
BURST_TYPE : string;
CL : integer;
OUTPUT_DRV : string;
RTT_NOM : string;
ADDR_CMD_MODE : string;
REG_CTRL : string;
CLKIN_PERIOD : integer;
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
tCKE : integer;
tFAW : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
tPRDI : integer;
SIM_BYPASS_INIT_CAL : string;
SIMULATION : string;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
IODELAY_HP_MODE : string;
IBUF_LPWR_MODE : string;
DATA_IO_IDLE_PWRDWN : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
CKE_ODT_AUX : string;
USER_REFRESH : string;
WRLVL : string;
ORDERING : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
TCQ : integer;
CMD_PIPE_PLUS1 : string;
tCK : integer;
nCK_PER_CLK : integer;
DIFF_TERM_SYSCLK : string;
DEBUG_PORT : string;
TEMP_MON_CONTROL : string;
IODELAY_GRP : string;
SYSCLK_TYPE : string;
REFCLK_TYPE : string;
SYS_RST_PORT : string;
REFCLK_FREQ : real;
DIFF_TERM_REFCLK : string;
DRAM_TYPE : string;
CAL_WIDTH : string;
STARVE_LIMIT : integer;
RST_ACT_LOW : integer
);
port(
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end component ddr;
-- End of User Design top component
component mig_7series_v1_9_traffic_gen_top
generic (
TCQ : integer;
SIMULATION : string;
FAMILY : string;
MEM_TYPE : string;
TST_MEM_INSTR_MODE : string;
--BL_WIDTH : integer;
nCK_PER_CLK : integer;
NUM_DQ_PINS : integer;
MEM_BURST_LEN : integer;
MEM_COL_WIDTH : integer;
ADDR_WIDTH : integer;
DATA_WIDTH : integer;
DATA_MODE : std_logic_vector(3 downto 0);
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
EYE_TEST : string;
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string
);
port (
clk : in std_logic;
rst : in std_logic;
manual_clear_error : in std_logic;
tg_only_rst : in std_logic;
memc_init_done : in std_logic;
memc_cmd_full : in std_logic;
memc_cmd_en : out std_logic;
memc_cmd_instr : out std_logic_vector(2 downto 0);
memc_cmd_bl : out std_logic_vector(5 downto 0);
memc_cmd_addr : out std_logic_vector(31 downto 0);
memc_wr_en : out std_logic;
memc_wr_end : out std_logic;
memc_wr_mask : out std_logic_vector(DATA_WIDTH/8-1 downto 0);
memc_wr_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
memc_wr_full : in std_logic;
memc_rd_en : out std_logic;
memc_rd_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
memc_rd_empty : in std_logic;
qdr_wr_cmd_o : out std_logic;
qdr_rd_cmd_o : out std_logic;
vio_pause_traffic : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(3 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_instr_mode_value : in std_logic_vector(3 downto 0);
vio_bl_mode_value : in std_logic_vector(1 downto 0);
vio_fixed_bl_value : in std_logic_vector(9 downto 0);
vio_fixed_instr_value : in std_logic_vector(2 downto 0);
vio_data_mask_gen : in std_logic;
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(31 downto 0);
simple_data0 : in std_logic_vector(31 downto 0);
simple_data1 : in std_logic_vector(31 downto 0);
simple_data2 : in std_logic_vector(31 downto 0);
simple_data3 : in std_logic_vector(31 downto 0);
simple_data4 : in std_logic_vector(31 downto 0);
simple_data5 : in std_logic_vector(31 downto 0);
simple_data6 : in std_logic_vector(31 downto 0);
simple_data7 : in std_logic_vector(31 downto 0);
wdt_en_i : in std_logic;
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
cmp_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
dq_error_bytelane_cmp : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
error : out std_logic;
error_status : out std_logic_vector((64+(2*DATA_WIDTH-1)) downto 0);
cumlative_dq_lane_error : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
cmd_wdt_err_o : out std_logic;
wr_wdt_err_o : out std_logic;
rd_wdt_err_o : out std_logic;
mem_pattern_init_done : out std_logic
);
end component mig_7series_v1_9_traffic_gen_top;
-- Signal declarations
signal app_ecc_multiple_err : std_logic_vector(2*nCK_PER_CLK-1 downto 0);
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_addr_i : std_logic_vector(31 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_rdy : std_logic;
signal app_rdy_i : std_logic;
signal app_rd_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rd_data_valid_i : std_logic;
signal app_wdf_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(APP_MASK_WIDTH-1 downto 0);
signal app_wdf_rdy : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_sr_req : std_logic;
signal app_sr_active : std_logic;
signal app_ref_req : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_req : std_logic;
signal app_zq_ack : std_logic;
signal app_wdf_wren : std_logic;
signal error_status : std_logic_vector(64 + (4*PAYLOAD_WIDTH*nCK_PER_CLK - 1) downto 0);
signal cumlative_dq_lane_error : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal mem_pattern_init_done : std_logic;
signal modify_enable_sel : std_logic;
signal data_mode_manual_sel : std_logic_vector(2 downto 0);
signal addr_mode_manual_sel : std_logic_vector(2 downto 0);
signal cmp_data : std_logic_vector(PAYLOAD_WIDTH*2*nCK_PER_CLK-1 downto 0);
signal cmp_data_r : std_logic_vector(63 downto 0);
signal cmp_data_valid : std_logic;
signal cmp_data_valid_r : std_logic;
signal cmp_error : std_logic;
signal wr_data_counts : std_logic_vector(47 downto 0);
signal rd_data_counts : std_logic_vector(47 downto 0);
signal dq_error_bytelane_cmp : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal init_calib_complete_i : std_logic;
signal tg_compare_error_i : std_logic;
signal tg_rst : std_logic;
signal po_win_tg_rst : std_logic;
signal manual_clear_error : std_logic;
signal clk : std_logic;
signal rst : std_logic;
signal vio_modify_enable : std_logic;
signal vio_data_mode_value : std_logic_vector(3 downto 0);
signal vio_pause_traffic : std_logic;
signal vio_addr_mode_value : std_logic_vector(2 downto 0);
signal vio_instr_mode_value : std_logic_vector(3 downto 0);
signal vio_bl_mode_value : std_logic_vector(1 downto 0);
signal vio_fixed_bl_value : std_logic_vector(BL_WIDTH-1 downto 0);
signal vio_fixed_instr_value : std_logic_vector(2 downto 0);
signal vio_data_mask_gen : std_logic;
signal dbg_clear_error : std_logic;
signal vio_tg_rst : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_pi_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_po_f_dec : std_logic;
signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
signal wdt_en_w : std_logic;
signal cmd_wdt_err_w : std_logic;
signal wr_wdt_err_w : std_logic;
signal rd_wdt_err_w : std_logic;
begin
--***************************************************************************
init_calib_complete <= init_calib_complete_i;
tg_compare_error <= tg_compare_error_i;
app_rdy_i <= not(app_rdy);
app_wdf_rdy_i <= not(app_wdf_rdy);
app_rd_data_valid_i <= not(app_rd_data_valid);
app_addr <= app_addr_i(ADDR_WIDTH-1 downto 0);
-- Start of User Design top instance
--***************************************************************************
-- The User design is instantiated below. The memory interface ports are
-- connected to the top-level and the application interface ports are
-- connected to the traffic generator module. This provides a reference
-- for connecting the memory controller to system.
--***************************************************************************
u_ddr : ddr
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_PER_DM => DQ_PER_DM,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
IODELAY_HP_MODE => IODELAY_HP_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
PHY_CONTROL_MASTER_BANK => PHY_CONTROL_MASTER_BANK,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
DM_WIDTH => DM_WIDTH,
nCK_PER_CLK => nCK_PER_CLK,
tCK => tCK,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
SYSCLK_TYPE => SYSCLK_TYPE,
REFCLK_TYPE => REFCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
REFCLK_FREQ => REFCLK_FREQ,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
IODELAY_GRP => IODELAY_GRP,
CAL_WIDTH => CAL_WIDTH,
STARVE_LIMIT => STARVE_LIMIT,
DRAM_TYPE => DRAM_TYPE,
RST_ACT_LOW => RST_ACT_LOW
)
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete_i,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_sr_active => app_sr_active,
app_ref_req => '0',
app_ref_ack => app_ref_ack,
app_zq_req => '0',
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
sys_rst => sys_rst
);
-- End of User Design top instance
--***************************************************************************
-- The traffic generation module instantiated below drives traffic (patterns)
-- on the application interface of the memory controller
--***************************************************************************
tg_rst <= vio_tg_rst or po_win_tg_rst;
u_traffic_gen_top : mig_7series_v1_9_traffic_gen_top
generic map (
TCQ => TCQ,
SIMULATION => SIMULATION,
FAMILY => "VIRTEX7",
MEM_TYPE => DRAM_TYPE,
TST_MEM_INSTR_MODE => TST_MEM_INSTR_MODE,
--BL_WIDTH => BL_WIDTH,
nCK_PER_CLK => nCK_PER_CLK,
NUM_DQ_PINS => PAYLOAD_WIDTH,
MEM_BURST_LEN => BURST_LENGTH,
MEM_COL_WIDTH => COL_WIDTH,
PORT_MODE => PORT_MODE,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => TG_ADDR_WIDTH,
DATA_WIDTH => APP_DATA_WIDTH,
BEGIN_ADDRESS => BEGIN_ADDRESS,
DATA_MODE => DATA_MODE,
END_ADDRESS => END_ADDRESS,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
CMD_WDT => CMD_WDT,
RD_WDT => RD_WDT,
WR_WDT => WR_WDT,
EYE_TEST => EYE_TEST
)
port map (
clk => clk,
rst => rst,
tg_only_rst => tg_rst,
manual_clear_error => manual_clear_error,
memc_init_done => init_calib_complete_i,
memc_cmd_full => app_rdy_i,
memc_cmd_en => app_en,
memc_cmd_instr => app_cmd,
memc_cmd_bl => open,
memc_cmd_addr => app_addr_i,
memc_wr_en => app_wdf_wren,
memc_wr_end => app_wdf_end,
memc_wr_mask => app_wdf_mask((PAYLOAD_WIDTH*2*nCK_PER_CLK)/8-1 downto 0),
memc_wr_data => app_wdf_data(PAYLOAD_WIDTH*2*nCK_PER_CLK-1 downto 0),
memc_wr_full => app_wdf_rdy_i,
memc_rd_en => open,
memc_rd_data => app_rd_data(PAYLOAD_WIDTH*2*nCK_PER_CLK-1 downto 0),
memc_rd_empty => app_rd_data_valid_i,
qdr_wr_cmd_o => open,
qdr_rd_cmd_o => open,
vio_pause_traffic => vio_pause_traffic,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_instr_mode_value => vio_instr_mode_value,
vio_bl_mode_value => vio_bl_mode_value,
vio_fixed_bl_value => vio_fixed_bl_value,
vio_fixed_instr_value=> vio_fixed_instr_value,
vio_data_mask_gen => vio_data_mask_gen,
fixed_addr_i => all_zeros1,
fixed_data_i => all_zeros1,
simple_data0 => all_zeros1,
simple_data1 => all_zeros1,
simple_data2 => all_zeros1,
simple_data3 => all_zeros1,
simple_data4 => all_zeros1,
simple_data5 => all_zeros1,
simple_data6 => all_zeros1,
simple_data7 => all_zeros1,
wdt_en_i => wdt_en_w,
bram_cmd_i => all_zeros2,
bram_valid_i => '0',
bram_rdy_o => open,
cmp_data => cmp_data,
cmp_data_valid => cmp_data_valid,
cmp_error => cmp_error,
wr_data_counts => wr_data_counts,
rd_data_counts => rd_data_counts,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
error => tg_compare_error_i,
error_status => error_status,
cumlative_dq_lane_error => cumlative_dq_lane_error,
cmd_wdt_err_o => cmd_wdt_err_w,
wr_wdt_err_o => wr_wdt_err_w,
rd_wdt_err_o => rd_wdt_err_w,
mem_pattern_init_done => mem_pattern_init_done
);
--*****************************************************************
-- Default values are assigned to the debug inputs of the traffic
-- generator
--*****************************************************************
vio_modify_enable <= '0';
vio_data_mode_value <= "0010";
vio_addr_mode_value <= "011";
vio_instr_mode_value <= "0010";
vio_bl_mode_value <= "10";
vio_fixed_bl_value <= "0000010000";
vio_data_mask_gen <= '0';
vio_pause_traffic <= '0';
vio_fixed_instr_value <= "001";
dbg_clear_error <= '0';
po_win_tg_rst <= '0';
vio_tg_rst <= '0';
wdt_en_w <= '1';
dbg_sel_pi_incdec <= '0';
dbg_sel_po_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
end architecture arch_example_top;
| mit | 1edd38c6d28953df1bb57849f03f4981 | 0.426462 | 4.475747 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/control.vhd | 1 | 26,752 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 01:13:09 PM
-- Module Name: control - Behavioral
-- Description: Control unit for RISCV core
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity control is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
instruction_ready: in std_logic; -- IM ready
writeback_ack: in std_logic; -- WB ready for input
writeback_request: out std_logic; -- Signal WB results waiting
MMU_load_complete: in std_logic; -- MMU load data is ready to be written back
ALU_halts: out std_logic_vector(4 downto 0); -- Signal ALU pipeline modules to halt
PC_select: out std_logic_vector(4 downto 0); -- Select for PCnext mux
instr_code: in instr_t; -- The current instruction from the decode module
instr: in doubleword; -- The instruction itself for CSR instruction access
RegFile_raddr: out std_logic_vector(4 downto 0);-- For CSR instrs, read address of regfile
RegFile_waddr: out std_logic_vector(4 downto 0);-- For CSR instrs, write back address of regfile
RegFile_rdata: in doubleword; -- For CSR instrs, read data from above address
RegFile_wdata: out doubleword; -- For CSR instrs, write data to above address
CSR_bits: in std_logic_vector(11 downto 0);-- For CSR instrs, address of CSR from spec
rs1: in reg_t;
rs2: in reg_t;
rs3: in reg_t;
rd: in reg_t
);
end control;
architecture Behavioral of control is
-- High-level states of operation (distinct from privilege modes)
type state is (setup, teardown, normal, waiting, exception);
signal curr_state, next_state: state;
-- Control status registers followed by scratch
type CSR_t is array (0 to 64) of doubleword;
signal CSR: CSR_t;
-- If in waiting state, reason determines actions on exit
signal waiting_reason: std_logic_vector(2 downto 0);
-- Handle complicated CSR read behaviors
-- @param CSR_bits - The 12 bit CSR address per the specification
-- @param value - The value to be read back
-- @param mode - What mode we encountered this instruction in
-- Notes: need to pass handle to CSR in because procedures are not allowed to modify signals without an explicit handle
-- TODO add in interrupt setting
-- TODO add in mode checking
-- TODO handle cycle and time readings externally
procedure CSR_read(CSR_bits: in std_logic_vector(11 downto 0); value: out doubleword; CSR: inout CSR_t; mode: in std_logic_vector(1 downto 0)) is
begin
-- TODO add checks for mode
-- TODO handle mode fails and offending instruction logging
case CSR_bits is
when CSR_ADDR_FFLAGS =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MSTATUS) and x"000000000000001f";
end if;
when CSR_ADDR_FRM =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MSTATUS) and x"00000000000000e0";
end if;
when CSR_ADDR_FCSR =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MSTATUS) and x"0000000000006000";
end if;
when CSR_ADDR_CYCLE =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if user mode not allowed to read
-- TODO flip bad instruction exception bit
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if supervisor mode not allowed to read
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_TIME =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if user mode not allowed to read
-- TODO flip bad instruction exception bit
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if supervisor mode not allowed to read
-- TODO flip bad instruction exception bit
else
-- TODO tie this to external time signal
end if;
when CSR_ADDR_INSTRET =>
if( (CSR(CSR_SCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if user mode not allowed to read
-- TODO flip bad instruction exception bit
elsif( (CSR(CSR_MCOUNTEREN)( 0 ) = '0') and true ) then
-- Error if supervisor mode not allowed to read
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_HPMCOUNTER3 | CSR_ADDR_HPMCOUNTER4 | CSR_ADDR_HPMCOUNTER5 | CSR_ADDR_HPMCOUNTER6 | CSR_ADDR_HPMCOUNTER7 |
CSR_ADDR_HPMCOUNTER8 | CSR_ADDR_HPMCOUNTER9 | CSR_ADDR_HPMCOUNTER10 | CSR_ADDR_HPMCOUNTER11 | CSR_ADDR_HPMCOUNTER12 |
CSR_ADDR_HPMCOUNTER13| CSR_ADDR_HPMCOUNTER14 | CSR_ADDR_HPMCOUNTER15 | CSR_ADDR_HPMCOUNTER16 | CSR_ADDR_HPMCOUNTER17 |
CSR_ADDR_HPMCOUNTER18| CSR_ADDR_HPMCOUNTER19 | CSR_ADDR_HPMCOUNTER20 | CSR_ADDR_HPMCOUNTER21 | CSR_ADDR_HPMCOUNTER22 |
CSR_ADDR_HPMCOUNTER23| CSR_ADDR_HPMCOUNTER24 | CSR_ADDR_HPMCOUNTER25 | CSR_ADDR_HPMCOUNTER26 | CSR_ADDR_HPMCOUNTER27 |
CSR_ADDR_HPMCOUNTER28| CSR_ADDR_HPMCOUNTER29 | CSR_ADDR_HPMCOUNTER30 | CSR_ADDR_HPMCOUNTER31 =>
-- From notes: *counteren(x) needs to be checked, where x = 1 << integer(address(4 downto 0))
-- Since this is always a single bit, just convert directly to an integer and use it to index the register
-- Example: hpmcounter17 -> x = 1 << 17 = (0100000000000000000)_2. Or, just use bit 17.
if( (CSR(CSR_SCOUNTEREN)( to_integer(unsigned(CSR_BITS(4 downto 0))) ) = '0') and true ) then
-- Error if user mode not allowed to read
-- TODO flip bad instruction exception bit
elsif( (CSR(CSR_MCOUNTEREN)( to_integer(unsigned(CSR_BITS(4 downto 0))) ) = '0') and true ) then
-- Error if supervisor mode not allowed to read
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_MINSTRET);
end if;
when CSR_ADDR_SSTATUS =>
if( CSR(CSR_MSTATUS)( 16 downto 15 ) = "11" or CSR(CSR_MSTATUS)( 14 downto 13 ) = "11") then
value := CSR(CSR_MSTATUS) and x"000000000005e122";
else
value := CSR(CSR_MSTATUS) and x"800000000005e122";
end if;
when CSR_ADDR_SIE =>
value := CSR(CSR_MIE) and CSR(CSR_MIDELEG);
when CSR_ADDR_STVEC =>
value := CSR(CSR_STVEC);
when CSR_ADDR_SCOUNTEREN =>
value := CSR(CSR_SCOUNTEREN);
when CSR_ADDR_SSCRATCH =>
value := CSR(CSR_SSCRATCH);
when CSR_ADDR_SEPC =>
value := CSR(CSR_SEPC);
when CSR_ADDR_SCAUSE =>
value := CSR(CSR_SCAUSE);
when CSR_ADDR_STVAL =>
value := CSR(CSR_STVAL);
when CSR_ADDR_SIP =>
value := CSR(CSR_MIP) and CSR(CSR_MIDELEG);
when CSR_ADDR_SATP =>
if(CSR(CSR_MSTATUS)( 20 ) = '1' and true) then
-- Check that we are in machine mode
-- TODO flip bad instruction exception bit
else
value := CSR(CSR_SATP);
end if;
when CSR_ADDR_MVENDORID =>
value := zero_word & zero_word;
when CSR_ADDR_MARCHID =>
value := zero_word & zero_word;
when CSR_ADDR_MIMPID =>
value := zero_word & zero_word;
when CSR_ADDR_MHARTID =>
value := zero_word & zero_word;
when CSR_ADDR_MSTATUS =>
value := CSR(CSR_MSTATUS);
when CSR_ADDR_MISA =>
value := CSR(CSR_MISA);
when CSR_ADDR_MEDELEG =>
value := CSR(CSR_MEDELEG);
when CSR_ADDR_MIDELEG =>
value := CSR(CSR_MIDELEG);
when CSR_ADDR_MIE =>
value := CSR(CSR_MIE);
when CSR_ADDR_MTVEC =>
value := CSR(CSR_MTVEC);
when CSR_ADDR_MCOUNTEREN =>
value := CSR(CSR_MCOUNTEREN);
when CSR_ADDR_MSCRATCH =>
value := CSR(CSR_MSCRATCH);
when CSR_ADDR_MEPC =>
value := CSR(CSR_MEPC);
when CSR_ADDR_MCAUSE =>
value := CSR(CSR_MCAUSE);
when CSR_ADDR_MTVAL =>
value := CSR(CSR_MTVAL);
when CSR_ADDR_MIP =>
value := CSR(CSR_MIP);
when CSR_ADDR_MHPMCOUNTER3 | CSR_ADDR_MHPMCOUNTER4 | CSR_ADDR_MHPMCOUNTER5 | CSR_ADDR_MHPMCOUNTER6 |
CSR_ADDR_MHPMCOUNTER7 | CSR_ADDR_MHPMCOUNTER8 | CSR_ADDR_MHPMCOUNTER9 | CSR_ADDR_MHPMCOUNTER10 |
CSR_ADDR_MHPMCOUNTER11 | CSR_ADDR_MHPMCOUNTER12 | CSR_ADDR_MHPMCOUNTER13 | CSR_ADDR_MHPMCOUNTER14 |
CSR_ADDR_MHPMCOUNTER15 | CSR_ADDR_MHPMCOUNTER16 | CSR_ADDR_MHPMCOUNTER17 | CSR_ADDR_MHPMCOUNTER18 |
CSR_ADDR_MHPMCOUNTER19 | CSR_ADDR_MHPMCOUNTER20 | CSR_ADDR_MHPMCOUNTER21 | CSR_ADDR_MHPMCOUNTER22 |
CSR_ADDR_MHPMCOUNTER23 | CSR_ADDR_MHPMCOUNTER24 | CSR_ADDR_MHPMCOUNTER25 | CSR_ADDR_MHPMCOUNTER26 |
CSR_ADDR_MHPMCOUNTER27 | CSR_ADDR_MHPMCOUNTER28 | CSR_ADDR_MHPMCOUNTER29 | CSR_ADDR_MHPMCOUNTER30 |
CSR_ADDR_MHPMCOUNTER31 =>
value := zero_word & zero_word;
when CSR_ADDR_MHPMEVENT3 | CSR_ADDR_MHPMEVENT4 | CSR_ADDR_MHPMEVENT5 | CSR_ADDR_MHPMEVENT6 |
CSR_ADDR_MHPMEVENT7 | CSR_ADDR_MHPMEVENT8 | CSR_ADDR_MHPMEVENT9 | CSR_ADDR_MHPMEVENT10 |
CSR_ADDR_MHPMEVENT11 | CSR_ADDR_MHPMEVENT12 | CSR_ADDR_MHPMEVENT13 | CSR_ADDR_MHPMEVENT14 |
CSR_ADDR_MHPMEVENT15 | CSR_ADDR_MHPMEVENT16 | CSR_ADDR_MHPMEVENT17 | CSR_ADDR_MHPMEVENT18 |
CSR_ADDR_MHPMEVENT19 | CSR_ADDR_MHPMEVENT20 | CSR_ADDR_MHPMEVENT21 | CSR_ADDR_MHPMEVENT22 |
CSR_ADDR_MHPMEVENT23 | CSR_ADDR_MHPMEVENT24 | CSR_ADDR_MHPMEVENT25 | CSR_ADDR_MHPMEVENT26 |
CSR_ADDR_MHPMEVENT27 | CSR_ADDR_MHPMEVENT28 | CSR_ADDR_MHPMEVENT29 | CSR_ADDR_MHPMEVENT30 |
CSR_ADDR_MHPMEVENT31 =>
value := zero_word & zero_word;
when others =>
-- All others not implemented, set trap
-- TODO set bad instruction exception
end case;
end; -- CSR_read procedure
-- Handle complicated CSR write behaviors
-- @param CSR_bits - The 12 bit CSR address per the specification
-- @param value - The write value
-- @param mode - What mode we encountered this instruction in
-- Notes: need to pass handle to CSR in because procedures are not allowed to modify signals without an explicit handle
-- TODO handle cycle and time readings externally
procedure CSR_write(CSR_bits: in std_logic_vector(11 downto 0); value: in doubleword; CSR: inout CSR_t; mode: in std_logic_vector(1 downto 0)) is
begin
-- TODO add checks for mode
-- TODO handle mode fails and offending instruction logging
case CSR_bits is
when CSR_ADDR_FFLAGS =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(4 downto 0) := value(4 downto 0); -- Set FP flags passed in
end if;
when CSR_ADDR_FRM =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(7 downto 5) := value(2 downto 0); -- Set FP rounging mode passed in
end if;
when CSR_ADDR_FCSR =>
if(CSR(CSR_MSTATUS)(14 downto 13) = "00") then
-- Error, no FP unit
-- TODO flip bad instruction exception bit
else
CSR(CSR_MSTATUS)(14 downto 13) := "11"; -- Set FP dirty bits
CSR(CSR_MSTATUS)( 63 ) := '1'; -- Set flag indicating dirty bits
CSR(CSR_FCSR)(7 downto 0) := value(7 downto 0); -- Set FP rounging mode and flags passed in
end if;
when CSR_ADDR_SSTATUS =>
CSR(CSR_MSTATUS)( 18 ) := value(18); -- Update Smode portion of MSTATUS
CSR(CSR_MSTATUS)( 16 downto 15 ) := value(16 downto 15);
CSR(CSR_MSTATUS)( 14 downto 13 ) := value(14 downto 13);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 1 ) := value(1);
when CSR_ADDR_SIE => -- Update Smode interrupts to and of MIE and delegations
CSR(CSR_MIE)( 12 ) := value(12) and CSR(CSR_MIDELEG)( 12 );
CSR(CSR_MIE)( 9 ) := value(9) and CSR(CSR_MIDELEG)( 9 );
CSR(CSR_MIE)( 7 ) := value(7) and CSR(CSR_MIDELEG)( 7 );
CSR(CSR_MIE)( 5 ) := value(5) and CSR(CSR_MIDELEG)( 5 );
CSR(CSR_MIE)( 3 ) := value(3) and CSR(CSR_MIDELEG)( 3 );
CSR(CSR_MIE)( 1 ) := value(1) and CSR(CSR_MIDELEG)( 1 );
when CSR_ADDR_STVEC => -- update STVec to the shifted address in 63:2
CSR(CSR_STVEC)(63 downto 2) := value(63 downto 2);
when CSR_ADDR_SCOUNTEREN =>
CSR( CSR_SCOUNTEREN ) := value; -- Pass through new enbale value
when CSR_ADDR_SSCRATCH =>
CSR( CSR_SSCRATCH ) := value; -- Pass through new scratch value
when CSR_ADDR_SEPC =>
CSR( CSR_SEPC ) := value; -- Pass through new scratch value
when CSR_ADDR_SCAUSE =>
CSR( CSR_SCAUSE ) := value; -- Pass through new scratch value
when CSR_ADDR_STVAL =>
CSR( CSR_STVAL ) := value; -- Pass through new scratch value
when CSR_ADDR_SIP =>
CSR(CSR_MIP)( 1 ) := value(1) and CSR(CSR_MIDELEG)( 1 ); -- Pass through new scratch value
when CSR_ADDR_SATP =>
if(CSR(CSR_MSTATUS)(20) = '1') then
-- TODO set bad instruction exception
elsif( (value(63 downto 60) = "0000") or
(value(63 downto 60) = "1000") or
(value(63 downto 60) = "1001") ) then
-- This won't actually do anything, since we aren't implementing address translations for Smode
CSR(CSR_SATP)(63 downto 60) := value(63 downto 60);
CSR(CSR_SATP)(43 downto 0) := value(43 downto 0);
end if;
when CSR_ADDR_MSTATUS =>
-- update status
if(value(14 downto 13) = "00") then -- if not dirty
CSR(CSR_MSTATUS)(22 downto 17) := value(22 downto 17);
CSR(CSR_MSTATUS)(14 downto 11) := value(14 downto 11);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 7 ) := value(7);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 3 ) := value(3);
CSR(CSR_MSTATUS)( 1 ) := value(1);
CSR(CSR_MSTATUS)( 63 ) := '0';
else
CSR(CSR_MSTATUS)(22 downto 17) := value(22 downto 17);
CSR(CSR_MSTATUS)(14 downto 11) := value(14 downto 11);
CSR(CSR_MSTATUS)( 8 ) := value(8);
CSR(CSR_MSTATUS)( 7 ) := value(7);
CSR(CSR_MSTATUS)( 5 ) := value(5);
CSR(CSR_MSTATUS)( 3 ) := value(3);
CSR(CSR_MSTATUS)( 1 ) := value(1);
CSR(CSR_MSTATUS)( 63 ) := '1';
end if;
when CSR_ADDR_MISA => -- Do nothing
when CSR_ADDR_MEDELEG => -- Update delegation of synchronous exceptions
CSR( CSR_MEDELEG ) := value;
when CSR_ADDR_MIDELEG => -- Update delegation of aynschronous exceptions
CSR(CSR_MIDELEG)( 12 ) := value(12);
CSR(CSR_MIDELEG)( 9 ) := value(9);
CSR(CSR_MIDELEG)( 5 ) := value(5);
CSR(CSR_MIDELEG)( 1 ) := value(1);
when CSR_ADDR_MIE => -- Update enabled exceptions
CSR(CSR_MIE)( 12 ) := value(12);
CSR(CSR_MIE)( 9 ) := value(9);
CSR(CSR_MIE)( 7 ) := value(7);
CSR(CSR_MIE)( 5 ) := value(5);
CSR(CSR_MIE)( 3 ) := value(3);
CSR(CSR_MIE)( 1 ) := value(1);
when CSR_ADDR_MTVEC => -- Update shifted base address for machine mode trap handler
-- Note: bit 1 is reserved because reasons
CSR(CSR_MTVEC)(63 downto 2) := value(63 downto 2);
CSR(CSR_MTVEC)( 0 ) := value(0);
when CSR_ADDR_MCOUNTEREN => -- Pass through new counter enable bit
CSR( CSR_MCOUNTEREN ) := value;
when CSR_ADDR_MSCRATCH => -- Pass through new scratch value
CSR( CSR_MSCRATCH ) := value;
when CSR_ADDR_MEPC => -- Pass through new exception PC
CSR( CSR_MEPC ) := value;
when CSR_ADDR_MCAUSE => -- Pass through new exception cause
CSR( CSR_MCAUSE ) := value;
when CSR_ADDR_MTVAL => -- Pass through address of the bad address for relevant interrupts (store/load misaligned, page fault)
CSR( CSR_MTVAL ) := value;
when CSR_ADDR_MIP => -- Allow Smode timer and software interrupts to be signalled
CSR(CSR_MIP)( 5 ) := value(5);
CSR(CSR_MIP)( 1 ) := value(1);
when CSR_ADDR_MHPMCOUNTER3 => -- Ignore writes
when CSR_ADDR_MHPMCOUNTER4 =>
when CSR_ADDR_MHPMCOUNTER5 =>
when CSR_ADDR_MHPMCOUNTER6 =>
when CSR_ADDR_MHPMCOUNTER7 =>
when CSR_ADDR_MHPMCOUNTER8 =>
when CSR_ADDR_MHPMCOUNTER9 =>
when CSR_ADDR_MHPMCOUNTER10 =>
when CSR_ADDR_MHPMCOUNTER11 =>
when CSR_ADDR_MHPMCOUNTER12 =>
when CSR_ADDR_MHPMCOUNTER13 =>
when CSR_ADDR_MHPMCOUNTER14 =>
when CSR_ADDR_MHPMCOUNTER15 =>
when CSR_ADDR_MHPMCOUNTER16 =>
when CSR_ADDR_MHPMCOUNTER17 =>
when CSR_ADDR_MHPMCOUNTER18 =>
when CSR_ADDR_MHPMCOUNTER19 =>
when CSR_ADDR_MHPMCOUNTER20 =>
when CSR_ADDR_MHPMCOUNTER21 =>
when CSR_ADDR_MHPMCOUNTER22 =>
when CSR_ADDR_MHPMCOUNTER23 =>
when CSR_ADDR_MHPMCOUNTER24 =>
when CSR_ADDR_MHPMCOUNTER25 =>
when CSR_ADDR_MHPMCOUNTER26 =>
when CSR_ADDR_MHPMCOUNTER27 =>
when CSR_ADDR_MHPMCOUNTER28 =>
when CSR_ADDR_MHPMCOUNTER29 =>
when CSR_ADDR_MHPMCOUNTER30 =>
when CSR_ADDR_MHPMCOUNTER31 =>
when CSR_ADDR_MHPMEVENT3 =>
when CSR_ADDR_MHPMEVENT4 =>
when CSR_ADDR_MHPMEVENT5 =>
when CSR_ADDR_MHPMEVENT6 =>
when CSR_ADDR_MHPMEVENT7 =>
when CSR_ADDR_MHPMEVENT8 =>
when CSR_ADDR_MHPMEVENT9 =>
when CSR_ADDR_MHPMEVENT10 =>
when CSR_ADDR_MHPMEVENT11 =>
when CSR_ADDR_MHPMEVENT12 =>
when CSR_ADDR_MHPMEVENT13 =>
when CSR_ADDR_MHPMEVENT14 =>
when CSR_ADDR_MHPMEVENT15 =>
when CSR_ADDR_MHPMEVENT16 =>
when CSR_ADDR_MHPMEVENT17 =>
when CSR_ADDR_MHPMEVENT18 =>
when CSR_ADDR_MHPMEVENT19 =>
when CSR_ADDR_MHPMEVENT20 =>
when CSR_ADDR_MHPMEVENT21 =>
when CSR_ADDR_MHPMEVENT22 =>
when CSR_ADDR_MHPMEVENT23 =>
when CSR_ADDR_MHPMEVENT24 =>
when CSR_ADDR_MHPMEVENT25 =>
when CSR_ADDR_MHPMEVENT26 =>
when CSR_ADDR_MHPMEVENT27 =>
when CSR_ADDR_MHPMEVENT28 =>
when CSR_ADDR_MHPMEVENT29 =>
when CSR_ADDR_MHPMEVENT30 =>
when CSR_ADDR_MHPMEVENT31 =>
when others =>
-- All others not implemented, set trap
-- TODO set bad isntruction exception
end case;
end; -- CSR_write procedure
begin
-- Advance state
update_state: process(clk,rst)
begin
if(rising_edge(clk)) then
if('1' = rst) then
curr_state <= setup;
else
curr_state <= next_state;
end if;
end if;
end process;
-- Compute outputs
update_signals: process(curr_state)
-- CSR temporary
variable tempVal: doubleword;
variable CSRVal: doubleword;
variable CSR_bits: std_logic_vector(11 downto 0) := instr(31 downto 20);
begin
-- default outputs
next_state <= curr_state;
-- adjust next state and outputs
case curr_state is
when setup => -- Bootloader code
-- Reset CSR
-- CSR <= (others => (zero_word & zero_word));
when teardown => -- Maybe superflous
when waiting =>
case waiting_reason is
when "000" => -- Waiting on MMU instruction
if('1' = instruction_ready) then
-- Resume normal mode
next_state <= normal;
end if;
when "001" => -- Waiting on MMU to clear WB (store instructions)
if('1' = writeback_ack) then
next_state <= normal;
end if;
when "010" => -- Waiting on mulhsu (one cycle)
-- always go back to normal, stalled one cycle
next_state <= normal;
when "011" => -- Waiting on MMU load data
if('1' = MMU_load_complete) then
next_state <= normal;
end if;
when others => -- Waiting for interrupt (special state when no work exists)
end case;
when exception => -- Interrupt to take
-- Determine which of supervisor/machine interrupt vector to use
-- Switch in exception address and perform jump
-- return to normal mode to execute handler instructions
next_state <= normal;
when others => -- Normal operation
-- Determine the appropriate pipeline for the active instruction
case instr_code is
-- Handle privileged instructions here
when instr_FENCE =>
-- NOT IMPLEMENTED - fence memory and I/O
when instr_FENCEI =>
-- NOT IMPLEMENTED - fence instruction stream
when instr_ECALL =>
-- Raise environment call exception
-- TODO implement me
when instr_EBREAK =>
-- NOT IMPLEMENTED - raise breakpoint exception
when instr_CSRRW =>
-- CSR read and then write
-- Write the value of the CSR to x[rd], then set the CSR to x[rs1]
RegFile_raddr <= x"0"; -- rs1 address
tempVal := RegFile_rdata;
CSRVal := CSR(to_integer(unsigned(CSR_bits)));
RegFile_waddr <= x"0";
RegFile_wdata <= CSR_read(to_integer(unsigned(CSR_bits)), CSRVal);
when instr_CSRRS =>
-- CSR read and set
-- Write the value fo the CSR to x[rd], then overwrite the CSR to the OR of the CSR value and the value of x[rs1]
-- TODO implement me
when instr_CSRRC =>
-- CSR read and clear
-- Write the value of the CSR to x[rd], get the contents of x[rs1], flip all its bits, and overwrite the CSR with the AND of its contents and the result.
-- Less insane explanation: CSR = CSR & ~x[rs1], The bits set in x[rs1] are the bits to clear in the CSR contents.
-- TODO implement me
when instr_CSRRWI =>
-- CSR read and then write immediate
-- Write the value of the CSR to x[rd], then set the CSR to the zero-extended immediate value.
-- TODO implement me
when instr_CSRRSI =>
-- CSR read and set immediate
-- Write the value of the CSR to x[rd], then overwrite the CSR to the OR of the CSR value and the (zero-extended) immediate value
-- TODO implement me
when instr_CSRRCI =>
-- CSR Read and clear immediate
-- Write the value of the CSR to x[rd], zero extend the immediate value, flip all its bits, and overwrite the CSR with the AND of its contents and the result.
-- Less insane explanation: The immediate value represents which of the 5 LSBs of the CSR should be set to zero. So zimm = "00100" means clear bit 2.
-- TODO implement me
when others =>
end case;
next_state <= normal;
end case;
end process;
end Behavioral;
| mit | bd741a6326ab04ccb0b15ff28fdf9f11 | 0.537306 | 4.373386 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/EthRx.vhd | 1 | 4,928 | -------------------------------------------------------------------------------
-- Title : Ethernet Lane
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : EthRx.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description:
-- Ethernet interface RX
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity EthRx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz clock and reset
ethClk : in sl;
ethRst : in sl;
-- Addressing
macAddr : in MacAddrType := MAC_ADDR_DEFAULT_C;
-- Connection to GT
macData : in EthMacDataType;
-- Connection to upper level ARP
arpRxOp : out slv(15 downto 0);
arpRxSenderMac : out MacAddrType;
arpRxSenderIp : out IpAddrType;
arpRxTargetMac : out MacAddrType;
arpRxTargetIp : out IpAddrType;
arpRxValid : out sl;
-- Connection to upper level IP interface
ethRxData : out slv(7 downto 0);
ethRxSenderMac : out MacAddrType;
ethRxDataValid : out sl;
ethRxDataLastByte : out sl
);
end EthRx;
architecture Behavioral of EthRx is
-- Communication between MAC and Ethernet framer
signal macRxData : slv(7 downto 0) := (others => '0');
signal macRxDataValid : sl := '0';
signal macRxDataLast : sl := '0';
signal macRxBadFrame : sl := '0';
-- Communication between Ethernet framer and higher level protocols
signal ethRxEtherType : EtherType := ETH_TYPE_INIT_C;
signal ethRxSrcMac : MacAddrType := MAC_ADDR_INIT_C;
signal ethRxDestMac : MacAddrType := MAC_ADDR_INIT_C;
signal rawEthRxData : std_logic_vector(7 downto 0);
signal rawEthRxDataValid : std_logic;
signal rawEthRxDataLast : std_logic;
begin
-- Receive into the Rx
U_MacRx : entity work.Eth1000BaseXMacRx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethRxClk => ethClk,
ethRxRst => ethRst,
-- Incoming data from the 16-to-8 mux
macDataIn => macData,
-- Outgoing bytes and flags to the applications
macRxData => macRxData,
macRxDataValid => macRxDataValid,
macRxDataLast => macRxDataLast,
macRxBadFrame => macRxBadFrame,
-- Monitoring flags
macBadCrcCount => open
);
-- Ethernet Type II Frame Receiver
U_EthFrameRx : entity work.EthFrameRx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethRxClk => ethClk,
ethRxRst => ethRst,
-- Settings from the upper level
macAddress => macAddr,
-- Incoming data from the MAC layer
macRxData => macRxData,
macRxDataValid => macRxDataValid,
macRxDataLast => macRxDataLast,
-- Outgoing data to next layer
macRxBadFrame => macRxBadFrame,
ethRxEtherType => ethRxEtherType,
ethRxSrcMac => ethRxSrcMac,
ethRxDestMac => ethRxDestMac,
ethRxData => rawEthRxData,
ethRxDataValid => rawEthRxDataValid,
ethRxDataLast => rawEthRxDataLast
);
-- ARP Packet Receiver
U_ArpPacketRx : entity work.ArpPacketRx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethRxClk => ethClk,
ethRxRst => ethRst,
-- Incoming data from Ethernet frame
ethRxSrcMac => ethRxSrcMac,
ethRxDestMac => ethRxDestMac,
ethRxData => rawEthRxData,
ethRxDataValid => rawEthRxDataValid,
ethRxDataLast => rawEthRxDataLast,
-- Received data from ARP packet
arpOp => arpRxOp,
arpSenderMac => arpRxSenderMac,
arpSenderIp => arpRxSenderIp,
arpTargetMac => arpRxTargetMac,
arpTargetIp => arpRxTargetIp,
arpValid => arpRxValid
);
-- IPv4 data out
ethRxData <= rawEthRxData when ethRxEtherType = ETH_TYPE_IPV4_C else (others => '0');
ethRxDataValid <= rawEthRxDataValid when ethRxEtherType = ETH_TYPE_IPV4_C else '0';
ethRxDataLastByte <= rawEthRxDataLast when ethRxEtherType = ETH_TYPE_IPV4_C else '0';
ethRxSenderMac <= ethRxSrcMac when ethRxEtherType = ETH_TYPE_IPV4_C else MAC_ADDR_INIT_C;
end Behavioral;
| lgpl-2.1 | d0e272ced36958cda734348b4ec3bd30 | 0.552151 | 5.171039 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_08/chiptest.vhd | 1 | 38,047 | ----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--
-- C64 ROM includes (NOT INCLUDED)
-- See python scripts for converting ROM images to VHDL files.
-- Import the generated sources into a library called "c64roms"
--
library c64roms;
use c64roms.p_char_rom.all; -- for char_rom(addr[11:0]) return byte[7:0]
use c64roms.p_basic_rom.all; -- for basic_rom(addr[12:0]) return byte[7:0]
use c64roms.p_kernal_rom.all; -- for kernal_rom(addr[12:0]) return byte[7:0]
entity chip_test is
port (
clk_125 : in std_logic;
-- audio configure
ac_scl : inout std_logic;
ac_sda : inout std_logic;
-- audio signal
ac_muten : out std_logic;
ac_mclk : out std_logic;
ac_bclk : out std_logic;
ac_pbdat : out std_logic;
ac_pblrc : out std_logic;
ac_recdat : in std_logic;
ac_reclrc : in std_logic;
-- report error in configuring audio
led : out std_logic_vector(3 downto 0);
-- to test waveforms
sw : in std_logic_vector(3 downto 0);
-- for freq/wvfm ramping tests
btn : in std_logic_vector(3 downto 0);
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end chip_test;
architecture testing of chip_test is
component clk_wiz_0
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk160 : out std_logic;
clk20ph1 : out std_logic;
clk20ph2 : out std_logic;
clk20ph3 : out std_logic;
clk20ph4 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
component clk_wiz_1
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk12 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
signal clk12 : std_logic;
signal clk160 : std_logic;
signal clk_lk1 : std_logic;
signal clk_lk2 : std_logic;
signal clk20p000 : std_logic;
signal clk20p010 : std_logic;
signal clk20p100 : std_logic;
signal clk20p110 : std_logic;
signal clk20_ph1 : std_logic;
signal clk20_ph2 : std_logic;
component blk_ram_64k
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
component blk_cram
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv5 is std_logic_vector(4 downto 0);
subtype u5 is unsigned(4 downto 0);
subtype u6 is unsigned(5 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype slv7 is std_logic_vector(6 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype slv10 is std_logic_vector(9 downto 0);
subtype slv14 is std_logic_vector(13 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype s16 is signed(15 downto 0);
subtype slv17 is std_logic_vector(16 downto 0);
subtype slv20 is std_logic_vector(19 downto 0);
subtype slv24 is std_logic_vector(23 downto 0);
subtype slv27 is std_logic_vector(26 downto 0); -- I2C SSM2603 send with ACK pads
signal res0 : std_logic;
signal res1 : std_logic;
signal cpu_r1w0 : std_logic:='1';
signal cpu_r0w1 : std_logic;
signal cpu_run : std_logic:='0';
signal cpu_rclk : std_logic;
component chip6502 is
port (
a : out std_logic_vector(15 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end component;
signal c6510_pi : byte;
signal c6510_po : byte;
signal c6510_a : word;
signal c6510_sync : std_logic;
signal c6510_rdy : std_logic;
signal c6510_irq0 : std_logic;
signal c6510_nmi0 : std_logic;
signal c6510_so0 : std_logic;
component sid6581 is
port (
res0 : in std_logic;
ph2 : in std_logic;
rga : in std_logic_vector(4 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
s16audio : out signed(15 downto 0)
);
end component;
signal bclk_cnt : pair;
alias bclk_ref : std_logic is bclk_cnt(0);--1
signal audio_frame : u6;
signal hold_srl : word;
function isZero6(tst: u6) return boolean is
begin
case tst is
when "000000" => return true;
when others => return false;
end case;
end;
function adv_frame(frm: u6) return u6 is
begin
case frm is
when "000000" => return "000001";
when "000001" => return "000010";
when "000010" => return "000011";
when "000011" => return "000100";
when "000100" => return "000101";
when "000101" => return "000110";
when "000110" => return "000111";
when "000111" => return "001000";
when "001000" => return "001001";
when "001001" => return "001010";
when "001010" => return "001011";
when "001011" => return "001100";
when "001100" => return "001101";
when "001101" => return "001110";
when "001110" => return "001111";
when "001111" => return "010000";
when "010000" => return "010001";
when "010001" => return "010010";
when "010010" => return "010011";
when "010011" => return "010100";
when "010100" => return "010101";
when "010101" => return "010110";
when "010110" => return "010111";
when "010111" => return "011000";
when "011000" => return "011001";
when "011001" => return "011010";
when "011010" => return "011011";
when "011011" => return "011100";
when "011100" => return "011101";
when "011101" => return "011110";
when "011110" => return "011111";
when "011111" => return "000000"; -- counts from 0 to 31
when "100000" => return "100001";
when "100001" => return "100010";
when "100010" => return "100011";
when "100011" => return "100100";
when "100100" => return "100101";
when "100101" => return "100110";
when "100110" => return "100111";
when "100111" => return "101000";
when "101000" => return "101001";
when "101001" => return "101010";
when "101010" => return "101011";
when "101011" => return "101100";
when "101100" => return "101101";
when "101101" => return "101110";
when "101110" => return "101111";
when "101111" => return "110000";
when "110000" => return "110001";
when "110001" => return "110010";
when "110010" => return "110011";
when "110011" => return "110100";
when "110100" => return "110101";
when "110101" => return "110110";
when "110110" => return "110111";
when "110111" => return "111000";
when "111000" => return "111001";
when "111001" => return "111010";
when "111010" => return "111011";
when "111011" => return "111100";
when "111100" => return "111101";
when "111101" => return "111110";
when "111110" => return "111111";
when "111111" => return "000000";
when others => return "000000";
end case;
end adv_frame;
signal sid1_rga : slv5;
signal sid1_dw : byte;
signal sid1_dr : byte;
signal sid1_out : s16;
signal sid1_r1w0 : std_logic;
component vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end component;
signal bankctl : slv5 := "11111";
alias exrom : std_logic is bankctl(4);
alias game : std_logic is bankctl(3);
alias charen : std_logic is bankctl(2);
alias hiram : std_logic is bankctl(1);
alias loram : std_logic is bankctl(0);
signal abus : word;
signal rama : word;
signal cpudo : byte;
signal cpudi : byte;
signal r1w0 : std_logic;
signal ram_clk : std_logic;
signal ramclk_init : std_logic := '0';
signal ramclk_cpu : std_logic := '0';
signal ramclk_vic : std_logic := '0';
signal ram_r1w0 : std_logic := '1';
signal ram_r0w1 : std_logic;
signal cram_r1w0 : std_logic := '1';
signal cram_r0w1 : std_logic;
signal ramdr : byte;
signal ramdw : byte;
signal ramen : std_logic := '1';
signal cramdr : nybble;
signal cramdw : nybble;
signal cramen : std_logic := '1';
signal vbank : pair := "00";
signal vic_rga : slv6;
signal vic_regw : byte;
signal vic_regr : byte;
signal vic_r1w0 : std_logic := '1';
signal cpu_ph1 : std_logic;
signal cpu_ph2 : std_logic;
signal vmem_clk : std_logic;
signal vic_ca : slv10;
signal vic_cd : nybble;
signal vic_wcd : nybble;
signal vic_va : slv14;
signal vic_vd : byte;
signal vic_wvd : byte;
signal cpu_on : std_logic;
signal vic_on : std_logic;
signal cpu_ph4x : std_logic;
function catoi(src: slv10) return integer is
begin
return to_integer(unsigned(src));
end catoi;
function vatoi(src: word) return integer is
begin
return to_integer(unsigned(src));
end vatoi;
function xtov6(src: byte) return slv6 is
begin
return src(5 downto 0);
end xtov6;
function xtov5(src: byte) return slv5 is
begin
return src(4 downto 0);
end xtov5;
type mbank_t is (
mbk_ram,
mbk_cram,
mbk_lorom,
mbk_hirom,
mbk_xio2,
mbk_xio1,
mbk_cia2,
mbk_cia1,
mbk_cgrom,
mbk_sid,
mbk_vic
);
function init_bank(addr:u16) return mbank_t is
begin
if (addr(15 downto 10) = "110110") then
return mbk_cram;
else
return mbk_ram;
end if;
end init_bank;
signal cur_a_bank : mbank_t;
signal cur_a_wt : std_logic;
function cpu_bank(addr: u16; bsel: slv5) return mbank_t is
variable b3 : slv3;
variable bb0 : std_logic;
variable ce : std_logic;
variable n3 : nybble;
begin
b3 := bsel(2 downto 0);
bb0 := bsel(1) nor bsel(0);
ce := bsel(2);
n3 := nybble(addr(11 downto 8));
if (addr >= x"e000") then
if (bsel(1)='1') then
return mbk_hirom;
else
return mbk_ram;
end if;
elsif (addr >= x"d000" and addr < x"e000") then
if (bb0 = '1') then
return mbk_ram;
else
if (ce = '0') then
return mbk_cgrom;
else
case n3 is
when x"f" =>
return mbk_xio2;
when x"e" =>
return mbk_xio1;
when x"d" =>
return mbk_cia2;
when x"c" =>
return mbk_cia1;
when x"b" =>
return mbk_cram;
when x"a" =>
return mbk_cram;
when x"9" =>
return mbk_cram;
when x"8" =>
return mbk_cram;
when x"7" =>
return mbk_sid;
when x"6" =>
return mbk_sid;
when x"5" =>
return mbk_sid;
when x"4" =>
return mbk_sid;
when x"3" =>
return mbk_vic;
when x"2" =>
return mbk_vic;
when x"1" =>
return mbk_vic;
when x"0" =>
return mbk_vic;
when others =>
return mbk_ram;
end case;
end if;
end if;
elsif (addr >= x"a000" and addr < x"c000") then
if ((bsel(1) and bsel(0)) = '1') then
return mbk_lorom;
else
return mbk_ram;
end if;
else
return mbk_ram;
end if;
end cpu_bank;
function bank_is_writethru(addr:word; bsel:slv5) return std_logic is
begin
case cpu_bank(u16(addr),bsel) is
when mbk_ram => return '1';
when mbk_cram => return '1';
when mbk_lorom => return '1';
when mbk_hirom => return '1';
when others => return '0';
end case;
end bank_is_writethru;
type init_t is (
initram_wait, initram_xfer, initram_idle);
signal init_stg : init_t := initram_wait;
constant init_wait_to : u16 := x"0014";
signal init_counter : u16 := x"0000";
signal init_addr : word;
signal init_data : byte;
signal init_r1w0 : std_logic := '1';
signal init_r0w1 : std_logic;
function ram_init(lin: u16) return slv24 is
begin
case lin is
when x"0000" => return x"0400" & x"08";
when x"0001" => return x"0401" & x"05";
when x"0002" => return x"0402" & x"0c";
when x"0003" => return x"0403" & x"0c";
when x"0004" => return x"0404" & x"0f";
when x"0005" => return x"0405" & x"2c";
when x"0006" => return x"0406" & x"20";
when x"0007" => return x"0407" & x"17";
when x"0008" => return x"0408" & x"0f";
when x"0009" => return x"0409" & x"12";
when x"000a" => return x"040a" & x"0c";
when x"000b" => return x"040b" & x"04";
when x"000c" => return x"040c" & x"21";
when x"000d" => return x"040d" & x"20";
when x"000e" => return x"05f2" & x"3a";
when x"000f" => return x"05f3" & x"3a";
when x"0010" => return x"05f4" & x"3a";
when x"0011" => return x"05f5" & x"3a";
when x"0012" => return x"07de" & x"30";
when x"0013" => return x"07df" & x"31";
when x"0014" => return x"07e0" & x"32";
when x"0015" => return x"07e1" & x"33";
when x"0016" => return x"07e2" & x"34";
when x"0017" => return x"07e3" & x"35";
when x"0018" => return x"07e4" & x"36";
when x"0019" => return x"07e5" & x"37";
when x"001a" => return x"07e6" & x"38";
when x"001b" => return x"07e7" & x"39";
when x"001c" => return x"d800" & x"01";
when x"001d" => return x"d801" & x"02";
when x"001e" => return x"d802" & x"03";
when x"001f" => return x"d803" & x"04";
when x"0020" => return x"d804" & x"05";
when x"0021" => return x"d805" & x"07";
when x"0022" => return x"d806" & x"0e";
when x"0023" => return x"d807" & x"08";
when x"0024" => return x"d808" & x"09";
when x"0025" => return x"d809" & x"0a";
when x"0026" => return x"d80a" & x"0b";
when x"0027" => return x"d80b" & x"0c";
when x"0028" => return x"d80c" & x"0d";
when x"0029" => return x"d80d" & x"0e";
when x"002a" => return x"d9f2" & x"01";
when x"002b" => return x"d9f3" & x"01";
when x"002c" => return x"d9f4" & x"01";
when x"002d" => return x"d9f5" & x"01";
when x"002e" => return x"dbde" & x"05";
when x"002f" => return x"dbdf" & x"07";
when x"0030" => return x"dbe0" & x"0d";
when x"0031" => return x"dbe1" & x"09";
when x"0032" => return x"dbe2" & x"08";
when x"0033" => return x"dbe3" & x"0a";
when x"0034" => return x"dbe4" & x"0b";
when x"0035" => return x"dbe5" & x"0c";
when x"0036" => return x"dbe6" & x"0f";
when x"0037" => return x"dbe7" & x"0e";
when others => return x"0000" & x"00"; -- 0 (and 1) inaccessible on C64
end case;
end ram_init;
constant ram_init_count : u16 := x"0038";
-- for initial settings for vic/sid
signal c_cycle : ubyte := x"00";
--
-- For setting the SSM2603 via I2C
--
function dac_init(lin : ubyte) return slv20 is
begin
case lin is
when x"00" => return x"06" & x"010";
when x"01" => return x"02" & x"075";
when x"02" => return x"03" & x"075";
when x"03" => return x"04" & x"010";
when x"04" => return x"05" & x"000";
when x"05" => return x"07" & x"003";
when x"06" => return x"08" & x"000";
when x"07" => return x"09" & x"001";
when x"08" => return x"06" & x"000";
when others => return x"ff" & x"fff";
end case;
end dac_init;
component i2c_xcvr port
(
-- with 1 MHz clock SSM2603 reg 9 delay step is 65.535 ms:
clk1M : in std_logic;
-- tie to system reset
res0 : in std_logic;
-- initialization line number
init_line : out unsigned(7 downto 0);
-- initialization data xRRRRRRRxxxxxxxDDDDDDDDD
init_data : in std_logic_vector(19 downto 0);
-- error status
error : out std_logic;
-- tie directly to ac_scl and ac_sda accordingly:
scl : inout std_logic;
sda : inout std_logic
);
end component;
signal ssm_init_line : ubyte;
signal ssm_init_data : slv20;
signal ssm_error : std_logic;
-- 3-bit counter for dividing 160 MHz into 8-phase 20 MHz clocks
signal clk20_ph : slv3;
function c20_next(src: slv3) return slv3 is
begin
case src is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end c20_next;
function vbk_cgrom(bk: pair; adr: slv14) return std_logic is
variable vsel : slv3;
begin
vsel := bk(0) & adr(13 downto 12);
case vsel is
when "001" => return '1';
when others => return '0';
end case;
end vbk_cgrom;
subtype u12 is unsigned(11 downto 0);
signal reset_wait : u12 := x"000";
constant reset_delay : u12 := x"0fb"; -- number of 125 MHz clocks in 2000 ns
signal cgrom_data : byte;
signal lorom_data : byte;
signal hirom_data : byte;
--
-- Architectural implementation
--
begin
--
-- Coldstart reset for 2000 ns
--
initial_reset: process(clk_125, reset_wait) is -- counts up to 2000 ns
variable not_yet : boolean;
begin
not_yet := (reset_wait < reset_delay);
if rising_edge(clk_125) then
if not_yet then
reset_wait <= reset_wait + 1;
end if;
end if;
if not_yet then -- drive reset accordingly
res0 <= '0';
else
res0 <= '1';
end if;
end process initial_reset;
pixclock: clk_wiz_0 port map (
-- Clock out ports
clk160 => clk160,
clk20ph1 => clk20p010,
clk20ph2 => clk20p100,
clk20ph3 => clk20p110,
clk20ph4 => clk20p000,
-- Status and control signals
reset => res1,
locked => clk_lk1,
-- Clock in ports
clk_in1 => clk_125
);
clk20gen: process(clk160) is
--clk20gen: process(clk20p000,clk20p010,clk20p100,clk20p110) is
variable cnext : slv3;
begin
if (rising_edge(clk160)) then
cnext := c20_next(clk20_ph);
clk20_ph <= cnext;
clk20_ph1 <= cnext(2) and (cnext(1) nor cnext(0));
clk20_ph2 <= not (cnext(2) or cnext(1) or cnext(0));
end if;
--if ( rising_edge(clk20p000)) then
-- clk20_ph <= "000";
--end if;
--if (falling_edge(clk20p000)) then
-- clk20_ph <= "001";
--end if;
--if ( rising_edge(clk20p010)) then
-- clk20_ph <= "010";
--end if;
--if (falling_edge(clk20p010)) then
-- clk20_ph <= "011";
--end if;
--if ( rising_edge(clk20p100)) then
-- clk20_ph <= "100";
--end if;
--if (falling_edge(clk20p100)) then
-- clk20_ph <= "101";
--end if;
--if ( rising_edge(clk20p110)) then
-- clk20_ph <= "110";
--end if;
--if (falling_edge(clk20p110)) then
-- clk20_ph <= "111";
--end if;
end process clk20gen;
--clk20_ph1 <= clk20p100;
--clk20_ph2 <= clk20p000;
cgrom_latch: process(rama,ram_clk) is
begin
if rising_edge(ram_clk) then
cgrom_data <= char_rom(rama(11 downto 0));
end if;
end process cgrom_latch;
lorom_latch: process(rama,ram_clk) is
begin
if rising_edge(ram_clk) then
lorom_data <= basic_rom(rama(12 downto 0));
end if;
end process lorom_latch;
hirom_latch: process(rama,ram_clk) is
begin
if rising_edge(ram_clk) then
hirom_data <= kernal_rom(rama(12 downto 0));
end if;
end process hirom_latch;
cpu: chip6502 port map (
a => c6510_a,
di => cpudi,
do => cpudo,
r1w0 => cpu_r1w0,
pi => c6510_pi,
po => c6510_po,
irq0 => c6510_irq0,
nmi0 => c6510_nmi0,
so0 => c6510_so0,
rdy => c6510_rdy,
ph4xin => cpu_rclk,
res0 => res0
);
c6510_irq0 <= '1';
c6510_nmi0 <= '1';
c6510_so0 <= '1';
c6510_rdy <= '1';
cpu_rclk <= cpu_ph4x and cpu_run;
init_ram: process(clk160,clk20_ph,init_stg) is
begin
if rising_edge(clk160) then
if (init_stg = initram_xfer and (clk20_ph >= "110" and clk20_ph <= "111")) then
init_r1w0 <= '0';
else
init_r1w0 <= '1';
end if;
if (clk20_ph = "011") then
case init_stg is
when initram_wait =>
if (init_counter = init_wait_to) then
init_counter <= x"0000";
init_stg <= initram_xfer;
init_addr <= x"ffff";
init_data <= x"ff";
else
init_counter <= init_counter + 1;
end if;
when initram_xfer =>
if (init_counter = ram_init_count) then
init_counter <= x"0000";
init_stg <= initram_idle;
else
init_addr <= ram_init(init_counter)(23 downto 8);
init_data <= ram_init(init_counter)(7 downto 0);
init_counter <= init_counter + 1;
end if;
when others =>
null;
end case;
end if;
end if;
end process init_ram;
sndclock: clk_wiz_1 port map (
-- Clock out ports
clk12 => clk12,
-- Status and control signals
reset => res1,
locked => clk_lk2,
-- Clock in ports
clk_in1 => clk_125
);
ram64: blk_ram_64k port map(
clka => ram_clk,
addra => rama,
dina => ramdw,
douta => ramdr,
wea(0) => ram_r0w1,
rsta => res1,
ena => ramen
);
color_ram: blk_cram port map(
clka => ram_clk,
addra => rama(9 downto 0),
dina => cramdw,
douta => cramdr,
wea(0) => cram_r0w1,
rsta => res1,
ena => cramen
);
res1 <= not res0;
cpu_r0w1 <= not cpu_r1w0;
ram_r0w1 <= not ram_r1w0;
cram_r0w1 <= not cram_r1w0;
init_r0w1 <= not init_r1w0;
ram_wren: process(cpu_r1w0,abus,bankctl,init_counter,init_addr,init_r1w0,init_stg,cpu_on) is
begin
if (init_stg = initram_xfer and init_counter > x"0000") then
if (init_bank(u16(init_addr)) = mbk_cram) then
cram_r1w0 <= init_r1w0;
ram_r1w0 <= '1';
else
cram_r1w0 <= '1';
ram_r1w0 <= init_r1w0;
end if;
elsif (cpu_on = '1') then
if (cpu_bank(u16(abus),bankctl) = mbk_cram) then
cram_r1w0 <= cpu_r1w0;
ram_r1w0 <= '1';
else
if (bank_is_writethru(abus,bankctl)='1') then
cram_r1w0 <= '1';
ram_r1w0 <= cpu_r1w0;
else
cram_r1w0 <= '1';
ram_r1w0 <= '1';
end if;
end if;
else
cram_r1w0 <= '1';
ram_r1w0 <= '1';
end if;
end process ram_wren;
with init_stg select ramdw <=
init_data when initram_xfer,
cpudo when others;
with init_stg select cramdw <=
init_data(3 downto 0) when initram_xfer,
cpudo(3 downto 0) when others;
abus <= c6510_a;
cur_a_bank <= cpu_bank(u16(abus),bankctl);
cur_a_wt <= bank_is_writethru(abus,bankctl);
-- CPU read data select
-- TODO: mbk_xio2,mbk_xio1,mbk_cia2,mbk_cia1
with cur_a_bank select cpudi <=
ramdr when mbk_ram,
ramdr(7 downto 4) & cramdr when mbk_cram,
vic_regr when mbk_vic,
sid1_dr when mbk_sid,
--char_rom(abus(11 downto 0)) when mbk_cgrom,
cgrom_data when mbk_cgrom,
lorom_data when mbk_lorom,
hirom_data when mbk_hirom,
ramdr when others;
ram_a_sel: process(init_stg,cpu_on,init_addr,abus,vbank,vic_va) is
begin
if (init_stg = initram_xfer) then
rama <= init_addr;
elsif (cpu_on = '1') then
rama <= abus;
else
rama <= vbank & vic_va;
end if;
end process ram_a_sel;
ram_clk_sel: process(init_stg,cpu_on,ramclk_init,ramclk_cpu,ramclk_vic) is
begin
if (init_stg = initram_xfer) then
ram_clk <= ramclk_init;
elsif (cpu_on = '1') then
ram_clk <= ramclk_cpu;
else
ram_clk <= ramclk_vic;
end if;
end process ram_clk_sel;
with clk20_ph select ramclk_init <=
'1' when "110",
'1' when "000",
'0' when others;
with clk20_ph select ramclk_vic <=
'1' when "110",
'1' when "000",
'0' when others;
with clk20_ph select ramclk_cpu <=
'1' when "110",
'1' when "000",
'0' when others;
vic: vic_ii port map(
clk20_ph1 => clk20_ph1,
clk20_ph2 => clk20_ph2,
rga => vic_rga,
rgdi => vic_regw,
rgdo => vic_regr,
r1w0 => vic_r1w0,
cpu_clk => cpu_ph4x,
cpu_ben => cpu_on,
vic_ben => vic_on,
bus_ph1 => cpu_ph1,
bus_ph2 => cpu_ph2,
va => vic_va,
vd => vic_vd,
cd => vic_cd,
res0 => res0,
vhs => vga_hs,
vvs => vga_vs,
vr => vga_r,
vg => vga_g,
vb => vga_b
);
vic_vd_sel: process(vbank,vic_va,ramdr) is
begin
if (vbk_cgrom(vbank,vic_va) = '1') then
--vic_wvd <= char_rom(vic_va(11 downto 0));
vic_wvd <= cgrom_data;
else
vic_wvd <= ramdr;
end if;
end process vic_vd_sel;
vic_wcd <= cramdr;
vic_vd <= vic_wvd;
vic_cd <= vic_wcd;
cpu_start: process(cpu_on,cpu_ph1,c_cycle) is
begin
if (cpu_on = '1' and rising_edge(cpu_ph1)) then
if ((c_cycle(7 downto 1) & '0') = x"22") then
cpu_run <= '1';
end if;
end if;
end process cpu_start;
vic_regs: process(cpu_on,cpu_ph2,c_cycle) is
begin
if (cpu_on = '1' and rising_edge(cpu_ph2)) then
case c_cycle is
when x"00" =>
vic_r1w0 <= '1';
sid1_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"01" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"02" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"03" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"04" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"05" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"06" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"07" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"08" =>
vic_rga <= xtov6(x"18");
vic_regw <= "00010100";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"09" =>
vic_rga <= xtov6(x"20");
vic_regw <= x"0e";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0a" =>
vic_rga <= xtov6(x"21");
vic_regw <= x"06";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0b" =>
vic_rga <= xtov6(x"11");
vic_regw <= x"1b";
--vic_regw <= x"17";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0c" =>
vic_rga <= xtov6(x"16");
vic_regw <= x"08";
--vic_regw <= x"07";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0d" =>
vic_rga <= xtov6(x"12");
vic_r1w0 <= '1';
sid1_rga <= xtov5(x"0e");
sid1_dw <= x"25";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0e" =>
sid1_rga <= xtov5(x"0f");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0f" =>
sid1_rga <= xtov5(x"10");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"10" =>
sid1_rga <= xtov5(x"11");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"11" =>
sid1_rga <= xtov5(x"12");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"12" =>
sid1_rga <= xtov5(x"13");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"13" =>
sid1_rga <= xtov5(x"14");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"14" =>
sid1_rga <= xtov5(x"07");
sid1_dw <= x"9a";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"15" =>
sid1_rga <= xtov5(x"08");
sid1_dw <= x"15";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"16" =>
sid1_rga <= xtov5(x"09");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"17" =>
sid1_rga <= xtov5(x"0a");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"18" =>
sid1_rga <= xtov5(x"0b");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"19" =>
sid1_rga <= xtov5(x"0c");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1a" =>
sid1_rga <= xtov5(x"0d");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1b" =>
sid1_rga <= xtov5(x"00");
sid1_dw <= x"81";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1c" =>
sid1_rga <= xtov5(x"01");
sid1_dw <= x"19";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1d" =>
sid1_rga <= xtov5(x"02");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1e" =>
sid1_rga <= xtov5(x"03");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1f" =>
sid1_rga <= xtov5(x"04");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"20" =>
sid1_rga <= xtov5(x"05");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"21" =>
sid1_rga <= xtov5(x"06");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"22" =>
sid1_rga <= xtov5(x"18");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when others =>
vic_rga <= xtov6(x"12");
vic_r1w0 <= '1';
sid1_rga <= xtov5(x"12");
sid1_dw <= sw & x"1";
sid1_r1w0 <= '0';
end case;
end if;
end process vic_regs;
sid_1: sid6581 port map (
res0 => res0,
ph2 => cpu_ph2,
rga => sid1_rga,
din => sid1_dw,
dout => sid1_dr,
r1w0 => sid1_r1w0,
s16audio => sid1_out
);
ac_muten <= res0;
ac_mclk <= clk12;
bclk_gen : process(clk12,bclk_cnt,res1) is
variable inc_0 : std_logic;
variable inc_1 : std_logic;
begin
inc_0 := not bclk_cnt(0);
inc_1 := bclk_cnt(1) xor bclk_cnt(0);
if (res1 = '1') then
bclk_cnt <= "00";
elsif (rising_edge(clk12)) then
bclk_cnt <= inc_1 & inc_0;
end if;
end process bclk_gen;
ac_bclk <= bclk_cnt(1);
audio_send : process(bclk_cnt,res1,sid1_out,hold_srl,audio_frame) is
variable stage : word;
variable frmZ : std_logic;
begin
if isZero6(audio_frame) then
stage := word(sid1_out);
frmZ := '1';
else
-- srl left-rotates to send MSB first
stage := hold_srl(14 downto 0) & hold_srl(15);
frmZ := '0';
end if;
if (res1 = '1') then
audio_frame <= "000000";
elsif (falling_edge(bclk_cnt(1))) then
if (audio_frame(4) = '0') then
-- MSB first
ac_pbdat <= stage(15);
else
-- I get a corrupt right channel if I try to
-- duplciate the data going to the left
ac_pbdat <= '0';
end if;
ac_pblrc <= audio_frame(4);
ac_pblrc <= frmZ;
hold_srl <= stage;
audio_frame <= adv_frame(audio_frame);
end if;
end process audio_send;
--
-- I2C config for SSM2603
--
i2c: component i2c_xcvr port map (
clk1M => cpu_ph2,
res0 => res0,
init_line => ssm_init_line,
init_data => ssm_init_data,
error => ssm_error,
scl => ac_scl,
sda => ac_sda
);
ssm_init_data <= dac_init(ssm_init_line);
led(0) <= ssm_error;
end testing;
| gpl-3.0 | 1d7cfbd741b2c96a75cb911272f763d3 | 0.481851 | 3.21533 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/config.vhd | 1 | 30,160 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ERROR :integer := -1; -- Not implemented, trap
constant CSR_ZERO :integer := 0; -- Not implemented, read 0, ignore write
constant CSR_FFLAGS :integer := 1;
constant CSR_FRM :integer := 2;
constant CSR_FCSR :integer := 3;
constant CSR_CYCLE :integer := 4;
constant CSR_TIME :integer := 5;
constant CSR_INSTRET :integer := 6;
constant CSR_SIE :integer := 7;
constant CSR_STVEC :integer := 8;
constant CSR_SCOUNTEREN :integer := 9;
constant CSR_SSCRATCH :integer := 10;
constant CSR_SEPC :integer := 11;
constant CSR_SCAUSE :integer := 12;
constant CSR_STVAL :integer := 13;
constant CSR_SIP :integer := 14;
constant CSR_SSTATUS :integer := 15;
constant CSR_SATP :integer := 16;
constant CSR_MSTATUS :integer := 17;
constant CSR_MISA :integer := 18;
constant CSR_MEDELEG :integer := 19;
constant CSR_MIDELEG :integer := 20;
constant CSR_MIE :integer := 21;
constant CSR_MTVEC :integer := 22;
constant CSR_MCOUNTEREN :integer := 23;
constant CSR_MSCRATCH :integer := 24;
constant CSR_MEPC :integer := 25;
constant CSR_MCAUSE :integer := 26;
constant CSR_MTVAL :integer := 27;
constant CSR_MIP :integer := 28;
constant CSR_MCYCLE :integer := 29;
constant CSR_MINSTRET :integer := 30;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector is
begin
if(unsigned(word) < 10) then
return "0011" & word;
elsif(unsigned(word) = 11) then
return "01100001";
elsif(unsigned(word) = 12) then
return "01100010";
elsif(unsigned(word) = 13) then
return "01100011";
elsif(unsigned(word) = 14) then
return "01100100";
elsif(unsigned(word) = 15) then
return "01100100";
else
return "00110000";
end if;
end;
end config;
| mit | c1ae56428133b6936e7a8f4b28722932 | 0.628614 | 3.557023 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/PCNext_Mux.vhd | 1 | 1,018 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 01:34:35 PM
-- Module Name: PCNext_Mux - Behavioral
-- Description: MUX to switch in value for PC Next
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity PCNext_Mux is
Port(
sel: in std_logic_vector(3 downto 0);
ALU_result: in word;
bootloader: in word;
branch_target: in word;
curr_PC: in word;
PC_plus_four: in word;
PC_next: out word
);
end PCNext_Mux;
architecture Behavioral of PCNext_Mux is
begin
PC_next <= ALU_result when sel = "000" else
bootloader when sel = "001" else
branch_target when sel = "010" else
curr_PC when sel = "011" else
PC_plus_four;
end Behavioral;
| mit | 38533353160f5bd8d1d1b95735d5ff4d | 0.5 | 4.138211 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/UART_TX_CTRL.vhd | 1 | 4,713 | ----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
--constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "00000000001000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
| mit | 70319ced5ca87df3921cfd8b9777e0fb | 0.570337 | 3.734548 | false | false | false | false |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/d_axi_pdm_1.2/hdl/d_axi_pdm_v1_2.vhd | 4 | 4,611 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity d_axi_pdm_v1_2 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
-- PDM
pdm_m_clk_o : out std_logic;
pdm_m_data_i : in std_logic;
pdm_lrsel_o : out std_logic;
-- PWM
pwm_audio : out std_logic;
pwm_sdaudio_o : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end d_axi_pdm_v1_2;
architecture arch_imp of d_axi_pdm_v1_2 is
-- component declaration
component d_axi_pdm_v1_2_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- PDM
pdm_m_clk_o : out std_logic;
pdm_m_data_i : in std_logic;
pdm_lrsel_o : out std_logic;
-- PWM
pwm_audio_o : out std_logic;
pwm_audio_t : out std_logic;
pwm_audio_i : in std_logic;
pwm_sdaudio_o : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component d_axi_pdm_v1_2_S_AXI;
signal pwm_audio_o : std_logic;
signal pwm_audio_i : std_logic;
signal pwm_audio_t : std_logic;
begin
-- Instantiation of Axi Bus Interface S_AXI
d_axi_pdm_v1_2_S_AXI_inst : d_axi_pdm_v1_2_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
pdm_m_clk_o => pdm_m_clk_o,
pdm_m_data_i => pdm_m_data_i,
pdm_lrsel_o => pdm_lrsel_o,
pwm_audio_o => pwm_audio_o,
pwm_sdaudio_o => pwm_sdaudio_o,
pwm_audio_t => pwm_audio,
pwm_audio_i => pwm_audio_i,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| bsd-3-clause | 1ba5ed675249def6f1dbd2c758eb4b34 | 0.607894 | 2.496481 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/IpV4Arbiter.vhd | 1 | 5,158 | ---------------------------------------------------------------------------------
-- Title : Arbiter between multiple IP interfaces
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : IpV4Arbiter.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Cycles through channels.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity IpV4Arbiter is
generic (
NUM_IP_G : integer := 1;
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl;
-- Multiple data inputs
multIpTxDataIn : in Word8Array(NUM_IP_G-1 downto 0);
multIpTxDataValid : in slv(NUM_IP_G-1 downto 0);
multIpTxDataLastByte : in slv(NUM_IP_G-1 downto 0);
multIpTxDataReady : out slv(NUM_IP_G-1 downto 0);
-- MUXed data out
ipTxData : out slv(7 downto 0);
ipTxDataValid : out sl;
ipTxDataLastByte : out sl;
ipTxDataReady : in sl
);
end IpV4Arbiter;
architecture rtl of IpV4Arbiter is
type StateType is (IDLE_S, PACKET_S);
type RegType is record
state : StateType;
channel : slv(3 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
channel => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
signal fifoWrData : slv(7 downto 0) := (others => '0');
signal fifoWrDataValid : sl := '0';
signal fifoWrDataLast : sl := '0';
signal fifoWrDataReady : sl := '0';
begin
---------------------------
-- Small buffering FIFO ---
---------------------------
U_FifoDist8x16 : entity work.fifoDist8x16
port map (
s_aclk => ethTxClk,
s_aresetn => not(ethTxRst),
s_axis_tvalid => fifoWrDataValid,
s_axis_tready => fifoWrDataReady,
s_axis_tdata => fifoWrData,
s_axis_tlast => fifoWrDataLast,
m_axis_tvalid => ipTxDataValid,
m_axis_tready => ipTxDataReady,
m_axis_tdata => ipTxData,
m_axis_tlast => ipTxDataLastByte
);
---------------------------
-- MUX the input data ---
---------------------------
mux : process(r,multIpTxDataIn,multIpTxDataValid,multIpTxDataLastByte,fifoWrDataReady) begin
fifoWrDataValid <= multIpTxDataValid(conv_integer(r.channel));
fifoWrData <= multIpTxDataIn(conv_integer(r.channel));
fifoWrDataLast <= multIpTxDataLastByte(conv_integer(r.channel));
for i in 0 to NUM_IP_G-1 loop
if i = conv_integer(r.channel) then
multIpTxDataReady(i) <= fifoWrDataReady;
else
multIpTxDataReady(i) <= '0';
end if;
end loop;
end process mux;
comb : process(r,ethTxRst,multIpTxDataIn,multIpTxDataValid,
multIpTxDataLastByte,ipTxDataReady,
fifoWrDataValid,fifoWrDataLast,fifoWrDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
-- State machine
case(r.state) is
when IDLE_S =>
if multIpTxDataValid(conv_integer(r.channel)) = '1' then
v.state := PACKET_S;
else
if r.channel < NUM_IP_G-1 then
v.channel := r.channel + 1;
else
v.channel := (others => '0');
end if;
end if;
when PACKET_S =>
if (fifoWrDataValid = '1' and
fifoWrDataLast = '1' and
fifoWrDataReady = '1') then
if r.channel < NUM_IP_G-1 then
v.channel := r.channel + 1;
else
v.channel := (others => '0');
end if;
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 52147bfd03fd31ac03eb5d7f6c4cff13 | 0.49748 | 4.461938 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/writeback.vhd | 1 | 3,579 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 01/11/2018 04:18:22 PM
-- Module Name: writeback - Behavioral
-- Description: Writeback shift register
--
-- Additional Comments:
-- This is an output buffer for the ALU stage for the control unit. This is included
-- to allow a simple two-bit control of writeback data.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity writeback is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
halt: in std_logic; -- Do nothing when high
ready_input: in std_logic; -- Control has data to be written back
ready_output: in std_logic; -- MMU is ready to accept data
output_OK: out std_logic; -- Write data and address are valid
input_OK: out std_logic; -- Read data and address recorded
input_data: in doubleword; -- Data from previous stage
input_address: in word; -- MMU Destination for input data
output_data: out doubleword; -- Data to be written to MMU
output_address: out word -- MMU destination for output data
);
end writeback;
architecture Behavioral of writeback is
-- Two states represent waiting or not waiting to dump the registers
-- Moore machine with inputs read, write, and halt, synchronous reset
type state is (state_idle, state_writing);
signal curr_state: state;
signal next_state: state;
signal last_data: doubleword;
signal last_addr: word;
signal s_output_ack: std_logic;
signal s_input_ack: std_logic;
begin
-- Advance State
process(clk, rst)
begin
if(rising_edge(clk)) then
if('1' = rst) then
curr_state <= state_idle;
else
curr_state <= next_state;
end if;
end if;
end process;
-- Compute outputs
-- Needs to be sensitive to clock in case MMU stalls, we
-- want to check for updates at each rising edge
process(clk, rst, curr_state)
begin
if(rising_edge(clk)) then
input_OK <= '0';
output_OK <= '0';
output_data <= last_data;
output_address <= last_addr;
next_state <= curr_state;
if('1' = rst) then
last_data <= (others => '0');
last_addr <= (others => '0');
output_data <= (others => '0');
output_address <= (others => '0');
next_state <= state_idle;
elsif('0' = halt) then -- Do nothing unless halt is low
case curr_state is
when state_writing => -- Case pending write
output_OK <= '1'; -- signal MMU data is valid
if('1' = ready_output) then -- Case MMU ready for data
next_state <= state_idle; -- Transition to idle state to get more input
end if;
when state_idle => -- Case no pending write
if('1' = ready_input) then -- Case control has new data
last_addr <= input_address; -- Update latches
last_data <= input_data;
input_OK <= '1'; -- signal control that data is accepted
next_state <= state_writing; -- Transition to write pending state
end if;
end case;
end if; -- rst/halt
end if; -- rising edge
end process;
end Behavioral;
| mit | 40c2bc9af8b00cd1c66d210105c6ad90 | 0.552668 | 4.215548 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/top_ROM_tb.vhd | 1 | 5,983 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/28/2018 05:30:29 PM
-- Design Name:
-- Module Name: top_system_simulation - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_ROM_tb is
-- Port ( );
end top_ROM_tb;
architecture Behavioral of top_ROM_tb is
component shell is
Port(
clk: in std_logic;
rst: in std_logic;
status: out std_logic;
DEBUG_halt: in std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- ROM / RAM lines --
MEM_addr: out std_logic_vector(26 downto 0);
MEM_data_in: out std_logic_vector(7 downto 0);
MEM_data_out: in std_logic_vector(7 downto 0);
MEM_ram: out std_logic;
MEM_write: out std_logic;
MEM_request: out std_logic;
MEM_status: in std_logic;
MEM_err: in std_logic
);
end component;
component stub_ram_int is
Port(
memAddress : in STD_LOGIC_VECTOR (26 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
valid : in STD_LOGIC;
done : out STD_LOGIC;
write : in STD_LOGIC;
chip_select : in STD_LOGIC;
err : out STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC
);
end component;
component rom_intf is
Port(
memAddress : in STD_LOGIC_VECTOR (26 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
valid : in STD_LOGIC;
done : out STD_LOGIC;
write : in STD_LOGIC;
chip_select : in STD_LOGIC;
err : out STD_LOGIC;
clk, rst : in STD_LOGIC;
-- ROM SPI signals
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0)
);
end component;
-- Signals
signal s_clk: std_logic;
signal s_rst: std_logic;
signal s_status: std_logic;
signal s_DEBUG_halt: std_logic;
signal s_cs_n: STD_LOGIC;
signal s_dq: std_logic_vector(3 downto 0);
-- LEDS out
signal s_LED: std_logic_vector(15 downto 0);
-- UART out
signal s_UART_TXD: std_logic;
signal s_UART_RXD: std_logic;
-- ROM / RAM lines --
signal s_MEM_addr: std_logic_vector(26 downto 0);
signal s_MEM_data_in: std_logic_vector(7 downto 0);
signal s_MEM_data_out: std_logic_vector(7 downto 0);
signal s_MEM_ram: std_logic;
signal s_MEM_write: std_logic;
signal s_MEM_request: std_logic;
signal s_MEM_status: std_logic;
signal s_MEM_err: std_logic;
signal s_rom_data_out: std_logic_vector(7 downto 0);
signal s_rom_done: std_logic;
signal s_rom_chip_select: std_logic;
signal s_rom_err: std_logic;
signal s_ram_data_out: std_logic_vector(7 downto 0);
signal s_ram_done: std_logic;
signal s_ram_chip_select: std_logic;
signal s_ram_err: std_logic;
begin
s_MEM_data_out <= s_ram_data_out when ( s_MEM_ram = '1' ) else s_rom_data_out;
s_MEM_status <= s_ram_done when ( s_MEM_ram = '1' ) else s_rom_done;
s_MEM_err <= s_ram_err when ( s_MEM_ram = '1' ) else s_rom_err;
s_ram_chip_select <= s_MEM_ram;
s_rom_chip_select <= not s_MEM_ram;
s_UART_RXD <= '0';
s_DEBUG_halt <= '0';
my_shell: shell
port map(
clk => s_clk,
rst => s_rst,
status => s_status,
DEBUG_halt => s_DEBUG_halt,
-- LEDS out
LED => s_LED,
-- UART out
UART_TXD => s_UART_TXD,
UART_RXD => s_UART_RXD,
-- ROM / RAM lines --
MEM_addr => s_MEM_addr,
MEM_data_in => s_MEM_data_in,
MEM_data_out => s_MEM_data_out,
MEM_ram => s_MEM_ram,
MEM_write => s_MEM_write,
MEM_request => s_MEM_request,
MEM_status => s_MEM_status,
MEM_err => s_MEM_err
);
my_ram: stub_ram_int
port map(
memAddress => s_MEM_addr,
dataIn => s_MEM_data_in,
dataOut => s_ram_data_out,
valid => s_MEM_request,
done => s_ram_done,
write => s_MEM_write,
chip_select => s_ram_chip_select,
err => s_ram_err,
clk => s_clk,
reset => s_rst
);
my_rom: rom_intf
port map(
memAddress => s_MEM_addr,
dataIn => s_MEM_data_in,
dataOut => s_rom_data_out,
valid => s_MEM_request,
done => s_rom_done,
write => s_MEM_write,
chip_select => s_rom_chip_select,
err => s_rom_err,
clk => s_clk,
rst => s_rst,
cs_n => s_cs_n,
dq => s_dq
);
process begin
s_rst <= '1';
wait for 8 ns;
s_rst <= '0';
wait;
end process;
process begin
s_clk <= '0';
wait for 5 ns;
s_clk <= '1';
wait for 5 ns;
end process;
end Behavioral;
| mit | 04bccd29f79cf356aa253994e6cb1410 | 0.510112 | 3.325737 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/ArpIpArbiter.vhd | 1 | 4,657 | ---------------------------------------------------------------------------------
-- Title : Arbiter between ARP and IPv4
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ArpIpArbiter.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Prioritizes responding to ARP requests.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity ArpIpArbiter is
generic (
GATE_DELAY_G : in time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl;
-- ARP request/ack, data interface
arpTxReq : in sl;
arpTxAck : in sl;
arpTxData : in slv(7 downto 0);
arpTxDataValid : in sl;
arpTxDataLastByte : in sl;
arpTxDataReady : out sl;
-- IPv4 request/ack, data interface
ipTxData : in slv(7 downto 0);
ipTxDataValid : in sl;
ipTxDataLastByte : in sl;
ipTxDataReady : out sl;
-- Output MUXed data
ethTxEtherType : out EtherType;
ethTxData : out slv(7 downto 0);
ethTxDataValid : out sl;
ethTxDataLastByte : out sl;
ethTxDataReady : in sl
);
end ArpIpArbiter;
architecture rtl of ArpIpArbiter is
type StateType is (IDLE_S, WAIT_ARP_S, WAIT_IP_S, FINISH_ARP_S);
type RegType is record
state : StateType;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethTxRst,arpTxReq,arpTxAck,arpTxData,arpTxDataValid,arpTxDataLastByte,
ipTxData,ipTxDataValid,ipTxDataLastByte,ethTxDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
ethTxEtherType <= (others => '0');
ethTxData <= (others => '0');
ethTxDataValid <= '0';
ethTxDataLastByte <= '0';
arpTxDataReady <= '0';
ipTxDataReady <= '0';
-- State machine
case(r.state) is
-- Ready should be zero for all possible output types
-- If we see an ARP request, go ahead with it
-- (if we want to add ICMP, put it here)
-- Otherwise, default to IP data
when IDLE_S =>
if (arpTxReq = '1') then
v.state := WAIT_ARP_S;
elsif ipTxDataValid = '1' then
v.state := WAIT_IP_S;
end if;
when WAIT_ARP_S =>
ethTxEtherType <= ETH_TYPE_ARP_C;
ethTxData <= arpTxData;
ethTxDataValid <= arpTxDataValid;
ethTxDataLastByte <= arpTxDataLastByte;
arpTxDataReady <= ethTxDataReady;
if arpTxAck = '1' then
v.state := FINISH_ARP_S;
end if;
when WAIT_IP_S =>
ethTxEtherType <= ETH_TYPE_IPV4_C;
ethTxData <= ipTxData;
ethTxDataValid <= ipTxDataValid;
ethTxDataLastByte <= ipTxDataLastByte;
ipTxDataReady <= ethTxDataReady;
-- Byte was valid, last, and accepted
if ipTxDataValid = '1' and ipTxDataLastByte = '1' and ethTxDataReady = '1' then
v.state := IDLE_S;
end if;
when FINISH_ARP_S =>
if arpTxReq = '0' then
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 2fb16dc78b89ead640faee84ce29efe1 | 0.509341 | 4.592702 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/UdpBufferTx.vhd | 1 | 9,917 | ---------------------------------------------------------------------------------
-- Title : UDP Packet Buffer and Transmitter
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : UdpBufferTx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Arbitrary 32-bit data input accepted from user clock domain.
-- Data is read out in the ethernet 125 MHz domain.
-- Buffers up an entire UDP packet (so that it
-- can generate header information), and then interfaces to the UdpTxFragmenter,
-- which breaks the data up into MTU-size chunks.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity UdpBufferTx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- User clock and reset (for writes to FIFO)
userClk : in sl;
userRst : in sl;
-- 125 MHz clock and reset (for reads from FIFO, interface to Eth blocks)
ethTxClk : in sl;
ethTxRst : in sl := '0';
-- User data interfaces
userData : in slv(31 downto 0);
userDataValid : in sl;
userDataLast : in sl;
userDataReady : out sl;
-- UDP settings
udpSrcPort : in slv(15 downto 0);
udpDstPort : in slv(15 downto 0);
-- Inputs for calculating checksums
ipSrcAddr : in IpAddrType;
ipDstAddr : in IpAddrType;
-- UDP fragmenter interfaces
udpData : out slv(31 downto 0);
udpDataValid : out sl;
udpDataReady : in sl;
udpLength : out slv(15 downto 0);
udpReq : out sl;
udpAck : in sl
);
end UdpBufferTx;
architecture rtl of UdpBufferTx is
type UserStateType is (IDLE_S, COUNTING_S);
type UserRegType is record
state : UserStateType;
payloadBytes : slv(15 downto 0);
sizeWrEn : sl;
end record UserRegType;
constant USER_REG_INIT_C : UserRegType := (
state => IDLE_S,
payloadBytes => (others => '0'),
sizeWrEn => '0'
);
signal rUser : UserRegType := USER_REG_INIT_C;
signal rinUser : UserRegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of rUser : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of rUser : signal is "true";
type EthStateType is (WAIT_PACKET_S,
HEADER_0_S, HEADER_1_S, READ_DATA_S);
type EthRegType is record
state : EthStateType;
ipSrcAddr : IpAddrType;
ipDstAddr : IpAddrType;
udpSrcPort : slv(15 downto 0);
udpDstPort : slv(15 downto 0);
udpData : slv(31 downto 0);
udpDataValid : sl;
udpLength : slv(15 downto 0);
udpReq : sl;
sizeFifoRdEn : sl;
bytesLeft : slv(15 downto 0);
udpFifoRdEn : sl;
end record EthRegType;
constant ETH_REG_INIT_C : EthRegType := (
state => WAIT_PACKET_S,
ipSrcAddr => IP_ADDR_INIT_C,
ipDstAddr => IP_ADDR_INIT_C,
udpSrcPort => (others => '0'),
udpDstPort => (others => '0'),
udpData => (others => '0'),
udpDataValid => '0',
udpLength => (others => '0'),
udpReq => '0',
sizeFifoRdEn => '0',
bytesLeft => (others => '0'),
udpFifoRdEn => '0'
);
signal rEth : EthRegType := ETH_REG_INIT_C;
signal rinEth : EthRegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of rEth : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of rEth : signal is "true";
-- Other signals used for interfacing to sub-blocks
signal udpFifoAlmostFull : sl;
signal udpFifoWrEn : sl;
signal udpFifoRdData : slv(31 downto 0);
signal udpFifoRdDataValid : sl;
signal udpFifoEmpty : sl;
signal udpFifoRdEn : sl;
signal sizeFifoEmpty : sl;
signal sizeFifoRdData : slv(15 downto 0);
signal sizeFifoAlmostFull : sl;
begin
-- UDP data gets written into this FIFO from
-- user clock domain, read out in ethernet clock
-- domain.
-- This fifo has FWFT enabled.
U_Udp64KFifo : entity work.udp64kfifo
port map (
rst => userRst,
wr_clk => userClk,
rd_clk => ethTxClk,
din => userData,
wr_en => udpFifoWrEn,
rd_en => udpFifoRdEn,
dout => udpFifoRdData,
full => open,
almost_full => udpFifoAlmostFull,
empty => udpFifoEmpty,
valid => udpFifoRdDataValid
);
userDataReady <= not(udpFifoAlmostFull) and not(sizeFifoAlmostFull);
udpFifoWrEn <= not(udpFifoAlmostFull) and not(sizeFifoAlmostFull) and userDataValid;
U_UdpSizeFifo : entity work.fifo16x64
port map (
rst => userRst,
wr_clk => userClk,
rd_clk => ethTxClk,
din => rUser.payloadBytes,
wr_en => rUser.sizeWrEn,
rd_en => rEth.sizeFifoRdEn,
dout => sizeFifoRdData,
full => open,
almost_full => sizeFifoAlmostFull,
empty => sizeFifoEmpty
);
------------------------------------------------
combUser : process(rUser,userRst,userData,userDataValid,userDataLast,
udpFifoAlmostFull, udpFifoWrEn) is
variable v : UserRegType;
begin
v := rUser;
-- Set defaults / reset any pulsed signals
v.sizeWrEn := '0';
-- State machine
case(rUser.state) is
when IDLE_S =>
v.payloadBytes := (others => '0');
if udpFifoWrEn = '1' then
v.payloadBytes := x"0004";
if userDataLast = '1' then
v.sizeWrEn := '1';
v.state := IDLE_S;
else
v.state := COUNTING_S;
end if;
end if;
when COUNTING_S =>
if udpFifoWrEn = '1' then
v.payloadBytes := rUser.payloadBytes + 4;
if userDataLast = '1' then
v.sizeWrEn := '1';
v.state := IDLE_S;
end if;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (userRst = '1') then
v := USER_REG_INIT_C;
end if;
-- Outputs to ports
-- Assign variable to signal
rinUser <= v;
end process combUser;
seqUser : process (userClk) is
begin
if (rising_edge(userClk)) then
rUser <= rinUser after GATE_DELAY_G;
end if;
end process seqUser;
------------------------------------------------
combEth : process(rEth,ethTxRst,udpSrcPort,udpDstPort,ipSrcAddr,ipDstAddr,
udpDataReady, udpAck, udpFifoRdData, udpFifoRdDataValid,
sizeFifoEmpty, sizeFifoRdData) is
variable v : EthRegType;
begin
v := rEth;
-- Set defaults / reset any pulsed signals
v.sizeFifoRdEn := '0';
v.udpFifoRdEn := '0';
udpDataValid <= '0';
udpFifoRdEn <= '0';
udpData <= (others => '0');
-- State machine
case(rEth.state) is
when WAIT_PACKET_S =>
if sizeFifoEmpty = '0' then
v.ipSrcAddr := ipSrcAddr;
v.ipDstAddr := ipDstAddr;
v.udpSrcPort := udpSrcPort;
v.udpDstPort := udpDstPort;
v.udpLength := sizeFifoRdData + 8;
v.bytesLeft := sizeFifoRdData - 4;
v.sizeFifoRdEn := '1';
v.state := HEADER_0_S;
end if;
when HEADER_0_S =>
udpData <= rEth.udpSrcPort & rEth.udpDstPort;
udpDataValid <= '1';
if udpDataReady = '1' then
v.state := HEADER_1_S;
end if;
when HEADER_1_S =>
udpData <= rEth.udpLength & x"0000";
udpDataValid <= '1';
if udpDataReady = '1' then
v.state := READ_DATA_S;
end if;
when READ_DATA_S =>
udpData <= udpFifoRdData;
udpDataValid <= udpFifoRdDataValid;
udpFifoRdEn <= udpDataReady and udpFifoRdDataValid;
if udpFifoRdDataValid = '1' and udpDataReady = '1' then
v.bytesLeft := rEth.bytesLeft - 4;
if rEth.bytesLeft = 0 then
v.state := WAIT_PACKET_S;
end if;
end if;
when others =>
v.state := WAIT_PACKET_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := ETH_REG_INIT_C;
end if;
-- Outputs to ports
-- udpData <= rEth.udpData;
-- udpDataValid <= rEth.udpDataValid;
udpLength <= rEth.udpLength;
udpReq <= rEth.udpReq;
-- Assign variable to signal
rinEth <= v;
end process combEth;
seqEth : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
rEth <= rinEth after GATE_DELAY_G;
end if;
end process seqEth;
end rtl;
| lgpl-2.1 | 7cced9da568fe15ebf90581fc9b3d62f | 0.506403 | 4.463096 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/load_store.vhd | 1 | 4,229 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 02:45:16 PM
-- Module Name: load_store - Behavioral
-- Description: Handles loading, storing, and signalling between core, control, and MMU
--
-- Additional Comments:
-- If storing, addr will be the MMU destination address and data will be the data to be written there
-- If loading, addr will be the MMU source address and data will be an encoding of the number of bytes to load
-- Encoding is as follows:
-- One byte (LB, LBU) -> 0x0
-- Two bytes (LH, LHU) -> 0x1
-- Four bytes (LW, LWU) -> 0x2
-- Eight bytes (LD) -> 0x3
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
-- If loading, we need to know:
-- Memory address to load from (register file holds base, instruction holds offset
-- Register address to load to
-- If storing, we need to know:
-- Register address to store from
-- Memory address to store to (register file holds base, instruction holds offset
entity load_store is
Port(
instr: in instr_t; -- Current instruction type
imm12: in std_logic_vector(11 downto 0); -- offset value
rs1: in reg_t; -- rs1 for S-type and I-type
rs2: in reg_t; -- rs2 for S-type
addr: out doubleword; -- Destination address
data: out doubleword -- Data to be stored
);
end load_store;
architecture Behavioral of load_store is
-- Latch for modifying data and address piecewise
signal s_data: doubleword;
signal s_addr: doubleword;
begin
process(instr)
begin
-- Encoding for load data is as follows:
-- One byte (LB, LBU) -> 0x0
-- Two bytes (LH, LHU) -> 0x1
-- Four bytes (LW, LWU) -> 0x2
-- Eight bytes (LD) -> 0x3
case instr is
when instr_LB =>
-- Load byte
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data <= (others => '0');
when instr_LBU =>
-- Load byte, unsigned
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data <= (others => '0');
when instr_LD =>
-- Load doubleword
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data <= (1 downto 0 => '1', others => '0');
when instr_LH =>
-- Load half word
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data <= (0 => '1', others => '0');
when instr_LHU =>
-- Load half word, unsigned
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data <= (0 => '1', others => '0');
when instr_LW =>
-- Load word
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data <= (1 => '1', others => '0');
when instr_LWU =>
-- Load word, unsigned
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data <= (1 => '1', others => '0');
when instr_SB =>
-- Store byte
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data(63 downto 8) <= (others => '0');
s_data(7 downto 0) <= rs2(7 downto 0);
when instr_SD =>
-- Store doubleword
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data <= rs2;
when instr_SH =>
-- Store half word
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data(63 downto 16) <= (others => '0');
s_data(15 downto 0) <= rs2(15 downto 0);
when instr_SW =>
-- Store word
s_addr <= std_logic_vector(signed(rs1) + signed(imm12));
s_data(63 downto 32) <= (others => '0');
s_data(31 downto 0) <= rs2(31 downto 0);
when others =>
s_addr <= (others => '0');
s_data <= (others => '0');
end case;
data <= s_data;
addr <= s_addr;
end process;
end Behavioral;
| mit | a22312cb6a31f2c338762ffaf3062f4a | 0.520218 | 3.725991 | false | false | false | false |
gau-veldt/InsideTheBox | Ep0003/AudioEcho_NACK.vhd | 1 | 10,988 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/14/2017 12:34:40 AM
-- Design Name:
-- Module Name: AudioEcho - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AudioEcho is
port (
led : out std_logic_vector(3 downto 0); -- Pretty light show for debugging stuff
clk_125 : in std_logic; -- 125 MHz Zybo clock
ac_sda : inout std_logic; -- I2C data
ac_scl : inout std_logic -- I2C clock
);
end AudioEcho;
architecture Driver of AudioEcho is
signal led_st : std_logic_vector(3 downto 0) := "0000"; -- output register for leds
subtype tCount is unsigned(31 downto 0); -- type alias: 32-bit unsigned integer
constant cZero : tCount := to_unsigned(0,tCount'length); -- zero constant
constant cMod : tCount := to_unsigned(2,tCount'length); -- 2/cMod is divider period in seconds
constant cMax : tCount := to_unsigned(125000000,tCount'length); -- input clock frequency constant
signal my_clk : std_logic := '0'; -- divider output
signal r_sda_i : std_logic := '1'; -- I2C sda input register
signal r_sda_o : std_logic := '1'; -- I2C sda output register
signal r_scl_i : std_logic := '1'; -- I2C scl input register
signal r_scl_o : std_logic := '1'; -- I2C scl output register
-- enumeration of audio configuration state machine states
type ac_states is (
acsInit,
acsStart,
acsA7pre,
acsA7set,
acsA7out,
acsA6pre,
acsA6set,
acsA6out,
acsA5pre,
acsA5set,
acsA5out,
acsA4pre,
acsA4set,
acsA4out,
acsA3pre,
acsA3set,
acsA3out,
acsA2pre,
acsA2set,
acsA2out,
acsA1pre,
acsA1set,
acsA1out,
acsWpre,
acsWset,
acsWout,
acsWACKpre,
acsWACKfloat,
acsWACKclk,
acsWACKtest,
acsStop,
acsForceStop,
acsForceStop2,
acsForceStop3,
acsSpin
);
signal ac_state : ac_states := acsInit;
signal ac_good : std_logic := '0';
begin
-- clock divider
divider: process(clk_125) is
variable dCur : tCount := cZero;
begin
if (rising_edge(clk_125)) then
dCur:=dCur+cMod;
if (dCur >= cMax) then
dCur := dCur - cMax;
my_clk <= not my_clk;
end if;
end if;
end process divider;
-- state machine for I2C
audioconf : process(my_clk) is
begin
-- NB: On the Zybo board only two slaves (EEPROM and SSM2603)
-- are present on the I2C bus thus we are the only master
-- in the system thus there is no need for arbitration logic.
if (rising_edge(my_clk)) then
case ac_state is
-- Initial state
when acsInit =>
-- Use a counter to pause the minimum initialization
-- duration before transitioning to starting condition.
ac_state <= acsStart;
-- Starting condition
when acsStart =>
if (r_scl_i='1' and r_sda_i='1') then
-- signal START on the bus
r_sda_o<='0';
ac_state <= acsA7pre;
else
-- still waiting for SCL=1 and SDA=1
ac_state <= acsStart;
end if;
-- each bit sent takes three states
-- since for I2C it is required to transition SDA
-- *after* the SCL low edge and not at the same
-- time (a device might register SDA before our
-- clock in that event and misinterpret a STOP
-- signal if SDA becomes 1 on this cycle when SDA
-- was 0 on the previous cycle since we'd have
-- set SCL to 1 to transmit that bit).
when acsA7pre => -- Call SSM2603 address for write (R=1, W=0):
r_scl_o<='0'; -- 0 0 1 1 0 1 0 W
ac_state<=acsA7set;
when acsA7set =>
r_sda_o<='0'; -- 0
ac_state<=acsA7out;
when acsA7out =>
r_scl_o<='1';
ac_state <= acsA6pre;
when acsA6pre =>
r_scl_o<='0';
ac_state<=acsA6set;
when acsA6set =>
r_sda_o<='0'; -- - 0
ac_state<=acsA6out;
when acsA6out =>
r_scl_o<='1';
ac_state <= acsA5pre;
when acsA5pre =>
r_scl_o<='0';
ac_state<=acsA5set;
when acsA5set =>
r_sda_o<='1'; -- - - 1
ac_state<=acsA5out;
when acsA5out =>
r_scl_o<='1';
ac_state <= acsA4pre;
when acsA4pre =>
r_scl_o<='0';
ac_state<=acsA4set;
when acsA4set =>
r_sda_o<='1'; -- - - - 1
ac_state<=acsA4out;
when acsA4out =>
r_scl_o<='1';
ac_state <= acsA3pre;
when acsA3pre =>
r_scl_o<='0';
ac_state<=acsA3set;
when acsA3set =>
r_sda_o<='0'; -- - - - - 0
ac_state<=acsA3out;
when acsA3out =>
r_scl_o<='1';
ac_state <= acsA2pre;
when acsA2pre =>
r_scl_o<='0';
ac_state<=acsA2set;
when acsA2set =>
r_sda_o<='1'; -- - - - - - 1
ac_state<=acsA2out;
when acsA2out =>
r_scl_o<='1';
ac_state <= acsA1pre;
when acsA1pre =>
r_scl_o<='0';
ac_state<=acsA1set;
when acsA1set =>
-- should be 0 thus we'll be sending the bogus address 0011011 thus
-- no device will respond so we'll have the negative-acknowledge case
r_sda_o<='1'; -- - - - - - - 0
ac_state<=acsA1out;
when acsA1out =>
r_scl_o<='1';
ac_state <= acsWpre;
when acsWpre =>
r_scl_o<='0';
ac_state<=acsWset;
when acsWset =>
r_sda_o<='0'; -- - - - - - - - W
ac_state<=acsWout;
when acsWout =>
r_scl_o<='1';
ac_state <= acsWACKpre;
-- On the ackknowledge there's a similar pattern
-- first we'll lower the clock THEN float SDA
-- THEN raise the clock THEN test SDA for
-- ACK/NACK. THENs mean delay is necessary
-- thus requiring a different state for each
-- step so they span different clock cycles
when acsWACKpre =>
r_scl_o<='0'; -- lower clock
ac_state<=acsWACKfloat;
when acsWACKfloat =>
r_sda_o<='1'; -- SDA floats to 1
ac_state<=acsWACKclk;
when acsWACKclk =>
r_scl_o<='1'; -- raise clock
ac_state<=acsWACKtest;
when acsWACKtest =>
-- if all is right SDA should be low at this point
-- We sent bogus address so it will still be high
-- this is a negative-acknowledge (NACK).
if (r_sda_i='0') then
-- we won't get here so LED will stay off
ac_good<='1';
end if;
ac_state<=acsForceStop;
-- forcibly stop:
-- lower SCL
-- lower SDA
-- raise SCL (first three transitions ensure the STOP precondition SCL high, SDA low)
-- raise SDA (STOP = "transition of SDA from 0 to 1 when SCL is high")
when acsForceStop =>
r_scl_o<='0';
ac_state <= acsForceStop2;
when acsForceStop2 =>
r_sda_o<='0';
ac_state <= acsForceStop3;
when acsForceStop3 =>
r_scl_o<='1';
ac_state <= acsStop;
when acsStop =>
r_sda_o<='1';
ac_state <= acsSpin;
-- Halted (infinite loop)
when acsSpin =>
ac_state <= acsSpin;
-- Catch-all: enter halted state
when others =>
ac_state <= acsSpin;
end case;
end if;
end process audioconf;
-- i2c output registers to i2c lines
with r_sda_o select
ac_sda <= '0' when '0', -- generate the 0 level (pulls down to ground)
'Z' when others; -- allows bus pull-up to generate the 1 level
with r_scl_o select
ac_scl <= '0' when '0', -- generate the 0 level (pulls down to ground)
'Z' when others; -- allows bus pull-up to generate the 1 level
-- i2c lines to i2c input registers
with ac_sda select
r_sda_i <= '0' when '0',
'1' when others;
with ac_scl select
r_scl_i <= '0' when '0',
'1' when others;
-- transfer led output register to led output lines
led_st(0) <= r_sda_i;
led_st(1) <= r_scl_i;
led_st(2) <= ac_good;
led_st(3) <= my_clk;
led <= led_st;
end Driver;
| gpl-3.0 | 17d75c954717e2c0f5a47a9a9f44ac73 | 0.441846 | 4.353407 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/MMU.vhd | 1 | 27,163 | ----------------------------------------------------------------------------------
-- Engineer: Cesar Avalos B
-- Create Date: 01/28/2018 07:53:02 PM
-- Module Name: MMU_stub - Behavioral
-- Description: Full flegded MMU to feed instructions and store data, supports SV39
--
-- Additional Comments: Mk. VIII
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.VCOMPONENTS.ALL;
entity MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic := '0'; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out doubleword; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);-- Error
page_fault: out std_logic; -- High when page fault
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- Debug Signals
-- This pragma crap is the equivalent of ifdef in C
--pragma synthesis_off
fkuck_vivado_so_much: out std_logic_vector(5 downto 0);
s_internal_address_out: out doubleword;
--pragma synthesis_on
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end MMU;
architecture Behavioral of MMU is
-- Components
component ram_controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
write, read: in STD_LOGIC;
done: out STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end component;
component ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
address_in: in STD_LOGIC_VECTOR(23 downto 0);
qd: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(31 downto 0);
--pragma synthesis_off
counter: out integer;
--pragma synthesis_on
-- command_int, address_int, reg_one_int, reg_two_int: inout integer;
done: out STD_LOGIC
);
end component;
component clk_wiz_0
port(
clk_in1 : in std_logic;
clk_100MHz_o: out std_logic;
clk_200MHz_o: out std_logic;
clk_25MHz_o: out std_logic;
locked: out std_logic);
end component;
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
type instsmem is array(0 to 100) of doubleword;
signal instr_mem: instsmem := (0 => X"00000000480017b7", 1 => "0000000000000000000000000000000000000000000101111001011100010011", 2 => "0000000000000000000000000000000000000000101100000000010110010011", 3 => "0000000000000000000000000000000000000000101101110011000000100011", 4 => "0000000000000000000000000000000000000000101100000000010110010011", 5 => "0000000000000000000000000000000000000000101100000000010110010011", 6=> X"0000000005200513", others => (others => '0'));
-- SPI signals
signal io_flash_en: std_logic;
signal io_flash_write: std_logic;
signal io_quad_io: std_logic_vector(3 downto 0);
signal io_flash_addr: std_logic_vector(23 downto 0);
signal io_flash_data_in: std_logic_vector(31 downto 0);
signal io_flash_data_out: std_logic_vector(31 downto 0);
signal io_read_id: std_logic;
signal io_state_to_cpu: std_logic_vector(11 downto 0);
signal io_SI, io_WP, io_tri_si, io_tri_wp, io_cs, io_ready: std_logic;
signal io_srl, io_cr : std_logic_vector(7 downto 0);
signal io_sckgate: std_logic;
signal io_rst: std_logic;
type MMU_state is (idle, loading, storing, fetching, decode_state,page_walk,loading_ram_page_walk, loading_ram, loading_rom, done_uart_rx, done_uart_tx, storing_ram);
signal curr_state: MMU_state := idle;
signal next_state: MMU_state := idle;
--signal paused_state : MMU_state := idle; --Bit of a misnomer, this is
signal LED_reg: std_logic_vector(15 downto 0);
-- RAM signals
signal w_en: std_logic := '0';
signal RAM_en, ROM_en: std_logic := '0';
type RAM_state is (idle, read_low, read_low_mid, read_upper_mid, read_upper,write_low, write_low_mid, write_upper_mid, write_upper, done);
signal RAM_curr_state : RAM_state := idle;
signal RAM_next_state : RAM_state := idle;
signal RAM_masks: std_logic_vector(7 downto 0);
signal RAM_timeout_counter: integer:= 0;
signal RAM_data_in: std_logic_vector(15 downto 0);
signal RAM_data_out: std_logic_vector(15 downto 0);
signal RAM_address_in: std_logic_vector(26 downto 0);
signal s_RAM_data_out: doubleword := (others => '0'); -- The register holding the ram doubleword
signal ROM_done, RAM_done: std_logic := '0';
signal BRAM_toggle : std_logic_vector(1 downto 0) := "00";
--32 Bits acceses for ROM, either, too slow
type ROM_state is (idle, reading_lower, reading_higher, done);
signal ROM_curr_state : ROM_state := idle;
signal ROM_next_state : ROM_state := idle;
signal gated_clk: std_logic := '0';
signal s_ROM_data_out: doubleword := (others => '0'); --Register holding the rom doubleword
signal ROM_address_in : std_logic_vector(23 downto 0);
signal s_ROM_done: std_logic;
-- UART out data signal, for reading UART registers
signal UART_out: STD_LOGIC_VECTOR(7 downto 0);
signal UART_toggle : std_logic := '0';
signal SATP_mode: std_logic_vector(63 downto 0) := (others => '0');
signal SATP_PPN: std_logic_vector(63 downto 0) := (others => '0');
signal s_internal_data : std_logic_vector(63 downto 0);
signal s_internal_address: doubleword;
signal clk_100, clk_200, clk_25, locked: std_logic;
signal page_address_in: doubleword := (others => '0');
signal uart_data_in, uart_data_out: std_logic_vector(7 downto 0);
signal uart_data_available, uart_ready: std_logic;
signal uart_reset_read, uart_send: std_logic;
signal UART_data: doubleword;
signal m_timer: integer := 0;
Type PAGE_WALK_STATE is (idle,level_i_read, level_i_decode, done);
signal PAGE_WALK_next_state, PAGE_WALK_current_state: PAGE_WALK_STATE := idle;
signal s_page_walk,page_walk_request_read, page_walk_done: std_logic := '0';
signal page_walk_address_out, page_address_final: doubleword;
signal Intermitent_Address_In: doubleword;
signal addr_in_latch: doubleword;
-- Debugging
signal s_fuck_vivado_so_much: std_logic_vector(5 downto 0);
signal qd: std_logic_vector(3 downto 0);
signal gated_clock, clock_gate: std_logic;
begin
clk_wizard: clk_wiz_0
port map(
clk_in1 =>clk,
clk_100MHz_o => clk_100,
clk_200MHz_o => clk_200,
clk_25MHz_o => clk_25,
locked => locked
);
myRAMController: ram_controller port map
(
clk_200 => clk_200,
clk_100 => clk_100,
rst => rst,
data_in => RAM_data_in,
data_out => RAM_data_out,
done => RAM_done,
write => w_en,
read => RAM_en,
contr_addr_in => RAM_address_in,
ddr2_addr => ddr2_addr ,
ddr2_ba => ddr2_ba ,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n ,
ddr2_ck_p => ddr2_ck_p ,
ddr2_ck_n => ddr2_ck_n ,
ddr2_cke => ddr2_cke ,
ddr2_cs_n => ddr2_cs_n ,
ddr2_dm => ddr2_dm ,
ddr2_odt => ddr2_odt ,
ddr2_dq => ddr2_dq ,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n
);
myROMController: ROM_controller_SPI port map(clk_25 => clk_25, rst => io_rst, read =>io_flash_en,
address_in => ROM_address_in, data_out => io_flash_data_out,
si_i =>io_SI, wp => io_WP, si_t => io_tri_si, wp_t => io_tri_wp,
cs_n => io_cs, qd => io_quad_io, done =>s_ROM_done);
myUARTTX: UART_TX_CTRL port map
(
SEND => uart_send,
DATA => uart_data_out,
CLK => CLK,
READY => uart_ready,
UART_TX => UART_TXD
);
myUARTRX: UART_RX_CTRL port map
(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => uart_data_available,
RESET_READ => uart_reset_read
);
-- Advance state
STATE_ADVANCE: process(clk, rst, RAM_done, ROM_done)
begin
if('1' = rst) then
curr_state <= idle;
ROM_curr_state <= idle;
RAM_curr_state <= idle;
PAGE_WALK_current_state <= idle;
m_timer <= 0;
elsif(rising_edge(clk)) then
curr_state <= next_state;
RAM_curr_state <= RAM_next_state;
ROM_curr_state <= ROM_next_state;
PAGE_WALK_current_state <= PAGE_WALK_next_state;
m_timer <= m_timer + 1;
end if;
end process;
MMU_FSM: process(clk, rst, curr_state)
-- variable s_internal_address: doubleword := (others => '0'); --Realized Physical Address
variable paused_state: MMU_state; -- When we find the mode from SATP, we resume from the state saved here
begin
if rst = '1' then
instr_out <= (others => '0');
error <= (others => '0');
io_flash_write <= '0';
io_read_id <= '0';
next_state <= idle;
-- LED <= (others => '0');
busy <= '0';
BRAM_toggle <= "11";
elsif(rising_edge(clk)) then
busy <= '1';
next_state <= curr_state;
case curr_state is
-- Idling by like the leech you are MMU arent U
when idle =>
busy <= '1';
s_fuck_vivado_so_much <= "000000";
s_internal_address <= addr_in;
if(load = '1') then
next_state <= decode_state;
paused_state := loading;
elsif(store = '1') then
next_state <= decode_state;
paused_state := storing;
elsif(ready_instr = '1') then
next_state <= decode_state;
s_internal_address <= addr_instr;
paused_state := fetching;
else
busy <= '0';
end if;
-- Figure out what state are we at
when decode_state =>
s_fuck_vivado_so_much <= "000001";
case satp_mode(3 downto 0) is
when x"0" => -- No translation is assumed
next_state <= paused_state;
when others =>
next_state <= page_walk; --SV39 is assumed whenever anything else is written, no SV48 shenanigans
end case;
-- Walk the thing blue page walk line
when page_walk =>
s_fuck_vivado_so_much <= "000010";
s_page_walk <= '1'; --We enable the page walk process
if(page_walk_done = '1') then --Page walk is done
s_internal_address <= page_walk_address_out; -- We assign the newly discovered address
next_state <= paused_state; --Resume wherever we left off matey
elsif(page_walk_request_read = '1') then
RAM_en <= '1';
end if;
-- Intermediate fetching state, just check if there is any misalignment errors
when fetching =>
busy <= '1';
s_fuck_vivado_so_much <= "000011";
--Fetches have to be aligned
if(unsigned(s_internal_address) mod 8 > 0) then
error(4) <= '1'; -- Misaligned error, geback geback
next_state <= idle;
elsif( s_internal_address(31 downto 16) = x"0000" ) then
next_state <= idle;
instr_out <= instr_mem(to_integer(unsigned(addr_instr))/8);
else
next_state <= loading; --Loading instructions from elsewhere
end if;
-- Loading states
when loading =>
s_fuck_vivado_so_much <= "000100";
if(s_internal_address(31 downto 16) = x"0000" ) then --BRAM
next_state <= idle; --Instruction already goes out here, so no need to do anything,
-- We do this to preserve the instr_out port, even though it's really not necesary.
elsif(s_internal_address(31 downto 16) = x"9801") then --UART Registers
next_state <= idle; -- By default go to idle
busy <= '0';
case s_internal_address(3 downto 0) is
when X"0" => UART_data(7 downto 0) <= uart_data_in;
when X"1" => UART_data(0) <= uart_data_available;
when X"2" => UART_data(0) <= uart_reset_read;
when X"3" => UART_data(7 downto 0) <= uart_data_out;
when X"4" => UART_data(0) <= uart_ready;
when X"5" => UART_data(0) <= uart_send;
when others => UART_data <= (others => '0');
end case;
elsif(s_internal_address(31 downto 24) = x"98") then --LEDS Registers
LED_reg <= data_in(15 downto 0);
next_state <= idle;
elsif(s_internal_address(31 downto 24) = x"97") then --m_clock Register
next_state <= idle;
elsif(s_internal_address(31 downto 28) = x"9") then --ROM
next_state <= loading_ram;
elsif(s_internal_address(31 downto 28) = x"8") then --RAM
next_state <= loading_rom;
else
next_state <= idle;
end if;
-- Special load cases
when loading_rom =>
s_fuck_vivado_so_much <= "000101";
ROM_en <= '1';
if(ROM_done = '1') then
if(paused_state = fetching) then
instr_out <= zero_word & s_ROM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
when loading_ram =>
s_fuck_vivado_so_much <= "000110";
RAM_en <= '1';
if(ROM_done = '1') then
if(paused_state = fetching) then
instr_out <= zero_word & s_RAM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
-- Stores and such
when storing =>
s_fuck_vivado_so_much <= "000111";
next_state <= idle; -- By default go back
if(s_internal_address(31 downto 16) = x"9801") then --UART
case s_internal_address(3 downto 0) is
when X"0" => NULL; -- Nothing here really, why would you write to buffer in?
when X"1" => NULL; -- Why?
when X"2" => uart_reset_read <= '1';
next_state <= done_uart_rx;
when X"3" => uart_data_out <= data_in(7 downto 0);
when X"4" => NULL; -- No no no write
when X"5" => uart_send <= '1'; -- Assuming if you are writing is to send something
next_state <= done_uart_tx; -- After writing to this register we reset it automatically
when others => UART_data <= (others => '0');
end case;
elsif(s_internal_address(31 downto 28) = x"9") then --LEDS
LED_reg <= data_in(15 downto 0);
next_state <= idle;
elsif(s_internal_address(31 downto 24) = x"97") then --m_clock
next_state <= idle;
-- elsif(addr_in(31 downto 28) = x"9") then --ROM
-- next_state <= idle; --Can't write to ROM, I mean you could, but hwhy? Don't write to ROM
elsif(s_internal_address(31 downto 28) = x"8") then --RAM
next_state <= storing_ram;
end if;
-- Special stores section
when storing_ram =>
s_fuck_vivado_so_much <= "001000";
w_en <= '1';
if(RAM_done = '1') then
w_en <= '0';
next_state <= idle;
end if;
-- Special done states, to reset whatever needs to be reset
when done_uart_tx =>
uart_send <= '0'; --Reset UART send
next_state <= idle;
when done_uart_rx =>
uart_reset_read <= '0';
next_state <= idle;
when others =>
end case;
end if;
end process;
-- Walk the page
PAGE_WALK_FSM: process(clk, rst, s_page_walk)
variable level: Integer := 0;
begin
if(rst = '1') then
page_fault <= '0';
elsif(rising_edge(clk)) then
PAGE_WALK_next_state <= PAGE_WALK_current_state;
case PAGE_WALK_current_state is
when idle =>
if(s_page_walk = '1') then
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & addr_in(31 downto 22) & "00";--SATP PPN will give us the root page table location
PAGE_WALK_next_state <= level_i_read;
level := 0; --Start at level 0
end if;
when level_i_read =>
if(level < 3) then
page_walk_request_read <= '1';
if(RAM_done = '1') then
level := level + 1;
PAGE_WALK_next_state <= level_i_decode;
end if;
else
--Raise exception here
PAGE_WALK_next_state <= idle;
end if;
when level_i_decode =>
PAGE_WALK_next_state <= idle;
if(s_RAM_data_out(0) = '0') then --Invalid PTE Raise the roof
NULL;
elsif(s_RAM_data_out(1) = '0' and s_RAM_data_out(7) = '1') then -- Other exception
NULL;
elsif(s_RAM_data_out(1) = '1' or s_RAM_data_out(3) = '1') then --All gucci, this address is final
page_walk_next_state <= done;
page_address_final <= s_RAM_data_out(63 downto 13) & s_internal_address(12 downto 0);
page_walk_done <= '1';
else -- We still have to go deeper son
page_walk_next_state <= level_i_read;
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & s_internal_address(31 downto 22) & "00";
end if;
when done =>
PAGE_WALK_next_state <= idle;
end case;
end if;
end process;
--busy <= '0' when curr_state = idle else '1';
-- Z high impedance
dq(0) <= 'Z' when io_tri_si = '1' else io_SI;
dq(1) <= 'Z';
dq(2) <= 'Z' when io_tri_wp = '1' else io_WP;
dq(3) <= 'Z';
qd(0) <= dq(0) when io_tri_si = '1' else 'Z';
qd(1) <= dq(1);
qd(2) <= dq(2) when io_tri_wp = '1' else 'Z';
qd(3) <= dq(3);
sck <= '0' when gated_clk = '1' else not(clk_25);
-- ROM SPI Clock Generation
ROM_CLK: process(clk_25, rst) begin
if(rst = '1') then
gated_clk <= '1';
elsif(rising_edge(clk_25)) then
if (io_cs = '0') then
gated_clk <= '0';
else
gated_clk <= '1';
end if;
end if;
end process;
-- ROM State Machine
-- To enable rom set ROM_en high
-- Will wait for 600 cycles and give back a 64 bit word
ROM_FSM: process(clk,rst, ROM_en)
variable ROM_counter: integer := 0;
begin
if(rst = '1') then
io_rst <= '1';
io_flash_en <= '0';
elsif(rising_edge(clk)) then
-- ROM_next_state <= ROM_curr_state;
case ROM_curr_state is
when idle =>
ROM_next_state <= idle;
io_flash_en <= '0';
ROM_counter := 0;
io_rst <= '1';
if(ROM_en = '1') then
ROM_done <= '0';
io_rst <= '0';
io_flash_addr <= s_internal_address(23 downto 0); --24 Bits in
io_flash_en <= '1'; --Enable the device
ROM_next_state <= reading_lower;
end if;
when reading_lower =>
ROM_next_state <= reading_lower;
ROM_counter := ROM_counter + 1; -- Wait a good amount of time to let the device react
if(ROM_counter > 300) then
s_ROM_data_out(31 downto 0) <= io_flash_data_out;
ROM_next_state <= reading_higher;
ROM_counter := 0;
end if;
when reading_higher =>
ROM_next_state <= reading_higher;
ROM_counter := ROM_counter + 1;
if(ROM_counter > 300) then
s_ROM_data_out(63 downto 32) <= io_flash_data_out;
ROM_next_state <= done;
end if;
when done =>
ROM_done <= '1';
ROM_next_state <= idle;
end case;
end if;
end process;
-- RAM State Machine
-- For reading from RAM, the ideal waiting time is of 230 ns
-- For writing into RAM, the ideal waiting time is of 270 ns
-- To make things easier we use 300 ns for both cases.
RAM_FSM: process(clk, RAM_en, w_en)
variable RAM_counter :integer := 0;
begin
if(rising_edge(clk)) then
if(RAM_curr_state /= idle) then
RAM_counter := RAM_counter + 1;
else
RAM_counter := 0;
end if;
RAM_next_state <= RAM_curr_state;
-- Forget about it
-- If for whatever reason we take long than
-- 1200 cycles, timeout and throw some error
if(RAM_timeout_counter >= 1200) then
RAM_next_state <= idle;
else
case RAM_curr_state is
-- Idle state, read before write
when idle =>
if(RAM_en = '1') then
RAM_next_state <= read_low;
elsif(w_en = '1') then
RAM_next_state <= write_low;
end if;
-- Load States
when read_low =>
if(RAM_counter > 30) then
s_RAM_data_out(15 downto 0) <= RAM_data_out;
RAM_next_state <= read_low_mid;
RAM_counter := 0;
end if;
when read_low_mid =>
if(RAM_counter > 30) then --Valid Data
s_RAM_data_out(31 downto 16) <= RAM_data_out;
RAM_next_state <= read_upper_mid;
RAM_counter := 0;
end if;
when read_upper_mid =>
if(RAM_counter > 30) then
s_RAM_data_out(47 downto 32) <= RAM_data_out;
RAM_next_state <= read_upper;
RAM_counter := 0;
end if;
when read_upper =>
if(RAM_counter > 30) then
s_RAM_data_out(63 downto 48) <= RAM_data_out;
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- Store States
when write_low =>
if(RAM_counter > 30) then
RAM_next_state <= write_low_mid;
RAM_counter := 0;
end if;
when write_low_mid =>
if(RAM_counter > 30) then --Valid Data
RAM_next_state <= write_upper_mid;
RAM_counter := 0;
end if;
when write_upper_mid =>
if(RAM_counter > 30) then
RAM_next_state <= write_upper;
RAM_counter := 0;
end if;
when write_upper =>
if(RAM_counter > 30) then
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- We are done here
when others =>
RAM_next_state <= idle;
end case;
end if;
end if;
end process;
-- Latches the last obtained datas (dati, datum? datae?)
LAST_OBTAINED_DATA: process(clk,rst) begin
if(rst = '1') then
data_out <= (others => '0');
elsif(rising_edge(clk)) then
if(RAM_curr_state = done) then
data_out <= s_RAM_data_out;
elsif(ROM_curr_state = done) then
data_out <= s_ROM_data_out;
elsif(UART_toggle = '1') then
data_out(7 downto 0) <= UART_out;
data_out(63 downto 8) <= (others => '0');
end if;
end if;
end process;
-- Muxes for addresses and data
-- Intermitent address is internal RAM address, whenever we need to use the RAM
-- to access something else, we will make use of this intermitent_address_in signal
Intermitent_Address_In <= addr_in when s_page_walk = '0' else page_address_in;
s_internal_data <= data_in; --For the moment this is right
-- Might change this to sequential logic if needed, I don't think it necessary
RAM_address_in <= std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 0) when RAM_curr_state = idle or RAM_curr_state = read_low or RAM_curr_state = write_low else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 2) when RAM_curr_state = read_low_mid or RAM_curr_state = write_low_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 4) when RAM_curr_state = read_upper_mid or RAM_curr_state = write_upper_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 6) when RAM_curr_state = read_upper or RAM_curr_state = write_upper
else (others => '0');
RAM_data_in <= s_internal_data(15 downto 0 ) when RAM_curr_state = idle or RAM_curr_state = write_low else
s_internal_data(31 downto 16) when RAM_curr_state = write_low_mid else
s_internal_data(47 downto 32) when RAM_curr_state = write_upper_mid else
s_internal_data(63 downto 48) when RAM_curr_state = write_upper else
(others => '0');
-- The CSR telling us where the page table start
SATP_mode(3 downto 0) <= satp(63 downto 60);
SATP_PPN(43 downto 0) <= satp(43 downto 0);
LED <= LED_reg;
--pragma synthesis_off
fkuck_vivado_so_much <= s_fuck_vivado_so_much;
s_internal_address_out <= s_internal_address;
--pragma synthesis_on
end Behavioral; | mit | bcf7104ae4e2606bd0a5fd424f8415c7 | 0.573169 | 3.40005 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/dcm_TFT9/simulation/timing/dcm_TFT9_tb.vhd | 1 | 6,190 | -- file: dcm_TFT9_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity dcm_TFT9_tb is
end dcm_TFT9_tb;
architecture test of dcm_TFT9_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
component dcm_TFT9_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : dcm_TFT9_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
end test;
| gpl-3.0 | 48cf455126df237de1bbe7a15d830ec2 | 0.635703 | 4.313589 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/ArpPacketRx.vhd | 1 | 7,334 | ---------------------------------------------------------------------------------
-- Title : ARP Packet RX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ArpPacketRx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to Ethernet layer, reads incoming ARP packets
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity ArpPacketRx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethRxClk : in sl;
ethRxRst : in sl := '0';
-- Incoming data from Ethernet frame
ethRxSrcMac : in MacAddrType;
ethRxDestMac : in MacAddrType;
ethRxData : in slv( 7 downto 0);
ethRxDataValid : in sl;
ethRxDataLast : in sl;
-- Received data from ARP packet
arpOp : out slv(15 downto 0);
arpSenderMac : out MacAddrType;
arpSenderIp : out IpAddrType;
arpTargetMac : out MacAddrType;
arpTargetIp : out IpAddrType;
arpValid : out sl
);
end ArpPacketRx;
-- Define architecture
architecture rtl of ArpPacketRx is
type StateType is (IDLE_S,
HTYPE_S, PTYPE_S, HLEN_S, PLEN_S, OPER_S,
SHA_S, SPA_S, THA_S, TPA_S, DUMP_S);
type RegType is record
state : StateType;
rdCount : slv(2 downto 0);
senderMac : MacAddrType;
senderIp : IpAddrType;
targetMac : MacAddrType;
targetIp : IpAddrType;
op : slv(15 downto 0);
valid : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
rdCount => (others => '0'),
senderMac => MAC_ADDR_INIT_C,
senderIp => IP_ADDR_INIT_C,
targetMac => MAC_ADDR_INIT_C,
targetIp => IP_ADDR_INIT_C,
op => (others => '0'),
valid => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethRxSrcMac,ethRxDestMac,ethRxData,
ethRxDataValid,ethRxDataLast,ethRxRst) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
v.valid := '0';
-- State machine
case(r.state) is
when IDLE_S =>
v.rdCount := (others => '0');
if ethRxDataValid = '1' then
if (ethRxData /= getByte(1,ARP_HTYPE_C)) then
v.state := DUMP_S;
else
v.state := HTYPE_S;
end if;
end if;
when HTYPE_S =>
if ethRxDataValid = '1' then
if (ethRxData /= getByte(0,ARP_HTYPE_C)) then
v.state := DUMP_S;
else
v.state := PTYPE_S;
end if;
end if;
when PTYPE_S =>
if ethRxDataValid = '1' then
if (ethRxData /= getByte(1-conv_integer(r.rdCount),ARP_PTYPE_C)) then
v.state := DUMP_S;
else
v.rdCount := r.rdCount + 1;
if (r.rdCount = 1) then
v.rdCount := (others => '0');
v.state := HLEN_S;
end if;
end if;
end if;
when HLEN_S =>
if ethRxDataValid = '1' then
if (ethRxData /= ARP_HLEN_C) then
v.state := DUMP_S;
else
v.state := PLEN_S;
end if;
end if;
when PLEN_S =>
if ethRxDataValid = '1' then
if (ethRxData /= ARP_PLEN_C) then
v.state := DUMP_S;
else
v.state := OPER_S;
end if;
end if;
when OPER_S =>
if ethRxDataValid = '1' then
v.op((2-conv_integer(r.rdCount))*8-1 downto (1-conv_integer(r.rdCount))*8) := ethRxData;
v.rdCount := r.rdCount + 1;
if (r.rdCount = 1) then
v.rdCount := (others => '0');
v.state := SHA_S;
end if;
end if;
when SHA_S =>
if ethRxDataValid = '1' then
v.senderMac(5-conv_integer(r.rdCount)) := ethRxData;
v.rdCount := r.rdCount + 1;
if (r.rdCount = 5) then
v.rdCount := (others => '0');
v.state := SPA_S;
end if;
end if;
when SPA_S =>
if ethRxDataValid = '1' then
v.senderIp(3-conv_integer(r.rdCount)) := ethRxData;
v.rdCount := r.rdCount + 1;
if (r.rdCount = 3) then
v.rdCount := (others => '0');
v.state := THA_S;
end if;
end if;
when THA_S =>
if ethRxDataValid = '1' then
v.targetMac(5-conv_integer(r.rdCount)) := ethRxData;
v.rdCount := r.rdCount + 1;
if (r.rdCount = 5) then
v.rdCount := (others => '0');
v.state := TPA_S;
end if;
end if;
when TPA_S =>
if ethRxDataValid = '1' then
v.targetIp(3-conv_integer(r.rdCount)) := ethRxData;
v.rdCount := r.rdCount + 1;
if (r.rdCount = 3) then
v.rdCount := (others => '0');
v.valid := '1';
v.state := DUMP_S;
end if;
end if;
when DUMP_S =>
if (ethRxDataLast = '1') then
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Should always return to idle if you see last out of place
if (ethRxDataLast = '1' and r.state /= DUMP_S) then
v.state := IDLE_S;
end if;
-- Reset logic
if (ethRxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
arpSenderMac <= r.senderMac;
arpSenderIp <= r.senderIp;
arpTargetMac <= r.targetMac;
arpTargetIp <= r.targetIp;
arpValid <= r.valid;
arpOp <= r.op;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
seq : process (ethRxClk) is
begin
if (rising_edge(ethRxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 770642681de735ad82377527171f7d50 | 0.447096 | 4.246671 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/sim/CoreAutoNegSim.vhd | 1 | 5,263 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:50:52 08/18/2015
-- Design Name:
-- Module Name: C:/Users/Kurtis/Desktop/testBed/ethernet/CoreAutoNegSim.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: EthFrameRx
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY CoreAutoNegSim IS
END CoreAutoNegSim;
ARCHITECTURE behavior OF CoreAutoNegSim IS
-- Clocking
signal eth125Clk : std_logic := '0';
signal eth125Rst : std_logic := '0';
signal eth62Clk : std_logic := '0';
signal eth62Rst : std_logic := '0';
signal aMacAddr : MacAddrType := MAC_ADDR_DEFAULT_C;
signal bMacAddr : MacAddrType := ( 5 => x"A1",
4 => x"B2",
3 => x"C3",
2 => x"D4",
1 => x"E5",
0 => x"F6" );
signal aIpAddr : IpAddrType := ( 3 => conv_std_logic_vector(192,8),
2 => conv_std_logic_vector(168,8),
1 => conv_std_logic_vector(1,8),
0 => conv_std_logic_vector(2,8) );
signal bIpAddr : IpAddrType := IP_ADDR_DEFAULT_C;
signal aRxData : EthRxPhyLaneInType;
signal aTxData : EthTxPhyLaneOutType;
signal bRxData : EthRxPhyLaneInType;
signal bTxData : EthTxPhyLaneOutType;
signal aSync : sl;
signal aAnDone : sl;
signal bSync : sl;
signal bAnDone : sl;
-- Clock period definitions
constant ethClk_period : time := 8 ns;
constant GATE_DELAY_C : time := 1 ns;
BEGIN
-- Match up B TX to A RX
aRxData.data <= bTxData.data;
aRxData.dataK <= bTxData.dataK;
aRxData.dispErr <= (others => '0');
aRxData.decErr <= (others => '0');
-- Match up A TX to B RX
bRxData.data <= aTxData.data;
bRxData.dataK <= aTxData.dataK;
bRxData.dispErr <= (others => '0');
bRxData.decErr <= (others => '0');
-- Core A
U_CoreA : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => 1,
EN_AUTONEG_G => true,
SIM_SPEEDUP_G => true,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- 125 MHz clock and reset
eth125Clk => eth125Clk,
eth125Rst => eth125Rst,
-- 62 MHz clock and reset
eth62Clk => eth62Clk,
eth62Rst => eth62Rst,
-- User clock and reset
userClk => eth125Clk,
userRst => eth125Rst,
-- Addressing
macAddr => aMacAddr,
ipAddrs => (0 => aIpAddr),
-- Data to/from GT
phyRxData => aRxData,
phyTxData => aTxData,
-- Status signals
statusSync => aSync,
statusAutoNeg => aAnDone
);
-- Core B
U_CoreB : entity work.Eth1000BaseXCore
generic map (
NUM_IP_G => 1,
EN_AUTONEG_G => true,
SIM_SPEEDUP_G => true,
GATE_DELAY_G => GATE_DELAY_C
)
port map (
-- 125 MHz clock and reset
eth125Clk => eth125Clk,
eth125Rst => eth125Rst,
-- 62 MHz clock and reset
eth62Clk => eth62Clk,
eth62Rst => eth62Rst,
-- Addressing
macAddr => bMacAddr,
ipAddrs => (0 => bIpAddr),
-- Data to/from GT
phyRxData => bRxData,
phyTxData => bTxData,
-- Status signals
statusSync => bSync,
statusAutoNeg => bAnDone
);
-- Clock process definitions
ethRxClk_process :process
begin
eth125Clk <= '0';
wait for ethClk_period/2;
eth125Clk <= '1';
wait for ethClk_period/2;
end process;
clk62_process : process(eth125Clk) begin
if rising_edge(eth125Clk) then
eth62Clk <= not(eth62Clk);
end if;
end process;
-- Stimulus process
stim_proc: process
begin
eth125Rst <= '1';
eth62Rst <= '1';
-- hold reset state for 100 ns.
wait for 20 ns;
eth125Rst <= '0';
eth62Rst <= '0';
wait for ethClk_period*10;
-- insert stimulus here
wait;
end process;
END;
| lgpl-2.1 | 69db3b0d197af251b2d4f311d38dbf64 | 0.530876 | 3.987121 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/dcm_TFT9.vhd | 2 | 6,366 | -- file: dcm_TFT9.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1_____9.000______0.000______50.0______373.081____240.171
-- CLK_OUT2_____9.000____180.000______50.0______373.081____240.171
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm_TFT9 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK9 : out std_logic;
CLK9_180 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm_TFT9;
architecture xilinx of dcm_TFT9 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm_TFT9,clk_wiz_v3_2,{component_name=dcm_TFT9,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 9,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 50,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 50,
CLKOUT1_PHASE => 180.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 10.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => RESET,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK9,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK9_180,
I => clkout1);
end xilinx;
| gpl-3.0 | 76e4f41462809daa9b3cf60ee06cee41 | 0.594879 | 4.160784 | false | false | false | false |
satputeaditya/vernier-ring-oscillator-tdc | slow_oscillator.vhd | 1 | 672 | -- slow_oscillator.vhd
--************************************
-- Program to simulate slow oscillator
--************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
entity slow_oscillator is
port (
start : in std_logic;
slow_clk : out std_logic:='0'
);
end entity;
architecture behave of slow_oscillator is
signal clk: std_logic:='0';
begin
process(clk,start)
begin
if start = '1' then
clk <= not clk after 100 pS;
elsif start = '0' then
clk <= '0';
end if;
end process;
slow_clk <= clk;
end behave; | mit | 015f64b5157ed2c08633c4dd90508b87 | 0.53869 | 3.36 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/EthLayerRx.vhd | 1 | 8,914 | ---------------------------------------------------------------------------------
-- Title : Ethernet Layer RX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : EthFrameRx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to MAC, reads and parses Ethernet frames
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity EthFrameRx is
generic (
GATE_DELAY_G : time := 1 ns;
-- Maximum number of data bytes allowed per frame
MAX_SIZE_G : integer := 1500;
SIZE_BITS_G : integer := 12
);
port (
-- 125 MHz ethernet clock in
ethRxClk : in sl;
ethRxRst : in sl := '0';
-- Settings from the upper level
macAddress : in MacAddrType := MAC_ADDR_INIT_C;
-- Incoming data from the MAC layer
macRxData : in slv(7 downto 0);
macRxDataValid : in sl;
macRxDataLast : in sl;
macRxBadFrame : in sl;
-- Outgoing data to next layer
ethRxEtherType : out EtherType;
ethRxSrcMac : out MacAddrType;
ethRxDestMac : out MacAddrType;
ethRxData : out slv( 7 downto 0);
ethRxDataValid : out sl;
ethRxDataLast : out sl
);
end EthFrameRx;
-- Define architecture
architecture rtl of EthFrameRx is
type StateType is (IDLE_S,
DST_MAC_S, SRC_MAC_S, ETHERTYPE_S,
BUFFER_S, DUMP_S, DONE_S);
type ReadStateType is (WAIT_S, READ_S);
type RegType is record
state : StateType;
rxDataOut : slv(7 downto 0);
rxDataValid : sl;
rxDataLast : sl;
rxByteCount : slv(SIZE_BITS_G-1 downto 0);
payloadCount : slv(SIZE_BITS_G-1 downto 0);
rxSrcMac : MacAddrType;
rxDstMac : MacAddrType;
rxEtherType : EtherType;
wrEn : sl;
wrData : slv(7 downto 0);
wrAddr : slv(SIZE_BITS_G-1 downto 0);
startRd : sl;
rdState : ReadStateType;
rdAddr : slv(SIZE_BITS_G-1 downto 0);
rdCount : slv(SIZE_BITS_G-1 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
rxDataOut => (others => '0'),
rxDataValid => '0',
rxDataLast => '0',
rxByteCount => (others => '0'),
payloadCount => (others => '0'),
rxSrcMac => MAC_ADDR_INIT_C,
rxDstMac => MAC_ADDR_INIT_C,
rxEtherType => ETH_TYPE_INIT_C,
wrEn => '0',
wrData => (others => '0'),
wrAddr => (others => '0'),
startRd => '0',
rdState => WAIT_S,
rdAddr => (others => '0'),
rdCount => (others => '0')
);
signal rdData : slv(7 downto 0);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
constant CRC_BYTES_C : integer := 4;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
-- This needs to be modified to match the max payload size
-- Size was changed to 4096 to support natural rollover!
U_FrameBuffer : entity work.bram8x3000
port map (
clka => ethRxClk,
wea(0) => r.wrEn,
addra => r.wrAddr,
dina => r.wrData,
clkb => ethRxClk,
rstb => ethRxRst,
addrb => r.rdAddr,
doutb => rdData
);
comb : process(r,rdData,ethRxRst,macAddress,
macRxData,macRxDataValid,
macRxDataLast, macRxBadFrame) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
v.rxDataLast := '0';
v.startRd := '0';
-- State machine
case(r.state) is
when IDLE_S =>
v.rxDataOut := (others => '0');
v.startRd := '0';
v.rxByteCount := (others => '0');
v.wrEn := '0';
v.wrData := (others => '0');
if (macRxDataValid = '1') then
v.rxDstMac(5) := macRxData;
v.rxByteCount := r.rxByteCount + 1;
v.state := DST_MAC_S;
end if;
when DST_MAC_S =>
if (macRxBadFrame = '1' or macRxDataLast = '1') then
v.state := IDLE_S;
elsif (macRxDataValid = '1') then
v.rxDstMac( 5-conv_integer(r.rxByteCount) ) := macRxData;
v.rxByteCount := r.rxByteCount + 1;
if (r.rxByteCount = 5) then
v.rxByteCount := (others => '0');
v.state := SRC_MAC_S;
end if;
end if;
when SRC_MAC_S =>
if (macRxBadFrame = '1' or macRxDataLast = '1') then
v.state := IDLE_S;
elsif (r.rxDstMac /= macAddress and
r.rxDstMac /= MAC_ADDR_BCAST_C) then
v.state := DUMP_S;
elsif (macRxDataValid = '1') then
v.rxSrcMac( 5-conv_integer(r.rxByteCount) ) := macRxData;
v.rxByteCount := r.rxByteCount + 1;
if (r.rxByteCount = 5) then
v.rxByteCount := (others => '0');
v.state := ETHERTYPE_S;
end if;
end if;
when ETHERTYPE_S =>
if (macRxBadFrame = '1' or macRxDataLast = '1') then
v.state := IDLE_S;
elsif (macRxDataValid = '1') then
v.rxEtherType( (2-conv_integer(r.rxByteCount))*8 - 1 downto (1-conv_integer(r.rxByteCount))*8 ) := macRxData;
v.rxByteCount := r.rxByteCount + 1;
if (r.rxByteCount = 1) then
v.rxByteCount := (others => '0');
v.payloadCount := (others => '0');
v.state := BUFFER_S;
end if;
end if;
when BUFFER_S =>
if (macRxBadFrame = '1') then
v.state := IDLE_S;
elsif (r.rxEtherType /= ETH_TYPE_IPV4_C and
r.rxEtherType /= ETH_TYPE_ARP_C) then
v.state := DUMP_S;
elsif (macRxDataLast = '1') then
v.startRd := '1';
v.state := IDLE_S;
end if;
v.wrData := macRxData;
if (macRxDataValid = '1') then
v.wrEn := macRxDataValid;
v.wrAddr := r.wrAddr + 1;
v.payloadCount := r.payloadCount + 1;
end if;
when DUMP_S =>
if (macRxDataLast = '1') then
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Separate state machine for reading ring buffer
case (r.rdState) is
when WAIT_S =>
v.rxDataValid := '0';
v.rdAddr := (others => '0');
v.rdCount := (others => '0');
if (r.startRd = '1') then
v.rdAddr := r.wrAddr - r.payloadCount + 1;
v.rdCount := r.payloadCount - CRC_BYTES_C - 1;
v.rdState := READ_S;
end if;
when READ_S =>
v.rxDataValid := '1';
v.rdAddr := r.rdAddr + 1;
v.rdCount := r.rdCount - 1;
if (r.rdCount = 0) then
v.rxDataLast := '1';
v.rdState := WAIT_S;
end if;
when others =>
v.rdState := WAIT_S;
end case;
-- Reset logic
if (ethRxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
ethRxEtherType <= r.rxEtherType;
ethRxSrcMac <= r.rxSrcMac;
ethRxDestMac <= r.rxDstMac;
ethRxData <= rdData;
ethRxDataValid <= r.rxDataValid;
ethRxDataLast <= r.rxDataLast;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
seq : process (ethRxClk) is
begin
if (rising_edge(ethRxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 87a8c0bc2257dae73d9d4dcb3c910a08 | 0.464775 | 4.210675 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/ArpResponder.vhd | 1 | 5,392 | ---------------------------------------------------------------------------------
-- Title : ARP Responder
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ArpResponder.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Receives ARP requests, sends back ARP responses.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity ArpResponder is
generic (
NUM_IP_G : integer := 1;
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethClk : in sl;
ethRst : in sl := '0';
-- Local MAC/IP settings
macAddress : in MacAddrType;
ipAddresses : in IpAddrArray(NUM_IP_G-1 downto 0);
-- Connection to ARP RX
arpRxOp : in slv(15 downto 0);
arpRxSenderMac : in MacAddrType;
arpRxSenderIp : in IpAddrType;
arpRxTargetMac : in MacAddrType;
arpRxTargetIp : in IpAddrType;
arpRxValid : in sl;
-- Connection to ARP TX
arpTxSenderMac : out MacAddrType;
arpTxSenderIp : out IpAddrType;
arpTxTargetMac : out MacAddrType;
arpTxTargetIp : out IpAddrType;
arpTxOp : out slv(15 downto 0);
arpTxReq : out sl;
arpTxAck : in sl
);
end ArpResponder;
architecture rtl of ArpResponder is
type StateType is (IDLE_S, CHECK_IP_S, RESPOND_S, WAIT_S);
type RegType is record
state : StateType;
rxSenderMac : MacAddrType;
rxSenderIp : IpAddrType;
rxTargetMac : MacAddrType;
rxTargetIp : IpAddrType;
txSenderMac : MacAddrType;
txSenderIp : IpAddrType;
txTargetMac : MacAddrType;
txTargetIp : IpAddrType;
txOp : slv(15 downto 0);
txReq : sl;
matchedIp : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
rxSenderMac => MAC_ADDR_INIT_C,
rxSenderIp => IP_ADDR_INIT_C,
rxTargetMac => MAC_ADDR_INIT_C,
rxTargetIp => IP_ADDR_INIT_C,
txSenderMac => MAC_ADDR_INIT_C,
txSenderIp => IP_ADDR_INIT_C,
txTargetMac => MAC_ADDR_INIT_C,
txTargetIp => IP_ADDR_INIT_C,
txOp => (others => '0'),
txReq => '0',
matchedIp => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethRst,macAddress,ipAddresses,
arpRxOp,arpRxSenderMac,arpRxSenderIp,arpRxTargetMac,
arpRxTargetIp,arpRxValid,arpTxAck) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
v.txReq := '0';
-- State machine
case(r.state) is
when IDLE_S =>
v.matchedIp := '0';
if (arpRxValid = '1') then
v.rxSenderMac := arpRxSenderMac;
v.rxSenderIp := arpRxSenderIp;
v.rxTargetMac := arpRxTargetMac;
v.rxTargetIp := arpRxTargetIp;
if (arpRxOp = ARP_OP_REQ_C) then
v.state := CHECK_IP_S;
end if;
end if;
when CHECK_IP_S =>
for ipNum in NUM_IP_G-1 downto 0 loop
if (r.rxTargetIp = ipAddresses(ipNum)) then
v.matchedIp := '1';
end if;
end loop;
if (v.matchedIp = '1') then
v.state := RESPOND_S;
else
v.state := IDLE_S;
end if;
when RESPOND_S =>
v.txReq := '1';
v.txSenderMac := macAddress;
v.txSenderIp := r.rxTargetIp;
v.txTargetMac := r.rxSenderMac;
v.txTargetIp := r.rxSenderIp;
v.txOp := ARP_OP_RES_C;
if (arpTxAck = '1') then
v.state := WAIT_S;
end if;
when WAIT_S =>
if (arpTxAck = '0') then
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
arpTxSenderMac <= r.txSenderMac;
arpTxSenderIp <= r.txSenderIp;
arpTxTargetMac <= r.txTargetMac;
arpTxTargetIp <= r.txTargetIp;
arpTxOp <= r.txOp;
arpTxReq <= r.txReq;
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethClk) is
begin
if (rising_edge(ethClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | cd0738e98f410649eabdf13425f8d017 | 0.500556 | 4.20265 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/MMU.vhd | 1 | 27,386 | ----------------------------------------------------------------------------------
-- Engineer: Cesar Avalos B
-- Create Date: 01/28/2018 07:53:02 PM
-- Module Name: MMU_stub - Behavioral
-- Description: Full flegded MMU to feed instructions and store data, supports SV39
--
-- Additional Comments: Mk. VIII
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MMU is
Port(
clk_100: in std_logic; -- 100 Mhz Clock
clk: in std_logic;
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
r_type: in std_logic_vector(1 downto 0); -- High to toggle store
done: out std_logic; -- High when busy
request: in std_logic; -- CPU request
num_bytes: in std_logic_vector(1 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
error: out std_logic_vector(6 downto 0); -- Error
debug_phys: out doubleword;
debug_virt: out doubleword;
SUM: in std_logic;
MXR: in std_logic;
MTIP: out std_logic;
MSIP: out std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- ROM / RAM lines --
MEM_addr: out std_logic_vector(26 downto 0);
MEM_data_in: out std_logic_vector(7 downto 0);
MEM_data_out: in std_logic_vector(7 downto 0);
MEM_ram: out std_logic;
MEM_write: out std_logic;
MEM_request: out std_logic;
MEM_status: in std_logic;
MEM_err: in std_logic
);
end MMU;
architecture Behavioral of MMU is
-- Components --
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
-- Signals --
type MMU_state is ( INIT, IDLE, SETUP, FINISH, FAULT, ALIGN_FAULT,
PAGE_WALK, PAGE_DECODE, PAGE_FAULT, PAGE_LEAF,
BUS_ACCESS, ACCESS_MSIP, ACCESS_TIME_CMP, ACCESS_TIME,
ACCESS_UART, ACCESS_LEDS, ACCESS_ROM, ACCESS_RAM,
ACCESS_MEM_WRITE, ACCESS_MEM_WRITE_WAIT, ACCESS_MEM_WRITE_WAIT_B,
ACCESS_MEM_READ, ACCESS_MEM_READ_WAIT, ACCESS_MEM_READ_WAIT_B );
signal curr_state, bus_ret_state, bus_err_ret_state : MMU_state;
signal init_counter : integer := 0;
signal m_time : doubleword;
signal m_time_cmp : doubleword;
signal s_MSIP : std_logic;
-- latched input request
signal s_addr_in: doubleword;
signal s_data_in: doubleword;
signal s_mode: std_logic_vector(1 downto 0);
signal s_r_type: std_logic_vector(1 downto 0);
signal s_num_bytes: std_logic_vector(1 downto 0);
-- Page Walk Signals --
signal vpn : vpn_arr;
signal pt_base : doubleword;
signal pte : doubleword;
signal page_index : integer;
-- Bus request --
signal bus_address : doubleword;
signal bus_num_bytes : std_logic_vector(1 downto 0);
signal bus_data_write : doubleword;
signal bus_data_read : doubleword;
signal bus_write : std_logic;
-- UART SIGNALS --
signal uart_send : std_logic;
signal uart_data_out : std_logic_vector(7 downto 0);
signal uart_ready : std_logic;
signal uart_data_in : std_logic_vector(7 downto 0);
signal uart_data_available : std_logic;
signal uart_reset_read : std_logic;
-- EXTERNAL MEMORY SIGNALS
signal mem_buff : byte_arr;
signal mem_buff_index : integer;
signal mem_buff_max : integer;
signal s_MEM_addr : std_logic_vector(26 downto 0);
begin
myUARTTX: UART_TX_CTRL port map
(
SEND => uart_send,
DATA => uart_data_out,
CLK => clk_100,
READY => uart_ready,
UART_TX => UART_TXD
);
myUARTRX: UART_RX_CTRL port map
(
UART_RX => UART_RXD,
CLK => clk_100,
DATA => uart_data_in,
READ_DATA => uart_data_available,
RESET_READ => uart_reset_read
);
MSIP <= s_MSIP;
MMU_FSM: process( clk )
variable bus_address_top : doubleword;
begin if(rising_edge(clk)) then
m_time <= m_time + 1;
if( m_time >= m_time_cmp ) then
MTIP <= '1';
else
MTIP <= '0';
end if;
case curr_state is
when INIT =>
init_counter <= init_counter + 1;
if( init_counter > INIT_WAIT ) then
curr_state <= idle;
end if;
done <= '0';
LED <= (others => '0');
MEM_request <= '0';
m_time <= ALL_ZERO;
m_time_cmp <= ALL_ZERO;
uart_send <= '0';
uart_reset_read <= '0';
debug_phys <= ALL_ZERO;
debug_virt <= ALL_ZERO;
data_out <= ALL_ZERO;
MTIP <= '0';
s_MSIP <= '0';
when idle =>
done <= '0';
if(request = '1') then
curr_state <= SETUP;
end if;
when SETUP =>
s_addr_in <= addr_in;
s_data_in <= data_in;
s_mode <= mode;
s_r_type <= r_type;
s_num_bytes <= num_bytes;
if( r_type = MEM_FETCH ) then
debug_virt <= addr_in;
end if;
case satp(SATP_MODE_H downto SATP_MODE_L) is
when SATP_MODE_SV39 =>
page_index <= 2;
vpn(2) <= s_addr_in(38 downto 30);
vpn(1) <= s_addr_in(29 downto 21);
vpn(0) <= s_addr_in(20 downto 12);
pt_base <= zero_byte & satp(SATP_PPN_H downto SATP_PPN_L) & zero_byte & "0000";
curr_state <= PAGE_WALK;
when others =>
bus_address <= addr_in;
bus_num_bytes <= num_bytes;
bus_ret_state <= FINISH;
bus_err_ret_state <= FAULT;
curr_state <= BUS_ACCESS;
if( r_type = MEM_STORE ) then
bus_write <= '1';
bus_data_write <= data_in;
else
bus_write <= '0';
end if;
end case;
when PAGE_FAULT =>
if( request = '0' ) then
curr_state <= IDLE;
end if;
if( s_r_type = MEM_FETCH ) then
error <= CAUSE_INSTRUCTION_PAGE_FAULT;
elsif( s_r_type = MEM_LOAD ) then
error <= CAUSE_LOAD_PAGE_FAULT;
else
error <= CAUSE_STORE_AMO_PAGE_FAULT;
end if;
done <= '1';
when ALIGN_FAULT =>
if( request = '0' ) then
curr_state <= IDLE;
end if;
if( s_r_type = MEM_FETCH ) then
error <= CAUSE_INSTRUCTION_ADDRESS_MISALIGNED;
elsif( s_r_type = MEM_LOAD ) then
error <= CAUSE_LOAD_ADDRESS_MISALIGNED;
else
error <= CAUSE_STORE_AMO_ADDRESS_MISALIGNED;
end if;
done <= '1';
when FAULT =>
if( request = '0' ) then
curr_state <= IDLE;
end if;
if( s_r_type = MEM_FETCH ) then
error <= CAUSE_INSTRUCTION_ACCESS_FAULT;
elsif( s_r_type = MEM_LOAD ) then
error <= CAUSE_LOAD_ACCESS_FAULT;
else
error <= CAUSE_STORE_AMO_ACCESS_FAULT;
end if;
done <= '1';
when PAGE_WALK =>
bus_address <= pt_base(63 downto 12) & vpn(page_index) & "000";
bus_num_bytes <= MEM_BYTES_8;
bus_write <= '0';
bus_ret_state <= PAGE_DECODE;
bus_err_ret_state <= PAGE_FAULT;
curr_state <= BUS_ACCESS;
when PAGE_DECODE =>
if( (bus_data_read(PTE_V) = '0')
or ((bus_data_read(PTE_R) = '0') and (bus_data_read(PTE_W) = '1')))
then
curr_state <= PAGE_FAULT;
elsif( (bus_data_read(PTE_R) = '1') or (bus_data_read(PTE_X) = '1') ) then
pte <= bus_data_read;
curr_state <= PAGE_LEAF;
else
-- node
pt_base <= zero_byte & bus_data_read(PTE_PPN_H downto PTE_PPN_L) & zero_byte & "0000";
page_index <= page_index - 1;
if( page_index = 0 ) then
curr_state <= PAGE_FAULT;
else
curr_state <= PAGE_WALK;
end if;
end if;
when PAGE_LEAF =>
if( (s_r_type = MEM_FETCH) and (pte(PTE_X) = '0') ) then
curr_state <= PAGE_FAULT;
elsif( ((s_r_type = MEM_LOAD ) and (pte(PTE_R) = '0'))
and ((MXR = '0') or ((MXR = '1') and (pte(PTE_X) = '0'))) )
then
curr_state <= PAGE_FAULT;
elsif( (s_r_type = MEM_STORE) and (pte(PTE_W) = '0')) then
curr_state <= PAGE_FAULT;
elsif( (s_mode = USER_MODE) and (pte(PTE_U) = '0') ) then
curr_state <= PAGE_FAULT;
elsif( (s_mode = SUPERVISOR_MODE) and (pte(PTE_U) = '1') and (SUM = '0') ) then
curr_state <= PAGE_FAULT;
else
if( (page_index = 1) and ( pte(18 downto 10) /= "000000000" ) ) then
curr_state <= PAGE_FAULT;
elsif( (page_index = 2) and ( pte(27 downto 10) /= "000000000000000000" ) ) then
curr_state <= PAGE_FAULT;
elsif( (pte(PTE_A) = '0') or ( (pte(PTE_D) = '0') and (s_r_type = MEM_LOAD) ) ) then
curr_state <= PAGE_FAULT;
else
bus_address(63 downto 56) <= zero_byte;
if( page_index = 0 ) then
bus_address(55 downto 12) <= pte(53 downto 10);
elsif( page_index = 1 ) then
bus_address(55 downto 12) <= pte(53 downto 19) & "000000000";
else
bus_address(55 downto 12) <= pte(53 downto 28) & "000000000000000000";
end if;
bus_address(11 downto 0) <= s_addr_in(11 downto 0);
bus_num_bytes <= s_num_bytes;
bus_ret_state <= FINISH;
bus_err_ret_state <= FAULT;
curr_state <= BUS_ACCESS;
if( s_r_type = MEM_STORE ) then
bus_write <= '1';
else
bus_write <= '0';
bus_data_write <= s_data_in;
end if;
end if;
end if;
when BUS_ACCESS =>
if( (bus_num_bytes = MEM_BYTES_8) and (bus_address(2 downto 0) /= "000") ) then
curr_state <= ALIGN_FAULT;
elsif( (bus_num_bytes = MEM_BYTES_4) and (bus_address(1 downto 0) /= "00" ) ) then
curr_state <= ALIGN_FAULT;
elsif( (bus_num_bytes = MEM_BYTES_2) and (bus_address(0) /= '0' ) ) then
curr_state <= ALIGN_FAULT;
else
if( bus_num_bytes = MEM_BYTES_8 ) then
bus_address_top := bus_address + 7;
elsif( bus_num_bytes = MEM_BYTES_4 ) then
bus_address_top := bus_address + 3;
elsif( bus_num_bytes = MEM_BYTES_2 ) then
bus_address_top := bus_address + 1;
else
bus_address_top := bus_address;
end if;
if( bus_address(63 downto 32) /= x"00000000" ) then
curr_state <= bus_err_ret_state;
elsif( bus_address(31 downto 16) = x"0200" ) then
if( ( bus_address(15 downto 0) >= x"0000" ) and ( bus_address_top(15 downto 0) < x"0004" ) ) then
curr_state <= ACCESS_MSIP;
elsif(( bus_address(15 downto 0) >= x"4000" ) and ( bus_address_top(15 downto 0) < x"4008" ) ) then
curr_state <= ACCESS_TIME_CMP;
elsif(( bus_address(15 downto 0) >= x"bff8" ) and ( bus_address_top(15 downto 0) < x"c000" ) ) then
curr_state <= ACCESS_TIME;
else
curr_state <= bus_err_ret_state;
end if;
elsif( bus_address = x"000000008FFFFFFC" ) then
bus_data_read(31 downto 0) <= x"00000013";
curr_state <= FINISH;
elsif( bus_address(31 downto 20) = x"980" ) then
if( ( bus_address(19 downto 0) >= x"10000" ) and ( bus_address_top(19 downto 0) < x"10006" ) ) then
curr_state <= ACCESS_UART;
elsif(( bus_address(19 downto 0) >= x"00000" ) and ( bus_address_top(19 downto 0) < x"00002" ) ) then
curr_state <= ACCESS_LEDS;
else
curr_state <= bus_err_ret_state;
end if;
elsif( bus_address(31 downto 28) = x"9" ) then
if( ( bus_address(27 downto 24) >= x"0" ) and ( bus_address_top(27 downto 24) < x"8" ) ) then
curr_state <= ACCESS_ROM;
MEM_ram <= '0';
else
curr_state <= bus_err_ret_state;
end if;
elsif( bus_address(31 downto 28) = x"8" ) then
if( ( bus_address(27 downto 24) >= x"0" ) and ( bus_address_top(27 downto 24) < x"8" ) ) then
curr_state <= ACCESS_RAM;
MEM_ram <= '1';
else
curr_state <= bus_err_ret_state;
end if;
else
curr_state <= bus_err_ret_state;
end if;
end if;
when FINISH =>
if( request = '0' ) then
curr_state <= IDLE;
end if;
if( bus_write = '0') then
data_out <= bus_data_read;
end if;
uart_send <= '0';
uart_reset_read <= '0';
if( s_r_type = MEM_FETCH ) then
debug_phys <= bus_address;
end if;
done <= '1';
error <= MEM_ERR_NONE;
when ACCESS_MSIP =>
if( bus_write = '1') then
if( bus_data_write(0) = '1' ) then
s_MSIP <= '1';
else
s_MSIP <= '0';
end if;
else
bus_data_read(63 downto 1) <= ALL_ZERO(63 downto 1);
if( s_MSIP = '1' ) then
bus_data_read(0) <= '1';
else
bus_data_read(0) <= '0';
end if;
end if;
curr_state <= bus_ret_state;
when ACCESS_TIME_CMP =>
if( bus_num_bytes = MEM_BYTES_8 ) then
if( bus_write = '1') then
m_time_cmp <= bus_data_write;
else
bus_data_read <= m_time_cmp;
end if;
curr_state <= bus_ret_state;
else
curr_state <= bus_err_ret_state;
end if;
when ACCESS_TIME =>
if( bus_num_bytes = MEM_BYTES_8 ) then
if( bus_write = '1') then
m_time <= bus_data_write;
else
bus_data_read <= m_time;
end if;
curr_state <= bus_ret_state;
else
curr_state <= bus_err_ret_state;
end if;
when ACCESS_UART =>
if( bus_num_bytes = MEM_BYTES_1 ) then
if( bus_write = '1') then
case bus_address(3 downto 0) is
when X"0" => curr_state <= bus_err_ret_state;
when X"1" => curr_state <= bus_err_ret_state;
when X"2" => uart_reset_read <= '1';
curr_state <= bus_ret_state;
when X"3" => uart_data_out <= bus_data_write(7 downto 0);
curr_state <= bus_ret_state;
when X"4" => curr_state <= bus_err_ret_state;
when X"5" => uart_send <= '1';
curr_state <= bus_ret_state;
when others => curr_state <= bus_err_ret_state;
end case;
else
case bus_address(3 downto 0) is
when X"0" => bus_data_read(7 downto 0) <= uart_data_in;
curr_state <= bus_ret_state;
when X"1" =>
if( uart_data_available = '1' ) then
bus_data_read(7 downto 0) <= x"01";
else
bus_data_read(7 downto 0) <= x"00";
end if;
curr_state <= bus_ret_state;
when X"2" => curr_state <= bus_err_ret_state;
when X"3" => curr_state <= bus_err_ret_state;
when X"4" =>
if( uart_ready = '1' ) then
bus_data_read(7 downto 0) <= x"01";
else
bus_data_read(7 downto 0) <= x"00";
end if;
curr_state <= bus_ret_state;
when X"5" => curr_state <= bus_err_ret_state;
when others => curr_state <= bus_err_ret_state;
end case;
end if;
else
curr_state <= bus_err_ret_state;
end if;
when ACCESS_LEDS =>
if( ( bus_num_bytes = MEM_BYTES_2 ) and ( bus_write = '1' ) ) then
LED <= bus_data_write(15 downto 0);
curr_state <= bus_ret_state;
else
curr_state <= bus_err_ret_state;
end if;
when ACCESS_ROM | ACCESS_RAM =>
mem_buff_index <= 0;
s_MEM_addr <= bus_address(26 downto 0);
if( bus_num_bytes = MEM_BYTES_8 ) then
mem_buff_max <= 8;
elsif( bus_num_bytes = MEM_BYTES_4 ) then
mem_buff_max <= 4;
elsif( bus_num_bytes = MEM_BYTES_2 ) then
mem_buff_max <= 2;
else
mem_buff_max <= 1;
end if;
if( bus_write = '1' ) then
MEM_write <= '1';
if( bus_num_bytes = MEM_BYTES_8 ) then
mem_buff(0) <= bus_data_write(7 downto 0); mem_buff(1) <= bus_data_write(15 downto 8);
mem_buff(2) <= bus_data_write(23 downto 16); mem_buff(3) <= bus_data_write(31 downto 24);
mem_buff(4) <= bus_data_write(39 downto 32); mem_buff(5) <= bus_data_write(47 downto 40);
mem_buff(6) <= bus_data_write(55 downto 48); mem_buff(7) <= bus_data_write(63 downto 56);
elsif( bus_num_bytes = MEM_BYTES_4 ) then
mem_buff(0) <= bus_data_write(7 downto 0); mem_buff(1) <= bus_data_write(15 downto 8);
mem_buff(2) <= bus_data_write(23 downto 16); mem_buff(3) <= bus_data_write(31 downto 24);
elsif( bus_num_bytes = MEM_BYTES_2 ) then
mem_buff(0) <= bus_data_write(7 downto 0); mem_buff(1) <= bus_data_write(15 downto 8);
else
mem_buff(0) <= bus_data_write(7 downto 0);
end if;
curr_state <= ACCESS_MEM_WRITE;
else
MEM_write <= '0';
curr_state <= ACCESS_MEM_READ;
end if;
when ACCESS_MEM_WRITE =>
if( mem_buff_index = mem_buff_max ) then
curr_state <= bus_ret_state;
else
if( MEM_status = '0' ) then
mem_buff_index <= mem_buff_index + 1;
s_MEM_addr <= s_MEM_addr + 1;
MEM_addr <= s_MEM_addr;
MEM_data_in <= mem_buff(mem_buff_index);
MEM_request <= '1';
curr_state <= ACCESS_MEM_WRITE_WAIT;
end if;
end if;
when ACCESS_MEM_WRITE_WAIT =>
if( MEM_status = '1' ) then
curr_state <= ACCESS_MEM_WRITE_WAIT_B;
end if;
when ACCESS_MEM_WRITE_WAIT_B =>
MEM_request <= '0';
if( MEM_err = '1') then
curr_state <= bus_err_ret_state;
else
curr_state <= ACCESS_MEM_WRITE;
end if;
when ACCESS_MEM_READ =>
if( mem_buff_index = mem_buff_max ) then
curr_state <= bus_ret_state;
if( bus_num_bytes = MEM_BYTES_8 ) then
bus_data_read(7 downto 0) <= mem_buff(0); bus_data_read(15 downto 8) <= mem_buff(1);
bus_data_read(23 downto 16) <= mem_buff(2); bus_data_read(31 downto 24) <= mem_buff(3);
bus_data_read(39 downto 32) <= mem_buff(4); bus_data_read(47 downto 40) <= mem_buff(5);
bus_data_read(55 downto 48) <= mem_buff(6); bus_data_read(63 downto 56) <= mem_buff(7);
elsif( bus_num_bytes = MEM_BYTES_4 ) then
bus_data_read(7 downto 0) <= mem_buff(0); bus_data_read(15 downto 8) <= mem_buff(1);
bus_data_read(23 downto 16) <= mem_buff(2); bus_data_read(31 downto 24) <= mem_buff(3);
elsif( bus_num_bytes = MEM_BYTES_2 ) then
bus_data_read(7 downto 0) <= mem_buff(0); bus_data_read(15 downto 8) <= mem_buff(1);
else
bus_data_read(7 downto 0) <= mem_buff(0);
end if;
else
if( MEM_status = '0' ) then
MEM_addr <= s_MEM_addr;
MEM_request <= '1';
curr_state <= ACCESS_MEM_READ_WAIT;
end if;
end if;
when ACCESS_MEM_READ_WAIT =>
if( MEM_status = '1' ) then
curr_state <= ACCESS_MEM_READ_WAIT_B;
end if;
when ACCESS_MEM_READ_WAIT_B =>
MEM_request <= '0';
if( MEM_err = '1') then
curr_state <= bus_err_ret_state;
else
curr_state <= ACCESS_MEM_READ;
s_MEM_addr <= s_MEM_addr + 1;
mem_buff_index <= mem_buff_index + 1;
mem_buff(mem_buff_index) <= MEM_data_out;
end if;
end case;
if('1' = rst) then
curr_state <= INIT;
init_counter <= 0;
end if;
end if; end process;
end Behavioral;
| mit | 758f1da62b2ea72acb3e9abbb97a87e1 | 0.390236 | 4.257774 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/rom_intf.vhd | 1 | 6,728 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.VCOMPONENTS.ALL;
entity rom_intf is
Port (
memAddress : in STD_LOGIC_VECTOR (26 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
valid : in STD_LOGIC;
done : out STD_LOGIC;
write : in STD_LOGIC;
chip_select : in STD_LOGIC;
err : out STD_LOGIC;
clk, rst : in STD_LOGIC;
-- ROM SPI signals
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0)
);
end rom_intf;
architecture Behavioral of rom_intf is
type ROM_state is ( INIT, IDLE, SETUP, SETUP_HOLD, FINISH,
COMMAND_SET, COMMAND_SEND, COMMAND_HOLD_LOW, COMMAND_HOLD_HIGH,
ADDR_SET, ADDR_SEND, ADDR_HOLD_LOW, ADDR_HOLD_HIGH,
DATA_READ, DATA_SET, DATA_HOLD_LOW, DATA_HOLD_HIGH);
signal curr_state : ROM_state := idle;
signal init_counter : integer := 0;
signal s_memAddress : STD_LOGIC_VECTOR (23 downto 0);
signal s_dataIn : STD_LOGIC_VECTOR (7 downto 0);
signal sck: std_logic;
constant SPI_OUT : integer := 1;
constant SPI_IN : integer := 0;
constant READ_COMMAND : STD_LOGIC_VECTOR (7 downto 0) := x"03";
signal count : integer;
begin
STARTUPE2_inst : STARTUPE2
generic map (
PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ => 10.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
CFGCLK => open, -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- 1-bit output: PROGRAM request to fabric output
CLK => '0', -- 1-bit input: User start-up clock input
GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => '0', -- 1-bit input: PROGRAM acknowledge input
USRCCLKO => sck, -- 1-bit input: User CCLK input
USRCCLKTS => '0', -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- 1-bit input: User DONE pin output control
USRDONETS => '0' -- 1-bit input: User DONE 3-state enable output
);
ROM_FSM: process( clk )
begin if(rising_edge(clk)) then
case curr_state is
when INIT =>
init_counter <= init_counter + 1;
if( init_counter > INIT_WAIT ) then
curr_state <= idle;
end if;
done <= '0';
cs_n <= '1';
sck <= '0';
dq(SPI_OUT) <= 'Z';
dq(SPI_IN) <= 'Z';
dq(2) <= 'Z';
dq(3) <= 'Z';
when IDLE =>
done <= '0';
cs_n <= '1';
sck <= '0';
dq(SPI_OUT) <= 'Z';
dq(SPI_IN) <= 'Z';
if((valid = '1') and (chip_select = '1')) then
curr_state <= SETUP;
end if;
when SETUP =>
if( (memAddress(26 downto 24) /= "000") or (write = '1')) then
err <= '1';
done <= '1';
curr_state <= IDLE;
else
s_memAddress <= MemAddress(23 downto 0);
s_dataIn <= DataIn;
cs_n <= '0';
sck <= '0';
count <= 7;
curr_state <= SETUP_HOLD;
end if;
when SETUP_HOLD =>
curr_state <= COMMAND_SET;
when COMMAND_SET =>
sck <= '0';
dq(SPI_IN) <= READ_COMMAND(count);
curr_state <= COMMAND_HOLD_LOW;
when COMMAND_HOLD_LOW =>
curr_state <= COMMAND_SEND;
when COMMAND_SEND =>
sck <= '1';
curr_state <= COMMAND_HOLD_HIGH;
when COMMAND_HOLD_HIGH =>
if( count = 0 ) then
count <= 23;
curr_state <= ADDR_SET;
else
count <= count - 1;
curr_state <= COMMAND_SET;
end if;
when ADDR_SET =>
sck <= '0';
dq(SPI_IN) <= s_memAddress(count);
curr_state <= ADDR_HOLD_LOW;
when ADDR_HOLD_LOW =>
curr_state <= ADDR_SEND;
when ADDR_SEND =>
sck <= '1';
curr_state <= ADDR_HOLD_HIGH;
when ADDR_HOLD_HIGH =>
if( count = 0 ) then
count <= 8;
curr_state <= DATA_READ;
else
count <= count - 1;
curr_state <= ADDR_SET;
end if;
when DATA_READ =>
sck <= '0';
if( count /= 8) then
dataOut(count) <= dq(SPI_OUT);
end if;
curr_state <= DATA_HOLD_LOW;
when DATA_HOLD_LOW =>
curr_state <= DATA_SET;
when DATA_SET =>
sck <= '1';
curr_state <= DATA_HOLD_HIGH;
when DATA_HOLD_HIGH =>
if( count = 0 ) then
curr_state <= FINISH;
else
count <= count - 1;
curr_state <= DATA_READ;
end if;
when FINISH =>
done <= '1';
dq(SPI_IN) <= 'Z';
sck <= '0';
cs_n <= '1';
if(valid <= '0') then
curr_state <= IDLE;
end if;
end case;
if('1' = rst) then
curr_state <= INIT;
init_counter <= 0;
end if;
end if; end process;
end Behavioral;
| mit | 3654de7858499de6ee4e1fa7817edb79 | 0.432818 | 4.165944 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/ram2ddrxadc.vhd | 2 | 20,311 | -------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : ram2ddrxadc.vhd
-- MODULE NAME : RAM to DDR2 Interface Converter with internal XADC
-- instantiation
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-02-04 Mihaita Nagy Created
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements a simple Static RAM to DDR2 interface
-- converter designed to be used with Digilent Nexys4-DDR board
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity ram2ddrxadc is
port (
-- Common
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
ram_a : in std_logic_vector(26 downto 0);
ram_dq_i : in std_logic_vector(15 downto 0);
ram_dq_o : out std_logic_vector(15 downto 0);
ram_cen : in std_logic;
ram_oen : in std_logic;
ram_wen : in std_logic;
ram_ub : in std_logic;
ram_lb : in std_logic;
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end ram2ddrxadc;
architecture Behavioral of ram2ddrxadc is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component ddr
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
--device_temp_i : in std_logic_vector(11 downto 0);
init_calib_complete : out std_logic);
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (stIdle, stSetCmd, stCheckRdy, stWaitRdy, stWaitCen);
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- ddr commands
constant CMD_WRITE : std_logic_vector(2 downto 0) := "000";
constant CMD_READ : std_logic_vector(2 downto 0) := "001";
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- state machine
signal cState, nState : state_type;
-- global signals
signal mem_ui_clk : std_logic;
signal mem_ui_rst : std_logic;
signal rst : std_logic;
signal rstn : std_logic;
-- ram internal signals
signal ram_a_int : std_logic_vector(26 downto 0);
signal ram_dq_i_int : std_logic_vector(15 downto 0);
signal ram_cen_int : std_logic;
signal ram_oen_int : std_logic;
signal ram_wen_int : std_logic;
signal ram_ub_int : std_logic;
signal ram_lb_int : std_logic;
-- ddr user interface signals
-- address for current request
signal mem_addr : std_logic_vector(26 downto 0);
-- command for current request
signal mem_cmd : std_logic_vector(2 downto 0);
-- active-high strobe for 'cmd' and 'addr'
signal mem_en : std_logic;
signal mem_rdy : std_logic;
-- write data FIFO is ready to receive data (wdf_rdy = 1 & wdf_wren = 1)
signal mem_wdf_rdy : std_logic;
signal mem_wdf_data : std_logic_vector(63 downto 0);
-- active-high last 'wdf_data'
signal mem_wdf_end : std_logic;
signal mem_wdf_mask : std_logic_vector(7 downto 0);
signal mem_wdf_wren : std_logic;
signal mem_rd_data : std_logic_vector(63 downto 0);
-- active-high last 'rd_data'
signal mem_rd_data_end : std_logic;
-- active-high 'rd_data' valid
signal mem_rd_data_valid : std_logic;
-- active-high calibration complete
signal mem_init_calib_complete : std_logic;
-- delayed valid
signal rd_vld : std_logic;
-- delayed end
signal rd_end : std_logic;
-- delayed data
signal rd_data_1, rd_data_2 : std_logic_vector(63 downto 0);
------------------------------------------------------------------------
-- Signal attributes (debugging)
------------------------------------------------------------------------
--attribute KEEP : string;
--attribute KEEP of mem_addr : signal is "TRUE";
--attribute KEEP of mem_cmd : signal is "TRUE";
--attribute KEEP of mem_en : signal is "TRUE";
--attribute KEEP of mem_wdf_data : signal is "TRUE";
--attribute KEEP of mem_wdf_end : signal is "TRUE";
--attribute KEEP of mem_wdf_mask : signal is "TRUE";
--attribute KEEP of mem_wdf_wren : signal is "TRUE";
--attribute KEEP of mem_rd_data : signal is "TRUE";
--attribute KEEP of mem_rd_data_end : signal is "TRUE";
--attribute KEEP of mem_rd_data_valid : signal is "TRUE";
--attribute KEEP of mem_rdy : signal is "TRUE";
--attribute KEEP of mem_wdf_rdy : signal is "TRUE";
--attribute KEEP of mem_init_calib_complete : signal is "TRUE";
--attribute KEEP of temp : signal is "TRUE";
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Registering all inputs
------------------------------------------------------------------------
REG_IN: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
ram_a_int <= ram_a;
ram_dq_i_int <= ram_dq_i;
ram_cen_int <= ram_cen;
ram_oen_int <= ram_oen;
ram_wen_int <= ram_wen;
ram_ub_int <= ram_ub;
ram_lb_int <= ram_lb;
end if;
end process REG_IN;
------------------------------------------------------------------------
-- DDR controller instance
------------------------------------------------------------------------
Inst_DDR: ddr
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Inputs
sys_clk_i => clk_200MHz_i,
sys_rst => rstn,
-- user interface signals
app_addr => mem_addr,
app_cmd => mem_cmd,
app_en => mem_en,
app_wdf_data => mem_wdf_data,
app_wdf_end => mem_wdf_end,
app_wdf_mask => mem_wdf_mask,
app_wdf_wren => mem_wdf_wren,
app_rd_data => mem_rd_data,
app_rd_data_end => mem_rd_data_end,
app_rd_data_valid => mem_rd_data_valid,
app_rdy => mem_rdy,
app_wdf_rdy => mem_wdf_rdy,
app_sr_req => '0',
app_sr_active => open,
app_ref_req => '0',
app_ref_ack => open,
app_zq_req => '0',
app_zq_ack => open,
ui_clk => mem_ui_clk,
ui_clk_sync_rst => mem_ui_rst,
--device_temp_i => device_temp_i,
init_calib_complete => mem_init_calib_complete);
rstn <= not rst_i;
rst <= rst_i or mem_ui_rst;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Synchronous process
SYNC_PROCESS: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if rst = '1' then
cState <= stIdle;
else
cState <= nState;
end if;
end if;
end process SYNC_PROCESS;
-- State machine transitions
NEXT_STATE_DECODE: process(cState, mem_init_calib_complete, mem_rdy,
mem_wdf_rdy, ram_cen_int, ram_oen_int, ram_wen_int)
begin
nState <= cState;
case(cState) is
when stIdle =>
if mem_init_calib_complete = '1' then -- memory initialized
if mem_rdy = '1' then -- check for memory ready
if mem_wdf_rdy = '1' then -- write ready
if ram_cen_int = '0' and
(ram_oen_int = '0' or ram_wen_int = '0') then
nState <= stSetCmd;
end if;
end if;
end if;
end if;
when stSetCmd =>
nState <= stCheckRdy;
when stCheckRdy => -- check for memory ready
if mem_rdy = '0' then
nState <= stWaitRdy;
else
nState <= stWaitCen;
end if;
when stWaitRdy =>
if mem_rdy = '1' then -- wait for memory ready
nState <= stWaitCen;
end if;
when stWaitCen =>
if ram_cen_int = '1' then
nState <= stIdle;
end if;
when others =>
nState <= stIdle;
end case;
end process;
------------------------------------------------------------------------
-- Memory control signals
------------------------------------------------------------------------
MEM_CTL: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stIdle or cState = stWaitCen then
mem_wdf_wren <= '0';
mem_wdf_end <= '0';
mem_en <= '0';
elsif cState = stSetCmd then
-- ui command
if ram_wen_int = '0' then -- write
mem_cmd <= CMD_WRITE;
mem_wdf_wren <= '1';
mem_wdf_end <= '1';
mem_en <= '1';
elsif ram_oen_int = '0' then -- read
mem_cmd <= CMD_READ;
mem_en <= '1';
end if;
end if;
end if;
end process MEM_CTL;
------------------------------------------------------------------------
-- Address decoder that forms the data mask
------------------------------------------------------------------------
WR_DATA_MSK: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stCheckRdy then
case(ram_a_int(2 downto 1)) is
when "00" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "11111101";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "11111110";
else -- 16-bit
mem_wdf_mask <= "11111100";
end if;
when "01" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "11110111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "11111011";
else -- 16-bit
mem_wdf_mask <= "11110011";
end if;
when "10" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "11011111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "11101111";
else -- 16-bit
mem_wdf_mask <= "11001111";
end if;
when "11" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "01111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "10111111";
else -- 16-bit
mem_wdf_mask <= "00111111";
end if;
when others => null;
end case;
end if;
end if;
end process WR_DATA_MSK;
------------------------------------------------------------------------
-- Write data and address
------------------------------------------------------------------------
WR_DATA_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stCheckRdy then
mem_wdf_data <= ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int;
mem_addr <= ram_a_int(26 downto 3) & "000";
end if;
end if;
end process WR_DATA_ADDR;
------------------------------------------------------------------------
-- Mask the data output
------------------------------------------------------------------------
-- delay stage for the valid and end signals (for an even better
-- synchronization)
SYNC: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
rd_vld <= mem_rd_data_valid;
rd_end <= mem_rd_data_end;
rd_data_1 <= mem_rd_data;
rd_data_2 <= rd_data_1;
end if;
end process SYNC;
RD_DATA: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if rst = '1' then
ram_dq_o <= (others => '0');
elsif cState = stWaitCen and rd_vld = '1' and rd_end = '1' then
case(ram_a_int(2 downto 1)) is
when "00" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= rd_data_2(15 downto 8) &
rd_data_2(15 downto 8);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= rd_data_2(7 downto 0) &
rd_data_2(7 downto 0);
else -- 16-bit
ram_dq_o <= rd_data_2(15 downto 0);
end if;
when "01" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= rd_data_2(31 downto 24) &
rd_data_2(31 downto 24);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= rd_data_2(23 downto 16) &
rd_data_2(23 downto 16);
else -- 16-bit
ram_dq_o <= rd_data_2(31 downto 16);
end if;
when "10" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= rd_data_2(47 downto 40) &
rd_data_2(47 downto 40);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= rd_data_2(39 downto 32) &
rd_data_2(39 downto 32);
else -- 16-bit
ram_dq_o <= rd_data_2(47 downto 32);
end if;
when "11" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= rd_data_2(63 downto 56) &
rd_data_2(63 downto 56);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= rd_data_2(55 downto 48) &
rd_data_2(55 downto 48);
else -- 16-bit
ram_dq_o <= rd_data_2(63 downto 48);
end if;
when others => null;
end case;
end if;
end if;
end process RD_DATA;
end Behavioral;
| mit | 75b7863ea9ad928d1df6861accffe283 | 0.401162 | 4.122387 | false | false | false | false |
gau-veldt/InsideTheBox | Ep0002/AudioEcho.vhd | 1 | 7,803 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/14/2017 12:34:40 AM
-- Design Name:
-- Module Name: AudioEcho - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AudioEcho is
port (
led : out std_logic_vector(3 downto 0);
sw : in std_logic_vector(3 downto 0);
clk_125 : in std_logic
);
end AudioEcho;
architecture Driver of AudioEcho is
subtype tCount is unsigned(31 downto 0);
constant cZero : tCount := to_unsigned(0,tCount'length);
constant cMod : tCount := to_unsigned(4,tCount'length);
constant cMax : tCount := to_unsigned(125000000,tCount'length);
signal led_st : std_logic_vector(3 downto 0) := "0001";
signal my_clk : std_logic := '0';
signal dCount : tCount := cZero;
signal pingpong : std_logic := '0';
begin
divider: process(clk_125) is
variable dCur : tCount := dCount;
begin
if (rising_edge(clk_125)) then
dCur:=dCur+cMod;
if (dCur >= cMax) then
dCur := dCur - cMax;
my_clk <= not my_clk;
end if;
end if;
end process divider;
lcount: process(my_clk) is
variable lCur : std_logic_vector(3 downto 0) := led_st;
begin
if (rising_edge(my_clk)) then
case sw is
when "0001" =>
-- L to R
case lCur is
when "0001" =>
led_st <= "1000";
when "0010" =>
led_st <= "0001";
when "0100" =>
led_st <= "0010";
when "1000" =>
led_st <= "0100";
when others =>
led_st <= "0001";
end case;
when "0010" =>
-- count binary
case lcur is
when "0000" =>
led_st <= "0001";
when "0001" =>
led_st <= "0010";
when "0010" =>
led_st <= "0011";
when "0011" =>
led_st <= "0100";
when "0100" =>
led_st <= "0101";
when "0101" =>
led_st <= "0110";
when "0110" =>
led_st <= "0111";
when "0111" =>
led_st <= "1000";
when "1000" =>
led_st <= "1001";
when "1001" =>
led_st <= "1010";
when "1010" =>
led_st <= "1011";
when "1011" =>
led_st <= "1100";
when "1100" =>
led_st <= "1101";
when "1101" =>
led_st <= "1110";
when "1110" =>
led_st <= "1111";
when "1111" =>
led_st <= "0000";
when others =>
led_st <= "0000";
end case;
when "0100" =>
-- count gray
case lcur is
when "0000" =>
led_st <= "0001";
when "0001" =>
led_st <= "0011";
when "0011" =>
led_st <= "0010";
when "0010" =>
led_st <= "0110";
when "0110" =>
led_st <= "0111";
when "0111" =>
led_st <= "0101";
when "0101" =>
led_st <= "0100";
when "0100" =>
led_st <= "1100";
when "1100" =>
led_st <= "1101";
when "1101" =>
led_st <= "1111";
when "1111" =>
led_st <= "1110";
when "1110" =>
led_st <= "1010";
when "1010" =>
led_st <= "1011";
when "1011" =>
led_st <= "1001";
when "1001" =>
led_st <= "1000";
when "1000" =>
led_st <= "0000";
when others =>
led_st <= "0000";
end case;
when "1000" =>
-- ping-pong
case pingpong is
when '0' =>
case lCur is
when "0001" =>
led_st <= "0010";
when "0010" =>
led_st <= "0100";
when "0100" =>
led_st <= "1000";
when "1000" =>
led_st <= "0100";
pingpong <= '1';
when others =>
led_st <= "0001";
end case;
when '1' =>
case lCur is
when "1000" =>
led_st <= "0100";
when "0100" =>
led_st <= "0010";
when "0010" =>
led_st <= "0001";
when "0001" =>
led_st <= "0010";
pingpong <= '0';
when others =>
led_st <= "1000";
end case;
end case;
when others =>
-- R to L
case lCur is
when "0001" =>
led_st <= "0010";
when "0010" =>
led_st <= "0100";
when "0100" =>
led_st <= "1000";
when "1000" =>
led_st <= "0001";
when others =>
led_st <= "0001";
end case;
end case;
end if;
end process lcount;
led <= led_st;
end Driver; | gpl-3.0 | 735e0065c753c3398ad0afe83e214cf3 | 0.297706 | 5.526204 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/rtl/Eth1000BaseX8To16Mux.vhd | 1 | 4,176 | --------------------------------------------------------------------
-- Title : 1000 BASE X (16-bit) to 8-bit MAC width translation
--------------------------------------------------------------------
-- File : Eth1000BaseX8To16Mux.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description: Width translation for outgoing data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity Eth1000BaseX8To16Mux is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- Clocking to deal with the GT data out (62.5 MHz)
eth62Clk : in sl;
eth62Rst : in sl;
-- 125 MHz clock for 8 bit inputs
eth125Clk : in sl;
eth125Rst : in sl;
-- PHY (16 bit) data interface out
ethPhyDataOut : out EthTxPhyLaneOutType;
-- MAC (8 bit) data interface out
ethMacDataIn : in EthMacDataType
);
end Eth1000BaseX8To16Mux;
-- Define architecture
architecture rtl of Eth1000BaseX8To16Mux is
type StateType is (SYNC_S, HIGH_S, LOW_S);
type RegType is record
state : StateType;
phyTxData : EthTxPhyLaneOutType;
end record RegType;
constant REG_INIT_C : RegType := (
state => SYNC_S,
phyTxData => ETH_TX_PHY_LANE_OUT_INIT_C
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,eth125Rst,ethMacDataIn) is
variable v : RegType;
begin
v := r;
-- Clear any pulsed signals
v.phyTxData.valid := '0';
-- Combinatorial state logic
case(r.state) is
-- We want to ensure proper alignment of the commas
when SYNC_S =>
if ethMacDataIn.dataValid = '1' and ethMacDataIn.dataK = '1' then
v.state := HIGH_S;
end if;
-- Set the high byte
when HIGH_S =>
v.phyTxData.data(15 downto 8) := ethMacDataIn.data;
v.phyTxData.dataK(1) := ethMacDataIn.dataK;
v.phyTxData.valid := '1';
v.state := LOW_S;
-- Set the low byte and write to the FIFO
when LOW_S =>
v.phyTxData.data( 7 downto 0) := ethMacDataIn.data;
v.phyTxData.dataK(0) := ethMacDataIn.dataK;
v.phyTxData.valid := '0';
v.state := HIGH_S;
when others =>
v.state := SYNC_S;
end case;
-- Reset logic
if (eth125Rst = '1') then
v := REG_INIT_C;
end if;
-- Map to outputs
-- Assignment to signal
rin <= v;
end process;
seq : process (eth125Clk) is
begin
if (rising_edge(eth125Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
-- FIFO to cross the two clock domains
U_Fifo18x16 : entity work.fifo18x16
port map (
rst => eth125Rst,
wr_clk => eth125Clk,
rd_clk => eth62Clk,
din(17 downto 16) => r.phyTxData.dataK,
din(15 downto 0) => r.phyTxData.data,
wr_en => r.phyTxData.valid,
rd_en => '1',
dout(17 downto 16) => ethPhyDataOut.dataK,
dout(15 downto 0) => ethPhyDataOut.data,
full => open,
empty => open,
valid => ethPhyDataOut.valid
);
end rtl;
| lgpl-2.1 | c164fd4446d91538957258d8cbdad9b6 | 0.503592 | 4.243902 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_08/sid_voice.vhd | 2 | 5,116 | ----------------------------------------------------------------------------------
--
-- Generate a single SID voice
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sid_voice is port (
clk1M : in std_logic;
freq : in unsigned (15 downto 0);
pw : in unsigned (11 downto 0);
wvfm : in std_logic_vector (3 downto 0);
test : in std_logic;
rmod : in std_logic;
sync : in std_logic;
gate : in std_logic;
enva : in unsigned (3 downto 0);
envd : in unsigned (3 downto 0);
envs : in unsigned (3 downto 0);
envr : in unsigned (3 downto 0);
envo : out unsigned (7 downto 0);
osco : out unsigned (7 downto 0);
uout : out unsigned (7 downto 0)
);
end sid_voice;
architecture sid_voice_impl of sid_voice is
subtype u8 is unsigned (7 downto 0);
subtype byte is std_logic_vector (7 downto 0);
subtype u9 is unsigned (8 downto 0);
subtype u12 is unsigned (11 downto 0);
subtype word is std_logic_vector (15 downto 0);
subtype u17 is unsigned (16 downto 0);
subtype u23 is unsigned (22 downto 0);
subtype u24 is unsigned (23 downto 0);
subtype word24 is std_logic_vector (23 downto 0);
subtype dword is std_logic_vector (31 downto 0);
signal count24 : u23 := "000" & x"00000";
signal lfsr : word := x"1337";
signal chg_ph : std_logic;
signal taps : std_logic;
signal wv_tri : u8;
signal wv_saw : u8;
signal wv_pul : u8;
signal wv_wht : u8;
signal wv_raw : u8;
signal env : u9;
signal wv_mul : u17;
-- pipelining
signal wv_raw_reg : u8;
signal env_reg : u9;
begin
NCO: process(clk1M, freq, test, count24) is
variable cur : u23;
begin
if (test='1') then
--count24 <= x"000000";
count24 <= "000" & x"00000";
chg_ph <= '0';
else
if (rising_edge(clk1M)) then
cur := count24;
cur := cur + freq;
--chg_ph <= cur(23) xor count24(23);
chg_ph <= cur(22) xor count24(22);
count24 <= cur;
end if;
end if;
end process NCO;
taps <= ((lfsr(0) xor lfsr(2)) xor lfsr(3)) xor lfsr(5);
noise: process(clk1M,test,chg_ph,taps,lfsr(15 downto 0)) is
begin
if (test='1') then
lfsr <= x"1337";
else
if (rising_edge(clk1M) and chg_ph='1') then
lfsr <= taps & lfsr(15 downto 1);
end if;
end if;
end process noise;
gen_tri: process(count24) is
variable calc : byte;
begin
for i in 0 to 6 loop
--calc(i+1) := count24(16+i) xor count24(23);
calc(i+1) := count24(15+i) xor count24(22);
end loop;
--calc(0) := count24(23);
calc(0) := count24(22);
wv_tri <= u8(calc);
end process gen_tri;
gen_saw: process(count24(22 downto 15)) is
begin
--wv_saw <= count24(23 downto 16);
wv_saw <= count24(22 downto 15);
end process gen_saw;
gen_pul: process(count24(22 downto 11),pw) is
variable sample : u12;
begin
--sample := count24(23 downto 12);
sample := count24(22 downto 11);
if ((pw = x"fff") or (sample < pw)) then
wv_pul <= x"ff";
else
wv_pul <= x"00";
end if;
end process gen_pul;
gen_wht: process(lfsr) is
begin
wv_wht <= lfsr(15) & lfsr(14) & lfsr(10) & lfsr( 9) &
lfsr( 5) & lfsr( 4) & lfsr( 3) & lfsr( 0);
end process gen_wht;
-- Handling of waveform selection signals
--
-- The ANDing of multiple waveforms when
-- multiple signals are on is supported
-- (excluding noise).
--
-- We are not replicating the noise-lock bug
-- when noise is combined with other waveforms
-- and c64 programs don't combine noise due to
-- this bug so it's not worthwhile to do so.
with wvfm select wv_raw <=
x"80" when "0000",
wv_tri when "0001",
wv_saw when "0010",
wv_tri and wv_saw when "0011",
wv_pul when "0100",
wv_pul and wv_tri when "0101",
wv_pul and wv_saw when "0110",
wv_pul and wv_tri and wv_saw when "0111",
wv_wht when others;
hold_wvraw: process(clk1M,wv_raw) is
begin
if (rising_edge(clk1M)) then
wv_raw_reg <= wv_raw;
end if;
end process hold_wvraw;
-- TODO: envelope generation
env <= '0' & x"ff";
hold_env: process(clk1M,env) is
begin
if (rising_edge(clk1M)) then
env_reg <= env+1;
end if;
end process hold_env;
hold_vmult: process(clk1M, env_reg, wv_raw_reg) is
begin
if (rising_edge(clk1M)) then
wv_mul <= env_reg * wv_raw_reg;
end if;
end process hold_vmult;
uout <= wv_mul(15 downto 8);
envo <= env_reg(7 downto 0);
osco <= wv_raw_reg;
end sid_voice_impl;
| gpl-3.0 | a941bfb0442b78ad9df2adf5e0ea3026 | 0.527365 | 3.290032 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/chip6502.vhd | 1 | 165,136 | ----------------------------------------------------------------------------------
--
-- Takes all the VHDL bits and makes a 6510 (6502) out of them
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity chip6502 is
port (
a : out std_logic_vector(15 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end chip6502;
architecture interaction of chip6502 is
subtype slv2 is std_logic_vector(1 downto 0);
subtype u8 is unsigned(7 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype word is std_logic_vector(15 downto 0);
constant v_nmi_l : word := x"FFFA";
constant v_nmi_h : word := x"FFFB";
constant v_res_l : word := x"FFFC";
constant v_res_h : word := x"FFFD";
constant v_irq_l : word := x"FFFE";
constant v_irq_h : word := x"FFFF";
component clockgen
port (
ph4Xin : in std_logic;
ph0 : out std_logic;
ph1 : out std_logic;
ph2 : out std_logic;
stg : out slv2;
res0 : in std_logic
);
end component;
subtype clkstg_t is std_logic_vector(1 downto 0);
signal clkStg : clkstg_t;
signal iph0 : std_logic;
signal iph1 : std_logic;
signal iph2 : std_logic;
constant sysclk_PH2_p : clkstg_t := "00";
constant sysclk_PH2_m : clkstg_t := "01";
constant sysclk_PH1_p : clkstg_t := "10";
constant sysclk_PH1_m : clkstg_t := "11";
component ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in byte;
dout : out byte;
ioi : in byte;
ioo : out byte
);
end component;
signal io_o : byte;
signal io_i : byte;
signal io_ce : std_logic;
signal io_clk : std_logic;
component alu_8bit
port (
a_in : in byte;
b_in : in byte;
c_in : in std_logic;
d_in : in std_logic; -- the dreaded BCD mode
op_in : in unsigned(2 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
r_out : out byte
);
end component;
signal ALUcin : std_logic;
signal ALUdin : std_logic;
signal ALUain : byte;
signal ALUbin : byte;
signal ALUop : unsigned(2 downto 0);
signal ALUrout : byte;
signal ALUnout : std_logic;
signal ALUvout : std_logic;
signal ALUzout : std_logic;
signal ALUcout : std_logic;
signal regbus : byte;
signal outval : byte;
signal abus : word;
signal DBen : std_logic := '1';
signal DBrw : std_logic := '1';
signal dbRE : std_logic;
signal dbWE : std_logic;
signal nDBen : std_logic;
signal aen0 : std_logic := '1';
signal aen1 : std_logic;
alias abus_off is aen0;
subtype seqType is byte;
function countSeq(src : seqType) return seqType is
variable v : unsigned(7 downto 0);
begin
v := unsigned(src);
v := v + 1;
return seqType(v);
end countSeq;
signal seq : seqType := x"00";
subtype dbctl_t is std_logic_vector(2 downto 0);
signal DB_ctl : dbctl_t := "011";
alias dbctl_sync : std_logic is DB_ctl(2);
alias dbctl_off : std_logic is DB_ctl(1);
alias dbctl_r1w0 : std_logic is DB_ctl(0);
subtype aop_t is std_logic_vector(2 downto 0);
signal aop : aop_t := "000";
constant aop_add : aop_t := "000";
constant aop_and : aop_t := "001";
constant aop_or : aop_t := "010";
constant aop_xor : aop_t := "011";
constant aop_lsl : aop_t := "100";
constant aop_lsr : aop_t := "101";
constant aop_rol : aop_t := "110";
constant aop_ror : aop_t := "111";
signal alu_bin_mode : slv2;
constant bin_reg : slv2 := "00";
constant bin_set : slv2 := "01";
constant bin_clr : slv2 := "10";
constant bin_ireg : slv2 := "11";
signal alu_cin_mode : slv2;
constant cin_psw : slv2 := "00";
constant cin_set : slv2 := "01";
constant cin_clr : slv2 := "10";
constant cin_aux : slv2 := "11";
signal alu_din_mode : std_logic;
constant din_clr : std_logic := '0';
constant din_psw : std_logic := '1';
--signal alu_bin_reg : byte;
alias alu_bin_reg : byte is ALUbin;
signal alu_bin_tie : byte;
type stage_t is (
stg_reset,
stg_fetch,
stg_sub_incpc, -- pc++
stg_sub_imm, -- mem=pc++
stg_sub_abs, -- meml=[pc++], memh=[pc++]
stg_sub_absx, -- meml=[X+(PC++)], memh=[C+(PC++)]
stg_sub_absy, -- meml=[Y+(PC++)], memh=[C+(PC++)]
stg_sub_zp, -- meml=[PC++], memh=[0]
stg_sub_zpx, -- meml=[X+(PC++)], memh=[0]
stg_sub_zpy, -- meml=[Y+(PC++)], memh=[0]
stg_sub_indx, -- buf2l=[X+(PC++)], buf2h=[0]. mem=[buf2].w
stg_sub_indy, -- buf2l=[PC++], buf2h=[0], mem=[Y+buf2].w
stg_mem2buf, -- BUF=[mem]
stg_mem2a, -- A=[mem]
stg_aCMPmem, -- NZC=A-[mem]
stg_aADDmem, -- NVZC,A=A+[mem]
stg_aSUBmem, -- NVZC,A=A-[mem]
stg_aORmem, -- A=A|[mem]
stg_aXORmem, -- A=A^[mem]
stg_aANDmem, -- A=A&mem
stg_xCMPmem, -- NZC=X-[mem]
stg_yCMPmem, -- NZC=Y-[mem]
stg_mem2x, -- X=[mem]
stg_mem2y, -- Y=[mem]
stg_a2mem, -- [mem]=A
stg_x2mem, -- [mem]=X
stg_y2mem, -- [mem]=Y
stg_ASLmem, -- ***TODO*** C <-- [7][mem][0] <-- 0
stg_ROLmem, -- ***TODO*** C <-- [7][mem][0] <-- C
stg_LSRmem, -- ***TODO*** 0 --> [7][mem][0] --> C
stg_RORmem, -- ***TODO*** C --> [7][mem][0] --> C
stg_INCmem, -- NZ=++[mem]
stg_DECmem, -- NZ=--[mem]
stg_BITmem, -- Z=[mem]&A, NV=[mem][7:6]
-- All interrupts can be handled as BRK w/flag-checks
stg_BRK, -- ***TODO*** ++PC, B=1, raise (unmaskable) IRQ
--stg_IRQ, -- [SP--]=PCH, [SP--]=PCL, [SP--]=PSW, I=1, PCL=[v_irq_l], PCH=[v_irq_h]
--stg_NMI, -- [SP--]=PCH, [SP--]=PCL, [SP--]=PSW, I=1, PCL=[v_nmi_l], PCH=[v_nmi_h]
stg_CLC,
stg_SEC,
stg_CLI,
stg_SEI,
stg_CLV,
stg_CLD,
stg_SED,
stg_TXS,
stg_TSX,
stg_PHA,
stg_PLA,
stg_PHP,
stg_PLP,
stg_TAX,
stg_TXA,
stg_TAY,
stg_TYA,
stg_DEX,
stg_DEY,
stg_INX,
stg_INY,
stg_JMP_abs,
stg_JMP_ind,
stg_reljmp, -- take branch
stg_BCC,
stg_BCS,
stg_BNE,
stg_BEQ,
stg_BPL,
stg_BMI,
stg_BVC,
stg_BVS,
stg_ASL_a,
stg_LSR_a,
stg_ROL_a,
stg_ROR_a,
stg_RTS,
stg_RTI,
stg_JSR,
stg_tail
);
signal seq_stage : stage_t := stg_reset;
signal ret_stage : stage_t := stg_fetch; -- return stage for sub stage
signal ir : byte := x"00";
signal reg_a : byte := x"00";
signal reg_x : byte := x"00";
signal reg_y : byte := x"00";
signal reg_pc : word := x"0000";
signal reg_sp : byte := x"00";
signal reg_p : byte := x"00";
alias psw_n is reg_p(7);
alias psw_v is reg_p(6);
alias psw_b is reg_p(4);
alias psw_d is reg_p(3);
alias psw_i is reg_p(2);
alias psw_z is reg_p(1);
alias psw_c is reg_p(0);
signal buf_data : byte := x"00";
signal buf_addr : word := x"0000";
signal buf2 : word := x"0000";
alias reg_pcl : byte is reg_pc(7 downto 0);
alias reg_pch : byte is reg_pc(15 downto 8);
alias buf_addr_l : byte is buf_addr(7 downto 0);
alias buf_addr_h : byte is buf_addr(15 downto 8);
alias buf2l : byte is buf2(7 downto 0);
alias buf2h : byte is buf2(15 downto 8);
signal private_c : std_logic;
signal NMI_last : std_logic;
function isZero(src: byte) return std_logic is
begin
return ((src(0) nor src(1)) and (src(2) nor src(3))) and
((src(4) nor src(5)) and (src(6) nor src(7)));
end isZero;
function dec(arg : byte) return byte is
variable argu : unsigned(8 downto 0);
begin
argu := ('0' & u8(arg)) - "000000001";
return byte(argu(7 downto 0));
end dec;
function inc(arg : byte) return byte is
variable argu : unsigned(8 downto 0);
begin
argu := ('0' & u8(arg)) + "000000001";
return byte(argu(7 downto 0));
end inc;
function inc16(arg : word) return word is
variable argu : unsigned(16 downto 0);
begin
argu := ('0' & u16(arg)) + ('0' & x"01");
return word(argu(15 downto 0));
end inc16;
function sgn(arg : byte) return byte is
variable tbyt : byte;
begin
tbyt:= arg(7) & arg(7) & arg(7) & arg(7) &
arg(7) & arg(7) & arg(7) & arg(7);
return tbyt;
end sgn;
function getb(arg : byte; bp : integer) return std_logic is
begin
return arg(bp);
end getb;
begin
clock: clockgen port map(
ph4Xin => ph4Xin,
ph0 => iph0,
ph1 => iph1,
ph2 => iph2,
stg => clkStg,
res0 => res0
);
ph0 <= iph0;
ph1 <= iph1;
ph2 <= iph2;
io8bit: ioport8bit port map(
ce => io_ce,
clk => io_clk,
res0 => res0,
r1w0 => dbRW,
a => abus(0),
din => io_i,
dout => io_o,
ioi => pi,
ioo => po
);
io_clk <= (not clkStg(1)) and clkStg(0);
io_ce <= not ( (((abus(15) or abus(14)) or (abus(13) or abus(12))) or
((abus(11) or abus(10)) or (abus( 9) or abus( 8)))) or
(((abus( 7) or abus( 6)) or (abus( 5) or abus( 4))) or
((abus( 3) or abus( 2)) or abus( 1) )) );
io_i <= regbus;
alunit: alu_8bit port map(
a_in => ALUain,
b_in => ALU_bin_tie,
c_in => ALUcin,
d_in => ALUdin,
op_in => ALUop,
n_out => ALUnout,
v_out => ALUvout,
z_out => ALUzout,
c_out => ALUcout,
r_out => ALUrout
);
alu_cin_mux: process(alu_cin_mode,psw_c,private_c) is
begin
case alu_cin_mode is
when cin_set => ALUcin <= '1';
when cin_clr => ALUcin <= '0';
when cin_aux => ALUcin <= private_c;
when others => ALUcin <= psw_c;
end case;
end process alu_cin_mux;
alu_din_mux: process(alu_din_mode,psw_d) is
begin
case alu_din_mode is
when din_clr => ALUdin <= '0';
when others => ALUdin <= psw_d;
end case;
end process alu_din_mux;
alu_bin_mux: process(alu_bin_mode,alu_bin_reg) is
begin
case alu_bin_mode is
when bin_clr => alu_bin_tie <= "00000000";
when bin_set => alu_bin_tie <= "11111111";
when bin_ireg => alu_bin_tie <= not alu_bin_reg;
when others => alu_bin_tie <= alu_bin_reg;
end case;
end process alu_bin_mux;
sync <= DB_ctl(2);
DBen <= DB_ctl(1);
DBrw <= DB_ctl(0);
nDBen <= not DBen;
DBre <= DBrw;
DBwe <= not DBrw;
aen1 <= not aen0;
r1w0 <= DBrw;
ALUop <= unsigned(aop);
-- Allow connection of data bus as output during write operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_ogate: process(nDBen,DBwe,outval) iS
begin
if ((nDBen and DBwe) = '1') then
if (io_ce='1') then
do <= io_o;
else
do <= outval;
end if;
else
do <= "ZZZZZZZZ";
end if;
end process db_ogate;
-- Allow connection of data bus as input during read operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_igate: process(nDBen,DBre,di) is
begin
if ((nDBen and DBre) = '1') then
regbus <= di;
else
regbus <= "ZZZZZZZZ";
end if;
end process db_igate;
addr_gate: process(aen1,abus) is
begin
if (aen1='1') then
a <= abus;
else
a <= "ZZZZZZZZZZZZZZZZ";
end if;
end process addr_gate;
main_proc: process(res0,ph4Xin) is
variable doNMI : std_logic;
variable doBRK : std_logic;
variable tmp8 : byte;
begin
-- Status register stuff
reg_p(5) <= '0';
if (so0 = '0') then
psw_V <= '1';
end if;
if (res0 = '0') then
seq <= x"00";
seq_stage <= stg_reset;
ret_stage <= stg_reset;
dbctl_r1w0 <= '1';
dbctl_off <= '1';
dbctl_sync <= '0';
abus_off <= '1';
elsif (rising_edge(ph4Xin)) then
-- allows sensing NMI on any clock
-- (but won't trigger until epilogue)
doNMI := doNMI or (NMI_last and (not nmi0)); -- only on transition to '0'
NMI_last <= nmi0; -- saves the state read
-- reset stage
if (seq_stage = stg_reset) then
if ((not (clkStg = sysclk_PH2_m)) and seq=x"00") then
else
-- we enter here at seq x00 on PH1+
case seq is
when x"00" => seq <= countSeq(seq); -- PH1+: put RES vector L on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= v_res_l;
doNMI := '0';
doBRK := '0';
psw_I <= '1';
psw_B <= '0';
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) write to PCL
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put RES vector H on abus
abus <= v_res_h;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
seq_stage <= stg_fetch; -- change to instruction decode
seq <= x"00";
when others => null;
end case;
end if;
end if;
-- instruction fetch/decode stage
if (seq_stage = stg_fetch) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
doBRK := '0'; -- clear BRK flag
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
dbctl_sync <= '1'; -- sync on for instruction decode
abus_off <= '0';
abus <= reg_pc; -- PC on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) get instruction
ir <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: sync off
dbctl_sync <= '0';
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"05" => -- PH1-: store PCL=1+PCL
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"07" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
if (rdy = '1') then
abus_off <= '0';
dbctl_off <= '0';
seq <= x"00";
case ir is
when x"00" => -- BRK
doBRK := '1'; -- set BRK flag
ret_stage <= stg_tail;
seq_stage <= stg_sub_incpc; -- bump PC (BRK runs in epilogue)
when x"4C" =>
seq_stage <= stg_JMP_abs; -- JMP abs
when x"6C" =>
seq_stage <= stg_JMP_ind; -- JMP ind
when x"18" =>
seq_stage <= stg_CLC; -- CLC
when x"38" =>
seq_stage <= stg_SEC; -- SEC
when x"58" =>
seq_stage <= stg_CLI; -- CLI
when x"78" =>
seq_stage <= stg_SEI; -- SEI
when x"B8" =>
seq_stage <= stg_CLV; -- CLV
when x"D8" =>
seq_stage <= stg_CLD; -- CLD
when x"F8" =>
seq_stage <= stg_SED; -- SED
when x"A9" => -- LDA
ret_stage <= stg_mem2a; -- imm
seq_stage <= stg_sub_imm;
when x"AD" => -- abs
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_abs;
when x"BD" => -- abs+x
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_absx;
when x"B9" => -- abs+y
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_absy;
when x"A5" => -- zp
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_zp;
when x"B5" => -- zp+x
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_zpx;
when x"A1" => -- indirect,X
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_indx;
when x"B1" => -- indirect,Y
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_indy;
when x"A2" => -- LDX
ret_stage <= stg_mem2x; -- imm
seq_stage <= stg_sub_imm;
when x"AE" => -- abs
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_abs;
when x"BE" => -- abs+y
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_absy;
when x"A6" => -- zp
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_zp;
when x"B6" => -- zp+y
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_zpy;
when x"A0" => -- LDY
ret_stage <= stg_mem2y; -- imm
seq_stage <= stg_sub_imm;
when x"AC" => -- abs
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_abs;
when x"BC" => -- abs+x
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_absx;
when x"A4" => -- zp
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_zp;
when x"B4" => -- zp+x
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_zpx;
when x"8D" => -- STA
ret_stage <= stg_a2mem; -- abs
seq_stage <= stg_sub_abs;
when x"9D" => -- abs+x
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_absx;
when x"99" => -- abs+y
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_absy;
when x"85" => -- zp
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_zp;
when x"95" => -- zp+x
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_zpx;
when x"81" => -- indirect,X
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_indx;
when x"91" => -- indirect,Y
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_indy;
when x"8E" => -- STX
ret_stage <= stg_x2mem; -- abs
seq_stage <= stg_sub_abs;
when x"86" => -- zp
ret_stage <= stg_x2mem;
seq_stage <= stg_sub_zp;
when x"96" => -- zp+y
ret_stage <= stg_x2mem;
seq_stage <= stg_sub_zpy;
when x"8C" => -- STY
ret_stage <= stg_y2mem; -- abs
seq_stage <= stg_sub_abs;
when x"84" => -- zp
ret_stage <= stg_y2mem;
seq_stage <= stg_sub_zp;
when x"94" => -- zp+x
ret_stage <= stg_y2mem;
seq_stage <= stg_sub_zpx;
when x"09" => -- ORA A | mem
ret_stage <= stg_aORmem; -- imm
seq_stage <= stg_sub_imm;
when x"0D" => -- abs
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_abs;
when x"1D" => -- abs+x
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_absx;
when x"19" => -- abs+y
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_absy;
when x"05" => -- zp
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_zp;
when x"15" => -- zp+x
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_zpx;
when x"01" => -- indirect,X
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_indx;
when x"11" => -- indirect,Y
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_indy;
when x"29" => -- AND A & mem
ret_stage <= stg_aANDmem; -- imm
seq_stage <= stg_sub_imm;
when x"2D" => -- abs
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_abs;
when x"3D" => -- abs+x
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_absx;
when x"39" => -- abs+y
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_absy;
when x"25" => -- zp
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_zp;
when x"35" => -- zp+x
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_zpx;
when x"21" => -- indirect,X
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_indx;
when x"31" => -- indirect,Y
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_indy;
when x"24" => -- BIT Z=A&M, NV=[MEM][7:6]
ret_stage <= stg_BITmem; -- zp
seq_stage <= stg_sub_zp;
when x"2C" => -- abs
ret_stage <= stg_BITmem;
seq_stage <= stg_sub_abs;
when x"49" => -- EOR A ^ mem
ret_stage <= stg_aXORmem; -- imm
seq_stage <= stg_sub_imm;
when x"4D" => -- abs
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_abs;
when x"5D" => -- abs+x
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_absx;
when x"59" => -- abs+y
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_absy;
when x"45" => -- zp
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_zp;
when x"55" => -- zp+x
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_zpx;
when x"41" => -- indirect,X
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_indx;
when x"51" => -- indirect,Y
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_indy;
when x"69" => -- ADC C + A + mem
ret_stage <= stg_aADDmem; -- imm
seq_stage <= stg_sub_imm;
when x"6D" => -- abs
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_abs;
when x"7D" => -- abs+x
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_absx;
when x"79" => -- abs+y
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_absy;
when x"65" => -- zp
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_zp;
when x"75" => -- zp+x
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_zpx;
when x"61" => -- indirect,X
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_indx;
when x"71" => -- indirect,Y
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_indy;
when x"C9" => -- CMP NZC = A - mem
ret_stage <= stg_aCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"CD" => -- abs
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_abs;
when x"DD" => -- abs+x
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_absx;
when x"D9" => -- abs+y
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_absy;
when x"C5" => -- zp
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_zp;
when x"D5" => -- zp+x
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_zpx;
when x"C1" => -- indirect,X
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_indx;
when x"D1" => -- indirect,Y
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_indy;
when x"C0" => -- CPY NZC = Y - mem
ret_stage <= stg_yCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"C4" => -- zp
ret_stage <= stg_yCMPmem;
seq_stage <= stg_sub_zp;
when x"CC" => -- abs
ret_stage <= stg_yCMPmem;
seq_stage <= stg_sub_abs;
when x"E0" => -- CPX NZC = X - mem
ret_stage <= stg_xCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"E4" => -- zp
ret_stage <= stg_xCMPmem;
seq_stage <= stg_sub_zp;
when x"EC" => -- abs
ret_stage <= stg_xCMPmem;
seq_stage <= stg_sub_abs;
when x"E9" => -- SBC A + C - (mem+1)
ret_stage <= stg_aSUBmem; -- imm
seq_stage <= stg_sub_imm;
when x"ED" => -- abs
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_abs;
when x"FD" => -- abs+x
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_absx;
when x"F9" => -- abs+y
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_absy;
when x"E5" => -- zp
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_zp;
when x"F5" => -- zp+x
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_zpx;
when x"E1" => -- indirect,X
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_indx;
when x"F1" => -- indirect,Y
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_indy;
when x"9A" => -- TXS sp=x
seq_stage <= stg_TXS;
when x"BA" => -- TSX x=sp
seq_stage <= stg_TSX;
when x"48" => -- PHA [sp--]=a
seq_stage <= stg_PHA;
when x"68" => -- PLA a=[++sp]
seq_stage <= stg_PLA;
when x"08" => -- PHP [sp--]=P
seq_stage <= stg_PHP;
when x"28" => -- PLP P=[++sp]
seq_stage <= stg_PLP;
when x"AA" => -- TAX X=A
seq_stage <= stg_TAX;
when x"8A" => -- TXA A=X
seq_stage <= stg_TXA;
when x"A8" => -- TAY Y=A
seq_stage <= stg_TAY;
when x"98" => -- TYA A=Y
seq_stage <= stg_TYA;
when x"CA" => -- DEX X=X-1
seq_stage <= stg_DEX;
when x"88" => -- DEY Y=Y-1
seq_stage <= stg_DEY;
when x"C6" => -- DEC --[mem]
ret_stage <= stg_decmem; -- zp
seq_stage <= stg_sub_zp;
when x"D6" =>
ret_stage <= stg_decmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"CE" =>
ret_stage <= stg_decmem; -- abs
seq_stage <= stg_sub_abs;
when x"DE" =>
ret_stage <= stg_decmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"E8" => -- INX X=X+1
seq_stage <= stg_INX;
when x"C8" => -- INY Y=Y+1
seq_stage <= stg_INY;
when x"E6" => -- INC ++[mem]
ret_stage <= stg_incmem; -- zp
seq_stage <= stg_sub_zp;
when x"F6" =>
ret_stage <= stg_incmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"EE" =>
ret_stage <= stg_incmem; -- abs
seq_stage <= stg_sub_abs;
when x"FE" =>
ret_stage <= stg_incmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"10" => -- BPL PC+OP when N=0
seq_stage <= stg_BPL;
when x"30" => -- BMI PC+OP when N=1
seq_stage <= stg_BMI;
when x"50" => -- BVC PC+OP when V=0
seq_stage <= stg_BVC;
when x"70" => -- BVS PC+OP when V=1
seq_stage <= stg_BVS;
when x"90" => -- BCC PC+OP when C=0
seq_stage <= stg_BCC;
when x"B0" => -- BCS PC+OP when C=1
seq_stage <= stg_BCS;
when x"D0" => -- BNE PC+OP when Z=0
seq_stage <= stg_BNE;
when x"F0" => -- BEQ PC+OP when Z=1
seq_stage <= stg_BEQ;
when x"0A" => -- ASL C << T << '0'
seq_stage <= stg_ASL_a; -- a
when x"06" =>
ret_stage <= stg_ASLmem; -- zp
seq_stage <= stg_sub_zp;
when x"16" =>
ret_stage <= stg_ASLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"0E" =>
ret_stage <= stg_ASLmem; -- abs
seq_stage <= stg_sub_abs;
when x"1E" =>
ret_stage <= stg_ASLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"2A" => -- ROL C << T << C
seq_stage <= stg_ROL_a; -- a
when x"26" =>
ret_stage <= stg_ROLmem; -- zp
seq_stage <= stg_sub_zp;
when x"36" =>
ret_stage <= stg_ROLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"2E" =>
ret_stage <= stg_ROLmem; -- abs
seq_stage <= stg_sub_abs;
when x"3E" =>
ret_stage <= stg_ROLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"4A" => -- LSR '0' >> T >> C
seq_stage <= stg_LSR_a; -- a
when x"46" =>
ret_stage <= stg_LSRmem; -- zp
seq_stage <= stg_sub_zp;
when x"56" =>
ret_stage <= stg_LSRmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"4E" =>
ret_stage <= stg_LSRmem; -- abs
seq_stage <= stg_sub_abs;
when x"5E" =>
ret_stage <= stg_LSRmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"6A" => -- ROR C >> T >> C
seq_stage <= stg_ROR_a; -- a
when x"66" =>
ret_stage <= stg_RORmem; -- zp
seq_stage <= stg_sub_zp;
when x"76" =>
ret_stage <= stg_RORmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"6E" =>
ret_stage <= stg_RORmem; -- abs
seq_stage <= stg_sub_abs;
when x"7E" =>
ret_stage <= stg_RORmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"60" => -- RTS PCH=[++SP],PCL=[++SP],++PC
seq_stage <= stg_RTS;
when x"40" => -- RTI P=[++SP], PCH=[++SP],PCL=[++SP]
seq_stage <= stg_RTI;
when x"20" => -- JSR [email protected] to stack, PC=OP.w
seq_stage <= stg_JSR;
when others =>
seq_stage <= stg_tail; -- NOP
end case;
else
abus_off <= '1'; -- burn a full PH1/PH2 cycle if RDY=0
dbctl_off <= '1';
seq <= x"08";
end if;
when x"08" => seq <= countSeq(seq); -- PH1+: burn
when x"09" => seq <= countSeq(seq); -- PH1-: burn
when x"0A" => seq <= x"07"; -- PH2+: will check RDY again on PH2-
when others => null;
end case;
end if;
-- epilogue stage (also handles NOP)
-- checks for interrupts
if (seq_stage = stg_tail) then
case seq is
when x"00" => -- PH1+: burn
abus_off <= '0'; -- abus enabled
dbctl_off <= '0'; -- dbus enabled
dbctl_r1w0 <= '1'; -- dbus to read
abus <= reg_PC; -- sets addr to stop spurious I/O
seq <= countSeq(seq);
when x"01" => -- PH1-: burn
seq <= countSeq(seq);
when x"02" => -- PH2+: burn
seq <= countSeq(seq);
when x"03" =>
if (doNMI='1') then
-- perofrm edge-sensed NMI
seq_stage <= stg_BRK;
elsif (doBRK='1') then
-- perform BRK (IRQ, pushed PSW.B=1)
seq_stage <= stg_BRK;
elsif (irq0 = '0' and psw_I='0') then
-- perform IRQ when PSW.I=0
seq_stage <= stg_BRK;
else
seq_stage <= stg_fetch; -- PH2-: return to fetch (on PH1+)
end if;
seq <= x"00";
when others => null;
end case;
end if;
-- BRK/NMI/IRQ processing
if (seq_stage = stg_BRK) then
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: write
dbctl_r1w0 <= '0';
abus_off <= '0';
abus <= x"01" & reg_sp; -- write to stack
outval <= reg_pch; -- write PCH
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-:
reg_sp <= dec(reg_sp); -- ++SP
seq <= countSeq(seq);
when x"04" => -- PH1+:
abus <= x"01" & reg_sp; -- write to stack
outval <= reg_pcl; -- write PCL
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-:
reg_sp <= dec(reg_sp); -- ++SP
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= x"01" & reg_sp; -- write to stack
if (doBRK='1') then
outval <= reg_p(7 downto 6) &
"01" & reg_p(3 downto 0); -- write P with B=1
else
outval <= reg_p(7 downto 6) &
"00" & reg_p(3 downto 0); -- write P with B=0
end if;
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-:
reg_sp <= dec(reg_sp); -- ++SP
seq <= countSeq(seq);
when x"0c" => -- PH1+:
dbctl_r1w0 <= '1'; -- BUS: read
if (doNMI='1') then -- NMIL (ffFA) for NMI
abus <= v_nmi_l;
else
abus <= v_irq_l; -- IRQL (ffFE) otherwise
end if;
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-:
reg_pcl <= regbus; -- store to PCL
seq <= countSeq(seq);
when x"10" => -- PH1+:
if (doNMI='1') then -- NMIH (FFfa) for NMI
abus <= v_nmi_h;
else
abus <= v_irq_h; -- IRQH (FFfe) otherwise
end if;
seq <= countSeq(seq);
when x"11" => seq <= countSeq(seq); -- PH1-: pass
when x"12" => seq <= countSeq(seq); -- PH2+: pass
when x"13" => -- PH2-:
reg_pch <= regbus; -- store to PCH
doNMI:='0'; -- clear NMI flag
doBRK:='0'; -- clear BRK flag
psw_I <= '1'; -- ints masked for handler
seq <= x"00";
seq_stage <= stg_fetch; -- resume at instruction fetch
when others => null;
end case;
end if;
if (seq_stage = stg_sub_incpc) then
case seq is
when x"00" => -- PH1+:
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+1
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
seq <= x"00";
seq_stage <= ret_stage; -- PH2+: set return-to stage (on PH1+)
when others => null;
end case;
end if;
if (seq_stage = stg_incmem) then -- ++[MEM]
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: read from [MEM]
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr;
alu_cin_mode <= cin_set; -- ALU: Rout=Ain+1
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
ALUain <= regbus; -- [MEM] => Ain
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- BUS: write to [MEM]
psw_z <= ALUzout; -- NZ,Dout=[MEM]+1
psw_n <= ALUnout;
outval <= ALUrout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq <= x"00";
seq_stage <= stg_tail; -- instruction finished
when others => null;
end case;
end if;
if (seq_stage = stg_decmem) then -- --[MEM]
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: read from [MEM]
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr;
alu_cin_mode <= cin_clr; -- ALU: Rout=Ain-1
alu_bin_mode <= bin_set;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
ALUain <= regbus; -- [MEM] => Ain
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- BUS: write to [MEM]
psw_z <= ALUzout; -- NZ,Dout=[MEM]+1
psw_n <= ALUnout;
outval <= ALUrout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq <= x"00";
seq_stage <= stg_tail; -- instruction finished
when others => null;
end case;
end if;
if (seq_stage = stg_reljmp) then
case seq is -- PC+=(signed)BUF
when x"00" => -- PH1+:
ALUain <= reg_pcl;
ALUbin <= buf_data;
alu_cin_mode <= cin_clr;
alu_bin_mode <= bin_reg;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+BUF
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
ALUbin <= sgn(buf_data); -- sign extend BUF for PCH
alu_cin_mode <= cin_aux; -- apply carry from PCL+BUF
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C+sgn(BUF)
seq <= x"00";
seq_stage <= stg_tail; -- branch finished
when others => null;
end case;
end if;
-- JMP abs
if (seq_stage = stg_JMP_abs) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
reg_pcl <= buf_addr_l; -- copy buffered lobyte to PCL
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- JMP ind
if (seq_stage = stg_JMP_ind) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- save to MEML
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) write to PCH
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= buf_addr; -- put MEM on abus
ALUain <= buf_addr_l; -- set up for ++MEM
ALU_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf2l <= ALUrout;
private_c <= ALUcout; -- BUF2=MEM+1
seq <= countSeq(seq);
when x"0a" => -- PH2+:
ALUain <= buf_addr_h; --
ALU_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data)
reg_pcl <= regbus; -- PCL=(MEM)
buf_addr_l <= buf2l;
buf_addr_h <= ALUrout; -- ++MEM
seq <= countSeq(seq);
when x"0c" => -- PH1+:
abus <= buf_addr; -- put MEM (+1) on abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
reg_pch <= regbus; -- PCH=MEM (+1)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2buf) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
buf_data <= regbus; -- save to BUF
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2a) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= regbus; -- save to A
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aANDmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A and regbus; -- A = A & [mem]
psw_z <= isZero(reg_A and regbus); -- Z flag
psw_n <= getb(reg_A and regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_BITmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
psw_z <= isZero(regbus and reg_A); -- Z flag as if A & [mem]
psw_n <= regbus(7); -- N flag <= [mem][7]
psw_v <= regbus(6); -- V flag <= [mem][6]
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aADDmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_psw; -- P.D => din
alu_cin_mode <= cin_psw; -- P.C => cin
alu_bin_mode <= bin_reg; -- reg => bin
ALUain <= reg_a; -- A
aop <= aop_add; -- + P.C +
ALUbin <= regbus; -- mem
seq <= countSeq(seq);
when x"04" => -- PH1+:
reg_a <= ALUrout; -- store result
psw_n <= ALUnout;
psw_v <= ALUvout;
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aSUBmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_psw; -- P.D => din
alu_cin_mode <= cin_psw; -- P.C => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_a; -- A
aop <= aop_add; -- + P.C -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
reg_a <= ALUrout; -- store result
psw_n <= ALUnout;
psw_v <= ALUvout;
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_a; -- A
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_xCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_x; -- X
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_yCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_y; -- Y
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aORmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A or regbus; -- A = A | [mem]
psw_z <= isZero(reg_A or regbus); -- Z flag
psw_n <= getb(reg_A or regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aXORmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A xor regbus; -- A = A ^ [mem]
psw_z <= isZero(reg_A xor regbus); -- Z flag
psw_n <= getb(reg_A xor regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2x) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_x <= regbus; -- save to X
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2y) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_y <= regbus; -- save to Y
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_a2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_a; -- A to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_x2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_x; -- X to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_y2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_y; -- Y to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_imm) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
buf_addr <= reg_pc; -- MEM=PC
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout;
alu_cin_mode <= cin_aux;
ALUain <= reg_pch;
seq <= countSeq(seq);
when x"02" => -- PH2+:
reg_pch <= ALUrout; -- PC=PC+1
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) store data to A
seq <= x"00";
seq_stage <= ret_stage;
when others => null;
end case;
end if;
if (seq_stage = stg_sub_abs) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_absx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEM+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr) pass
buf_addr_l <= ALUrout; -- MEML=MEML+X
private_c <= ALUcout;
seq <= countSeq(seq);
when x"0A" => -- PH2+:
ALUain <= buf_addr_h;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux; -- MEMH+C
seq <= countSeq(seq);
when x"0B" => -- PH2-: (valid data)
buf_addr_h <= ALUrout; -- MEMH=MEMH+C
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_absy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEM+Y
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_y; -- MEML+Y
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
private_c <= ALUcout;
seq <= countSeq(seq);
when x"0A" => -- PH2+:
ALUain <= buf_addr_h;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux; -- MEMH+C
seq <= countSeq(seq);
when x"0B" => -- PH2-: (valid data)
buf_addr_h <= ALUrout; -- MEMH=MEMH+C
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zp) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zpx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+X
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_indx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- BUF2=00:MEML+X
buf2h <= x"00";
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => seq <= countSeq(seq); -- PH2-: (valid data) pass
when x"08" => -- PH1+:
abus <= buf2; -- buf2 on abus
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
buf_addr_l <= regbus; -- MEML=[buf2++]
buf2 <= inc16(buf2);
seq <= countSeq(seq);
when x"0c" => -- PH1+:
abus <= buf2; -- buf2 (+1) on abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
buf_addr_h <= regbus; -- MEMH=[buf2] (+1)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zpy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+Y
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_y; -- MEML+Y
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_indy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
buf2h <= x"00";
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
buf_addr_l <= regbus; -- MEML = [PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
abus <= x"00" & buf_addr_l; -- put 00:MEML on abus
buf2 <= x"00" & buf_addr_l; -- buf2=00:MEML
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) pass
buf_addr_l <= regbus; -- MEML = [BUF2]
buf2 <= inc16(buf2); -- ++buf2
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= buf2; -- buf2 (buf+1) on abus
ALUain <= buf_addr_l; -- start MEM=MEM+Y
ALUbin <= reg_y; -- MEML+Y
ALU_cin_mode <= cin_clr;
ALU_bin_mode <= bin_reg;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
private_c <= ALUcout;
alu_cin_mode <= cin_aux;
alu_bin_mode <= bin_clr;
seq <= countSeq(seq);
when x"0a" => -- PH2+:
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data)
ALUain <= regbus; -- C+[BUF2] (MSB)
seq <= countSeq(seq);
when x"0c" => -- PH1+:
buf_addr_h <= ALUrout; -- MEMH=C+[BUF2] (MSB)
seq <= countSeq(seq); -- MEM=MEM+Y done
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
-- CLC
if (seq_stage = stg_CLC) then
case seq is
when x"00" => -- PH1+: C=0
psw_c <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEC
if (seq_stage = stg_SEC) then
case seq is
when x"00" => -- PH1+: C=1
psw_c <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLI
if (seq_stage = stg_CLI) then
case seq is
when x"00" => -- PH1+: I=0
psw_i <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEI
if (seq_stage = stg_SEI) then
case seq is
when x"00" => -- PH1+: I=1
psw_i <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLV
if (seq_stage = stg_CLV) then
case seq is
when x"00" => -- PH1+: V=0
psw_v <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLD
if (seq_stage = stg_CLD) then
case seq is
when x"00" => -- PH1+: D=0
psw_d <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SED
if (seq_stage = stg_SED) then
case seq is
when x"00" => -- PH1+: D=1
psw_d <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXS
if (seq_stage = stg_TXS) then
case seq is
when x"00" => -- PH1+:
reg_sp <= reg_x; -- store SP=X
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TSX
if (seq_stage = stg_TSX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_sp; -- store X=SP
psw_z <= isZero(reg_sp); -- Z flag
psw_n <= reg_sp(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- PHA
if (seq_stage = stg_PHA) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= reg_a;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PHP
if (seq_stage = stg_PHP) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= (reg_p(7 downto 6) & "01" &
reg_p(3 downto 0)); -- 6502 quirk: B always set on pushed psw
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLA
if (seq_stage = stg_PLA) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_a <= regbus;
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLP
if (seq_stage = stg_PLP) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_p <= (regbus(7 downto 6) & "0" &
regbus(4 downto 0)); -- store status value (unused bit forced to 0)
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- TAX
if (seq_stage = stg_TAX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_a; -- store X=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXA
if (seq_stage = stg_TXA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_x; -- store A=X
psw_z <= isZero(reg_x); -- Z flag
psw_n <= reg_x(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TAY
if (seq_stage = stg_TAY) then
case seq is
when x"00" => -- PH1+:
reg_y <= reg_a; -- store Y=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TYA
if (seq_stage = stg_TYA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_y; -- store A=Y
psw_z <= isZero(reg_y); -- Z flag
psw_n <= reg_y(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- DEX
if (seq_stage = stg_DEX) then
case seq is
when x"00" => -- PH1+: BUF=x-1
buf_data <= dec(reg_x);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_x <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- DEY
if (seq_stage = stg_DEY) then
case seq is
when x"00" => -- PH1+: BUF=y-1
buf_data <= dec(reg_y);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_y <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- INX
if (seq_stage = stg_INX) then
case seq is
when x"00" => -- PH1+: BUF=x+1
buf_data <= inc(reg_x);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_x <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- INY
if (seq_stage = stg_INY) then
case seq is
when x"00" => -- PH1+: BUF=y+1
buf_data <= inc(reg_y);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_y <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- BCC
if (seq_stage = stg_BCC) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_C = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BCS
if (seq_stage = stg_BCS) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_C = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc; -- ++PC then branch or finish
when others => null;
end case;
end if;
-- BNE
if (seq_stage = stg_BNE) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_Z = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BEQ
if (seq_stage = stg_BEQ) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_Z = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BPL
if (seq_stage = stg_BPL) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_N = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BMI
if (seq_stage = stg_BMI) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_N = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BVC
if (seq_stage = stg_BVC) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_V = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BVS
if (seq_stage = stg_BVS) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_V = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- ASL A
if (seq_stage = stg_ASL_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := reg_a(6 downto 0) & '0'; -- tmp = A << 1
psw_c <= reg_a(7); -- C = A(7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ASL [mem]
if (seq_stage = stg_ASLmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := regbus(6 downto 0) & '0'; -- tmp = [mem] << 1
psw_c <= regbus(7); -- C = [mem](7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- LSR A
if (seq_stage = stg_LSR_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := '0' & reg_a(7 downto 1); -- tmp = A >> 1
psw_c <= reg_a(0); -- C = A(0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- LSR [mem]
if (seq_stage = stg_LSRmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := '0' & regbus(7 downto 1); -- tmp = [mem] >> 1
psw_c <= regbus(0); -- C = [mem](0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROL A
if (seq_stage = stg_ROL_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := reg_a(6 downto 0) & psw_c; -- tmp = A[6:0],C
psw_c <= reg_a(7); -- C = A(7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROL[mem]
if (seq_stage = stg_ROLmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := regbus(6 downto 0) & psw_c; -- tmp = [mem](6:0),C
psw_c <= regbus(7); -- C = [mem](7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROR A
if (seq_stage = stg_ROR_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := psw_c & reg_a(7 downto 1); -- tmp = C,A[7:1]
psw_c <= reg_a(0); -- C = A(0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROR [mem]
if (seq_stage = stg_RORmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := psw_c & regbus(7 downto 1); -- tmp = C,[mem](7:1)
psw_c <= regbus(0); -- C = [mem](0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- RTS (PCH=[++SP], PCL=[++SP], incpc, tail)
if (seq_stage = stg_RTS) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf_data <= ALUrout; -- we didn't have addr ready on PH1+
seq <= countSeq(seq); -- so we'll store this SP+1 in BUF
when x"02" => -- PH2+: and pipeline BUF+1 (SP+2)
ALUain <= buf_data; -- through this bus cycle
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"03" => seq <= countSeq(seq); -- PH2-: (valid data)
reg_sp <= ALUrout; -- SP=SP+2
seq <= countSeq(seq); -- BUF is PCL, SP is PCH
when x"04" => -- PH1+: put out address of PCL
abus <= (x"01" & buf_data); -- 01:BUF
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"08" => -- PH1+: put out address of PCH
abus <= (x"01" & reg_sp); -- 01:SP
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
reg_pch <= regbus;
seq <= countSeq(seq);
seq <= x"00";
ret_stage <= stg_tail; -- JSR saves PC-1 so we incpc
seq_stage <= stg_sub_incpc; -- first, then tail (done)
when others => null;
end case;
end if;
-- RTI (P=[++SP], PCH=[++SP], PCL=[++SP], tail)
if (seq_stage = stg_RTI) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) not yet available
reg_sp <= ALUrout; -- ++SP (now on psw)
ALUain <= ALUrout; -- set up next ++SP
seq <= countSeq(seq); -- we need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have addresses for bus
abus <= (x"01" & reg_sp); -- 01:sp (psw) to abus
reg_sp <= ALUrout; -- ++SP (now on PCL)
ALUain <= ALUrout; -- set up next ++SP
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
reg_p <= (regbus(7 downto 6) & "00" &
regbus(3 downto 0)); -- store psw (unused/brk set to 0)
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp (PCL) to abus
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
reg_pcl <= regbus; -- save PCL=[SP]
reg_sp <= ALUrout; -- ++SP (now on PCH)
seq <= countSeq(seq); -- BUF is PCL, SP is PCH
when x"0c" => -- PH1+: put out address of PCL
abus <= (x"01" & reg_sp); -- 01:sp (PCH) to abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
reg_pch <= regbus; -- save PCH=[SP]
seq <= x"00";
seq_stage <= stg_tail; -- instruction done
when others => null;
end case;
end if;
-- JSR (buf_addr=[pc].w, ++pc, [sp--]=PCL, [sp--]=PCH)
if (seq_stage = stg_JSR) then
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to MEMH
buf_addr_h <= regbus; -- (PC not yet saved)
seq <= countSeq(seq);
when x"08" => -- PH1+:
dbctl_r1w0 <= '0'; -- data bus to write mode
abus <= (x"01" & reg_sp); -- put out address of 01:SP
ALUain <= reg_sp; -- set up SP--
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- SP--
seq <= countSeq(seq);
when x"0a" => seq <= countSeq(seq); -- PH2+:
outval <= reg_pch; -- [01:SP]=PCH
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data) pass
seq <= countSeq(seq);
when x"0c" => -- PH1+:
dbctl_r1w0 <= '0'; -- data bus to write mode
abus <= (x"01" & reg_sp); -- put out address of 01:SP
ALUain <= reg_sp; -- set up SP--
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"0d" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- SP--
seq <= countSeq(seq);
when x"0e" => seq <= countSeq(seq); -- PH2+:
outval <= reg_pcl; -- [01:SP]=PCL
seq <= countSeq(seq);
when x"0f" => -- PH2-: (valid data)
dbctl_r1w0 <= '1'; -- shut off write
reg_pc <= buf_addr; -- PC=MEM
seq_stage <= stg_tail;
seq <= x"00"; -- instruction done
when others => null;
end case;
end if;
end if;
end process main_proc;
end interaction;
| gpl-3.0 | 28d519f356dca49f89d9d233b190d704 | 0.292153 | 4.966198 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/ArpPacketTx.vhd | 1 | 7,644 | ---------------------------------------------------------------------------------
-- Title : ARP Packet TX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ArpPacketTx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to Ethernet layer, sends ARP packets
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity ArpPacketTx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl := '0';
-- Data to send
arpSenderMac : in MacAddrType;
arpSenderIp : in IpAddrType;
arpTargetMac : in MacAddrType;
arpTargetIp : in IpAddrType;
arpOp : in slv(15 downto 0);
arpReq : in sl;
arpAck : out sl;
-- User data to be sent
ethTxData : out slv(7 downto 0);
ethTxDataValid : out sl;
ethTxDataLastByte : out sl;
ethTxDataReady : in sl
);
end ArpPacketTx;
architecture rtl of ArpPacketTx is
type StateType is (IDLE_S,
HTYPE_S, PTYPE_S, HLEN_S, PLEN_S, OPER_S,
SHA_S, SPA_S, THA_S, TPA_S, WAIT_S);
type RegType is record
state : StateType;
wrCount : slv(2 downto 0);
senderMac : MacAddrType;
senderIp : IpAddrType;
targetMac : MacAddrType;
targetIp : IpAddrType;
last : sl;
op : slv(15 downto 0);
ack : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
wrCount => (others => '0'),
senderMac => MAC_ADDR_INIT_C,
senderIp => IP_ADDR_INIT_C,
targetMac => MAC_ADDR_INIT_C,
targetIp => IP_ADDR_INIT_C,
last => '0',
op => (others => '0'),
ack => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,arpSenderMac,arpSenderIp,arpTargetMac,arpTargetIp,
arpOp,arpReq,ethTxDataReady,ethTxRst) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
v.ack := '0';
ethTxData <= (others => '0');
ethTxDataLastByte <= '0';
ethTxDataValid <= '0';
-- State machine
case(r.state) is
when IDLE_S =>
ethTxData <= (others => '0');
ethTxDataValid <= '0';
ethTxDataLastByte <= '0';
v.wrCount := (others => '0');
if arpReq = '1' then
-- Register all input MACs/IPs
v.senderMac := arpSenderMac;
v.senderIp := arpSenderIp;
v.targetMac := arpTargetMac;
v.targetIp := arpTargetIp;
v.op := arpOp;
v.state := HTYPE_S;
end if;
when HTYPE_S =>
ethTxData <= getByte(1-conv_integer(r.wrCount),ARP_HTYPE_C);
ethTxDataValid <= '1';
if ethTxDataReady = '1' then
v.wrCount := r.wrCount + 1;
if (r.wrCount = 1) then
v.wrCount := (others => '0');
v.state := PTYPE_S;
end if;
end if;
when PTYPE_S =>
ethTxData <= getByte(1-conv_integer(r.wrCount),ARP_PTYPE_C);
ethTxDataValid <= '1';
if ethTxDataReady = '1' then
v.wrCount := r.wrCount + 1;
if (r.wrCount = 1) then
v.wrCount := (others => '0');
v.state := HLEN_S;
end if;
end if;
when HLEN_S =>
ethTxData <= ARP_HLEN_C;
ethTxDataValid <= '1';
if ethTxDataReady = '1' then
v.state := PLEN_S;
end if;
when PLEN_S =>
ethTxData <= ARP_PLEN_C;
ethTxDataValid <= '1';
if ethTxDataReady = '1' then
v.state := OPER_S;
end if;
when OPER_S =>
ethTxData <= getByte(1-conv_integer(r.wrCount),r.op);
ethTxDataValid <= '1';
if ethTxDataReady = '1' then
v.wrCount := r.wrCount + 1;
if (r.wrCount = 1) then
v.wrCount := (others => '0');
v.state := SHA_S;
end if;
end if;
when SHA_S =>
ethTxData <= r.senderMac(5-conv_integer(r.wrCount));
ethTxDataValid <= '1';
if ethTxDataReady = '1' then
v.wrCount := r.wrCount + 1;
if (r.wrCount = 5) then
v.wrCount := (others => '0');
v.state := SPA_S;
end if;
end if;
when SPA_S =>
ethTxData <= r.senderIp(3-conv_integer(r.wrCount));
ethTxDataValid <= '1';
if ethTxDataReady = '1' then
v.wrCount := r.wrCount + 1;
if (r.wrCount = 3) then
v.wrCount := (others => '0');
v.state := THA_S;
end if;
end if;
when THA_S =>
ethTxData <= r.targetMac(5-conv_integer(r.wrCount));
ethTxDataValid <= '1';
if ethTxDataReady = '1' then
v.wrCount := r.wrCount + 1;
if (r.wrCount = 5) then
v.wrCount := (others => '0');
v.state := TPA_S;
end if;
end if;
when TPA_S =>
ethTxData <= r.targetIp(3-conv_integer(r.wrCount));
ethTxDataValid <= '1';
if (r.wrCount = 3) then
ethTxDataLastByte <= '1';
end if;
if ethTxDataReady = '1' then
v.wrCount := r.wrCount + 1;
if (r.wrCount = 3) then
v.wrCount := (others => '0');
v.state := WAIT_S;
end if;
end if;
when WAIT_S =>
ethTxDataValid <= '0';
ethTxDataLastByte <= '0';
v.ack := '1';
if (arpReq = '0') then
v.ack := '0';
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
arpAck <= r.ack;
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | c89302eb648c99449d3d5f0c816896cd | 0.434328 | 4.301632 | false | false | false | false |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/trace_cntrl_1_2/hdl/vhdl/trace_cntrl.vhd | 4 | 38,040 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity trace_cntrl is
generic (
C_S_AXI_TRACE_CNTRL_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_TRACE_CNTRL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
A_TDATA : IN STD_LOGIC_VECTOR (63 downto 0);
A_TVALID : IN STD_LOGIC;
A_TREADY : OUT STD_LOGIC;
A_TKEEP : IN STD_LOGIC_VECTOR (7 downto 0);
A_TSTRB : IN STD_LOGIC_VECTOR (7 downto 0);
A_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
A_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
A_TID : IN STD_LOGIC_VECTOR (4 downto 0);
A_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
B_TDATA : OUT STD_LOGIC_VECTOR (63 downto 0);
B_TVALID : OUT STD_LOGIC;
B_TREADY : IN STD_LOGIC;
B_TKEEP : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TSTRB : OUT STD_LOGIC_VECTOR (7 downto 0);
B_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0);
B_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
B_TID : OUT STD_LOGIC_VECTOR (4 downto 0);
B_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
s_axi_trace_cntrl_AWVALID : IN STD_LOGIC;
s_axi_trace_cntrl_AWREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_WVALID : IN STD_LOGIC;
s_axi_trace_cntrl_WREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH/8-1 downto 0);
s_axi_trace_cntrl_ARVALID : IN STD_LOGIC;
s_axi_trace_cntrl_ARREADY : OUT STD_LOGIC;
s_axi_trace_cntrl_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_ADDR_WIDTH-1 downto 0);
s_axi_trace_cntrl_RVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_RREADY : IN STD_LOGIC;
s_axi_trace_cntrl_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_TRACE_CNTRL_DATA_WIDTH-1 downto 0);
s_axi_trace_cntrl_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_trace_cntrl_BVALID : OUT STD_LOGIC;
s_axi_trace_cntrl_BREADY : IN STD_LOGIC;
s_axi_trace_cntrl_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of trace_cntrl is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"trace_cntrl,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.628000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=631,HLS_SYN_LUT=706}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000";
constant ap_ST_pp1_stg0_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000";
constant ap_ST_st12_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_28 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal data_compare_V : STD_LOGIC_VECTOR (63 downto 0);
signal length_r : STD_LOGIC_VECTOR (31 downto 0);
signal sample_rate : STD_LOGIC_VECTOR (31 downto 0);
signal A_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_62 : BOOLEAN;
signal ap_sig_cseq_ST_pp1_stg0_fsm_9 : STD_LOGIC;
signal ap_sig_69 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal tmp_5_fu_293_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal match_phi_fu_183_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal B_TDATA_blk_n : STD_LOGIC;
signal or_cond_reg_534 : STD_LOGIC_VECTOR (0 downto 0);
signal match_reg_179 : STD_LOGIC_VECTOR (0 downto 0);
signal i_reg_191 : STD_LOGIC_VECTOR (30 downto 0);
signal sample_rate_read_reg_407 : STD_LOGIC_VECTOR (31 downto 0);
signal length_read_reg_413 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_232_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_419 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_226_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal total_input_samples_reg_425 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_147 : BOOLEAN;
signal A_temp_data_V_reg_430 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_reg_435 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_reg_440 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_reg_445 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_reg_450 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_reg_455 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_250_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_171 : BOOLEAN;
signal tmp_5_reg_525 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_175 : BOOLEAN;
signal ap_sig_ioackin_B_TREADY : STD_LOGIC;
signal i_1_fu_298_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal or_cond_fu_342_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_fu_362_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal A_temp_last_V_reg_538 : STD_LOGIC_VECTOR (0 downto 0);
signal sample_counter_fu_86 : STD_LOGIC_VECTOR (31 downto 0);
signal sample_counter_1_fu_348_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_fu_90 : STD_LOGIC_VECTOR (31 downto 0);
signal samples_1_fu_367_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal A_temp_data_V_1_fu_94 : STD_LOGIC_VECTOR (63 downto 0);
signal A_temp_keep_V_1_fu_98 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_strb_V_1_fu_102 : STD_LOGIC_VECTOR (7 downto 0);
signal A_temp_user_V_1_fu_106 : STD_LOGIC_VECTOR (1 downto 0);
signal A_temp_id_V_1_fu_110 : STD_LOGIC_VECTOR (4 downto 0);
signal A_temp_dest_V_1_fu_114 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ioackin_B_TREADY : STD_LOGIC := '0';
signal tmp_1_fu_236_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_240_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_cast_fu_289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_fu_337_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st12_fsm_10 : STD_LOGIC;
signal ap_sig_372 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0);
component trace_cntrl_mul_32s_32s_32_7 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component trace_cntrl_trace_cntrl_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
data_compare_V : OUT STD_LOGIC_VECTOR (63 downto 0);
length_r : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_rate : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
trace_cntrl_trace_cntrl_s_axi_U : component trace_cntrl_trace_cntrl_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_TRACE_CNTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_TRACE_CNTRL_DATA_WIDTH)
port map (
AWVALID => s_axi_trace_cntrl_AWVALID,
AWREADY => s_axi_trace_cntrl_AWREADY,
AWADDR => s_axi_trace_cntrl_AWADDR,
WVALID => s_axi_trace_cntrl_WVALID,
WREADY => s_axi_trace_cntrl_WREADY,
WDATA => s_axi_trace_cntrl_WDATA,
WSTRB => s_axi_trace_cntrl_WSTRB,
ARVALID => s_axi_trace_cntrl_ARVALID,
ARREADY => s_axi_trace_cntrl_ARREADY,
ARADDR => s_axi_trace_cntrl_ARADDR,
RVALID => s_axi_trace_cntrl_RVALID,
RREADY => s_axi_trace_cntrl_RREADY,
RDATA => s_axi_trace_cntrl_RDATA,
RRESP => s_axi_trace_cntrl_RRESP,
BVALID => s_axi_trace_cntrl_BVALID,
BREADY => s_axi_trace_cntrl_BREADY,
BRESP => s_axi_trace_cntrl_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
data_compare_V => data_compare_V,
length_r => length_r,
sample_rate => sample_rate);
trace_cntrl_mul_32s_32s_32_7_U0 : component trace_cntrl_mul_32s_32s_32_7
generic map (
ID => 1,
NUM_STAGE => 7,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => sample_rate,
din1 => length_r,
ce => ap_const_logic_1,
dout => grp_fu_226_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_ioackin_B_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_1 = B_TREADY)))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
A_temp_data_V_1_fu_94_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_data_V_1_fu_94 <= A_TDATA;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_data_V_1_fu_94 <= A_temp_data_V_reg_430;
end if;
end if;
end process;
A_temp_dest_V_1_fu_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_dest_V_1_fu_114 <= A_TDEST;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_dest_V_1_fu_114 <= A_temp_dest_V_reg_455;
end if;
end if;
end process;
A_temp_id_V_1_fu_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_id_V_1_fu_110 <= A_TID;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_id_V_1_fu_110 <= A_temp_id_V_reg_450;
end if;
end if;
end process;
A_temp_keep_V_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_keep_V_1_fu_98 <= A_TKEEP;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_keep_V_1_fu_98 <= A_temp_keep_V_reg_435;
end if;
end if;
end process;
A_temp_strb_V_1_fu_102_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_strb_V_1_fu_102 <= A_TSTRB;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_strb_V_1_fu_102 <= A_temp_strb_V_reg_440;
end if;
end if;
end process;
A_temp_user_V_1_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
A_temp_user_V_1_fu_106 <= A_TUSER;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
A_temp_user_V_1_fu_106 <= A_temp_user_V_reg_445;
end if;
end if;
end process;
i_reg_191_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
i_reg_191 <= i_1_fu_298_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
i_reg_191 <= ap_const_lv31_0;
end if;
end if;
end process;
match_reg_179_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_reg_179 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
match_reg_179 <= ap_const_lv1_1;
end if;
end if;
end process;
sample_counter_fu_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
sample_counter_fu_86 <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and (ap_const_lv1_0 = or_cond_fu_342_p2))) then
sample_counter_fu_86 <= sample_counter_1_fu_348_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
sample_counter_fu_86 <= ap_const_lv32_0;
end if;
end if;
end process;
samples_fu_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
samples_fu_90 <= samples_1_fu_367_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
samples_fu_90 <= ap_const_lv32_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0)))) then
A_temp_data_V_reg_430 <= A_TDATA;
A_temp_dest_V_reg_455 <= A_TDEST;
A_temp_id_V_reg_450 <= A_TID;
A_temp_keep_V_reg_435 <= A_TKEEP;
A_temp_strb_V_reg_440 <= A_TSTRB;
A_temp_user_V_reg_445 <= A_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) and not((ap_const_lv1_0 = or_cond_fu_342_p2)))) then
A_temp_last_V_reg_538 <= A_temp_last_V_fu_362_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
length_read_reg_413 <= length_r;
sample_rate_read_reg_407 <= sample_rate;
tmp_reg_419 <= tmp_fu_232_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
or_cond_reg_534 <= or_cond_fu_342_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_4_reg_520 <= tmp_4_fu_250_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
tmp_5_reg_525 <= tmp_5_fu_293_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
total_input_samples_reg_425 <= grp_fu_226_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, A_TVALID, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY, tmp_3_fu_245_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
if ((not((A_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_3_fu_245_p2))) then
ap_NS_fsm <= ap_ST_st8_fsm_7;
elsif ((not((A_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_3_fu_245_p2)))) then
ap_NS_fsm <= ap_ST_st9_fsm_8;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
when ap_ST_pp1_stg0_fsm_9 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and (tmp_5_fu_293_p2 = ap_const_lv1_0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))))) then
ap_NS_fsm <= ap_ST_st12_fsm_10;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_9;
end if;
when ap_ST_st12_fsm_10 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXX";
end case;
end process;
A_TDATA_blk_n_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4)))) then
A_TDATA_blk_n <= A_TVALID;
else
A_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
A_TREADY_assign_proc : process(A_TVALID, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, tmp_5_fu_293_p2, match_phi_fu_183_p4, or_cond_reg_534, ap_sig_175, ap_sig_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((A_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175) or ((ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY))))))) then
A_TREADY <= ap_const_logic_1;
else
A_TREADY <= ap_const_logic_0;
end if;
end process;
A_temp_last_V_fu_362_p2 <= "1" when (samples_fu_90 = tmp_4_reg_520) else "0";
B_TDATA <= A_temp_data_V_1_fu_94;
B_TDATA_blk_n_assign_proc : process(B_TREADY, ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, or_cond_reg_534)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)))) then
B_TDATA_blk_n <= B_TREADY;
else
B_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
B_TDEST <= A_temp_dest_V_1_fu_114;
B_TID <= A_temp_id_V_1_fu_110;
B_TKEEP <= A_temp_keep_V_1_fu_98;
B_TLAST <= A_temp_last_V_reg_538;
B_TSTRB <= A_temp_strb_V_1_fu_102;
B_TUSER <= A_temp_user_V_1_fu_106;
B_TVALID_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it0, ap_reg_ppiten_pp1_it1, or_cond_reg_534, ap_sig_175, ap_reg_ioackin_B_TREADY)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = or_cond_reg_534)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and ap_sig_175)) and (ap_const_logic_0 = ap_reg_ioackin_B_TREADY)))) then
B_TVALID <= ap_const_logic_1;
else
B_TVALID <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st12_fsm_10)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_10)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_147_assign_proc : process(ap_CS_fsm)
begin
ap_sig_147 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
ap_sig_171_assign_proc : process(ap_CS_fsm)
begin
ap_sig_171 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
ap_sig_175_assign_proc : process(A_TVALID, tmp_5_fu_293_p2, match_phi_fu_183_p4)
begin
ap_sig_175 <= (not((tmp_5_fu_293_p2 = ap_const_lv1_0)) and (ap_const_lv1_0 = match_phi_fu_183_p4) and (A_TVALID = ap_const_logic_0));
end process;
ap_sig_28_assign_proc : process(ap_CS_fsm)
begin
ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_372_assign_proc : process(ap_CS_fsm)
begin
ap_sig_372 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
ap_sig_62_assign_proc : process(ap_CS_fsm)
begin
ap_sig_62 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
ap_sig_69_assign_proc : process(ap_CS_fsm)
begin
ap_sig_69 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
ap_sig_cseq_ST_pp1_stg0_fsm_9_assign_proc : process(ap_sig_69)
begin
if (ap_sig_69) then
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_9 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st12_fsm_10_assign_proc : process(ap_sig_372)
begin
if (ap_sig_372) then
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_10 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28)
begin
if (ap_sig_28) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_147)
begin
if (ap_sig_147) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_62)
begin
if (ap_sig_62) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_171)
begin
if (ap_sig_171) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
ap_sig_ioackin_B_TREADY_assign_proc : process(B_TREADY, ap_reg_ioackin_B_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_B_TREADY)) then
ap_sig_ioackin_B_TREADY <= B_TREADY;
else
ap_sig_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end process;
i_1_fu_298_p2 <= std_logic_vector(unsigned(i_reg_191) + unsigned(ap_const_lv31_1));
i_cast_fu_289_p1 <= std_logic_vector(resize(unsigned(i_reg_191),32));
match_phi_fu_183_p4_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_9, ap_reg_ppiten_pp1_it1, match_reg_179, tmp_5_reg_525)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_9) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not((ap_const_lv1_0 = tmp_5_reg_525)))) then
match_phi_fu_183_p4 <= ap_const_lv1_0;
else
match_phi_fu_183_p4 <= match_reg_179;
end if;
end process;
or_cond_fu_342_p2 <= (tmp_7_fu_337_p2 or match_phi_fu_183_p4);
sample_counter_1_fu_348_p2 <= std_logic_vector(unsigned(sample_counter_fu_86) + unsigned(ap_const_lv32_1));
samples_1_fu_367_p2 <= std_logic_vector(unsigned(samples_fu_90) + unsigned(ap_const_lv32_1));
tmp_1_fu_236_p1 <= A_TDATA(32 - 1 downto 0);
tmp_2_fu_240_p2 <= (tmp_reg_419 and tmp_1_fu_236_p1);
tmp_3_fu_245_p2 <= "1" when (tmp_2_fu_240_p2 = tmp_reg_419) else "0";
tmp_4_fu_250_p2 <= std_logic_vector(signed(length_read_reg_413) + signed(ap_const_lv32_FFFFFFFF));
tmp_5_fu_293_p2 <= "1" when (signed(i_cast_fu_289_p1) < signed(total_input_samples_reg_425)) else "0";
tmp_7_fu_337_p2 <= "1" when (sample_counter_fu_86 = sample_rate_read_reg_407) else "0";
tmp_fu_232_p1 <= data_compare_V(32 - 1 downto 0);
end behav;
| bsd-3-clause | b351e4f6858725247fc5ed6f4ef8e923 | 0.586041 | 2.726295 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/ALU.vhd | 1 | 19,779 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 12/04/2017 08:30:06 AM
-- Module Name: ALU - Behavioral
-- Description:
--
-- Additional Comments: Omitted MULSHU because it is a special snowflake.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.NUMERIC_BIT.ALL;
library config;
use work.config.all;
entity ALU is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
halt: in std_logic; -- Do nothing
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end ALU;
architecture Behavioral of ALU is
-- component declaration
component Shifter is
port (
clk : in std_logic;
rst : in std_logic;
ctrl: in instr_t;
i_a1 : in std_logic_vector(63 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
result: out doubleword
);
end component;
-- Signals and constants
constant all_bits_set : doubleword := (others => '1');
signal result: doubleword;
signal feedback: std_logic_vector(2 downto 0); -- (Error, Overflow, Zero)
signal mul_reg: std_logic_vector(127 downto 0);
signal mul_reg_plus: std_logic_vector(129 downto 0); -- Special case for MULSHU
signal add_word: doubleword;
-- Shift unit signals
signal s_shift_amt: std_logic_vector(5 downto 0);
signal s_shift_arg: doubleword;
signal s_shift_result: doubleword;
begin
-- Instantiation
myShifter : Shifter
port map(
clk => clk,
rst => rst,
ctrl => ctrl,
i_a1 => s_shift_arg, -- Operand 1
i_a2 => s_shift_amt, -- Shift bits number
result => s_shift_result
);
process(clk, rst)
-- variable shift_limit: natural;;
begin
-- shift_arg <= to_integer(unsigned(shamt));
feedback <= "000";
if(rising_edge(clk)) then
if('0' = halt) then
if('1' = rst) then
result <= (others => '0');
else
case ctrl is
-- Treat as 32-bit operands
when instr_SLL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
-- shift_limit := to_integer(unsigned(shamt));
-- result <= zero_word & rs1(31 - shift_limit downto 0) & zero_word(shift_limit-1 downto 0);
when instr_SRL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRA =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADD =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
when instr_ADDI =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_SUB =>
result <= std_logic_vector(signed(rs1) - signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_LUI =>
-- In brief: rd = sign_extend(rsimm20 << 12)
-- Load low 20 of immediate value shifted left 12
-- sign extend to fit 64 bit system
result(31 downto 0) <= rs2(19 downto 0) & "000000000000";
result(63 downto 32) <= (others => rs2(19));
when instr_AUIPC =>
-- TODO verify that PC can easily be passed in here as arg 1
-- In brief: rd = PC + (rs << 12)
-- Load 20 MSBs of low word with low 20 of immediate value
-- sign extend (rs << 12) to fit 64 bit
-- NOTE: Here, we use a "qualified expression" to hint at how the compiler should resolve
-- the ambiguity. We give a hint as to which overloaded function should be used,
-- in this case, the one that takes in a bit vector constant and a std_logic_vector
-- and returns a std_logic_vector.
--auipc_ext(31 downto 0) := std_logic_vector'(rs2(19 downto 0) & "000000000000");
result <= std_logic_vector(signed(rs1) + signed(std_logic_vector'(rs2(19 downto 0) & "000000000000")));
when instr_XOR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_XORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_OR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_ORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_AND =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_ANDI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_SLT =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTI =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTIU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLLW =>
-- Since these are word operations instead of double
-- word operations, only use the bottom 5 bits instead of 6
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADDW =>
add_word <= std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_ADDIW =>
add_word <= std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_SUBW =>
add_word <= std_logic_vector(signed(rs1) - signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_MUL =>
mul_reg <= std_logic_vector(signed(rs1) * signed(rs2));
result <= mul_reg(63 downto 0);
when instr_MULH =>
mul_reg <= std_logic_vector(signed(rs1) * signed(rs2));
result <= zero_word & mul_reg(63 downto 32);
when instr_MULHU =>
mul_reg <= std_logic_vector(unsigned(rs1) * unsigned(rs2));
result <= zero_word & mul_reg(63 downto 32);
--when instr_MULHSU =>
-- TODO - verify that this multiplier does not introduce problems on the schematic/layout
--mul_reg_plus <= std_logic_vector(signed(rs1(31) & rs1) * signed('0' & rs2));
--result <= zero_word & mul_reg_plus(63 downto 32);
--
-- Special Values for Divide by Zero and Division Overflow (per 2.2 spec)
-- Situation || Special Return Values for Each Instruction
-- <condition> <Dividend> <Divisor> || <DIVU> <REMU> <DIV> <REM>
-- Divide by 0 x 0 || All bits set x -1 x
-- Overflow -(2^64 -1) -1 || N/A N/A -(2^(64-1)) 0
--
when instr_DIV =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg <= all_bits_set & all_bits_set;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set only MSB
mul_reg <= (63 => '1', others => '0');
else
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1) / signed(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_DIVU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to all ones
mul_reg <= all_bits_set & all_bits_set;
else
mul_reg <= zero_word & zero_word & std_logic_vector(unsigned(rs1) / unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_REM =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set result to 0
mul_reg <= (others => '0');
else
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1) rem signed(rs2));
end if;
result(31 downto 0) <= mul_reg(31 downto 0);
result(63 downto 32) <= (others => mul_reg(31));
when instr_REMU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
else
mul_reg <= zero_word & zero_word & std_logic_vector(unsigned(rs1) rem unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_MULW =>
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) * signed(rs2(31 downto 0)));
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg <= all_bits_set & all_bits_set;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set only MSB
mul_reg <= (31 => '1', others => '0');
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) / signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to all ones
mul_reg <= all_bits_set & all_bits_set;
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) / unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set result to 0
mul_reg <= (others => '0');
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) rem signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) rem unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when others =>
-- Error condition: unknown control code
feedback(0) <= '1';
result <= (others => '0');
end case;
end if; -- Reset
end if; -- Halt
end if; -- Clock
end process;
error <= feedback(0); -- TODO feedback single bit for error conditions.
overflow <= feedback(1);-- TODO check here, remove from logic above
zero <= '1' when (0 = unsigned(result)) else '0';
rout <= result;
end Behavioral; | mit | ee879dc1b8a596cbe1b35816c27a2e51 | 0.392335 | 4.942279 | false | false | false | false |
satputeaditya/vernier-ring-oscillator-tdc | fast_oscillator.vhd | 1 | 667 | -- fast_Oscillator.vhd
--************************************
-- Program to simulate fast oscillator
--************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
entity fast_oscillator is
port (
stop : in std_logic;
fast_clk : out std_logic:='0'
);
end entity;
architecture behave of fast_oscillator is
signal clk: std_logic:='0';
begin
process(clk,Stop)
begin
if Stop = '1' then
clk <= not clk after 99 pS;
elsif stop = '0' then
clk <= '0';
end if;
end process;
fast_clk <= clk;
end behave; | mit | 69373afce4c15def68357481bb1481f6 | 0.535232 | 3.335 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/i2c_xcvr.vhd | 2 | 6,000 | ----------------------------------------------------------------------------------
--
-- I2C Transceiver
--
-- Used to send SSM2603 initialization data via I2C
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_xcvr is
port (
-- with 1 MHz clock SSM2603 reg 9 delay step is 65.535 ms:
clk1M : in std_logic;
-- tie to system reset
res0 : in std_logic;
-- initialization line number
init_line : out unsigned(7 downto 0);
-- initialization data xRRRRRRRxxxxxxxDDDDDDDDD
init_data : in std_logic_vector(19 downto 0);
-- error status
error : out std_logic;
-- tie directly to ac_scl and ac_sda accordingly:
scl : inout std_logic;
sda : inout std_logic
);
end i2c_xcvr;
architecture i2c_init_guts of i2c_xcvr is
subtype byte is std_logic_vector(7 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype slv20 is std_logic_vector(19 downto 0);
subtype slv27 is std_logic_vector(26 downto 0);
constant dac_addr_w : byte := "0011010" & "0";
constant dac_addr_r : byte := "0011010" & "1";
signal dac_buffer : slv27 := x"00" & '1' & x"00" & '1' & x"00" & '1'; --padded for ACKs
signal dac_x_offs : ubyte := x"00";
signal dac_init_line : ubyte := x"00";
signal dac_init_wait : u16 := x"0000";
signal dac_ok : std_logic := '1';
type dacstg_t is (
dac_reset,
dac_i2c_start,
dac_loadbuf,
dac_i2c_send0_c0,
dac_i2c_send1_c0dx,
dac_i2c_send2_c1,
dac_i2c_send3_next,
dac_i2c_stop,
dac_i2c_stop_c1d0,
dac_i2c_stop_c1d1,
dac_idle
);
signal dac_init_stg : dacstg_t := dac_reset;
signal dac_scl_o : std_logic := '1';
signal dac_sda_o : std_logic := '1';
signal dac_scl_i : std_logic;
signal dac_sda_i : std_logic;
begin
dac_scl_i <= scl; -- I2C clock input
dac_sda_i <= sda; -- I2C data input (used to sense ACK by testing for dac_sda_i='0' when dac_sda_o='1')
with dac_scl_o select scl <=
'0' when '0', -- pull down to send '0'
'Z' when others; -- bus is pulled up so '1' is sent by breaking the connection (high-Z)
with dac_sda_o select sda <=
'0' when '0', -- pull down to send '0'
'Z' when others; -- bus is pulled up so '1' is sent by breaking the connection (high-Z)
init_line <= dac_init_line;
error <= not dac_ok;
i2c: process(clk1M,res0,dac_buffer,dac_x_offs, init_data, dac_sda_i,
dac_buffer, dac_init_line, dac_init_wait,dac_init_stg) is
variable cur_data : slv20;
variable nack : std_logic;
begin
cur_data := init_data;
nack := dac_sda_i;
if (res0 = '0') then
dac_init_stg <= dac_reset;
elsif (rising_edge(clk1M)) then
case dac_init_stg is
when dac_reset =>
dac_ok <= '1';
dac_scl_o <= '1';
dac_sda_o <= '1';
dac_init_line <= x"00";
dac_init_wait <= x"0000";
dac_init_stg <= dac_loadbuf;
when dac_loadbuf =>
dac_x_offs <= x"1a"; -- position in sequence
dac_buffer <= dac_addr_w & '1' & -- buffer the sequence (ACK bits are constant '1')
cur_data(18 downto 12) & cur_data(8) & '1' &
cur_data(7 downto 0) & '1';
if (cur_data(19 downto 12)=x"09" and dac_init_wait<x"ffff") then
-- since the VMID delay is precondition to setting reg 09
-- the delay is performed when the current initialization
-- data indicate setting of reg 09
dac_init_wait <= dac_init_wait + 1;
elsif (cur_data = x"fffff") then
-- init data of 0xfffff is end sentinel
dac_init_stg <= dac_idle;
else
dac_init_stg <= dac_i2c_start;
end if;
when dac_i2c_start =>
dac_sda_o <= '0';
dac_init_stg <= dac_i2c_send0_c0;
when dac_i2c_send0_c0 =>
dac_scl_o <= '0';
dac_init_stg <= dac_i2c_send1_c0dx;
when dac_i2c_send1_c0dx =>
dac_sda_o <= dac_buffer(to_integer(dac_x_offs));
dac_init_stg <= dac_i2c_send2_c1;
when dac_i2c_send2_c1 =>
dac_scl_o <= '1';
dac_init_stg <= dac_i2c_send3_next;
when dac_i2c_send3_next =>
if ((dac_x_offs=x"00" or dac_x_offs=x"09" or dac_x_offs=x"12") and nack='1') then
dac_ok <= '0';
dac_init_stg <= dac_i2c_stop;
elsif (dac_x_offs = x"00") then
dac_init_stg <= dac_i2c_stop;
else
dac_x_offs <= dac_x_offs - 1;
dac_init_stg <= dac_i2c_send0_c0;
end if;
when dac_i2c_stop =>
dac_scl_o <= '0';
dac_sda_o <= '0';
dac_init_stg <= dac_i2c_stop_c1d0;
when dac_i2c_stop_c1d0 =>
dac_scl_o <= '1';
dac_init_stg <= dac_i2c_stop_c1d1;
when dac_i2c_stop_c1d1 =>
dac_sda_o <= '1';
if (dac_ok = '0') then
dac_init_stg <= dac_idle;
else
dac_init_line <= dac_init_line + 1;
dac_init_stg <= dac_loadbuf;
end if;
when others =>
null;
end case;
end if;
end process i2c;
end i2c_init_guts;
| gpl-3.0 | 856dfc2bb178ad6a972686f5c7197926 | 0.474167 | 3.313087 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/EthCore.vhd | 1 | 16,970 | -------------------------------------------------------------------------------
-- Title : Ethernet Interface
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : EthCore.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description:
-- Ethernet interface
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity EthCore is
generic (
NUM_IP_G : integer := 1;
MTU_SIZE_G : integer := 1500;
LITTLE_ENDIAN_G : boolean := true;
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz clock and reset
ethClk : in sl;
ethRst : in sl;
-- Addressing
macAddr : in MacAddrType := MAC_ADDR_DEFAULT_C;
ipAddrs : in IpAddrArray(NUM_IP_G-1 downto 0) := (others => IP_ADDR_DEFAULT_C);
udpPorts : in Word16Array(NUM_IP_G-1 downto 0) := (others => (others => '0'));
-- Connection to physical interface (GT or otherwise)
macTxData : out EthMacDataType;
macRxData : in EthMacDataType;
-- User clock and reset
userClk : in sl;
userRst : in sl;
-- Connection to user logic
userTxData : in Word32Array(NUM_IP_G-1 downto 0);
userTxDataValid : in slv(NUM_IP_G-1 downto 0);
userTxDataLast : in slv(NUM_IP_G-1 downto 0);
userTxDataReady : out slv(NUM_IP_G-1 downto 0);
userRxData : out Word32Array(NUM_IP_G-1 downto 0);
userRxDataValid : out slv(NUM_IP_G-1 downto 0);
userRxDataLast : out slv(NUM_IP_G-1 downto 0);
userRxDataReady : in slv(NUM_IP_G-1 downto 0)
);
end EthCore;
architecture Behavioral of EthCore is
-- Signals for ARP interfacing
signal arpTxSenderMac : MacAddrType;
signal arpTxSenderIp : IpAddrType;
signal arpTxTargetMac : MacAddrType;
signal arpTxTargetIp : IpAddrType;
signal arpTxOp : slv(15 downto 0);
signal arpTxReq : sl;
signal arpTxAck : sl;
signal arpRxOp : slv(15 downto 0);
signal arpRxSenderMac : MacAddrType;
signal arpRxSenderIp : IpAddrType;
signal arpRxTargetMac : MacAddrType;
signal arpRxTargetIp : IpAddrType;
signal arpRxValid : sl;
-- TX interfaces
signal multIpTxData : Word8Array(NUM_IP_G-1 downto 0);
signal multIpTxDataValid : slv(NUM_IP_G-1 downto 0);
signal multIpTxDataLastByte : slv(NUM_IP_G-1 downto 0);
signal multIpTxDataReady : slv(NUM_IP_G-1 downto 0);
signal ipTxData : Word32Array(NUM_IP_G-1 downto 0);
signal ipTxDataValid : slv(NUM_IP_G-1 downto 0);
signal ipTxDataReady : slv(NUM_IP_G-1 downto 0);
signal muxIpTxData : slv(7 downto 0);
signal muxIpTxDataValid : sl;
signal muxIpTxDataLastByte : sl;
signal muxIpTxDataReady : sl;
signal ipPacketLength : Word16Array(NUM_IP_G-1 downto 0);
signal ipPacketId : Word16Array(NUM_IP_G-1 downto 0);
signal ipMoreFragments : slv(NUM_IP_G-1 downto 0);
signal ipFragOffset : Word13Array(NUM_IP_G-1 downto 0);
signal ipProtocol : Word8Array(NUM_IP_G-1 downto 0);
signal ipSrcAddr : IpAddrArray(NUM_IP_G-1 downto 0);
signal ipDstAddr : IpAddrArray(NUM_IP_G-1 downto 0);
signal udpTxData : Word32Array(NUM_IP_G-1 downto 0);
signal udpTxDataValid : slv(NUM_IP_G-1 downto 0);
signal udpTxDataReady : slv(NUM_IP_G-1 downto 0);
signal udpTxLength : Word16Array(NUM_IP_G-1 downto 0);
signal udpTxReq : slv(NUM_IP_G-1 downto 0);
signal udpTxAck : slv(NUM_IP_G-1 downto 0);
-- RX interfaces
signal ethRxData : slv(7 downto 0);
signal ethRxDataValid : sl;
signal ethRxDataLast : sl;
signal ethRxSenderMac : MacAddrType;
signal ipRxLength : slv(15 downto 0);
signal ipRxId : slv(15 downto 0);
signal ipRxMoreFragments : sl;
signal ipRxFragOffset : slv(12 downto 0);
signal ipRxTtl : slv( 7 downto 0);
signal ipRxProtocol : slv( 7 downto 0);
signal ipRxSrcAddr : IpAddrType;
signal ipRxDstAddr : IpAddrType;
signal ipRxData : slv(31 downto 0);
signal ipRxDataValid : sl;
signal ipRxDataLast : sl;
signal udpRxSrcPort : Word16Array(NUM_IP_G-1 downto 0);
signal udpRxDstPort : Word16Array(NUM_IP_G-1 downto 0);
signal udpRxLength : Word16Array(NUM_IP_G-1 downto 0);
signal udpRxChecksum : Word16Array(NUM_IP_G-1 downto 0);
signal udpTxDstPort : Word16Array(NUM_IP_G-1 downto 0);
signal iUserRxDataValid : slv(NUM_IP_G-1 downto 0);
-- For optional endian reversal operations
signal userTxDataByteOrdered : Word32Array(NUM_IP_G-1 downto 0);
signal userRxDataByteOrdered : Word32Array(NUM_IP_G-1 downto 0);
begin
---------------------------------------
-- Communications to top level ports --
---------------------------------------
G_ByteSwizzle : if LITTLE_ENDIAN_G = true generate
G_Swizzle : for i in NUM_IP_G-1 downto 0 generate
userTxDataByteOrdered(i) <= userTxData(i)(7 downto 0) & userTxData(i)(15 downto 8) & userTxData(i)(23 downto 16) & userTxData(i)(31 downto 24);
userRxData(i) <= userRxDataByteOrdered(i)(7 downto 0) & userRxDataByteOrdered(i)(15 downto 8) & userRxDataByteOrdered(i)(23 downto 16) & userRxDataByteOrdered(i)(31 downto 24);
end generate;
end generate;
G_NoByteSwizzle : if LITTLE_ENDIAN_G = false generate
G_NoSwizzle : for i in NUM_IP_G-1 downto 0 generate
userTxDataByteOrdered(i) <= userTxData(i);
userRxData(i) <= userRxDataByteOrdered(i);
end generate;
end generate;
--------------------------
-- Ethernet Frame TX/RX --
--------------------------
U_EthTx : entity work.EthTx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz clock and reset
ethClk => ethClk,
ethRst => ethRst,
-- Addressing
macAddr => macAddr,
-- Connection to GT
macData => macTxData,
-- Connection to upper level ARP
arpTxSenderMac => arpTxSenderMac,
arpTxSenderIp => arpTxSenderIp,
arpTxTargetMac => arpTxTargetMac,
arpTxTargetIp => arpTxTargetIp,
arpTxOp => arpTxOp,
arpTxReq => arpTxReq,
arpTxAck => arpTxAck,
-- Connection to IPv4 interface
ipTxDestMac => ethRxSenderMac,
ipTxData => muxIpTxData,
ipTxDataValid => muxIpTxDataValid,
ipTxDataLastByte => muxIpTxDataLastByte,
ipTxDataReady => muxIpTxDataReady
);
U_EthRx : entity work.EthRx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz clock and reset
ethClk => ethClk,
ethRst => ethRst,
-- Addressing
macAddr => macAddr,
-- Connection to GT
macData => macRxData,
-- Connection to upper level ARP
arpRxOp => arpRxOp,
arpRxSenderMac => arpRxSenderMac,
arpRxSenderIp => arpRxSenderIp,
arpRxTargetMac => arpRxTargetMac,
arpRxTargetIp => arpRxTargetIp,
arpRxValid => arpRxValid,
-- Connection to upper level IP interface
ethRxData => ethRxData,
ethRxSenderMac => ethRxSenderMac,
ethRxDataValid => ethRxDataValid,
ethRxDataLastByte => ethRxDataLast
);
----------------------------
-- Higher level protocols --
----------------------------
-- ARP : respond to ARP requests based on our IPs
U_ArpResponder : entity work.ArpResponder
generic map (
NUM_IP_G => NUM_IP_G,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethClk => ethClk,
ethRst => ethRst,
-- Local MAC/IP settings
macAddress => macAddr,
ipAddresses => ipAddrs,
-- Connection to ARP RX
arpRxOp => arpRxOp,
arpRxSenderMac => arpRxSenderMac,
arpRxSenderIp => arpRxSenderIp,
arpRxTargetMac => arpRxTargetMac,
arpRxTargetIp => arpRxTargetIp,
arpRxValid => arpRxValid,
-- Connection to ARP TX
arpTxSenderMac => arpTxSenderMac,
arpTxSenderIp => arpTxSenderIp,
arpTxTargetMac => arpTxTargetMac,
arpTxTargetIp => arpTxTargetIp,
arpTxOp => arpTxOp,
arpTxReq => arpTxReq,
arpTxAck => arpTxAck
);
-- IPv4 TX arbitration
U_IPv4Arbiter : entity work.IpV4Arbiter
generic map (
GATE_DELAY_G => GATE_DELAY_G,
NUM_IP_G => NUM_IP_G
)
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- Multiple data inputs
multIpTxDataIn => multIpTxData,
multIpTxDataValid => multIpTxDataValid,
multIpTxDataLastByte => multIpTxDataLastByte,
multIpTxDataReady => multIpTxDataReady,
-- MUXed data out
ipTxData => muxIpTxData,
ipTxDataValid => muxIpTxDataValid,
ipTxDataLastByte => muxIpTxDataLastByte,
ipTxDataReady => muxIpTxDataReady
);
-- TX modules for each IP address
G_UdpTxInstance : for i in NUM_IP_G - 1 downto 0 generate
-- IPv4 TX packet transmission
U_IPv4Tx : entity work.IPv4Tx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- Header data
ipPacketLength => ipPacketLength(i),
ipPacketId => ipPacketId(i),
ipMoreFragments => ipMoreFragments(i),
ipFragOffset => ipFragOffset(i),
ipProtocol => ipProtocol(i),
ipSrcAddr => ipAddrs(i),
ipDstAddr => ipRxSrcAddr,
-- User data to be sent
ipData => ipTxData(i),
ipDataValid => ipTxDataValid(i),
ipDataReady => ipTxDataReady(i),
-- Interface to Ethernet frame block
ethTxDataIn => multIpTxData(i),
ethTxDataValid => multIpTxDataValid(i),
ethTxDataLastByte => multIpTxDataLastByte(i),
ethTxDataReady => multIpTxDataReady(i)
);
-- UDP fragmenter to break UDP packets into MTU size chunks
U_UdpTxFragmenter : entity work.UdpTxFragmenter
generic map (
GATE_DELAY_G => GATE_DELAY_G,
MTU_SIZE_G => MTU_SIZE_G,
ID_OFFSET_G => conv_std_logic_vector(i*8192,16)
)
port map (
-- 125 MHz ethernet clock in
ethTxClk => ethClk,
ethTxRst => ethRst,
-- Header data
ipPacketLength => ipPacketLength(i),
ipPacketId => ipPacketId(i),
ipMoreFragments => ipMoreFragments(i),
ipFragOffset => ipFragOffset(i),
ipProtocol => ipProtocol(i),
-- User data to be sent
udpData => udpTxData(i),
udpDataValid => udpTxDataValid(i),
udpDataReady => udpTxDataReady(i),
udpLength => udpTxLength(i),
udpReq => udpTxReq(i),
udpAck => udpTxAck(i),
-- Interface to IPv4 frame block
ipData => ipTxData(i),
ipDataValid => ipTxDataValid(i),
ipDataReady => ipTxDataReady(i)
);
-- UDP TX buffer
U_UdpBufferTx : entity work.UdpBufferTx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- User clock and reset (for writes to FIFO)
userClk => userClk,
userRst => userRst,
-- 125 MHz clock and reset (for reads from FIFO, interface to Eth blocks)
ethTxClk => ethClk,
ethTxRst => ethRst,
-- User data interfaces
userData => userTxDataByteOrdered(i),
userDataValid => userTxDataValid(i),
userDataLast => userTxDataLast(i),
userDataReady => userTxDataReady(i),
-- UDP settings
udpSrcPort => udpPorts(i),
udpDstPort => udpTxDstPort(i),
-- Inputs for calculating checksums
ipSrcAddr => ipAddrs(i),
ipDstAddr => ipRxSrcAddr,
-- UDP fragmenter interfaces
udpData => udpTxData(i),
udpDataValid => udpTxDataValid(i),
udpDataReady => udpTxDataReady(i),
udpLength => udpTxLength(i),
udpReq => udpTxReq(i),
udpAck => udpTxAck(i)
);
end generate;
-- IPv4 RX receiver
U_IPv4Rx : entity work.IPv4Rx
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethRxClk => ethClk,
ethRxRst => ethRst,
-- Incoming data from Ethernet frame
ethRxData => ethRxData,
ethRxDataValid => ethRxDataValid,
ethRxDataLast => ethRxDataLast,
-- Data from the IPv4 header
ipLength => ipRxLength,
ipId => ipRxId,
ipMoreFragments => ipRxMoreFragments,
ipFragOffset => ipRxFragOffset,
ipTtl => ipRxTtl,
ipProtocol => ipRxProtocol,
ipSrcAddr => ipRxSrcAddr,
ipDstAddr => ipRxDstAddr,
-- Actual data from the payload
ipData => ipRxData,
ipDataValid => ipRxDataValid,
ipDataLast => ipRxDataLast
);
-- IPv4 RX demuxer
G_Rx : for i in NUM_IP_G-1 downto 0 generate
U_UdpBufferRx : entity work.UdpBufferRx
generic map (
NUM_IP_G => NUM_IP_G,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
-- 125 MHz ethernet clock in
ethRxClk => ethClk,
ethRxRst => ethRst,
-- Settings for this receiver
ipAddr => ipAddrs(i),
udpPort => udpPorts(i),
-- Data from the IPv4 header
ipLength => ipRxLength,
ipId => ipRxId,
ipMoreFragments => ipRxMoreFragments,
ipFragOffset => ipRxFragOffset,
ipTtl => ipRxTtl,
ipProtocol => ipRxProtocol,
ipSrcAddr => ipRxSrcAddr,
ipDstAddr => ipRxDstAddr,
-- Actual data from the payload
ipData => ipRxData,
ipDataValid => ipRxDataValid,
ipDataLast => ipRxDataLast,
-- UDP outputs
udpSrcPort => udpRxSrcPort(i),
udpDstPort => udpRxDstPort(i),
udpLength => udpRxLength(i),
udpChecksum => udpRxChecksum(i),
-- UDP payload data interface
userRxClk => userClk,
userRxData => userRxDataByteOrdered(i),
userRxDataValid => iUserRxDataValid(i),
userRxDataLast => userRxDataLast(i),
userRxDataReady => userRxDataReady(i)
);
userRxDataValid(i) <= iUserRxDataValid(i);
end generate;
-- If you last heard from port X, respond to it
process(ethClk) begin
if rising_edge(ethClk) then
if ethRst = '1' then
for i in NUM_IP_G-1 downto 0 loop
udpTxDstPort(i) <= udpPorts(i);
end loop;
else
for i in NUM_IP_G-1 downto 0 loop
if udpRxSrcPort(i) /= udpTxDstPort(i) and iUserRxDataValid(i) = '1' then
udpTxDstPort(i) <= udpRxSrcPort(i);
end if;
end loop;
end if;
end if;
end process;
end Behavioral;
| lgpl-2.1 | 1aa7886fd91acd0c8cbf3678a308fd6c | 0.529523 | 4.792432 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/IPv4Tx.vhd | 1 | 11,417 | ---------------------------------------------------------------------------------
-- Title : ARP Packet TX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : IPv4Tx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to Ethernet layer, sends IPv4 packets
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity IPv4Tx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl := '0';
-- Header data
ipPacketLength : in slv(15 downto 0);
ipPacketId : in slv(15 downto 0);
ipMoreFragments : in sl;
ipFragOffset : in slv(12 downto 0);
ipProtocol : in slv( 7 downto 0);
ipSrcAddr : in IpAddrType;
ipDstAddr : in IpAddrType;
-- User data to be sent
ipData : in slv(31 downto 0);
ipDataValid : in sl;
ipDataReady : out sl;
-- Interface to Ethernet frame block
ethTxDataIn : out slv(7 downto 0);
ethTxDataValid : out sl;
ethTxDataLastByte : out sl;
ethTxDataReady : in sl
);
end IPv4Tx;
architecture rtl of IPv4Tx is
type StateType is (IDLE_S, HEADER_PREP_0_S, HEADER_PREP_1_S,
HEADER_PREP_2_S, HEADER_PREP_3_S,
HEADER_0_S, HEADER_1_S, HEADER_2_S, HEADER_3_S, HEADER_4_S,
PAYLOAD_S, PAUSE_S);
type RegType is record
state : StateType;
byteCount : slv( 1 downto 0);
header0 : slv(31 downto 0);
header1 : slv(31 downto 0);
header2 : slv(31 downto 0);
header3 : slv(31 downto 0);
header4 : slv(31 downto 0);
header0Checksum : slv(31 downto 0);
header1Checksum : slv(31 downto 0);
header2Checksum : slv(31 downto 0);
header3Checksum : slv(31 downto 0);
header4Checksum : slv(31 downto 0);
ipCheckSum32 : slv(31 downto 0);
ipCheckSum16 : slv(15 downto 0);
wordsLeft : slv(13 downto 0);
data32 : slv(31 downto 0);
data8 : slv( 7 downto 0);
data8Valid : sl;
data8Last : sl;
ethTxDataIn : slv(7 downto 0);
ethTxDataValid : sl;
ethTxDataLast : sl;
ipDataReady : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
byteCount => (others => '1'),
header0 => (others => '0'),
header1 => (others => '0'),
header2 => (others => '0'),
header3 => (others => '0'),
header4 => (others => '0'),
header0Checksum => (others => '0'),
header1Checksum => (others => '0'),
header2Checksum => (others => '0'),
header3Checksum => (others => '0'),
header4Checksum => (others => '0'),
ipCheckSum32 => (others => '0'),
ipChecksum16 => (others => '0'),
wordsLeft => (others => '0'),
data32 => (others => '0'),
data8 => (others => '0'),
data8Valid => '0',
data8Last => '0',
ethTxDataIn => (others => '0'),
ethTxDataValid => '0',
ethTxDataLast => '0',
ipDataReady => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
----------------------------------
-- State machine to prep packet --
----------------------------------
comb : process(r,ethTxRst,ipPacketLength,ipPacketId,ipMoreFragments,
ipFragOffset,ipProtocol,ipSrcAddr,ipDstAddr,
ipData,ipDataValid,ethTxDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
v.data8Valid := '0';
v.data8Last := '0';
v.ipDataReady := '0';
-- State machine
case(r.state) is
when IDLE_S =>
v.byteCount := (others => '1');
if ipDataValid = '1' then
-- Prepare header words
v.header0 := IPV4_VERSION_C & IPV4_IHL_C & IPV4_DSCP_C & IPV4_ECN_C & ipPacketLength;
v.header1 := ipPacketId & "00" & ipMoreFragments & ipFragOffset;
v.header2 := IPV4_TTL_C & ipProtocol & x"0000"; --Placeholder for checksum
v.header3 := ipSrcAddr(3) & ipSrcAddr(2) & ipSrcAddr(1) & ipSrcAddr(0);
v.header4 := ipDstAddr(3) & ipDstAddr(2) & ipDstAddr(1) & ipDstAddr(0);
-- Prepare initial checksum stages
v.header0Checksum := conv_std_logic_vector(conv_integer(v.header0(31 downto 16)) + conv_integer(v.header0(15 downto 0)),32);
v.header1Checksum := conv_std_logic_vector(conv_integer(v.header1(31 downto 16)) + conv_integer(v.header1(15 downto 0)),32);
v.header2Checksum := conv_std_logic_vector(conv_integer(v.header2(31 downto 16)) + conv_integer(v.header2(15 downto 0)),32);
v.header3Checksum := conv_std_logic_vector(conv_integer(v.header3(31 downto 16)) + conv_integer(v.header3(15 downto 0)),32);
v.header4Checksum := conv_std_logic_vector(conv_integer(v.header4(31 downto 16)) + conv_integer(v.header4(15 downto 0)),32);
-- Prep number of total payload words to read, not including header
v.wordsLeft := ipPacketLength(15 downto 2) - 5 - 1;
-- Move to next state
v.state := HEADER_PREP_0_S;
end if;
when HEADER_PREP_0_S =>
-- Partial addition of checksum
v.ipChecksum32 := r.header0Checksum + r.header1Checksum + r.header2Checksum;
v.state := HEADER_PREP_1_S;
-- Also go ahead and grab first word here and allow upstream block to clock to next word
v.data32 := ipData;
v.ipDataReady := '1';
when HEADER_PREP_1_S =>
-- Remaining addition of checksum
v.ipChecksum32 := r.ipChecksum32 + r.header3Checksum + r.header4Checksum;
v.state := HEADER_PREP_2_S;
when HEADER_PREP_2_S =>
-- Switch checksum to 16 bit version
v.ipChecksum16 := conv_std_logic_vector(conv_integer(r.ipChecksum32(15 downto 0)) + conv_integer(r.ipChecksum32(31 downto 16)),16);
v.state := HEADER_PREP_3_S;
when HEADER_PREP_3_S =>
-- Bit flip of the checksum and place it into header
v.header2(15 downto 0) := not(r.ipChecksum16);
-- Move into actual data
v.data8 := getByte(conv_integer(r.byteCount),r.header0);
v.data8Valid := '1';
v.state := HEADER_0_S;
when HEADER_0_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header0);
if v.byteCount = 0 then
v.state := HEADER_1_S;
end if;
end if;
when HEADER_1_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header1);
if v.byteCount = 0 then
v.state := HEADER_2_S;
end if;
end if;
when HEADER_2_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header2);
if v.byteCount = 0 then
v.state := HEADER_3_S;
end if;
end if;
when HEADER_3_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header3);
if v.byteCount = 0 then
v.state := HEADER_4_S;
end if;
end if;
when HEADER_4_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.header4);
if v.byteCount = 0 then
v.state := PAYLOAD_S;
end if;
end if;
when PAYLOAD_S =>
v.data8Valid := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.byteCount := r.byteCount - 1;
v.data8 := getByte(conv_integer(v.byteCount),r.data32);
if r.byteCount = 1 and r.wordsLeft /= 0 then
v.ipDataReady := '1';
end if;
if v.byteCount = 0 then
v.data32 := ipData;
if r.wordsLeft = 0 then
v.data8Last := '1';
v.state := PAUSE_S;
else
v.wordsLeft := r.wordsLeft - 1;
end if;
end if;
end if;
when PAUSE_S =>
v.data8Valid := '1';
v.data8Last := '1';
if ethTxDataReady = '1' and r.data8Valid = '1' then
v.data8Valid := '0';
v.data8Last := '0';
v.state := IDLE_S;
end if;
-- -- Hold one extra cycle here to let the transfer finish
-- if r.data8Last = '0' then
-- v.state := IDLE_S;
-- end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
ethTxDataIn <= r.data8;
ethTxDataValid <= r.data8Valid;
ethTxDataLastByte <= r.data8Last;
ipDataReady <= r.ipDataReady;
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | bf411a0d1da2a27830b7882d47e43a4e | 0.480512 | 4.058656 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/testbench/tb_writeback.vhd | 1 | 3,381 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 01/28/2018 03:09:12 PM
-- Module Name: tb_writeback - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity tb_writeback is
-- Port ( );
end tb_writeback;
architecture Behavioral of tb_writeback is
-- component forward declaration
component writeback is
port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
halt: in std_logic; -- Do nothing when high
ready_input: in std_logic; -- Control requests read
ready_output: in std_logic; -- MMU requests write
output_OK: out std_logic; -- Write data and address are valid
input_OK: out std_logic; -- Read data and address recorded
input_data: in doubleword; -- Data from previous stage
input_address: in word; -- MMU Destination for input data
output_data: out doubleword; -- Data to be written to MMU
output_address: out word -- MMU destination for output data
);
end component;
-- Signals and constants
constant t_per: time := 1 ns;
constant w1 : doubleword := (63 downto 32 => '0', others => '1');
constant w2 : doubleword := (63 downto 32 => '0', others => '1');
constant ad : word := "01111111111111111111111111111111";
signal s_clk: std_logic := '0';
signal s_rst: std_logic := '1';
signal s_ra: word := (others => '0');
signal s_wa: word;
signal s_rdata: doubleword := (others => '0');
signal s_wdata: doubleword;
signal s_ack_r: std_logic := '0';
signal s_ack_w: std_logic := '0';
signal s_halt: std_logic := '0';
signal s_read: std_logic := '0';
signal s_write: std_logic := '0';
begin
-- Instantiation
myWB: writeback
port map(
clk => s_clk,
rst => s_rst,
halt => s_halt,
ready_input => s_read,
ready_output => s_write,
output_OK => s_ack_w,
input_OK => s_ack_r,
input_data => s_rdata,
input_address => s_ra,
output_data => s_wdata,
output_address => s_wa
);
-- Clock generation
tiktok: process
begin
s_clk <= '0';
wait for t_per/2;
s_clk <= '1';
wait for t_per/2;
end process;
main: process
begin
-- Settling
wait for t_per/2;
wait for t_per;
s_rst <= '0';
-- Test read and write in isolation
s_read <= '1';
s_ra <= ad;
s_rdata <= w1;
wait for t_per;
s_write <= '1';
s_read <= '0';
wait for t_per;
s_write <= '0';
-- Test simple write and read (RAW test)
s_read <= '1';
s_ra <= ad;
s_rdata <= w1;
s_write <= '0';
wait for t_per; -- allow write to propagate
s_rdata <= w2;
s_write <= '1'; -- attempt simultaneous read and write
wait for t_per;
-- Test reset
s_read <= '0';
s_write <= '0';
s_rst <= '1';
wait for t_per;
-- Test halt
s_rst <= '0';
s_halt <= '1';
s_read <= '1';
s_ra <= ad;
s_rdata <= w1;
wait for t_per;
-- Test resume
s_halt <= '0';
wait for t_per;
wait;
end process;
end Behavioral;
| mit | 2b37d6c54746759df35a84c20b83cf60 | 0.534753 | 3.435976 | false | false | false | false |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/rgb2dvi_v1_2/src/rgb2dvi.vhd | 3 | 7,781 | -------------------------------------------------------------------------------
--
-- File: rgb2dvi.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 source interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure (optional), encoding and serialization logic.
-- On the input side it has 24-bit RGB video data bus, pixel clock and synchronization
-- signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb2dvi is
Generic (
kGenerateSerialClk : boolean := true;
kClkPrimitive : string := "MMCM"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kRstActiveHigh : boolean := true); --true, if active-high; false, if active-low
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : out std_logic;
TMDS_Clk_n : out std_logic;
TMDS_Data_p : out std_logic_vector(2 downto 0);
TMDS_Data_n : out std_logic_vector(2 downto 0);
-- Auxiliary signals
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video in
vid_pData : in std_logic_vector(23 downto 0);
vid_pVDE : in std_logic;
vid_pHSync : in std_logic;
vid_pVSync : in std_logic;
PixelClk : in std_logic; --pixel-clock recovered from the DVI interface
SerialClk : in std_logic); -- 5x PixelClk
end rgb2dvi;
architecture Behavioral of rgb2dvi is
type dataOut_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type dataOutRaw_t is array (2 downto 0) of std_logic_vector(9 downto 0);
signal pDataOut : dataOut_t;
signal pDataOutRaw : dataOutRaw_t;
signal pVde, pC0, pC1 : std_logic_vector(2 downto 0);
signal aRst_int, aPixelClkLckd : std_logic;
signal PixelClkIO, SerialClkIO, aRstLck, pRstLck : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
-- Generate SerialClk internally?
ClockGenInternal: if kGenerateSerialClk generate
ClockGenX: entity work.ClockGen
Generic map (
kClkRange => kClkRange, -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive => kClkPrimitive) -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port map (
PixelClkIn => PixelClk,
PixelClkOut => PixelClkIO,
SerialClk => SerialClkIO,
aRst => aRst_int,
aLocked => aPixelClkLckd);
--TODO revise this
aRstLck <= not aPixelClkLckd;
end generate ClockGenInternal;
ClockGenExternal: if not kGenerateSerialClk generate
PixelClkIO <= PixelClk;
SerialClkIO <= SerialClk;
aRstLck <= aRst_int;
end generate ClockGenExternal;
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRstLck,
OutClk => PixelClk,
oRst => pRstLck);
-- Clock needs no encoding, send a pulse
ClockSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Clk_p,
sDataOut_n => TMDS_Clk_n,
--Encoded parallel data (raw)
pDataOut => "1111100000",
aRst => pRstLck);
DataEncoders: for i in 0 to 2 generate
DataEncoder: entity work.TMDS_Encoder
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
pDataOutRaw => pDataOutRaw(i),
aRst => pRstLck,
pDataOut => pDataOut(i),
pC0 => pC0(i),
pC1 => pC1(i),
pVde => pVde(i)
);
DataSerializer: entity work.OutputSERDES
generic map (
kParallelWidth => 10) -- TMDS uses 1:10 serialization
port map(
PixelClk => PixelClkIO,
SerialClk => SerialClkIO,
sDataOut_p => TMDS_Data_p(i),
sDataOut_n => TMDS_Data_n(i),
--Encoded parallel data (raw)
pDataOut => pDataOutRaw(i),
aRst => pRstLck);
end generate DataEncoders;
-- DVI Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason vid_data is packed in RBG order
pDataOut(2) <= vid_pData(23 downto 16); -- red is channel 2
pDataOut(0) <= vid_pData(7 downto 0); -- green is channel 1
pDataOut(1) <= vid_pData(15 downto 8); -- blue is channel 0
pC0(2 downto 1) <= (others => '0'); -- default is low for control signals
pC1(2 downto 1) <= (others => '0'); -- default is low for control signals
pC0(0) <= vid_pHSync; -- channel 0 carries control signals too
pC1(0) <= vid_pVSync; -- channel 0 carries control signals too
pVde <= vid_pVDE & vid_pVDE & vid_pVDE; -- all of them are either active or blanking at once
end Behavioral;
| bsd-3-clause | df48194989b7e25bf1477feed288849c | 0.662126 | 4.373806 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/controllers/controller.vhd | 1 | 2,620 | library ieee;
use ieee.std_logic_1164.all;
package controller is
component pc is
generic
(
res_x : integer := 15;
res_y : integer := 15;
aux_y : integer := 0;
aux_x : integer := 0;
pos_y : integer := 5;
clock_div : integer := 2
);
port
(
reset_i, enable_i : in std_logic;
right_flag_i : in std_logic;
clock_i : in std_logic;
clock_o : out std_logic;
position_x_o : buffer integer range 0 to res_x;
position_y_o : out integer range 0 to res_y
);
end component;
component cpu is
generic
(
res_x : integer := 15;
res_y : integer := 15;
pos_x : integer := 10;
pos_y : integer := 10;
aux_x : integer := 0;
aux_y : integer := 0;
clock_div : integer := 4
);
port
(
reset_i, kill_i : in std_logic;
clock_i,turn_i : in std_logic;
-- position of player's ship
turn_o : out std_logic;
enable_o : out std_logic;
position_x_o : out integer range 0 to res_x;
position_y_o : out integer range 0 to res_y;
dying : out std_logic;
game_over : out std_logic
);
end component;
component shot is
generic
(
res_x : integer := 15;
res_y : integer := 15;
aux_y : integer := 0;
aux_x : integer := 0;
flag_up : std_logic := '1';
clock_div : integer := 2
);
port
(
clock_i,
reset_i,
trigger_i : std_logic;
position_x_i : in integer range 0 to res_x;
position_y_i : in integer range 0 to res_y;
enable_o : buffer std_logic;
position_x_o : buffer integer range 0 to res_x;
position_y_ox : buffer integer range 0 to res_y
);
end component;
component collisor is
generic
(
res_x : integer := 15;
res_y : integer := 15;
w : integer := 2;
h : integer := 2;
clock_div : integer := 100
);
port
(
clock: in std_logic;
enable_i: in std_logic;
position_x1,
position_x2: in integer range 0 to res_x;
position_y1,
position_y2: in integer range 0 to res_y;
collision_o: out std_logic
);
end component;
component score is
port
(
clock_i,reset_i: in std_logic;
score_o: out std_logic_vector(27 downto 0)
);
end component;
end package;
| mit | 69a68927ada523f8d3bdba76ccb536ed | 0.484733 | 3.484043 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/remote_sources/_/lib/digilent/VideoTimingCtl.vhd | 1 | 6,772 | ----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:35:21 02/23/2009
-- Design Name:
-- Module Name: VideoTimingCtl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: VideoTimingCtl generates the proper synchronization signals
-- according to the selected resolution.
--
-- Dependencies: digilent.Video
--
-- Revision:
-- Revision 0.03 - Moved the Active Video area to the first part of the counter
-- Revision 0.02 - Added resolution 480x272 progressive
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library digilent;
use digilent.Video.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VideoTimingCtl is
Port (
PCLK_I : in STD_LOGIC; --variable depending on RSEL_I
RST_I : in STD_LOGIC; --reset
RSEL_I : in RESOLUTION;
VDE_O : out STD_LOGIC; --data enable for pixel bus
HS_O : out STD_LOGIC;
VS_O : out STD_LOGIC;
HCNT_O : out NATURAL;
VCNT_O : out NATURAL);
end VideoTimingCtl;
architecture Behavioral of VideoTimingCtl is
----------------------------------------------------------------------------------
-- VGA Timing Signals
----------------------------------------------------------------------------------
signal HCnt : NATURAL range 0 to H_MAX := 0; --horizontal counter
signal VCnt : NATURAL range 0 to V_MAX := 0; --vertical counter
signal H_AV, V_AV, H_AV_FP, V_AV_FP, H_AV_FP_S, V_AV_FP_S, H_AV_FP_S_BP, V_AV_FP_S_BP : NATURAL;
signal hs, vs: std_logic; -- horizontal/vertical sync
signal vde : std_logic; -- data enable
signal SRst : std_logic;
signal H_POL, V_POL : BOOLEAN;
begin
----------------------------------------------------------------------------------
-- Resolution Selector
----------------------------------------------------------------------------------
with RSEL_I select
H_AV <= H_640_480p_AV when R640_480P,
H_720_480p_AV when R720_480P,
H_480_272p_AV when R480_272P,
H_1280_720p_AV when R1280_720P,
H_1600_900p_AV when R1600_900P,
H_800_600p_AV when R800_600P,
H_640_480p_AV when others;
with RSEL_I select
V_AV <= V_640_480p_AV when R640_480P,
V_720_480p_AV when R720_480P,
V_480_272p_AV when R480_272P,
V_1280_720p_AV when R1280_720P,
V_1600_900p_AV when R1600_900P,
V_800_600p_AV when R800_600P,
V_640_480p_AV when others;
with RSEL_I select
H_AV_FP <= H_640_480p_AV_FP when R640_480P,
H_720_480p_AV_FP when R720_480P,
H_480_272p_AV_FP when R480_272P,
H_1280_720p_AV_FP when R1280_720P,
H_1600_900p_AV_FP when R1600_900P,
H_800_600p_AV_FP when R800_600P,
H_640_480p_AV_FP when others;
with RSEL_I select
V_AV_FP <= V_640_480p_AV_FP when R640_480P,
V_720_480p_AV_FP when R720_480P,
V_480_272p_AV_FP when R480_272P,
V_1280_720p_AV_FP when R1280_720P,
V_1600_900p_AV_FP when R1600_900P,
V_800_600p_AV_FP when R800_600P,
V_640_480p_AV_FP when others;
with RSEL_I select
H_AV_FP_S <= H_640_480p_AV_FP_S when R640_480P,
H_720_480p_AV_FP_S when R720_480P,
H_480_272p_AV_FP_S when R480_272P,
H_1280_720p_AV_FP_S when R1280_720P,
H_1600_900p_AV_FP_S when R1600_900P,
H_800_600p_AV_FP_S when R800_600P,
H_640_480p_AV_FP_S when others;
with RSEL_I select
V_AV_FP_S <= V_640_480p_AV_FP_S when R640_480P,
V_720_480p_AV_FP_S when R720_480P,
V_480_272p_AV_FP_S when R480_272P,
V_1280_720p_AV_FP_S when R1280_720P,
V_1600_900p_AV_FP_S when R1600_900P,
V_800_600p_AV_FP_S when R800_600P,
V_640_480p_AV_FP_S when others;
with RSEL_I select
H_AV_FP_S_BP <= H_640_480p_AV_FP_S_BP when R640_480P,
H_720_480p_AV_FP_S_BP when R720_480P,
H_480_272p_AV_FP_S_BP when R480_272P,
H_1280_720p_AV_FP_S_BP when R1280_720P,
H_1600_900p_AV_FP_S_BP when R1600_900P,
H_800_600p_AV_FP_S_BP when R800_600P,
H_640_480p_AV_FP_S_BP when others;
with RSEL_I select
V_AV_FP_S_BP <= V_640_480p_AV_FP_S_BP when R640_480P,
V_720_480p_AV_FP_S_BP when R720_480P,
V_480_272p_AV_FP_S_BP when R480_272P,
V_1280_720p_AV_FP_S_BP when R1280_720P,
V_1600_900p_AV_FP_S_BP when R1600_900P,
V_800_600p_AV_FP_S_BP when R800_600P,
V_640_480p_AV_FP_S_BP when others;
with RSEL_I select
H_POL <= H_640_480p_POL when R640_480P,
H_720_480p_POL when R720_480P,
H_480_272p_POL when R480_272P,
H_1280_720p_POL when R1280_720P,
H_1600_900p_POL when R1600_900P,
H_800_600p_POL when R800_600P,
H_640_480p_POL when others;
with RSEL_I select
V_POL <= V_640_480p_POL when R640_480P,
V_720_480p_POL when R720_480P,
V_480_272p_POL when R480_272P,
V_1280_720p_POL when R1280_720P,
V_1600_900p_POL when R1600_900P,
V_800_600p_POL when R800_600P,
V_640_480p_POL when others;
----------------------------------------------------------------------------------
-- Local Reset
----------------------------------------------------------------------------------
Inst_LocalRst: entity digilent.LocalRst PORT MAP(
RST_I => RST_I,
CLK_I => PCLK_I,
SRST_O => SRst
);
----------------------------------------------------------------------------------
-- Video Timing Counter
----------------------------------------------------------------------------------
process (PCLK_I)
begin
if Rising_Edge(PCLK_I) then
if (SRst = '1') then
HCnt <= H_AV_FP_S_BP - 1; -- 0 is an active pixel
VCnt <= V_AV_FP_S_BP - 1;
vde <= '0';
hs <= '1';
vs <= '1';
else
--pixel/line counters and video data enable
if (HCnt = H_AV_FP_S_BP - 1) then
HCnt <= 0;
if (VCnt = V_AV_FP_S_BP - 1) then
VCnt <= 0;
else
VCnt <= VCnt + 1;
end if;
else
HCnt <= HCnt + 1;
end if;
--sync pulse in sync phase
if (HCnt >= H_AV_FP-1) and (HCnt < H_AV_FP_S-1) then -- one cycle earlier (registered)
hs <= '0';
if (VCnt >= V_AV_FP) and (VCnt < V_AV_FP_S) then
vs <= '0';
else
vs <= '1';
end if;
else
hs <= '1';
end if;
--video data enable
if ((HCnt = H_AV_FP_S_BP - 1 and (VCnt = V_AV_FP_S_BP - 1 or VCnt < V_AV - 1)) or -- first pixel in frame
(HCnt < H_AV - 1 and VCnt < V_AV)) then
vde <= '1';
else
vde <= '0';
end if;
end if;
end if;
end process;
HCNT_O <= HCnt;
VCNT_O <= VCnt;
HS_O <= not hs when H_POL else
hs;
VS_O <= not vs when V_POL else
vs;
VDE_O <= vde;
end Behavioral;
| gpl-3.0 | a2536db9d0d0589268c5e4b9092d1f55 | 0.554489 | 2.597622 | false | false | false | false |
gau-veldt/InsideTheBox | SideQuest 0001/clocking.vhd | 1 | 1,559 | ----------------------------------------------------------------------------------
--
-- Clocking Example using an MMCM tile in the Zynq
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clocking is port (
led : out std_logic_vector(3 downto 0);
clk_125 : in std_logic
);
end clocking;
architecture clock_impl of clocking is
component clk_wiz_0
port
(-- Clock in ports
-- Clock out ports
clk8M : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic;
clk_in1 : in std_logic
);
end component;
signal clk8M : std_logic;
signal reset : std_logic;
signal locked : std_logic;
subtype u24 is unsigned(23 downto 0);
signal count : u24 := x"000000";
constant count8m : u24 := to_unsigned(4000000,24);
signal slow_clock : std_logic := '0';
begin
clock : clk_wiz_0
port map (
-- Clock out ports
clk8M => clk8M,
-- Status and control signals
reset => reset,
locked => locked,
-- Clock in ports
clk_in1 => clk_125
);
reset <= '0';
divider: process(clk8m) is
variable cur : u24;
begin
if (rising_edge(clk8m)) then
cur := count;
cur := cur + 1;
if (cur >= count8M) then
cur := x"000000";
slow_clock <= not slow_clock;
end if;
count <= cur;
end if;
end process divider;
led(0) <= slow_clock;
end clock_impl;
| gpl-3.0 | 7814002fc73a8bb0aba2ff15055b75c0 | 0.524695 | 3.668235 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/chiptest.vhd | 1 | 59,138 | ----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--
-- C64 ROM includes (NOT INCLUDED)
-- See python scripts for converting ROM images to VHDL files.
-- Import the generated sources into a library called "c64roms"
--
library c64roms;
use c64roms.p_char_rom.all; -- for char_rom(addr[11:0]) return byte[7:0]
use c64roms.p_basic_rom.all; -- for basic_rom(addr[12:0]) return byte[7:0]
use c64roms.p_kernal_rom.all; -- for kernal_rom(addr[12:0]) return byte[7:0]
entity chip_test is
port (
clk_125 : in std_logic;
-- audio configure
ac_scl : inout std_logic;
ac_sda : inout std_logic;
-- audio signal
ac_muten : out std_logic;
ac_mclk : out std_logic;
ac_bclk : out std_logic;
ac_pbdat : out std_logic;
ac_pblrc : out std_logic;
ac_recdat : in std_logic;
ac_reclrc : in std_logic;
-- report error in configuring audio
led : out std_logic_vector(3 downto 0);
-- to test waveforms
sw : in std_logic_vector(3 downto 0);
-- for freq/wvfm ramping tests
btn : in std_logic_vector(3 downto 0);
-- for keyboard
je : inout std_logic_vector(7 downto 0);
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end chip_test;
architecture testing of chip_test is
constant use_init_fsm : boolean := false;
attribute mark_debug : string;
attribute keep : string;
component clk_wiz_0
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk160 : out std_logic;
clk20ph1 : out std_logic;
clk20ph2 : out std_logic;
clk20ph3 : out std_logic;
clk20ph4 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
component clk_wiz_1
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk12 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
signal clk12 : std_logic;
signal clk160 : std_logic;
signal clk_lk1 : std_logic;
signal clk_lk2 : std_logic;
signal clk20p000 : std_logic;
signal clk20p010 : std_logic;
signal clk20p100 : std_logic;
signal clk20p110 : std_logic;
signal clk20_ph1 : std_logic;
signal clk20_ph2 : std_logic;
component blk_ram_64k
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
component blk_cram
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype u4 is unsigned(3 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv5 is std_logic_vector(4 downto 0);
subtype u5 is unsigned(4 downto 0);
subtype u6 is unsigned(5 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype slv7 is std_logic_vector(6 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype slv10 is std_logic_vector(9 downto 0);
subtype slv11 is std_logic_vector(10 downto 0);
subtype u12 is unsigned(11 downto 0);
subtype slv14 is std_logic_vector(13 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype s16 is signed(15 downto 0);
subtype slv17 is std_logic_vector(16 downto 0);
subtype slv20 is std_logic_vector(19 downto 0);
subtype slv24 is std_logic_vector(23 downto 0);
subtype slv27 is std_logic_vector(26 downto 0); -- I2C SSM2603 send with ACK pads
signal res0 : std_logic;
signal res1 : std_logic;
signal c12res1 : std_logic; -- 12 MHz domain reset
signal c12fdr1 : std_logic;
signal cpu_r1w0 : std_logic:='1';
signal cpu_r0w1 : std_logic;
signal cpu_run : std_logic:='0';
signal cpu_rclk : std_logic;
signal cpu_in_cycle : std_logic;
component chip6502 is
port (
a : out std_logic_vector(15 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end component;
signal c6510_pi : byte;
signal c6510_po : byte;
signal c6510_a : word;
signal c6510_sync : std_logic;
signal c6510_rdy : std_logic;
signal c6510_irq0 : std_logic;
signal c6510_nmi0 : std_logic;
signal c6510_so0 : std_logic;
component sid6581 is
port (
res0 : in std_logic;
ph2 : in std_logic;
rga : in std_logic_vector(4 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
s16audio : out signed(15 downto 0)
);
end component;
signal bclk_cnt : pair;
alias bclk_ref : std_logic is bclk_cnt(0);--1
signal audio_frame : u6;
signal hold_srl : word;
function isZero6(tst: u6) return boolean is
begin
case tst is
when "000000" => return true;
when others => return false;
end case;
end;
function adv_frame(frm: u6) return u6 is
begin
case frm is
when "000000" => return "000001";
when "000001" => return "000010";
when "000010" => return "000011";
when "000011" => return "000100";
when "000100" => return "000101";
when "000101" => return "000110";
when "000110" => return "000111";
when "000111" => return "001000";
when "001000" => return "001001";
when "001001" => return "001010";
when "001010" => return "001011";
when "001011" => return "001100";
when "001100" => return "001101";
when "001101" => return "001110";
when "001110" => return "001111";
when "001111" => return "010000";
when "010000" => return "010001";
when "010001" => return "010010";
when "010010" => return "010011";
when "010011" => return "010100";
when "010100" => return "010101";
when "010101" => return "010110";
when "010110" => return "010111";
when "010111" => return "011000";
when "011000" => return "011001";
when "011001" => return "011010";
when "011010" => return "011011";
when "011011" => return "011100";
when "011100" => return "011101";
when "011101" => return "011110";
when "011110" => return "011111";
when "011111" => return "000000"; -- counts from 0 to 31
when "100000" => return "100001";
when "100001" => return "100010";
when "100010" => return "100011";
when "100011" => return "100100";
when "100100" => return "100101";
when "100101" => return "100110";
when "100110" => return "100111";
when "100111" => return "101000";
when "101000" => return "101001";
when "101001" => return "101010";
when "101010" => return "101011";
when "101011" => return "101100";
when "101100" => return "101101";
when "101101" => return "101110";
when "101110" => return "101111";
when "101111" => return "110000";
when "110000" => return "110001";
when "110001" => return "110010";
when "110010" => return "110011";
when "110011" => return "110100";
when "110100" => return "110101";
when "110101" => return "110110";
when "110110" => return "110111";
when "110111" => return "111000";
when "111000" => return "111001";
when "111001" => return "111010";
when "111010" => return "111011";
when "111011" => return "111100";
when "111100" => return "111101";
when "111101" => return "111110";
when "111110" => return "111111";
when "111111" => return "000000";
when others => return "000000";
end case;
end adv_frame;
signal sid1_rga : slv5;
signal sid1_dw : byte;
signal sid1_dr : byte;
signal sid1_out : s16;
signal sid1_r1w0 : std_logic;
component vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end component;
signal bankctl : slv5 := "11111";
alias exrom : std_logic is bankctl(4);
alias game : std_logic is bankctl(3);
alias charen : std_logic is bankctl(2);
alias hiram : std_logic is bankctl(1);
alias loram : std_logic is bankctl(0);
signal abus : word;
signal rama : word;
signal cpudo : byte;
signal cpudi : byte;
signal r1w0 : std_logic;
signal ram_clk : std_logic;
signal ramclk_init : std_logic := '0';
signal ramclk_cpu : std_logic := '0';
signal ramclk_vic : std_logic := '0';
signal ram_r1w0 : std_logic := '1';
signal ram_r0w1 : std_logic;
signal cram_r1w0 : std_logic := '1';
signal cram_r0w1 : std_logic;
signal ramdr : byte;
signal ramdw : byte;
signal ramen : std_logic := '1';
signal cramdr : nybble;
signal cramdw : nybble;
signal cramen : std_logic := '1';
signal vbank : pair := "00";
signal vic_rga : slv6;
signal vic_regw : byte;
signal vic_regr : byte;
signal vic_r1w0 : std_logic := '1';
signal cpu_ph1 : std_logic;
signal cpu_ph2 : std_logic;
signal vmem_clk : std_logic;
signal vic_ca : slv10;
signal vic_cd : nybble;
signal vic_wcd : nybble;
signal vic_va : slv14;
signal vic_vd : byte;
signal vic_wvd : byte;
signal cpu_on : std_logic;
signal vic_on : std_logic;
signal cpu_ph4x : std_logic;
function catoi(src: slv10) return integer is
begin
return to_integer(unsigned(src));
end catoi;
function vatoi(src: word) return integer is
begin
return to_integer(unsigned(src));
end vatoi;
function xtov6(src: byte) return slv6 is
begin
return src(5 downto 0);
end xtov6;
function xtov5(src: byte) return slv5 is
begin
return src(4 downto 0);
end xtov5;
type mbank_t is (
mbk_ram,
mbk_cram,
mbk_lorom,
mbk_hirom,
mbk_xio2,
mbk_xio1,
mbk_cia2,
mbk_cia1,
mbk_cgrom,
mbk_sid,
mbk_vic
);
function init_bank(addr:u16) return mbank_t is
begin
if (addr(15 downto 10) = "110110") then
return mbk_cram;
else
return mbk_ram;
end if;
end init_bank;
signal cur_a_bank : mbank_t;
signal cur_a_wt : std_logic;
function cpu_bank(addr: u16; bsel: slv5) return mbank_t is
variable b3 : slv3;
variable bb0 : std_logic;
variable ce : std_logic;
variable n3 : nybble;
begin
b3 := bsel(2 downto 0);
bb0 := bsel(1) nor bsel(0);
ce := bsel(2);
n3 := nybble(addr(11 downto 8));
if (addr >= x"e000") then
if (bsel(1)='1') then
return mbk_hirom;
else
return mbk_ram;
end if;
elsif (addr >= x"d000" and addr < x"e000") then
if (bb0 = '1') then
return mbk_ram;
else
if (ce = '0') then
return mbk_cgrom;
else
case n3 is
when x"f" =>
return mbk_xio2;
when x"e" =>
return mbk_xio1;
when x"d" =>
return mbk_cia2;
when x"c" =>
return mbk_cia1;
when x"b" =>
return mbk_cram;
when x"a" =>
return mbk_cram;
when x"9" =>
return mbk_cram;
when x"8" =>
return mbk_cram;
when x"7" =>
return mbk_sid;
when x"6" =>
return mbk_sid;
when x"5" =>
return mbk_sid;
when x"4" =>
return mbk_sid;
when x"3" =>
return mbk_vic;
when x"2" =>
return mbk_vic;
when x"1" =>
return mbk_vic;
when x"0" =>
return mbk_vic;
when others =>
return mbk_ram;
end case;
end if;
end if;
elsif (addr >= x"a000" and addr < x"c000") then
if ((bsel(1) and bsel(0)) = '1') then
return mbk_lorom;
else
return mbk_ram;
end if;
else
return mbk_ram;
end if;
end cpu_bank;
function bank_is_writethru(addr:word; bsel:slv5) return std_logic is
begin
case cpu_bank(u16(addr),bsel) is
when mbk_ram => return '1';
when mbk_cram => return '1';
when mbk_lorom => return '1';
when mbk_hirom => return '1';
when others => return '0';
end case;
end bank_is_writethru;
type init_t is (
initram_wait, initram_xfer, initram_idle);
signal init_stg : init_t := initram_wait;
constant init_wait_to : u16 := x"0014";
signal init_counter : u16 := x"0000";
signal init_cnt_less1 : u16 := x"ffff";
signal init_addr : word;
signal init_data : byte;
signal init_r1w0 : std_logic := '1';
signal init_r0w1 : std_logic;
signal rd_init : slv24 := x"000000"; -- output of init ROM
function ram_init(lin: u16) return slv24 is
begin
-- values for init ROM
case lin is
when x"0000" => return x"0400" & x"08";
when x"0001" => return x"0401" & x"05";
when x"0002" => return x"0402" & x"0c";
when x"0003" => return x"0403" & x"0c";
when x"0004" => return x"0404" & x"0f";
when x"0005" => return x"0405" & x"2c";
when x"0006" => return x"0406" & x"20";
when x"0007" => return x"0407" & x"17";
when x"0008" => return x"0408" & x"0f";
when x"0009" => return x"0409" & x"12";
when x"000a" => return x"040a" & x"0c";
when x"000b" => return x"040b" & x"04";
when x"000c" => return x"040c" & x"21";
when x"000d" => return x"040d" & x"20";
when x"000e" => return x"05f2" & x"3a";
when x"000f" => return x"05f3" & x"3a";
when x"0010" => return x"05f4" & x"3a";
when x"0011" => return x"05f5" & x"3a";
when x"0012" => return x"07de" & x"30";
when x"0013" => return x"07df" & x"31";
when x"0014" => return x"07e0" & x"32";
when x"0015" => return x"07e1" & x"33";
when x"0016" => return x"07e2" & x"34";
when x"0017" => return x"07e3" & x"35";
when x"0018" => return x"07e4" & x"36";
when x"0019" => return x"07e5" & x"37";
when x"001a" => return x"07e6" & x"38";
when x"001b" => return x"07e7" & x"39";
when x"001c" => return x"d800" & x"01";
when x"001d" => return x"d801" & x"02";
when x"001e" => return x"d802" & x"03";
when x"001f" => return x"d803" & x"04";
when x"0020" => return x"d804" & x"05";
when x"0021" => return x"d805" & x"07";
when x"0022" => return x"d806" & x"0e";
when x"0023" => return x"d807" & x"08";
when x"0024" => return x"d808" & x"09";
when x"0025" => return x"d809" & x"0a";
when x"0026" => return x"d80a" & x"0b";
when x"0027" => return x"d80b" & x"0c";
when x"0028" => return x"d80c" & x"0d";
when x"0029" => return x"d80d" & x"0e";
when x"002a" => return x"d9f2" & x"01";
when x"002b" => return x"d9f3" & x"01";
when x"002c" => return x"d9f4" & x"01";
when x"002d" => return x"d9f5" & x"01";
when x"002e" => return x"dbde" & x"05";
when x"002f" => return x"dbdf" & x"07";
when x"0030" => return x"dbe0" & x"0d";
when x"0031" => return x"dbe1" & x"09";
when x"0032" => return x"dbe2" & x"08";
when x"0033" => return x"dbe3" & x"0a";
when x"0034" => return x"dbe4" & x"0b";
when x"0035" => return x"dbe5" & x"0c";
when x"0036" => return x"dbe6" & x"0f";
when x"0037" => return x"dbe7" & x"0e";--
when x"0038" => return x"8000" & x"1e";
when x"0039" => return x"8001" & x"80";
when x"003a" => return x"8002" & x"5e";
when x"003b" => return x"8003" & x"fe";
when x"003c" => return x"8004" & x"c3";
when x"003d" => return x"8005" & x"ff";--"c2";
when x"003e" => return x"8006" & x"cd";
when x"003f" => return x"8007" & x"38";
when x"0040" => return x"8008" & x"30";
when x"0041" => return x"8009" & x"81";
when x"0042" => return x"800a" & x"19";
when x"0043" => return x"800b" & x"00";
when x"0044" => return x"800c" & x"08";
when x"0045" => return x"800d" & x"11";
when x"0046" => return x"800e" & x"0f";
when x"0047" => return x"800f" & x"ff";
when x"0048" => return x"8010" & x"9a";
when x"0049" => return x"8011" & x"15";
when x"004a" => return x"8012" & x"00";
when x"004b" => return x"8013" & x"08";
when x"004c" => return x"8014" & x"11";
when x"004d" => return x"8015" & x"0f";
when x"004e" => return x"8016" & x"ff";
when x"004f" => return x"8017" & x"25";
when x"0050" => return x"8018" & x"11";
when x"0051" => return x"8019" & x"00";
when x"0052" => return x"801a" & x"08";
when x"0053" => return x"801b" & x"11";
when x"0054" => return x"801c" & x"0f";
when x"0055" => return x"801d" & x"ff";
when x"0056" => return x"801e" & x"a2"; -- LDX
when x"0057" => return x"801f" & x"15"; -- #$15
when x"0058" => return x"8020" & x"bd"; -- LDA
when x"0059" => return x"8021" & x"08"; --
when x"005a" => return x"8022" & x"80"; -- $8008,X
when x"005b" => return x"8023" & x"9d"; -- STA
when x"005c" => return x"8024" & x"ff"; --
when x"005d" => return x"8025" & x"d3"; -- $D3FF,X
when x"005e" => return x"8026" & x"ca"; -- DEX
when x"005f" => return x"8027" & x"d0"; -- BNE
when x"0060" => return x"8028" & x"f7"; -- $8020
when x"0061" => return x"8029" & x"a9"; -- LDA
when x"0062" => return x"802a" & x"0f"; -- #$0F
when x"0063" => return x"802b" & x"8d"; -- STA
when x"0064" => return x"802c" & x"18"; --
when x"0065" => return x"802d" & x"d4"; -- $D418
when x"0066" => return x"802e" & x"ee"; -- INC
when x"0067" => return x"802f" & x"08"; --
when x"0068" => return x"8030" & x"80"; -- $8008
when x"0069" => return x"8031" & x"4c"; -- JMP
when x"006a" => return x"8032" & x"ef"; --
when x"006b" => return x"8033" & x"fc"; -- $FCEF
when others => return x"0000" & x"00"; -- 0 (and 1) inaccessible on C64
end case;
end ram_init;
constant ram_init_count : u16 := x"006c";
-- for initial settings for vic/sid
signal c_cycle : ubyte := x"00";
--
-- For setting the SSM2603 via I2C
--
function dac_init(lin : ubyte) return slv20 is
begin
case lin is
when x"00" => return x"06" & x"010";
when x"01" => return x"02" & x"075";
when x"02" => return x"03" & x"075";
when x"03" => return x"04" & x"010";
when x"04" => return x"05" & x"000";
when x"05" => return x"07" & x"003";
when x"06" => return x"08" & x"000";
when x"07" => return x"09" & x"001";
when x"08" => return x"06" & x"000";
when others => return x"ff" & x"fff";
end case;
end dac_init;
component i2c_xcvr port
(
-- with 1 MHz clock SSM2603 reg 9 delay step is 65.535 ms:
clk1M : in std_logic;
-- tie to system reset
res0 : in std_logic;
-- initialization line number
init_line : out unsigned(7 downto 0);
-- initialization data xRRRRRRRxxxxxxxDDDDDDDDD
init_data : in std_logic_vector(19 downto 0);
-- error status
error : out std_logic;
-- tie directly to ac_scl and ac_sda accordingly:
scl : inout std_logic;
sda : inout std_logic
);
end component;
signal ssm_init_line : ubyte;
signal ssm_init_data : slv20;
signal ssm_error : std_logic;
-- 3-bit counter for dividing 160 MHz into 8-phase 20 MHz clocks
signal clk20_ph : slv3;
function c20_next(src: slv3) return slv3 is
begin
case src is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end c20_next;
function vbk_cgrom(bk: pair; adr: slv14) return std_logic is
variable vsel : slv3;
begin
vsel := bk(0) & adr(13 downto 12);
case vsel is
when "001" => return '1';
when others => return '0';
end case;
end vbk_cgrom;
signal reset_wait : u12 := x"000";
constant reset_delay : u12 := x"0fb"; -- number of 125 MHz clocks in 2000 ns
signal cgrom_data : byte;
signal lorom_data : byte;
signal hirom_data : byte;
component cia6526 is
port (
PAo : out std_logic_vector(7 downto 0);
PAi : in std_logic_vector(7 downto 0);
PBo : out std_logic_vector(7 downto 0);
PBi : in std_logic_vector(7 downto 0);
irq0 : out std_logic;
rga : in std_logic_vector(3 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
ce : in std_logic;
clk : in std_logic -- 1 MHz
);
end component;
signal cia1EN : std_logic;
signal cia2EN : std_logic;
signal cia1PAi : byte;
signal cia1PAo : byte;
signal cia1PBi : byte;
signal cia1PBo : byte;
signal cia1_irq : std_logic;
signal cia1_rga : nybble;
signal cia1_dr : byte;
signal cia1_dw : byte;
signal cia1_r1w0 : std_logic;
signal cia2PAi : byte;
signal cia2PAo : byte;
signal cia2PBi : byte;
signal cia2PBo : byte;
signal cia2_irq : std_logic;
signal cia2_rga : nybble;
signal cia2_dr : byte;
signal cia2_dw : byte;
signal cia2_r1w0 : std_logic;
signal irq_tie : std_logic;
component ROM_IEC
port (
ATN0 : in std_logic; -- master broadcasting command when low
LCLK0 : in std_logic; -- input clock when listening 0=low=idle 1=bit valid
DATAI0 : in std_logic; -- input data when listening
TCLK0 : out std_logic; -- output clock when talking 0=low=idle 1=bit valid
DATAO0 : out std_logic; -- output data when talking
clk : in std_logic -- system clock (use PH2)
);
end component;
signal iecMATN0 : std_logic := '1';
signal iecMCLK0 : std_logic := '1';
signal iecMDATA0 : std_logic := '1';
signal iecSCLK0 : std_logic;
signal iecSDATA0 : std_logic;
--
-- For accessing PS/2 keyboard (via PMOD-2-PS/2 accessory)
--
signal kbled_s : slv3 := "000"; -- slave for kdb leds
signal kbled : slv3 := "000"; -- master for kbd leds
signal kbled_ne : std_logic; -- dirty. master!=slave
alias kb_data : std_logic is je(0); -- PS/2 data io
alias kb_clk : std_logic is je(2); -- PS/2 clock io
signal kb_din : std_logic; -- PS/2 data i
signal kb_clkin : std_logic; -- PS/2 clock i
signal kb_dout : std_logic := '1'; -- PS/2 data o
signal kb_clkout : std_logic := '1'; -- PS/2 clock o
--signal kb_clkout : std_logic := '0'; -- PS/2 clock o (NB: keep the 0 here!)
signal kb_slow : u6 := "000000"; -- counter to yield 64 usec period from 1 MHz
alias kb_fsm_clk : std_logic is kb_slow(5); -- msb of counter works as clock
signal kbi_sr : slv11 := "00000000000";
signal kbi_cnt : u4 := x"0";
type kb_ofsm_mode is (
kbo_idle
);
signal kb_ofsm : kb_ofsm_mode := kbo_idle;
signal kbo_sr : slv11 := "00000000000";
signal kbo_p : std_logic; -- to hold parity calc
type kbsel_t is array(7 downto 0) of byte;
signal kbsel : kbsel_t := (others => x"FF");
alias kbsel0 : byte is kbsel(0);
alias kbsel1 : byte is kbsel(1);
alias kbsel2 : byte is kbsel(2);
alias kbsel3 : byte is kbsel(3);
alias kbsel4 : byte is kbsel(4);
alias kbsel5 : byte is kbsel(5);
alias kbsel6 : byte is kbsel(6);
alias kbsel7 : byte is kbsel(7);
signal kb_restore : std_logic := '1';
--
-- Architectural implementation
--
begin
--
-- Coldstart reset for 2000 ns
--
initial_reset: process(clk_125, reset_wait) is -- counts up to 2000 ns
variable not_yet : boolean;
begin
not_yet := (reset_wait < reset_delay);
if rising_edge(clk_125) then
if not_yet then
reset_wait <= reset_wait + 1;
end if;
end if;
if not_yet then -- drive reset accordingly
res0 <= '0';
else
res0 <= '1';
end if;
end process initial_reset;
reset_12M_bridge: process(clk12,res1) is
begin
if (res1='1') then
c12fdr1 <= '1';
c12res1 <= '1';
elsif rising_edge(clk12) then
c12fdr1 <= '0';
c12res1 <= c12fdr1;
end if;
end process reset_12M_bridge;
pixclock: clk_wiz_0 port map (
-- Clock out ports
clk160 => clk160,
clk20ph1 => clk20p010,
clk20ph2 => clk20p100,
clk20ph3 => clk20p110,
clk20ph4 => clk20p000,
-- Status and control signals
reset => res1,
locked => clk_lk1,
-- Clock in ports
clk_in1 => clk_125
);
clk20gen: process(clk160) is
--clk20gen: process(clk20p000,clk20p010,clk20p100,clk20p110) is
variable cnext : slv3;
begin
if (rising_edge(clk160)) then
cnext := c20_next(clk20_ph);
clk20_ph <= cnext;
clk20_ph1 <= cnext(2) and (cnext(1) nor cnext(0));
clk20_ph2 <= not (cnext(2) or cnext(1) or cnext(0));
end if;
--if ( rising_edge(clk20p000)) then
-- clk20_ph <= "000";
--end if;
--if (falling_edge(clk20p000)) then
-- clk20_ph <= "001";
--end if;
--if ( rising_edge(clk20p010)) then
-- clk20_ph <= "010";
--end if;
--if (falling_edge(clk20p010)) then
-- clk20_ph <= "011";
--end if;
--if ( rising_edge(clk20p100)) then
-- clk20_ph <= "100";
--end if;
--if (falling_edge(clk20p100)) then
-- clk20_ph <= "101";
--end if;
--if ( rising_edge(clk20p110)) then
-- clk20_ph <= "110";
--end if;
--if (falling_edge(clk20p110)) then
-- clk20_ph <= "111";
--end if;
end process clk20gen;
--clk20_ph1 <= clk20p100;
--clk20_ph2 <= clk20p000;
cgrom_latch: process(rama,ram_clk) is
begin
if rising_edge(ram_clk) then
cgrom_data <= char_rom(rama(11 downto 0));
end if;
end process cgrom_latch;
lorom_latch: process(rama,ram_clk) is
begin
if rising_edge(ram_clk) then
lorom_data <= basic_rom(rama(12 downto 0));
end if;
end process lorom_latch;
hirom_latch: process(rama,ram_clk) is
begin
if rising_edge(ram_clk) then
hirom_data <= kernal_rom(rama(12 downto 0));
end if;
end process hirom_latch;
cpu: chip6502 port map (
a => c6510_a,
di => cpudi,
do => cpudo,
r1w0 => cpu_r1w0,
pi => c6510_pi,
po => c6510_po,
irq0 => c6510_irq0,
nmi0 => c6510_nmi0,
so0 => c6510_so0,
rdy => c6510_rdy,
ph4xin => cpu_rclk,
res0 => res0
);
irq_tie <= cia1_irq;
--irq_tie <= not btn(3);
led(3) <= not irq_tie;
c6510_irq0 <= irq_tie;
c6510_nmi0 <= '1';
c6510_so0 <= '1';
c6510_rdy <= '1';
cpu_rclk <= cpu_ph4x and cpu_run;
cpu_buscycle: process(cpu_on, cpu_ph1) is
begin
if (falling_edge(cpu_on)) then
cpu_in_cycle <= '0';
end if;
if ((cpu_on='1') and rising_edge(cpu_ph1)) then
cpu_in_cycle <= '1';
end if;
end process cpu_buscycle;
init_cnt_less1 <= init_counter -1;
initrom_latch: process(init_cnt_less1,clk160) is
begin
if (rising_edge(clk160)) then
rd_init <= ram_init(init_cnt_less1);
end if;
end process initrom_latch;
init_addr <= rd_init(23 downto 8);
init_data <= rd_init(7 downto 0);
init_ram: process(clk160,clk20_ph,init_stg) is
begin
if rising_edge(clk160) then
if (init_stg = initram_xfer and (clk20_ph >= "110" and clk20_ph <= "111")) then
init_r1w0 <= '0';
else
init_r1w0 <= '1';
end if;
if (clk20_ph = "011") then
case init_stg is
when initram_wait =>
if (init_counter = init_wait_to) then
init_counter <= x"0000";
init_stg <= initram_xfer;
--init_addr <= x"ffff";
--init_data <= x"ff";
else
init_counter <= init_counter + 1;
end if;
when initram_xfer =>
if (init_counter = ram_init_count) then
init_counter <= x"0000";
init_stg <= initram_idle;
else
--init_addr <= ram_init(init_counter)(23 downto 8);
--init_data <= ram_init(init_counter)(7 downto 0);
init_counter <= init_counter + 1;
end if;
when others =>
null;
end case;
end if;
end if;
end process init_ram;
sndclock: clk_wiz_1 port map (
-- Clock out ports
clk12 => clk12,
-- Status and control signals
reset => res1,
locked => clk_lk2,
-- Clock in ports
clk_in1 => clk_125
);
ram64: blk_ram_64k port map(
clka => ram_clk,
addra => rama,
dina => ramdw,
douta => ramdr,
wea(0) => ram_r0w1,
rsta => res1,
ena => ramen
);
color_ram: blk_cram port map(
clka => ram_clk,
addra => rama(9 downto 0),
dina => cramdw,
douta => cramdr,
wea(0) => cram_r0w1,
rsta => res1,
ena => cramen
);
res1 <= not res0;
cpu_r0w1 <= not cpu_r1w0;
ram_r0w1 <= not ram_r1w0;
cram_r0w1 <= not cram_r1w0;
init_r0w1 <= not init_r1w0;
ram_wren: process(cpu_r1w0,abus,bankctl,init_counter,init_addr,init_r1w0,init_stg,cpu_on) is
begin
if (init_stg = initram_xfer and init_counter > x"0000") then
if (init_bank(u16(init_addr)) = mbk_cram) then
cram_r1w0 <= init_r1w0;
ram_r1w0 <= '1';
else
cram_r1w0 <= '1';
ram_r1w0 <= init_r1w0;
end if;
elsif (cpu_on = '1') then
if (cpu_bank(u16(abus),bankctl) = mbk_cram) then
cram_r1w0 <= cpu_r1w0;
ram_r1w0 <= '1';
else
if (bank_is_writethru(abus,bankctl)='1') then
cram_r1w0 <= '1';
ram_r1w0 <= cpu_r1w0;
else
cram_r1w0 <= '1';
ram_r1w0 <= '1';
end if;
end if;
else
cram_r1w0 <= '1';
ram_r1w0 <= '1';
end if;
end process ram_wren;
with init_stg select ramdw <=
init_data when initram_xfer,
cpudo when others;
with init_stg select cramdw <=
init_data(3 downto 0) when initram_xfer,
cpudo(3 downto 0) when others;
abus <= c6510_a;
cur_a_bank <= cpu_bank(u16(abus),bankctl);
cur_a_wt <= bank_is_writethru(abus,bankctl);
-- CPU read data select
-- TODO: mbk_xio2,mbk_xio1
with cur_a_bank select cpudi <=
ramdr when mbk_ram,
ramdr(7 downto 4) & cramdr when mbk_cram,
vic_regr when mbk_vic,
sid1_dr when mbk_sid,
cia1_dr when mbk_cia1,
cia2_dr when mbk_cia2,
cgrom_data when mbk_cgrom,
lorom_data when mbk_lorom,
hirom_data when mbk_hirom,
ramdr when others;
with cur_a_bank select cia1EN <= '1' when mbk_cia1, '0' when others;
with cur_a_bank select cia2EN <= '1' when mbk_cia2, '0' when others;
ram_a_sel: process(init_stg,cpu_on,init_addr,abus,vbank,vic_va) is
begin
if (init_stg = initram_xfer) then
rama <= init_addr;
elsif (cpu_on = '1') then
rama <= abus;
else
rama <= vbank & vic_va;
end if;
end process ram_a_sel;
ram_clk_sel: process(init_stg,cpu_on,ramclk_init,ramclk_cpu,ramclk_vic) is
begin
if (init_stg = initram_xfer) then
ram_clk <= ramclk_init;
elsif (cpu_on = '1') then
ram_clk <= ramclk_cpu;
else
ram_clk <= ramclk_vic;
end if;
end process ram_clk_sel;
with clk20_ph select ramclk_init <=
'1' when "110",
'1' when "000",
'0' when others;
with clk20_ph select ramclk_vic <=
'1' when "110",
'1' when "000",
'0' when others;
with clk20_ph select ramclk_cpu <=
'1' when "110",
'1' when "000",
'0' when others;
vic: vic_ii port map(
clk20_ph1 => clk20_ph1,
clk20_ph2 => clk20_ph2,
rga => vic_rga,
rgdi => vic_regw,
rgdo => vic_regr,
r1w0 => vic_r1w0,
cpu_clk => cpu_ph4x,
cpu_ben => cpu_on,
vic_ben => vic_on,
bus_ph1 => cpu_ph1,
bus_ph2 => cpu_ph2,
va => vic_va,
vd => vic_vd,
cd => vic_cd,
res0 => res0,
vhs => vga_hs,
vvs => vga_vs,
vr => vga_r,
vg => vga_g,
vb => vga_b
);
vic_vd_sel: process(vbank,vic_va,ramdr) is
begin
if (vbk_cgrom(vbank,vic_va) = '1') then
--vic_wvd <= char_rom(vic_va(11 downto 0));
vic_wvd <= cgrom_data;
else
vic_wvd <= ramdr;
end if;
end process vic_vd_sel;
vic_wcd <= cramdr;
vic_vd <= vic_wvd;
vic_cd <= vic_wcd;
cpu_vicsid: if not use_init_fsm generate
cpu_start: process(cpu_on,cpu_ph1,init_stg) is
begin
if (cpu_on = '1' and init_stg=initram_idle and rising_edge(cpu_ph1)) then
cpu_run <= '1';
end if;
end process cpu_start;
vic_rga <= abus(5 downto 0);
sid1_rga <= abus(4 downto 0);
cia1_rga <= abus(3 downto 0);
cia2_rga <= abus(3 downto 0);
vic_regw <= cpudo;
sid1_dw <= cpudo;
cia1_dw <= cpudo;
cia2_dw <= cpudo;
process(cpu_in_cycle,cpu_r1w0,cur_a_bank) is
--
-- chip write select logic
--
begin
if (cpu_in_cycle='1') then
if (cur_a_bank = mbk_vic) then
vic_r1w0 <= cpu_r1w0;
else
vic_r1w0 <= '1';
end if;
if (cur_a_bank = mbk_sid) then
sid1_r1w0 <= cpu_r1w0;
else
sid1_r1w0 <= '1';
end if;
if (cur_a_bank = mbk_cia1) then
cia1_r1w0 <= cpu_r1w0;
else
cia1_r1w0 <= '1';
end if;
if (cur_a_bank = mbk_cia2) then
cia2_r1w0 <= cpu_r1w0;
else
cia2_r1w0 <= '1';
end if;
end if;
end process;
end generate;
fsm_vicsid: if use_init_fsm generate
cpu_start: process(cpu_on,cpu_ph1,c_cycle) is
begin
if (cpu_on = '1' and rising_edge(cpu_ph1)) then
if ((c_cycle(7 downto 1) & '0') = x"22") then
cpu_run <= '1';
end if;
end if;
end process cpu_start;
process(cpu_on,cpu_ph2,c_cycle) is
begin
if (cpu_on = '1' and rising_edge(cpu_ph2)) then
case c_cycle is
when x"00" =>
vic_r1w0 <= '1';
sid1_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"01" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"02" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"03" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"04" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"05" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"06" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"07" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"08" =>
vic_rga <= xtov6(x"18");
vic_regw <= "00010100";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"09" =>
vic_rga <= xtov6(x"20");
vic_regw <= x"0e";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0a" =>
vic_rga <= xtov6(x"21");
vic_regw <= x"06";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0b" =>
vic_rga <= xtov6(x"11");
vic_regw <= x"1b";
--vic_regw <= x"17";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0c" =>
vic_rga <= xtov6(x"16");
vic_regw <= x"08";
--vic_regw <= x"07";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0d" =>
vic_rga <= xtov6(x"12");
vic_r1w0 <= '1';
sid1_rga <= xtov5(x"0e");
sid1_dw <= x"25";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0e" =>
sid1_rga <= xtov5(x"0f");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0f" =>
sid1_rga <= xtov5(x"10");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"10" =>
sid1_rga <= xtov5(x"11");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"11" =>
sid1_rga <= xtov5(x"12");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"12" =>
sid1_rga <= xtov5(x"13");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"13" =>
sid1_rga <= xtov5(x"14");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"14" =>
sid1_rga <= xtov5(x"07");
sid1_dw <= x"9a";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"15" =>
sid1_rga <= xtov5(x"08");
sid1_dw <= x"15";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"16" =>
sid1_rga <= xtov5(x"09");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"17" =>
sid1_rga <= xtov5(x"0a");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"18" =>
sid1_rga <= xtov5(x"0b");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"19" =>
sid1_rga <= xtov5(x"0c");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1a" =>
sid1_rga <= xtov5(x"0d");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1b" =>
sid1_rga <= xtov5(x"00");
sid1_dw <= x"81";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1c" =>
sid1_rga <= xtov5(x"01");
sid1_dw <= x"19";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1d" =>
sid1_rga <= xtov5(x"02");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1e" =>
sid1_rga <= xtov5(x"03");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1f" =>
sid1_rga <= xtov5(x"04");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"20" =>
sid1_rga <= xtov5(x"05");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"21" =>
sid1_rga <= xtov5(x"06");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"22" =>
sid1_rga <= xtov5(x"18");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when others =>
vic_rga <= xtov6(x"12");
vic_r1w0 <= '1';
sid1_rga <= xtov5(x"12");
sid1_dw <= sw & x"1";
sid1_r1w0 <= '0';
end case;
end if;
end process vic_regs;
end generate;
sid_1: sid6581 port map (
res0 => res0,
ph2 => cpu_ph2,
rga => sid1_rga,
din => sid1_dw,
dout => sid1_dr,
r1w0 => sid1_r1w0,
s16audio => sid1_out
);
ac_muten <= res0;
ac_mclk <= clk12;
bclk_gen : process(clk12,bclk_cnt,res1) is
variable inc_0 : std_logic;
variable inc_1 : std_logic;
begin
inc_0 := not bclk_cnt(0);
inc_1 := bclk_cnt(1) xor bclk_cnt(0);
if (c12res1 = '1') then
bclk_cnt <= "00";
elsif (rising_edge(clk12)) then
bclk_cnt <= inc_1 & inc_0;
end if;
end process bclk_gen;
ac_bclk <= bclk_cnt(1);
audio_send : process(bclk_cnt,res1,sid1_out,hold_srl,audio_frame) is
variable stage : word;
variable frmZ : std_logic;
begin
if isZero6(audio_frame) then
stage := word(sid1_out);
frmZ := '1';
else
-- srl left-rotates to send MSB first
stage := hold_srl(14 downto 0) & hold_srl(15);
frmZ := '0';
end if;
if (c12res1 = '1') then
audio_frame <= "000000";
elsif (falling_edge(bclk_cnt(1))) then
if (audio_frame(4) = '0') then
-- MSB first
ac_pbdat <= stage(15);
else
-- I get a corrupt right channel if I try to
-- duplciate the data going to the left
--ac_pbdat <= stage(15);
ac_pbdat <= '0';
end if;
--ac_pblrc <= audio_frame(4);
ac_pblrc <= frmZ;
hold_srl <= stage;
audio_frame <= adv_frame(audio_frame);
end if;
end process audio_send;
--
-- I2C config for SSM2603
--
i2c: component i2c_xcvr port map (
clk1M => cpu_ph2,
res0 => res0,
init_line => ssm_init_line,
init_data => ssm_init_data,
error => ssm_error,
scl => ac_scl,
sda => ac_sda
);
ssm_init_data <= dac_init(ssm_init_line);
--led(0) <= ssm_error;
cia1: component cia6526 port map (
clk => cpu_ph2,
ce => cia1EN,
rga => cia1_rga,
rgdi => cia1_dw,
rgdo => cia1_dr,
r1w0 => cia1_r1w0,
irq0 => cia1_irq,
PAi => cia1PAi,
PAo => cia1PAo,
PBi => cia1PBi,
PBo => cia1PBo
);
cia2: component cia6526 port map (
clk => cpu_ph2,
ce => cia2EN,
rga => cia2_rga,
rgdi => cia2_dw,
rgdo => cia2_dr,
r1w0 => cia2_r1w0,
irq0 => cia2_irq,
PAi => cia2PAi,
PAo => cia2PAo,
PBi => cia2PBi,
PBo => cia2PBo
);
iecrom: ROM_IEC port map (
ATN0 => iecMATN0,
LCLK0 => iecMCLK0,
DATAI0 => iecMDATA0,
TCLK0 => iecSCLK0,
DATAO0 => iecSDATA0,
clk => cpu_ph2
);
iecMDATA0 <= not cia2PAo(5);
iecMCLK0 <= not cia2PAo(4);
iecMATN0 <= not cia2PAo(3);
cia2PAi <= iecSDATA0 & iecSCLK0 & "111111";
cia2PBi <= "11111111";
--
-- PS/2 keyboard driver
--
-- NB: je(0),je(2) choice is partly based on my hardware:
-- a PMOD12-to-2xPMOD6 splitter connected at PMOD JE where each PMOD6
-- connects to a digilent PS/2-to-PMOD6 accessory (one for keys, one
-- for mouse). JE is the only "standard" (series protection, unpaired
-- signals) PMOD on the Zybo. The PS/2 accessor does not need the
-- high speed differentials of the high-speed PMODs and using JF (MIO
-- which is PS-side) renderes the connected PMOD(s) unavailable from
-- the PL (FPGA) side.
--
-- JE(0) is the PS/2 data line.
-- JE(2) is the PS/2 clock line.
--
--signal kbled_s : slv3; -- slave for kdb leds
--signal kbled : slv3; -- master for kbd leds
--signal kbled_ne : std_logic; -- dirty. master!=slave
--
-- first let's obtain the input (real) state of the lines
kb_din <= kb_data;
kb_clkin <= kb_clk;
-- now the driving logic
with kb_dout select kb_data <=
'0' when '0', -- drive the 0
'Z' when others; -- high-Z == don't drive == line pulled to 1
with kb_clkout select kb_clk <=
'0' when '0', -- drive the 0
'Z' when others; -- high-Z == don't drive == line pulled to 1
-- the handshake...
-- The PS/2 port will only send data when the clock is released.
-- If we drive the clock low no data will be sent. When we wish to
-- send data we follow the same rule and never send when we find
-- the clock low. Normally we will find this line high when we wish
-- to send since any time it isn't our FSM is going to be in a receive
-- frame and thus not trying to send.
--
-- An input-only FSM can be driven just off the PS/2's clock signal.
--
-- To send we can have this machine pause whenever the dirty bit flips up
-- indicating the status of keyboard leds should change. It then pauses
-- once outside a frame and resumes once we clear the dirty bit in the
-- sending FSM. The sending FSM needs its own clock since the PS/2 port
-- only clocks its own transmission. The slowest ones around are the
-- PH1/PH2 clocks used to clock the 6510 and they are too fast since a
-- 1 usec period is too fast since the minimum edge period for PS/2 port
-- is 30 so we need a slowdown for clocking the sending FSM. 32 usec
-- edges will work fine (max is 60) so we'll use a 6-bit counter's msb as
-- the clock which transitions every 32 usec if the counter counts on the
-- 1 MHz PH2 clock.
--kbled_ne <= (kbled(2) xor kbled_s(2) ) or
-- (kbled(1) xor kbled_s(1) ) or
-- (kbled(0) xor kbled_s(0) );
--ps2_slow: process(cpu_ph2,kb_slow) is
--begin
-- if (rising_edge(cpu_ph2)) then
-- kb_slow <= kb_slow + 1;
-- end if;
--end process ps2_slow;
ps2_recv: process(kb_clkin,kb_din) is
variable curCnt : u4;
variable data : slv11;
variable code : byte;
variable ext : std_logic := '0';
variable iext : std_logic := '1';
variable brk : std_logic := '0';
variable rkey,xkey : std_logic;
variable restore_key : std_logic := '1';
begin
led(1) <= not kb_clkin;
led(0) <= not kb_din;
if (falling_edge(kb_clkin)) then
curCnt := kbi_cnt;
data := kbi_sr;
curCnt := curCnt + 1;
data := kb_din & kbi_sr(10 downto 1);
if (curCnt = x"b") then
curCnt := x"0";
code := data(8 downto 1);
if (code = x"E0") then
ext := '1';
iext := '0';
elsif (code = x"F0") then
brk := '1';
else
rkey := brk or ext;
xkey := brk or iext;
case code is -- PC (C64)
when x"71" => kbsel0(0) <= xkey; -- DEL
when x"70" => kbsel0(0) <= xkey; kbsel1(7) <= xkey; -- INS (shift+DEL)
when x"5A" => kbsel0(1) <= rkey; -- ENTER (RETURN)
when x"74" => kbsel0(2) <= xkey; -- right
when x"6B" => kbsel0(2) <= xkey; kbsel1(7) <= xkey; -- left (shift+CRSR RT)
when x"83" => kbsel0(3) <= rkey; -- F7
when x"0A" => kbsel0(3) <= rkey; kbsel1(7) <= rkey; -- F8 (shift+F7)
when x"05" => kbsel0(4) <= rkey; -- F1
when x"06" => kbsel0(4) <= rkey; kbsel1(7) <= rkey; -- F2 (shift+F1)
when x"04" => kbsel0(5) <= rkey; -- F3
when x"0c" => kbsel0(5) <= rkey; kbsel1(7) <= rkey; -- F4 (shift+F3)
when x"03" => kbsel0(6) <= rkey; -- F5
when x"0B" => kbsel0(6) <= rkey; kbsel1(7) <= rkey; -- F6 (shift+F5)
when x"72" => kbsel0(7) <= xkey; -- dowm
when x"75" => kbsel0(7) <= xkey; kbsel1(7) <= xkey; -- up (shift+CRSR DN)
kbsel6(6) <= rkey; -- KP 8 (exp arrow)
when x"26" => kbsel1(0) <= rkey; -- 3
when x"1D" => kbsel1(1) <= rkey; -- W
when x"1C" => kbsel1(2) <= rkey; -- A
when x"25" => kbsel1(3) <= rkey; -- 4
when x"1A" => kbsel1(4) <= rkey; -- Z
when x"1B" => kbsel1(5) <= rkey; -- S
when x"24" => kbsel1(6) <= rkey; -- E
when x"12" => kbsel1(7) <= rkey; -- LSHIFT
when x"2E" => kbsel2(0) <= rkey; -- 5
when x"2D" => kbsel2(1) <= rkey; -- R
when x"23" => kbsel2(2) <= rkey; -- D
when x"36" => kbsel2(3) <= rkey; -- 6
when x"21" => kbsel2(4) <= rkey; -- C
when x"2B" => kbsel2(5) <= rkey; -- F
when x"2C" => kbsel2(6) <= rkey; -- T
when x"22" => kbsel2(7) <= rkey; -- X
when x"3D" => kbsel3(0) <= rkey; -- 7
when x"35" => kbsel3(1) <= rkey; -- Y
when x"34" => kbsel3(2) <= rkey; -- G
when x"3E" => kbsel3(3) <= rkey; -- 8
when x"32" => kbsel3(4) <= rkey; -- B
when x"33" => kbsel3(5) <= rkey; -- H
when x"3C" => kbsel3(6) <= rkey; -- U
when x"2A" => kbsel3(7) <= rkey; -- V
when x"46" => kbsel4(0) <= rkey; -- 9
when x"43" => kbsel4(1) <= rkey; -- I
when x"3B" => kbsel4(2) <= rkey; -- J
when x"45" => kbsel4(3) <= rkey; -- 0
when x"3A" => kbsel4(4) <= rkey; -- M
when x"42" => kbsel4(5) <= rkey; -- K
when x"44" => kbsel4(6) <= rkey; -- O
when x"31" => kbsel4(7) <= rkey; -- N
when x"79" => kbsel5(0) <= rkey; -- KP + (+)
when x"4D" => kbsel5(1) <= rkey; -- P
when x"4B" => kbsel5(2) <= rkey; -- L
when x"7B" => kbsel5(3) <= rkey; -- KP - (-)
when x"4E" => kbsel5(3) <= rkey; -- -
when x"49" => kbsel5(4) <= rkey; -- .
when x"4C" => kbsel5(5) <= rkey; -- ; (:)
when x"54" => kbsel5(6) <= rkey; -- [ (@)
when x"41" => kbsel5(7) <= rkey; -- ,
when x"5D" => kbsel6(0) <= rkey; -- \ (GBP)
when x"5B" => kbsel6(1) <= rkey; -- ] (*)
when x"52" => kbsel6(2) <= rkey; -- ' (;)
when x"6C" => kbsel6(3) <= xkey; -- HOME (HOME)
when x"59" => kbsel6(4) <= rkey; -- RSHIFT
when x"55" => kbsel6(5) <= rkey; -- =
-- when x"75" *** SEE LINE 1619 *** -- KP 8 (exp arrow)
when x"4A" => kbsel6(7) <= rkey; -- /
when x"16" => kbsel7(0) <= rkey; -- 1
when x"66" => kbsel7(1) <= rkey; -- BS ( <-- )
when x"0D" => kbsel7(2) <= rkey; -- TAB (CTRL)
when x"1E" => kbsel7(3) <= rkey; -- 2
when x"29" => kbsel7(4) <= rkey; -- SPACE
when x"1F" => kbsel7(5) <= xkey; -- WINDOZE (C=)
when x"15" => kbsel7(6) <= rkey; -- Q
when x"76" => kbsel7(7) <= rkey; -- ESC (STOP)
when x"2F" => restore_key := xkey; -- MENU (RESTORE)
when others =>
null;
end case;
brk := '0';
ext := '0';
iext := '1';
end if;
end if;
end if;
kbi_sr <= data;
kbi_cnt <= curCnt;
kb_restore <= restore_key;
end process ps2_recv;
kbport: process(cia1PAo,kbsel) is
variable matrix : byte;
begin
matrix := x"FF";
for sel in 7 downto 0 loop
if (cia1PAo(sel)='0') then
matrix := matrix and kbsel(sel);
end if;
end loop;
cia1PBi <= matrix;
end process kbport;
end testing;
| gpl-3.0 | 25c7f5b2729a95cb7b1ffbac971729ea | 0.469106 | 3.243282 | false | false | false | false |
wltr/cern-onewire-idtemp | src/rtl/onewire_idtemp/onewire_interface.vhd | 1 | 7,822 | -------------------------------------------------------------------------------
--! @file onewire_interface.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief 1-wire bus interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.lfsr_pkg.all;
--! @brief Entity declaration of onewire_interface
entity onewire_interface is
generic (
--! System clock frequency in Hz
clk_frequency_g : natural := 40e6);
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Internal signals
--! @{
--! Send a bus reset command
bus_rst_i : in std_ulogic;
--! Send data bit
send_i : in std_ulogic;
--! The data bit to be sent
data_i : in std_ulogic;
--! Receive data bit
recv_i : in std_ulogic;
--! The received data bit
data_o : out std_ulogic;
--! The received data bit enable
data_en_o : out std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! @}
--! @name External signals
--! @{
--! Receiving bus input
rx_i : in std_ulogic;
--! Transmitting bus output
tx_o : out std_ulogic);
--! @}
end entity onewire_interface;
--! RTL implementation of onewire_interface
architecture rtl of onewire_interface is
-----------------------------------------------------------------------------
--! @name Types and Constants
-----------------------------------------------------------------------------
--! @{
--! Time to start a read or write operation in seconds
constant t_rw_start_c : real := 0.000005;
--! Time to wait until input is sampled during a read operation in seconds
constant t_rw_smpl_c : real := 0.000010;
--! Time to hold the state during a write operation or wait during a read operation in seconds
constant t_rw_hold_c : real := 0.00006;
--! Time to recover from a read or write operation in seconds
constant t_rw_recvr_c : real := t_rw_hold_c + 0.00001;
--! Time to start a reset command in seconds
constant t_rst_start_c : real := 0.0005;
--! Time to wait until presence pulse is sampled in seconds
constant t_rst_smpl_c : real := 0.00057;
--! Total length of reset command in seconds
constant t_rst_end_c : real := 0.001;
constant clk_period_c : real := 1.0 / real(clk_frequency_g);
constant cnt_rw_start_c : natural := natural(ceil(t_rw_start_c / clk_period_c));
constant cnt_rw_recvr_c : natural := natural(ceil(t_rw_recvr_c / clk_period_c));
constant cnt_rw_hold_c : natural := natural(ceil(t_rw_hold_c / clk_period_c));
constant cnt_rw_smpl_c : natural := natural(ceil(t_rw_smpl_c / clk_period_c));
constant cnt_rst_start_c : natural := natural(ceil(t_rst_start_c / clk_period_c));
constant cnt_rst_smpl_c : natural := natural(ceil(t_rst_smpl_c / clk_period_c));
constant cnt_rst_end_c : natural := natural(ceil(t_rst_end_c / clk_period_c));
constant lfsr_len_c : natural := lfsr_length(cnt_rst_end_c);
subtype lfsr_t is std_ulogic_vector(lfsr_len_c - 1 downto 0);
constant lfsr_seed_c : lfsr_t := lfsr_seed(lfsr_len_c);
constant max_rw_start_c : lfsr_t := x"CC73"; --lfsr_shift(lfsr_seed_c, cnt_rw_start_c - 1);
constant max_rw_recvr_c : lfsr_t := x"6EA4"; --lfsr_shift(lfsr_seed_c, cnt_rw_recvr_c - 1);
constant max_rw_hold_c : lfsr_t := x"EE75"; --lfsr_shift(lfsr_seed_c, cnt_rw_hold_c - 1);
constant max_rw_smpl_c : lfsr_t := x"8C97"; --lfsr_shift(lfsr_seed_c, cnt_rw_smpl_c - 1);
constant max_rst_start_c : lfsr_t := x"FD03"; --lfsr_shift(lfsr_seed_c, cnt_rst_start_c - 1);
constant max_rst_smpl_c : lfsr_t := x"672B"; --lfsr_shift(lfsr_seed_c, cnt_rst_smpl_c - 1);
constant max_rst_end_c : lfsr_t := x"0170"; --lfsr_shift(lfsr_seed_c, cnt_rst_end_c - 1);
type state_t is (IDLE, RESET, SEND, RECEIVE);
type reg_t is record
state : state_t;
lfsr : lfsr_t;
tx : std_ulogic;
done : std_ulogic;
data : std_ulogic;
data_en : std_ulogic;
end record;
constant init_c : reg_t := (
state => IDLE,
lfsr => lfsr_seed_c,
tx => '1',
done => '0',
data => '0',
data_en => '0');
--! @}
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal nxt_reg : reg_t;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
data_o <= reg.data;
data_en_o <= reg.data_en;
done_o <= reg.done;
tx_o <= reg.tx;
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= nxt_reg;
end if;
end if;
end process regs;
-----------------------------------------------------------------------------
-- Combinatorics
-----------------------------------------------------------------------------
comb : process (reg, bus_rst_i, send_i, recv_i, data_i, rx_i) is
begin -- process comb
-- Defaults
nxt_reg <= reg;
nxt_reg.done <= init_c.done;
nxt_reg.data_en <= init_c.data_en;
case reg.state is
when IDLE =>
if bus_rst_i = '1' then
nxt_reg.state <= RESET;
nxt_reg.tx <= '0';
elsif send_i = '1' then
nxt_reg.state <= SEND;
nxt_reg.tx <= '0';
nxt_reg.data <= data_i;
elsif recv_i = '1' then
nxt_reg.state <= RECEIVE;
nxt_reg.tx <= '0';
end if;
when RESET =>
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
if reg.lfsr = max_rst_start_c then
nxt_reg.tx <= '1';
end if;
if reg.lfsr = max_rst_smpl_c then
nxt_reg.data <= rx_i;
end if;
if reg.lfsr = max_rst_end_c then
nxt_reg <= init_c;
nxt_reg.done <= '1';
nxt_reg.data <= reg.data;
end if;
when SEND =>
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
if reg.lfsr = max_rw_start_c then
nxt_reg.tx <= reg.data;
end if;
if reg.lfsr = max_rw_hold_c then
nxt_reg.tx <= '1';
end if;
if reg.lfsr = max_rw_recvr_c then
nxt_reg <= init_c;
nxt_reg.done <= '1';
end if;
when RECEIVE =>
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
if reg.lfsr = max_rw_start_c then
nxt_reg.tx <= '1';
end if;
if reg.lfsr = max_rw_smpl_c then
nxt_reg.data <= rx_i;
end if;
if reg.lfsr = max_rw_recvr_c then
nxt_reg <= init_c;
nxt_reg.done <= '1';
nxt_reg.data <= reg.data;
nxt_reg.data_en <= '1';
end if;
end case;
end process comb;
end architecture rtl;
| lgpl-2.1 | d40946755db9ab46216eb87591a9cc66 | 0.48338 | 3.609599 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/io/vga_module.vhd | 1 | 17,207 | --------------------------------------------------------------------------------
-- WARNING! --
-- You have entered the Twilight Zone --
-- Beyond this world strange things are known. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.io.all;
--------------------------------------------------------------------------------
-- VGA MODULE
--------------------------------------------------------------------------------
entity vga_module is
generic (
RX : integer := 160; -- Number of horizontal pixels
RY : integer := 120; -- Number of vertical pixels
NUM_OF_ALIENS : integer := 24 -- Number of enemies
);
port (
clk27M : in std_logic;
reset : in std_logic;
game_state_i : GAME_STATE;
nave_x : integer range 0 to RX; -- ship x coordinate
nave_y : integer range 0 to RY; -- ship y coordinate
nave_d : std_logic; -- ship destroy
tiro_x : integer range 0 to RX; -- shoot x coordinate
tiro_y : integer range 0 to RY; -- shoot y coordinate
tiro_enemy_x : integer range 0 to RX; -- enemy shoot x coordinate
tiro_enemy_y : integer range 0 to RY; -- enemy shoot y coordinate
cpu_e : std_logic_vector(NUM_OF_ALIENS-1 downto 0);
cpu_d : std_logic_vector(NUM_OF_ALIENS-1 downto 0);
cpu_x : pos_arr_xt;
cpu_y : pos_arr_yt;
red, green, blue : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic
);
end entity;
architecture behavior of vga_module is
component vgacon is
generic (
NUM_HORZ_PIXELS : natural := 128; -- Number of horizontal pixels
NUM_VERT_PIXELS : natural := 96 -- Number of vertical pixels
);
port (
clk27M, rstn : in std_logic;
write_clk, write_enable : in std_logic;
write_addr : in integer range 0 to NUM_HORZ_PIXELS * NUM_VERT_PIXELS - 1;
data_in : in std_logic_vector (2 downto 0);
red, green, blue : out std_logic_vector (3 downto 0);
hsync, vsync : out std_logic
);
end component;
constant CONS_CLOCK_DIV : integer := 400000;
constant HORZ_SIZE : integer := 160;
constant VERT_SIZE : integer := 120;
constant NUM_HORZ_PIXELS1 : integer := 160;
constant NUM_VERT_PIXELS1 : integer := 120;
signal slow_clock : std_logic;
signal video_address : integer range 0 TO HORZ_SIZE * VERT_SIZE - 1;
signal video_word : std_logic_vector (2 downto 0);
signal video_word_s : std_logic_vector (2 downto 0);
-- Sprites
signal inv1, inv2 : std_logic_vector (87 downto 0);
signal dead_player : std_logic_vector (119 downto 0);
signal space_inv : std_logic_vector (1304 downto 0);
signal big_alien : std_logic_vector (2199 downto 0);
signal you_win : std_logic_vector (674 downto 0);
signal game_over : std_logic_vector (872 downto 0);
signal dead_inv : std_logic_vector (87 downto 0);
begin
vga_component: vgacon
generic map (
NUM_HORZ_PIXELS => HORZ_SIZE,
NUM_VERT_PIXELS => VERT_SIZE
) port map (
clk27M => clk27M,
rstn => reset,
write_clk => clk27M,
write_enable => '1',
write_addr => video_address,
data_in => video_word,
red => red,
green => green,
blue => blue,
hsync => hsync,
vsync => vsync
);
-- Clock Divider
clock_divider:
process (clk27M, reset)
variable i : INTEGER := 0;
begin
if (reset = '0') then
i := 0;
slow_clock <= '0';
elsif (rising_edge(clk27M)) then
if (i <= CONS_CLOCK_DIV/2) then
i := i + 1;
slow_clock <= '0';
elsif (i < CONS_CLOCK_DIV-1) then
i := i + 1;
slow_clock <= '1';
else
i := 0;
end if;
end if;
end process;
----------------------------------------
----------------------------------------
-- SPRITES
-- Really, these numbers are sprites!
----------------------------------------
-- Invader
inv1 <= "0001101100010100000101101111111011111111111101101110110001111111000001000100000100000100";
inv2 <= "0100000001000100000100011111111100111111111011101110111101111111011001000100100100000100";
dead_inv <= "1001000100101001010010001000001001100000001100100000100010010100101001000100100000000000";
-- Dead ship (player)
dead_player <= "011111111110101001111111100100100010110101000000000110110000001001000000000000001010100000000000000010000000001000000000";
-- Text: SPACE INVADERS
space_inv <= "111111111001100000110011111111100001111111001100000110000011000000110000011001100000000000001111111110011111111100110000011000000000110011111111111111111100110000011001111111110000111111100110000011000001100000011000001100110000000000000111111111001111111110011000001100000000011001111111111100000000000100001100000000011001100000110011000001100001101100001100000110011000000000000000000001100000000011001100000110000000001100110000000110000000000010000110000000001100110000011001100000110000110110000110000011001100000000000000000000110000000001100110000011000000000110011000000011111111100111111111000001111110011000001100111111111001100000110011000001100110000000000000000111111000000000110011111111100111111111001111111110000000110011000001100000000011001100000110011000001100110000011001100000110011000000000000000000001100000000011001100000110011000001100000000011000000011001100000110000000001100110000011001100000110011000001100110000011001100000000000000000000110000000001100110000011001100000110000000001111111111100111111111001111111110000111111100111111111001100000110011111111100110000000000000111111111001111111110011111111100111111111001111111111111111110011111111100111111111000011111110011111111100110000011001111111110011000000000000011111111100111111111001111111110011111111100111111111";
-- Text: YOU WIN
you_win <= "110000011001111111110011000001100000000000001111111110011111111100000110000110000011001111111110011000001100000000000001111111110011111111100000110000111000011000000100000011110111100000000000001100000110011000001100000110000111000011000000100000011110111100000000000001100000110011000001100000110000110110011000000100000011001001100000000000001100000110011000001100111111111110001111000000100000011000001100000000000001100000110011000001100110000011110001111000000100000011000001100000000000001100000110011000001100110000011110000011001111111110011000001100000000000001100000110011111111100110000011110000011001111111110011000001100000000000001100000110011111111100110000011";
-- Text: GAME OVER
game_over <= "110000011001111111110000011000000111111111000000000000011111111100110000011001100000110011111111111000001100111111111000001100000011111111100000000000001111111110011000001100110000011001111111110010000110000000001100001101100001100000110000000000000000000011001100000110011000001100110000011001000011000000000110000110110000110000011000000000000000000001100110000011001100000110011000001111111111100000111111001100000110011000001100000000000000001111110011011001100111111111001111100111100000110000000001100110000011001100000110000000000000000000011001111011110011000001100000000011110000011000000000110011000001100110000011000000000000000000001100111101111001100000110000000001100111111100111111111001100000110011111111100000000000001111111110011000001100111111111001111111110011111110011111111100110000011001111111110000000000000111111111001100000110011111111100111111111";
-- Big Invader
big_alien <= "0000011111000000000000000000000000000000000001111100000000001111100000000000000000000000000000000000111110000000000111110000000000000000000000000000000000011111000000000011111000000000000000000000000000000000001111100000000001111100000000000000000000000000000000000111110000000000000001111100000000000000000000000001111100000000000000000000111110000000000000000000000000111110000000000000000000011111000000000000000000000000011111000000000000000000001111100000000000000000000000001111100000000000000000000111110000000000000000000000000111110000000000000001111111111111111111111111111111111111111111110000000000111111111111111111111111111111111111111111111000000000011111111111111111111111111111111111111111111100000000001111111111111111111111111111111111111111111110000000000111111111111111111111111111111111111111111111000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000111111111111111000001111111111111111111111111111110000011111111111111100000111111111111111111111111111111000001111111111111110000011111111111111111111111111111100000111111111111111000001111111111111111111111111111110000011111111111111100000111111111111111111110000011111111111111111111111111111111111000001111111111000001111111111111111111111111111111111100000111111111100000111111111111111111111111111111111110000011111111110000011111111111111111111111111111111111000001111111111000001111111111111111111111111111111111100000111111111100000000001111100000000000000011111000000000011111111110000000000111110000000000000001111100000000001111111111000000000011111000000000000000111110000000000111111111100000000001111100000000000000011111000000000011111111110000000000111110000000000000001111100000000001111100000000001111100000000000000000000000001111100000000000000000000111110000000000000000000000000111110000000000000000000011111000000000000000000000000011111000000000000000000001111100000000000000000000000001111100000000000000000000111110000000000000000000000000111110000000000";
vga_fsm:
process (clk27M)
begin
if rising_edge(clk27M) then
case game_state_i is
-- START SCREEN
when START =>
video_word <= "000";
-- Text SPACE INVADERS
if video_address >= 4*HORZ_SIZE AND video_address < (9+4)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 7 AND (video_address mod HORZ_SIZE) < 145+7 then
video_word <= (OTHERS => space_inv( (video_address mod 160-7) + 145*(video_address/160-4))) ;
end if;
-- Big Invader
elsif video_address >= 40*HORZ_SIZE AND video_address < (40+40)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 52 AND (video_address mod HORZ_SIZE) < 55+52 then
video_word <= "0" & big_alien( (video_address mod 160-52) + 55*(video_address/160-40)) & "0" ;
end IF;
end if;
video_address <= video_address + 1;
-- GAME OVER SCREEN
when GAME_OVER_STATE =>
video_word <= "000";
-- Text "GAME OVER"
if video_address >= 4*HORZ_SIZE AND video_address < (9+4)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 32 AND (video_address mod HORZ_SIZE) < 97+32 then
video_word <= (OTHERS => game_over( (video_address mod 160-32) + 97*(video_address/160-4))) ;
end if;
-- Big Invader
elsif video_address >= 40*HORZ_SIZE AND video_address < (40+40)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 52 AND (video_address mod HORZ_SIZE) < 55+52 then
video_word <= big_alien( (video_address mod 160-52) + 55*(video_address/160-40)) & "00" ;
end if;
end if;
video_address <= video_address + 1;
-- WIN SCREEN
when WIN =>
video_word <= "000";
-- Text YOU WIN
if video_address >= 4*HORZ_SIZE AND video_address < (9+4)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 42 AND (video_address mod HORZ_SIZE) < 75+42 then
video_word <= (OTHERS => you_win( (video_address mod 160-42) + 75*(video_address/160-4))) ;
end if;
-- Big Invader
elsif video_address >= 40*HORZ_SIZE AND video_address < (40+40)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= 52 AND (video_address mod HORZ_SIZE) < 55+52 then
video_word <= "0" & big_alien( (video_address mod 160-52) + 55*(video_address/160-40)) & "0" ;
end if;
end if;
video_address <= video_address + 1;
when PLAYING =>
video_word <= "000";
video_address <= video_address + 1;
----------------------------------------
-- DRAWS THE PLAYER SHOT
----------------------------------------
if (tiro_x + tiro_y > 0) AND (video_address = (tiro_x + tiro_y*HORZ_SIZE)
OR video_address = (tiro_x + (tiro_y+1)*HORZ_SIZE)
OR video_address = (tiro_x + (tiro_y+2)*HORZ_SIZE)) then
video_word <= "001";
end if;
----------------------------------------
----------------------------------------
-- DRAWS THE PLAYER SHIP
----------------------------------------
if nave_d = '1' then
if video_address >= nave_y*HORZ_SIZE AND video_address < (nave_y+8)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= (nave_x) AND (video_address mod HORZ_SIZE) < nave_x+15 then
video_word <= '0' & dead_player( (video_address mod 160-nave_x) + 15*(video_address/160-nave_y)) & '0' ;
end if;
end if;
else
if video_address >= (nave_y)*HORZ_SIZE AND video_address < (nave_y+2)*HORZ_SIZE then
video_word <= "000";
if (video_address mod HORZ_SIZE) >= (nave_x+4) AND (video_address mod HORZ_SIZE) <= (nave_x+8) then
video_word <= "010";
end if;
elsif video_address >= (nave_y+2)*HORZ_SIZE AND video_address < (nave_y+6)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= (nave_x) AND (video_address mod HORZ_SIZE) <= (nave_x+12) then
video_word <= "010";
end if;
end if;
end if;
----------------------------------------
----------------------------------------
-- DRAWS ENEMY SHIPS
----------------------------------------
for i in NUM_OF_ALIENS-1 downto 0 loop
if video_address >= (cpu_y(i))*HORZ_SIZE and video_address < (cpu_y(i)+8)*HORZ_SIZE then
if (video_address mod HORZ_SIZE) >= (cpu_x(i)) and (video_address mod HORZ_SIZE) <= (cpu_x(i)+10) then
if cpu_d(i)='1' then
video_word <= (others => dead_inv( (video_address mod 160)-cpu_x(i) + 11*(video_address/160 - cpu_y(i)))) ;
elsif cpu_e(i)='1' then
if (cpu_x(i) rem 2) = 0 then
video_word <= (others => inv1( (video_address mod 160)-cpu_x(i) + 11*(video_address/160 - cpu_y(i)))) ;
else
video_word <= (others => inv2( (video_address mod 160)-cpu_x(i) + 11*(video_address/160 - cpu_y(i)))) ;
end if;
end if;
end if;
end if;
end loop;
----------------------------------------
----------------------------------------
-- DRAWS ENEMY SHOTS
----------------------------------------
if (tiro_enemy_x + tiro_enemy_y > 0) AND (video_address = (tiro_enemy_x + tiro_enemy_y*HORZ_SIZE)
OR video_address = (tiro_enemy_x + (tiro_enemy_y+1)*HORZ_SIZE)) then
video_word <= "100";
end if;
----------------------------------------
when others =>
end case;
end if;
end process;
end architecture;
| mit | 3af1509d3b98b2ea6dd5bf01f359a9d3 | 0.608822 | 5.455612 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/testbench/tb_regfile.vhd | 1 | 3,503 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/27/2017 09:05:36 AM
-- Module Name: tb_regfile - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity tb_regfile is
-- Port ( );
end tb_regfile;
architecture Behavioral of tb_regfile is
-- Component declarations
component regfile is
port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end component;
-- Signals and constants
constant t_per: time := 1 ns;
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal ra1: std_logic_vector(4 downto 0) := "00000";
signal ra2: std_logic_vector(4 downto 0) := "00000";
signal wa: std_logic_vector(4 downto 0) := "00000";
signal halt: std_logic := '0';
signal write_en: std_logic := '0';
signal rd1: doubleword;
signal rd2:doubleword;
signal wd: doubleword := (others => '0');
signal write_error: std_logic;
signal debug: regfile_arr;
begin
-- Instantiation
myReg: regfile
port map(
clk => clk,
rst => rst,
read_addr_1 => ra1,
read_addr_2 => ra2,
write_addr => wa,
write_data => wd,
halt => halt,
write_en => write_en,
read_data_1 => rd1,
read_data_2 => rd2,
write_error => write_error,
debug_out => debug
);
-- Clock generation
tiktok: process
begin
clk <= '0';
wait for t_per/2;
clk <= '1';
wait for t_per/2;
end process;
main: process
begin
-- Settling
wait for t_per;
-- Test error condition
wd <= (others => '1');
wa <= "00000";
write_en <= '1';
rst <= '0';
wait for t_per;
-- Test simple write and read (RAW test)
ra1 <= "00001";
ra2 <= "00010";
wa <= "00001";
write_en <= '1';
wd <= (others => '1');
wait for t_per;
-- Test write to all valid writeable registers
for I in 1 to 32 loop
wa <= std_logic_vector(to_unsigned(I, 5));
wd <= (others => '1');
write_en <= '1';
wait for t_per;
end loop;
-- Test reset
rst <= '1';
wa <= "00001";
wait for t_per;
-- Test halt
rst <= '0';
halt <= '1';
wa <= "00001";
wd <= (others => '1');
wait for t_per;
-- Test resume
halt <= '0';
wa <= "00001";
wd <= (others => '1');
wait for t_per;
wait;
end process;
end Behavioral;
| mit | 2f676fe13c12abaaf1e21380df81c12f | 0.510991 | 3.622544 | false | true | false | false |
SLongofono/Senior_Design_Capstone | Demo/Decode.vhd | 1 | 22,710 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/06/2017 10:33:06 AM
-- Module Name: decode - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- Decode Unit
-- Determines the intruction type
-- Parses out all possible fields (whether or not they are relevant)
-- May sign extend and prepare a full immediate address, I'm not sure if
-- this is the right place to do this yet. For now, just pulls the 12 or 20 bit
-- raw immediate value based on instruction type. See config.vhd for typedefs and constants
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity decode is
Port(
instr : in std_logic_vector(63 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20)
);
end decode;
architecture Behavioral of decode is
signal s_imm12 : std_logic_vector(11 downto 0);
signal s_imm20 : std_logic_vector(19 downto 0);
signal s_instr_t: instr_t;
signal s_shamt: std_logic_vector(4 downto 0);
signal s_csr: std_logic_vector(11 downto 0);
begin
-- Update instruction type whenever it changes
process(instr)
begin
s_imm12 <= (others => '0');
s_imm20 <= (others => '0');
s_instr_t<= (others => '1');
s_shamt <= (others => '0');
s_csr <= (others => '0');
case instr(6 downto 0) is
when LUI_T =>
s_instr_t <= instr_LUI;
s_imm20 <= instr(31 downto 12);
when AUIPC_T =>
s_instr_t <= instr_AUIPC;
s_imm20 <= instr(31 downto 12);
when JAL_T =>
s_instr_t <= instr_JAL;
s_imm20 <= instr(31) & instr(19 downto 12) & instr(20) & instr(30 downto 21);
when JALR_T =>
s_instr_t <= instr_JALR;
s_imm12 <= instr(31 downto 20);
when BRANCH_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_BEQ;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "001" =>
s_instr_t <= instr_BNE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "100" =>
s_instr_t <= instr_BLT;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "101" =>
s_instr_t <= instr_BGE;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "110" =>
s_instr_t <= instr_BLTU;
s_imm12 <= instr(31) & instr(7) & instr(30 downto 25) & instr(11 downto 8);
when "111" =>
s_instr_t <= instr_BGEU;
s_imm12 <= instr(31) & instr(0) & instr(30 downto 25) & instr(11 downto 8);
when others => -- error state
end case;
when LOAD_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_LB;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_LH;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_LW;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_LBU;
s_imm12 <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_LHU;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_LWU;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_LD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when STORE_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_SB;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "001" =>
s_instr_t <= instr_SH;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "010" =>
s_instr_t <= instr_SW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_SD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => -- error state
end case;
when ALUI_T =>
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDI;
s_imm12 <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_SLTI;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_SLTIU;
s_imm12 <= instr(31 downto 20);
when "100" =>
s_instr_t <= instr_XORI;
s_imm12 <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_ORI;
s_imm12 <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_ANDI;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLI;
s_shamt <= instr(24 downto 20);
when "101" =>
if (instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAI;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLI;
s_shamt <= instr(24 downto 20);
end if;
when others => -- error state
end case;
when ALU_T =>
if(instr(31 downto 25)="0000001") then
-- Case RV32M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MUL;
when "001" => s_instr_t <= instr_MULH;
when "010" => s_instr_t <= instr_MULHSU;
when "011" => s_instr_t <= instr_MULHU;
when "100" => s_instr_t <= instr_DIV;
when "101" => s_instr_t <= instr_DIVU;
when "110" => s_instr_t <= instr_REM;
when "111" => s_instr_t <= instr_REMU;
when others => -- error state
end case;
else
-- Case RV32I
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUB;
else
s_instr_t <= instr_ADD;
end if;
when "001" =>
s_instr_t <= instr_SLL;
when "010" =>
s_instr_t <= instr_SLT;
when "011" =>
s_instr_t <= instr_SLTU;
when "100" =>
s_instr_t <= instr_XOR;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRA;
else
s_instr_t <= instr_SRL;
end if;
when "110" =>
s_instr_t <= instr_OR;
when "111" =>
s_instr_t <= instr_AND;
when others => -- error state
end case;
end if;
when FENCE_T =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FENCE;
else
s_instr_t <= instr_FENCEI;
end if;
when CSR_T =>
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 20) = "000000000000") then
s_instr_t <= instr_EBREAK;
elsif(instr(31 downto 20) = "000000000001") then
s_instr_t <= instr_ECALL;
elsif(instr(31 downto 20) = "000000000010") then
s_instr_t <= instr_URET;
elsif(instr(31 downto 20) = "000100000010") then
s_instr_t <= instr_SRET;
elsif(instr(31 downto 20) = "001100000010") then
s_instr_t <= instr_MRET;
elsif(instr(31 downto 20) = "000100000101") then
s_instr_t <= instr_WFI;
elsif(instr(31 downto 25) = "0001001") then
s_instr_t <= instr_SFENCEVM;
else
end if;
when "001" =>
s_instr_t <= instr_CSRRW;
s_csr <= instr(31 downto 20);
when "010" =>
s_instr_t <= instr_CSRRS;
s_csr <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_CSRRC;
s_csr <= instr(31 downto 20);
when "101" =>
s_instr_t <= instr_CSRRWI;
s_csr <= instr(31 downto 20);
when "110" =>
s_instr_t <= instr_CSRRSI;
s_csr <= instr(31 downto 20);
when "111" =>
s_instr_t <= instr_CSRRCI;
s_csr <= instr(31 downto 20);
when others => -- error state
end case;
when ALUW_T =>
if(instr(31 downto 25) = "0000001") then
-- Case RV64M
case instr(14 downto 12) is
when "000" => s_instr_t <= instr_MULW;
when "100" => s_instr_t <= instr_DIVW;
when "101" => s_instr_t <= instr_DIVUW;
when "110" => s_instr_t <= instr_REMW;
when "111" => s_instr_t <= instr_REMUW;
when others => --error state
end case;
else
-- Case 64I ALU
case instr(14 downto 12) is
when "000" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SUBW;
else
s_instr_t <= instr_ADDW;
end if;
when "001" =>
s_instr_t <= instr_SLLW;
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAW;
else
s_instr_t <= instr_SRLW;
end if;
when others => -- error state
end case;
end if;
when ALUIW_T =>
-- case RV64I
case instr(14 downto 12) is
when "000" =>
s_instr_t <= instr_ADDIW;
s_imm12 <= instr(31 downto 20);
when "001" =>
s_instr_t <= instr_SLLIW;
s_shamt <= instr(24 downto 20);
when "101" =>
if(instr(31 downto 25) = "0100000") then
s_instr_t <= instr_SRAIW;
s_shamt <= instr(24 downto 20);
else
s_instr_t <= instr_SRLIW;
s_shamt <= instr(24 downto 20);
end if;
when others => --error state
end case;
when ATOM_T =>
if(instr(14 downto 12)="011") then
-- case RV64A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRD;
when "00011" => s_instr_t <= instr_SCD;
when "00001" => s_instr_t <= instr_AMOSWAPD;
when "00000" => s_instr_t <= instr_AMOADDD;
when "00100" => s_instr_t <= instr_AMOXORD;
when "01100" => s_instr_t <= instr_AMOANDD;
when "01000" => s_instr_t <= instr_AMOORD;
when "10000" => s_instr_t <= instr_AMOMIND;
when "10100" => s_instr_t <= instr_AMOMAXD;
when "11000" => s_instr_t <= instr_AMOMINUD;
when "11100" => s_instr_t <= instr_AMOMAXUD;
when others => --error state
end case;
else
-- case RV32A
case instr(31 downto 27) is
when "00010" => s_instr_t <= instr_LRW;
when "00011" => s_instr_t <= instr_SCW;
when "00001" => s_instr_t <= instr_AMOSWAPW;
when "00000" => s_instr_t <= instr_AMOADDW;
when "00100" => s_instr_t <= instr_AMOXORW;
when "01100" => s_instr_t <= instr_AMOANDW;
when "01000" => s_instr_t <= instr_AMOORW;
when "10000" => s_instr_t <= instr_AMOMINW;
when "10100" => s_instr_t <= instr_AMOMAXW;
when "11000" => s_instr_t <= instr_AMOMINUW;
when "11100" => s_instr_t <= instr_AMOMAXUW;
when others => --error state
end case;
end if;
when FLOAD_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FLW;
s_imm12 <= instr(31 downto 20);
when "011" =>
s_instr_t <= instr_FLD;
s_imm12 <= instr(31 downto 20);
when others => --error state
end case;
when FSTORE_T =>
case instr(14 downto 12) is
when "010" =>
s_instr_t <= instr_FSW;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when "011" =>
s_instr_t <= instr_FSD;
s_imm12 <= instr(31 downto 25) & instr(11 downto 7);
when others => --error state
end case;
when FMADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMADDS;
else
s_instr_t <= instr_FMADDD;
end if;
when FMSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FMSUBS;
else
s_instr_t <= instr_FMSUBD;
end if;
when FNADD_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMADDS;
else
s_instr_t <= instr_FNMADDD;
end if;
when FNSUB_T =>
if(instr(26 downto 25) = "00") then
s_instr_t <= instr_FNMSUBS;
else
s_instr_t <= instr_FNMSUBD;
end if;
when FPALU_T =>
case instr(31 downto 25) is
when "0000000" =>
s_instr_t <= instr_FADDS;
when "0000100" =>
s_instr_t <= instr_FSUBS;
when "0001000" =>
s_instr_t <= instr_FMULS;
when "0001100" =>
s_instr_t <= instr_FDIVS;
when "0101100" =>
s_instr_t <= instr_FSQRTS;
when "0010000" =>
if (instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJS;
elsif (instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJNS;
else
s_instr_t <= instr_FSGNJXS;
end if;
when "0010100" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMINS;
else
s_instr_t <= instr_FMAXS;
end if;
when "1100000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWS;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUS;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLS;
else
s_instr_t <= instr_FCVTLUS;
end if;
when "1110000" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMVXW;
else
s_instr_t <= instr_FCLASSS;
end if;
when "1010000" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQS;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTS;
else
s_instr_t <= instr_FLES;
end if;
when "1101000" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTSW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTSWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTSL;
else
s_instr_t <= instr_FCVTSLU;
end if;
when "1111000" =>
s_instr_t <= instr_FMVWX;
when "0000001" =>
s_instr_t <= instr_FADDD;
when "0000101" =>
s_instr_t <= instr_FSUBD;
when "0001001" =>
s_instr_t <= instr_FMULD;
when "0001101" =>
s_instr_t <= instr_FDIVD;
when "0101101" =>
s_instr_t <= instr_FSQRTD;
when "0010001" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FSGNJD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FSGNJND;
else
s_instr_t <= instr_FSGNJXD;
end if;
when "0010101" =>
if(instr(14 downto 12) = "000") then
s_instr_t <= instr_FMIND;
else
s_instr_t <= instr_FMAXD;
end if;
when "0100000" =>
s_instr_t <= instr_FCVTSD;
when "0100001" =>
s_instr_t <= instr_FCVTDS;
when "1010001" =>
if(instr(14 downto 12) = "010") then
s_instr_t <= instr_FEQD;
elsif(instr(14 downto 12) = "001") then
s_instr_t <= instr_FLTD;
else
s_instr_t <= instr_FLED;
end if;
when "1110001" =>
if(instr(14 downto 12) = "001") then
s_instr_t <= instr_FCLASSD;
else
s_instr_t <= instr_FMVXD;
end if;
when "1100001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTWD;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTWUD;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTLD;
else
s_instr_t <= instr_FCVTLUD;
end if;
when "1101001" =>
if(instr(24 downto 20) = "00000") then
s_instr_t <= instr_FCVTDW;
elsif(instr(24 downto 20) = "00001") then
s_instr_t <= instr_FCVTDWU;
elsif(instr(24 downto 20) = "00010") then
s_instr_t <= instr_FCVTDL;
else
s_instr_t <= instr_FCVTDLU;
end if;
when "1111001" =>
s_instr_t <= instr_FMVDX;
when others => --error state
end case;
when others => -- error state
end case;
end process;
rd <= instr(11 downto 7);
rs1 <= instr(19 downto 15);
rs2 <= instr(24 downto 20);
rs3 <= instr(31 downto 27);
funct3 <= instr(14 downto 12);
funct6 <= instr(31 downto 26);
funct7 <= instr(31 downto 25);
opcode <= instr(6 downto 0);
imm12 <= s_imm12;
imm20 <= s_imm20;
shamt <= s_shamt;
csr <= s_csr;
instr_code <= s_instr_t;
end Behavioral;
| mit | 0d099b3ff0cd4efc8d082ce33c85296b | 0.38133 | 4.423451 | false | false | false | false |
satputeaditya/vernier-ring-oscillator-tdc | vernier_ring_tdc_top.vhd | 1 | 2,188 | -- vernier_ring_tdc_top.vhd
--**********************************************************************
-- HDL to detect if STOP pulse is leading and lagging edge wrt START
--**********************************************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
entity vernier_ring_tdc_top is
port (
rst : in std_logic;
start : in std_logic;
stop : in std_logic;
count : out std_logic_Vector(15 downto 0):=x"0000"
);
end entity;
architecture behave of vernier_ring_tdc_top is
signal slow_clk : std_logic:='0';
signal fast_clk : std_logic:='0';
signal leading : std_logic:='0';
signal lagging : std_logic:='0';
component coincidence_detector
port (
rst : in std_logic;
slow_clk : in std_logic;
fast_clk : in std_logic;
leading : out std_logic; -- SLOW CLK = Reference
lagging : out std_logic -- SLOW CLK = Reference
);
end component;
component fast_oscillator
port (
stop : in std_logic;
fast_clk : out std_logic:='0'
);
end component;
component slow_oscillator
port (
start : in std_logic;
slow_clk : out std_logic:='0'
);
end component;
component counter
port (
rst : in std_logic;
slow_clk : in std_logic;
fast_clk : in std_logic;
latch : in std_logic;
count : out std_logic_Vector(15 downto 0):=x"0000"
);
end component;
begin
U1 : coincidence_detector
port map(
rst => rst,
slow_clk => slow_clk,
fast_clk => fast_clk,
leading => leading,
lagging => lagging
);
U2 : fast_oscillator
port map(
stop => stop,
fast_clk => fast_clk
);
U3 : slow_oscillator
port map(
start => start,
slow_clk => slow_clk
);
U4 : counter
port map(
rst => rst,
slow_clk => slow_clk,
fast_clk => fast_clk,
latch => leading,
count => count
);
end behave;
| mit | 3fd0adf7484732468a83179c909bd028 | 0.502742 | 3.047354 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/timer.vhd | 1 | 1,503 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 01:43:16 PM
-- Module Name: timer - Behavioral
-- Description: Control unit timer module
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity timer is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
CSR_compare: in doubleword; -- Comparison value to trigger interrupt
CSR_count: out doubleword; -- Current timer count in 50 MHz ticks
timer_interrupt: out std_logic -- Interrupt condition signal
);
end timer;
architecture Behavioral of timer is
-- latch for counter
signal lastVal: doubleword;
signal interrupt: std_logic;
begin
-- Updates counter value
process(clk, rst)
begin
if('1' = rst) then
lastVal <= (others => '0');
elsif(rising_edge(clk)) then
lastVal <= std_logic_vector(unsigned(lastVal) + 1);
end if;
end process;
-- Triggers timer interrupt signal
process(CSR_compare, lastVal)
begin
if(unsigned(CSR_compare) = unsigned(lastVal)) then
interrupt <= '1';
else
interrupt <= '0';
end if;
end process;
CSR_count <= lastVal;
timer_interrupt <= interrupt;
end Behavioral;
| mit | 8d8fa08828d2f8ae8b09231230cd971c | 0.567532 | 4.129121 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/demo_tb/tb_div.vhd | 1 | 14,541 | ---------------------------------------------------------------------------
--
-- (c) Copyright 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
---------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the Divider Generator
-- LogiCORE module. The testbench has been generated by the Xilinx
-- CORE Generator software to accompany the netlist you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with the netlist created for your core.
--
-- See the Divider Generator datasheet for further information about
-- this core.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated Divider Generator core
-- named "div".
--
-- There are two versions of your core that you can use in this testbench:
-- the XilinxCoreLib behavioral model or the generated netlist.
--
-- 1. XilinxCoreLib behavioral model
-- Compile div.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
-- 2. Generated netlist
-- Execute the following command in the directory containing your CORE
-- Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl div.ngc div_netlist.vhd
--
-- Compile div_netlist.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_div is
end tb_div;
architecture tb of tb_div is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
constant TEST_CYCLES : integer := 3000;
constant PHASE_CYCLES : integer := 1000;
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Slave channel DIVIDEND inputs
signal s_axis_dividend_tvalid : std_logic := '0'; -- TVALID for channel A
signal s_axis_dividend_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel A
-- Slave channel DIVISOR inputs
signal s_axis_divisor_tvalid : std_logic := '0'; -- TVALID for channel B
signal s_axis_divisor_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel B
-- Breakout signals. These signals are the application-specific operands which
-- become subfields of the TDATA fields.
signal dividend : std_logic_vector(12 downto 0) := (others => '0');
signal divisor : std_logic_vector(12 downto 0) := (others => '0');
signal quotient : std_logic_vector(12 downto 0) := (others => '0');
signal fractional : std_logic_vector(11 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- DUT output signals
-----------------------------------------------------------------------
-- Master channel DOUT outputs
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel DOUT
signal m_axis_dout_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- TDATA for channel DOUT
-----------------------------------------------------------------------
-- Testbench signals
-----------------------------------------------------------------------
signal cycles : integer := 0; -- Clock cycle counter
-----------------------------------------------------------------------
-- Constants, types and functions to create input data
-- Feed the divider walking ones on the dividend and walking one's with the
-- LSB set so as to show simple results which will still use remainder and fraction,
-- e.g. 8/5.
-----------------------------------------------------------------------
constant IP_dividend_DEPTH : integer := 30;
constant IP_dividend_WIDTH : integer := 13;
constant IP_divisor_DEPTH : integer := 32;
constant IP_divisor_WIDTH : integer := 13;
subtype T_IP_dividend_ENTRY is std_logic_vector(IP_dividend_WIDTH-1 downto 0);
subtype T_IP_divisor_ENTRY is std_logic_vector(IP_divisor_WIDTH-1 downto 0);
type T_IP_dividend_TABLE is array (0 to IP_dividend_DEPTH-1) of T_IP_dividend_ENTRY;
type T_IP_divisor_TABLE is array (0 to IP_divisor_DEPTH-1) of T_IP_divisor_ENTRY;
-- Use separate functions to calculate channel dividend and divisor
-- waveforms as they return different widths in general
function create_ip_dividend_table return T_IP_dividend_TABLE is
variable result : T_IP_dividend_TABLE;
variable entry_int : signed(IP_dividend_WIDTH-1 downto 0) := (others => '0');
begin
for i in 0 to IP_dividend_DEPTH-1 loop
entry_int := (others => '0');
entry_int(i mod IP_dividend_WIDTH) := '1';
result(i) := std_logic_vector(entry_int);
end loop;
return result;
end function create_ip_dividend_table;
function create_ip_divisor_table return T_IP_divisor_TABLE is
variable result : T_IP_divisor_TABLE;
variable entry_int : signed(IP_divisor_WIDTH-1 downto 0) := (others => '0');
begin
for i in 0 to IP_divisor_DEPTH-1 loop
entry_int := (others => '0');
entry_int(0) := '1';
entry_int(i mod IP_divisor_WIDTH) := '1';
result(i) := std_logic_vector(entry_int);
end loop;
return result;
end function create_ip_divisor_table;
-- Call the functions to create the data
constant IP_dividend_DATA : T_IP_dividend_TABLE := create_ip_dividend_table;
constant IP_divisor_DATA : T_IP_divisor_TABLE := create_ip_divisor_table;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.div
port map (
aclk => aclk,
s_axis_dividend_tvalid => s_axis_dividend_tvalid,
s_axis_dividend_tdata => s_axis_dividend_tdata,
s_axis_divisor_tvalid => s_axis_divisor_tvalid,
s_axis_divisor_tdata => s_axis_divisor_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tdata => m_axis_dout_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
cycles <= cycles + 1;
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
if cycles >= TEST_CYCLES then
report "Not a real failure. Simulation finished successfully." severity failure;
wait;
end if;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
variable ip_dividend_index : integer := 0;
variable ip_divisor_index : integer := 0;
variable dividend_tvalid_nxt : std_logic := '0';
variable divisor_tvalid_nxt : std_logic := '0';
variable phase2_cycles : integer := 1;
variable phase2_count : integer := 0;
constant PHASE2_LIMIT : integer := 30;
begin
-- Test is stopped in clock_gen process, use endless loop here
loop
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive AXI TVALID signals to demonstrate different types of operation
case cycles is -- do different types of operation at different phases of the test
when 0 to PHASE_CYCLES * 1 - 1 =>
-- Phase 1: inputs always valid, no missing input data
dividend_tvalid_nxt := '1';
divisor_tvalid_nxt := '1';
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
-- Phase 2: deprive channel A of valid transactions at an increasing rate
divisor_tvalid_nxt := '1';
if phase2_count < phase2_cycles then
dividend_tvalid_nxt := '0';
else
dividend_tvalid_nxt := '1';
end if;
phase2_count := phase2_count + 1;
if phase2_count >= PHASE2_LIMIT then
phase2_count := 0;
phase2_cycles := phase2_cycles + 1;
end if;
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
-- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions
if cycles mod 2 = 0 then
dividend_tvalid_nxt := '0';
else
dividend_tvalid_nxt := '1';
end if;
if cycles mod 3 = 0 then
divisor_tvalid_nxt := '0';
else
divisor_tvalid_nxt := '1';
end if;
when others =>
-- Test will stop imminently - do nothing
null;
end case;
-- Drive handshake signals with local variable values
s_axis_dividend_tvalid <= dividend_tvalid_nxt;
s_axis_divisor_tvalid <= divisor_tvalid_nxt;
-- Drive AXI slave channel A payload
-- Drive 'X's on payload signals when not valid
if dividend_tvalid_nxt /= '1' then
s_axis_dividend_tdata <= (others => 'X');
else
-- TDATA: This holds the dividend operand. It is 13 bits wide and byte-aligned with the operand in the LSBs
s_axis_dividend_tdata <= std_logic_vector(resize(signed(IP_dividend_DATA(ip_dividend_index)),16));
end if;
-- Drive AXI slave channel B payload
-- Drive 'X's on payload signals when not valid
if divisor_tvalid_nxt /= '1' then
s_axis_divisor_tdata <= (others => 'X');
else
-- TDATA: Holds the divisor operand. It is 13 bits wide and byte-aligned with the operand in the LSBs
s_axis_divisor_tdata <= std_logic_vector(resize(signed(IP_divisor_DATA(ip_divisor_index)),16));
end if;
-- Increment input data indices
if dividend_tvalid_nxt = '1' then
ip_dividend_index := ip_dividend_index + 1;
if ip_dividend_index = IP_dividend_DEPTH then
ip_dividend_index := 0;
end if;
end if;
if divisor_tvalid_nxt = '1' then
ip_divisor_index := ip_divisor_index + 1;
if ip_divisor_index = IP_divisor_DEPTH then
ip_divisor_index := 0;
end if;
end if;
end loop;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the DOUT channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_dout_tvalid = '1' then
if is_x(m_axis_dout_tdata) then
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
divisor <= s_axis_divisor_tdata(12 downto 0);
dividend <= s_axis_dividend_tdata(12 downto 0);
fractional <= m_axis_dout_tdata(11 downto 0);
quotient <= m_axis_dout_tdata(24 downto 12);
end tb;
| gpl-3.0 | 17f1e1c29d3828a311b088f17140d443 | 0.579671 | 4.403695 | false | false | false | false |
wltr/cern-onewire-idtemp | src/rtl/onewire_idtemp/onewire_crc.vhd | 1 | 2,573 | -------------------------------------------------------------------------------
--! @file onewire_crc.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief Calculate the CRC of incoming data bits. (x^8 + x^5 + x^4 + 1)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! @brief Entity declaration of onewire_crc
entity onewire_crc is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Status and control signals
--! @{
--! Reset CRC generation
reset_i : in std_ulogic;
--! Incoming data bit
data_i : in std_ulogic;
--! Incoming data bit enable
data_en_i : in std_ulogic;
--! CRC valid flag
valid_o : out std_ulogic);
--! @}
end entity onewire_crc;
--! RTL implementation of onewire_crc
architecture rtl of onewire_crc is
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal crc : std_ulogic_vector(7 downto 0);
signal pristine : std_ulogic;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
valid_o <= '1' when crc = x"00" and pristine = '0' else '0';
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
crc <= (others => '0');
pristine <= '1';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' or reset_i = '1' then
reset;
elsif data_en_i = '1' then
crc(0) <= crc(1);
crc(1) <= crc(2);
crc(2) <= crc(3) xor crc(0) xor data_i;
crc(3) <= crc(4) xor crc(0) xor data_i;
crc(4) <= crc(5);
crc(5) <= crc(6);
crc(6) <= crc(7);
crc(7) <= crc(0) xor data_i;
pristine <= '0';
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 047cd73d29a589bf44025563c4c16caf | 0.413525 | 4.190554 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/sid6581.vhd | 3 | 22,220 | ----------------------------------------------------------------------------------
--
-- SID chip (audio)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sid6581 is
port (
res0 : in std_logic;
ph2 : in std_logic;
rga : in std_logic_vector(4 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
s16audio : out signed(15 downto 0)
);
end sid6581;
architecture sid_impl of sid6581 is
signal r0w1 : std_logic;
attribute gated_clock : string;
--attribute gated_clock of ph2:signal is "true";
component sid_voice is
port (
clk1M : in std_logic;
freq : in unsigned (15 downto 0);
pw : in unsigned (11 downto 0);
wvfm : in std_logic_vector (3 downto 0);
test : in std_logic;
rmod : in std_logic;
sync : in std_logic;
gate : in std_logic;
enva : in unsigned (3 downto 0);
envd : in unsigned (3 downto 0);
envs : in unsigned (3 downto 0);
envr : in unsigned (3 downto 0);
envo : out unsigned (7 downto 0);
osco : out unsigned (7 downto 0);
uout : out unsigned (7 downto 0)
);
end component;
component ccm_85
port (
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(9 DOWNTO 0);
p : out STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end component;
subtype u3 is unsigned (2 downto 0);
subtype u4 is unsigned (3 downto 0);
subtype nybble is std_logic_vector (3 downto 0);
subtype u8 is unsigned (7 downto 0);
subtype byte is std_logic_vector (7 downto 0);
subtype slv10 is std_logic_vector (9 downto 0);
subtype s10 is signed (9 downto 0);
subtype u11 is unsigned (10 downto 0);
subtype u12 is unsigned (11 downto 0);
subtype slv12 is std_logic_vector (11 downto 0);
subtype s16 is signed (15 downto 0);
subtype u16 is unsigned (15 downto 0);
subtype word is std_logic_vector (15 downto 0);
subtype s20 is signed (19 downto 0);
signal clk1m : std_logic;
type sidregs_t is array(28 downto 0) of byte;
signal sid_regs : sidregs_t := (others => x"00");
signal v1_freq : u16;
signal v1_pw : u12;
alias v1_wvfm : nybble is sid_regs( 4)(7 downto 4);
alias v1_test : std_logic is sid_regs( 4)(3);
alias v1_ring : std_logic is sid_regs( 4)(2);
alias v1_sync : std_logic is sid_regs( 4)(1);
alias v1_gate : std_logic is sid_regs( 4)(0);
alias v1_enva : nybble is sid_regs( 5)(7 downto 4);
alias v1_envd : nybble is sid_regs( 5)(3 downto 0);
alias v1_envs : nybble is sid_regs( 6)(7 downto 4);
alias v1_envr : nybble is sid_regs( 6)(3 downto 0);
signal v1_envo : u8;
signal v1_osco : u8;
signal v1_out : u8;
signal v2_freq : u16;
signal v2_pw : u12;
alias v2_wvfm : nybble is sid_regs(11)(7 downto 4);
alias v2_test : std_logic is sid_regs(11)(3);
alias v2_ring : std_logic is sid_regs(11)(2);
alias v2_sync : std_logic is sid_regs(11)(1);
alias v2_gate : std_logic is sid_regs(11)(0);
alias v2_enva : nybble is sid_regs(12)(7 downto 4);
alias v2_envd : nybble is sid_regs(12)(3 downto 0);
alias v2_envs : nybble is sid_regs(13)(7 downto 4);
alias v2_envr : nybble is sid_regs(13)(3 downto 0);
signal v2_envo : u8;
signal v2_osco : u8;
signal v2_out : u8;
signal v3_freq : u16;
signal v3_pw : u12;
alias v3_wvfm : nybble is sid_regs(18)(7 downto 4);
alias v3_test : std_logic is sid_regs(18)(3);
alias v3_ring : std_logic is sid_regs(18)(2);
alias v3_sync : std_logic is sid_regs(18)(1);
alias v3_gate : std_logic is sid_regs(18)(0);
alias v3_enva : nybble is sid_regs(19)(7 downto 4);
alias v3_envd : nybble is sid_regs(19)(3 downto 0);
alias v3_envs : nybble is sid_regs(20)(7 downto 4);
alias v3_envr : nybble is sid_regs(20)(3 downto 0);
signal v3_envo : u8;
signal v3_osco : u8;
signal v3_out : u8;
signal filter_fc : u11;
alias filter_res : u4 is u4(sid_regs(23)(7 downto 4));
alias filter_v3 : std_logic is sid_regs(23)(2);
alias filter_v2 : std_logic is sid_regs(23)(1);
alias filter_v1 : std_logic is sid_regs(23)(0);
alias mute3 : std_logic is sid_regs(24)(7);
alias filter_hp : std_logic is sid_regs(24)(6);
alias filter_bp : std_logic is sid_regs(24)(5);
alias filter_lp : std_logic is sid_regs(24)(4);
alias volume : nybble is sid_regs(24)(3 downto 0);
alias pot_x : byte is sid_regs(25);
alias pot_y : byte is sid_regs(26);
alias osc3rnd : byte is sid_regs(27);
alias env3 : byte is sid_regs(28);
function u8tos10(uns : u8) return s10 is
begin
case uns is
when x"00" => return to_signed(-128,10);
when x"01" => return to_signed(-127,10);
when x"02" => return to_signed(-126,10);
when x"03" => return to_signed(-125,10);
when x"04" => return to_signed(-124,10);
when x"05" => return to_signed(-123,10);
when x"06" => return to_signed(-122,10);
when x"07" => return to_signed(-121,10);
when x"08" => return to_signed(-120,10);
when x"09" => return to_signed(-119,10);
when x"0a" => return to_signed(-118,10);
when x"0b" => return to_signed(-117,10);
when x"0c" => return to_signed(-116,10);
when x"0d" => return to_signed(-115,10);
when x"0e" => return to_signed(-114,10);
when x"0f" => return to_signed(-113,10);
when x"10" => return to_signed(-112,10);
when x"11" => return to_signed(-111,10);
when x"12" => return to_signed(-110,10);
when x"13" => return to_signed(-109,10);
when x"14" => return to_signed(-108,10);
when x"15" => return to_signed(-107,10);
when x"16" => return to_signed(-106,10);
when x"17" => return to_signed(-105,10);
when x"18" => return to_signed(-104,10);
when x"19" => return to_signed(-103,10);
when x"1a" => return to_signed(-102,10);
when x"1b" => return to_signed(-101,10);
when x"1c" => return to_signed(-100,10);
when x"1d" => return to_signed(- 99,10);
when x"1e" => return to_signed(- 98,10);
when x"1f" => return to_signed(- 97,10);
when x"20" => return to_signed(- 96,10);
when x"21" => return to_signed(- 95,10);
when x"22" => return to_signed(- 94,10);
when x"23" => return to_signed(- 93,10);
when x"24" => return to_signed(- 92,10);
when x"25" => return to_signed(- 91,10);
when x"26" => return to_signed(- 80,10);
when x"27" => return to_signed(- 89,10);
when x"28" => return to_signed(- 88,10);
when x"29" => return to_signed(- 87,10);
when x"2a" => return to_signed(- 86,10);
when x"2b" => return to_signed(- 85,10);
when x"2c" => return to_signed(- 84,10);
when x"2d" => return to_signed(- 83,10);
when x"2e" => return to_signed(- 82,10);
when x"2f" => return to_signed(- 81,10);
when x"30" => return to_signed(- 80,10);
when x"31" => return to_signed(- 79,10);
when x"32" => return to_signed(- 78,10);
when x"33" => return to_signed(- 77,10);
when x"34" => return to_signed(- 76,10);
when x"35" => return to_signed(- 75,10);
when x"36" => return to_signed(- 74,10);
when x"37" => return to_signed(- 73,10);
when x"38" => return to_signed(- 72,10);
when x"39" => return to_signed(- 71,10);
when x"3a" => return to_signed(- 70,10);
when x"3b" => return to_signed(- 69,10);
when x"3c" => return to_signed(- 68,10);
when x"3d" => return to_signed(- 67,10);
when x"3e" => return to_signed(- 66,10);
when x"3f" => return to_signed(- 65,10);
when x"40" => return to_signed(- 64,10);
when x"41" => return to_signed(- 63,10);
when x"42" => return to_signed(- 62,10);
when x"43" => return to_signed(- 61,10);
when x"44" => return to_signed(- 60,10);
when x"45" => return to_signed(- 59,10);
when x"46" => return to_signed(- 58,10);
when x"47" => return to_signed(- 57,10);
when x"48" => return to_signed(- 56,10);
when x"49" => return to_signed(- 55,10);
when x"4a" => return to_signed(- 54,10);
when x"4b" => return to_signed(- 53,10);
when x"4c" => return to_signed(- 52,10);
when x"4d" => return to_signed(- 51,10);
when x"4e" => return to_signed(- 50,10);
when x"4f" => return to_signed(- 49,10);
when x"50" => return to_signed(- 48,10);
when x"51" => return to_signed(- 47,10);
when x"52" => return to_signed(- 46,10);
when x"53" => return to_signed(- 45,10);
when x"54" => return to_signed(- 44,10);
when x"55" => return to_signed(- 43,10);
when x"56" => return to_signed(- 42,10);
when x"57" => return to_signed(- 41,10);
when x"58" => return to_signed(- 40,10);
when x"59" => return to_signed(- 39,10);
when x"5a" => return to_signed(- 38,10);
when x"5b" => return to_signed(- 37,10);
when x"5c" => return to_signed(- 36,10);
when x"5d" => return to_signed(- 35,10);
when x"5e" => return to_signed(- 34,10);
when x"5f" => return to_signed(- 33,10);
when x"60" => return to_signed(- 32,10);
when x"61" => return to_signed(- 31,10);
when x"62" => return to_signed(- 30,10);
when x"63" => return to_signed(- 29,10);
when x"64" => return to_signed(- 28,10);
when x"65" => return to_signed(- 27,10);
when x"66" => return to_signed(- 26,10);
when x"67" => return to_signed(- 25,10);
when x"68" => return to_signed(- 24,10);
when x"69" => return to_signed(- 23,10);
when x"6a" => return to_signed(- 22,10);
when x"6b" => return to_signed(- 21,10);
when x"6c" => return to_signed(- 20,10);
when x"6d" => return to_signed(- 19,10);
when x"6e" => return to_signed(- 18,10);
when x"6f" => return to_signed(- 17,10);
when x"70" => return to_signed(- 16,10);
when x"71" => return to_signed(- 15,10);
when x"72" => return to_signed(- 14,10);
when x"73" => return to_signed(- 13,10);
when x"74" => return to_signed(- 12,10);
when x"75" => return to_signed(- 11,10);
when x"76" => return to_signed(- 10,10);
when x"77" => return to_signed(- 9,10);
when x"78" => return to_signed(- 8,10);
when x"79" => return to_signed(- 7,10);
when x"7a" => return to_signed(- 6,10);
when x"7b" => return to_signed(- 5,10);
when x"7c" => return to_signed(- 4,10);
when x"7d" => return to_signed(- 3,10);
when x"7e" => return to_signed(- 2,10);
when x"7f" => return to_signed(- 1,10);
when x"80" => return to_signed( 0,10);
when x"81" => return to_signed( 1,10);
when x"82" => return to_signed( 2,10);
when x"83" => return to_signed( 3,10);
when x"84" => return to_signed( 4,10);
when x"85" => return to_signed( 5,10);
when x"86" => return to_signed( 6,10);
when x"87" => return to_signed( 7,10);
when x"88" => return to_signed( 8,10);
when x"89" => return to_signed( 9,10);
when x"8a" => return to_signed( 10,10);
when x"8b" => return to_signed( 11,10);
when x"8c" => return to_signed( 12,10);
when x"8d" => return to_signed( 13,10);
when x"8e" => return to_signed( 14,10);
when x"8f" => return to_signed( 15,10);
when x"90" => return to_signed( 16,10);
when x"91" => return to_signed( 17,10);
when x"92" => return to_signed( 18,10);
when x"93" => return to_signed( 19,10);
when x"94" => return to_signed( 20,10);
when x"95" => return to_signed( 21,10);
when x"96" => return to_signed( 22,10);
when x"97" => return to_signed( 23,10);
when x"98" => return to_signed( 24,10);
when x"99" => return to_signed( 25,10);
when x"9a" => return to_signed( 26,10);
when x"9b" => return to_signed( 27,10);
when x"9c" => return to_signed( 28,10);
when x"9d" => return to_signed( 29,10);
when x"9e" => return to_signed( 30,10);
when x"9f" => return to_signed( 31,10);
when x"a0" => return to_signed( 32,10);
when x"a1" => return to_signed( 33,10);
when x"a2" => return to_signed( 34,10);
when x"a3" => return to_signed( 35,10);
when x"a4" => return to_signed( 36,10);
when x"a5" => return to_signed( 37,10);
when x"a6" => return to_signed( 38,10);
when x"a7" => return to_signed( 39,10);
when x"a8" => return to_signed( 40,10);
when x"a9" => return to_signed( 41,10);
when x"aa" => return to_signed( 42,10);
when x"ab" => return to_signed( 43,10);
when x"ac" => return to_signed( 44,10);
when x"ad" => return to_signed( 45,10);
when x"ae" => return to_signed( 46,10);
when x"af" => return to_signed( 47,10);
when x"b0" => return to_signed( 48,10);
when x"b1" => return to_signed( 49,10);
when x"b2" => return to_signed( 50,10);
when x"b3" => return to_signed( 51,10);
when x"b4" => return to_signed( 52,10);
when x"b5" => return to_signed( 53,10);
when x"b6" => return to_signed( 54,10);
when x"b7" => return to_signed( 55,10);
when x"b8" => return to_signed( 56,10);
when x"b9" => return to_signed( 57,10);
when x"ba" => return to_signed( 58,10);
when x"bb" => return to_signed( 59,10);
when x"bc" => return to_signed( 60,10);
when x"bd" => return to_signed( 61,10);
when x"be" => return to_signed( 62,10);
when x"bf" => return to_signed( 63,10);
when x"c0" => return to_signed( 64,10);
when x"c1" => return to_signed( 65,10);
when x"c2" => return to_signed( 66,10);
when x"c3" => return to_signed( 67,10);
when x"c4" => return to_signed( 68,10);
when x"c5" => return to_signed( 69,10);
when x"c6" => return to_signed( 70,10);
when x"c7" => return to_signed( 71,10);
when x"c8" => return to_signed( 72,10);
when x"c9" => return to_signed( 73,10);
when x"ca" => return to_signed( 74,10);
when x"cb" => return to_signed( 75,10);
when x"cc" => return to_signed( 76,10);
when x"cd" => return to_signed( 77,10);
when x"ce" => return to_signed( 78,10);
when x"cf" => return to_signed( 79,10);
when x"d0" => return to_signed( 80,10);
when x"d1" => return to_signed( 81,10);
when x"d2" => return to_signed( 82,10);
when x"d3" => return to_signed( 83,10);
when x"d4" => return to_signed( 84,10);
when x"d5" => return to_signed( 85,10);
when x"d6" => return to_signed( 86,10);
when x"d7" => return to_signed( 87,10);
when x"d8" => return to_signed( 88,10);
when x"d9" => return to_signed( 89,10);
when x"da" => return to_signed( 90,10);
when x"db" => return to_signed( 91,10);
when x"dc" => return to_signed( 92,10);
when x"dd" => return to_signed( 93,10);
when x"de" => return to_signed( 94,10);
when x"df" => return to_signed( 95,10);
when x"e0" => return to_signed( 96,10);
when x"e1" => return to_signed( 97,10);
when x"e2" => return to_signed( 98,10);
when x"e3" => return to_signed( 99,10);
when x"e4" => return to_signed( 100,10);
when x"e5" => return to_signed( 101,10);
when x"e6" => return to_signed( 102,10);
when x"e7" => return to_signed( 103,10);
when x"e8" => return to_signed( 104,10);
when x"e9" => return to_signed( 105,10);
when x"ea" => return to_signed( 106,10);
when x"eb" => return to_signed( 107,10);
when x"ec" => return to_signed( 108,10);
when x"ed" => return to_signed( 109,10);
when x"ee" => return to_signed( 110,10);
when x"ef" => return to_signed( 111,10);
when x"f0" => return to_signed( 112,10);
when x"f1" => return to_signed( 113,10);
when x"f2" => return to_signed( 114,10);
when x"f3" => return to_signed( 115,10);
when x"f4" => return to_signed( 116,10);
when x"f5" => return to_signed( 117,10);
when x"f6" => return to_signed( 118,10);
when x"f7" => return to_signed( 119,10);
when x"f8" => return to_signed( 120,10);
when x"f9" => return to_signed( 121,10);
when x"fa" => return to_signed( 122,10);
when x"fb" => return to_signed( 123,10);
when x"fc" => return to_signed( 124,10);
when x"fd" => return to_signed( 125,10);
when x"fe" => return to_signed( 126,10);
when x"ff" => return to_signed( 127,10);
when others => return to_signed( 0,10);
end case;
end u8tos10;
signal vmix_reg : s10;
signal vmix_m16 : word;
begin
r0w1 <= not r1w0;
clk1m <= ph2;
v1_freq <= u8(sid_regs(1)) & u8(sid_regs(0));
v1_pw <= u4(sid_regs(3)(3 downto 0)) & u8(sid_regs(2));
v2_freq <= u8(sid_regs(8)) & u8(sid_regs(7));
v2_pw <= u4(sid_regs(10)(3 downto 0)) & u8(sid_regs(9));
v3_freq <= u8(sid_regs(15)) & u8(sid_regs(14));
v3_pw <= u4(sid_regs(17)(3 downto 0)) & u8(sid_regs(16));
filter_fc <= u8(sid_regs(22)) & u3(sid_regs(21)(2 downto 0));
voice_1: sid_voice port map (
clk1m => clk1m,
freq => v1_freq,
pw => v1_pw,
wvfm => v1_wvfm,
test => v1_test,
rmod => v1_ring,
sync => v1_sync,
gate => v1_gate,
enva => u4(v1_enva),
envd => u4(v1_envd),
envs => u4(v1_envs),
envr => u4(v1_envr),
envo => v1_envo,
osco => v1_osco,
uout => v1_out
);
voice_2: sid_voice port map (
clk1m => clk1m,
freq => v2_freq,
pw => v2_pw,
wvfm => v2_wvfm,
test => v2_test,
rmod => v2_ring,
sync => v2_sync,
gate => v2_gate,
enva => u4(v2_enva),
envd => u4(v2_envd),
envs => u4(v2_envs),
envr => u4(v2_envr),
envo => v2_envo,
osco => v2_osco,
uout => v2_out
);
voice_3: sid_voice port map (
clk1m => clk1m,
freq => v3_freq,
pw => v3_pw,
wvfm => v3_wvfm,
test => v3_test,
rmod => v3_ring,
sync => v3_sync,
gate => v3_gate,
enva => u4(v3_enva),
envd => u4(v3_envd),
envs => u4(v3_envs),
envr => u4(v3_envr),
envo => v3_envo,
osco => v3_osco,
uout => v3_out
);
hold_mix: process(clk1M, mute3, v1_out, v2_out, v3_out) is
variable v1s : s10;
variable v2s : s10;
variable v3s : s10;
variable vpair : s10;
begin
--v1s := s10("00" & v1_out) - 128;
--v2s := s10("00" & v2_out) - 128;
--v3s := s10("00" & v3_out) - 128;
v1s := u8tos10(v1_out);
v2s := u8tos10(v2_out);
v3s := u8tos10(v3_out);
vpair := v1s + v2s;
if (rising_edge(clk1M)) then
if (mute3 = '1') then
vmix_reg <= vpair;
else
vmix_reg <= vpair + v3s;
end if;
end if;
end process hold_mix;
scaler: ccm_85 port map(
clk => clk1M,
a => slv10(vmix_reg),
p => vmix_m16
);
audio: process(clk1m, vmix_m16) is
--variable s20tmp : s20;
begin
--s20tmp := vmix_reg*85;
if (rising_edge(clk1m)) then
--s16audio <= s20tmp(15 downto 0);
s16audio <= s16(vmix_m16);
end if;
end process audio;
reg_rd: process(ph2, rga, sid_regs, v3_osco, v3_envo) is
variable rdata : byte;
begin
case "000" & rga is
when x"19" => rdata := sid_regs(25);
when x"1a" => rdata := sid_regs(26);
when x"1b" => rdata := byte(v3_osco);
when x"1c" => rdata := byte(v3_envo(7 downto 0));
when others => rdata := "11111111";
end case;
if (rising_edge(ph2)) then
dout <= rdata;
end if;
end process reg_rd;
reg_wr: process(ph2, rga, r1w0, din) is
begin
if (falling_edge(ph2)) then
if ((("000"&rga) < x"19") and (r0w1 = '1')) then
sid_regs(to_integer(unsigned(rga))) <= din;
end if;
end if;
end process reg_wr;
end sid_impl;
| gpl-3.0 | 4aa22618eed348240622e6111ec77266 | 0.495995 | 2.806619 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/core.vhd | 1 | 38,530 | ----------------------------------------------------------------------------------
-- Engineer: Longofono Modified by Avalos
--
-- Create Date: 02/10/2018 06:05:22 PM
-- Module Name: simpler_core - Behavioral
-- Description: Even Simpler version of the ALU pipeline for HW testing
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
library unisim;
use unisim.VCOMPONENTS.ALL;
entity simpler_core is
Port(
status: out std_logic; -- LED blinkenlites
CLK: in std_logic; -- Tied to switch V10
RST: in std_logic; -- Tied to switch J15
LED: out std_logic_vector(15 downto 0);
PC_Switch: in std_logic;
ALU_Switch: in std_logic;
ROM_Switch: in std_logic_vector(1 downto 0);
UART_Switch: in std_logic;
-- UART Serial I/O
UART_RXD: in std_logic;
UART_TXD: out std_logic;
-- DDR2 signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
--ROM signals
dq: inout STD_LOGIC_VECTOR(3 downto 0);
cs_n: out STD_LOGIC
);
end simpler_core;
architecture Behavioral of simpler_core is
-- Component instantiation
component ALU is
port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
halt: in std_logic; -- Do nothing
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end component;
component fence is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
halt: in std_logic; -- Do nothing when high
ready_input: in std_logic; -- Control has data to be written back
ready_output: in std_logic; -- MMU is ready to accept data
output_OK: out std_logic; -- Write data and address are valid
input_OK: out std_logic; -- Read data and address recorded
input_data: in doubleword; -- Data from previous stage
input_address: in doubleword; -- MMU Destination for input data
output_data: out doubleword; -- Data to be written to MMU
output_address: out doubleword -- MMU destination for output data
);
end component;
component decode is
Port(
instr : in std_logic_vector(63 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20)
);
end component;
component regfile is
Port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end component;
component mux is
Port(
sel: in std_logic; -- Select from zero, one ports
zero_port: in doubleword; -- Data in, zero select port
one_port: in doubleword; -- Data in, one select port
out_port: out doubleword -- Output data
);
end component;
component sext is
Port(
imm12: in std_logic_vector(11 downto 0);
imm20: in std_logic_vector(19 downto 0);
output_imm12: out std_logic_vector(63 downto 0);
output_imm20: out std_logic_vector(63 downto 0)
);
end component;
component MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic;
addr_in: in doubleword;
data_in: in doubleword;
satp: in doubleword;
-- mode: in std_logic_vector(1 downto 0); -- Machine mode, user mode, hypervisor mode or machine mode
store: in std_logic;
load: in std_logic;
busy: out std_logic;
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
ready_instr: in std_logic;
addr_instr: in doubleword;
alignment: in std_logic_vector(3 downto 0);
data_out: out doubleword;
instr_out: out word;
error: out std_logic_vector(5 downto 0);
LED: out std_logic_vector(15 downto 0);
-- debug_MEM: out doubleword; -- Dummy register that will be written to
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- UART
UART_RXD: in std_logic;
UART_TXD: out std_logic;
-- Debug Signals
-- ROM
sck: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0);
cs_n: out STD_LOGIC);
end component;
component Debug_Controller is
Port (clk,rst: in STD_LOGIC;
halt: out STD_LOGIC;
REGGIE: in regfile_arr;
PC_IN: in doubleword;
uart_rxd : in STD_LOGIC;
uart_txd : out STD_LOGIC);
end component;
-- Signals and constants
-- Feedback signals
signal s_rst: std_logic; -- internal reset
signal s_halts: std_logic_vector(2 downto 0); -- IM, REG, ALU halt signals
signal s_ALU_op: ctrl_t; -- ALU operation control
signal s_request_IM_in: std_logic; -- Signal pending write to IM
signal s_request_IM_inack: std_logic; -- Acknowledge above write handled
signal s_request_IM_out: std_logic; -- Signal ready for instruction
signal s_request_IM_outack: std_logic; -- Acknowledge instruction data is fresh
signal s_wb_select: std_logic; -- Select from ALU result or MMU data to Regfile write
signal s_PC_next: doubleword; -- Next PC address
signal s_PC_curr: doubleword; -- Preserves current PC for jumps
signal s_MMU_store: std_logic; -- Signal MMU to store
signal s_MMU_load: std_logic; -- Signal MMU to load
signal s_MMU_busy: std_logic; -- MMU is loading, storing, or fetching
signal s_ATU_busy: std_logic; -- Atomic unit is doing its thing
signal s_ATU_stage:std_logic; -- After resuming, need to know what stage of atomic instruction we are in
signal s_ALU_source_select: std_logic_vector(1 downto 0); -- Switch in immediate values
-- Decoded instruction parts
signal s_instr_code: instr_t; -- Exact instruction encoding
signal s_opcode: opcode_t; -- Opcode category abstraction
signal s_rs1: reg_t; -- Regfile read address
signal s_rs2: reg_t; -- Regfile read address
signal s_rs3: reg_t; -- Regfile read address
signal s_rd: reg_t; -- Regfile write address
signal s_shamt: std_logic_vector(4 downto 0); -- Shift amount, immediate shifts
signal s_imm12: std_logic_vector(11 downto 0); -- Immediate value, 12 bit style
signal s_imm20: std_logic_vector(19 downto 0); -- Immediate value, 20 bit style
signal s_csr_bits: std_logic_vector(11 downto 0); -- CSR address for CSR instructions
signal s_functs: std_logic_vector(15 downto 0); -- Holds concatenation of funct3, funct6, funct7
-- ALU connectors
signal s_ALU_input2: doubleword;
signal s_ALU_result: doubleword;
signal s_ALU_Error: std_logic_vector(2 downto 0);
-- Instruction memory connectors
signal s_IM_input_addr: doubleword;
signal s_IM_input_data: doubleword;
signal s_IM_output_addr: doubleword;
signal s_IM_output_data: doubleword;
-- Register file connectors
signal s_REG_raddr1: reg_t;
signal s_REG_raddr2: reg_t;
signal s_REG_rdata1: doubleword;
signal s_REG_rdata2: doubleword;
signal s_REG_wdata: doubleword;
signal s_REG_waddr: reg_t;
signal s_REG_write: std_logic;
signal s_REG_error: std_logic;
signal s_REG_debug: regfile_arr;
-- MMU connectors
signal s_MMU_input_addr: doubleword := (others => '0');
signal s_MMU_input_data: doubleword;
signal s_MMU_alignment: std_logic_vector(3 downto 0); -- One-hot selection in bytes
signal s_MMU_output_data: doubleword;
signal s_MMU_output_instr: doubleword;
signal s_MMU_error: std_logic_vector(5 downto 0);
signal s_MMU_instr_out: word;
signal s_MMU_fetch: std_logic;
signal s_MMU_LED: std_logic_vector(15 downto 0);
signal s_MMU_satp: doubleword := (others => '0');
signal s_MMU_mode: std_logic_vector(1 downto 0); -- Machine mode, user mode, hypervisor mode or machine mode
signal s_MMU_UART_RXD, s_MMU_UART_TXD: std_logic;
signal d_clk: std_logic := '0';
-- Jump and branch connectors
signal s_wb_to_jal: doubleword; -- Connects output of mem/alu wb mux to input of jump mux
signal s_jump_select: std_logic; -- Select from output of mem/alu mux or jump address data
signal s_jump_wdata: doubleword; -- Data representing the jump return address or AUIPC result
--signal s_jump_target: doubleword; -- Address of the jump targer
--signal s_jump_sext: doubleword; -- Intermediate helper variable for clarity's sake
-- Others
signal s_sext_12: doubleword; -- Sign extended immediate value
signal s_sext_20: doubleword; -- Sign extended immediate value
signal privilege_mode: std_logic_vector(1 downto 0) := MACHINE_MODE;
signal counter_sc: integer := 0;
signal debugger_step: std_logic;
-- Debug
signal fkuck_vivado_so_much: std_logic_vector(5 downto 0);
signal s_internal_address_out: doubleword;
-- Load/Store connectors
-- Changing these signals to variables to avoid losing time
--signal s_load_base: doubleword; -- Base address from regfile
--signal s_load_offset: doubleword; -- Offset from sext(imm12 value)
--signal s_store_base: doubleword; -- Base address from regfile
--signal s_store_offset: doubleword; -- Offset from sext(imm12 value)
signal s_load_type : std_logic_vector(7 downto 0); -- Record type so we can properly extend later
signal s_load_dest : reg_t; -- Record rd so we can access it later
signal s_load_wb_data: doubleword; -- Extended data to be written back to regfile
-- High-level states of operation (distinct from modes)
type state is (fetching, fetching_wait, regs, alus,load_store, mem, wb, done);
signal curr_state, next_state: state := fetching;
signal stupid_fucking_vivado: std_logic_vector(5 downto 0);
signal s_DEBUG_UART_TXD, s_DEBUG_UART_RXD: std_logic;
-- Control status registers followed by scratch
type CSR_t is array (0 to 64) of doubleword;
signal CSR: CSR_t;
signal shifterCounter: integer := 0;
-- Exception flags
-- From privilege specification: MSB 1 => asynchronous, MSB 0 => synchronous
-- Remaining bits are binary-encoded exception code
signal exceptions: std_logic_vector(4 downto 0) := (others => '0');
-- in order to act appropriately on CSr exceptions, drive and track them separately
signal csr_exceptions: std_logic := '0';
signal exception_offending_instr : instr_t := (others => '0');
signal s_decode_instruction: doubleword;
-- If in waiting state, reason determines actions on exit
signal waiting_reason: std_logic_vector(2 downto 0);
signal gated_clock: std_logic;
begin
-- Component instantiations and mapping
myDecode: decode
port map(
instr => s_decode_instruction,
instr_code => s_instr_code,
funct3 => s_functs(15 downto 13),
funct6 => s_functs(12 downto 7),
funct7 => s_functs(6 downto 0),
imm12 => s_imm12,
imm20 => s_imm20,
opcode => s_opcode,
rs1 => s_rs1,
rs2 => s_rs2,
rs3 => s_rs3,
rd => s_rd,
shamt => s_shamt,
csr => s_csr_bits
);
myALU: ALU
port map(
clk => clk,
rst => s_rst,
halt => s_halts(0),
ctrl => s_instr_code,
rs1 => s_REG_rdata1,
rs2 => s_ALU_input2,
shamt => s_shamt,
rout => s_ALU_result,
error => s_ALU_error(2),
overflow => s_ALU_error(1),
zero => s_ALU_error(0)
);
--WBMux: mux
-- port map(
-- sel => s_WB_select,
-- zero_port => s_ALU_result,
-- one_port => s_load_wb_data,
-- out_port => s_wb_to_jal
--);
--JumpReturn: mux
-- port map(
-- sel => s_jump_select,
-- zero_port => s_wb_to_jal,
-- one_port => s_jump_wdata,
-- out_port => s_REG_wdata
--);
--ALUMux: mux
-- port map(
-- sel => s_ALU_source_select,
-- zero_port => s_REG_rdata2,
-- one_port => s_sext_12,
-- out_port => s_ALU_input2
-- );
-- Muxes
s_REG_wdata <= s_ALU_result when s_WB_select = '0' and s_jump_select = '0' else s_load_wb_data when s_WB_select = '1' and s_jump_select = '0' else s_jump_wdata when s_WB_select = '0' and s_jump_select = '1';
--s_wb_to_jal <= s_ALU_result when s_WB_select = '0' else s_load_wb_data;
--s_REG_wdata <= s_wb_to_jal when s_jump_select = '0' else s_jump_wdata;
s_ALU_input2 <= s_REG_rdata2 when s_ALU_source_select = "00" else s_sext_12 when s_ALU_source_select = "01" else s_sext_20;
myMMU: MMU port map
(
clk => CLK,
rst => s_rst,
addr_in => s_MMU_input_addr,
data_in => s_MMU_input_data,
satp => s_MMU_satp,
mode => s_MMU_mode,
store => s_MMU_store,
load => s_MMU_load,
busy => s_MMU_busy,
ready_instr => s_MMU_fetch,
addr_instr => s_PC_curr,
alignment => s_MMU_alignment,
data_out => s_MMU_output_data,
instr_out => s_MMU_instr_out,
error => s_MMU_error,
UART_RXD => UART_RXD,
UART_TXD => s_MMU_UART_txd,
LED => s_MMU_LED,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
-- Debug Signals
sck => gated_clock,
cs_n => cs_n,
dq => dq
);
myDebug: Debug_Controller
port map(
clk => clk,
rst => rst,
reggie => s_REG_debug,
PC_IN => s_PC_curr,
halt => d_clk,
uart_rxd => s_DEBUG_UART_RXD,
uart_txd => s_DEBUG_UART_TXD
);
myREG: regfile
port map(
clk => clk,
rst => s_rst,
read_addr_1 => s_REG_raddr1,
read_addr_2 => s_REG_raddr2,
write_addr => s_REG_waddr,
write_data => s_REG_wdata,
halt => s_halts(1),
write_en => s_REG_write,
read_data_1 => s_REG_rdata1,
read_data_2 => s_REG_rdata2,
write_error => s_REG_error,
debug_out => s_REG_debug
);
mySext: sext
port map(
imm12 => s_imm12,
imm20 => s_imm20,
output_imm12 => s_sext_12,
output_imm20 => s_sext_20
);
advance_state: process(clk,rst, next_state) begin
if(rst = '1') then
curr_state <= fetching;
if(PC_Switch = '0') then
s_PC_curr <= (others => '0');
else
s_PC_curr <= x"0000000090000000";
end if;
elsif(rising_edge(clk)) then
curr_state <= next_state;
if(curr_state = done) then
s_PC_curr <= s_PC_next;
end if;
end if;
end process;
process(clk, rst, curr_state, next_state)
variable s_store_offset, s_load_offset, s_load_base, s_store_base, s_jump_target, s_jump_sext: doubleword;
begin
if(rst = '1') then
next_state <= fetching;
s_rst <= '1';
s_REG_write <= '0';
s_MMU_fetch <= '0';
s_MMU_store <= '0';
s_MMU_load <= '0';
s_halts <= "000";
s_wb_select <= '0';
counter_sc <= 0;
s_ALU_source_select <= "00";
elsif(rising_edge(clk)) then
case curr_state is
when fetching =>
stupid_fucking_vivado <= "000000";
s_PC_next <= std_logic_vector(unsigned(s_PC_curr) + 4);
s_MMU_fetch <= '1';
s_MMU_store <= '0';
s_MMU_load <= '0';
s_REG_write <= '0';
s_halts <= "000";
s_rst <= '0';
s_jump_select <= '0';
s_wb_select <= '0';
next_state <= fetching_wait;
-- if(d_clk = '1') then
-- next_state <= fetching_wait;
-- else
-- next_state <= fetching;
-- end if;
when fetching_wait =>
next_state <= fetching_wait;
stupid_fucking_vivado <= "000001";
s_MMU_fetch <= '0';
if(s_MMU_busy = '0') then
next_state <= regs;
s_decode_instruction <= zero_word & s_MMU_instr_out;
end if;
when regs =>
stupid_fucking_vivado <= "000010";
next_state <= alus;
when alus =>
stupid_fucking_vivado <= "000011";
next_state <= mem;
case s_opcode is
when ALU_T => -- Case regular, R-type ALU operations
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_raddr2 <= s_rs2;
s_REG_waddr <= s_rd;
-- s_REG_write <= '0';
s_REG_write <= '1';
-- Use rdata2 instead of sign extended immediate
s_ALU_source_select <= "00";
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when LUI_T =>
s_REG_raddr1 <= s_rs1;
s_REG_waddr <= s_rd;
--s_REG_write <= '1';
s_ALU_source_select <= "11";
s_wb_select <= '0';
s_REG_write <= '1';
-- next_state <= wb;
when ALUIW_T =>
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_waddr <= s_rd;
next_state <= wb;
-- s_REG_write <= '1';
-- Use sign extended immediate instead of rdata2
s_ALU_source_select <= "01";
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when ALUI_T => -- Case regular, I-type ALU operations
-- REG signals
s_REG_raddr1 <= s_rs1;
s_REG_waddr <= s_rd;
next_state <= wb;
-- s_REG_write <= '1';
-- Use sign extended immediate instead of rdata2
s_ALU_source_select <= "01";
-- Use ALU result instead of MMU data
s_wb_select <= '0';
when LOAD_T =>
-- Little endian byte ordering
-- Need to signal MMU: full word, half word, quarter word
-- effective address is sext(regFile[rs1]) + sext(imm12)
case s_instr_code is
when instr_LB =>
s_MMU_alignment <= "0001";
s_load_type <= instr_LB;
when instr_LBU =>
s_MMU_alignment <= "0001";
s_load_type <= instr_LBU;
when instr_LH =>
s_MMU_alignment <= "0010";
s_load_type <= instr_LH;
when instr_LHU =>
s_MMU_alignment <= "0010";
s_load_type <= instr_LHU;
when instr_LW =>
s_MMU_alignment <= "0100";
s_load_type <= instr_LW;
when instr_LWU =>
s_MMU_alignment <= "0100";
s_load_type <= instr_LWU;
when others =>
s_MMU_alignment <= "1000";
s_load_type <= instr_LD;
end case;
s_load_base := s_REG_debug(to_integer(unsigned(s_rs1)));
if('0' = s_imm12(11)) then
s_load_offset := zero_word & "00000000000000000000" & s_imm12;
--s_load_offset <= zero_word & "00000000000000000000" & s_imm12;
else
s_load_offset := ones_word & "11111111111111111111" & s_imm12;
--s_load_offset <= ones_word & "11111111111111111111" & s_imm12;
end if;
s_load_dest <= s_rd;
s_MMU_input_addr <= std_logic_vector(signed(s_load_base) + signed(s_load_offset));
--s_MMU_load <= '1';
waiting_reason <= "001";
next_state <= load_store;
when STORE_T =>
-- Little endian byte ordering
s_store_base := s_REG_debug(to_integer(unsigned(s_rs1)));
if('0' = s_imm12(11)) then
s_store_offset := zero_word & "00000000000000000000" & s_imm12;
else
s_store_offset := ones_word & "11111111111111111111" & s_imm12;
end if;
--s_MMU_input_addr <= std_logic_vector(signed(s_load_base) + signed(s_load_offset));
s_MMU_input_addr <= std_logic_vector(signed(s_store_base) + signed(s_store_offset));
case s_instr_code is
when instr_SB =>
s_MMU_input_data <= byte_mask_1 and s_REG_debug(to_integer(unsigned(s_rs2)));
when instr_SH =>
s_MMU_input_data <= byte_mask_2 and s_REG_debug(to_integer(unsigned(s_rs2)));
when instr_SW =>
s_MMU_input_data <= byte_mask_4 and s_REG_debug(to_integer(unsigned(s_rs2)));
when others => -- store doubleword
s_MMU_input_data <= s_REG_debug(to_integer(unsigned(s_rs2)));
end case;
--s_MMU_store <= '1';
next_state <= load_store;
when BRANCH_T =>
case s_instr_code is
when instr_BEQ =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) = signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when instr_BNE =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) /= signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when instr_BLT =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) < signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when instr_BGE =>
if(signed(s_REG_debug(to_integer(unsigned(s_rs1)))) >= signed(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when instr_BLTU =>
if(unsigned(s_REG_debug(to_integer(unsigned(s_rs1)))) < unsigned(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
when others => --instr_BGEU
if(unsigned(s_REG_debug(to_integer(unsigned(s_rs1)))) >= unsigned(s_REG_debug(to_integer(unsigned(s_rs2))))) then
if('0' = s_imm12(11)) then
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(zero_word & "0000000000000000000" & s_imm12 & '0')));
else
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(std_logic_vector'(ones_word & "1111111111111111111" & s_imm12 & '0')));
end if;
end if;
end case;
when JAL_T =>
s_jump_select <= '1'; -- switch in jal write data
s_REG_waddr <= s_rd; -- TODO may be problems since rd could be omitted (pp. 152-3)
s_jump_wdata <= s_PC_next;
if('0' = s_imm20(19)) then
s_jump_target := zero_word & "00000000000" & s_imm20 & "0";
else
s_jump_target := ones_word & "11111111111" & s_imm20 & "0";
end if;
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(s_jump_target));
when JALR_T =>
s_jump_select <= '1'; -- switch in jal write data
s_REG_waddr <= s_rd; -- TODO may be problems since rd could be omitted (pp. 152-3)
s_jump_wdata <= s_PC_next;
if('0' = s_imm12(11)) then
-- note type hinting again
-- note wonky ".. set low bit of result to '0' ..."
s_jump_sext := zero_word & "00000000000000000000" & s_imm12;
s_jump_target := std_logic_vector(
signed(s_REG_debug(to_integer(unsigned(s_rs1)))) +
signed(s_jump_sext)
);
s_jump_target(0) := '0';
else
-- note type hinting again
-- note wonky ".. set low bit of result to '0' ..."
s_jump_sext := ones_word & "11111111111111111111" & s_imm12;
s_jump_target := std_logic_vector(
signed(s_REG_debug(to_integer(unsigned(s_rs1)))) +
signed(s_jump_sext)
);
s_jump_target(0) := '0';
end if;
s_PC_next <= std_logic_vector(signed(s_PC_curr) + signed(s_jump_target));
when AUIPC_T =>
s_jump_select <= '1';
s_REG_waddr <= s_rd;
next_state <= wb;
if('0' = s_imm20(19)) then
s_jump_wdata <= std_logic_vector(
signed(s_PC_curr) +
signed(std_logic_vector'( zero_word & s_imm20 & "000000000000" ))
);
else
s_jump_wdata <= std_logic_vector(
signed(s_PC_curr) +
signed(std_logic_vector'( ones_word & s_imm20 & "000000000000" ))
); end if;
when others =>
end case;
when load_store =>
next_state <= mem;
if(s_OPCODE = LOAD_T) then
s_MMU_load <= '1';
elsif(s_OPCODE = STORE_T) then
s_MMU_store <= '1';
end if;
when mem =>
next_state <= mem;
stupid_fucking_vivado <= "000100";
s_REG_write <= '0';
s_MMU_store <= '0';
s_MMU_load <= '0'; --Reset these suckers
if(s_mmu_busy = '0') then
if(s_opcode = LOAD_T) then
s_wb_select <= '1';
next_state <= wb;
s_REG_waddr <= s_load_dest;
-- These are the special cases for the writebacks
case s_load_type is
when instr_LB =>
if('0' = s_MMU_output_data(7)) then
s_load_wb_data <= zero_word & "000000000000000000000000" & s_MMU_output_data(7 downto 0);
else
s_load_wb_data <= ones_word & "111111111111111111111111" & s_MMU_output_data(7 downto 0);
end if;
when instr_LBU =>
s_load_wb_data <= zero_word & "000000000000000000000000" & s_MMU_output_data(7 downto 0);
when instr_LH =>
if('0' = s_MMU_output_data(7)) then
s_load_wb_data <= zero_word & "0000000000000000" & s_MMU_output_data(15 downto 0);
else
s_load_wb_data <= ones_word & "1111111111111111" & s_MMU_output_data(15 downto 0);
end if;
when instr_LHU =>
s_load_wb_data <= zero_word & "0000000000000000" & s_MMU_output_data(15 downto 0);
when instr_LW =>
if('0' = s_MMU_output_data(31)) then
s_load_wb_data <= zero_word & s_MMU_output_data(31 downto 0);
else
s_load_wb_data <= ones_word & s_MMU_output_data(31 downto 0);
end if;
when instr_LWU =>
s_load_wb_data <= zero_word & s_MMU_output_data(31 downto 0);
when others =>
s_load_wb_data <= s_MMU_output_data;
end case;
else
next_state <= done;
end if;
end if;
when wb =>
next_state <= wb;
next_state <= done;
s_REG_write <= '1';
stupid_fucking_vivado <= "000101";
-- shifterCounter <= shifterCounter + 1;
-- if(shifterCounter > 2) then
-- s_REG_write <= '1';
-- next_state <= done;
-- shifterCounter <= 0;
-- end if;
when done =>
counter_sc <= 0;
s_jump_select <= '0';
s_REG_write <= '0';
if(debugger_step = '0') then
next_state <= fetching;
else
next_state <= done;
end if;
--pragma synthesis off
next_state <= fetching;
--pragma synthesis on
stupid_fucking_vivado <= "000110";
when others =>
stupid_fucking_vivado <= "000111";
next_state <= fetching;
end case;
end if;
end process;
s_MMU_satp <= (others => '0');
status <= s_MMU_busy;
--s_IM_input_data <= s_MMU_instr_out;
--LED(15 downto 9) <= s_opcode;
--LED(8 downto 0) <= s_MMU_LED(8 downto 0);
UART_TXD <= s_MMU_UART_TXD when UART_Switch = '1' else s_DEBUG_UART_TXD;
debugger_step <= '0' when UART_Switch ='1' else d_clk;
LED <= s_MMU_LED;
--process(clk) begin
-- if(rising_edge(clk)) then
-- if(ALU_Switch = '1') then
-- case ROM_Switch is
-- when "00" => LED <= s_MMU_instr_out(15 downto 0);
-- when "01" => LED <= s_MMU_LED;
-- when "10" => LED <= s_ALU_result(15 downto 0);
-- when "11" => LED <= s_ALU_result(31 downto 16);
-- when others => --what
-- end case;
-- else
-- LED <= s_MMU_LED;
-- end if;
-- end if;
--end process;
end Behavioral;
| mit | cea47af382facea612b894999d213c06 | 0.472307 | 3.910484 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/debug_controller.vhd | 1 | 26,308 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/31/2017 03:31:33 PM
-- Design Name:
-- Module Name: Debug_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity Debug_Controller is
port (clk,RST: in STD_LOGIC;
HALT: out STD_LOGIC;
REGGIE: in regfile_arr;
PC_IN: in doubleword;
UART_RXD: in STD_LOGIC;
UART_TXD : out STD_LOGIC);
end Debug_Controller;
architecture Behavioral of Debug_Controller is
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
-- Types
type CHAR_ARRAY is array (integer range<>) of std_logic_vector(7 downto 0);
type UART_STATE_TYPE is (IDLE, RECEIVE, UNPAUSE, DECODE, REGISTERS, PC, STEP, STEP_HI, STEP_LO, SEND_CHAR, REGFILE, REGFILE_I, SEND_CHAR_2, SEND_CHAR_3, SEND_CHAR_4, WAIT_CHAR, KEEP_WAITING_CHAR, LD_REGISTERS_STR, RESET_LO, RESET_HI);
type BOUNDS is array (integer range<>) of integer;
-- Constants
constant MAX_STR_LEN : integer := 501;
constant MAX_REGISTER_LEN : integer := 23;
constant RESET_CNTR_MAX : std_logic_vector(17 downto 0) := "110000110101000000";-- 100,000,000 * 0.002 = 200,000 = clk cycles per 2 ms
-- Signals
signal uart_curr_state, uart_next_state : UART_STATE_TYPE := idle;
signal uartRdy, uartSend ,uartTX: std_logic;
signal uartData: std_logic_vector(7 downto 0);
signal sendStr : CHAR_ARRAY(0 to (MAX_STR_LEN - 1)) := ( others => (others => '0'));
signal reset_cntr : std_logic_vector (17 downto 0) := (others=>'0');
-- String counters
signal reggie_counter : integer := 0;
signal reggie_str_counter : integer := 12;
signal reggie_counter_counter : integer := 0;
signal strEnd, strIndex: natural := 0;
signal strConcatCtr: integer := 0;
signal pc_str_counter: integer := 0;
signal pc_reg: doubleword := (others => '0');
-- CPU halt interface
signal halt_l : std_logic := '1';
-- UART RX and TX signals
signal uart_data_in: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal data_available, reset_read: STD_LOGIC;
signal rx_str : CHAR_ARRAY(30 DOWNTO 0);
signal rx_str_ctr : integer := 0;
signal d_clk: std_logic := '0';
begin
DEBUG_UART_TX: UART_TX_CTRL port map(SEND => uartSend,
DATA => uartData,
CLK => CLK,
READY => uartRdy,
UART_TX => UART_TXD );
DEBUG_UART_RX: UART_RX_CTRL
port map(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => data_available,
RESET_READ => reset_read
);
--State Machine transition
DEBUG_FSM: process(clk, rst) begin
if(rst = '1') then
uart_curr_state <= IDLE;
elsif(rising_edge(clk)) then
uart_curr_state <= uart_next_state;
end if;
end process;
HALT <= halt_l;
-- Generate the debug clock d_clk
D_CLK_GEN: process(clk) begin
if(rising_edge(clk)) then
if(halt_l = '0') then
d_clk <= d_clk xor '1';
end if;
end if;
end process;
DEBUG_FSM_TRANSITION: process(clk, rst)
variable internal_register_int: integer;
variable has_r_been_pressed_yet: integer;
begin
if(rst = '1') then
strConcatCtr <= 0;
reggie_str_counter <= 0;
reset_read <= '1';
uart_next_state <= IDLE;
strIndex <= 0;
halt_l <= '1';
has_r_been_pressed_yet := 0;
elsif(rising_edge(clk)) then
case uart_curr_state is
-- State IDLE: Nothing happening
when IDLE =>
reggie_counter_counter <= 0;
reggie_str_counter <= 0;
strConcatCtr <= 0;
strEnd <= 25;
uartSend <= '0';
strIndex <= 0;
reset_read <= '0';
reggie_counter <= 0;
pc_str_counter <= 0;
uart_next_state <= IDLE;
-- Default go to IDLE
if(data_available = '1' AND uartRdy = '1' ) then -- If we have data and not outputing anything
rx_str(0) <= uart_data_in; -- Save the data
uart_next_state <= DECODE;
end if;
-- State DECODE: Decode what function the user is accessing
when DECODE =>
if(rx_str(0) = X"72") then
uart_next_state <= REGFILE;
reggie_counter <= 0;
strEnd <= 500;
elsif(rx_str(0) = X"30") then
internal_register_int := 0;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"31") then
internal_register_int := 12;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"32") then
internal_register_int := 13;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"33") then
internal_register_int := 14;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"34") then
internal_register_int := 15;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"73") then
uart_next_state <= STEP;
elsif(rx_str(0) = X"75") then
uart_next_state <= UNPAUSE;
elsif(rx_str(0) = X"70") then
uart_next_state <= PC;
strEnd <= 23;
pc_reg <= PC_IN;
else
uart_next_state <= IDLE;
end if;
-- State REGFILE: Print out the entire register file
-- TODO: it is now less crappy
-- To use type rxx, where xx is the register number to access.
-- reggie_counter_counter is the length of the string printed per register
when REGFILE =>
uart_next_state <= REGFILE;
if( reggie_counter_counter = 23) then
reggie_counter <= reggie_counter + 1;
end if;
if(reggie_counter >= 19) then
uart_next_state <= REGISTERS;
else
reggie_str_counter <= reggie_str_counter + 1;
case reggie_str_counter is
when 0 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"72";
reggie_counter_counter <= 0;
when 2 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(std_logic_vector(to_unsigned(reggie_counter, 5)));
reggie_counter_counter <= 1;
when 1 => if(reggie_counter = 32) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"2");
elsif(reggie_counter > 15) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"1");
else
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"0");
end if;
reggie_counter_counter <= 2;
when 3 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"78";
reggie_counter_counter <= 2;
when 4 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(63 downto 60));
reggie_counter_counter <= 3;
when 5 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(59 downto 56));
reggie_counter_counter <= 4;
when 6 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(55 downto 52));
reggie_counter_counter <= 5;
when 7 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(51 downto 48));
reggie_counter_counter <= 6;
when 8 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(47 downto 44));
reggie_counter_counter <= 7;
when 9 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(43 downto 40));
reggie_counter_counter <= 8;
when 10 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(39 downto 36));
reggie_counter_counter <= 9;
when 11 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(35 downto 32));
reggie_counter_counter <= 10;
when 12 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(31 downto 28));
reggie_counter_counter <= 11;
when 13 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(27 downto 24));
reggie_counter_counter <= 12;
when 14 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(23 downto 20));
reggie_counter_counter <= 13;
when 15 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(19 downto 16));
reggie_counter_counter <= 14;
when 16 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(15 downto 12));
reggie_counter_counter <= 15;
when 17 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(11 downto 8));
reggie_counter_counter <= 16;
when 18 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(7 downto 4));
reggie_counter_counter <= 17;
when 19 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(3 downto 0));
reggie_counter_counter <= 18;
when 20 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"20";
reggie_counter_counter <= 19;
when 21 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 20;
when 22 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 21;
when 23 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 22;
when 24 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 23;
reggie_str_counter <= 0;
when others => sendStr(24) <= X"20";
end case;
end if;
when REGFILE_I =>
-- MSD to the left
if(internal_register_int > 31) then
uart_next_state <= IDLE; --Don't do nothing
else
uart_next_state <= REGFILE;
-- (reggie_counter_counter = 23) then
reggie_counter <= reggie_counter + 1;
end if;
if(reggie_str_counter > 23) then
uart_next_state <= REGISTERS;
else
reggie_str_counter <= reggie_str_counter + 1;
case reggie_str_counter is
when 0 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"72";
reggie_counter_counter <= 0;
when 1 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(std_logic_vector(to_unsigned(internal_register_int, 8)));
reggie_counter_counter <= 1;
when 2 => if(reggie_counter = 32) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"2");
elsif(reggie_counter > 15) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"1");
else
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"0");
end if;
reggie_counter_counter <= 2;
when 3 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"78";
reggie_counter_counter <= 2;
when 4 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(63 downto 60));
reggie_counter_counter <= 3;
when 5 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(59 downto 56));
reggie_counter_counter <= 4;
when 6 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(55 downto 52));
reggie_counter_counter <= 5;
when 7 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(51 downto 48));
reggie_counter_counter <= 6;
when 8 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(47 downto 44));
reggie_counter_counter <= 7;
when 9 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(43 downto 40));
reggie_counter_counter <= 8;
when 10 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(39 downto 36));
reggie_counter_counter <= 9;
when 11 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(35 downto 32));
reggie_counter_counter <= 10;
when 12 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(31 downto 28));
reggie_counter_counter <= 11;
when 13 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(27 downto 24));
reggie_counter_counter <= 12;
when 14 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(23 downto 20));
reggie_counter_counter <= 13;
when 15 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(19 downto 16));
reggie_counter_counter <= 14;
when 16 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(15 downto 12));
reggie_counter_counter <= 15;
when 17 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(11 downto 8));
reggie_counter_counter <= 16;
when 18 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(7 downto 4));
reggie_counter_counter <= 17;
when 19 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(3 downto 0));
reggie_counter_counter <= 18;
when 20 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"20";
reggie_counter_counter <= 19;
when 21 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 20;
when 22 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 21;
when 23 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 22;
when 24 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 23;
reggie_str_counter <= 0;
when others => sendStr(24) <= X"20";
end case;
end if;
when PC =>
uart_next_state <= PC;
if(pc_str_counter > 21) then
uart_next_state <= SEND_CHAR;
else
pc_str_counter <= pc_str_counter + 1;
case pc_str_counter is
when 1 => sendStr(pc_str_counter) <= X"50";
when 2 => sendStr(pc_str_counter) <= X"43";
when 3 => sendStr(pc_str_counter) <= X"3A";
when 4 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(63 downto 60));
when 5 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(59 downto 56));
when 6 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(55 downto 52));
when 7 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(51 downto 48));
when 8 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(47 downto 44));
when 9 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(43 downto 40));
when 10 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(39 downto 36));
when 11 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(35 downto 32));
when 12 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(31 downto 28));
when 13 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(27 downto 24));
when 14 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(23 downto 20));
when 15 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(19 downto 16));
when 16 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(15 downto 12));
when 17 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(11 downto 8));
when 18 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(7 downto 4));
when 19 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(3 downto 0));
when 20 => sendStr(pc_str_counter) <= X"20";
when 21 => sendStr(pc_str_counter) <= X"0A";
when 22 => sendStr(pc_str_counter) <= X"0A";
when 23 => sendStr(pc_str_counter) <= X"0A";
when 24 => sendStr(pc_str_counter) <= X"0A";
when others => sendStr(24) <= X"20";
end case;
end if;
-- State STEP: Step one clock cycle
-- halt_l is 0, allows the CPU to continue for one clock cycle
when STEP =>
halt_l <= '0';
uart_next_state <= STEP_HI;
-- State STEP_HI: One step done
-- halt_l is 1, halts the processor
when STEP_HI =>
halt_l <= '1';
uart_next_state <= STEP_LO;
-- State STEP_LO: One step done
-- If the user wants to skip 2 clock cycles instead of one,
-- STEP_HI can set halt_l to 0 and STEP_LO can be set to 1
-- This can be
when STEP_LO =>
halt_l <= '1';
uart_next_state <= RESET_LO;
-- State REGISTERS: Once the strings are prepared, send the characters
when REGISTERS =>
uart_next_state <= SEND_CHAR;
-- State SEND_CHAR: Tell the UART controller to print things
when SEND_CHAR =>
strIndex <= strIndex + 1;
uartSend <= '1';
uartData <= sendStr(strIndex);
uart_next_state <= WAIT_CHAR;
-- State WAIT_CHAR: Checks if the entirety of the string
-- has been sent
when WAIT_CHAR =>
uart_next_state <= WAIT_CHAR;
if(strEnd <= strIndex) then
uart_next_state <= RESET_LO;
elsif(uartRdy = '1') then
uart_next_state <= SEND_CHAR;
end if;
-- State RESET_LO: Resets the RX_UART to flush whatever it
-- had as an input to prepare for the next function
when RESET_LO =>
reset_read <= '1';
uart_next_state <= RESET_HI;
-- State RESET_HI:
when RESET_HI =>
reset_read <= '0';
uart_next_state <= IDLE;
-- State UNPAUSE: Lifts the halt_l, allowing the CPU to run normally
when UNPAUSE =>
halt_l <= '0';
uart_next_state <= RESET_LO;
when OTHERS =>
uart_next_state <= IDLE;
end case;
end if;
end process;
end Behavioral; | mit | edae38bfe447e8b9348e8d9373184b6c | 0.455337 | 4.619491 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/dcm_TFT9/example_design/dcm_TFT9_exdes.vhd | 1 | 6,821 | -- file: dcm_TFT9_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm_TFT9_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end dcm_TFT9_exdes;
architecture xilinx of dcm_TFT9_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
-- Need to buffer input clocks that aren't already buffered
signal clk_in1_buf : std_logic;
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component dcm_TFT9 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK9 : out std_logic;
CLK9_180 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Insert BUFGs on all input clocks that don't already have them
----------------------------------------------------------------
clkin1_buf : BUFG
port map
(O => clk_in1_buf,
I => CLK_IN1);
-- Instantiation of the clocking network
----------------------------------------
clknetwork : dcm_TFT9
port map
(-- Clock in ports
CLK_IN1 => clk_in1_buf,
-- Clock out ports
CLK9 => clk_int(1),
CLK9_180 => clk_int(2),
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| gpl-3.0 | 848866c38d8a06eae378d845c869c739 | 0.62073 | 3.981903 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/config.vhd | 1 | 30,841 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ERROR :integer := -1; -- Not implemented, trap
constant CSR_ZERO :integer := 0; -- Not implemented, read 0, ignore write
constant CSR_FFLAGS :integer := 1;
constant CSR_FRM :integer := 2;
constant CSR_FCSR :integer := 3;
constant CSR_CYCLE :integer := 4;
constant CSR_TIME :integer := 5;
constant CSR_INSTRET :integer := 6;
constant CSR_SIE :integer := 7;
constant CSR_STVEC :integer := 8;
constant CSR_SCOUNTEREN :integer := 9;
constant CSR_SSCRATCH :integer := 10;
constant CSR_SEPC :integer := 11;
constant CSR_SCAUSE :integer := 12;
constant CSR_STVAL :integer := 13;
constant CSR_SIP :integer := 14;
constant CSR_SSTATUS :integer := 15;
constant CSR_SATP :integer := 16;
constant CSR_MSTATUS :integer := 17;
constant CSR_MISA :integer := 18;
constant CSR_MEDELEG :integer := 19;
constant CSR_MIDELEG :integer := 20;
constant CSR_MIE :integer := 21;
constant CSR_MTVEC :integer := 22;
constant CSR_MCOUNTEREN :integer := 23;
constant CSR_MSCRATCH :integer := 24;
constant CSR_MEPC :integer := 25;
constant CSR_MCAUSE :integer := 26;
constant CSR_MTVAL :integer := 27;
constant CSR_MIP :integer := 28;
constant CSR_MCYCLE :integer := 29;
constant CSR_MINSTRET :integer := 30;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector;
function ASCII_TO_HEX(word: std_logic_vector(7 downto 0)) return integer;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector is
begin
if(unsigned(word) < 10) then
return "0011" & word;
elsif(unsigned(word) = 11) then
return "01100001";
elsif(unsigned(word) = 12) then
return "01100010";
elsif(unsigned(word) = 13) then
return "01100011";
elsif(unsigned(word) = 14) then
return "01100100";
elsif(unsigned(word) = 15) then
return "01100100";
else
return "00110000";
end if;
end;
-- Takes an ASCII character and returns an integer value
function ASCII_TO_HEX(word: std_logic_vector(7 downto 0)) return integer is
begin
if(unsigned(word) > 47 AND unsigned(word) < 58) then
return to_integer(unsigned(word)) - 48;
elsif(unsigned(word) > 96 AND unsigned(word) < 103) then
-- We want to return 11 for a, 12 for b, so on
return to_integer(unsigned(word)) - 86;
else --Which happens when the user puts garbage in
return 99;
end if;
end;
end config;
| mit | eab1a58ed7f165a537d01eff7efa7760 | 0.627314 | 3.569973 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/controllers/cpu.vhd | 1 | 3,439 | library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- CPU: ENEMY ALIEN CONTROLLER
-- This entity asynchronously receives commands (reset/enable) and synchronously
-- updates the positions of the aliens.
--------------------------------------------------------------------------------
entity cpu is
generic
(
res_x : integer := 15;
res_y : integer := 15;
pos_x : integer := 11;
pos_y : integer := 8;
aux_x : integer := 11;
aux_y : integer := 8;
clock_div : integer := 4
);
port
(
reset_i,kill_i : in std_logic;
clock_i, turn_i : in std_logic;
turn_o : out std_logic; -- when any alien reaches a side, it sends
-- sends a signal for every alien to change
-- direction.
enable_o : buffer std_logic;
position_x_o : buffer integer range 0 to res_x;
position_y_o : buffer integer range 0 to res_y;
dying : out std_logic; -- exploding animation
game_over : out std_logic
);
end entity;
architecture behavior of cpu is
-- clock for updating x position
signal clock_s : std_logic;
type CPU_STATE is (ALIVE, EXPLODING, DEAD);
signal state : CPU_STATE;
begin
cpu_clock: clock_counter
generic map ( clock_div )
port map ( clock_i, clock_s );
cpu_movement_x:
process (reset_i, kill_i, clock_s, enable_o)
variable move_right_v : std_logic := '1';
begin
if reset_i = '1' then
position_x_o <= pos_x - aux_x/2;
position_y_o <= pos_y - aux_y/2;
--enable_o <= '1';
move_right_v := '1';
turn_o <= '0';
game_over <= '0';
elsif kill_i = '1' then
--enable_o <= '0';
turn_o <= '0';
else
if rising_edge(clock_s) and enable_o='1' then
if position_y_o >= 110 then
game_over <= '1';
elsif turn_i = '1' then
position_y_o <= position_y_o + 10;
move_right_v := not(move_right_v);
turn_o <= '0';
else
if move_right_v = '1' then
position_x_o <= position_x_o + 3;
elsif move_right_v = '0' then
position_x_o <= position_x_o - 3;
end if;
if position_x_o + aux_x > res_x-9 and move_right_v = '1' then
turn_o <= '1';
elsif position_x_o < 9 and move_right_v = '0' then
turn_o <= '1';
end if;
end if;
end if;
end if;
end process;
-- CPU State Control
cpu_fsm:
process (reset_i,clock_s,kill_i)
begin
if reset_i = '1' then
enable_o <= '1';
dying <= '0';
state <= ALIVE;
elsif kill_i = '1' then
dying <= '1';
state <= EXPLODING;
elsif rising_edge(clock_s) then
case state is
when ALIVE =>
when EXPLODING =>
enable_o <= '0';
state <= DEAD;
when DEAD =>
dying <= '0';
end case;
end if;
end process;
end architecture;
| mit | 17d165cb2b263b1ced998efd65557884 | 0.445769 | 3.754367 | false | false | false | false |
satputeaditya/vernier-ring-oscillator-tdc | coincidence_detector.vhd | 1 | 1,249 | -- coincidence_detector.vhd
--**********************************************************************
-- Program to detect if STOP pulse is leading and lagging edge wrt START
--**********************************************************************
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
entity coincidence_detector is
port (
rst : in std_logic;
slow_clk : in std_logic;
fast_clk : in std_logic;
leading : out std_logic; -- SLOW CLK = Reference
lagging : out std_logic -- SLOW CLK = Reference
);
end entity;
architecture behave of coincidence_detector is
signal edge_1 : std_logic;
signal edge_2 : std_logic;
signal rising_edge : std_logic;
signal falling_edge : std_logic;
begin
process(rst,slow_clk,fast_clk)
begin
if rst = '1' then
edge_1 <= '0';
edge_2 <= '0';
elsif FAST_CLK'event and FAST_CLK = '1' then
edge_1 <= SLOW_CLK;
edge_2 <= edge_1;
end if;
end process;
rising_edge <= edge_1 and (not edge_2);
falling_edge <= edge_2 and (not edge_1);
leading <= rising_edge;
lagging <= falling_edge;
end behave; | mit | 32b77ea8204613ab78ff6ab9a9e2ba2b | 0.533227 | 3.431319 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/ALU.vhd | 1 | 18,435 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 12/04/2017 08:30:06 AM
-- Module Name: ALU - Behavioral
-- Description:
--
-- Additional Comments: Omitted MULSHU because it is a special snowflake.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.NUMERIC_BIT.ALL;
library config;
use work.config.all;
entity ALU is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end ALU;
architecture Behavioral of ALU is
-- component declaration
component Shifter is
port (
clk : in std_logic;
rst : in std_logic;
ctrl: in instr_t;
i_a1 : in std_logic_vector(63 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
result: out doubleword
);
end component;
-- Signals and constants
constant all_bits_set : doubleword := (others => '1');
signal result: doubleword;
signal feedback: std_logic_vector(2 downto 0); -- (Error, Overflow, Zero)
-- Shift unit signals
signal s_shift_amt: std_logic_vector(5 downto 0);
signal s_shift_arg: doubleword;
signal s_shift_result: doubleword;
begin
-- Instantiation
myShifter : Shifter
port map(
clk => clk,
rst => rst,
ctrl => ctrl,
i_a1 => s_shift_arg, -- Operand 1
i_a2 => s_shift_amt, -- Shift bits number
result => s_shift_result
);
process( clk )
variable shift_limit: natural;
variable mul_reg: std_logic_vector(127 downto 0);
variable add_word: doubleword;
begin
-- shift_arg <= to_integer(unsigned(shamt));
feedback <= "000";
if(rising_edge(clk)) then
case ctrl is
-- Treat as 32-bit operands
when instr_SLL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
-- shift_limit := to_integer(unsigned(shamt));
-- result <= zero_word & rs1(31 - shift_limit downto 0) & zero_word(shift_limit-1 downto 0);
when instr_SRL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRA =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADD =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
when instr_ADDI =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_SUB =>
result <= std_logic_vector(signed(rs1) - signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_LUI =>
-- In brief: rd = sign_extend(rsimm20 << 12)
-- Load low 20 of immediate value shifted left 12
-- sign extend to fit 64 bit system
result(31 downto 0) <= rs2(19 downto 0) & "000000000000";
result(63 downto 32) <= (others => rs2(19));
when instr_AUIPC =>
-- TODO verify that PC can easily be passed in here as arg 1
-- In brief: rd = PC + (rs << 12)
-- Load 20 MSBs of low word with low 20 of immediate value
-- sign extend (rs << 12) to fit 64 bit
-- NOTE: Here, we use a "qualified expression" to hint at how the compiler should resolve
-- the ambiguity. We give a hint as to which overloaded function should be used,
-- in this case, the one that takes in a bit vector constant and a std_logic_vector
-- and returns a std_logic_vector.
--auipc_ext(31 downto 0) := std_logic_vector'(rs2(19 downto 0) & "000000000000");
result <= std_logic_vector(signed(rs1) + signed(std_logic_vector'(rs2(19 downto 0) & "000000000000")));
when instr_XOR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_XORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_OR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_ORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_AND =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_ANDI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_SLT =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTI =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTIU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLLW =>
-- Since these are word operations instead of double
-- word operations, only use the bottom 5 bits instead of 6
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADDW =>
add_word := std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_ADDIW =>
add_word := std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_SUBW =>
add_word := std_logic_vector(signed(rs1) - signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_MUL =>
mul_reg := std_logic_vector(signed(rs1) * signed(rs2));
result <= mul_reg(63 downto 0);
when instr_MULH =>
mul_reg := std_logic_vector(signed(rs1) * signed(rs2));
result <= zero_word & mul_reg(63 downto 32);
when instr_MULHU =>
mul_reg := std_logic_vector(unsigned(rs1) * unsigned(rs2));
result <= zero_word & mul_reg(63 downto 32);
--when instr_MULHSU =>
-- TODO - verify that this multiplier does not introduce problems on the schematic/layout
--mul_reg_plus <= std_logic_vector(signed(rs1(31) & rs1) * signed('0' & rs2));
--result <= zero_word & mul_reg_plus(63 downto 32);
--
-- Special Values for Divide by Zero and Division Overflow (per 2.2 spec)
-- Situation || Special Return Values for Each Instruction
-- <condition> <Dividend> <Divisor> || <DIVU> <REMU> <DIV> <REM>
-- Divide by 0 x 0 || All bits set x -1 x
-- Overflow -(2^64 -1) -1 || N/A N/A -(2^(64-1)) 0
--
when instr_DIV =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg := all_bits_set & all_bits_set;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set only MSB
mul_reg := (63 => '1', others => '0');
else
mul_reg := zero_word & zero_word & std_logic_vector(signed(rs1) / signed(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_DIVU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to all ones
mul_reg := all_bits_set & all_bits_set;
else
mul_reg := zero_word & zero_word & std_logic_vector(unsigned(rs1) / unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_REM =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg := zero_word & zero_word & rs1;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set result to 0
mul_reg := (others => '0');
else
mul_reg := zero_word & zero_word & std_logic_vector(signed(rs1) rem signed(rs2));
end if;
result(31 downto 0) <= mul_reg(31 downto 0);
result(63 downto 32) <= (others => mul_reg(31));
when instr_REMU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg := zero_word & zero_word & rs1;
else
mul_reg := zero_word & zero_word & std_logic_vector(unsigned(rs1) rem unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_MULW =>
mul_reg := zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) * signed(rs2(31 downto 0)));
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg := all_bits_set & all_bits_set;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set only MSB
mul_reg := (31 => '1', others => '0');
else
mul_reg := zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) / signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to all ones
mul_reg := all_bits_set & all_bits_set;
else
mul_reg := zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) / unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg := zero_word & zero_word & rs1;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set result to 0
mul_reg := (others => '0');
else
mul_reg := zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) rem signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg := zero_word & zero_word & rs1;
else
mul_reg := zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) rem unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when others =>
-- Error condition: unknown control code
feedback(0) <= '1';
result <= (others => '0');
end case;
end if; -- Clock
end process;
error <= feedback(0); -- TODO feedback single bit for error conditions.
overflow <= feedback(1);-- TODO check here, remove from logic above
zero <= '1' when (0 = unsigned(result)) else '0';
rout <= result;
end Behavioral; | mit | 464987539038a43078f4c1bb0ef46d9a | 0.413398 | 4.70761 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/simple_core.vhd | 1 | 70,726 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/10/2018 06:05:22 PM
-- Module Name: simple_core - Behavioral
-- Description: Incremental build of the simplified processor core
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library config;
use work.config.all;
entity simple_core is
Port(
status: out std_logic; -- LED blinkenlites
clk: in std_logic; -- System clock (100 MHz)
rst: in std_logic; -- Tied to switch SW0
DEBUG_halt: in std_logic;
SUM: out std_logic;
MXR: out std_logic;
MTIP: in std_logic;
MSIP: in std_logic;
MMU_addr_in: out doubleword; -- 64-bits address for load/store/fetch
MMU_data_in: out doubleword; -- 64-bits data for store
MMU_satp: out doubleword; -- Signals address translation privilege
MMU_mode: out std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
MMU_type: out std_logic_vector(1 downto 0); -- High to toggle store / low means load
MMU_done: in std_logic; -- High when busy
MMU_request: out std_logic; -- request has been made
MMU_num_bytes: out std_logic_vector(1 downto 0); -- alignment in bytes
MMU_data_out: in doubleword; -- 64-Bits data out for load
MMU_error: in std_logic_vector(6 downto 0); -- Error bits from MMU
MMU_debug_phys: in doubleword;
MMU_debug_virt: in doubleword
);
end simple_core;
architecture Behavioral of simple_core is
----------------------------------------------------------------------------------
-- Component instantiation
----------------------------------------------------------------------------------
component ALU is
port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end component;
component decoder is
Port(
instr : in std_logic_vector(31 downto 0);
instr_code : out instr_t;
funct3 : out funct3_t;
funct6 : out funct6_t;
funct7 : out funct7_t;
imm12 : out std_logic_vector(11 downto 0); -- I, B, and S Immediates
imm20 : out std_logic_vector(19 downto 0); -- U and J Immediates
opcode : out opcode_t;
rs1 : out reg_t;
rs2 : out reg_t;
rs3 : out reg_t;
rd : out reg_t;
shamt : out std_logic_vector(4 downto 0);
csr : out std_logic_vector(31 downto 20);
sext_imm12 : out std_logic_vector(63 downto 0);
sext_imm20 : out std_logic_vector(63 downto 0);
reg_A : out integer;
reg_B : out integer;
reg_C : out integer;
reg_D : out integer
);
end component;
----------------------------------------------------------------------------------
-- Signals and constants
----------------------------------------------------------------------------------
-- Decoded instruction parts
signal s_save_instr: word;
signal s_output_data: word;
signal s_instr_code: instr_t; -- Exact instruction encoding
signal s_opcode: opcode_t; -- Opcode category abstraction
signal s_rs1: reg_t; -- Regfile read address
signal s_rs2: reg_t; -- Regfile read address
signal s_rs3: reg_t; -- Regfile read address
signal s_rd: reg_t; -- Regfile write address
signal s_shamt: std_logic_vector(4 downto 0); -- Shift amount, immediate shifts
signal s_imm12: std_logic_vector(11 downto 0); -- Immediate value, 12 bit style
signal s_imm20: std_logic_vector(19 downto 0); -- Immediate value, 20 bit style
signal s_csr_bits: std_logic_vector(11 downto 0); -- CSR address for CSR instructions
signal s_functs: std_logic_vector(15 downto 0); -- Holds concatenation of funct3, funct6, funct7
signal s_sext_12: doubleword; -- Sign extended immediate value
signal s_sext_20: doubleword; -- Sign extended immediate value
signal reg_A : integer;
signal reg_B : integer;
signal reg_C : integer;
signal reg_D : integer;
-- ALU connectors
signal s_ALU_input1: doubleword;
signal s_ALU_input2: doubleword;
signal s_ALU_result: doubleword;
signal s_ALU_Error: std_logic_vector(2 downto 0);
-- MMU connectors
signal mem_ret_data : doubleword;
signal s_MMU_input_addr: doubleword;
signal s_MMU_type: std_logic_vector(1 downto 0);
signal s_MMU_num_bytes: std_logic_vector(1 downto 0); -- One-hot selection in bytes
-- High-level states of operation (distinct from modes)
type state is ( INIT, FETCH, DECODE, DECODE_B, EXECUTE, FINISH_UP,
TAKE_TRAP, TAKE_TRAP_SUPERVISOR, TAKE_TRAP_MACHINE, CHECK_INTERRUPT,
MEM_A, MEM_B, MEM_C, LOAD_COMPLETE_UNSIGNED, LOAD_COMPLETE_SIGNED,
CSR_CHECK_ACCESS, CSR_READ_CURRENT, CSR_OPERATOR, CSR_WRITE_BACK, CSR_WRITE_NEW,
SUPERVISOR_RETURN, MACHINE_RETURN,
DEBUG_DUMP, DEBUG_DUMP_REG, DEBUG_DUMP_CSR, DEBUG_GET_COMMAND, DEBUG_GET_ADDRESS,
DEBUG_WRITE_DWORD,
DEBUG_DO_COMMAND_STEP, DEBUG_DO_COMMAND_CONTINUE, DEBUG_DO_COMMAND_PHYS, DEBUG_DO_COMMAND_VIRT,
DEBUG_READ_UART, DEBUG_READ_UART_RDY, DEBUG_READ_UART_DATA, DEBUG_READ_UART_DONE,
DEBUG_WRITE_UART, DEBUG_WRITE_UART_RDY, DEBUG_WRITE_UART_DATA, DEBUG_WRITE_UART_DONE,
ATOMIC_DO_LOAD, ATOMIC_DO_OPERATION, ATOMIC_DO_STORE,
ALU_RUN, ALU_RUN_B, ALU_RUN_C, ALU_RUN_D, ALU_RUN_E, ALU_RUN_F,
ALU_RUN_G, ALU_RUN_H, ALU_RUN_I, ALU_RUN_J, ALU_RUN_K, ALU_RUN_L, WRITE_BACK );
signal curr_state, mem_ret_state, execute_ret_state, alu_ret_state : state;
signal s_debug_write_dwrod_ret, s_debug_get_addr_ret, s_debug_uart_ret : state;
signal init_counter : integer := 0;
-- Control status registers followed by scratch
signal csr : regfile_arr;
signal pc : doubleword; -- current program counter
signal s_PC_next : doubleword; -- Next PC address
signal isa : doubleword;
signal prv : std_logic_vector(1 downto 0);
signal mstatus : doubleword;
signal mepc : doubleword;
signal mtval : doubleword;
signal mscratch : doubleword;
signal mtvec : doubleword;
signal mcause : doubleword;
signal minstret : doubleword;
signal mie : doubleword;
signal mip : doubleword;
signal medeleg : doubleword;
signal mideleg : doubleword;
signal mcounteren : doubleword;
signal scounteren : doubleword;
signal sepc : doubleword;
signal stval : doubleword;
signal sscratch : doubleword;
signal stvec : doubleword;
signal satp : doubleword;
signal scause : doubleword;
signal cause : doubleword;
signal epc : doubleword;
signal tval : doubleword;
signal load_reservation : STD_LOGIC_VECTOR( 63 downto 0 );
-- Normal registers --
signal reg: regfile_arr;
signal reg_zero : doubleword;
signal reg_ra : doubleword;
signal reg_sp : doubleword;
signal reg_gp : doubleword;
signal reg_tp : doubleword;
signal reg_t0 : doubleword;
signal reg_t1 : doubleword;
signal reg_t2 : doubleword;
signal reg_s0_fp : doubleword;
signal reg_s1 : doubleword;
signal reg_a0 : doubleword;
signal reg_a1 : doubleword;
signal reg_a2 : doubleword;
signal reg_a3 : doubleword;
signal reg_a4 : doubleword;
signal reg_a5 : doubleword;
signal reg_a6 : doubleword;
signal reg_a7 : doubleword;
signal reg_s2 : doubleword;
signal reg_s3 : doubleword;
signal reg_s4 : doubleword;
signal reg_s5 : doubleword;
signal reg_s6 : doubleword;
signal reg_s7 : doubleword;
signal reg_s8 : doubleword;
signal reg_s9 : doubleword;
signal reg_s10 : doubleword;
signal reg_s11 : doubleword;
signal reg_t3 : doubleword;
signal reg_t4 : doubleword;
signal reg_t5 : doubleword;
signal reg_t6 : doubleword;
signal s_csr_should_write : std_logic;
signal s_csr_old_value : doubleword;
signal s_csr_mod_value : doubleword;
-- DEBUGGER --
signal s_debug_break : std_logic;
signal s_debug_address : doubleword;
signal s_debug_phys_address : doubleword;
signal s_debug_virt_address : doubleword;
signal s_debug_index : integer;
signal s_debug_reg_index : integer;
signal s_debug_dword_out : doubleword;
signal s_debug_byte : STD_LOGIC_VECTOR( 7 downto 0 );
signal s_debug_bytes : byte_arr;
signal s_debug_access : std_logic;
-- ATOMIC --
signal s_atomic_bytes : STD_LOGIC_VECTOR( 1 downto 0 );
signal s_atomic_address : doubleword;
signal s_atomic_output : doubleword;
signal s_sext_12_shift_1 : STD_LOGIC_VECTOR( 63 downto 0 );
signal s_sext_20_shift_1 : STD_LOGIC_VECTOR( 63 downto 0 );
signal s_sext_20_shift_12 : STD_LOGIC_VECTOR( 63 downto 0 );
----------------------------------------------------------------------------------
-- Architecture Begin
----------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------
-- Component instantiations and mapping
----------------------------------------------------------------------------------
myDecode: decoder
port map(
instr => s_output_data,
instr_code => s_instr_code,
funct3 => s_functs(15 downto 13),
funct6 => s_functs(12 downto 7),
funct7 => s_functs(6 downto 0),
imm12 => s_imm12,
imm20 => s_imm20,
opcode => s_opcode,
rs1 => s_rs1,
rs2 => s_rs2,
rs3 => s_rs3,
rd => s_rd,
shamt => s_shamt,
csr => s_csr_bits,
sext_imm12 => s_sext_12,
sext_imm20 => s_sext_20,
reg_A => reg_A,
reg_B => reg_B,
reg_C => reg_C,
reg_D => reg_D
);
myALU: ALU
port map(
clk => clk,
rst => rst,
ctrl => s_instr_code,
rs1 => s_ALU_input1,
rs2 => s_ALU_input2,
shamt => s_shamt,
rout => s_ALU_result,
error => s_ALU_error(2),
overflow => s_ALU_error(1),
zero => s_ALU_error(0)
);
s_sext_12_shift_1 <= s_sext_12(62 downto 0) & '0';
s_sext_20_shift_1 <= s_sext_20(62 downto 0) & '0';
s_sext_20_shift_12 <= s_sext_20(51 downto 0) & ALL_ZERO(11 downto 0);
----------------------------------------------------------------------------------
-- Main Logic
----------------------------------------------------------------------------------
process( clk )
variable deleg : STD_LOGIC_VECTOR( 63 downto 0 );
variable cause_bit : integer;
--- CHECK_INTERRUPT ---
variable pending_interrupts : STD_LOGIC_VECTOR( 63 downto 0 );
variable m_enabled : STD_LOGIC;
variable s_enabled : STD_LOGIC;
variable enabled_interrupts : STD_LOGIC_VECTOR( 63 downto 0 );
variable tmp_cause : STD_LOGIC_VECTOR( 6 downto 0 );
--- CSR ---
variable csr_priv : integer;
variable csr_read_only : STD_LOGIC_VECTOR( 1 downto 0 );
variable csr_should_write : std_logic;
variable csr_type : STD_LOGIC_VECTOR( 2 downto 0 );
variable csr_error : std_logic;
variable csr_mask : doubleword;
-- ATOM --
variable atomic_sext : STD_LOGIC_VECTOR( 63 downto 0 );
begin if(rising_edge(clk)) then
case curr_state is
when INIT =>
init_counter <= init_counter + 1;
if( init_counter > INIT_WAIT ) then
curr_state <= CHECK_INTERRUPT;
end if;
s_debug_break <= '0';
pc <= x"000000008FFFFFFC";
s_PC_next <= x"000000008FFFFFFC";
s_debug_phys_address <= (others => '0');
s_debug_virt_address <= (others => '0');
load_reservation <= LOAD_RESERVATION_NONE;
prv <= MACHINE_MODE;
reg <= (others => (others => '0'));
isa <= x"8000000000141101"; -- isa supports 'aim' and 'us' modes
-- the MMU drives MIP_MTIP and MIP_MSIP we start all other bits at 0
mip(63 downto MIP_MTIP + 1) <= ALL_ZERO(63 downto MIP_MTIP + 1);
mip(MIP_MTIP - 1 downto MIP_MSIP + 1) <= ALL_ZERO(MIP_MTIP - 1 downto MIP_MSIP + 1);
mip(MIP_MSIP - 1 downto 0) <= ALL_ZERO(MIP_MSIP - 1 downto 0);
mstatus <= (others => '0'); mepc <= (others => '0'); mtval <= (others => '0');
mscratch <= (others => '0'); mtvec <= x"000000008FFFFFFC"; mcause <= (others => '0');
minstret <= (others => '0'); mie <= (others => '0');
medeleg <= (others => '0'); mideleg <= (others => '0'); mcounteren <= (others => '0');
scounteren <= (others => '0'); sepc <= (others => '0'); stval <= (others => '0');
sscratch <= (others => '0'); stvec <= (others => '0'); satp <= (others => '0');
scause <= (others => '0');
cause <= (others => '0'); epc <= (others => '0'); tval <= (others => '0');
s_debug_access <= '0';
MMU_request <= '0';
when TAKE_TRAP =>
--- cause should be in the generic cause register
--- any bad addresses and values should be in tval
-- if this was from an interrupt
if( cause(CAUSE_INTERRUPT_BIT) = CAUSE_INTERRUPT ) then
-- use interrupt delegate
deleg := mideleg;
else
-- use exception delegate
deleg := medeleg;
end if;
-- reservations are wiped out from traps
load_reservation <= LOAD_RESERVATION_NONE;
cause_bit := to_integer( unsigned ( cause( 62 downto 0 ) ) );
-- if we are in supervisor or user mode
if( ( prv <= SUPERVISOR_MODE ) and
( cause_bit < 64 ) and
( deleg(cause_bit) = '1' ) )
then
curr_state <= TAKE_TRAP_SUPERVISOR;
else
curr_state <= TAKE_TRAP_MACHINE;
end if;
when TAKE_TRAP_SUPERVISOR =>
-- if we are in vectored mode and this is an interrupt
if( ( stvec(TVEC_MODE_H downto TVEC_MODE_L) = TVEC_MODE_VECTORED ) and
( cause(CAUSE_INTERRUPT_BIT) = CAUSE_INTERRUPT ) )
then
-- jump to the base + the vector
-- vector is cause * 4 ( ignoring interrupt bit )
pc <= ( stvec( TVEC_BASE_H downto TVEC_BASE_L ) & ALL_ZERO( TVEC_BASE_L - 1 downto 0 ) )
+
( cause( 61 downto 0 ) & "00" );
else
-- Direct mode, go straight to the vector base
pc <= ( stvec( TVEC_BASE_H downto TVEC_BASE_L ) & ALL_ZERO( TVEC_BASE_L - 1 downto 0 ) );
end if;
-- transfer the trap values
scause <= cause;
sepc <= pc;
stval <= tval;
-- save the Supervisor Interrupts Enabled bit
mstatus(MSTATUS_SPIE) <= mstatus(MSTATUS_SIE);
-- save the return privilage mode
-- only 1 bit saved since only options are user and super
mstatus(MSTATUS_SPP) <= prv(0);
-- disable supervisor interrupts
mstatus(MSTATUS_SIE) <= '0';
-- set privilage mode to supervisor
prv <= SUPERVISOR_MODE;
-- return to normal instruction flow
curr_state <= CHECK_INTERRUPT;
when TAKE_TRAP_MACHINE =>
-- if we are in vectored mode and this is an interrupt
if( ( mtvec(TVEC_MODE_H downto TVEC_MODE_L) = TVEC_MODE_VECTORED ) and
( cause(CAUSE_INTERRUPT_BIT) = CAUSE_INTERRUPT ) )
then
-- jump to the base + the vector
-- vector is cause * 4 ( ignoring interrupt bit )
pc <= ( mtvec( TVEC_BASE_H downto TVEC_BASE_L ) & ALL_ZERO( TVEC_BASE_L - 1 downto 0 ) )
+
( cause( 61 downto 0 ) & "00" );
else
-- Direct mode, go straight to the vector base
pc <= ( mtvec( TVEC_BASE_H downto TVEC_BASE_L ) & ALL_ZERO( TVEC_BASE_L - 1 downto 0 ) );
end if;
-- transfer the trap values
mcause <= cause;
mepc <= pc;
mtval <= tval;
-- save the Machine Interrupts Enabled bit
mstatus(MSTATUS_MPIE) <= mstatus(MSTATUS_MIE);
-- save the return privilage mode
mstatus(MSTATUS_MPP_H downto MSTATUS_MPP_L) <= prv;
-- disable machine interrupts
mstatus(MSTATUS_MIE) <= '0';
-- set privilage mode to machine mode
prv <= MACHINE_MODE;
-- return to normal instruction flow
curr_state <= CHECK_INTERRUPT;
when CHECK_INTERRUPT =>
--- get interrupts that are pending and enabled
pending_interrupts := mip and mie;
--- are machine interrupts enabled
if( ( prv < MACHINE_MODE ) or
( ( prv = MACHINE_MODE ) and ( mstatus(MSTATUS_MIE) = '1' ) ) )
then
m_enabled := '1';
else
m_enabled := '0';
end if;
--- get interrupts that machine mode should service
if( m_enabled = '1' ) then
enabled_interrupts := pending_interrupts and not(mideleg);
else
enabled_interrupts := ( others => '0');
end if;
--- are supervisor interrupts enabled
if( ( prv < SUPERVISOR_MODE ) or
( ( prv = SUPERVISOR_MODE ) and ( mstatus(MSTATUS_SIE) = '1' ) ) )
then
s_enabled := '1';
else
s_enabled := '0';
end if;
--- if no machine interrupts can run see if supervisor ones can
if( enabled_interrupts = ALL_ZERO ) then
if( s_enabled = '1' ) then
enabled_interrupts := ( pending_interrupts and mideleg );
end if;
end if;
if( enabled_interrupts /= ALL_ZERO ) then
if( enabled_interrupts(MIP_MEIP) = '1' ) then
tmp_cause := MIP_MEIP_CAUSE;
elsif( enabled_interrupts(MIP_SEIP) = '1' ) then
tmp_cause := MIP_SEIP_CAUSE;
elsif( enabled_interrupts(MIP_UEIP) = '1' ) then
tmp_cause := MIP_UEIP_CAUSE;
elsif( enabled_interrupts(MIP_MSIP) = '1' ) then
tmp_cause := MIP_MSIP_CAUSE;
elsif( enabled_interrupts(MIP_SSIP) = '1' ) then
tmp_cause := MIP_SSIP_CAUSE;
elsif( enabled_interrupts(MIP_USIP) = '1' ) then
tmp_cause := MIP_USIP_CAUSE;
elsif( enabled_interrupts(MIP_MTIP) = '1' ) then
tmp_cause := MIP_MTIP_CAUSE;
elsif( enabled_interrupts(MIP_STIP) = '1' ) then
tmp_cause := MIP_STIP_CAUSE;
elsif( enabled_interrupts(MIP_UTIP) = '1' ) then
tmp_cause := MIP_UTIP_CAUSE;
end if;
curr_state <= TAKE_TRAP;
cause <= '1' & ALL_ZERO(55 downto 0) & tmp_cause;
else
curr_state <= FETCH;
end if;
when FETCH =>
s_PC_next <= pc;
s_MMU_input_addr <= pc;
s_MMU_type <= MEM_FETCH;
s_MMU_num_bytes <= MEM_BYTES_4;
mem_ret_state <= DECODE;
execute_ret_state <= FINISH_UP;
curr_state <= MEM_A;
when MEM_A =>
-- wait for the MMU to not be busy
if ( MMU_done = '0' ) then
if( s_debug_access = '1' ) then
MMU_mode <= MACHINE_MODE;
else
MMU_mode <= prv;
end if;
-- If MPRV is high tell MMU our privilage is MPP
if( ( s_MMU_type /= MEM_FETCH ) and ( mstatus(MSTATUS_MPRV) = '1' ) ) then
MMU_mode <= mstatus(MSTATUS_MPP_H downto MSTATUS_MPP_L);
end if;
-- make the request
MMU_request <= '1';
curr_state <= MEM_B;
end if;
when MEM_B =>
if( MMU_done = '1' ) then
curr_state <= MEM_C;
end if;
when MEM_C =>
MMU_request <= '0';
curr_state <= mem_ret_state;
-- If there was no error, then latch the returned data
if( MMU_error = MEM_ERR_NONE ) then
if ( ( s_MMU_type = MEM_FETCH ) or ( s_MMU_type = MEM_LOAD ) ) then
mem_ret_data <= MMU_data_out;
end if;
else
-- there was an error, take the trap
cause <= CAUSE_EXCEPTION_HIGH & MMU_error;
tval <= s_MMU_input_addr;
curr_state <= TAKE_TRAP;
end if;
when DECODE =>
-- put the fetched instruction on the decoder
s_save_instr <= mem_ret_data(31 downto 0);
s_output_data <= mem_ret_data(31 downto 0);
if( (MMU_debug_phys = s_debug_phys_address) or (MMU_debug_virt = s_debug_virt_address)
or (s_debug_break = '1') or (DEBUG_halt = '1') )
then
s_debug_access <= '1';
curr_state <= DEBUG_DUMP;
else
curr_state <= DECODE_B;
end if;
when DECODE_B =>
curr_state <= EXECUTE;
when ALU_RUN => curr_state <= ALU_RUN_B;
when ALU_RUN_B => curr_state <= ALU_RUN_C;
when ALU_RUN_C => curr_state <= ALU_RUN_D;
when ALU_RUN_D => curr_state <= ALU_RUN_E;
when ALU_RUN_E => curr_state <= ALU_RUN_L;
--when ALU_RUN_F => curr_state <= ALU_RUN_G;
--when ALU_RUN_G => curr_state <= ALU_RUN_H;
--when ALU_RUN_H => curr_state <= ALU_RUN_I;
--when ALU_RUN_I => curr_state <= ALU_RUN_J;
--when ALU_RUN_J => curr_state <= ALU_RUN_K;
--when ALU_RUN_K => curr_state <= ALU_RUN_L;
when ALU_RUN_L => curr_state <= alu_ret_state;
when WRITE_BACK =>
reg(reg_D) <= s_ALU_result;
curr_state <= execute_ret_state;
when LOAD_COMPLETE_UNSIGNED =>
if (s_MMU_num_bytes = MEM_BYTES_1) then
reg(reg_D) <= ALL_ZERO(63 downto 8) & mem_ret_data(7 downto 0);
elsif (s_MMU_num_bytes = MEM_BYTES_2) then
reg(reg_D) <= ALL_ZERO(63 downto 16) & mem_ret_data(15 downto 0);
elsif (s_MMU_num_bytes = MEM_BYTES_4) then
reg(reg_D) <= ALL_ZERO(63 downto 32) & mem_ret_data(31 downto 0);
else
reg(reg_D) <= mem_ret_data;
end if;
curr_state <= execute_ret_state;
when LOAD_COMPLETE_SIGNED =>
if (s_MMU_num_bytes = MEM_BYTES_1) then
reg(reg_D)(63 downto 8) <= (others => mem_ret_data(7));
reg(reg_D)( 7 downto 0) <= mem_ret_data(7 downto 0);
elsif (s_MMU_num_bytes = MEM_BYTES_2) then
reg(reg_D)(63 downto 16) <= (others => mem_ret_data(15));
reg(reg_D)(15 downto 0) <= mem_ret_data(15 downto 0);
else
reg(reg_D)(63 downto 32) <= (others => mem_ret_data(31));
reg(reg_D)(31 downto 0) <= mem_ret_data(31 downto 0);
end if;
curr_state <= execute_ret_state;
when EXECUTE =>
case s_opcode is
when ALUW_T => -- Case word, R-type ALU operations
-- REG signals
s_ALU_input1 <= reg(reg_A);
s_ALU_input2 <= reg(reg_B);
curr_state <= ALU_RUN;
alu_ret_state <= WRITE_BACK;
when LUI_T =>
s_ALU_input1 <= reg(reg_A);
s_ALU_input2 <= s_sext_20;
curr_state <= ALU_RUN;
alu_ret_state <= WRITE_BACK;
when ALU_T => -- Case regular, R-type ALU operations
-- REG signals
s_ALU_input1 <= reg(reg_A);
s_ALU_input2 <= reg(reg_B);
curr_state <= ALU_RUN;
alu_ret_state <= WRITE_BACK;
when ALUI_T => -- Case regular, I-type ALU operations
-- REG signals
s_ALU_input1 <= reg(reg_A);
s_ALU_input2 <= s_sext_12;
curr_state <= ALU_RUN;
alu_ret_state <= WRITE_BACK;
when ALUIW_T => -- Case word, I-type ALU operations
-- REG signals
s_ALU_input1 <= reg(reg_A);
s_ALU_input2 <= s_sext_12;
curr_state <= ALU_RUN;
alu_ret_state <= WRITE_BACK;
when LOAD_T =>
curr_state <= MEM_A;
s_MMU_type <= MEM_LOAD;
s_MMU_input_addr <= reg(reg_A) + s_sext_12;
case s_instr_code is
when instr_LB =>
s_MMU_num_bytes <= MEM_BYTES_1;
mem_ret_state <= LOAD_COMPLETE_SIGNED;
when instr_LBU =>
s_MMU_num_bytes <= MEM_BYTES_1;
mem_ret_state <= LOAD_COMPLETE_UNSIGNED;
when instr_LH =>
s_MMU_num_bytes <= MEM_BYTES_2;
mem_ret_state <= LOAD_COMPLETE_SIGNED;
when instr_LHU =>
s_MMU_num_bytes <= MEM_BYTES_2;
mem_ret_state <= LOAD_COMPLETE_UNSIGNED;
when instr_LW =>
s_MMU_num_bytes <= MEM_BYTES_4;
mem_ret_state <= LOAD_COMPLETE_SIGNED;
when instr_LWU =>
s_MMU_num_bytes <= MEM_BYTES_4;
mem_ret_state <= LOAD_COMPLETE_UNSIGNED;
when others =>
s_MMU_num_bytes <= MEM_BYTES_8;
mem_ret_state <= LOAD_COMPLETE_UNSIGNED;
end case;
when STORE_T =>
s_MMU_input_addr <= reg(reg_A) + s_sext_12;
MMU_data_in <= reg(reg_B);
curr_state <= MEM_A;
s_MMU_type <= MEM_STORE;
mem_ret_state <= execute_ret_state;
case s_instr_code is
when instr_SB =>
s_MMU_num_bytes <= MEM_BYTES_1;
when instr_SH =>
s_MMU_num_bytes <= MEM_BYTES_2;
when instr_SW =>
s_MMU_num_bytes <= MEM_BYTES_4;
when others => -- store doubleword
s_MMU_num_bytes <= MEM_BYTES_8;
end case;
when BRANCH_T =>
curr_state <= execute_ret_state;
case s_instr_code is
when instr_BEQ =>
if( reg(reg_A) = reg(reg_B) ) then
s_PC_next <= pc + s_sext_12_shift_1;
end if;
when instr_BNE =>
if( reg(reg_A) /= reg(reg_B) ) then
s_PC_next <= pc + s_sext_12_shift_1;
end if;
when instr_BLT =>
if( signed(reg(reg_A)) < signed(reg(reg_B)) ) then
s_PC_next <= pc + s_sext_12_shift_1;
end if;
when instr_BGE =>
if( signed(reg(reg_A)) >= signed(reg(reg_B)) ) then
s_PC_next <= pc + s_sext_12_shift_1;
end if;
when instr_BLTU =>
if( reg(reg_A) < reg(reg_B) ) then
s_PC_next <= pc + s_sext_12_shift_1;
end if;
when others => --instr_BGEU
if( reg(reg_A) >= reg(reg_B) ) then
s_PC_next <= pc + s_sext_12_shift_1;
end if;
end case;
when JAL_T =>
reg(reg_D) <= pc + 4;
curr_state <= execute_ret_state;
s_PC_next <= pc + s_sext_20_shift_1;
when JALR_T =>
curr_state <= execute_ret_state;
reg(reg_D) <= pc + 4;
s_PC_next <= reg(reg_A) + s_sext_12;
s_PC_next(0) <= '0';
when AUIPC_T =>
curr_state <= execute_ret_state;
reg(reg_D) <= pc + s_sext_20_shift_12;
when CSR_T =>
case s_instr_code is
when instr_EBREAK =>
s_debug_break <= '1';
curr_state <= execute_ret_state;
when instr_ECALL =>
-- environment call
if( prv = USER_MODE ) then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ENV_CALL_U_MODE;
elsif( prv = SUPERVISOR_MODE ) then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ENV_CALL_S_MODE;
else
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ENV_CALL_M_MODE;
end if;
curr_state <= TAKE_TRAP;
when instr_SRET => curr_state <= SUPERVISOR_RETURN;
when instr_MRET => curr_state <= MACHINE_RETURN;
when instr_WFI =>
-- noop, no interrupts that drive the system to wait for.
curr_state <= execute_ret_state;
when instr_SFENCEVM =>
-- noop, we don't have a tlb to flush.
-- supposed to throw an error in certain privilage modes, but does nothing.
curr_state <= execute_ret_state;
when instr_CSRRW => curr_state <= CSR_CHECK_ACCESS;
when instr_CSRRS => curr_state <= CSR_CHECK_ACCESS;
when instr_CSRRC => curr_state <= CSR_CHECK_ACCESS;
when instr_CSRRWI => curr_state <= CSR_CHECK_ACCESS;
when instr_CSRRSI => curr_state <= CSR_CHECK_ACCESS;
when instr_CSRRCI => curr_state <= CSR_CHECK_ACCESS;
when others =>
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ILLEGAL_INSTRUCTION;
tval <= zero_word & s_output_data;
curr_state <= TAKE_TRAP;
end case;
when ATOM_T =>
if( ( s_instr_code = instr_SCD ) or ( s_instr_code = instr_SCW ) ) then
if ( ( load_reservation /= LOAD_RESERVATION_NONE ) and ( load_reservation = reg(reg_A) ) ) then
curr_state <= ATOMIC_DO_STORE;
s_atomic_output <= reg(reg_B);
reg(reg_D) <= x"0000000000000001";
else
curr_state <= execute_ret_state;
reg(reg_D) <= x"0000000000000000";
end if;
else
curr_state <= ATOMIC_DO_LOAD;
end if;
if( ( s_instr_code = instr_LRD ) or ( s_instr_code = instr_SCD )
or ( s_instr_code = instr_AMOSWAPD ) or ( s_instr_code = instr_AMOADDD )
or ( s_instr_code = instr_AMOXORD ) or ( s_instr_code = instr_AMOANDD )
or ( s_instr_code = instr_AMOORD ) or ( s_instr_code = instr_AMOMIND )
or ( s_instr_code = instr_AMOMAXD ) or ( s_instr_code = instr_AMOMINUD )
or ( s_instr_code = instr_AMOMAXUD ) ) then
s_atomic_bytes <= MEM_BYTES_8;
else
s_atomic_bytes <= MEM_BYTES_4;
end if;
s_atomic_address <= reg(reg_A);
when FENCE_T =>
-- noop, we have no out of order accesses or caches
curr_state <= execute_ret_state;
when others =>
-- trap on the unknown instruction
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ILLEGAL_INSTRUCTION;
tval <= zero_word & s_output_data;
curr_state <= TAKE_TRAP;
end case;
when SUPERVISOR_RETURN =>
if( ( prv = USER_MODE ) or ( (mstatus(MSTATUS_TSR) = '1') and (prv = SUPERVISOR_MODE) ) ) then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ILLEGAL_INSTRUCTION;
tval <= zero_word & s_output_data;
curr_state <= TAKE_TRAP;
elsif( sepc(1 downto 0) /= "00" ) then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_INSTRUCTION_ADDRESS_MISALIGNED;
tval <= sepc;
curr_state <= TAKE_TRAP;
else
s_PC_next <= sepc;
pc <= x"0000000000000005";
load_reservation <= LOAD_RESERVATION_NONE;
mstatus(MSTATUS_SIE) <= mstatus(MSTATUS_SPIE);
mstatus(MSTATUS_SPIE) <= '1';
prv <= '0' & mstatus(MSTATUS_SPP);
mstatus(MSTATUS_SPP) <= '0';
curr_state <= execute_ret_state;
end if;
when MACHINE_RETURN =>
if( prv /= MACHINE_MODE ) then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ILLEGAL_INSTRUCTION;
tval <= zero_word & s_output_data;
curr_state <= TAKE_TRAP;
elsif( mepc(1 downto 0) /= "00" ) then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_INSTRUCTION_ADDRESS_MISALIGNED;
tval <= mepc;
curr_state <= TAKE_TRAP;
else
s_PC_next <= mepc;
pc <= x"0000000000000005";
load_reservation <= LOAD_RESERVATION_NONE;
mstatus(MSTATUS_MIE) <= mstatus(MSTATUS_MPIE);
mstatus(MSTATUS_MPIE) <= '1';
prv <= mstatus(MSTATUS_MPP_H downto MSTATUS_MPP_L);
mstatus(MSTATUS_MPP_H downto MSTATUS_MPP_L) <= USER_MODE;
curr_state <= execute_ret_state;
end if;
when ATOMIC_DO_LOAD =>
if( ((s_atomic_bytes = MEM_BYTES_8) and (s_atomic_address(2 downto 0) /= "000"))
or ((s_atomic_bytes = MEM_BYTES_4) and (s_atomic_address(1 downto 0) /= "00")) )
then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_STORE_AMO_ADDRESS_MISALIGNED;
tval <= s_atomic_address;
curr_state <= TAKE_TRAP;
else
curr_state <= MEM_A;
s_MMU_type <= MEM_LOAD;
s_MMU_input_addr <= s_atomic_address;
s_MMU_num_bytes <= s_atomic_bytes;
mem_ret_state <= ATOMIC_DO_OPERATION;
end if;
when ATOMIC_DO_OPERATION =>
if( s_atomic_bytes = MEM_BYTES_4 ) then
if( mem_ret_data(31) = '1' ) then
atomic_sext := ones_word & mem_ret_data( 31 downto 0 );
else
atomic_sext := zero_word & mem_ret_data( 31 downto 0 );
end if;
else
atomic_sext := mem_ret_data;
end if;
reg(reg_D) <= atomic_sext;
if( ( s_instr_code = instr_LRD ) or ( s_instr_code = instr_LRW ) ) then
load_reservation <= s_atomic_address;
curr_state <= execute_ret_state;
else
curr_state <= ATOMIC_DO_STORE;
if( (s_instr_code = instr_AMOSWAPD) or (s_instr_code = instr_AMOSWAPW) ) then
s_atomic_output <= reg(reg_B);
elsif( (s_instr_code = instr_AMOADDD) or (s_instr_code = instr_AMOADDW)) then
s_atomic_output <= reg(reg_B) + atomic_sext;
elsif( (s_instr_code = instr_AMOANDD) or (s_instr_code = instr_AMOANDW)) then
s_atomic_output <= reg(reg_B) and atomic_sext;
elsif( (s_instr_code = instr_AMOORD) or (s_instr_code = instr_AMOORW)) then
s_atomic_output <= reg(reg_B) or atomic_sext;
elsif( (s_instr_code = instr_AMOXORD) or (s_instr_code = instr_AMOXORW)) then
s_atomic_output <= reg(reg_B) xor atomic_sext;
elsif( (s_instr_code = instr_AMOXORD) or (s_instr_code = instr_AMOXORW)) then
s_atomic_output <= reg(reg_B) xor atomic_sext;
elsif( (s_instr_code = instr_AMOMAXD) or (s_instr_code = instr_AMOMAXW)) then
if( reg(reg_B) > atomic_sext ) then
s_atomic_output <= reg(reg_B);
else
s_atomic_output <= atomic_sext;
end if;
elsif( (s_instr_code = instr_AMOMIND) or (s_instr_code = instr_AMOMINW)) then
if( reg(reg_B) < atomic_sext ) then
s_atomic_output <= reg(reg_B);
else
s_atomic_output <= atomic_sext;
end if;
elsif( (s_instr_code = instr_AMOMAXUD) or (s_instr_code = instr_AMOMAXUW)) then
if( unsigned(reg(reg_B)) > unsigned(atomic_sext) ) then
s_atomic_output <= reg(reg_B);
else
s_atomic_output <= atomic_sext;
end if;
elsif( (s_instr_code = instr_AMOMINUD) or (s_instr_code = instr_AMOMINUW)) then
if( unsigned(reg(reg_B)) < unsigned(atomic_sext) ) then
s_atomic_output <= reg(reg_B);
else
s_atomic_output <= atomic_sext;
end if;
end if;
end if;
when ATOMIC_DO_STORE =>
s_MMU_input_addr <= s_atomic_address;
MMU_data_in <= s_atomic_output;
s_MMU_type <= MEM_STORE;
s_MMU_num_bytes <= s_atomic_bytes;
mem_ret_state <= execute_ret_state;
curr_state <= MEM_A;
when CSR_CHECK_ACCESS =>
csr_priv := to_integer(unsigned(s_csr_bits(9 downto 8)));
csr_read_only := s_csr_bits(11 downto 10);
csr_should_write := '0';
s_csr_should_write <= '0';
csr_type := s_functs(15 downto 13);
-- RW instructions always write, RS and RC do not write if not changing
-- which is if rs1 is zero register or bit field is all 0's
if( (csr_type = FUNC3_CSRRW) or (csr_type = FUNC3_CSRRWI) ) then
csr_should_write := '1';
s_csr_should_write <= '1';
elsif( (csr_type = FUNC3_CSRRS ) or (csr_type = FUNC3_CSRRC)
or (csr_type = FUNC3_CSRRSI) or (csr_type = FUNC3_CSRRCI)) then
if( reg_A /= 0 ) then
csr_should_write := '1';
s_csr_should_write <= '1';
end if;
end if;
-- if we want to write or just do not have access throw trap
if( ( (csr_should_write = '1') and (csr_read_only = CSR_RO) )
or ( to_integer(unsigned(prv)) < csr_priv ) )
then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ILLEGAL_INSTRUCTION;
tval <= zero_word & s_output_data;
curr_state <= TAKE_TRAP;
else
curr_state <= CSR_READ_CURRENT;
end if;
when CSR_READ_CURRENT =>
csr_error := '0';
case s_csr_bits is
when CSR_ADDR_CYCLE | CSR_ADDR_INSTRET | CSR_ADDR_MCYCLE | CSR_ADDR_MINSTRET =>
if( (scounteren(0) = '0') and prv = USER_MODE ) then
-- Error if user mode not allowed to read
csr_error := '1';
elsif( (mcounteren(0) = '0') and prv = SUPERVISOR_MODE ) then
-- Error if supervisor mode not allowed to read
csr_error := '1';
else
s_csr_old_value <= minstret;
end if;
when CSR_ADDR_HPMCOUNTER3 | CSR_ADDR_HPMCOUNTER4 | CSR_ADDR_HPMCOUNTER5 | CSR_ADDR_HPMCOUNTER6 | CSR_ADDR_HPMCOUNTER7 |
CSR_ADDR_HPMCOUNTER8 | CSR_ADDR_HPMCOUNTER9 | CSR_ADDR_HPMCOUNTER10 | CSR_ADDR_HPMCOUNTER11 | CSR_ADDR_HPMCOUNTER12 |
CSR_ADDR_HPMCOUNTER13| CSR_ADDR_HPMCOUNTER14 | CSR_ADDR_HPMCOUNTER15 | CSR_ADDR_HPMCOUNTER16 | CSR_ADDR_HPMCOUNTER17 |
CSR_ADDR_HPMCOUNTER18| CSR_ADDR_HPMCOUNTER19 | CSR_ADDR_HPMCOUNTER20 | CSR_ADDR_HPMCOUNTER21 | CSR_ADDR_HPMCOUNTER22 |
CSR_ADDR_HPMCOUNTER23| CSR_ADDR_HPMCOUNTER24 | CSR_ADDR_HPMCOUNTER25 | CSR_ADDR_HPMCOUNTER26 | CSR_ADDR_HPMCOUNTER27 |
CSR_ADDR_HPMCOUNTER28| CSR_ADDR_HPMCOUNTER29 | CSR_ADDR_HPMCOUNTER30 | CSR_ADDR_HPMCOUNTER31 =>
-- From notes: *counteren(x) needs to be checked, where x = 1 << integer(address(4 downto 0))
-- Since this is always a single bit, just convert directly to an integer and use it to index the register
-- Example: hpmcounter17 -> x = 1 << 17 = (0100000000000000000)_2. Or, just use bit 17.
if( (scounteren( to_integer(unsigned(s_csr_bits(4 downto 0))) ) = '0') and (prv = USER_MODE) ) then
-- Error if user mode not allowed to read
csr_error := '1';
elsif( (mcounteren( to_integer(unsigned(s_csr_bits(4 downto 0))) ) = '0') and prv = SUPERVISOR_MODE ) then
-- Error if supervisor mode not allowed to read
csr_error := '1';
else
s_csr_old_value <= ALL_ZERO;
end if;
when CSR_ADDR_SSTATUS =>
if( mstatus( 16 downto 15 ) = "11" or mstatus( 14 downto 13 ) = "11") then
s_csr_old_value <= mstatus and x"000000000005e122";
else
s_csr_old_value <= mstatus and x"800000000005e122";
end if;
when CSR_ADDR_SIE =>
s_csr_old_value <= mie and mideleg;
when CSR_ADDR_STVEC =>
s_csr_old_value <= stvec;
when CSR_ADDR_SCOUNTEREN =>
s_csr_old_value <= scounteren;
when CSR_ADDR_SSCRATCH =>
s_csr_old_value <= sscratch;
when CSR_ADDR_SEPC =>
s_csr_old_value <= sepc;
when CSR_ADDR_SCAUSE =>
s_csr_old_value <= scause;
when CSR_ADDR_STVAL =>
s_csr_old_value <= stval;
when CSR_ADDR_SIP =>
s_csr_old_value <= mip and mideleg;
when CSR_ADDR_SATP =>
if( mstatus( 20 ) = '1' and not (prv = MACHINE_MODE)) then
-- Error if not in machine mode
csr_error := '1';
else
s_csr_old_value <= satp;
end if;
when CSR_ADDR_MVENDORID =>
s_csr_old_value <= zero_word & zero_word;
when CSR_ADDR_MARCHID =>
s_csr_old_value <= zero_word & zero_word;
when CSR_ADDR_MIMPID =>
s_csr_old_value <= zero_word & zero_word;
when CSR_ADDR_MHARTID =>
s_csr_old_value <= zero_word & zero_word;
when CSR_ADDR_MSTATUS =>
s_csr_old_value <= mstatus;
when CSR_ADDR_MISA =>
s_csr_old_value <= isa;
when CSR_ADDR_MEDELEG =>
s_csr_old_value <= medeleg;
when CSR_ADDR_MIDELEG =>
s_csr_old_value <= mideleg;
when CSR_ADDR_MIE =>
s_csr_old_value <= mie;
when CSR_ADDR_MTVEC =>
s_csr_old_value <= mtvec;
when CSR_ADDR_MCOUNTEREN =>
s_csr_old_value <= mcounteren;
when CSR_ADDR_MSCRATCH =>
s_csr_old_value <= mscratch;
when CSR_ADDR_MEPC =>
s_csr_old_value <= mepc;
when CSR_ADDR_MCAUSE =>
s_csr_old_value <= mcause;
when CSR_ADDR_MTVAL =>
s_csr_old_value <= mtval;
when CSR_ADDR_MIP =>
s_csr_old_value <= mip;
when CSR_ADDR_MHPMCOUNTER3 | CSR_ADDR_MHPMCOUNTER4 | CSR_ADDR_MHPMCOUNTER5 | CSR_ADDR_MHPMCOUNTER6 |
CSR_ADDR_MHPMCOUNTER7 | CSR_ADDR_MHPMCOUNTER8 | CSR_ADDR_MHPMCOUNTER9 | CSR_ADDR_MHPMCOUNTER10 |
CSR_ADDR_MHPMCOUNTER11 | CSR_ADDR_MHPMCOUNTER12 | CSR_ADDR_MHPMCOUNTER13 | CSR_ADDR_MHPMCOUNTER14 |
CSR_ADDR_MHPMCOUNTER15 | CSR_ADDR_MHPMCOUNTER16 | CSR_ADDR_MHPMCOUNTER17 | CSR_ADDR_MHPMCOUNTER18 |
CSR_ADDR_MHPMCOUNTER19 | CSR_ADDR_MHPMCOUNTER20 | CSR_ADDR_MHPMCOUNTER21 | CSR_ADDR_MHPMCOUNTER22 |
CSR_ADDR_MHPMCOUNTER23 | CSR_ADDR_MHPMCOUNTER24 | CSR_ADDR_MHPMCOUNTER25 | CSR_ADDR_MHPMCOUNTER26 |
CSR_ADDR_MHPMCOUNTER27 | CSR_ADDR_MHPMCOUNTER28 | CSR_ADDR_MHPMCOUNTER29 | CSR_ADDR_MHPMCOUNTER30 |
CSR_ADDR_MHPMCOUNTER31 =>
s_csr_old_value <= ALL_ZERO;
when CSR_ADDR_MHPMEVENT3 | CSR_ADDR_MHPMEVENT4 | CSR_ADDR_MHPMEVENT5 | CSR_ADDR_MHPMEVENT6 |
CSR_ADDR_MHPMEVENT7 | CSR_ADDR_MHPMEVENT8 | CSR_ADDR_MHPMEVENT9 | CSR_ADDR_MHPMEVENT10 |
CSR_ADDR_MHPMEVENT11 | CSR_ADDR_MHPMEVENT12 | CSR_ADDR_MHPMEVENT13 | CSR_ADDR_MHPMEVENT14 |
CSR_ADDR_MHPMEVENT15 | CSR_ADDR_MHPMEVENT16 | CSR_ADDR_MHPMEVENT17 | CSR_ADDR_MHPMEVENT18 |
CSR_ADDR_MHPMEVENT19 | CSR_ADDR_MHPMEVENT20 | CSR_ADDR_MHPMEVENT21 | CSR_ADDR_MHPMEVENT22 |
CSR_ADDR_MHPMEVENT23 | CSR_ADDR_MHPMEVENT24 | CSR_ADDR_MHPMEVENT25 | CSR_ADDR_MHPMEVENT26 |
CSR_ADDR_MHPMEVENT27 | CSR_ADDR_MHPMEVENT28 | CSR_ADDR_MHPMEVENT29 | CSR_ADDR_MHPMEVENT30 |
CSR_ADDR_MHPMEVENT31 =>
s_csr_old_value <= ALL_ZERO;
when others =>
-- All others not implemented, set trap
csr_error := '1';
end case;
if( csr_error = '1' ) then
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ILLEGAL_INSTRUCTION;
tval <= zero_word & s_output_data;
curr_state <= TAKE_TRAP;
else
curr_state <= CSR_OPERATOR;
end if;
when CSR_OPERATOR =>
csr_type := s_functs(15 downto 13);
if( s_csr_should_write = '1' ) then
if( csr_type(2) = '0' ) then
csr_mask := reg(reg_A);
else
csr_mask := ALL_ZERO(63 downto 5) & s_rs1;
end if;
if( ('0' & csr_type(1 downto 0)) = FUNC3_CSRRW ) then
s_csr_mod_value <= csr_mask;
elsif( ('0' & csr_type(1 downto 0)) = FUNC3_CSRRC ) then
s_csr_mod_value <= s_csr_old_value and not csr_mask;
else
s_csr_mod_value <= s_csr_old_value or csr_mask;
end if;
curr_state <= CSR_WRITE_NEW;
else
curr_state <= CSR_WRITE_BACK;
end if;
when CSR_WRITE_NEW =>
curr_state <= CSR_WRITE_BACK;
case s_csr_bits is
when CSR_ADDR_MCYCLE | CSR_ADDR_MINSTRET =>
minstret <= s_csr_mod_value;
when CSR_ADDR_SSTATUS =>
mstatus(18) <= s_csr_mod_value(18); -- Update Smode portion of MSTATUS
mstatus(16 downto 15) <= s_csr_mod_value(16 downto 15);
mstatus(14 downto 13) <= s_csr_mod_value(14 downto 13);
mstatus(8) <= s_csr_mod_value(8);
mstatus(5) <= s_csr_mod_value(5);
mstatus(1) <= s_csr_mod_value(1);
when CSR_ADDR_SIE =>
mie(12) <= s_csr_mod_value(12) and mideleg(12);
mie(9) <= s_csr_mod_value(9) and mideleg(9);
mie(7) <= s_csr_mod_value(7) and mideleg(7);
mie(5) <= s_csr_mod_value(5) and mideleg(5);
mie(3) <= s_csr_mod_value(3) and mideleg(3);
mie(1) <= s_csr_mod_value(1) and mideleg(1);
when CSR_ADDR_STVEC =>
stvec(63 downto 2) <= s_csr_mod_value(63 downto 2);
when CSR_ADDR_SCOUNTEREN =>
scounteren <= s_csr_mod_value;
when CSR_ADDR_SSCRATCH =>
sscratch <= s_csr_mod_value;
when CSR_ADDR_SEPC =>
sepc <= s_csr_mod_value;
when CSR_ADDR_SCAUSE =>
scause <= s_csr_mod_value;
when CSR_ADDR_STVAL =>
stval <= s_csr_mod_value;
when CSR_ADDR_SIP =>
mip(1) <= s_csr_mod_value(1) and mideleg(1);
when CSR_ADDR_SATP =>
if( (s_csr_mod_value(63 downto 60) = "0000") or
(s_csr_mod_value(63 downto 60) = "1000") or
(s_csr_mod_value(63 downto 60) = "1001") ) then
satp(63 downto 60) <= s_csr_mod_value(63 downto 60);
satp(43 downto 0) <= s_csr_mod_value(43 downto 0);
end if;
when CSR_ADDR_MSTATUS =>
-- update status
if(s_csr_mod_value(14 downto 13) = "00") then -- if not dirty
mstatus(22 downto 17) <= s_csr_mod_value(22 downto 17);
mstatus(14 downto 11) <= s_csr_mod_value(14 downto 11);
mstatus( 8 ) <= s_csr_mod_value(8);
mstatus( 7 ) <= s_csr_mod_value(7);
mstatus( 5 ) <= s_csr_mod_value(5);
mstatus( 3 ) <= s_csr_mod_value(3);
mstatus( 1 ) <= s_csr_mod_value(1);
mstatus( 63 ) <= '0';
else
mstatus(22 downto 17) <= s_csr_mod_value(22 downto 17);
mstatus(14 downto 11) <= s_csr_mod_value(14 downto 11);
mstatus( 8 ) <= s_csr_mod_value(8);
mstatus( 7 ) <= s_csr_mod_value(7);
mstatus( 5 ) <= s_csr_mod_value(5);
mstatus( 3 ) <= s_csr_mod_value(3);
mstatus( 1 ) <= s_csr_mod_value(1);
mstatus( 63 ) <= '1';
end if;
when CSR_ADDR_MISA =>
when CSR_ADDR_MEDELEG =>
medeleg <= s_csr_mod_value;
when CSR_ADDR_MIDELEG =>
mideleg(12) <= s_csr_mod_value(12);
mideleg(9) <= s_csr_mod_value(9);
mideleg(5) <= s_csr_mod_value(5);
mideleg(1) <= s_csr_mod_value(1);
when CSR_ADDR_MIE =>
mie(12) <= s_csr_mod_value(12);
mie(9) <= s_csr_mod_value(9);
mie(7) <= s_csr_mod_value(7);
mie(5) <= s_csr_mod_value(5);
mie(3) <= s_csr_mod_value(3);
mie(1) <= s_csr_mod_value(1);
when CSR_ADDR_MTVEC =>
mtvec(63 downto 2) <= s_csr_mod_value(63 downto 2);
mtvec(0) <= s_csr_mod_value(0);
when CSR_ADDR_MCOUNTEREN =>
mcounteren <= s_csr_mod_value;
when CSR_ADDR_MSCRATCH =>
mscratch <= s_csr_mod_value;
when CSR_ADDR_MEPC =>
mepc <= s_csr_mod_value;
when CSR_ADDR_MCAUSE =>
mcause <= s_csr_mod_value;
when CSR_ADDR_MTVAL =>
mtval <= s_csr_mod_value;
when CSR_ADDR_MIP =>
mip(5) <= s_csr_mod_value(5);
mip(1) <= s_csr_mod_value(1);
when others =>
-- Do nothing, if were going to trap would have already happened
end case;
when CSR_WRITE_BACK =>
reg(reg_D) <= s_csr_old_value;
curr_state <= execute_ret_state;
when FINISH_UP =>
minstret <= minstret + 1;
reg(0) <= ALL_ZERO;
if( pc = s_PC_next ) then
pc <= pc + 4;
else
pc <= s_PC_next;
end if;
if( prv = "10" ) then
prv <= USER_MODE;
end if;
curr_state <= CHECK_INTERRUPT;
when DEBUG_DUMP =>
s_debug_write_dwrod_ret <= DEBUG_DUMP_REG;
curr_state <= DEBUG_WRITE_DWORD;
s_debug_dword_out <= x"005A0A5ADEADBEEF"; -- debugger magic sequence
s_debug_index <= 0;
s_debug_reg_index <= 0;
when DEBUG_DUMP_REG =>
if( s_debug_reg_index = 32 ) then
s_debug_reg_index <= 0;
curr_state <= DEBUG_DUMP_CSR;
else
s_debug_write_dwrod_ret <= DEBUG_DUMP_REG;
curr_state <= DEBUG_WRITE_DWORD;
s_debug_index <= 0;
s_debug_dword_out <= reg(s_debug_reg_index);
s_debug_reg_index <= s_debug_reg_index + 1;
end if;
when DEBUG_DUMP_CSR =>
if( s_debug_reg_index = 27 ) then
s_debug_reg_index <= 0;
s_debug_byte <= DEBUG_COMMAND_NONE;
curr_state <= DEBUG_GET_COMMAND;
else
s_debug_write_dwrod_ret <= DEBUG_DUMP_CSR;
curr_state <= DEBUG_WRITE_DWORD;
s_debug_index <= 0;
s_debug_dword_out <= csr(s_debug_reg_index);
s_debug_reg_index <= s_debug_reg_index + 1;
end if;
when DEBUG_GET_COMMAND =>
s_debug_index <= 0;
s_debug_reg_index <= 0;
curr_state <= DEBUG_READ_UART;
if( s_debug_byte = DEBUG_COMMAND_STEP) then
curr_state <= DEBUG_DO_COMMAND_STEP;
elsif( s_debug_byte = DEBUG_COMMAND_CONT ) then
curr_state <= DEBUG_DO_COMMAND_CONTINUE;
elsif( s_debug_byte = DEBUG_COMMAND_PHYS ) then
s_debug_uart_ret <= DEBUG_GET_ADDRESS;
s_debug_get_addr_ret <= DEBUG_DO_COMMAND_PHYS;
elsif( s_debug_byte = DEBUG_COMMAND_VIRT ) then
s_debug_uart_ret <= DEBUG_GET_ADDRESS;
s_debug_get_addr_ret <= DEBUG_DO_COMMAND_VIRT;
else
s_debug_uart_ret <= DEBUG_GET_COMMAND;
end if;
when DEBUG_GET_ADDRESS =>
-- addresses sent in big endian
s_debug_bytes(s_debug_index) <= s_debug_byte;
s_debug_index <= s_debug_index + 1;
if( s_debug_index = 7 ) then
s_debug_index <= 0;
s_debug_address <= s_debug_bytes(0) & s_debug_bytes(1) & s_debug_bytes(2) & s_debug_bytes(3)
& s_debug_bytes(4) & s_debug_bytes(5) & s_debug_bytes(6) & s_debug_byte;
curr_state <= s_debug_get_addr_ret;
else
s_debug_uart_ret <= DEBUG_GET_ADDRESS;
curr_state <= DEBUG_READ_UART;
end if;
when DEBUG_WRITE_DWORD =>
if( s_debug_index = 0) then
s_debug_byte <= s_debug_dword_out(63 downto 56);
s_debug_bytes(1) <= s_debug_dword_out(55 downto 48);
s_debug_bytes(2) <= s_debug_dword_out(47 downto 40);
s_debug_bytes(3) <= s_debug_dword_out(39 downto 32);
s_debug_bytes(4) <= s_debug_dword_out(31 downto 24);
s_debug_bytes(5) <= s_debug_dword_out(23 downto 16);
s_debug_bytes(6) <= s_debug_dword_out(15 downto 8);
s_debug_bytes(7) <= s_debug_dword_out(7 downto 0);
else
s_debug_byte <= s_debug_bytes(s_debug_index);
end if;
s_debug_index <= s_debug_index + 1;
curr_state <= DEBUG_WRITE_UART;
s_debug_uart_ret <= DEBUG_WRITE_DWORD;
if( s_debug_index = 7 ) then
s_debug_uart_ret <= s_debug_write_dwrod_ret;
s_debug_index <= 0;
end if;
when DEBUG_DO_COMMAND_STEP =>
s_debug_break <= '1';
s_debug_access <= '0';
curr_state <= EXECUTE;
when DEBUG_DO_COMMAND_CONTINUE =>
s_debug_break <= '0';
s_debug_access <= '0';
curr_state <= EXECUTE;
when DEBUG_DO_COMMAND_PHYS =>
s_debug_phys_address <= s_debug_address;
curr_state <= DEBUG_DUMP;
when DEBUG_DO_COMMAND_VIRT =>
s_debug_virt_address <= s_debug_address;
curr_state <= DEBUG_DUMP;
when DEBUG_READ_UART =>
mem_ret_data <= ALL_ZERO;
curr_state <= DEBUG_READ_UART_RDY;
when DEBUG_READ_UART_RDY =>
if( mem_ret_data(0) = '1' ) then
curr_state <= DEBUG_READ_UART_DATA;
else
curr_state <= MEM_A;
s_MMU_type <= MEM_LOAD;
s_MMU_input_addr <= UART_RX_READY;
s_MMU_num_bytes <= MEM_BYTES_1;
mem_ret_state <= DEBUG_READ_UART_RDY;
end if;
when DEBUG_READ_UART_DATA =>
curr_state <= MEM_A;
s_MMU_type <= MEM_LOAD;
s_MMU_input_addr <= UART_RX_DATA;
s_MMU_num_bytes <= MEM_BYTES_1;
mem_ret_state <= DEBUG_READ_UART_DONE;
when DEBUG_READ_UART_DONE =>
s_debug_byte <= mem_ret_data(7 downto 0);
s_MMU_input_addr <= UART_RX_RESET;
MMU_data_in <= ALL_ZERO(63 downto 1) & '1';
s_MMU_type <= MEM_STORE;
s_MMU_num_bytes <= MEM_BYTES_1;
mem_ret_state <= s_debug_uart_ret;
curr_state <= MEM_A;
when DEBUG_WRITE_UART =>
mem_ret_data <= ALL_ZERO;
curr_state <= DEBUG_WRITE_UART_RDY;
when DEBUG_WRITE_UART_RDY =>
if( mem_ret_data(0) = '1' ) then
curr_state <= DEBUG_WRITE_UART_DATA;
else
curr_state <= MEM_A;
s_MMU_type <= MEM_LOAD;
s_MMU_input_addr <= UART_TX_READY;
s_MMU_num_bytes <= MEM_BYTES_1;
mem_ret_state <= DEBUG_WRITE_UART_RDY;
end if;
when DEBUG_WRITE_UART_DATA =>
s_MMU_input_addr <= UART_TX_DATA;
MMU_data_in <= ALL_ZERO(63 downto 8) & s_debug_byte;
s_MMU_type <= MEM_STORE;
s_MMU_num_bytes <= MEM_BYTES_1;
mem_ret_state <= DEBUG_WRITE_UART_DONE;
curr_state <= MEM_A;
when DEBUG_WRITE_UART_DONE =>
s_MMU_input_addr <= UART_TX_SEND;
MMU_data_in <= ALL_ZERO(63 downto 1) & '1';
s_MMU_type <= MEM_STORE;
s_MMU_num_bytes <= MEM_BYTES_1;
mem_ret_state <= s_debug_uart_ret;
curr_state <= MEM_A;
when others =>
-- trap for unknown state
cause <= CAUSE_EXCEPTION_HIGH & CAUSE_ILLEGAL_INSTRUCTION;
tval <= x"DEADBEEFDEADBEEF";
curr_state <= TAKE_TRAP;
end case;
if('1' = rst) then
curr_state <= INIT;
init_counter <= 0;
end if;
end if; end process;
-- Map outbound signals
status <= MMU_done;
MMU_addr_in <= s_MMU_input_addr; -- 64-bits address for load/store
MMU_satp <= satp; -- Signals address translation privilege
MMU_type <= s_MMU_type; -- High to toggle store
MMU_num_bytes <= s_MMU_num_bytes; -- alignment in bytes
SUM <= mstatus(MSTATUS_SUM);
MXR <= mstatus(MSTATUS_MXR);
mip(MIP_MTIP) <= MTIP;
mip(MIP_MSIP) <= MSIP;
csr(CSR_ISA) <= isa;
csr(CSR_PRV) <= ALL_ZERO(63 downto 2) & prv;
csr(CSR_MSTATUS) <= mstatus;
csr(CSR_MEPC) <= mepc;
csr(CSR_MTVAL) <= mtval;
csr(CSR_MSCRATCH) <= mscratch;
csr(CSR_MTVEC) <= mtvec;
csr(CSR_MCAUSE) <= mcause;
csr(CSR_MINSTRET) <= minstret;
csr(CSR_MIE) <= mie;
csr(CSR_MIP) <= mip;
csr(CSR_MEDELEG) <= medeleg;
csr(CSR_MIDELEG) <= mideleg;
csr(CSR_MCOUNTEREN) <= mcounteren;
csr(CSR_SCOUNTEREN) <= scounteren;
csr(CSR_SEPC) <= sepc;
csr(CSR_STVAL) <= stval;
csr(CSR_SSCRATCH) <= sscratch;
csr(CSR_STVEC) <= stvec;
csr(CSR_SATP) <= satp;
csr(CSR_SCAUSE) <= scause;
csr(CSR_LOAD_RES) <= load_reservation;
csr(CSR_DBG_PHYS) <= s_debug_phys_address;
csr(CSR_DBG_VIRT) <= s_debug_virt_address;
csr(CSR_MMU_PHYS) <= MMU_debug_phys;
csr(CSR_MMU_VIRT) <= MMU_debug_virt;
csr(CSR_INSTR) <= zero_word & s_save_instr;
-- Normal registers --
reg_zero <= reg(0);
reg_ra <= reg(1);
reg_sp <= reg(2);
reg_gp <= reg(3);
reg_tp <= reg(4);
reg_t0 <= reg(5);
reg_t1 <= reg(6);
reg_t2 <= reg(7);
reg_s0_fp <= reg(8);
reg_s1 <= reg(9);
reg_a0 <= reg(10);
reg_a1 <= reg(11);
reg_a2 <= reg(12);
reg_a3 <= reg(13);
reg_a4 <= reg(14);
reg_a5 <= reg(15);
reg_a6 <= reg(16);
reg_a7 <= reg(17);
reg_s2 <= reg(18);
reg_s3 <= reg(19);
reg_s4 <= reg(20);
reg_s5 <= reg(21);
reg_s6 <= reg(22);
reg_s7 <= reg(23);
reg_s8 <= reg(24);
reg_s9 <= reg(25);
reg_s10 <= reg(26);
reg_s11 <= reg(27);
reg_t3 <= reg(28);
reg_t4 <= reg(29);
reg_t5 <= reg(30);
reg_t6 <= reg(31);
end Behavioral;
| mit | 54a6b7bf3c135751636d6fed08f19aa6 | 0.434564 | 4.239914 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/stub_ram_int.vhd | 1 | 3,275 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity stub_ram_int is
Port ( memAddress : in STD_LOGIC_VECTOR (26 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
valid : in STD_LOGIC;
done : out STD_LOGIC;
write : in STD_LOGIC;
chip_select : in STD_LOGIC;
err : out STD_LOGIC;
clk, reset : in STD_LOGIC );
end stub_ram_int;
architecture Behavioral of stub_ram_int is
component stub_ram
port(
address : in STD_LOGIC_VECTOR (13 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal s_mem_address : STD_LOGIC_VECTOR (13 downto 0);
signal s_data_in : STD_LOGIC_VECTOR (7 downto 0);
signal s_mem_clock : STD_LOGIC;
signal s_write : STD_LOGIC;
signal s_mem_data_out : STD_LOGIC_VECTOR (7 downto 0);
type memState is ( WAITING, INVALID_REQUEST, MEM_CLOCK, FINISH );
signal curr_state : memState;
begin
MEM : stub_ram
port map ( address => s_mem_address,
clock => s_mem_clock,
we => s_write,
dataIn => s_data_in,
dataOut => s_mem_data_out);
process( clk, reset )
begin
if ( reset = '1' ) then
err <= '0';
done <= '0';
curr_state <= WAITING;
elsif ( rising_edge( clk ) ) then
case curr_state is
when WAITING =>
s_mem_clock <= '0';
done <= '0';
err <= '0';
if( (valid = '1') and (chip_select = '1') ) then
if( (memAddress < x"0700000") and (memAddress >= x"06FC000") ) then
s_mem_address <= memAddress(13 downto 0);
s_data_in <= dataIn;
s_write <= write;
curr_state <= MEM_CLOCK;
else
curr_state <= INVALID_REQUEST;
end if;
end if;
when INVALID_REQUEST =>
err <= '1';
done <= '1';
if( valid = '0' ) then
curr_state <= WAITING;
end if;
when MEM_CLOCK =>
s_mem_clock <= '1';
curr_state <= FINISH;
when FINISH =>
done <= '1';
err <= '0';
dataOut <= s_mem_data_out;
if( valid = '0' ) then
curr_state <= WAITING;
end if;
end case;
end if;
end process;
end Behavioral;
| mit | 2b7d59b299eb45c54d4e850a386eb0bc | 0.404275 | 4.474044 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/remote_sources/_/lib/digilent/InputSync.vhd | 1 | 2,247 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:35 11/15/2010
-- Design Name:
-- Module Name: InputSync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity InputSync is
Port ( D_I : in STD_LOGIC;
D_O : out STD_LOGIC;
CLK_I : in STD_LOGIC);
end InputSync;
architecture Behavioral of InputSync is
signal sreg : std_logic_vector(1 downto 0);
attribute TIG : string;
attribute IOB : string;
attribute ASYNC_REG : string;
attribute SHIFT_EXTRACT : string;
attribute HBLKNM : string;
attribute TIG of D_I : signal is "TRUE";
attribute IOB of D_I : signal is "FALSE";
attribute ASYNC_REG of sreg : signal is "TRUE";
attribute SHIFT_EXTRACT of sreg : signal is "NO";
attribute HBLKNM of sreg : signal is "sync_reg";
begin
process (CLK_I)
begin
if Rising_Edge(CLK_I) then
D_O <= sreg(1);
sreg <= sreg(0) & D_I;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity InputSyncV is
Port ( D_I : in STD_LOGIC_VECTOR;
D_O : out STD_LOGIC_VECTOR;
CLK_I : in STD_LOGIC);
end InputSyncV;
architecture Behavioral of InputSyncV is
component InputSync is
Port ( D_I : in STD_LOGIC;
D_O : out STD_LOGIC;
CLK_I : in STD_LOGIC);
end component;
signal sreg : std_logic_vector(1 downto 0);
attribute TIG : string;
attribute IOB : string;
attribute ASYNC_REG : string;
attribute SHIFT_EXTRACT : string;
attribute HBLKNM : string;
attribute TIG of D_I : signal is "TRUE";
attribute IOB of D_I : signal is "FALSE";
attribute ASYNC_REG of sreg : signal is "TRUE";
attribute SHIFT_EXTRACT of sreg : signal is "NO";
attribute HBLKNM of sreg : signal is "sync_reg";
begin
gen_bits: for i in D_I'high downto D_I'low generate
gen_bit: InputSync PORT MAP (
D_I => D_I(i),
D_O => D_O(D_O'high-(D_I'high-i)),
CLK_I => CLK_I
);
end generate;
end Behavioral;
| gpl-3.0 | 7dd8c34a0a8f16f644ed6eb7dd656b0a | 0.609257 | 3.358744 | false | false | false | false |
SLongofono/Senior_Design_Capstone | simple_core/regfile.vhd | 2 | 2,369 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/27/2017 08:36:56 AM
-- Module Name: regfile - Behavioral
-- Description:
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity regfile is
Port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end regfile;
architecture Behavioral of regfile is
-- Contents of regfile, all zeros
signal reggie: regfile_arr := (others => (others => '0'));
begin
-- Synchronous write
process(clk, rst)
begin
if('1' = halt) then
-- Do nothing
else
write_error <= '0';
if('1' = rst) then
reggie <= (others => (others => '0'));
elsif(rising_edge(clk)) then
if('1' = write_en) then
if("00000" = write_addr) then
write_error <= '1';
else
reggie(to_integer(unsigned(write_addr))) <= write_data;
end if; -- write_error
end if; -- write_en
end if; -- rst
end if; -- halt
end process;
-- Asynchronous read
read_data_1 <= reggie(to_integer(unsigned(read_addr_1)));
read_data_2 <= reggie(to_integer(unsigned(read_addr_2)));
-- Asynchronous debug out
debug_out <= reggie;
end Behavioral; | mit | ed330a57d09b0954a318c268bb5be646 | 0.502744 | 4.112847 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/EthLayerTx.vhd | 1 | 6,245 | ---------------------------------------------------------------------------------
-- Title : Ethernet Layer TX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : EthFrameTx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to GTP interface to 1000 BASE X Ethernet.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity EthFrameTx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl := '0';
-- Data for the header
ethTxDestMac : in MacAddrType := MAC_ADDR_DEFAULT_C;
ethTxSrcMac : in MacAddrType := MAC_ADDR_INIT_C;
ethTxEtherType : in EtherType;
-- User data to be sent
ethTxDataIn : in slv(7 downto 0);
ethTxDataValid : in sl;
ethTxDataLastByte : in sl;
ethTxDataReady : out sl;
-- Data output
macTxDataOut : out slv(7 downto 0);
macTxDataValid : out sl;
macTxDataLastByte : out sl;
macTxDataReady : in sl
);
end EthFrameTx;
architecture rtl of EthFrameTx is
type StateType is (IDLE_S, DEST_MAC_S, SRC_MAC_S, ETHERTYPE_S, DATA_S);
type RegType is record
state : StateType;
ethTxDestMac : MacAddrType;
ethTxSrcMac : MacAddrType;
ethTxEtherType : EtherType;
ethTxDataReady : sl;
macTxDataOut : slv(7 downto 0);
macTxDataValid : sl;
macTxDataLastByte : sl;
byteCounter : slv(3 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
ethTxDestMac => MAC_ADDR_INIT_C,
ethTxSrcMac => MAC_ADDR_INIT_C,
ethTxEtherType => (others => '0'),
ethTxDataReady => '0',
macTxDataOut => (others => '0'),
macTxDataValid => '0',
macTxDataLastByte => '0',
byteCounter => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethTxRst,ethTxDestMac,ethTxSrcMac,ethTxEtherType,
ethTxDataIn,ethTxDataValid,ethTxDataLastByte,
macTxDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
ethTxDataReady <= '0';
v.ethTxDataReady := '0';
v.macTxDataValid := '0';
v.macTxDataLastByte := '0';
-- State machine
-- if (macTxDataReady = '1') then
case(r.state) is
when IDLE_S =>
if (ethTxDataValid = '1' and macTxDataReady = '1') then
v.ethTxDestMac := ethTxDestMac;
v.ethTxSrcMac := ethTxSrcMac;
v.ethTxEtherType := ethTxEtherType;
v.byteCounter := (others => '0');
v.state := DEST_MAC_S;
end if;
when DEST_MAC_S =>
v.macTxDataOut := r.ethTxDestMac(5-conv_integer(r.byteCounter));
v.macTxDataValid := '1';
if (macTxDataReady = '1') then
v.byteCounter := r.byteCounter + 1;
--v.macTxDataOut := r.ethTxDestMac(5-conv_integer(v.byteCounter));
if (r.byteCounter = 5) then
v.byteCounter := (others => '0');
v.state := SRC_MAC_S;
end if;
end if;
when SRC_MAC_S =>
v.macTxDataOut := r.ethTxSrcMac(5-conv_integer(r.byteCounter));
v.macTxDataValid := '1';
if (macTxDataReady = '1') then
v.byteCounter := r.byteCounter + 1;
if (r.byteCounter = 5) then
v.byteCounter := (others => '0');
v.state := ETHERTYPE_S;
end if;
end if;
when ETHERTYPE_S =>
v.macTxDataOut := getByte(1-conv_integer(r.byteCounter),r.ethTxEtherType);
v.macTxDataValid := '1';
if (macTxDataReady = '1') then
v.byteCounter := r.byteCounter + 1;
if (r.byteCounter = 1) then
v.ethTxDataReady := macTxDataReady;
v.byteCounter := (others => '0');
v.state := DATA_S;
end if;
end if;
when DATA_S =>
ethTxDataReady <= macTxDataReady;
v.ethTxDataReady := macTxDataReady;
v.macTxDataOut := ethTxDataIn;
v.macTxDataValid := ethTxDataValid;
v.macTxDataLastByte := ethTxDataLastByte;
if (r.macTxDataValid = '1' and r.macTxDataLastByte = '1' and macTxDataReady = '1') then
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- end if;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
-- ethTxDataReady <= r.ethTxDataReady;
macTxDataOut <= r.macTxDataOut;
macTxDataValid <= r.macTxDataValid;
macTxDataLastByte <= r.macTxDataLastByte;
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 4c4f776fa00eb57832c6d4e9d48cab5b | 0.500721 | 4.467096 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/vic_ii.vhd | 1 | 33,498 | ----------------------------------------------------------------------------------
--
-- VIC II simulator
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end vic_ii;
architecture vic_ii_impl of vic_ii is
attribute ram_style : string;
attribute gated_clock : string;
attribute fsm_encoding : string;
--attribute gated_clock of clk20_ph1 : signal is "true";
--attribute gated_clock of clk20_ph2 : signal is "true";
subtype sl is std_logic;
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype u6 is unsigned(5 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u9 is unsigned(8 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype cgptr is std_logic_vector(11 downto 0);
subtype dword is std_logic_vector(31 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype long is unsigned(31 downto 0);
subtype v_addr is std_logic_vector(13 downto 0);
subtype c_addr is std_logic_vector(9 downto 0);
subtype r_addr is std_logic_vector(5 downto 0);
type vregs is array(46 downto 0) of byte;
signal vic_regs : vregs := (
others => x"00"
);
attribute ram_style of vic_regs : signal is "registers";
alias vic_M0X : byte is vic_regs( 0);
alias vic_M0X8 : sl is vic_regs(16)(0);
alias vic_M1X : byte is vic_regs( 1);
alias vic_M1X8 : sl is vic_regs(16)(1);
alias vic_M2X : byte is vic_regs( 2);
alias vic_M2X8 : sl is vic_regs(16)(2);
alias vic_M3X : byte is vic_regs( 3);
alias vic_M3X8 : sl is vic_regs(16)(3);
alias vic_M4X : byte is vic_regs( 4);
alias vic_M4X8 : sl is vic_regs(16)(4);
alias vic_M5X : byte is vic_regs( 5);
alias vic_M5X8 : sl is vic_regs(16)(5);
alias vic_M6X : byte is vic_regs( 6);
alias vic_M6X8 : sl is vic_regs(16)(6);
alias vic_M7X : byte is vic_regs( 7);
alias vic_M7X8 : sl is vic_regs(16)(7);
alias vic_M0Y : byte is vic_regs( 8);
alias vic_M1Y : byte is vic_regs( 9);
alias vic_M2Y : byte is vic_regs(10);
alias vic_M3Y : byte is vic_regs(11);
alias vic_M4Y : byte is vic_regs(12);
alias vic_M5Y : byte is vic_regs(13);
alias vic_M6Y : byte is vic_regs(14);
alias vic_M7Y : byte is vic_regs(15);
alias vic_YSCROLL : slv3 is vic_regs(17)(2 downto 0);
alias vic_RSEL : sl is vic_regs(17)(3);
alias vic_DEN : sl is vic_regs(17)(4);
alias vic_BMM : sl is vic_regs(17)(5);
alias vic_ECM : sl is vic_regs(17)(6);
alias vic_RST8 : sl is vic_regs(17)(7);
alias vic_RASTER : byte is vic_regs(18);
alias vic_LPX : byte is vic_regs(19);
alias vic_LPY : byte is vic_regs(20);
alias vic_M0E : sl is vic_regs(21)(0);
alias vic_M1E : sl is vic_regs(21)(1);
alias vic_M2E : sl is vic_regs(21)(2);
alias vic_M3E : sl is vic_regs(21)(3);
alias vic_M4E : sl is vic_regs(21)(4);
alias vic_M5E : sl is vic_regs(21)(5);
alias vic_M6E : sl is vic_regs(21)(6);
alias vic_M7E : sl is vic_regs(21)(7);
alias vic_XSCROLL : slv3 is vic_regs(22)(2 downto 0);
alias vic_CSEL : sl is vic_regs(22)(3);
alias vic_MCM : sl is vic_regs(22)(4);
alias vic_RES : sl is vic_regs(22)(5);
alias vic_M0YE : sl is vic_regs(23)(0);
alias vic_M1YE : sl is vic_regs(23)(1);
alias vic_M2YE : sl is vic_regs(23)(2);
alias vic_M3YE : sl is vic_regs(23)(3);
alias vic_M4YE : sl is vic_regs(23)(4);
alias vic_M5YE : sl is vic_regs(23)(5);
alias vic_M6YE : sl is vic_regs(23)(6);
alias vic_M7YE : sl is vic_regs(23)(7);
alias vic_CB : slv3 is vic_regs(24)(3 downto 1);
alias vic_VM : nybble is vic_regs(24)(7 downto 4);
alias vic_IRQ : sl is vic_regs(25)(7);
alias vic_ILP : sl is vic_regs(25)(3);
alias vic_IMMC : sl is vic_regs(25)(2);
alias vic_IMBC : sl is vic_regs(25)(1);
alias vic_IRST : sl is vic_regs(25)(0);
alias vic_ELP : sl is vic_regs(26)(3);
alias vic_EMMC : sl is vic_regs(26)(2);
alias vic_EMBC : sl is vic_regs(26)(1);
alias vic_ERST : sl is vic_regs(26)(0);
alias vic_M0DP : sl is vic_regs(27)(0);
alias vic_M1DP : sl is vic_regs(27)(1);
alias vic_M2DP : sl is vic_regs(27)(2);
alias vic_M3DP : sl is vic_regs(27)(3);
alias vic_M4DP : sl is vic_regs(27)(4);
alias vic_M5DP : sl is vic_regs(27)(5);
alias vic_M6DP : sl is vic_regs(27)(6);
alias vic_M7DP : sl is vic_regs(27)(7);
alias vic_M0MC : sl is vic_regs(28)(0);
alias vic_M1MC : sl is vic_regs(28)(1);
alias vic_M2MC : sl is vic_regs(28)(2);
alias vic_M3MC : sl is vic_regs(28)(3);
alias vic_M4MC : sl is vic_regs(28)(4);
alias vic_M5MC : sl is vic_regs(28)(5);
alias vic_M6MC : sl is vic_regs(28)(6);
alias vic_M7MC : sl is vic_regs(28)(7);
alias vic_M0XE : sl is vic_regs(29)(0);
alias vic_M1XE : sl is vic_regs(29)(1);
alias vic_M2XE : sl is vic_regs(29)(2);
alias vic_M3XE : sl is vic_regs(29)(3);
alias vic_M4XE : sl is vic_regs(29)(4);
alias vic_M5XE : sl is vic_regs(29)(5);
alias vic_M6XE : sl is vic_regs(29)(6);
alias vic_M7XE : sl is vic_regs(29)(7);
alias vic_M0M : sl is vic_regs(30)(0);
alias vic_M1M : sl is vic_regs(30)(1);
alias vic_M2M : sl is vic_regs(30)(2);
alias vic_M3M : sl is vic_regs(30)(3);
alias vic_M4M : sl is vic_regs(30)(4);
alias vic_M5M : sl is vic_regs(30)(5);
alias vic_M6M : sl is vic_regs(30)(6);
alias vic_M7M : sl is vic_regs(30)(7);
alias vic_M0D : sl is vic_regs(31)(0);
alias vic_M1D : sl is vic_regs(31)(1);
alias vic_M2D : sl is vic_regs(31)(2);
alias vic_M3D : sl is vic_regs(31)(3);
alias vic_M4D : sl is vic_regs(31)(4);
alias vic_M5D : sl is vic_regs(31)(5);
alias vic_M6D : sl is vic_regs(31)(6);
alias vic_M7D : sl is vic_regs(31)(7);
alias vic_EC : nybble is vic_regs(32)(3 downto 0);
alias vic_B0C : nybble is vic_regs(33)(3 downto 0);
alias vic_B1C : nybble is vic_regs(34)(3 downto 0);
alias vic_B2C : nybble is vic_regs(35)(3 downto 0);
alias vic_B3C : nybble is vic_regs(36)(3 downto 0);
alias vic_MM0 : nybble is vic_regs(37)(3 downto 0);
alias vic_MM1 : nybble is vic_regs(38)(3 downto 0);
alias vic_M0C : nybble is vic_regs(39)(3 downto 0);
alias vic_M1C : nybble is vic_regs(40)(3 downto 0);
alias vic_M2C : nybble is vic_regs(41)(3 downto 0);
alias vic_M3C : nybble is vic_regs(42)(3 downto 0);
alias vic_M4C : nybble is vic_regs(43)(3 downto 0);
alias vic_M5C : nybble is vic_regs(44)(3 downto 0);
alias vic_M6C : nybble is vic_regs(45)(3 downto 0);
alias vic_M7C : nybble is vic_regs(46)(3 downto 0);
type clist is array(15 downto 0) of byte;
constant vc_red : clist := (
0=>x"00", 1=>x"FF", 2=>x"a1", 3=>x"6a", 4=>x"a2", 5=>x"5c", 6=>x"50", 7=>x"cb",
8=>x"a3", 9=>x"6e", 10=>x"cc", 11=>x"63", 12=>x"8b", 13=>x"9b", 14=>x"8a", 15=>x"af"
);
constant vc_green : clist := (
0=>x"00", 1=>x"FF", 2=>x"4d", 3=>x"c1", 4=>x"57", 5=>x"ad", 6=>x"44", 7=>x"d6",
8=>x"68", 9=>x"53", 10=>x"7f", 11=>x"63", 12=>x"8b", 13=>x"e3", 14=>x"7f", 15=>x"af"
);
constant vc_blue : clist := (
0=>x"00", 1=>x"FF", 2=>x"43", 3=>x"c8", 4=>x"a5", 5=>x"5f", 6=>x"9c", 7=>x"89",
8=>x"3a", 9=>x"0b", 10=>x"76", 11=>x"63", 12=>x"8b", 13=>x"9d", 14=>x"cd", 15=>x"af"
);
function vcolor_r(color : nybble) return byte is
begin return vc_red(to_integer(unsigned(color))); end vcolor_r;
function vcolor_g(color : nybble) return byte is
begin return vc_green(to_integer(unsigned(color))); end vcolor_g;
function vcolor_b(color : nybble) return byte is
begin return vc_blue(to_integer(unsigned(color))); end vcolor_b;
function count3(org: slv3) return slv3 is
begin
case org is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end count3;
function clk20ph_count(org: u6) return u6 is
begin
case org is
when "000000" => return "000001";
when "000001" => return "000010";
when "000010" => return "000011";
when "000011" => return "000100";
when "000100" => return "000101";
when "000101" => return "000110";
when "000110" => return "000111";
when "000111" => return "001000";
when "001000" => return "001001";
when "001001" => return "010000";
when "010000" => return "010001";
when "010001" => return "010010";
when "010010" => return "010011";
when "010011" => return "010100";
when "010100" => return "010101";
when "010101" => return "010110";
when "010110" => return "010111";
when "010111" => return "011000";
when "011000" => return "011001";
when "011001" => return "100000";
when "100000" => return "100001";
when "100001" => return "100010";
when "100010" => return "100011";
when "100011" => return "100100";
when "100100" => return "100101";
when "100101" => return "100110";
when "100110" => return "100111";
when "100111" => return "101000";
when "101000" => return "101001";
when "101001" => return "110000";
when "110000" => return "110001";
when "110001" => return "110010";
when "110010" => return "110011";
when "110011" => return "110100";
when "110100" => return "110101";
when "110101" => return "110110";
when "110110" => return "110111";
when "110111" => return "111000";
when "111000" => return "111001";
when "111001" => return "000000";
when others => return "000000";
end case;
end clk20ph_count;
signal clk20_12 : std_logic;
signal clk20ph : u6 := "001001";
attribute fsm_encoding of clk20ph : signal is "sequential";
signal clk20stg : pair;
signal clk20tik : nybble := "0000";
signal cpuclk : std_logic;
signal ph0 : std_logic;
signal ph1 : std_logic;
signal ph2 : std_logic;
signal cpu_slice : std_logic;
signal vic_slice : std_logic;
signal rapos_V : u16 := "0000000000000000";
signal rapos_H : u16 := "0000000000000000";
signal vis_V : u16;
signal vis_H : u16;
signal win_V : u16;
signal win_H : u16;
signal regras_v : u9;
signal vbdr : std_logic;
signal hbdr : std_logic;
signal bdr : std_logic;
signal en_V : std_logic;
signal en_H : std_logic;
signal en : std_logic;
signal cell_h : ubyte;
signal cell_v : ubyte;
signal cell_ph : ubyte;
signal cell_pv : ubyte;
signal rg_o : byte;
signal rg_i : byte;
function d_to_slv(arg : long) return dword is
begin
return dword(arg);
end d_to_slv;
-- line pixel/color registers
subtype slin is std_logic_vector(23 downto 0);
subtype sptr_t is std_logic_vector(13 downto 0);
type cline is array(39 downto 0) of nybble;
type bline is array(39 downto 0) of byte;
type sptr is array(7 downto 0) of sptr_t;
type sdata is array(7 downto 0) of slin;
signal line_pix : std_logic_vector(319 downto 0) := (others => '0'); -- pixels
signal line_c : cline := (others => x"f"); -- color
signal line_b : bline := (others => x"ff"); -- block (character)
signal line_sprs : sdata := (others => x"000000"); -- sprites
signal spr_ptr : sptr := (others => "00000000000000");
function u8toi(src: ubyte) return integer is
begin
return to_integer(unsigned(src));
end u8toi;
function ratoi(src: slv6) return integer is
begin
return to_integer(unsigned(src));
end ratoi;
function pxtoi(src: slv9) return integer is
begin
return to_integer(unsigned(src));
end pxtoi;
function inc6(src: slv6) return slv6 is
variable conv : unsigned(5 downto 0);
begin
conv := unsigned(src) + 1;
return slv6(conv);
end inc6;
function cpu_read(cbus,cr1w0 : std_logic) return boolean is
begin
case cbus and cr1w0 is
when '1' => return true;
when others => return false;
end case;
end;
function cpu_write(cbus,cr1w0 : std_logic) return boolean is
begin
case cbus and (not cr1w0) is
when '1' => return true;
when others => return false;
end case;
end;
function reg_in_range(rega: slv6) return boolean is
begin
case rega is
when "000000" => return true;
when "000001" => return true;
when "000010" => return true;
when "000011" => return true;
when "000100" => return true;
when "000101" => return true;
when "000110" => return true;
when "000111" => return true;
when "001000" => return true;
when "001001" => return true;
when "001010" => return true;
when "001011" => return true;
when "001100" => return true;
when "001101" => return true;
when "001110" => return true;
when "001111" => return true;
when "010000" => return true;
when "010001" => return true;
when "010010" => return true;
when "010011" => return true;
when "010100" => return true;
when "010101" => return true;
when "010110" => return true;
when "010111" => return true;
when "011000" => return true;
when "011001" => return true;
when "011010" => return true;
when "011011" => return true;
when "011100" => return true;
when "011101" => return true;
when "011110" => return true;
when "011111" => return true;
when "100000" => return true;
when "100001" => return true;
when "100010" => return true;
when "100011" => return true;
when "100100" => return true;
when "100101" => return true;
when "100110" => return true;
when "100111" => return true;
when "101000" => return true;
when "101001" => return true;
when "101010" => return true;
when "101011" => return true;
when "101100" => return true;
when "101101" => return true;
when "101110" => return true;
when others => return false;
end case;
end reg_in_range;
type fstg_t is (
get_idle,
get_m_ptrs,
get_m_data,
get_c_ptrs,
get_c_data
);
signal fetch_stg : fstg_t := get_idle;
signal fetch_m : slv3 := "000";
signal fetch_n : slv6 := "000000";
signal fetch_p : u16;
--
-- "unused vic register bits yield 1 on reading"
--
impure function vic_regs_masked(reg: integer) return byte is
variable tbyt : byte;
begin
case reg is
when 0 => tbyt:= ( vic_regs( 0));
when 1 => tbyt:= ( vic_regs( 1));
when 2 => tbyt:= ( vic_regs( 2));
when 3 => tbyt:= ( vic_regs( 3));
when 4 => tbyt:= ( vic_regs( 4));
when 5 => tbyt:= ( vic_regs( 5));
when 6 => tbyt:= ( vic_regs( 6));
when 7 => tbyt:= ( vic_regs( 7));
when 8 => tbyt:= ( vic_regs( 8));
when 9 => tbyt:= ( vic_regs( 9));
when 10 => tbyt:= ( vic_regs(10));
when 11 => tbyt:= ( vic_regs(11));
when 12 => tbyt:= ( vic_regs(12));
when 13 => tbyt:= ( vic_regs(13));
when 14 => tbyt:= ( vic_regs(14));
when 15 => tbyt:= ( vic_regs(15));
when 16 => tbyt:= ( vic_regs(16));
when 17 => tbyt:= ( regras_v( 8) & vic_regs(17)(6 downto 0));
when 18 => tbyt:= ( byte(regras_v(7 downto 0)));
when 19 => tbyt:= ( vic_regs(19));
when 20 => tbyt:= ( vic_regs(20));
when 21 => tbyt:= ( vic_regs(21));
when 22 => tbyt:= ("11" & vic_regs(22)(5 downto 0));
when 23 => tbyt:= ( vic_regs(23));
when 24 => tbyt:= ( vic_regs(24)(7 downto 1) & '1');
when 25 => tbyt:= ( vic_regs(25)(7) & "111" & vic_regs(25)(3 downto 0));
when 26 => tbyt:= ("1111" & vic_regs(26)(3 downto 0));
when 27 => tbyt:= ( vic_regs(27));
when 28 => tbyt:= ( vic_regs(28));
when 29 => tbyt:= ( vic_regs(29));
when 30 => tbyt:= ( vic_regs(30));
when 31 => tbyt:= ( vic_regs(31));
when 32 => tbyt:= ("1111" & vic_regs(32)(3 downto 0));
when 33 => tbyt:= ("1111" & vic_regs(33)(3 downto 0));
when 34 => tbyt:= ("1111" & vic_regs(34)(3 downto 0));
when 35 => tbyt:= ("1111" & vic_regs(35)(3 downto 0));
when 36 => tbyt:= ("1111" & vic_regs(36)(3 downto 0));
when 37 => tbyt:= ("1111" & vic_regs(37)(3 downto 0));
when 38 => tbyt:= ("1111" & vic_regs(38)(3 downto 0));
when 39 => tbyt:= ("1111" & vic_regs(39)(3 downto 0));
when 40 => tbyt:= ("1111" & vic_regs(40)(3 downto 0));
when 41 => tbyt:= ("1111" & vic_regs(41)(3 downto 0));
when 42 => tbyt:= ("1111" & vic_regs(42)(3 downto 0));
when 43 => tbyt:= ("1111" & vic_regs(43)(3 downto 0));
when 44 => tbyt:= ("1111" & vic_regs(44)(3 downto 0));
when 45 => tbyt:= ("1111" & vic_regs(45)(3 downto 0));
when 46 => tbyt:= ("1111" & vic_regs(46)(3 downto 0));
when others => tbyt:= "11111111";
end case;
return tbyt;
end vic_regs_masked;
function valid_cell_x(xc : slv6) return boolean is
begin
case xc is
when "101000" => return false;
when "101001" => return false;
when "101010" => return false;
when "101011" => return false;
when "101100" => return false;
when "101101" => return false;
when "101110" => return false;
when "101111" => return false;
when "110000" => return false;
when "110001" => return false;
when "110010" => return false;
when "110011" => return false;
when "110100" => return false;
when "110101" => return false;
when "110110" => return false;
when "110111" => return false;
when "111000" => return false;
when "111001" => return false;
when "111010" => return false;
when "111011" => return false;
when "111100" => return false;
when "111101" => return false;
when "111110" => return false;
when "111111" => return false;
when others => return true;
end case;
end valid_cell_x;
begin
clock20ph: process(clk20_ph1,clk20_ph2,clk20ph,rapos_V,rapos_H,res0) is
variable raV : u16;
variable raH : u16;
begin
raV := rapos_V;
raH := rapos_H;
if (res0 = '0') then
--clk20ph <= "001001";
rapos_V <= "0000000000000000";
rapos_H <= "0000000000000000";
else
if (falling_edge(clk20_ph2)) then
--if (rising_edge(clk20_ph2)) then
--clk20ph <= clk20ph_count(clk20ph);
raV := rapos_V;
raH := raH + 1;
if (raH >= 528) then
raH := "0000000000000000";
raV := raV + 1;
if (raV >= 628) then
raV := "0000000000000000";
end if;
end if;
rapos_V <= raV;
rapos_H <= raH;
end if;
--if (falling_edge(clk20_ph1)) then
--if (rising_edge(clk20_ph1)) then
--clk20ph <= clk20ph_count(clk20ph);
--end if;
end if;
end process clock20ph;
clk20_12 <= clk20_ph1 or clk20_ph2;
cpu_clkcnt: process(clk20_12,clk20ph) is
begin
if (res0 = '0') then
clk20ph <= "001001";
elsif (falling_edge(clk20_12)) then
clk20ph <= clk20ph_count(clk20ph);
end if;
end process cpu_clkcnt;
cpu_clocks: process(clk20_ph1,clk20_ph2,clk20ph) is
variable sigs : nybble;
begin
case clk20ph is
when "110001" => sigs := "1110";
when "110010" => sigs := "1000";
when "110011" => sigs := "1100";
when "110100" => sigs := "1000";
when "110101" => sigs := "0101";
when "110110" => sigs := "0000";
when "110111" => sigs := "0100";
when "111000" => sigs := "0000";
when others => sigs := "0000";
end case;
if (rising_edge(clk20_ph1) or rising_edge(clk20_ph2)) then
ph0 <= sigs(3);
cpuclk <= sigs(2);
ph1 <= sigs(1);
ph2 <= sigs(0);
--case clk20ph is
-- when "110001" => cpuclk <= '1';
-- when "110011" => cpuclk <= '1';
-- when "110101" => cpuclk <= '1';
-- when "110111" => cpuclk <= '1';
-- when others => cpuclk <= '0';
--end case;
--case clk20ph is
-- when "110001" => ph0 <= '1';
-- when "110010" => ph0 <= '1';
-- when "110011" => ph0 <= '1';
-- when "110100" => ph0 <= '1';
-- when others => ph0 <= '0';
--end case;
--case clk20ph is
-- when "110001" => ph1 <= '1';
-- when others => ph1 <= '0';
--end case;
--case clk20ph is
-- when "110101" => ph2 <= '1';
-- when others => ph2 <= '0';
--end case;
end if;
end process cpu_clocks;
cpu_clk <= cpuclk;
bus_ph0 <= ph0;
bus_ph1 <= ph1;
bus_ph2 <= ph2;
clk20stg <= pair(clk20ph(5 downto 4));
cpu_slice <= clk20stg(1) and clk20stg(0); -- when 1 it's CPU's turn on bus
vic_slice <= clk20stg(1) nand clk20stg(0); -- when 1 it's VIC's turn on bus
cpu_ben <= cpu_slice;
vic_ben <= vic_slice;
poscalc: process(clk20_ph2, rapos_V, rapos_H) is
begin
vis_V <= rapos_V - 5;
--win_V <= rapos_V - 105;
case vic_YSCROLL is
when "000" => win_V <= rapos_V - 99;
when "001" => win_V <= rapos_V - 101;
when "010" => win_V <= rapos_V - 103;
when "011" => win_V <= rapos_V - 105;
when "100" => win_V <= rapos_V - 107;
when "101" => win_V <= rapos_V - 109;
when "110" => win_V <= rapos_V - 111;
when others => win_V <= rapos_V - 113;
end case;
vis_H <= rapos_H - 84;
--win_H <= rapos_H - 124;
case vic_XSCROLL is
when "000" => win_H <= rapos_H - 125;
when "001" => win_H <= rapos_H - 126;
when "010" => win_H <= rapos_H - 127;
when "011" => win_H <= rapos_H - 128;
when "100" => win_H <= rapos_H - 129;
when "101" => win_H <= rapos_H - 130;
when "110" => win_H <= rapos_H - 131;
when others => win_H <= rapos_H - 132;
end case;
end process poscalc;
calc_rg_raster: process(clk20_ph1,clk20_ph2,vis_V) is
-- calculate the raster for the system to read
begin
if rising_edge(clk20_ph1) or rising_edge(clk20_ph2) then
if (vis_V <= x"03ff") then
regras_v <= vis_v(9 downto 1);
end if;
end if;
end process calc_rg_raster;
cell_H <= ubyte(win_H(10 downto 3));
cell_V <= ubyte(win_V(11 downto 4)); -- ignoring bit 0 (so odd lines repeat the even lines)
cell_PH <= ubyte("00000" & win_H(2 downto 0));
cell_PV <= ubyte("00000" & win_V(3 downto 1)); -- ignoring bit 0 (so odd lines repeat the even lines)
hb_calc: process(clk20_ph2, rapos_H, vic_CSEL) is
begin
if (falling_edge(clk20_ph2)) then
if (vic_CSEL='1' and ((rapos_H < 124) or (rapos_H > 443))) then
hbdr <= '1';
elsif (vic_CSEL='0' and ((rapos_H < 131) or (rapos_H > 434))) then
hbdr <= '1';
else
hbdr <= '0';
end if;
end if;
end process hb_calc;
vb_calc: process(clk20_ph2, rapos_V, vic_RSEL) is
begin
if (falling_edge(clk20_ph2)) then
if (vic_RSEL='1' and ((rapos_V < 105) or (rapos_V > 504))) then
vbdr <= '1';
elsif (vic_RSEL='0' and ((rapos_V < 113) or (rapos_V > 496))) then
vbdr <= '1';
else
vbdr <= '0';
end if;
end if;
end process vb_calc;
eh_calc: process(clk20_ph2, rapos_H) is
begin
if (falling_edge(clk20_ph2)) then
if ((rapos_H < 84) or (rapos_H > 483)) then
en_H <= '0';
else
en_H <= '1';
end if;
end if;
end process eh_calc;
ev_calc: process(clk20_ph2, rapos_V) is
begin
if (falling_edge(clk20_ph2)) then
if ((rapos_V < 5) or (rapos_V > 604)) then
en_V <= '0';
else
en_V <= '1';
end if;
end if;
end process ev_calc;
bdr <= vbdr or hbdr;
en <= en_V and en_H;
hsync: process(rapos_H) is
begin
if (rapos_H < 64) then
vhs <= '1';
else
vhs <= '0';
end if;
end process hsync;
vsync: process(rapos_V) is
begin
if (rapos_V < 4) then
vvs <= '1';
else
vvs <= '0';
end if;
end process vsync;
rgdo <= rg_o;
rg_i <= rgdi;
vreg_rd: process(ph2,cpu_slice,rga,vic_regs,r1w0) is
begin
if (rising_edge(ph2)) then
if (cpu_read(cpu_slice,r1w0)) then
-- reading register
if (reg_in_range(rga)) then
--rg_o <= vic_regs(ratoi(rga));
rg_o <= vic_regs_masked(ratoi(rga));
else
rg_o <= x"FF";
end if;
end if;
end if;
end process vreg_rd;
vreg_wr: process(ph2,cpu_slice,rga,r1w0,rg_i) is
begin
if (falling_edge(ph2)) then
if (cpu_write(cpu_slice,r1w0) and reg_in_range(rga)) then
-- writing register
vic_regs(ratoi(rga)) <= rg_i;
end if;
end if;
end process vreg_wr;
fetching: process(clk20_ph1,clk20_ph2,vic_slice,fetch_stg,fetch_m,cell_PV,cd,vd,
win_v,res0,rapos_H,fetch_n,fetch_p,vic_VM,vic_CB,line_c,line_b) is
variable cur_stg : fstg_t;
variable cur_n : slv6;
begin
if (res0 = '0') then
fetch_stg <= get_idle;
else
if (vic_slice='1') then
if (rising_edge(clk20_ph1)) then
case fetch_stg is
when get_idle =>
va <= "11111111111111";
when get_m_ptrs =>
va <= vic_VM & c_addr(fetch_p(9 downto 0));
when get_m_data =>
va <= vic_CB & line_b(ratoi(fetch_n)) & slv3(cell_PV(2 downto 0));
when others =>
null;
end case;
end if;
if (falling_edge(clk20_ph2)) then
cur_stg := fetch_stg;
cur_n := fetch_n;
case cur_stg is
when get_idle =>
if (rapos_H < x"0018" and win_V < x"8000") then
if (win_V(3 downto 0) = "0000") then
fetch_stg <= get_m_ptrs;
fetch_m <= "000";
fetch_n <= "000000";
fetch_p <= (cell_V*40);
else
fetch_stg <= get_m_data;
fetch_m <= "000";
fetch_n <= "000000";
end if;
end if;
when get_m_ptrs =>
line_c(ratoi(cur_n)) <= cd;
line_b(ratoi(cur_n)) <= vd;
if (cur_n < "100111") then
fetch_n <= inc6(cur_n);
fetch_p <= fetch_p + 1;
else
fetch_n <= "000000";
fetch_stg <= get_m_data;
end if;
when get_m_data =>
line_pix(pxtoi(fetch_n & "000")) <= vd(0);
line_pix(pxtoi(fetch_n & "001")) <= vd(1);
line_pix(pxtoi(fetch_n & "010")) <= vd(2);
line_pix(pxtoi(fetch_n & "011")) <= vd(3);
line_pix(pxtoi(fetch_n & "100")) <= vd(4);
line_pix(pxtoi(fetch_n & "101")) <= vd(5);
line_pix(pxtoi(fetch_n & "110")) <= vd(6);
line_pix(pxtoi(fetch_n & "111")) <= vd(7);
if (fetch_n < "100111") then
fetch_n <= inc6(fetch_n);
else
fetch_n <= "000000";
fetch_stg <= get_idle;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process fetching;
pixgen: process(en,bdr,vic_EC,win_H,cell_H,vic_B0C,clk20_ph1) is
variable cur_px_pos : slv9;
variable cur_cell_x : slv6;
begin
cur_px_pos := "000000000";
cur_cell_x := slv6(win_H(8 downto 3));
if (rising_edge(clk20_ph1)) then
if (en = '1') then
if (bdr = '1') then
vr <= vcolor_r(vic_EC)(7 downto 3);
vg <= vcolor_g(vic_EC)(7 downto 2);
vb <= vcolor_b(vic_EC)(7 downto 3);
else
cur_px_pos(8 downto 3) := cur_cell_x;
cur_px_pos(2 downto 0) := "111" xor slv3(win_H(2 downto 0));
if (not valid_cell_x(cur_cell_x)) then
vr <= vcolor_r(vic_B0C)(7 downto 3);
vg <= vcolor_g(vic_B0C)(7 downto 2);
vb <= vcolor_b(vic_B0C)(7 downto 3);
--vr <= vcolor_r(x"2")(7 downto 3); -- debug to catch out-of-range columns
--vg <= vcolor_g(x"2")(7 downto 2);
--vb <= vcolor_b(x"2")(7 downto 3);
elsif (line_pix(to_integer(unsigned(cur_px_pos))) = '1') then
vr <= vcolor_r(line_c(u8toi(cell_H)))(7 downto 3);
vg <= vcolor_g(line_c(u8toi(cell_H)))(7 downto 2);
vb <= vcolor_b(line_c(u8toi(cell_H)))(7 downto 3);
else
vr <= vcolor_r(vic_B0C)(7 downto 3);
vg <= vcolor_g(vic_B0C)(7 downto 2);
vb <= vcolor_b(vic_B0C)(7 downto 3);
end if;
end if;
else
vr <= "00000";
vg <= "000000";
vb <= "00000";
end if;
end if;
end process pixgen;
end vic_ii_impl;
| gpl-3.0 | 8fa2f8e3f171ebe074313d3bfaae2730 | 0.493522 | 3.206164 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/GigabitEthPkg.vhd | 1 | 3,988 | -------------------------------------------------------------------------------
-- Title : Gigabit Ethernet Package
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : GigabitEthPkg.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description:
-- Gigabit ethernet constants & types.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.UtilityPkg.all;
package GigabitEthPkg is
-----------------------------------------------------
-- Constants
-----------------------------------------------------
-- Ethernet constants
constant ETH_PRE_C : slv(7 downto 0) := x"55"; -- Preamble
constant ETH_SOF_C : slv(7 downto 0) := x"D5"; -- Start of Frame
constant ETH_PAD_C : slv(7 downto 0) := x"00"; -- Padding bytes
-- Minimum payload size for Ethernet frame in bytes
-- (starting from destination MAC and going through data)
constant ETH_MIN_SIZE_C : integer := 64;
-- This is the value you should get if you apply the CRC value to the packet
-- over which it is applied. It will be a constant value for correct CRC.
constant CRC_CHECK_C : slv(31 downto 0) := x"1CDF4421";
type EthMacDataType is record
data : slv(7 downto 0);
dataK : sl;
dataValid : sl;
end record EthMacDataType;
---------------------------------------------------------------------------------------------
-- Type for IP address
type IPAddrType is array(3 downto 0) of std_logic_vector(7 downto 0);
constant IP_ADDR_DEFAULT_C : IPAddrType := (3 => x"C0", 2 => x"A8", 1 => x"01", 0 => x"14"); --192.168.1.20
constant IP_ADDR_INIT_C : IPAddrType := (others => (others => '0'));
-- Array of IP addresses
type IpAddrArray is array(natural range<>) of IpAddrType;
-- Type for mac address
type MacAddrType is array(5 downto 0) of std_logic_vector(7 downto 0);
constant MAC_ADDR_DEFAULT_C : MacAddrType := (5 => x"00", 4 => x"44", 3 => x"56", 2 => x"00", 1 => x"03", 0 => x"01");
constant MAC_ADDR_BCAST_C : MacAddrType := (others => (others => '1'));
constant MAC_ADDR_INIT_C : MacAddrType := (others => (others => '0'));
-- Ethernet header field constants
subtype EtherType is std_logic_vector(15 downto 0);
constant ETH_TYPE_INIT_C : EtherType := x"0000";
constant ETH_TYPE_IPV4_C : EtherType := x"0800";
constant ETH_TYPE_ARP_C : EtherType := x"0806";
-- Not implemented at the moment but maybe in the future
--constant EthTypeIPV6 : EtherType := x"86DD";
--constant EthTypeMac : EtherType := x"8808";
-- UDP header field constants
subtype ProtocolType is std_logic_vector(7 downto 0);
constant UDP_PROTOCOL_C : ProtocolType := x"11";
-- Not implemented at the moment but maybe in the future
--constant ICMP_PROTOCOL_C : ProtocolType := x"01";
--constant TCP_PROTOCOL_C : ProtocolType := x"06";
-- ARP constants
constant ARP_HTYPE_C : slv(15 downto 0) := x"0001";
constant ARP_PTYPE_C : slv(15 downto 0) := x"0800";
constant ARP_HLEN_C : slv( 7 downto 0) := x"06";
constant ARP_PLEN_C : slv( 7 downto 0) := x"04";
constant ARP_OP_REQ_C : slv(15 downto 0) := x"0001";
constant ARP_OP_RES_C : slv(15 downto 0) := x"0002";
-- IPv4 constants
constant IPV4_VERSION_C : slv(3 downto 0) := x"4";
constant IPV4_IHL_C : slv(3 downto 0) := x"5";
constant IPV4_DSCP_C : slv(5 downto 0) := (others => '0');
constant IPV4_ECN_C : slv(1 downto 0) := (others => '0');
constant IPV4_TTL_C : slv(7 downto 0) := x"02";
constant IPV4_PROTO_UDP_C : slv(7 downto 0) := x"11";
constant IPV4_PROTO_ICMP_C : slv(7 downto 0) := x"01";
end GigabitEthPkg;
package body GigabitEthPkg is
end package body GigabitEthPkg;
| lgpl-2.1 | 426dd10a130d91535e78b1b8deea038b | 0.54338 | 3.871845 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/rtl/Eth1000BaseXMacTx.vhd | 1 | 12,650 | ---------------------------------------------------------------------------------
-- Title : 1000 BASE X MAC TX Layer
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : Eth1000BaseXMacTx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to GTP interface to 1000 BASE X Ethernet.
-- User supplies data starting at destination MAC address
-- This module will send /S/, preamble, SOF, <user data>, FCS(CRC), /T/R/...
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity Eth1000BaseXMacTx is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl := '0';
-- User data to be sent
userDataIn : in slv(7 downto 0);
userDataValid : in sl;
userDataLastByte : in sl;
userDataReady : out sl;
-- Data out to the GTX
macDataOut : out EthMacDataType);
end Eth1000BaseXMacTx;
architecture rtl of Eth1000BaseXMacTx is
type StateType is (S_IDLE, S_SPD, S_PREAMBLE, S_SOF, S_FRAME_DATA, S_PAD,
S_FCS_0, S_FCS_1, S_FCS_2, S_FCS_3, S_EPD, S_CAR,
S_INTERPACKET_GAP);
type WriteStateType is (S_WAIT_READY, S_WRITE, S_WAIT_NOT_READY);
type RegType is record
state : StateType;
wrState : WriteStateType;
oddEven : sl;
dataOut : slv(7 downto 0);
dataKOut : sl;
dataValidOut : sl;
readyOut : sl;
crcDataIn : slv(7 downto 0);
crcDataValid : sl;
crcReset : sl;
crcByteCount : slv(15 downto 0);
userByteCount : slv(15 downto 0);
preambleCount : slv(7 downto 0);
fifoDataWrEn : sl;
fifoDataIn : slv(7 downto 0);
fifoDataRdEn : sl;
gapWaitCnt : slv(7 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => S_IDLE,
wrState => S_WAIT_READY,
oddEven => '0',
dataOut => (others => '0'),
dataKOut => '0',
dataValidOut => '0',
readyOut => '0',
crcDataIn => (others => '0'),
crcDataValid => '0',
crcReset => '0',
crcByteCount => (others => '0'),
userByteCount => (others => '0'),
preambleCount => (others => '0'),
fifoDataWrEn => '0',
fifoDataIn => (others => '0'),
fifoDataRdEn => '0',
gapWaitCnt => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal crcOut : slv(31 downto 0);
signal fifoDataOut : slv(7 downto 0);
signal fifoDataValid : sl;
signal fifoAlmostEmpty : sl;
signal fifoEmpty : sl;
-- Gigabit ethernet should have a minimum 12 cycle gap between packets
constant INTERPACKET_GAP_WAIT_C : slv(7 downto 0) := x"0C";
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
-- Calculate the CRC on incoming data so we can append it as the FCS
U_Crc32 : entity work.Crc32
generic map (
BYTE_WIDTH_G => 1,
CRC_INIT_G => x"FFFFFFFF",
GATE_DELAY_G => GATE_DELAY_G)
port map (
crcOut => crcOut,
crcClk => ethTxClk,
crcDataValid => r.crcDataValid,
crcDataWidth => (others => '0'),
crcIn => r.crcDataIn,
crcReset => r.crcReset);
-- Short buffer to allow for queuing up a few data words
-- while we send preambles, etc. Also allows calculation of the CRC in time
-- for transmission.
U_DataBuffer : entity work.fifo8x64
port map (
clk => ethTxClk,
srst => ethTxRst,
din => r.fifoDataIn,
wr_en => r.fifoDataWrEn,
rd_en => r.fifoDataRdEn,
dout => fifoDataOut,
full => open,
empty => fifoEmpty,
almost_empty => fifoAlmostEmpty,
valid => fifoDataValid
);
comb : process(r,userDataIn,userDataLastByte,userDataValid,ethTxRst,fifoDataOut,fifoDataValid,fifoEmpty,fifoAlmostEmpty,crcOut) is
variable v : RegType;
begin
v := r;
-- Always toggle the odd/even bit
v.oddEven := not(r.oddEven);
-- Logic to handle the CRC data and reset
-- It's out of sync with the state machine so that
-- we can have the value ready immediately after
-- the user data + padding, so it's handled separately here
if (r.state = S_IDLE) then
v.crcDataIn := r.fifoDataIn; --userDataIn;
if (r.fifoDataWrEn = '1') then
v.crcByteCount := r.crcByteCount + 1;
v.crcDataValid := '1';
v.crcReset := '0';
else
v.crcByteCount := (others => '0');
v.crcReset := '1';
end if;
else
if (r.fifoDataWrEn = '1') then
v.crcDataIn := r.fifoDataIn; --userDataIn;
v.crcDataValid := '1';
v.crcByteCount := r.crcByteCount + 1;
elsif (r.crcByteCount < ETH_MIN_SIZE_C-4) then
v.crcDataIn := ETH_PAD_C;
v.crcDataValid := '1';
v.crcByteCount := r.crcByteCount + 1;
else
v.crcDataIn := r.fifoDataIn; --userDataIn;
v.crcDataValid := '0';
end if;
end if;
-- Simple state machine to throttle requests for transmission
case(r.wrState) is
when S_WAIT_READY =>
v.readyOut := '1';
if (userDataValid = '1' and r.readyOut = '1') then
v.fifoDataWrEn := '1';
v.fifoDataIn := userDataIn;
v.wrState := S_WRITE;
end if;
when S_WRITE =>
v.readyOut := '1';
v.fifoDataIn := userDataIn;
v.fifoDataWrEn := userDataValid and r.ReadyOut;
if (r.readyOut = '1' and userDataValid = '1' and userDataLastByte = '1') then
v.readyOut := '0';
v.wrState := S_WAIT_NOT_READY;
end if;
when S_WAIT_NOT_READY =>
v.fifoDataWrEn := '0';
v.readyOut := '0';
if (r.state = S_IDLE) then
v.wrState := S_WAIT_READY;
end if;
when others =>
v.wrState := S_WAIT_NOT_READY;
end case;
-- The rest of the state machine just sends data
-- following the 1000-BASEX and Ethernet standards.
case(r.state) is
-- In idle, transmit commas forever
when S_IDLE =>
-- Current frame is odd, next frame will be even
if (r.oddEven = '1') then
v.dataOut := (K_COM_C);
v.dataKOut := '1';
-- Data is always valid but we should sync up with an even word
-- for benefit of the 8-to-16 stage that comes after this.
v.dataValidOut := '1';
-- Current frame is even, next frame will be odd
else
v.dataOut := (D_162_C);
v.dataKOut := '0';
end if;
v.userByteCount := (others => '0');
v.preambleCount := (others => '0');
v.fifoDataRdEn := '0';
if (r.fifoDataWrEn = '1') then
v.state := S_SPD;
end if;
-- Once we see good data, send /S/ in next even position
when S_SPD =>
-- If next frame is even, transmit /S/ and move on to next state
if (r.oddEven = '1') then
v.dataOut := (K_SOP_C);
v.dataKOut := '1';
v.state := S_PREAMBLE;
-- Next frame is odd, finish the comma sequence and stay here
else
v.dataOut := (D_162_C);
v.dataKOut := '0';
end if;
-- Then send the preamble
when S_PREAMBLE =>
v.dataOut := ETH_PRE_C;
v.dataKOut := '0';
v.preambleCount := r.preambleCount + 1;
if (r.preambleCount = 6) then
v.state := S_SOF;
end if;
-- Then send the ethernet SOF
when S_SOF =>
v.dataOut := ETH_SOF_C;
v.dataKOut := '0';
v.state := S_FRAME_DATA;
v.fifoDataRdEn := '1';
-- Move on to the user data
when S_FRAME_DATA =>
if (r.userByteCount < ETH_MIN_SIZE_C-4-1) then
v.userByteCount := r.userByteCount + 1;
end if;
v.dataKOut := '0';
v.dataOut := fifoDataOut;
v.fifoDataRdEn := fifoDataValid;
if (fifoAlmostEmpty = '1') then
if (r.userByteCount < ETH_MIN_SIZE_C-4-1) then
v.state := S_PAD;
else
v.state := S_FCS_0;
end if;
end if;
-- If we need padding, do it here, otherwise, move on to FCS
when S_PAD =>
v.userByteCount := r.userByteCount + 1;
v.dataKOut := '0';
v.dataOut := ETH_PAD_C;
v.fifoDataRdEn := '0';
if (r.userByteCount >= ETH_MIN_SIZE_C-4-1) then
v.state := S_FCS_0;
end if;
-- Send the various bytes of FCS (CRC)
when S_FCS_0 =>
v.dataKOut := '0';
v.dataOut := crcOut(31 downto 24);
v.state := S_FCS_1;
when S_FCS_1 =>
v.dataKOut := '0';
v.dataOut := crcOut(23 downto 16);
v.state := S_FCS_2;
when S_FCS_2 =>
v.dataKOut := '0';
v.dataOut := crcOut(15 downto 8);
v.state := S_FCS_3;
when S_FCS_3 =>
v.dataKOut := '0';
v.dataOut := crcOut(7 downto 0);
v.state := S_EPD;
-- Then send /T/
when S_EPD =>
v.dataKOut := '1';
v.dataOut := K_EOP_C;
v.state := S_CAR;
-- Send any /R/ required
when S_CAR =>
v.dataKOut := '1';
v.dataOut := K_CAR_C;
-- Make sure we put IDLE back on an even boundary
if (r.oddEven = '0') then
v.state := S_INTERPACKET_GAP;
v.gapWaitCnt := INTERPACKET_GAP_WAIT_C;
end if;
-- Force an interpacket gap filled with comma chars
when S_INTERPACKET_GAP =>
-- Current frame is odd, next frame will be even
if (r.oddEven = '1') then
v.dataOut := (K_COM_C);
v.dataKOut := '1';
-- Current frame is even, next frame will be odd
else
v.dataOut := (D_162_C);
v.dataKOut := '0';
end if;
v.userByteCount := (others => '0');
v.preambleCount := (others => '0');
v.fifoDataRdEn := '0';
if (r.gapWaitCnt = 0) then
v.state := S_IDLE;
else
v.gapWaitCnt := r.gapWaitCnt - 1;
end if;
-- Reset the CRC value so it's ready for
-- immediate use next packet
v.crcReset := '1';
when others =>
v.state := S_IDLE;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
macDataOut.data <= r.dataOut;
macDataOut.dataK <= r.dataKOut;
macDataOut.dataValid <= r.dataValidOut;
userDataReady <= r.readyOut;
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 7a8182a6ef06a15c99ba23ed76e94bd7 | 0.480158 | 4.044118 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/ROM_IEC.vhd | 1 | 2,815 | ----------------------------------------------------------------------------------
-- Load an embbedded PRG file in block RAM to Zybo C64 via IEC
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ROM_IEC is
port (
ATN0 : in std_logic; -- master broadcasting command when low
LCLK0 : in std_logic; -- input clock when listening 0=low=idle 1=bit valid
DATAI0 : in std_logic; -- input data when listening
TCLK0 : out std_logic; -- output clock when talking 0=low=idle 1=bit valid
DATAO0 : out std_logic; -- output data when talking
clk : in std_logic -- system clock (use PH2)
);
end ROM_IEC;
architecture IEC_ROMLoad_Impl of ROM_IEC is
signal atn : std_logic;
signal clkr : std_logic;
signal datar : std_logic;
signal clkw : std_logic:='1';
signal dataw : std_logic:='1';
signal clk_pull : std_logic;
signal data_pull : std_logic;
subtype u4 is unsigned(3 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype u8 is unsigned(7 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype word is std_logic_vector(15 downto 0);
constant prg_size : u16 := x"66BF";
signal prg_addr : u16 := x"0000";
type iec_st is (
iec_idle
);
signal iecST : iec_st := iec_idle;
signal iecSeq : byte := x"00";
signal iecFNp : nybble := x"0";
signal iecCyc : byte := x"00";
signal iecEOI : std_logic := '0';
signal xferSR : byte := x"00"; -- shift reg for xfers
signal xferCnt : u4 := x"0";
signal xferTrn : std_logic;
begin
atn <= ATN0;
clkr <= LCLK0;
datar <= DATAI0;
TCLK0 <= clkw;
DATAO0 <= dataw;
clk_pull <= clkw and not LCLK0; -- 1 whenever we output a one but signal is in pulldown
data_pull <= dataw and not DATAI0; -- 1 whenever we output a one but signal is in pulldown
iec_proto: process(clk,iecST,iecSeq,iecFNp,iecCyc,iecEOI,atn,clkr,datar) is
variable eoi : std_logic;
variable cyc : u8;
variable seq : u8;
variable fnp : u4;
begin
if (rising_edge(clk)) then
seq := u8(iecSeq);
fnp := u4(iecFNp);
cyc := u8(iecCyc);
eoi := iecEOI;
case iecST is
when iec_idle =>
clkw <= '1';
dataw <= '1';
when others =>
null;
end case;
iecSeq <= byte(seq);
iecFNp <= nybble(fnp);
iecCyc <= byte(cyc);
iecEOI <= eoi;
end if;
end process iec_proto;
end IEC_ROMLoad_Impl;
| gpl-3.0 | 72144b9157e3724a3ab447173d6dc0f3 | 0.533215 | 3.437118 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/testbench/tb_timer.vhd | 1 | 2,285 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 02/04/2018 02:05:57 PM
-- Module Name: tb_timer - Behavioral
-- Description: Test bench for timer and timer interrupt
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity tb_timer is
-- Port ( );
end tb_timer;
architecture Behavioral of tb_timer is
-- component forward declaration
component timer is
port(
clk: in std_logic; -- System clock
rst: in std_logic; -- System reset
CSR_compare: in doubleword; -- Comparison value to trigger interrupt
CSR_count: out doubleword; -- Current timer count in 50 MHz ticks
timer_interrupt:out std_logic -- Interrupt condition signal
);
end component;
-- Signals and constants
constant t_per: time := 1 ns;
signal s_clk: std_logic;
signal s_rst: std_logic;
signal s_CSR_compare: doubleword;
signal s_CSR_count: doubleword;
signal s_timer_interrupt: std_logic;
begin
-- Instantiation
myTimer: timer
port map(
clk => s_clk,
rst => s_rst,
CSR_compare => s_CSR_compare,
CSR_count => s_CSR_count,
timer_interrupt => s_timer_interrupt
);
-- Clock generation
tiktok: process
begin
s_clk <= '0';
wait for t_per/2;
s_clk <= '1';
wait for t_per/2;
end process;
main: process
begin
s_rst <= '1';
-- Settling
wait for t_per/2;
wait for t_per;
-- Test simple count compare
s_rst <= '0';
s_CSR_compare <= (others => '0');
wait for 10 * t_per;
-- Test 1 tick timer
s_CSR_compare <= std_logic_vector(unsigned(s_CSR_count) + 1);
wait for t_per;
-- Test 10 tick timer
s_CSR_compare <= std_logic_vector(unsigned(s_CSR_count) + 10);
wait for 11 * t_per;
-- quick reset
s_rst <= '1';
wait for t_per;
s_rst <= '0';
-- Test 0.1 second timer or stack overflow and crash Vivado
s_CSR_compare <= std_logic_vector(to_unsigned(5000000, 64));
wait for 200 * t_per;
wait;
end process;
end Behavioral;
| mit | c79fcc688fa6817fca0052a2620d3c39 | 0.568928 | 3.604101 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/1000BASE-X/rtl/Eth1000BaseXAbilityMatch.vhd | 1 | 5,719 | ---------------------------------------------------------------------------------
-- Title : 1000 BASE X ability match
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : Eth1000BaseXAbilityMatch.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Ability, acknowledge, consistency, idle match for Clause 37 auto-negotiation
-- Next pages are not supported.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
use work.GigabitEthPkg.all;
entity Eth1000BaseXAbilityMatch is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
-- System clock, reset & control
ethRx62Clk : in sl;
ethRx62Rst : in sl;
-- Link is stable
rxLinkSync : in sl;
-- Entering a new state (abMatch should be reset on new state)
newState : in sl;
-- Output match signals
abilityMatch : out sl;
ability : out slv(15 downto 0);
acknowledgeMatch : out sl;
consistencyMatch : out sl;
idleMatch : out sl;
-- Physical Interface Signals
phyRxData : in EthRxPhyLaneInType
);
end Eth1000BaseXAbilityMatch;
-- Define architecture
architecture rtl of Eth1000BaseXAbilityMatch is
type RegType is record
ability : slv(15 downto 0);
abCount : slv(2 downto 0);
ackCount : slv(2 downto 0);
idleCount : slv(2 downto 0);
abMatch : sl;
ackMatch : sl;
consMatch : sl;
idleMatch : sl;
wordIsConfig : sl;
end record RegType;
constant REG_INIT_C : RegType := (
ability => (others => '0'),
abCount => (others => '0'),
ackCount => (others => '0'),
idleCount => (others => '0'),
abMatch => '0',
ackMatch => '0',
consMatch => '0',
idleMatch => '0',
wordIsConfig => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
begin
comb : process(r,phyRxData,ethRx62Rst,rxLinkSync,newState) is
variable v : RegType;
begin
v := r;
-- Check for /C1/ or /C2/
if ( phyRxData.dataK = "01" and
(phyRxData.data = OS_C1_C or phyRxData.data = OS_C2_C)) then
v.wordIsConfig := '1';
else
v.wordIsConfig := '0';
end if;
-- On /I1/ or /I2/, reset abCount and ackCount
if ( phyRxData.dataK = "01" and
(phyRxData.data = OS_I1_C or phyRxData.dataK = OS_I2_C)) then
v.abCount := (others => '0');
v.ackCount := (others => '0');
-- If we just saw /C1/ or /C2/ the next word is the ability word
elsif (r.wordIsConfig = '1') then
v.ability := phyRxData.data;
-- If the ability word doesn't match the last one, reset the counter
-- Note we ignore the ack bit in this comparison
if (v.ability(15) /= r.ability(15) or (v.ability(13 downto 0) /= r.ability(13 downto 0))) then
v.abCount := (others => '0');
-- Otherwise, we match. Increment the ability count
elsif (r.abCount < 3) then
v.abCount := r.abCount + 1;
end if;
-- For acknowledge, need a match and the ack bit set or we reset
if (v.ability /= r.ability or (r.ability(14) = '0')) then
v.ackCount := (others => '0');
-- Otherwise, we match. Increment the ability count
elsif (r.ackCount < 3) then
v.ackCount := r.ackCount + 1;
end if;
end if;
-- On /C1/ or /C2/, reset idle count
if ( r.wordIsConfig = '1' ) then
v.idleCount := (others => '0');
-- If see /I1/ or /I2/ increment the idle count
elsif (phyRxData.dataK = "01" and (phyRxData.data = OS_I1_C or phyRxData.data = OS_I2_C) ) then
if (r.idleCount < 3) then
v.idleCount := r.idleCount + 1;
end if;
end if;
-- If the ability count is 3, we're matched
if (r.abCount = 3) then
v.abMatch := '1';
-- Otherwise, we're not
else
v.abMatch := '0';
end if;
-- If the acknowledge count is 3, we're matched
if (r.ackCount = 3) then
v.ackMatch := '1';
-- Otherwise, we're not
else
v.ackMatch := '0';
end if;
-- If the idle count is 3, we're matched
if (r.idleCount = 3) then
v.idleMatch := '1';
-- Otherwise, we're not
else
v.idleMatch := '0';
end if;
-- Check for consistency match
if (v.abMatch = '1' and v.ackMatch = '1') then
v.consMatch := '1';
else
v.consMatch := '0';
end if;
-- Reset on ethernet reset or sync down
if (ethRx62Rst = '1' or rxLinkSync = '0' or newState = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
abilityMatch <= r.abMatch;
acknowledgeMatch <= r.ackMatch;
consistencyMatch <= r.consMatch;
idleMatch <= r.idleMatch;
ability <= r.ability;
rin <= v;
end process;
seq : process (ethRx62Clk) is
begin
if (rising_edge(ethRx62Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | f324f856d2cc203a3852efe5ab2f4abb | 0.50953 | 3.835681 | false | false | false | false |
fabioperez/space-invaders-vhdl | lib/controllers/shot.vhd | 1 | 2,539 | library ieee;
use ieee.std_logic_1164.all;
library lib;
use lib.general.all;
--------------------------------------------------------------------------------
-- SHOT CONTROLLING ENTITY
--------------------------------------------------------------------------------
entity shot is
generic
(
res_x : integer := 15;
res_y : integer := 15;
aux_x : integer := 0;
aux_y : integer := 0;
flag_up : std_logic := '1';
clock_div : integer := 1
);
port
(
clock_i,
reset_i,
trigger_i : in std_logic;
position_x_i : in integer range 0 to res_x;
position_y_i : in integer range 0 to res_y;
enable_o : buffer std_logic;
position_x_o : buffer integer range 0 to res_x;
position_y_o : buffer integer range 0 to res_y
);
end entity;
architecture behavior of shot is
signal clock_s: std_logic;
begin
shot_clock: clock_counter
generic map ( clock_div )
port map ( clock_i, clock_s );
shot_movement:
process (reset_i, trigger_i, clock_s, position_y_i, position_x_i)
variable trigger_v: std_logic := '0';
begin
trigger_v := trigger_i;
if reset_i = '1' then
enable_o <= '0';
trigger_v := '0';
position_y_o <= position_y_i;
position_x_o <= position_x_i+aux_x/2;
elsif rising_edge(clock_s) then
-- If triggered and there is no bullet in the screen
if trigger_v = '1' and enable_o = '0' then
enable_o <= '1';
trigger_v := '0';
position_y_o <= position_y_i;
position_x_o <= position_x_i+aux_x/2;
-- If the bullet is enabled
elsif enable_o = '1' and position_y_o > 0 and position_y_o < res_y then
-- player shoot
if flag_up = '1' then
position_y_o <= position_y_o - 1;
if position_y_o < 4 then
enable_o <= '0';
end if;
-- enemy shoot
else
position_y_o <= position_y_o + 1;
if position_y_o = res_y then
enable_o <= '0';
end if;
end if;
elsif trigger_v = '0' then
position_x_o <= 0; --
position_y_o <= 0;
enable_o <= '0';
else
position_x_o <= position_x_i+aux_x/2; --
position_y_o <= position_y_i; --
end if;
end if;
end process;
end architecture;
| mit | 16501db2ec4b918b15664bd6b7a4bfa9 | 0.460024 | 3.531293 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/ddr.vhd | 1 | 9,704 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : ddr.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Wrapper module for the user design top level file. This module can be
-- instantiated in the system and interconnect as shown in example design
-- (example_top module).
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr is
port (
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end entity ddr;
architecture arch_ddr of ddr is
-- Start of IP top component
component ddr_mig
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end component ddr_mig;
-- End of IP top component
begin
-- Start of IP top instance
u_ddr_mig : ddr_mig
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_ref_req => app_ref_req,
app_zq_req => app_zq_req,
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
sys_rst => sys_rst
);
-- End of IP top instance
end architecture arch_ddr;
| mit | 3b3f7d4c3e78fed3dad2a6d9be2ef482 | 0.498969 | 3.716584 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/Ram2DdrXadc_RefComp/ipcore_dir/ddr/user_design/rtl/ddr_mig.vhd | 1 | 79,923 | --*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : ddr_mig.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module can be instantiated in the
-- system and interconnect as shown in user design wrapper file (user top module).
-- In addition to the memory controller, the module instantiates:
-- 1. Clock generation/distribution, reset logic
-- 2. IDELAY control block
-- 3. Debug logic
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr_mig is
generic (
RST_ACT_LOW : integer := 1;
-- =1 for active low reset,
-- =0 for active high.
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per rank for phy
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
DATA_BUF_ADDR_WIDTH : integer := 4;
DQ_CNT_WIDTH : integer := 4;
-- = ceil(log2(DQ_WIDTH))
DQ_PER_DM : integer := 8;
DM_WIDTH : integer := 2;
-- # of DM (data mask)
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC : string := "OFF";
ECC_TEST : string := "OFF";
PAYLOAD_WIDTH : integer := 16;
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
--nBANK_MACHS : integer := 4;
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
ODT_WIDTH : integer := 1;
-- # of ODT outputs to memory.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
USE_CS_PORT : integer := 1;
-- # = 1, When Chip Select (CS#) output is enabled
-- = 0, When Chip Select (CS#) output is disabled
-- If CS_N disabled, user must connect
-- DRAM CS_N input(s) to ground
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disabled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
USE_ODT_PORT : integer := 1;
-- # = 1, When ODT output is enabled
-- = 0, When ODT output is disabled
PHY_CONTROL_MASTER_BANK : integer := 0;
-- The bank index where master PHY_CONTROL resides,
-- equal to the PLL residing bank
MEM_DENSITY : string := "1Gb";
-- Indicates the density of the Memory part
-- Added for the sake of Vivado simulations
MEM_SPEEDGRADE : string := "25E";
-- Indicates the Speed grade of Memory Part
-- Added for the sake of Vivado simulations
MEM_DEVICE_WIDTH : integer := 16;
-- Indicates the device width of the Memory Part
-- Added for the sake of Vivado simulations
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
CL : integer := 5;
-- in number of clock cycles
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
OUTPUT_DRV : string := "HIGH";
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
RTT_NOM : string := "50";
-- RTT (Nominal) (Extended Mode Register).
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
ADDR_CMD_MODE : string := "1T" ;
-- # = "1T", "2T".
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
--***************************************************************************
CLKIN_PERIOD : integer := 4999;
-- Input Clock Period
CLKFBOUT_MULT : integer := 6;
-- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1;
-- write PLL VCO divisor
CLKOUT0_PHASE : real := 0.0;
-- Phase for PLL output clock (CLKOUT0)
CLKOUT0_DIVIDE : integer := 2;
-- VCO output divisor for PLL output clock (CLKOUT0)
CLKOUT1_DIVIDE : integer := 4;
-- VCO output divisor for PLL output clock (CLKOUT1)
CLKOUT2_DIVIDE : integer := 64;
-- VCO output divisor for PLL output clock (CLKOUT2)
CLKOUT3_DIVIDE : integer := 8;
-- VCO output divisor for PLL output clock (CLKOUT3)
MMCM_VCO : integer := 1200;
-- Max Freq (MHz) of MMCM VCO
MMCM_MULT_F : integer := 7;
-- write MMCM VCO multiplier
MMCM_DIVCLK_DIVIDE : integer := 1;
-- write MMCM VCO divisor
--***************************************************************************
-- Memory Timing Parameters. These parameters varies based on the selected
-- memory part.
--***************************************************************************
tCKE : integer := 7500;
-- memory tCKE paramter in pS
tFAW : integer := 45000;
-- memory tRAW paramter in pS.
tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
tRAS : integer := 40000;
-- memory tRAS paramter in pS.
tRCD : integer := 15000;
-- memory tRCD paramter in pS.
tREFI : integer := 7800000;
-- memory tREFI paramter in pS.
tRFC : integer := 127500;
-- memory tRFC paramter in pS.
tRP : integer := 12500;
-- memory tRP paramter in pS.
tRRD : integer := 10000;
-- memory tRRD paramter in pS.
tRTP : integer := 7500;
-- memory tRTP paramter in pS.
tWTR : integer := 7500;
-- memory tWTR paramter in pS.
tZQI : integer := 128000000;
-- memory tZQI paramter in nS.
tZQCS : integer := 64;
-- memory tZQCS paramter in clock cycles.
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIM_BYPASS_INIT_CAL : string := "OFF";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- The following parameters varies based on the pin out entered in MIG GUI.
-- Do not change any of these parameters directly by editing the RTL.
-- Any changes required should be done through GUI and the design regenerated.
--***************************************************************************
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
-- Byte lanes used in an IO column.
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- Byte lanes used in an IO column.
DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0101";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
-- Indicates Byte lane is data byte lane
-- or control Byte lane. '1' in a bit
-- position indicates a data byte lane and
-- a '0' indicates a control byte lane
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"FFC3F7FFF3FE";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000003";
ADDR_MAP
: std_logic_vector(191 downto 0) := X"00000000001003301A01903203A034018036012011017015";
BANK_MAP : std_logic_vector(35 downto 0) := X"01301601B";
CAS_MAP : std_logic_vector(11 downto 0) := X"039";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000038";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000035";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000037";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"014";
WE_MAP : std_logic_vector(11 downto 0) := X"03B";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000200";
DATA0_MAP : std_logic_vector(95 downto 0) := X"008004009007005001006003";
DATA1_MAP : std_logic_vector(95 downto 0) := X"022028020024027025026021";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029002";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- Mapping of Ranks.
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
DATA_IO_IDLE_PWRDWN : string := "ON";
-- # = "ON", "OFF"
BANK_TYPE : string := "HR_IO";
-- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
DATA_IO_PRIM_TYPE : string := "HR_LP";
-- # = "HP_LP", "HR_LP", "DEFAULT"
CKE_ODT_AUX : string := "FALSE";
USER_REFRESH : string := "OFF";
WRLVL : string := "OFF";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT", "RELAXED".
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
-- Calibration row address will be used for
-- calibration read and write operations
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
-- Calibration column address will be used for
-- calibration read and write operations
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
-- Calibration bank address will be used for
-- calibration read and write operations
TCQ : integer := 100;
IODELAY_GRP0 : string := "DDR_IODELAY_MIG0";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (200MHz).
IODELAY_GRP1 : string := "DDR_IODELAY_MIG1";
-- It is associated to a set of IODELAYs with
-- an IDELAYCTRL that have same IODELAY CONTROLLER
-- clock frequency (300MHz/400MHz).
SYSCLK_TYPE : string := "NO_BUFFER";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
SYS_RST_PORT : string := "FALSE";
-- "TRUE" - if pin is selected for sys_rst
-- and IBUF will be instantiated.
-- "FALSE" - if pin is not selected for sys_rst
FPGA_SPEED_GRADE : integer := 1;
-- FPGA speed grade
REF_CLK_MMCM_IODELAY_CTRL : string := "FALSE";
CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
DRAM_TYPE : string := "DDR2";
CAL_WIDTH : string := "HALF";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
--***************************************************************************
-- Referece clock frequency parameters
--***************************************************************************
REFCLK_FREQ : real := 200.0;
-- IODELAYCTRL reference clock frequency
DIFF_TERM_REFCLK : string := "TRUE";
-- Differential Termination for idelay
-- reference clock input pins
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
tCK : integer := 3333;
-- memory tCK paramter.
-- # = Clock Period in pS.
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric CLK
DIFF_TERM_SYSCLK : string := "TRUE";
-- Differential Termination for System
-- clock input pins
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr2_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr2_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr2_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr2_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr2_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr2_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr2_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH/8)-1 downto 0) ;
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity ddr_mig;
architecture arch_ddr_mig of ddr_mig is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;
constant DATA_WIDTH : integer := 16;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant TAPSPERKCLK : integer := 56;
function TEMP_MON return string is
begin
if(SIMULATION = "FALSE") then
return "ON";
else
return "OFF";
end if;
end function;
constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
constant ECC_WIDTH : integer := ECCWIDTH;
constant DATA_BUF_OFFSET_WIDTH : integer := 1;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
constant TEMP_MON_EN : string := TEMP_MON;
-- Enable or disable the temp monitor module
constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
component mig_7series_v4_0_iodelay_ctrl is
generic(
TCQ : integer;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
REFCLK_TYPE : string;
SYSCLK_TYPE : string;
SYS_RST_PORT : string;
RST_ACT_LOW : integer;
DIFF_TERM_REFCLK : string;
FPGA_SPEED_GRADE : integer;
REF_CLK_MMCM_IODELAY_CTRL : string
);
port (
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
clk_ref_i : in std_logic;
sys_rst : in std_logic;
clk_ref : out std_logic_vector(1 downto 0);
sys_rst_o : out std_logic;
iodelay_ctrl_rdy : out std_logic_vector(1 downto 0)
);
end component mig_7series_v4_0_iodelay_ctrl;
component mig_7series_v4_0_clk_ibuf is
generic (
SYSCLK_TYPE : string;
DIFF_TERM_SYSCLK : string
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk_i : in std_logic;
mmcm_clk : out std_logic
);
end component mig_7series_v4_0_clk_ibuf;
component mig_7series_v4_0_infrastructure is
generic (
SIMULATION : string := "FALSE";
TCQ : integer;
CLKIN_PERIOD : integer;
nCK_PER_CLK : integer;
SYSCLK_TYPE : string;
UI_EXTRA_CLOCKS : string := "FALSE";
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKOUT0_PHASE : real;
CLKOUT0_DIVIDE : integer;
CLKOUT1_DIVIDE : integer;
CLKOUT2_DIVIDE : integer;
CLKOUT3_DIVIDE : integer;
MMCM_VCO : integer;
MMCM_MULT_F : integer;
MMCM_DIVCLK_DIVIDE : integer;
MMCM_CLKOUT0_EN : string := "FALSE";
MMCM_CLKOUT1_EN : string := "FALSE";
MMCM_CLKOUT2_EN : string := "FALSE";
MMCM_CLKOUT3_EN : string := "FALSE";
MMCM_CLKOUT4_EN : string := "FALSE";
MMCM_CLKOUT0_DIVIDE : integer := 1;
MMCM_CLKOUT1_DIVIDE : integer := 1;
MMCM_CLKOUT2_DIVIDE : integer := 1;
MMCM_CLKOUT3_DIVIDE : integer := 1;
MMCM_CLKOUT4_DIVIDE : integer := 1;
RST_ACT_LOW : integer;
tCK : integer;
MEM_TYPE : string
);
port (
mmcm_clk : in std_logic;
sys_rst : in std_logic;
iodelay_ctrl_rdy : in std_logic_vector(1 downto 0);
psen : in std_logic;
psincdec : in std_logic;
clk : out std_logic;
clk_div2 : out std_logic;
rst_div2 : out std_logic;
mem_refclk : out std_logic;
freq_refclk : out std_logic;
sync_pulse : out std_logic;
mmcm_ps_clk : out std_logic;
poc_sample_pd : out std_logic;
iddr_rst : out std_logic;
psdone : out std_logic;
-- auxout_clk : out std_logic;
ui_addn_clk_0 : out std_logic;
ui_addn_clk_1 : out std_logic;
ui_addn_clk_2 : out std_logic;
ui_addn_clk_3 : out std_logic;
ui_addn_clk_4 : out std_logic;
pll_locked : out std_logic;
mmcm_locked : out std_logic;
rstdiv0 : out std_logic;
rst_phaser_ref : out std_logic;
ref_dll_lock : in std_logic
);
end component mig_7series_v4_0_infrastructure;
component mig_7series_v4_0_tempmon is
generic (
TCQ : integer;
TEMP_MON_CONTROL : string;
XADC_CLK_PERIOD : integer;
tTEMPSAMPLE : integer
);
port (
clk : in std_logic;
xadc_clk : in std_logic;
rst : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
device_temp : out std_logic_vector(11 downto 0)
);
end component mig_7series_v4_0_tempmon;
component mig_7series_v4_0_memc_ui_top_std is
generic (
TCQ : integer;
DDR3_VDD_OP_VOLT : string := "135";
PAYLOAD_WIDTH : integer;
ADDR_CMD_MODE : string;
AL : string;
BANK_WIDTH : integer;
BM_CNT_WIDTH : integer;
BURST_MODE : string;
BURST_TYPE : string;
CA_MIRROR : string := "FALSE";
CK_WIDTH : integer;
CL : integer;
COL_WIDTH : integer;
CMD_PIPE_PLUS1 : string;
CS_WIDTH : integer;
CKE_WIDTH : integer;
CWL : integer := 5;
DATA_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DDR2_DQSN_ENABLE : string := "YES";
DM_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
DRAM_WIDTH : integer;
ECC : string;
ECC_WIDTH : integer;
ECC_TEST : string;
MC_ERR_ADDR_WIDTH : integer;
MASTER_PHY_CTL : integer;
nAL : integer;
nBANK_MACHS : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
ORDERING : string;
IBUF_LPWR_MODE : string;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN : string;
IODELAY_GRP0 : string;
IODELAY_GRP1 : string;
FPGA_SPEED_GRADE : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string := "120";
STARVE_LIMIT : integer;
tCK : integer;
tCKE : integer;
tFAW : integer;
tPRDI : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
USER_REFRESH : string;
TEMP_MON_EN : string;
WRLVL : string;
DEBUG_PORT : string;
CAL_WIDTH : string;
RANK_WIDTH : integer;
RANKS : integer;
ODT_WIDTH : integer;
ROW_WIDTH : integer;
ADDR_WIDTH : integer;
APP_MASK_WIDTH : integer;
APP_DATA_WIDTH : integer;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
MEM_ADDR_ORDER : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
SIM_BYPASS_INIT_CAL : string;
REFCLK_FREQ : real;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IDELAY_ADJ : string;
FINE_PER_BIT : string;
CENTER_COMP_MODE : string;
PI_VAL_ADJ : string;
TAPSPERKCLK : integer := 56;
SKIP_CALIB : string;
FPGA_VOLT_TYPE : string
);
port (
clk : in std_logic;
clk_div2 : in std_logic;
rst_div2 : in std_logic;
clk_ref : in std_logic_vector(1 downto 0);
mem_refclk : in std_logic;
freq_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
mmcm_ps_clk : in std_logic;
poc_sample_pd : in std_logic;
rst : in std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_hi_pri : in std_logic;
app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1 downto 0);
app_wdf_wren : in std_logic;
app_correct_en_i : in std_logic;
app_raw_not_ecc : in std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_multiple_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_ecc_single_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
calib_tap_req : out std_logic;
calib_tap_addr : in std_logic_vector(6 downto 0);
calib_tap_load : in std_logic;
calib_tap_val : in std_logic_vector(7 downto 0);
calib_tap_load_done : in std_logic;
device_temp : in std_logic_vector(11 downto 0);
psen : out std_logic;
psincdec : out std_logic;
psdone : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_final_po_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
init_calib_complete : out std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_cpt_tap_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
rst_phaser_ref : in std_logic;
ref_dll_lock : out std_logic;
iddr_rst : in std_logic;
dbg_rd_data_offset : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_calib_rd_data_offset_1 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_calib_rd_data_offset_2 : out std_logic_vector((6*RANKS)-1 downto 0);
dbg_data_offset : out std_logic_vector(5 downto 0);
dbg_data_offset_1 : out std_logic_vector(5 downto 0);
dbg_data_offset_2 : out std_logic_vector(5 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
dbg_prbs_final_dqs_tap_cnt_r : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_first_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_prbs_second_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
dbg_poc : out std_logic_vector (1023 downto 0)
);
end component mig_7series_v4_0_memc_ui_top_std;
-- Signal declarations
signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
signal clk : std_logic;
signal clk_ref : std_logic_vector(1 downto 0);
signal iodelay_ctrl_rdy : std_logic_vector(1 downto 0);
signal clk_ref_in : std_logic;
signal sys_rst_o : std_logic;
signal clk_div2 : std_logic;
signal rst_div2 : std_logic;
signal freq_refclk : std_logic;
signal mem_refclk : std_logic;
signal pll_locked : std_logic;
signal sync_pulse : std_logic;
signal mmcm_ps_clk : std_logic;
signal poc_sample_pd : std_logic;
signal psen : std_logic;
signal psincdec : std_logic;
signal psdone : std_logic;
signal iddr_rst : std_logic;
signal ref_dll_lock : std_logic;
signal rst_phaser_ref : std_logic;
signal rst : std_logic;
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_ecc_single_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal ddr2_reset_n : std_logic;
signal ddr2_parity : std_logic;
signal init_calib_complete_i : std_logic;
signal sys_clk_p : std_logic;
signal sys_clk_n : std_logic;
signal mmcm_clk : std_logic;
signal clk_ref_p : std_logic;
signal clk_ref_n : std_logic;
signal clk_ref_i : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
signal device_temp_i : std_logic_vector(11 downto 0);
-- Debug port signals
signal dbg_idel_down_all : std_logic;
signal dbg_idel_down_cpt : std_logic;
signal dbg_idel_up_all : std_logic;
signal dbg_idel_up_cpt : std_logic;
signal dbg_sel_all_idel_cpt : std_logic;
signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal dbg_po_f_stg23_sel : std_logic;
signal dbg_sel_pi_incdec : std_logic;
signal dbg_sel_po_incdec : std_logic;
signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
signal dbg_pi_f_inc : std_logic;
signal dbg_po_f_inc : std_logic;
signal dbg_pi_f_dec : std_logic;
signal dbg_po_f_dec : std_logic;
signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps : std_logic_vector(11 downto 0);
signal dbg_cpt_tap_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_dq_idelay_tap_cnt : std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_calib_top : std_logic_vector(255 downto 0);
signal dbg_cpt_first_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_cpt_second_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
signal dbg_rd_data_offset : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
signal dbg_final_po_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_final_po_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
signal dbg_phy_init : std_logic_vector(255 downto 0);
signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
signal dbg_pi_phaselock_start : std_logic;
signal dbg_pi_phaselocked_done : std_logic;
signal dbg_pi_phaselock_err : std_logic;
signal dbg_pi_dqsfound_start : std_logic;
signal dbg_pi_dqsfound_done : std_logic;
signal dbg_pi_dqsfound_err : std_logic;
signal dbg_wrcal_start : std_logic;
signal dbg_wrcal_done : std_logic;
signal dbg_wrcal_err : std_logic;
signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
signal dbg_oclkdelay_calib_start : std_logic;
signal dbg_oclkdelay_calib_done : std_logic;
signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
signal dbg_oclkdelay_rd_data : std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
signal dbg_rddata : std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
signal dbg_rddata_valid : std_logic;
signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
signal dbg_wrlvl_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
signal dbg_wl_edge_detect_valid : std_logic;
signal dbg_wrlvl_done : std_logic;
signal dbg_wrlvl_err : std_logic;
signal dbg_wrlvl_start : std_logic;
signal dbg_rddata_r : std_logic_vector(63 downto 0);
signal dbg_rddata_valid_r : std_logic;
signal ocal_tap_cnt : std_logic_vector(53 downto 0);
signal dbg_dqs : std_logic_vector(4 downto 0);
signal dbg_bit : std_logic_vector(8 downto 0);
signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
signal dbg_calib_rd_data_offset_1 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_calib_rd_data_offset_2 : std_logic_vector((6*RANKS)-1 downto 0);
signal dbg_data_offset : std_logic_vector(5 downto 0);
signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
signal all_zeros : std_logic_vector((2*nCK_PER_CLK)-1 downto 0) := (others => '0');
signal ddr2_ila_basic_int : std_logic_vector(119 downto 0);
signal ddr2_ila_wrpath_int : std_logic_vector(390 downto 0);
signal ddr2_ila_rdpath_int : std_logic_vector(1023 downto 0);
signal dbg_prbs_final_dqs_tap_cnt_r_int : std_logic_vector(11 downto 0);
signal dbg_prbs_first_edge_taps_int : std_logic_vector(11 downto 0);
signal dbg_prbs_second_edge_taps_int : std_logic_vector(11 downto 0);
begin
--***************************************************************************
ui_clk <= clk;
ui_clk_sync_rst <= rst;
sys_clk_p <= '0';
sys_clk_n <= '0';
clk_ref_i <= '0';
init_calib_complete <= init_calib_complete_i;
clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
clk_ref_in <= mmcm_clk;
end generate;
clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
clk_ref_in <= clk_ref_i;
end generate;
u_iodelay_ctrl : mig_7series_v4_0_iodelay_ctrl
generic map
(
TCQ => TCQ,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
REFCLK_TYPE => REFCLK_TYPE,
SYSCLK_TYPE => SYSCLK_TYPE,
SYS_RST_PORT => SYS_RST_PORT,
RST_ACT_LOW => RST_ACT_LOW,
DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REF_CLK_MMCM_IODELAY_CTRL => REF_CLK_MMCM_IODELAY_CTRL
)
port map
(
-- Outputs
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
sys_rst_o => sys_rst_o,
clk_ref => clk_ref,
-- Inputs
clk_ref_p => clk_ref_p,
clk_ref_n => clk_ref_n,
clk_ref_i => clk_ref_in,
sys_rst => sys_rst
);
u_ddr2_clk_ibuf : mig_7series_v4_0_clk_ibuf
generic map
(
SYSCLK_TYPE => SYSCLK_TYPE,
DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
)
port map
(
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_clk_i => sys_clk_i,
mmcm_clk => mmcm_clk
);
-- Temperature monitoring logic
temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
u_tempmon : mig_7series_v4_0_tempmon
generic map
(
TCQ => TCQ,
TEMP_MON_CONTROL => TEMP_MON_CONTROL,
XADC_CLK_PERIOD => XADC_CLK_PERIOD,
tTEMPSAMPLE => tTEMPSAMPLE
)
port map
(
clk => clk,
xadc_clk => clk_ref(0),
rst => rst,
device_temp_i => device_temp_i,
device_temp => device_temp
);
end generate;
temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
device_temp <= (others => '0');
end generate;
u_ddr2_infrastructure : mig_7series_v4_0_infrastructure
generic map
(
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLKIN_PERIOD => CLKIN_PERIOD,
SYSCLK_TYPE => SYSCLK_TYPE,
CLKFBOUT_MULT => CLKFBOUT_MULT,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
MMCM_VCO => MMCM_VCO,
MMCM_MULT_F => MMCM_MULT_F,
MMCM_DIVCLK_DIVIDE => MMCM_DIVCLK_DIVIDE,
RST_ACT_LOW => RST_ACT_LOW,
tCK => tCK,
MEM_TYPE => DRAM_TYPE
)
port map
(
-- Outputs
rstdiv0 => rst,
clk => clk,
clk_div2 => clk_div2,
rst_div2 => rst_div2,
mem_refclk => mem_refclk,
freq_refclk => freq_refclk,
sync_pulse => sync_pulse,
psen => psen,
psincdec => psincdec,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
iddr_rst => iddr_rst,
psdone => psdone,
-- auxout_clk => open,
ui_addn_clk_0 => open,
ui_addn_clk_1 => open,
ui_addn_clk_2 => open,
ui_addn_clk_3 => open,
ui_addn_clk_4 => open,
pll_locked => pll_locked,
mmcm_locked => open,
rst_phaser_ref => rst_phaser_ref,
-- Inputs
mmcm_clk => mmcm_clk,
sys_rst => sys_rst_o,
iodelay_ctrl_rdy => iodelay_ctrl_rdy,
ref_dll_lock => ref_dll_lock
);
u_memc_ui_top_std : mig_7series_v4_0_memc_ui_top_std
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
COL_WIDTH => COL_WIDTH,
CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
CS_WIDTH => CS_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
CKE_WIDTH => CKE_WIDTH,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DM_WIDTH => DM_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
ECC_WIDTH => ECC_WIDTH,
ECC_TEST => ECC_TEST,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
REFCLK_FREQ => REFCLK_FREQ,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
CKE_ODT_AUX => CKE_ODT_AUX,
nCK_PER_CLK => nCK_PER_CLK,
ORDERING => ORDERING,
OUTPUT_DRV => OUTPUT_DRV,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP0 => IODELAY_GRP0,
IODELAY_GRP1 => IODELAY_GRP1,
FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
CL => CL,
tCK => tCK,
tCKE => tCKE,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
USER_REFRESH => USER_REFRESH,
TEMP_MON_EN => TEMP_MON_EN,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
CAL_WIDTH => CAL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
ROW_WIDTH => ROW_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
MEM_ADDR_ORDER => MEM_ADDR_ORDER,
STARVE_LIMIT => STARVE_LIMIT,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IDELAY_ADJ => "OFF",
FINE_PER_BIT => "OFF",
CENTER_COMP_MODE => "OFF",
PI_VAL_ADJ => "OFF",
MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK,
TAPSPERKCLK => TAPSPERKCLK,
SKIP_CALIB => "FALSE",
FPGA_VOLT_TYPE => "N"
)
port map (
clk => clk,
clk_div2 => clk_div2,
rst_div2 => rst_div2,
clk_ref => clk_ref,
mem_refclk => mem_refclk, --memory clock
freq_refclk => freq_refclk,
pll_lock => pll_locked,
sync_pulse => sync_pulse,
rst => rst,
rst_phaser_ref => rst_phaser_ref,
ref_dll_lock => ref_dll_lock,
iddr_rst => iddr_rst,
mmcm_ps_clk => mmcm_ps_clk,
poc_sample_pd => poc_sample_pd,
-- Memory interface ports
ddr_dq => ddr2_dq,
ddr_dqs_n => ddr2_dqs_n,
ddr_dqs => ddr2_dqs_p,
ddr_addr => ddr2_addr,
ddr_ba => ddr2_ba,
ddr_cas_n => ddr2_cas_n,
ddr_ck_n => ddr2_ck_n,
ddr_ck => ddr2_ck_p,
ddr_cke => ddr2_cke,
ddr_cs_n => ddr2_cs_n,
ddr_dm => ddr2_dm,
ddr_odt => ddr2_odt,
ddr_ras_n => ddr2_ras_n,
ddr_reset_n => ddr2_reset_n,
ddr_parity => ddr2_parity,
ddr_we_n => ddr2_we_n,
bank_mach_next => bank_mach_next,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_hi_pri => '0',
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_mask => app_wdf_mask,
app_wdf_wren => app_wdf_wren,
app_ecc_multiple_err => app_ecc_multiple_err,
app_ecc_single_err => app_ecc_single_err,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => app_sr_req,
app_sr_active => app_sr_active,
app_ref_req => app_ref_req,
app_ref_ack => app_ref_ack,
app_zq_req => app_zq_req,
app_zq_ack => app_zq_ack,
app_raw_not_ecc => all_zeros,
app_correct_en_i => '1',
psen => psen,
psincdec => psincdec,
psdone => psdone,
device_temp => device_temp,
-- Ports to be used when SKIP_CALIB="TRUE"
calib_tap_req => open,
calib_tap_addr => (others => '0'),
calib_tap_load => '0',
calib_tap_val => (others => '0'),
calib_tap_load_done => '0',
-- Debug logic ports
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_calib_top => dbg_calib_top,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_rd_data_offset => dbg_rd_data_offset,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_rddata => dbg_rddata,
dbg_rddata_valid => dbg_rddata_valid,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_pi_counter_read_val => dbg_pi_counter_read_val,
dbg_po_counter_read_val => dbg_po_counter_read_val,
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_phaselocked_done => dbg_pi_phaselocked_done,
dbg_pi_phaselock_err => dbg_pi_phaselock_err,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
dbg_data_offset => dbg_data_offset,
dbg_data_offset_1 => dbg_data_offset_1,
dbg_data_offset_2 => dbg_data_offset_2,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrcal_err => dbg_wrcal_err,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
dbg_prbs_final_dqs_tap_cnt_r => dbg_prbs_final_dqs_tap_cnt_r_int,
dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps_int,
dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps_int,
init_calib_complete => init_calib_complete_i,
dbg_poc => open
);
--*********************************************************************
-- Resetting all RTL debug inputs as the debug ports are not enabled
--*********************************************************************
dbg_idel_down_all <= '0';
dbg_idel_down_cpt <= '0';
dbg_idel_up_all <= '0';
dbg_idel_up_cpt <= '0';
dbg_sel_all_idel_cpt <= '0';
dbg_sel_idel_cpt <= (others => '0');
dbg_byte_sel <= (others => '0');
dbg_sel_pi_incdec <= '0';
dbg_pi_f_inc <= '0';
dbg_pi_f_dec <= '0';
dbg_po_f_inc <= '0';
dbg_po_f_dec <= '0';
dbg_po_f_stg23_sel <= '0';
dbg_sel_po_incdec <= '0';
end architecture arch_ddr_mig;
| mit | 6e563927572ad8aef1cdbf0a051bd58c | 0.439348 | 4.263242 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/UART_RX_CTRL.vhd | 2 | 4,128 | ----------------------------------------------------------------------------
-- UART_RX_CTRL.vhd -- Simple UART RX controller
-- Written by Hamster
-- Modified by Warren Toomey
--
-- This component may be used to transfer data over a UART device. It will
-- receive a byte of serial data and transmit it over an 8-bit bus. The
-- serialized data has to have the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
-- UART_RX - This is the serial signal line from the UART.
-- CLK - A 100 MHz clock is expected.
-- DATA - The parallel data to be read.
-- READ_DATA - Signal flag indicating when data is ready to be read.
-- RESET_READ - Data has been read, which turns off READ_DATA
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_RX_CTRL is
port ( UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC := '0';
RESET_READ: in STD_LOGIC
);
end UART_RX_CTRL;
architecture behavioral of UART_RX_CTRL is
constant FREQ : integer := 100000000; -- 100MHz Nexys4 CLK
constant BAUD : integer := 9600; -- Bit rate of serial comms
-- A counter of clock cycles. We sample the incoming
-- serial signal at 1.5x the serial bit duration to
-- skip the start bit and get halfway into the first
-- data bit. After that, we skip whole bit durations
-- to sample midway through the other data bits
signal count : integer := 0;
constant sample_0: integer := 3 * FREQ/(BAUD*2)-1;
constant sample_1: integer := 5 * FREQ/(BAUD*2)-1;
constant sample_2: integer := 7 * FREQ/(BAUD*2)-1;
constant sample_3: integer := 9 * FREQ/(BAUD*2)-1;
constant sample_4: integer := 11 * FREQ/(BAUD*2)-1;
constant sample_5: integer := 13 * FREQ/(BAUD*2)-1;
constant sample_6: integer := 15 * FREQ/(BAUD*2)-1;
constant sample_7: integer := 17 * FREQ/(BAUD*2)-1;
constant stop_bit: integer := 19 * FREQ/(BAUD*2)-1;
-- The bits from the serial input accumulate here
signal byte: std_logic_vector(7 downto 0) := (others => '0');
begin
rx_state_process : process (CLK)
begin
if (rising_edge(CLK)) then
-- The data has been read, so lower the flag
-- that indicates new data has arrived
if (RESET_READ = '1') then
READ_DATA <= '0';
end if;
-- Sample the serial line several times to find
-- the eight data bits and the stop bit
case count is
when sample_0 => byte <= UART_RX & byte(7 downto 1);
when sample_1 => byte <= UART_RX & byte(7 downto 1);
when sample_2 => byte <= UART_RX & byte(7 downto 1);
when sample_3 => byte <= UART_RX & byte(7 downto 1);
when sample_4 => byte <= UART_RX & byte(7 downto 1);
when sample_5 => byte <= UART_RX & byte(7 downto 1);
when sample_6 => byte <= UART_RX & byte(7 downto 1);
when sample_7 => byte <= UART_RX & byte(7 downto 1);
when stop_bit =>
-- Send out the data when we see a valid stop bit
if UART_RX = '1' then
DATA <= byte;
READ_DATA <= '1';
end if;
when others =>
null;
end case;
-- Reset the counter when we reach the stop bit
if count = stop_bit then
count <= 0;
elsif count = 0 then
if UART_RX = '0' then -- Start bit just seen, so start counting
count <= count + 1;
end if;
else
count <= count + 1;
end if;
end if;
end process;
end behavioral;
| mit | e2d71002cba3f9e008b20edf37e7df2c | 0.522529 | 4.1571 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_21/cia6526.vhd | 1 | 8,149 | ----------------------------------------------------------------------------------
--
-- 6526 CIA
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cia6526 is
port (
PAo : out std_logic_vector(7 downto 0);
PAi : in std_logic_vector(7 downto 0);
PBo : out std_logic_vector(7 downto 0);
PBi : in std_logic_vector(7 downto 0);
irq0 : out std_logic;
rga : in std_logic_vector(3 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
ce : in std_logic;
clk : in std_logic -- 1 MHz
);
end cia6526;
architecture CIA_impl of cia6526 is
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv5 is std_logic_vector(4 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype word is std_logic_vector(15 downto 0);
-- io ports A,B
signal PA : byte := x"00";
signal PB : byte := x"00";
signal PArd : byte; -- reg 0x0
signal PBrd : byte; -- reg 0x1
-- data direction registers (1=output, 0=input)
signal ddrA : byte := x"00"; -- reg 0x2
signal ddrB : byte := x"00"; -- reg 0x3
signal TAcnt : u16 := x"ffff";
signal TAltc : u16 := x"ffff";
signal TBcnt : u16 := x"ffff";
signal TBltc : u16 := x"ffff";
signal TActl : byte := x"00";
signal TBctl : byte := x"00";
alias TArun : std_logic is TActl(0);
alias TAto : std_logic is TActl(1);
alias TAupm : std_logic is TActl(2);
alias TAloop : std_logic is TActl(3);
alias TAsrc : pair is TActl(6 downto 5);
alias TBrun : std_logic is TBctl(0);
alias TBto : std_logic is TBctl(1);
alias TBupm : std_logic is TBctl(2);
alias TBloop : std_logic is TBctl(3);
alias TBsrc : pair is TBctl(6 downto 5);
signal ir_mask : slv5 := "00000";
signal ir_ltc : slv5 := "00000"; -- any bits set in here trigger an IRQ
signal ir_irq : std_logic;
constant src_ATO : integer := 0;
constant src_BTO : integer := 1;
constant src_TOD : integer := 2;
constant src_SDR : integer := 3;
constant src_FLG : integer := 4;
-- returns 1 if input is nonzero
function notZero(arg: slv5) return std_logic is
begin
return arg(0) or arg(1) or arg(2) or arg(3) or
arg(4);
end function notZero;
begin
ir_irq <= notZero(ir_ltc);
irq0 <= not ir_irq;
outA: process(ddrA,PA) is
begin
for i in 7 downto 0 loop
if (ddrA(i)='1') then
-- dump appropriate bit of port data register to any lines flagged output
PAo(i) <= PA(i);
else
-- if the line is flagged input read output a one to simluate hardware pullup
PAo(i) <= '1';
end if;
end loop;
end process outA;
outB: process(ddrB,PB) is
begin
for i in 7 downto 0 loop
if (ddrB(i)='1') then
-- dump appropriate bit of port data register to any lines flagged output
PBo(i) <= PB(i);
else
-- if the line is flagged input read output a one to simluate hardware pullup
PBo(i) <= '1';
end if;
end loop;
end process outB;
rd_A: process(ddrA,PA,PAi) is
begin
for i in 7 downto 0 loop
if (ddrA(i)='1') then
-- output lines just parrot the appropriate bit in the port data register
PArd(i) <= PA(i);
else
-- input lines reflect the corresponding external input lines
PArd(i) <= PAi(i);
end if;
end loop;
end process rd_A;
rd_B: process(ddrB,PB,PBi) is
begin
for i in 7 downto 0 loop
if (ddrB(i)='1') then
-- output lines just parrot the appropriate bit in the port data register
PBrd(i) <= PB(i);
else
-- input lines reflect the corresponding external input lines
PBrd(i) <= PBi(i);
end if;
end loop;
end process rd_B;
reg_access: process(clk,rgdi,ir_irq,ir_ltc,TAltc,TBltc,TAcnt,TBcnt,TActl,TBctl,PArd,PBrd,ddrA,ddrB) is
variable Acnt : u16;
variable Bcnt : u16;
begin
Acnt := TAcnt;
Bcnt := TBcnt;
if (rising_edge(clk) and ce='1' and r1w0='1') then
-- reading
case rga is
when x"0" => rgdo <= PArd;
when x"1" => rgdo <= PBrd;
when x"2" => rgdo <= ddrA;
when x"3" => rgdo <= ddrB;
when x"4" => rgdo <= byte(TAcnt( 7 downto 0));
when x"5" => rgdo <= byte(TAcnt(15 downto 8));
when x"6" => rgdo <= byte(TBcnt( 7 downto 0));
when x"7" => rgdo <= byte(TBcnt(15 downto 8));
when x"D" =>
rgdo <= ir_irq & "00" & ir_ltc;
when x"E" => rgdo <= TActl;
when x"F" => rgdo <= TBctl;
when others => rgdo <= x"FF";
end case;
end if;
if (falling_edge(clk)) then
if (TArun='1') then
if (Acnt=x"0000") then
ir_ltc(src_ATO) <= ir_mask(src_ATO);
if (TAloop='0') then
Acnt := TAltc;
else
TArun <= '0';
end if;
else
Acnt := Acnt - 1;
end if;
end if;
if (TBrun='1') then
if (Bcnt=x"0000") then
ir_ltc(src_BTO) <= ir_mask(src_BTO);
if (TBloop='0') then
Bcnt := TBltc;
else
TBrun <= '0';
end if;
else
Bcnt := Bcnt - 1;
end if;
end if;
if (ce='1' and r1w0='1') then
-- state-changes due to read cycles occur on downclock
case rga is
when x"d" =>
ir_ltc <= "00000";
when others => null;
end case;
end if;
-- writing
if (ce='1' and r1w0='0') then
case rga is
when x"0" => PA <= rgdi;
when x"1" => PB <= rgdi;
when x"2" => ddrA <= rgdi;
when x"3" => ddrB <= rgdi;
when x"4" => TAltc( 7 downto 0) <= unsigned(rgdi);
when x"5" => TAltc(15 downto 8) <= unsigned(rgdi);
when x"6" => TBltc( 7 downto 0) <= unsigned(rgdi);
when x"7" => TBltc(15 downto 8) <= unsigned(rgdi);
when x"D" =>
if (rgdi(7)='1') then
-- setting
for i in 4 downto 0 loop
if (rgdi(i)='1') then
ir_mask(i) <= '1';
end if;
end loop;
else
-- clearing
for i in 4 downto 0 loop
if (rgdi(i)='1') then
ir_mask(i) <= '0';
end if;
end loop;
end if;
when x"E" =>
TActl <= rgdi(7 downto 5) & '0' & rgdi(3 downto 0);
if (rgdi(4)='1') then
Acnt := TAltc;
end if;
when x"F" =>
TBctl <= rgdi(7 downto 5) & '0' & rgdi(3 downto 0);
if (rgdi(4)='1') then
Bcnt := TBltc;
end if;
when others => null;
end case;
end if;
TAcnt <= Acnt;
TBcnt <= Bcnt;
end if;
end process reg_access;
end CIA_impl;
| gpl-3.0 | 447090ed62d477c4f84952d41567e1ad | 0.453307 | 3.650986 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/ipcore_dir/dcm_TFT9/simulation/dcm_TFT9_tb.vhd | 1 | 5,373 | -- file: dcm_TFT9_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity dcm_TFT9_tb is
end dcm_TFT9_tb;
architecture test of dcm_TFT9_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
component dcm_TFT9_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*COUNT_PHASE);
simtimeprint;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : dcm_TFT9_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
end test;
| gpl-3.0 | 878554f4a87488310255a5b837179fc4 | 0.638191 | 4.386122 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/UdpTxFragmenter.vhd | 1 | 6,970 | ---------------------------------------------------------------------------------
-- Title : UDP TX Fragmenter
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : UdpTxFragmenter.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects UDP layer to IPv4 layer, decides how to fragment data into MTU-size
-- blocks.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity UdpTxFragmenter is
generic (
GATE_DELAY_G : time := 1 ns;
MTU_SIZE_G : integer := 1500;
ID_OFFSET_G : slv(15 downto 0) := (others => '0')
);
port (
-- 125 MHz ethernet clock in
ethTxClk : in sl;
ethTxRst : in sl := '0';
-- Header data
ipPacketLength : out slv(15 downto 0);
ipPacketId : out slv(15 downto 0);
ipMoreFragments : out sl;
ipFragOffset : out slv(12 downto 0);
ipProtocol : out slv( 7 downto 0);
-- User data to be sent
udpData : in slv(31 downto 0);
udpDataValid : in sl;
udpDataReady : out sl;
udpLength : in slv(15 downto 0);
udpReq : in sl;
udpAck : out sl;
-- Interface to IPv4 frame block
ipData : out slv(31 downto 0);
ipDataValid : out sl;
ipDataReady : in sl
);
end UdpTxFragmenter;
architecture rtl of UdpTxFragmenter is
type StateType is (IDLE_S, CHECK_SIZE_S,
SEND_MTU_PAUSE_S, SEND_MTU_S,
SEND_REMAINDER_PAUSE_S, SEND_REMAINDER_S,
WAIT_S);
type RegType is record
state : StateType;
udpBytesLeft : slv(15 downto 0);
mtuCount : slv(15 downto 0);
ipPacketLength : slv(15 downto 0);
ipPacketId : slv(15 downto 0);
ipMoreFragments : sl;
ipFragOffset : slv(12 downto 0);
ipProtocol : slv( 7 downto 0);
udpAck : sl;
ipData : slv(31 downto 0);
ipDataValid : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
udpBytesLeft => (others => '0'),
mtuCount => (others => '0'),
ipPacketLength => (others => '0'),
ipPacketId => ID_OFFSET_G,
ipMoreFragments => '0',
ipFragOffset => (others => '0'),
ipProtocol => (others => '0'),
udpAck => '0',
ipData => (others => '0'),
ipDataValid => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
comb : process(r,ethTxRst,udpData,udpDataValid,udpLength,
udpReq,ipDataReady) is
variable v : RegType;
begin
v := r;
-- Set defaults / reset any pulsed signals
udpDataReady <= '0';
ipDataValid <= '0';
ipData <= (others => '0');
v.ipProtocol := UDP_PROTOCOL_C;
-- State machine
case(r.state) is
when IDLE_S =>
if udpDataValid = '1' then
v.udpBytesLeft := udpLength - 4;
v.ipFragOffset := (others => '0');
v.state := CHECK_SIZE_S;
end if;
when CHECK_SIZE_S =>
-- Wait for last transfer to finish
if r.ipDataValid = '0' then
-- If the size of the UDP payload + IPv4 header (20 bytes) is
-- less than an MTU, then this is the only packet
if conv_integer(r.udpBytesLeft) + 24 <= MTU_SIZE_G then
v.ipPacketLength := r.udpBytesLeft + 24;
v.ipMoreFragments := '0';
v.state := SEND_REMAINDER_PAUSE_S;
else
v.ipPacketLength := conv_std_logic_vector(MTU_SIZE_G,v.ipPacketLength'length);
v.ipMoreFragments := '1';
-- Offset here to stop on the right word
v.mtuCount := conv_std_logic_vector(MTU_SIZE_G - 20 - 4,v.mtuCount'length);
v.state := SEND_MTU_PAUSE_S;
end if;
end if;
when SEND_MTU_PAUSE_S =>
v.state := SEND_MTU_S;
when SEND_MTU_S =>
ipData <= udpData;
ipDataValid <= udpDataValid;
udpDataReady <= ipDataReady;
if ipDataReady = '1' and udpDataValid = '1' then
v.mtuCount := r.mtuCount - 4;
v.udpBytesLeft := r.udpBytesLeft - 4;
if r.mtuCount = 0 then
v.ipFragOffset := r.ipFragOffset + ( (MTU_SIZE_G-20)/8 );
v.state := CHECK_SIZE_S;
end if;
end if;
when SEND_REMAINDER_PAUSE_S =>
v.state := SEND_REMAINDER_S;
when SEND_REMAINDER_S =>
ipData <= udpData;
ipDataValid <= udpDataValid;
udpDataReady <= ipDataReady;
if ipDataReady = '1' and udpDataValid = '1' then
v.udpBytesLeft := r.udpBytesLeft - 4;
if r.udpBytesLeft = 0 then
v.udpAck := '1';
v.state := WAIT_S;
end if;
end if;
when WAIT_S =>
if udpReq = '0' then
v.ipPacketId := r.ipPacketId + 1;
v.udpAck := '0';
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (ethTxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
ipPacketLength <= r.ipPacketLength;
ipPacketId <= r.ipPacketId;
ipMoreFragments <= r.ipMoreFragments;
ipFragOffset <= r.ipFragOffset;
ipProtocol <= r.ipProtocol;
udpAck <= r.udpAck;
-- ipData <= r.ipData;
-- ipDataValid <= r.ipDataValid;
-- Assign variable to signal
rin <= v;
end process;
seq : process (ethTxClk) is
begin
if (rising_edge(ethTxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | fe1676e37c6880405a02db5319bbcaab | 0.476758 | 4.345387 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/ROM_Controller.vhd | 1 | 11,229 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
-- so, acc, hold: in STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
address_in: in STD_LOGIC_VECTOR(23 downto 0);
qd: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(63 downto 0);
--pragma synthesis_off
counter: out integer;
--pragma synthesis_on
-- command_int, address_int, reg_one_int, reg_two_int: inout integer;
done: out STD_LOGIC
);
end ROM_controller_SPI;
architecture Behavioral of ROM_controller_SPI is
signal CFGCLK, CFGMCLK, EOS, PREQ: std_logic;
signal SCLK: std_logic := '0';
signal read_command: std_logic_vector(8 downto 0) := (0=>'0', 1=>'0', 2=>'0', 3=>'0', 4=>'0',5=>'0',6=>'1',7=>'1', 8 => '0');
signal address_signal: std_logic_vector(23 downto 0) := (others => '0');
signal command_ctr, address_ctr, data_1_ctr, data_2_ctr, dummy_ctr: natural := 0;
signal done_1_flag, done_2_flag: std_logic := '1';
signal data_register_1, data_register_2 : std_logic_vector(63 downto 0) := (others => '0');
type spi_states is (idle, command, address, data_out_one_low, data_out_one_high, data_out_two, dummy, deasrt);
signal curr_state, next_state : spi_states := idle;
signal sckl_o,locked : std_logic;
signal s_t_si: std_logic;
signal s_clok_wat: std_logic := '0';
signal data_counter: natural := 0;
signal stop: std_logic := '0';
signal s_done: std_logic := '0';
signal retarded_counter : integer := 0;
signal one_clock_cycle: integer := 0;
signal s_read: std_logic;
signal counter_s : std_logic;
signal counter_o : std_logic_vector(30 downto 0) := (others => '0');
signal buffered_read : std_logic;
begin
retarded_ctr_adder: process(clk_25, rst) begin
if(rst = '1') then
retarded_counter <= 0;
elsif(rising_edge(clk_25)) then
if(read = '1' and retarded_counter < 100) then
retarded_counter <= retarded_counter + 1;
end if;
end if;
end process;
read_proc: process(clk_25, rst, read) begin
if(rst = '1') then
one_clock_cycle <= 0;
s_read <= '0';
elsif(rising_edge(clk_25) and read = '1') then
one_clock_cycle <= one_clock_cycle + 1;
if(one_clock_cycle = 0) then
s_read <= '1';
elsif(one_clock_cycle = 1) then
s_read <= '0';
end if;
end if;
end process;
latch_qd: process(qd(1)) begin
buffered_read <= qd(1);
end process;
retarded_ctr_fsm: process(clk_25, rst, s_read) begin
if(rst = '1') then
cs_n <= '1';
SCLK <= '0';
si_t <= '0';
wp_t <= '1';
data_out <= (others => '0');
-- data_register_1 <= (others => '0');
elsif(rising_edge(clk_25)) then
if(retarded_counter > 0) then
sclk <= sclk xor '1';
end if;
case retarded_counter is
when 0 =>
si_t <= '0';
s_done <= '0';
si_i <= '0';
wp <= '0';
cs_n <= '1';
if(s_read = '1') then
cs_n <= '0';
end if;
wp_t <= '1';
when 1 => -- Wait for cs_n to propagate (?)
cs_n <= '0';
-- Opcode in starts
when 2 =>
si_i <= '0';
when 3 =>
si_i <= '0';
when 4 =>
si_i <= '0';
when 5 =>
si_i <= '0';
when 6 =>
si_i <= '0';
when 7 =>
si_i <= '0';
when 8 =>
si_i <= '1';
when 9 =>
si_i <= '1';
-- Address_in starts
when 10 =>
--si_t <= '1';
si_i <= address_in(23);
when 11 =>
si_i <= address_in(22);
when 12 =>
si_i <= address_in(21);
when 13 =>
si_i <= address_in(20);
when 14 =>
si_i <= address_in(19);
when 15 =>
si_i <= address_in(18);
when 16 =>
si_i <= address_in(17);
when 17 =>
si_i <= address_in(16);
when 18 =>
si_i <= address_in(15);
when 19 =>
si_i <= address_in(14);
when 20 =>
si_i <= address_in(13);
when 21 =>
si_i <= address_in(12);
when 22 =>
si_i <= address_in(11);
when 23 =>
si_i <= address_in(10);
when 24 =>
si_i <= address_in(9);
when 25 =>
si_i <= address_in(8);
when 26 =>
si_i <= address_in(7);
when 27 =>
si_i <= address_in(6);
when 28 =>
si_i <= address_in(5);
when 29 =>
si_i <= address_in(4);
when 30 =>
si_i <= address_in(3);
when 31 =>
si_i <= address_in(2);
when 32 =>
si_i <= address_in(1);
when 33 =>
si_i <= address_in(0);
when 34 =>
si_t <= '1';
-- Start of Data
-- Data comes out MSB first in bytes, like so
-- [7][6][5][4][3][2][1][0] | [7][6][5][4][...]
when 35 =>
data_out(7) <= buffered_read;
when 36 =>
data_out(6) <= buffered_read;
when 37 =>
data_out(5) <= buffered_read;
when 38 =>
data_out(4) <= buffered_read;
when 39 =>
data_out(3) <= buffered_read;
when 40 =>
data_out(2) <= buffered_read;
when 41 =>
data_out(1) <= buffered_read;
when 42 =>
data_out(0) <= buffered_read;
when 43 =>
data_out(15) <= buffered_read;
when 44 =>
data_out(14) <= buffered_read;
when 45 =>
data_out(13) <= buffered_read;
when 46 =>
data_out(12) <= buffered_read;
when 47 =>
data_out(11) <= buffered_read;
when 48 =>
data_out(10) <= buffered_read;
when 49 =>
data_out(9) <= buffered_read;
when 50 =>
data_out(8) <= buffered_read;
-- Byte 3
when 51 =>
data_out(23) <= buffered_read;
when 52 =>
data_out(22) <= buffered_read;
when 53 =>
data_out(21) <= buffered_read;
when 54 =>
data_out(20) <= buffered_read;
when 55 =>
data_out(19) <= buffered_read;
when 56 =>
data_out(18) <= buffered_read;
when 57 =>
data_out(17) <= buffered_read;
when 58 =>
data_out(16) <= buffered_read;
-- Byte 4
when 59 =>
data_out(31) <= buffered_read;
when 60 =>
data_out(30) <= buffered_read;
when 61 =>
data_out(29) <= buffered_read;
when 62 =>
data_out(28) <= buffered_read;
when 63 =>
data_out(27) <= buffered_read;
when 64 =>
data_out(26) <= buffered_read;
when 65 =>
data_out(25) <= buffered_read;
when 66 =>
data_out(24) <= buffered_read;
-- Byte 5
when 67 =>
data_out(39) <= buffered_read;
when 68 =>
data_out(38) <= buffered_read;
when 69 =>
data_out(37) <= buffered_read;
when 70 =>
data_out(36) <= buffered_read;
when 71 =>
data_out(35) <= buffered_read;
when 72 =>
data_out(34) <= buffered_read;
when 73 =>
data_out(33) <= buffered_read;
when 74 =>
data_out(32) <= buffered_read;
-- Byte 6
when 75 =>
data_out(47) <= buffered_read;
when 76 =>
data_out(46) <= buffered_read;
when 77 =>
data_out(45) <= buffered_read;
when 78 =>
data_out(44) <= buffered_read;
when 79 =>
data_out(43) <= buffered_read;
when 80 =>
data_out(42) <= buffered_read;
when 81 =>
data_out(41) <= buffered_read;
when 82 =>
data_out(40) <= buffered_read;
-- Byte 7
when 83 =>
data_out(55) <= buffered_read;
when 84 =>
data_out(54) <= buffered_read;
when 85 =>
data_out(53) <= buffered_read;
when 86 =>
data_out(52) <= buffered_read;
when 87 =>
data_out(51) <= buffered_read;
when 88 =>
data_out(50) <= buffered_read;
when 89 =>
data_out(49) <= buffered_read;
when 90 =>
data_out(48) <= buffered_read;
-- Byte 8
when 91 =>
data_out(63) <= buffered_read;
when 92 =>
data_out(62) <= buffered_read;
when 93 =>
data_out(61) <= buffered_read;
when 94 =>
data_out(60) <= buffered_read;
when 95 =>
data_out(59) <= buffered_read;
when 96 =>
data_out(58) <= buffered_read;
when 97 =>
data_out(57) <= buffered_read;
when 98 =>
data_out(56) <= buffered_read;
cs_n <= '1';
done <= '1';
si_t <= '0';
when others =>
end case;
end if;
end process;
-- QUAD command if switch 2 is off, SINGLE READ if switch 2 is on
read_command <= (0=>'0', 1=>'0', 2=>'0', 3=>'0', 4=>'0',5=>'0',6=>'1',7=>'1', 8 => '0');
--done <= s_done;
address_signal <= address_in;
--data_out <= data_register_1;
--pragma synthesis_off
counter <= retarded_counter;
--pragma synthesis_on
end Behavioral; | mit | 96bf418c35a7f398c3577e0362f33ab8 | 0.401015 | 3.930347 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/remote_sources/_/lib/digilent/PWM.vhd | 1 | 3,290 | ----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 19:44:54 04/12/2011
-- Design Name:
-- Module Name: PWM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Pulse-Width Modulator with center-aligned pulses, variable
-- PWM frequency and resolution.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PWM is
Generic (
C_CLK_I_FREQUENCY : natural := 50; -- in MHZ
C_PWM_FREQUENCY : natural := 20000; -- in Hz
C_PWM_RESOLUTION : natural := 8
);
Port (
CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
PWM_O : out STD_LOGIC;
DUTY_FACTOR_I : in STD_LOGIC_VECTOR (C_PWM_RESOLUTION-1 downto 0)
);
end PWM;
architecture Behavioral of PWM is
constant C_CLOCK_DIVIDER : natural := C_CLK_I_FREQUENCY*1_000_000/C_PWM_FREQUENCY/2/2**C_PWM_RESOLUTION;
signal PWMCnt : STD_LOGIC_VECTOR (C_PWM_RESOLUTION-1 downto 0) := (others => '0');
signal PWMCntEn, int_PWM : std_logic;
begin
----------------------------------------------------------------------------------
-- Pre-scaler
----------------------------------------------------------------------------------
process (CLK_I)
variable PSCnt : natural range 0 to C_CLOCK_DIVIDER := 0;
begin
if CLK_I='1' and CLK_I'event then
if (PSCnt = C_CLOCK_DIVIDER) then
PSCnt := 0;
PWMCntEn <= '1'; --enable pulse for PWM counter
else
PSCnt := PSCnt + 1;
PWMCntEn <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Up/Down counter for mid-aligned PWM pulse
-- In designs with multiple PWM chanels mid-alignment eliminates simultaneously
-- switching PWM outputs, resulting in less stress on power rails.
----------------------------------------------------------------------------------
process (CLK_I)
variable PWMCntUp : boolean := true;
begin
if CLK_I='1' and CLK_I'event then
if (RST_I='1') then
PWMCnt <= (others => '0');
elsif (PWMCntEn='1') then
if (PWMCntUp) then
PWMCnt <= PWMCnt + 1;
else
PWMCnt <= PWMCnt - 1;
end if;
end if;
if (PWMCnt = 0) then
PWMCntUp := true;
elsif (PWMCnt = 2**C_PWM_RESOLUTION-1) then
PWMCntUp := false;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- PWM output
----------------------------------------------------------------------------------
process (CLK_I, RST_I)
begin
if Rising_Edge(CLK_I) then
if PWMCnt < DUTY_FACTOR_I then
int_PWM <= '1';
else
int_PWM <= '0';
end if;
end if;
end process;
PWM_O <= 'Z' when RST_I = '1' else
int_PWM;
end Behavioral;
| gpl-3.0 | f4e0a83de2587387acde195d63e1089e | 0.518237 | 3.834499 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/UART_TX.vhd | 1 | 4,822 | ----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
--pragma synthesis_off
--txState <= RDY;
--pragma synthesis_on
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
| mit | 0e6bb2245227aca412895bafc020406a | 0.551224 | 3.712086 | false | false | false | false |
SLongofono/Senior_Design_Capstone | solid_C/config.vhd | 1 | 36,765 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
constant INIT_WAIT : integer := 100;
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant ALL_ZERO : STD_LOGIC_VECTOR( 63 downto 0 ) := ( others => '0');
constant ALL_ONES : STD_LOGIC_VECTOR( 63 downto 0 ) := ( others => '1');
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant zero_byte: std_logic_vector(7 downto 0) := "00000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
constant DEBUG_COMMAND_NONE : STD_LOGIC_VECTOR( 7 downto 0 ) := x"00";
constant DEBUG_COMMAND_STEP : STD_LOGIC_VECTOR( 7 downto 0 ) := x"73";
constant DEBUG_COMMAND_CONT : STD_LOGIC_VECTOR( 7 downto 0 ) := x"63";
constant DEBUG_COMMAND_PHYS : STD_LOGIC_VECTOR( 7 downto 0 ) := x"70";
constant DEBUG_COMMAND_VIRT : STD_LOGIC_VECTOR( 7 downto 0 ) := x"76";
constant UART_RX_DATA : doubleword := x"0000000098010000";
constant UART_RX_READY : doubleword := x"0000000098010001";
constant UART_RX_RESET : doubleword := x"0000000098010002";
constant UART_TX_DATA : doubleword := x"0000000098010003";
constant UART_TX_READY : doubleword := x"0000000098010004";
constant UART_TX_SEND : doubleword := x"0000000098010005";
--- memory constants
constant MEM_FETCH : STD_LOGIC_VECTOR( 1 downto 0 ) := "00";
constant MEM_LOAD : STD_LOGIC_VECTOR( 1 downto 0 ) := "01";
constant MEM_STORE : STD_LOGIC_VECTOR( 1 downto 0 ) := "10";
constant MEM_BYTES_1 : STD_LOGIC_VECTOR( 1 downto 0 ) := "00";
constant MEM_BYTES_2 : STD_LOGIC_VECTOR( 1 downto 0 ) := "01";
constant MEM_BYTES_4 : STD_LOGIC_VECTOR( 1 downto 0 ) := "10";
constant MEM_BYTES_8 : STD_LOGIC_VECTOR( 1 downto 0 ) := "11";
constant LOAD_RESERVATION_NONE : STD_LOGIC_VECTOR( 63 downto 0 ) := ( others => '1');
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ISA :integer := 0;
constant CSR_PRV :integer := 1;
constant CSR_MSTATUS :integer := 2;
constant MSTATUS_SIE : integer := 1;
constant MSTATUS_MIE : integer := 3;
constant MSTATUS_SPIE : integer := 5;
constant MSTATUS_MPIE : integer := 7;
constant MSTATUS_SPP : integer := 8;
constant MSTATUS_MPP_L : integer := 11;
constant MSTATUS_MPP_H : integer := 12;
constant MSTATUS_MPRV : integer := 17;
constant MSTATUS_SUM : integer := 18;
constant MSTATUS_MXR : integer := 19;
constant MSTATUS_TSR : integer := 22;
constant CSR_MEPC :integer := 3;
constant CSR_MTVAL :integer := 4;
constant CSR_MSCRATCH :integer := 5;
constant CSR_MTVEC :integer := 6;
constant TVEC_MODE_H : integer := 1;
constant TVEC_MODE_L : integer := 0;
constant TVEC_MODE_DIRECT : STD_LOGIC_VECTOR( 1 downto 0 ) := "00";
constant TVEC_MODE_VECTORED : STD_LOGIC_VECTOR( 1 downto 0 ) := "01";
constant TVEC_BASE_H : integer := 63;
constant TVEC_BASE_L : integer := 2;
constant CSR_MCAUSE :integer := 7;
constant CAUSE_INTERRUPT_BIT : integer := 63;
constant CAUSE_INTERRUPT : STD_LOGIC := '1';
constant CAUSE_EXCEPTION : STD_LOGIC := '0';
constant CAUSE_EXCEPTION_HIGH : STD_LOGIC_VECTOR( 63 downto 7 ) := ALL_ZERO( 63 downto 7 );
constant CAUSE_INSTRUCTION_ADDRESS_MISALIGNED : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000000";
constant CAUSE_INSTRUCTION_ACCESS_FAULT : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000001";
constant CAUSE_ILLEGAL_INSTRUCTION : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000010";
constant CAUSE_BREAKPOINT : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000011";
constant CAUSE_LOAD_ADDRESS_MISALIGNED : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000100";
constant CAUSE_LOAD_ACCESS_FAULT : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000101";
constant CAUSE_STORE_AMO_ADDRESS_MISALIGNED : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000110";
constant CAUSE_STORE_AMO_ACCESS_FAULT : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000111";
constant CAUSE_ENV_CALL_U_MODE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001000";
constant CAUSE_ENV_CALL_S_MODE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001001";
constant CAUSE_ENV_CALL_M_MODE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001011";
constant CAUSE_INSTRUCTION_PAGE_FAULT : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001100";
constant CAUSE_LOAD_PAGE_FAULT : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001101";
constant CAUSE_STORE_AMO_PAGE_FAULT : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001111";
-- this exception cannot come from the MMU so use it for no error
constant MEM_ERR_NONE : STD_LOGIC_VECTOR( 6 downto 0 ) := CAUSE_ILLEGAL_INSTRUCTION;
constant CSR_MINSTRET :integer := 8;
constant CSR_MIE :integer := 9;
constant CSR_MIP :integer := 10;
constant MIP_USIP : integer := 0;
constant MIP_USIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000000";
constant MIP_SSIP : integer := 1;
constant MIP_SSIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000001";
constant MIP_MSIP : integer := 3;
constant MIP_MSIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000011";
constant MIP_UTIP : integer := 4;
constant MIP_UTIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000100";
constant MIP_STIP : integer := 5;
constant MIP_STIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000101";
constant MIP_MTIP : integer := 7;
constant MIP_MTIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0000111";
constant MIP_UEIP : integer := 8;
constant MIP_UEIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001000";
constant MIP_SEIP : integer := 9;
constant MIP_SEIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001001";
constant MIP_MEIP : integer := 11;
constant MIP_MEIP_CAUSE : STD_LOGIC_VECTOR( 6 downto 0 ) := "0001011";
constant CSR_MEDELEG :integer := 11;
constant CSR_MIDELEG :integer := 12;
constant CSR_MCOUNTEREN :integer := 13;
constant CSR_SCOUNTEREN :integer := 14;
constant CSR_SEPC :integer := 15;
constant CSR_STVAL :integer := 16;
constant CSR_SSCRATCH :integer := 17;
constant CSR_STVEC :integer := 18;
constant CSR_SATP :integer := 19;
constant SATP_MODE_H : integer := 63;
constant SATP_MODE_L : integer := 60;
constant SATP_MODE_SV39 : STD_LOGIC_VECTOR( 3 downto 0 ) := x"8";
constant SATP_ASID_H : integer := 59;
constant SATP_ASID_L : integer := 44;
constant SATP_PPN_H : integer := 43;
constant SATP_PPN_L : integer := 0;
constant CSR_SCAUSE :integer := 20;
constant CSR_LOAD_RES :integer := 21;
constant CSR_DBG_PHYS :integer := 22;
constant CSR_DBG_VIRT :integer := 23;
constant CSR_MMU_PHYS :integer := 24;
constant CSR_MMU_VIRT :integer := 25;
constant CSR_INSTR :integer := 26;
constant PTE_V : integer := 0;
constant PTE_R : integer := 1;
constant PTE_W : integer := 2;
constant PTE_X : integer := 3;
constant PTE_U : integer := 4;
constant PTE_G : integer := 5;
constant PTE_A : integer := 6;
constant PTE_D : integer := 7;
constant PTE_RSW_L : integer := 8;
constant PTE_RSW_H : integer := 9;
constant PTE_PPN_L : integer := 10;
constant PTE_PPN_H : integer := 53;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
type byte_arr is array (0 to 7) of std_logic_vector(7 downto 0);
type vpn_arr is array (0 to 2) of std_logic_vector(8 downto 0);
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
constant FUNC3_CSRRW : std_logic_vector(2 downto 0) := "001";
constant FUNC3_CSRRS : std_logic_vector(2 downto 0) := "010";
constant FUNC3_CSRRC : std_logic_vector(2 downto 0) := "011";
constant FUNC3_CSRRWI : std_logic_vector(2 downto 0) := "101";
constant FUNC3_CSRRSI : std_logic_vector(2 downto 0) := "110";
constant FUNC3_CSRRCI : std_logic_vector(2 downto 0) := "111";
constant CSR_RO : std_logic_vector(1 downto 0) := "11";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
end config;
| mit | f748f2be52810ff6ac87e2f4cb6aa87c | 0.613056 | 3.610784 | false | false | false | false |
DevynCJohnson/Pybooster | geany/filedefs/filetypes.vhdl | 1 | 3,708 | [styling]
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comment_line_bang=comment_line_bang
identifier=identifier
keyword=keyword
number=number
operator=operator
stdfunction=stdfunction
stdoperator=stdoperator
stdpackage=stdpackage
stdtype=stdtype
string=string
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| lgpl-3.0 | 2a234fc1735eb3ab37d7584cc331a759 | 0.849784 | 4.161616 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_08/chip6502.vhd | 1 | 158,981 | ----------------------------------------------------------------------------------
--
-- Takes all the VHDL bits and makes a 6510 (6502) out of them
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity chip6502 is
port (
a : out std_logic_vector(15 downto 0);
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
pi : in std_logic_vector(7 downto 0);
po : out std_logic_vector(7 downto 0);
r1w0 : out std_logic;
sync : out std_logic;
nmi0 : in std_logic;
irq0 : in std_logic;
so0 : in std_logic;
rdy : in std_logic;
res0 : in std_logic;
ph4Xin : in std_logic; -- clock input
ph0 : out std_logic;
ph1 : out std_logic; -- clock on high edge
ph2 : out std_logic -- clock on low edge
);
end chip6502;
architecture interaction of chip6502 is
subtype slv2 is std_logic_vector(1 downto 0);
subtype u8 is unsigned(7 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype word is std_logic_vector(15 downto 0);
constant v_nmi_l : word := x"FFFA";
constant v_nmi_h : word := x"FFFB";
constant v_res_l : word := x"FFFC";
constant v_res_h : word := x"FFFD";
constant v_irq_l : word := x"FFFE";
constant v_irq_h : word := x"FFFF";
component clockgen
port (
ph4Xin : in std_logic;
ph0 : out std_logic;
ph1 : out std_logic;
ph2 : out std_logic;
stg : out slv2;
res0 : in std_logic
);
end component;
subtype clkstg_t is std_logic_vector(1 downto 0);
signal clkStg : clkstg_t;
signal iph0 : std_logic;
signal iph1 : std_logic;
signal iph2 : std_logic;
constant sysclk_PH2_p : clkstg_t := "00";
constant sysclk_PH2_m : clkstg_t := "01";
constant sysclk_PH1_p : clkstg_t := "10";
constant sysclk_PH1_m : clkstg_t := "11";
component ioport8bit is
port (
ce : in std_logic;
clk : in std_logic;
res0 : in std_logic;
r1w0 : in std_logic;
a : in std_logic;
din : in byte;
dout : out byte;
ioi : in byte;
ioo : out byte
);
end component;
signal io_o : byte;
signal io_i : byte;
signal io_ce : std_logic;
signal io_clk : std_logic;
component alu_8bit
port (
a_in : in byte;
b_in : in byte;
c_in : in std_logic;
d_in : in std_logic; -- the dreaded BCD mode
op_in : in unsigned(2 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
r_out : out byte
);
end component;
signal ALUcin : std_logic;
signal ALUdin : std_logic;
signal ALUain : byte;
signal ALUbin : byte;
signal ALUop : unsigned(2 downto 0);
signal ALUrout : byte;
signal ALUnout : std_logic;
signal ALUvout : std_logic;
signal ALUzout : std_logic;
signal ALUcout : std_logic;
signal regbus : byte;
signal outval : byte;
signal abus : word;
signal DBen : std_logic := '1';
signal DBrw : std_logic := '1';
signal dbRE : std_logic;
signal dbWE : std_logic;
signal nDBen : std_logic;
signal aen0 : std_logic := '1';
signal aen1 : std_logic;
alias abus_off is aen0;
subtype seqType is byte;
function countSeq(src : seqType) return seqType is
variable v : unsigned(7 downto 0);
begin
v := unsigned(src);
v := v + 1;
return seqType(v);
end countSeq;
signal seq : seqType := x"00";
subtype dbctl_t is std_logic_vector(2 downto 0);
signal DB_ctl : dbctl_t := "011";
alias dbctl_sync : std_logic is DB_ctl(2);
alias dbctl_off : std_logic is DB_ctl(1);
alias dbctl_r1w0 : std_logic is DB_ctl(0);
subtype aop_t is std_logic_vector(2 downto 0);
signal aop : aop_t := "000";
constant aop_add : aop_t := "000";
constant aop_and : aop_t := "001";
constant aop_or : aop_t := "010";
constant aop_xor : aop_t := "011";
constant aop_lsl : aop_t := "100";
constant aop_lsr : aop_t := "101";
constant aop_rol : aop_t := "110";
constant aop_ror : aop_t := "111";
signal alu_bin_mode : slv2;
constant bin_reg : slv2 := "00";
constant bin_set : slv2 := "01";
constant bin_clr : slv2 := "10";
constant bin_ireg : slv2 := "11";
signal alu_cin_mode : slv2;
constant cin_psw : slv2 := "00";
constant cin_set : slv2 := "01";
constant cin_clr : slv2 := "10";
constant cin_aux : slv2 := "11";
signal alu_din_mode : std_logic;
constant din_clr : std_logic := '0';
constant din_psw : std_logic := '1';
--signal alu_bin_reg : byte;
alias alu_bin_reg : byte is ALUbin;
signal alu_bin_tie : byte;
type stage_t is (
stg_reset,
stg_fetch,
stg_sub_incpc, -- pc++
stg_sub_imm, -- mem=pc++
stg_sub_abs, -- meml=[pc++], memh=[pc++]
stg_sub_absx, -- meml=[X+(PC++)], memh=[C+(PC++)]
stg_sub_absy, -- meml=[Y+(PC++)], memh=[C+(PC++)]
stg_sub_zp, -- meml=[PC++], memh=[0]
stg_sub_zpx, -- meml=[X+(PC++)], memh=[0]
stg_sub_zpy, -- meml=[Y+(PC++)], memh=[0]
stg_sub_indx, -- buf2l=[X+(PC++)], buf2h=[0]. mem=[buf2].w
stg_sub_indy, -- buf2l=[PC++], buf2h=[0], mem=[Y+buf2].w
stg_mem2buf, -- BUF=[mem]
stg_mem2a, -- A=[mem]
stg_aCMPmem, -- NZC=A-[mem]
stg_aADDmem, -- NVZC,A=A+[mem]
stg_aSUBmem, -- NVZC,A=A-[mem]
stg_aORmem, -- A=A|[mem]
stg_aXORmem, -- A=A^[mem]
stg_aANDmem, -- A=A&mem
stg_xCMPmem, -- NZC=X-[mem]
stg_yCMPmem, -- NZC=Y-[mem]
stg_mem2x, -- X=[mem]
stg_mem2y, -- Y=[mem]
stg_a2mem, -- [mem]=A
stg_x2mem, -- [mem]=X
stg_y2mem, -- [mem]=Y
stg_ASLmem, -- ***TODO*** C <-- [7][mem][0] <-- 0
stg_ROLmem, -- ***TODO*** C <-- [7][mem][0] <-- C
stg_LSRmem, -- ***TODO*** 0 --> [7][mem][0] --> C
stg_RORmem, -- ***TODO*** C --> [7][mem][0] --> C
stg_INCmem, -- NZ=++[mem]
stg_DECmem, -- NZ=--[mem]
stg_BITmem, -- Z=[mem]&A, NV=[mem][7:6]
stg_BRK, -- ***TODO*** ++PC, B=1, raise (unmaskable) IRQ
stg_IRQ, -- [SP--]=PCH, [SP--]=PCL, [SP--]=PSW, I=1, PCL=[v_irq_l], PCH=[v_irq_h]
stg_NMI, -- [SP--]=PCH, [SP--]=PCL, [SP--]=PSW, I=1, PCL=[v_nmi_l], PCH=[v_nmi_h]
stg_CLC,
stg_SEC,
stg_CLI,
stg_SEI,
stg_CLV,
stg_CLD,
stg_SED,
stg_TXS,
stg_TSX,
stg_PHA,
stg_PLA,
stg_PHP,
stg_PLP,
stg_TAX,
stg_TXA,
stg_TAY,
stg_TYA,
stg_DEX,
stg_DEY,
stg_INX,
stg_INY,
stg_JMP_abs,
stg_JMP_ind,
stg_reljmp, -- take branch
stg_BCC,
stg_BCS,
stg_BNE,
stg_BEQ,
stg_BPL,
stg_BMI,
stg_BVC,
stg_BVS,
stg_ASL_a,
stg_LSR_a,
stg_ROL_a,
stg_ROR_a,
stg_RTS,
stg_RTI,
stg_JSR,
stg_tail
);
signal seq_stage : stage_t := stg_reset;
signal ret_stage : stage_t := stg_fetch; -- return stage for sub stage
signal ir : byte := x"00";
signal reg_a : byte := x"00";
signal reg_x : byte := x"00";
signal reg_y : byte := x"00";
signal reg_pc : word := x"0000";
signal reg_sp : byte := x"00";
signal reg_p : byte := x"00";
alias psw_n is reg_p(7);
alias psw_v is reg_p(6);
alias psw_b is reg_p(4);
alias psw_d is reg_p(3);
alias psw_i is reg_p(2);
alias psw_z is reg_p(1);
alias psw_c is reg_p(0);
signal buf_data : byte := x"00";
signal buf_addr : word := x"0000";
signal buf2 : word := x"0000";
alias reg_pcl : byte is reg_pc(7 downto 0);
alias reg_pch : byte is reg_pc(15 downto 8);
alias buf_addr_l : byte is buf_addr(7 downto 0);
alias buf_addr_h : byte is buf_addr(15 downto 8);
alias buf2l : byte is buf2(7 downto 0);
alias buf2h : byte is buf2(15 downto 8);
signal private_c : std_logic;
signal NMI_last : std_logic;
function isZero(src: byte) return std_logic is
begin
return ((src(0) nor src(1)) and (src(2) nor src(3))) and
((src(4) nor src(5)) and (src(6) nor src(7)));
end isZero;
function dec(arg : byte) return byte is
variable argu : unsigned(8 downto 0);
begin
argu := ('0' & u8(arg)) - "000000001";
return byte(argu(7 downto 0));
end dec;
function inc(arg : byte) return byte is
variable argu : unsigned(8 downto 0);
begin
argu := ('0' & u8(arg)) + "000000001";
return byte(argu(7 downto 0));
end inc;
function inc16(arg : word) return word is
variable argu : unsigned(16 downto 0);
begin
argu := ('0' & u16(arg)) + ('0' & x"01");
return word(argu(15 downto 0));
end inc16;
function sgn(arg : byte) return byte is
begin
return arg(7) & arg(7) & arg(7) & arg(7) &
arg(7) & arg(7) & arg(7) & arg(7);
end sgn;
function getb(arg : byte; bp : integer) return std_logic is
begin
return arg(bp);
end getb;
begin
clock: clockgen port map(
ph4Xin => ph4Xin,
ph0 => iph0,
ph1 => iph1,
ph2 => iph2,
stg => clkStg,
res0 => res0
);
ph0 <= iph0;
ph1 <= iph1;
ph2 <= iph2;
io8bit: ioport8bit port map(
ce => io_ce,
clk => io_clk,
res0 => res0,
r1w0 => dbRW,
a => abus(0),
din => io_i,
dout => io_o,
ioi => pi,
ioo => po
);
io_clk <= (not clkStg(1)) and clkStg(0);
io_ce <= not ( (((abus(15) or abus(14)) or (abus(13) or abus(12))) or
((abus(11) or abus(10)) or (abus( 9) or abus( 8)))) or
(((abus( 7) or abus( 6)) or (abus( 5) or abus( 4))) or
((abus( 3) or abus( 2)) or abus( 1) )) );
io_i <= regbus;
alunit: alu_8bit port map(
a_in => ALUain,
b_in => ALU_bin_tie,
c_in => ALUcin,
d_in => ALUdin,
op_in => ALUop,
n_out => ALUnout,
v_out => ALUvout,
z_out => ALUzout,
c_out => ALUcout,
r_out => ALUrout
);
alu_cin_mux: process(alu_cin_mode,psw_c,private_c) is
begin
case alu_cin_mode is
when cin_set => ALUcin <= '1';
when cin_clr => ALUcin <= '0';
when cin_aux => ALUcin <= private_c;
when others => ALUcin <= psw_c;
end case;
end process alu_cin_mux;
alu_din_mux: process(alu_din_mode,psw_d) is
begin
case alu_din_mode is
when din_clr => ALUdin <= '0';
when others => ALUdin <= psw_d;
end case;
end process alu_din_mux;
alu_bin_mux: process(alu_bin_mode,alu_bin_reg) is
begin
case alu_bin_mode is
when bin_clr => alu_bin_tie <= "00000000";
when bin_set => alu_bin_tie <= "11111111";
when bin_ireg => alu_bin_tie <= not alu_bin_reg;
when others => alu_bin_tie <= alu_bin_reg;
end case;
end process alu_bin_mux;
sync <= DB_ctl(2);
DBen <= DB_ctl(1);
DBrw <= DB_ctl(0);
nDBen <= not DBen;
DBre <= DBrw;
DBwe <= not DBrw;
aen1 <= not aen0;
r1w0 <= DBrw;
ALUop <= unsigned(aop);
-- Allow connection of data bus as output during write operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_ogate: process(nDBen,DBwe,outval) iS
begin
if ((nDBen and DBwe) = '1') then
if (io_ce='1') then
do <= io_o;
else
do <= outval;
end if;
else
do <= "ZZZZZZZZ";
end if;
end process db_ogate;
-- Allow connection of data bus as input during read operations or disconnected
-- (high-Z) otherwise allowing other devices to use data bus while the CPU is halted.
db_igate: process(nDBen,DBre,di) is
begin
if ((nDBen and DBre) = '1') then
regbus <= di;
else
regbus <= "ZZZZZZZZ";
end if;
end process db_igate;
addr_gate: process(aen1,abus) is
begin
if (aen1='1') then
a <= abus;
else
a <= "ZZZZZZZZZZZZZZZZ";
end if;
end process addr_gate;
main_proc: process(res0,ph4Xin) is
variable doNMI : std_logic;
variable tmp8 : byte;
begin
-- Status register stuff
reg_p(5) <= '0';
if (so0 = '0') then
psw_V <= '1';
end if;
if (res0 = '0') then
seq <= x"00";
seq_stage <= stg_reset;
ret_stage <= stg_reset;
dbctl_r1w0 <= '1';
dbctl_off <= '1';
dbctl_sync <= '0';
abus_off <= '1';
doNMI := '0';
elsif (rising_edge(ph4Xin)) then
-- allows sensing NMI on any clock
-- (but won't trigger until epilogue)
doNMI := doNMI or (NMI_last and (not nmi0)); -- only on transition to '0'
NMI_last <= nmi0; -- saves the state read
-- reset stage
if (seq_stage = stg_reset) then
if ((not (clkStg = sysclk_PH2_m)) and seq=x"00") then
else
-- we enter here at seq x00 on PH1+
case seq is
when x"00" => seq <= countSeq(seq); -- PH1+: put RES vector L on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= v_res_l;
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) write to PCL
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put RES vector H on abus
abus <= v_res_h;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
seq_stage <= stg_fetch; -- change to instruction decode
seq <= x"00";
when others => null;
end case;
end if;
end if;
-- instruction fetch/decode stage
if (seq_stage = stg_fetch) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
dbctl_sync <= '1'; -- sync on for instruction decode
abus_off <= '0';
abus <= reg_pc; -- PC on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) get instruction
ir <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: sync off
dbctl_sync <= '0';
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"05" => -- PH1-: store PCL=1+PCL
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"07" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
if (rdy = '1') then
abus_off <= '0';
dbctl_off <= '0';
seq <= x"00";
case ir is
when x"4C" =>
seq_stage <= stg_JMP_abs; -- JMP abs
when x"6C" =>
seq_stage <= stg_JMP_ind; -- JMP ind
when x"18" =>
seq_stage <= stg_CLC; -- CLC
when x"38" =>
seq_stage <= stg_SEC; -- SEC
when x"58" =>
seq_stage <= stg_CLI; -- CLI
when x"78" =>
seq_stage <= stg_SEI; -- SEI
when x"B8" =>
seq_stage <= stg_CLV; -- CLV
when x"D8" =>
seq_stage <= stg_CLD; -- CLD
when x"F8" =>
seq_stage <= stg_SED; -- SED
when x"A9" => -- LDA
ret_stage <= stg_mem2a; -- imm
seq_stage <= stg_sub_imm;
when x"AD" => -- abs
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_abs;
when x"BD" => -- abs+x
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_absx;
when x"B9" => -- abs+y
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_absy;
when x"A5" => -- zp
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_zp;
when x"B5" => -- zp+x
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_zpx;
when x"A1" => -- indirect,X
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_indx;
when x"B1" => -- indirect,Y
ret_stage <= stg_mem2a;
seq_stage <= stg_sub_indy;
when x"A2" => -- LDX
ret_stage <= stg_mem2x; -- imm
seq_stage <= stg_sub_imm;
when x"AE" => -- abs
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_abs;
when x"BE" => -- abs+y
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_absy;
when x"A6" => -- zp
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_zp;
when x"B6" => -- zp+y
ret_stage <= stg_mem2x;
seq_stage <= stg_sub_zpy;
when x"A0" => -- LDY
ret_stage <= stg_mem2y; -- imm
seq_stage <= stg_sub_imm;
when x"AC" => -- abs
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_abs;
when x"BC" => -- abs+x
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_absx;
when x"A4" => -- zp
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_zp;
when x"B4" => -- zp+x
ret_stage <= stg_mem2y;
seq_stage <= stg_sub_zpx;
when x"8D" => -- STA
ret_stage <= stg_a2mem; -- abs
seq_stage <= stg_sub_abs;
when x"9D" => -- abs+x
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_absx;
when x"99" => -- abs+y
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_absy;
when x"85" => -- zp
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_zp;
when x"95" => -- zp+x
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_zpx;
when x"81" => -- indirect,X
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_indx;
when x"91" => -- indirect,Y
ret_stage <= stg_a2mem;
seq_stage <= stg_sub_indy;
when x"8E" => -- STX
ret_stage <= stg_x2mem; -- abs
seq_stage <= stg_sub_abs;
when x"86" => -- zp
ret_stage <= stg_x2mem;
seq_stage <= stg_sub_zp;
when x"96" => -- zp+y
ret_stage <= stg_x2mem;
seq_stage <= stg_sub_zpy;
when x"8C" => -- STY
ret_stage <= stg_y2mem; -- abs
seq_stage <= stg_sub_abs;
when x"84" => -- zp
ret_stage <= stg_y2mem;
seq_stage <= stg_sub_zp;
when x"94" => -- zp+x
ret_stage <= stg_y2mem;
seq_stage <= stg_sub_zpx;
when x"09" => -- ORA A | mem
ret_stage <= stg_aORmem; -- imm
seq_stage <= stg_sub_imm;
when x"0D" => -- abs
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_abs;
when x"1D" => -- abs+x
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_absx;
when x"19" => -- abs+y
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_absy;
when x"05" => -- zp
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_zp;
when x"15" => -- zp+x
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_zpx;
when x"01" => -- indirect,X
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_indx;
when x"11" => -- indirect,Y
ret_stage <= stg_aORmem;
seq_stage <= stg_sub_indy;
when x"29" => -- AND A & mem
ret_stage <= stg_aANDmem; -- imm
seq_stage <= stg_sub_imm;
when x"2D" => -- abs
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_abs;
when x"3D" => -- abs+x
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_absx;
when x"39" => -- abs+y
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_absy;
when x"25" => -- zp
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_zp;
when x"35" => -- zp+x
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_zpx;
when x"21" => -- indirect,X
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_indx;
when x"31" => -- indirect,Y
ret_stage <= stg_aANDmem;
seq_stage <= stg_sub_indy;
when x"24" => -- BIT Z=A&M, NV=[MEM][7:6]
ret_stage <= stg_BITmem; -- zp
seq_stage <= stg_sub_zp;
when x"2C" => -- abs
ret_stage <= stg_BITmem;
seq_stage <= stg_sub_abs;
when x"49" => -- EOR A ^ mem
ret_stage <= stg_aXORmem; -- imm
seq_stage <= stg_sub_imm;
when x"4D" => -- abs
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_abs;
when x"5D" => -- abs+x
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_absx;
when x"59" => -- abs+y
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_absy;
when x"45" => -- zp
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_zp;
when x"55" => -- zp+x
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_zpx;
when x"41" => -- indirect,X
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_indx;
when x"51" => -- indirect,Y
ret_stage <= stg_aXORmem;
seq_stage <= stg_sub_indy;
when x"69" => -- ADC C + A + mem
ret_stage <= stg_aADDmem; -- imm
seq_stage <= stg_sub_imm;
when x"6D" => -- abs
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_abs;
when x"7D" => -- abs+x
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_absx;
when x"79" => -- abs+y
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_absy;
when x"65" => -- zp
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_zp;
when x"75" => -- zp+x
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_zpx;
when x"61" => -- indirect,X
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_indx;
when x"71" => -- indirect,Y
ret_stage <= stg_aADDmem;
seq_stage <= stg_sub_indy;
when x"C9" => -- CMP NZC = A - mem
ret_stage <= stg_aCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"CD" => -- abs
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_abs;
when x"DD" => -- abs+x
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_absx;
when x"D9" => -- abs+y
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_absy;
when x"C5" => -- zp
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_zp;
when x"D5" => -- zp+x
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_zpx;
when x"C1" => -- indirect,X
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_indx;
when x"D1" => -- indirect,Y
ret_stage <= stg_aCMPmem;
seq_stage <= stg_sub_indy;
when x"C0" => -- CPY NZC = Y - mem
ret_stage <= stg_yCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"C4" => -- zp
ret_stage <= stg_yCMPmem;
seq_stage <= stg_sub_zp;
when x"CC" => -- abs
ret_stage <= stg_yCMPmem;
seq_stage <= stg_sub_abs;
when x"E0" => -- CPX NZC = X - mem
ret_stage <= stg_xCMPmem; -- imm
seq_stage <= stg_sub_imm;
when x"E4" => -- zp
ret_stage <= stg_xCMPmem;
seq_stage <= stg_sub_zp;
when x"EC" => -- abs
ret_stage <= stg_xCMPmem;
seq_stage <= stg_sub_abs;
when x"E9" => -- SBC A + C - (mem+1)
ret_stage <= stg_aSUBmem; -- imm
seq_stage <= stg_sub_imm;
when x"ED" => -- abs
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_abs;
when x"FD" => -- abs+x
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_absx;
when x"F9" => -- abs+y
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_absy;
when x"E5" => -- zp
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_zp;
when x"F5" => -- zp+x
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_zpx;
when x"E1" => -- indirect,X
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_indx;
when x"F1" => -- indirect,Y
ret_stage <= stg_aSUBmem;
seq_stage <= stg_sub_indy;
when x"9A" => -- TXS sp=x
seq_stage <= stg_TXS;
when x"BA" => -- TSX x=sp
seq_stage <= stg_TSX;
when x"48" => -- PHA [sp--]=a
seq_stage <= stg_PHA;
when x"68" => -- PLA a=[++sp]
seq_stage <= stg_PLA;
when x"08" => -- PHP [sp--]=P
seq_stage <= stg_PHP;
when x"28" => -- PLP P=[++sp]
seq_stage <= stg_PLP;
when x"AA" => -- TAX X=A
seq_stage <= stg_TAX;
when x"8A" => -- TXA A=X
seq_stage <= stg_TXA;
when x"A8" => -- TAY Y=A
seq_stage <= stg_TAY;
when x"98" => -- TYA A=Y
seq_stage <= stg_TYA;
when x"CA" => -- DEX X=X-1
seq_stage <= stg_DEX;
when x"88" => -- DEY Y=Y-1
seq_stage <= stg_DEY;
when x"C6" => -- DEC --[mem]
ret_stage <= stg_decmem; -- zp
seq_stage <= stg_sub_zp;
when x"D6" =>
ret_stage <= stg_decmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"CE" =>
ret_stage <= stg_decmem; -- abs
seq_stage <= stg_sub_abs;
when x"DE" =>
ret_stage <= stg_decmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"E8" => -- INX X=X+1
seq_stage <= stg_INX;
when x"C8" => -- INY Y=Y+1
seq_stage <= stg_INY;
when x"E6" => -- INC ++[mem]
ret_stage <= stg_incmem; -- zp
seq_stage <= stg_sub_zp;
when x"F6" =>
ret_stage <= stg_incmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"EE" =>
ret_stage <= stg_incmem; -- abs
seq_stage <= stg_sub_abs;
when x"FE" =>
ret_stage <= stg_incmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"10" => -- BPL PC+OP when N=0
seq_stage <= stg_BPL;
when x"30" => -- BMI PC+OP when N=1
seq_stage <= stg_BMI;
when x"50" => -- BVC PC+OP when V=0
seq_stage <= stg_BVC;
when x"70" => -- BVS PC+OP when V=1
seq_stage <= stg_BVS;
when x"90" => -- BCC PC+OP when C=0
seq_stage <= stg_BCC;
when x"B0" => -- BCS PC+OP when C=1
seq_stage <= stg_BCS;
when x"D0" => -- BNE PC+OP when Z=0
seq_stage <= stg_BNE;
when x"F0" => -- BEQ PC+OP when Z=1
seq_stage <= stg_BEQ;
when x"0A" => -- ASL C << T << '0'
seq_stage <= stg_ASL_a; -- a
when x"06" =>
ret_stage <= stg_ASLmem; -- zp
seq_stage <= stg_sub_zp;
when x"16" =>
ret_stage <= stg_ASLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"0E" =>
ret_stage <= stg_ASLmem; -- abs
seq_stage <= stg_sub_abs;
when x"1E" =>
ret_stage <= stg_ASLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"2A" => -- ROL C << T << C
seq_stage <= stg_ROL_a; -- a
when x"26" =>
ret_stage <= stg_ROLmem; -- zp
seq_stage <= stg_sub_zp;
when x"36" =>
ret_stage <= stg_ROLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"2E" =>
ret_stage <= stg_ROLmem; -- abs
seq_stage <= stg_sub_abs;
when x"3E" =>
ret_stage <= stg_ROLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"4A" => -- LSR '0' >> T >> C
seq_stage <= stg_LSR_a; -- a
when x"46" =>
ret_stage <= stg_LSRmem; -- zp
seq_stage <= stg_sub_zp;
when x"56" =>
ret_stage <= stg_LSRmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"4E" =>
ret_stage <= stg_LSRmem; -- abs
seq_stage <= stg_sub_abs;
when x"5E" =>
ret_stage <= stg_LSRmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"6A" => -- ROR C >> T >> C
seq_stage <= stg_ROR_a; -- a
when x"66" =>
ret_stage <= stg_ROLmem; -- zp
seq_stage <= stg_sub_zp;
when x"76" =>
ret_stage <= stg_ROLmem; -- zp+x
seq_stage <= stg_sub_zpx;
when x"6E" =>
ret_stage <= stg_ROLmem; -- abs
seq_stage <= stg_sub_abs;
when x"7E" =>
ret_stage <= stg_ROLmem; -- abs+x
seq_stage <= stg_sub_absx;
when x"60" => -- RTS PCH=[++SP],PCL=[++SP],++PC
seq_stage <= stg_RTS;
when x"40" => -- RTI P=[++SP], PCH=[++SP],PCL=[++SP]
seq_stage <= stg_RTI;
when x"20" => -- JSR [email protected] to stack, PC=OP.w
seq_stage <= stg_JSR;
when others =>
seq_stage <= stg_tail; -- NOP
end case;
else
abus_off <= '1'; -- burn a full PH1/PH2 cycle if RDY=0
dbctl_off <= '1';
seq <= x"08";
end if;
when x"08" => seq <= countSeq(seq); -- PH1+: burn
when x"09" => seq <= countSeq(seq); -- PH1-: burn
when x"0A" => seq <= x"07"; -- PH2+: will check RDY again on PH2-
when others => null;
end case;
end if;
-- epilogue stage (also handles NOP)
-- checks for interrupts
if (seq_stage = stg_tail) then
case seq is
when x"00" => -- PH1+: burn
abus_off <= '0'; -- abus enabled
dbctl_off <= '0'; -- dbus enabled
dbctl_r1w0 <= '1'; -- dbus to read
seq <= countSeq(seq);
when x"01" => -- PH1-: burn
seq <= countSeq(seq);
when x"02" => -- PH2+: burn
seq <= countSeq(seq);
when x"03" =>
seq_stage <= stg_fetch; -- PH2-: return to fetch (on PH1+)
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_incpc) then
case seq is
when x"00" => -- PH1+:
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+1
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux; -- apply carry from PCL+1
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C
seq <= x"00";
seq_stage <= ret_stage; -- PH2+: set return-to stage (on PH1+)
when others => null;
end case;
end if;
if (seq_stage = stg_incmem) then -- ++[MEM]
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: read from [MEM]
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr;
alu_cin_mode <= cin_set; -- ALU: Rout=Ain+1
alu_bin_mode <= bin_clr;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
ALUain <= regbus; -- [MEM] => Ain
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- BUS: write to [MEM]
psw_z <= ALUzout; -- NZ,Dout=[MEM]+1
psw_n <= ALUnout;
outval <= ALUrout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq <= x"00";
seq_stage <= stg_tail; -- instruction finished
when others => null;
end case;
end if;
if (seq_stage = stg_decmem) then -- --[MEM]
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0'; -- BUS: read from [MEM]
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr;
alu_cin_mode <= cin_clr; -- ALU: Rout=Ain-1
alu_bin_mode <= bin_set;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
ALUain <= regbus; -- [MEM] => Ain
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- BUS: write to [MEM]
psw_z <= ALUzout; -- NZ,Dout=[MEM]+1
psw_n <= ALUnout;
outval <= ALUrout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq <= x"00";
seq_stage <= stg_tail; -- instruction finished
when others => null;
end case;
end if;
if (seq_stage = stg_reljmp) then
case seq is -- PC+=(signed)BUF
when x"00" => -- PH1+:
ALUain <= reg_pcl;
ALUbin <= buf_data;
alu_cin_mode <= cin_clr;
alu_bin_mode <= bin_reg;
alu_din_mode <= din_clr;
aop <= aop_add;
seq <= countSeq(seq);
when x"01" => -- PH1-: store PCL=PCL+BUF
reg_pcl <= ALUrout;
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
ALUbin <= sgn(buf_data); -- sign extend BUF for PCH
alu_cin_mode <= cin_aux; -- apply carry from PCL+BUF
seq <= countSeq(seq);
when x"03" => -- PH2-:
reg_pch <= ALUrout; -- store PCH=PCH+C+sgn(BUF)
seq <= x"00";
seq_stage <= stg_tail; -- branch finished
when others => null;
end case;
end if;
-- JMP abs
if (seq_stage = stg_JMP_abs) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pch <= regbus;
reg_pcl <= buf_addr_l; -- copy buffered lobyte to PCL
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- JMP ind
if (seq_stage = stg_JMP_ind) then
case seq is
when x"00" => -- PH1+: put PC on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- save to MEML
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) write to PCH
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= buf_addr; -- put MEM on abus
ALUain <= buf_addr_l; -- set up for ++MEM
ALU_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf2l <= ALUrout;
private_c <= ALUcout; -- BUF2=MEM+1
seq <= countSeq(seq);
when x"0a" => -- PH2+:
ALUain <= buf_addr_h; --
ALU_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data)
reg_pcl <= regbus; -- PCL=(MEM)
buf_addr_l <= buf2l;
buf_addr_h <= ALUrout; -- ++MEM
seq <= countSeq(seq);
when x"0c" => -- PH1+:
abus <= buf_addr; -- put MEM (+1) on abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
reg_pch <= regbus; -- PCH=MEM (+1)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2buf) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
buf_data <= regbus; -- save to BUF
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2a) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= regbus; -- save to A
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aANDmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A and regbus; -- A = A & [mem]
psw_z <= isZero(reg_A and regbus); -- Z flag
psw_n <= getb(reg_A and regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_BITmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
psw_z <= isZero(regbus and reg_A); -- Z flag as if A & [mem]
psw_n <= regbus(7); -- N flag <= [mem][7]
psw_v <= regbus(6); -- V flag <= [mem][6]
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aADDmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_psw; -- P.D => din
alu_cin_mode <= cin_psw; -- P.C => cin
alu_bin_mode <= bin_reg; -- reg => bin
ALUain <= reg_a; -- A
aop <= aop_add; -- + P.C +
ALUbin <= regbus; -- mem
seq <= countSeq(seq);
when x"04" => -- PH1+:
reg_a <= ALUrout; -- store result
psw_n <= ALUnout;
psw_v <= ALUvout;
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aSUBmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_psw; -- P.D => din
alu_cin_mode <= cin_psw; -- P.C => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_a; -- A
aop <= aop_add; -- + P.C -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
reg_a <= ALUrout; -- store result
psw_n <= ALUnout;
psw_v <= ALUvout;
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_a; -- A
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_xCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_x; -- X
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_yCMPmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
alu_din_mode <= din_clr; -- 0 => din
alu_cin_mode <= cin_set; -- 1 => cin
alu_bin_mode <= bin_ireg; -- ^reg => bin (1's compliment)
ALUain <= reg_y; -- Y
aop <= aop_add; -- + 1 -
ALUbin <= regbus; -- (mem+1)
seq <= countSeq(seq);
when x"04" => -- PH1+:
psw_n <= ALUnout; -- store result (NZC only)
psw_z <= ALUzout;
psw_c <= ALUcout;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aORmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A or regbus; -- A = A | [mem]
psw_z <= isZero(reg_A or regbus); -- Z flag
psw_n <= getb(reg_A or regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_aXORmem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_a <= reg_A xor regbus; -- A = A ^ [mem]
psw_z <= isZero(reg_A xor regbus); -- Z flag
psw_n <= getb(reg_A xor regbus,7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2x) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_x <= regbus; -- save to X
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_mem2y) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
reg_y <= regbus; -- save to Y
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_a2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_a; -- A to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_x2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_x; -- X to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_y2mem) then
case seq is
when x"00" => -- PH1+: put PC (+1) on abus
dbctl_off <= '0';
dbctl_r1w0 <= '0'; -- write
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => -- PH2+:
outval <= reg_y; -- Y to data out
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_imm) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
buf_addr <= reg_pc; -- MEM=PC
ALUain <= reg_pcl;
alu_cin_mode <= cin_set;
alu_bin_mode <= bin_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout;
alu_cin_mode <= cin_aux;
ALUain <= reg_pch;
seq <= countSeq(seq);
when x"02" => -- PH2+:
reg_pch <= ALUrout; -- PC=PC+1
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) store data to A
seq <= x"00";
seq_stage <= ret_stage;
when others => null;
end case;
end if;
if (seq_stage = stg_sub_abs) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_absx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEM+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr) pass
buf_addr_l <= ALUrout; -- MEML=MEML+X
private_c <= ALUcout;
seq <= countSeq(seq);
when x"0A" => -- PH2+:
ALUain <= buf_addr_h;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux; -- MEMH+C
seq <= countSeq(seq);
when x"0B" => -- PH2-: (valid data)
buf_addr_h <= ALUrout; -- MEMH=MEMH+C
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_absy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_l <= regbus;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
alu_cin_mode <= cin_set;
ALUain <= reg_pcl;
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr) pass
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"06" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to PCH
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
buf_addr_h <= regbus; -- save to MEMH
seq <= countSeq(seq);
when x"08" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEM+Y
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_y; -- MEML+Y
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
private_c <= ALUcout;
seq <= countSeq(seq);
when x"0A" => -- PH2+:
ALUain <= buf_addr_h;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux; -- MEMH+C
seq <= countSeq(seq);
when x"0B" => -- PH2-: (valid data)
buf_addr_h <= ALUrout; -- MEMH=MEMH+C
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zp) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zpx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+X
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_indx) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+X
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_x; -- MEML+X
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- BUF2=00:MEML+X
buf2h <= x"00";
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => seq <= countSeq(seq); -- PH2-: (valid data) pass
when x"08" => -- PH1+:
abus <= buf2; -- buf2 on abus
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
buf_addr_l <= regbus; -- MEML=[buf2++]
buf2 <= inc16(buf2);
seq <= countSeq(seq);
when x"0c" => -- PH1+:
abus <= buf2; -- buf2 (+1) on abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
buf_addr_h <= regbus; -- MEMH=[buf2] (+1)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_zpy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) get MEML
buf_addr_h <= x"00";
buf_addr_l <= regbus; -- MEM = 00:[PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
alu_bin_mode <= bin_reg; -- now do MEML+Y
alu_cin_mode <= cin_clr;
ALUain <= buf_addr_l;
ALUbin <= reg_y; -- MEML+Y
seq <= countSeq(seq);
when x"05" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
seq <= countSeq(seq);
when x"06" => seq <= countSeq(seq); -- PH2+: pass (ZP offset wraps around)
when x"07" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
if (seq_stage = stg_sub_indy) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0';
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
ALUain <= reg_pcl; -- set up for ++PC
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf2l <= ALUrout; -- save to temp since PC in use
buf2h <= x"00";
private_c <= ALUcout;
seq <= countSeq(seq);
when x"02" => -- PH2+:
ALUain <= reg_pch;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data)
buf_addr_l <= regbus; -- MEML = [PC]
reg_pcl <= buf2l;
reg_pch <= ALUrout; -- ++PC
seq <= countSeq(seq);
when x"04" => -- PH1+:
abus <= x"00" & buf_addr_l; -- put 00:MEML on abus
buf2 <= x"00" & buf_addr_l; -- buf2=00:MEML
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) pass
buf_addr_l <= regbus; -- MEML = [BUF2]
buf2 <= inc16(buf2); -- ++buf2
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= buf2; -- buf2 (buf+1) on abus
ALUain <= buf_addr_l; -- start MEM=MEM+Y
ALUbin <= reg_y; -- MEML+Y
ALU_cin_mode <= cin_clr;
ALU_bin_mode <= bin_reg;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
buf_addr_l <= ALUrout; -- MEML=MEML+Y
private_c <= ALUcout;
alu_cin_mode <= cin_aux;
alu_bin_mode <= bin_clr;
seq <= countSeq(seq);
when x"0a" => -- PH2+:
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data)
ALUain <= regbus; -- C+[BUF2] (MSB)
seq <= countSeq(seq);
when x"0c" => -- PH1+:
buf_addr_h <= ALUrout; -- MEMH=C+[BUF2] (MSB)
seq <= countSeq(seq); -- MEM=MEM+Y done
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
seq_stage <= ret_stage;
seq <= x"00";
when others => null;
end case;
end if;
-- CLC
if (seq_stage = stg_CLC) then
case seq is
when x"00" => -- PH1+: C=0
psw_c <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEC
if (seq_stage = stg_SEC) then
case seq is
when x"00" => -- PH1+: C=1
psw_c <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLI
if (seq_stage = stg_CLI) then
case seq is
when x"00" => -- PH1+: I=0
psw_i <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SEI
if (seq_stage = stg_SEI) then
case seq is
when x"00" => -- PH1+: I=1
psw_i <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLV
if (seq_stage = stg_CLV) then
case seq is
when x"00" => -- PH1+: V=0
psw_v <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- CLD
if (seq_stage = stg_CLD) then
case seq is
when x"00" => -- PH1+: D=0
psw_d <= '0';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- SED
if (seq_stage = stg_SED) then
case seq is
when x"00" => -- PH1+: D=1
psw_d <= '1';
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXS
if (seq_stage = stg_TXS) then
case seq is
when x"00" => -- PH1+:
reg_sp <= reg_x; -- store SP=X
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TSX
if (seq_stage = stg_TSX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_sp; -- store X=SP
psw_z <= isZero(reg_sp); -- Z flag
psw_n <= reg_sp(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- PHA
if (seq_stage = stg_PHA) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= reg_a;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PHP
if (seq_stage = stg_PHP) then
case seq is
when x"00" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp to abus
abus_off <= '0';
dbctl_off <= '0'; -- dbus to write
dbctl_r1w0 <= '0';
ALUain <= reg_sp;
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) sp=sp-1
reg_sp <= ALUrout;
seq <= countSeq(seq);
when x"02" => -- PH2+: place a on dbus
outval <= (reg_p(7 downto 6) & "01" &
reg_p(3 downto 0)); -- 6502 quirk: B always set on pushed psw
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) instruction done
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLA
if (seq_stage = stg_PLA) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_a <= regbus;
psw_z <= isZero(regbus); -- Z flag
psw_n <= regbus(7); -- N flag
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- PLP
if (seq_stage = stg_PLP) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- we didn't have addr ready this PH1+
seq <= countSeq(seq); -- so we'll need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have address for bus
abus <= (x"01" & reg_sp); -- 01:sp to abus
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_p <= (regbus(7 downto 6) & "0" &
regbus(4 downto 0)); -- store status value (unused bit forced to 0)
seq_stage <= stg_tail;
seq <= x"00";
when others => null;
end case;
end if;
-- TAX
if (seq_stage = stg_TAX) then
case seq is
when x"00" => -- PH1+:
reg_x <= reg_a; -- store X=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TXA
if (seq_stage = stg_TXA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_x; -- store A=X
psw_z <= isZero(reg_x); -- Z flag
psw_n <= reg_x(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TAY
if (seq_stage = stg_TAY) then
case seq is
when x"00" => -- PH1+:
reg_y <= reg_a; -- store Y=A
psw_z <= isZero(reg_a); -- Z flag
psw_n <= reg_a(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- TYA
if (seq_stage = stg_TYA) then
case seq is
when x"00" => -- PH1+:
reg_a <= reg_y; -- store A=Y
psw_z <= isZero(reg_y); -- Z flag
psw_n <= reg_y(7); -- N flag
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- DEX
if (seq_stage = stg_DEX) then
case seq is
when x"00" => -- PH1+: BUF=x-1
buf_data <= dec(reg_x);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_x <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- DEY
if (seq_stage = stg_DEY) then
case seq is
when x"00" => -- PH1+: BUF=y-1
buf_data <= dec(reg_y);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_y <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- INX
if (seq_stage = stg_INX) then
case seq is
when x"00" => -- PH1+: BUF=x+1
buf_data <= inc(reg_x);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_x <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- INY
if (seq_stage = stg_INY) then
case seq is
when x"00" => -- PH1+: BUF=y+1
buf_data <= inc(reg_y);
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
reg_y <= buf_data;
psw_z <= isZero(buf_data);
psw_n <= buf_data(7);
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- BCC
if (seq_stage = stg_BCC) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_C = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BCS
if (seq_stage = stg_BCS) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_C = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc; -- ++PC then branch or finish
when others => null;
end case;
end if;
-- BNE
if (seq_stage = stg_BNE) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_Z = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BEQ
if (seq_stage = stg_BEQ) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_Z = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BPL
if (seq_stage = stg_BPL) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_N = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BMI
if (seq_stage = stg_BMI) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_N = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BVC
if (seq_stage = stg_BVC) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_V = '0') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- BVS
if (seq_stage = stg_BVS) then
case seq is
when x"00" => -- PH1+: sync on, PC to abus
abus_off <= '0'; -- BUF=branch offset
abus <= reg_pc;
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus on for read
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data) store data to BUF
buf_data <= regbus;
seq <= x"00";
if (psw_V = '1') then
ret_stage <= stg_reljmp; -- branch taken
else
ret_stage <= stg_tail; -- branch not taken
end if;
seq_stage <= stg_sub_incpc;
when others => null;
end case;
end if;
-- ASL A
if (seq_stage = stg_ASL_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := reg_a(6 downto 0) & '0'; -- tmp = A << 1
psw_c <= reg_a(7); -- C = A(7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ASL [mem]
if (seq_stage = stg_ASLmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := regbus(6 downto 0) & '0'; -- tmp = [mem] << 1
psw_c <= regbus(7); -- C = [mem](7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- LSR A
if (seq_stage = stg_LSR_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := '0' & reg_a(7 downto 1); -- tmp = A >> 1
psw_c <= reg_a(0); -- C = A(0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- LSR [mem]
if (seq_stage = stg_LSRmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := '0' & regbus(7 downto 1); -- tmp = [mem] >> 1
psw_c <= regbus(0); -- C = [mem](0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROL A
if (seq_stage = stg_ROL_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := reg_a(6 downto 0) & psw_c; -- tmp = A[6:0],C
psw_c <= reg_a(7); -- C = A(7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROL[mem]
if (seq_stage = stg_ROLmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := regbus(6 downto 0) & psw_c; -- tmp = [mem](6:0),C
psw_c <= regbus(7); -- C = [mem](7)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROR A
if (seq_stage = stg_ROR_a) then
case seq is
when x"00" => -- PH1+:
tmp8 := psw_c & reg_a(7 downto 1); -- tmp = C,A[7:1]
psw_c <= reg_a(0); -- C = A(0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
reg_a <= tmp8; -- A = tmp
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" =>
seq_stage <= stg_tail; -- PH2-: instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- ROR [mem]
if (seq_stage = stg_RORmem) then
case seq is
when x"00" => -- PH1+: put MEM on abus (read)
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= buf_addr; -- put MEM on abus
seq <= countSeq(seq);
when x"01" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => -- PH2-: (valid data)
tmp8 := psw_c & regbus(7 downto 1); -- tmp = C,[mem](7:1)
psw_c <= regbus(0); -- C = [mem](0)
psw_z <= isZero(tmp8); -- Z flag
psw_n <= tmp8(7); -- N flag
outval <= tmp8;
seq <= countSeq(seq);
when x"04" => -- PH1+:
dbctl_r1w0 <= '0'; -- bus to write ([MEM]=tmp)
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
seq_stage <= stg_tail; -- instruction done
seq <= x"00";
when others => null;
end case;
end if;
-- RTS (PCH=[++SP], PCL=[++SP], incpc, tail)
if (seq_stage = stg_RTS) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
buf_data <= ALUrout; -- we didn't have addr ready on PH1+
seq <= countSeq(seq); -- so we'll store this SP+1 in BUF
when x"02" => -- PH2+: and pipeline BUF+1 (SP+2)
ALUain <= buf_data; -- through this bus cycle
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
seq <= countSeq(seq);
when x"03" => seq <= countSeq(seq); -- PH2-: (valid data)
reg_sp <= ALUrout; -- SP=SP+2
seq <= countSeq(seq); -- BUF is PCL, SP is PCH
when x"04" => -- PH1+: put out address of PCL
abus <= (x"01" & buf_data); -- 01:BUF
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data) instruction done
reg_pcl <= regbus;
seq <= countSeq(seq);
when x"08" => -- PH1+: put out address of PCH
abus <= (x"01" & reg_sp); -- 01:SP
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr)
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
reg_pch <= regbus;
seq <= countSeq(seq);
seq <= x"00";
ret_stage <= stg_tail; -- JSR saves PC-1 so we incpc
seq_stage <= stg_sub_incpc; -- first, then tail (done)
when others => null;
end case;
end if;
-- RTI (P=[++SP], PCH=[++SP], PCL=[++SP], tail)
if (seq_stage = stg_RTI) then
case seq is
when x"00" => -- PH1+:
abus_off <= '0';
dbctl_off <= '0';
dbctl_r1w0 <= '1'; -- dbus to read
ALUain <= reg_sp;
alu_bin_mode <= bin_clr; -- sp pre-increment
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr) not yet available
reg_sp <= ALUrout; -- ++SP (now on psw)
ALUain <= ALUrout; -- set up next ++SP
seq <= countSeq(seq); -- we need to wait for next PH1+
when x"02" => seq <= countSeq(seq); -- PH2+: pass
when x"03" => seq <= countSeq(seq); -- PH2-: pass
when x"04" => -- PH1+: now we have addresses for bus
abus <= (x"01" & reg_sp); -- 01:sp (psw) to abus
reg_sp <= ALUrout; -- ++SP (now on PCL)
ALUain <= ALUrout; -- set up next ++SP
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
when x"07" => -- PH2-: (valid data)
reg_p <= (regbus(7 downto 6) & "00" &
regbus(3 downto 0)); -- store psw (unused/brk set to 0)
seq <= countSeq(seq);
when x"08" => -- PH1+:
abus <= (x"01" & reg_sp); -- 01:sp (PCL) to abus
seq <= countSeq(seq);
when x"09" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0a" => seq <= countSeq(seq); -- PH2+: pass
when x"0b" => -- PH2-: (valid data)
reg_pcl <= regbus; -- save PCL=[SP]
reg_sp <= ALUrout; -- ++SP (now on PCH)
seq <= countSeq(seq); -- BUF is PCL, SP is PCH
when x"0c" => -- PH1+: put out address of PCL
abus <= (x"01" & reg_sp); -- 01:sp (PCH) to abus
seq <= countSeq(seq);
when x"0d" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"0e" => seq <= countSeq(seq); -- PH2+: pass
when x"0f" => -- PH2-: (valid data)
reg_pch <= regbus; -- save PCH=[SP]
seq <= x"00";
seq_stage <= stg_tail; -- instruction done
when others => null;
end case;
end if;
-- JSR (buf_addr=[pc].w, ++pc, [sp--]=PCL, [sp--]=PCH)
if (seq_stage = stg_JSR) then
case seq is
when x"00" => -- PH1+:
dbctl_off <= '0';
dbctl_r1w0 <= '1';
abus_off <= '0';
abus <= reg_pc;
ALUain <= reg_pcl;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_set;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"01" => -- PH1-: (valid addr)
reg_pcl <= ALUrout;
private_c <= ALUcout; -- ++PC
seq <= countSeq(seq);
when x"02" => -- PH2+: pass
ALUain <= reg_pch;
alu_bin_mode <= bin_clr;
alu_cin_mode <= cin_aux;
seq <= countSeq(seq);
when x"03" => -- PH2-: (valid data) write to MEML
buf_addr_l <= regbus; -- (we can't store to PC as we're using it)
reg_pch <= ALUrout;
seq <= countSeq(seq);
when x"04" => -- PH1+: put PC (+1) on abus
abus <= reg_pc;
seq <= countSeq(seq);
when x"05" => seq <= countSeq(seq); -- PH1-: (valid addr) pass
when x"06" => seq <= countSeq(seq); -- PH2+: pass
seq <= countSeq(seq);
when x"07" => -- PH2-: (valid data) write to MEMH
buf_addr_h <= regbus; -- (PC not yet saved)
seq <= countSeq(seq);
when x"08" => -- PH1+:
dbctl_r1w0 <= '0'; -- data bus to write mode
abus <= (x"01" & reg_sp); -- put out address of 01:SP
ALUain <= reg_sp; -- set up SP--
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"09" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- SP--
seq <= countSeq(seq);
when x"0a" => seq <= countSeq(seq); -- PH2+:
outval <= reg_pch; -- [01:SP]=PCH
seq <= countSeq(seq);
when x"0b" => -- PH2-: (valid data) pass
seq <= countSeq(seq);
when x"0c" => -- PH1+:
dbctl_r1w0 <= '0'; -- data bus to write mode
abus <= (x"01" & reg_sp); -- put out address of 01:SP
ALUain <= reg_sp; -- set up SP--
alu_bin_mode <= bin_set;
alu_cin_mode <= cin_clr;
alu_din_mode <= din_clr;
seq <= countSeq(seq);
when x"0d" => -- PH1-: (valid addr)
reg_sp <= ALUrout; -- SP--
seq <= countSeq(seq);
when x"0e" => seq <= countSeq(seq); -- PH2+:
outval <= reg_pcl; -- [01:SP]=PCL
seq <= countSeq(seq);
when x"0f" => -- PH2-: (valid data)
dbctl_r1w0 <= '1'; -- shut off write
reg_pc <= buf_addr; -- PC=MEM
seq_stage <= stg_tail;
seq <= x"00"; -- instruction done
when others => null;
end case;
end if;
end if;
end process main_proc;
end interaction;
| gpl-3.0 | 76a7cc19436884355e59b7b18cd15e0f | 0.293123 | 4.951599 | false | false | false | false |
SLongofono/Senior_Design_Capstone | hdl/system_top.vhd | 1 | 9,545 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 04/21/2018 01:23:15 PM
-- Module Name: system_top - Behavioral
-- Description: System-level wrapper for processor components
--
-- Additional Comments: "Death must be so beautiful. To lie in te soft brown earth,
-- with the grasses waving above one's head, and listen to
-- silence. To have no yesterday, and no tomorrow. To forget
-- time, to forget life, to forget Vivado, to be at peace."
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.config.all;
entity system_top is
Port(
clk: in std_logic;
rst: in std_logic;
status: out std_logic;
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0)
);
end system_top;
architecture Behavioral of system_top is
--------------------------------------------------------------------------------
-- Components Forward Declarations
--------------------------------------------------------------------------------
component simple_core is
Port(
status: out std_logic; -- LED blinkenlites
clk: in std_logic; -- System clock (100 MHz)
rst: in std_logic; -- Tied to switch SW0
MMU_addr_in: out doubleword; -- 64-bits address for load/store
MMU_data_in: out doubleword; -- 64-bits data for store
MMU_satp: out doubleword; -- Signals address translation privilege
MMU_mode: out std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
MMU_store: out std_logic; -- High to toggle store
MMU_load: out std_logic; -- High to toggle load
MMU_busy: in std_logic; -- High when busy
MMU_ready_instr: out std_logic; -- Ready for a new instruction (initiates fetch)
MMU_addr_instr: out doubleword; -- Instruction Address (AKA PC)
MMU_alignment: out std_logic_vector(3 downto 0);-- alignment in bytes
MMU_data_out: in doubleword; -- 64-Bits data out for load
MMU_instr_out: in doubleword; -- 64-Bits instruction out for fetch
MMU_error: in std_logic_vector(5 downto 0) -- Error bits from MMU
);
end component;
component MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic := '0'; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out doubleword; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);-- Error
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end component;
--------------------------------------------------------------------------------
-- Signals
--------------------------------------------------------------------------------
signal s_MMU_addr_in: doubleword; -- 64-bits address for load/store
signal s_MMU_data_in: doubleword; -- 64-bits data for store
signal s_MMU_satp: doubleword; -- Signals address translation privilege
signal s_MMU_mode: std_logic_vector(1 downto 0); -- Current operating mode (Machine, Supervisor, Etc)
signal s_MMU_store: std_logic; -- High to toggle store
signal s_MMU_load: std_logic; -- High to toggle load
signal s_MMU_busy: std_logic; -- High when busy
signal s_MMU_ready_instr: std_logic; -- Ready for a new instruction (initiates fetch)
signal s_MMU_addr_instr: doubleword; -- Instruction Address (AKA PC)
signal s_MMU_alignment: std_logic_vector(3 downto 0);-- alignment in bytes
signal s_MMU_data_out: doubleword; -- 64-Bits data out for load
signal s_MMU_instr_out: doubleword; -- 64-Bits instruction out for fetch
signal s_MMU_error: std_logic_vector(5 downto 0); -- Error bits from MMU
begin
--------------------------------------------------------------------------------
-- Instantiations
--------------------------------------------------------------------------------
bestCore: simple_core
port map(
status => status,
clk => clk,
rst => rst,
MMU_addr_in => s_MMU_addr_in,
MMU_data_in => s_MMU_data_in,
MMU_satp => s_MMU_satp,
MMU_mode => s_MMU_mode,
MMU_store => s_MMU_store,
MMU_load => s_MMU_load,
MMU_busy => s_MMU_busy,
MMU_ready_instr => s_MMU_ready_instr,
MMU_addr_instr => s_MMU_addr_instr,
MMU_alignment => s_MMU_alignment,
MMU_data_out => s_MMU_data_out,
MMU_instr_out => s_MMU_instr_out,
MMU_error => s_MMU_error
);
memmy: MMU
port map(
clk => clk,
rst => rst,
addr_in => s_MMU_addr_in,
data_in => s_MMU_data_in,
satp => s_MMU_satp,
mode => s_MMU_mode,
store => s_MMU_store,
load => s_MMU_load,
busy => s_MMU_busy,
ready_instr => s_MMU_ready_instr,
addr_instr => s_MMU_addr_instr,
alignment => s_MMU_alignment,
data_out => s_MMU_data_out,
instr_out => s_MMU_instr_out,
error => s_MMU_error,
LED => LED,
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
sck => sck,
cs_n => cs_n,
dq => dq
);
--------------------------------------------------------------------------------
-- Do Work
--------------------------------------------------------------------------------
end Behavioral;
| mit | 4e67fdfa43f8ee03c680358890821a14 | 0.480985 | 3.978741 | false | false | false | false |
SLongofono/Senior_Design_Capstone | OLD_CORE/testbench/tb_ALU.vhd | 1 | 35,052 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 01/02/2018 02:03:32 PM
-- Module Name: tb_ALU - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
entity tb_ALU is
-- Port ( );
end tb_ALU;
architecture Behavioral of tb_ALU is
-- Component declarations
component ALU is
port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
halt: in std_logic; -- Do nothing
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end component;
-- Signals and constants
constant t_per: time := 1 ns;
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal s_halt: std_logic := '0';
signal s_ctrl: instr_t := "00000000";
signal s_rs1: doubleword := (others => '0');
signal s_rs2: doubleword := (others => '0');
signal s_shamt: std_logic_vector(4 downto 0) := "00000";
signal s_rd: doubleword := (others => '0');
signal s_zero : std_logic := '0';
signal s_overflow : std_logic := '0';
signal s_error : std_logic := '0';
begin
-- Instantiate components
myALU: ALU
port map(
clk => clk,
rst => rst,
halt => s_halt,
ctrl => s_ctrl,
rs1 => s_rs1,
rs2 => s_rs2,
shamt => s_shamt,
rout => s_rd,
error => s_error,
overflow => s_overflow,
zero => s_zero
);
-- Clock generation
tiktok: process
begin
clk <= '0';
wait for t_per/2;
clk <= '1';
wait for t_per/2;
end process;
main: process
begin
-- Settling
wait for t_per;
-- Begin Test
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
rst <= '0';
wait for 1.5*t_per;
-- Test instr_SLL - OK
s_ctrl <= instr_SLL;
s_rs1 <= (0 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 downto 59 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SLLI - OK
s_ctrl <= instr_SLLI;
s_rs1 <= (0 => '1', others => '0');
s_rs2 <= (others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00010";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
s_rs1 <= (63 downto 59 => '1', others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00010";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
-- Test instr_SRL - OK
s_ctrl <= instr_SRL;
s_rs1 <= (10 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 downto 59 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SRLI - OK
s_ctrl <= instr_SRLI;
s_rs1 <= (10 => '1', others => '0');
s_rs2 <= (others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00010";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
s_rs1 <= (63 downto 59 => '1', others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
-- Test instr_SRA - OK
s_ctrl <= instr_SRA;
s_rs1 <= (10 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 downto 59 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SRAI - OK
s_ctrl <= instr_SRAI;
s_rs1 <= (10 => '1', others => '0');
s_rs2 <= (others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00010";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
s_rs1 <= (63 downto 59 => '1', others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
-- Test instr_ADD - OK
s_ctrl <= instr_ADD;
s_rs1 <= (others => '0'); -- 0 + 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0'); -- 2 + 4
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (2 => '1', others => '0'); -- 4 + -2
s_rs2 <= (0 => '0', others => '1');
wait for t_per;
s_rs1 <= (1 downto 0 => '0', others => '1'); -- -4 + 2
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0'); -- 2 + 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 + -2
s_rs2 <= (0 => '0', others => '1');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1 + 1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- -1 + -1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 => '0', others => '1'); -- overflow positive
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (63 => '1', others => '0'); -- overflow negative
s_rs2 <= (1 downto 0 => '0', others => '1');
wait for t_per;
-- Test instr_ADDI - OK
s_ctrl <= instr_ADDI;
s_rs1 <= (others => '0'); -- 0 + 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0'); -- 2 + 4
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (2 => '1', others => '0'); -- 4 + -2
s_rs2 <= (0 => '0', others => '1');
wait for t_per;
s_rs1 <= (1 downto 0 => '0', others => '1'); -- -4 + 2
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0'); -- 2 + 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 + -2
s_rs2 <= (0 => '0', others => '1');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1 + 1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- -1 + -1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 => '0', others => '1'); -- overflow positive
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (63 => '1', 0 => '1', others => '0'); -- overflow negative
s_rs2 <= (1 downto 0 => '0', others => '1');
wait for t_per;
-- Test instr_SUB - OK
s_ctrl <= instr_SUB;
s_rs1 <= (others => '0'); -- 0 - 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0'); -- 2 - 4
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (2 => '1', others => '0'); -- 4 - -2
s_rs2 <= (0 => '0', others => '1');
wait for t_per;
s_rs1 <= (1 downto 0 => '0', others => '1'); -- -4 - 2
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0'); -- 2 - 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 - 2
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1 - 1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- -1 - -1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 => '0', others => '1'); -- overflow positive
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 => '1', 0 => '1', others => '0'); -- overflow negative
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
-- Test instr_LUI - OK
s_ctrl <= instr_LUI;
s_rs1 <= (others => '1');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (19 downto 0 => '1', others => '0');
s_rs2 <= (19 downto 0 => '1', others => '0');
wait for t_per;
wait for t_per;
-- Test instr_AUIPC - OK
s_ctrl <= instr_AUIPC;
s_rs1 <= (31 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (31 => '1', others => '0');
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (31 => '1', others => '0');
s_rs2 <= (60 => '1', others => '0');
wait for t_per;
s_rs1 <= (31 => '1', others => '0');
s_rs2 <= (40 downto 32 => '1', others => '0');
wait for t_per;
-- Test instr_XOR - OK
s_ctrl <= instr_XOR;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= "1010101010101010101010101010101010101010101010101010101010101010";
s_rs2 <= (others => '0');
wait for t_per;
-- Test instr_XORI - OK
s_ctrl <= instr_XORI;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= "1010101010101010101010101010101010101010101010101010101010101010";
s_rs2 <= (others => '0');
wait for t_per;
-- Test instr_OR - OK
s_ctrl <= instr_OR;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= "1010101010101010101010101010101010101010101010101010101010101010";
s_rs2 <= (others => '0');
wait for t_per;
-- Test instr_ORI - OK
s_ctrl <= instr_ORI;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= "1010101010101010101010101010101010101010101010101010101010101010";
s_rs2 <= (others => '0');
wait for t_per;
-- Test instr_AND - OK
s_ctrl <= instr_AND;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= "1010101010101010101010101010101010101010101010101010101010101010";
s_rs2 <= (others => '0');
wait for t_per;
-- Test instr_ANDI - OK
s_ctrl <= instr_ANDI;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= "1010101010101010101010101010101010101010101010101010101010101010";
s_rs2 <= (others => '0');
wait for t_per;
-- Test instr_SLT - OK
s_ctrl <= instr_SLT;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (1 => '0', others => '1');
wait for t_per;
s_rs1 <= (1 => '0', others => '1');
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SLTI - OK
s_ctrl <= instr_SLTI;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (1 => '0', others => '1');
wait for t_per;
s_rs1 <= (1 => '0', others => '1');
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SLTU - OK
s_ctrl <= instr_SLTU;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (1 => '0', others => '1');
wait for t_per;
s_rs1 <= (1 => '0', others => '1');
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SLTIU - OK
s_ctrl <= instr_SLTIU;
s_rs1 <= (others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0');
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '1');
s_rs2 <= (1 => '0', others => '1');
wait for t_per;
s_rs1 <= (1 => '0', others => '1');
s_rs2 <= (others => '1');
wait for t_per;
wait for t_per;
-- Test instr_SLLW - OK
s_ctrl <= instr_SLLW;
s_rs1 <= (0 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 downto 59 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SLLIW - OK
s_ctrl <= instr_SLLIW;
s_rs1 <= (0 => '1', others => '0');
s_rs2 <= (others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00010";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
s_rs1 <= (63 downto 59 => '1', others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00010";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
-- Test instr_SRLW - OK
s_ctrl <= instr_SRLW;
s_rs1 <= (10 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 downto 59 => '1', 30 downto 29 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SRLIW - OK
s_ctrl <= instr_SRLIW;
s_rs1 <= (10 => '1', others => '0');
s_rs2 <= (others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00010";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
s_rs1 <= (63 downto 59 => '1', 30 downto 29 => '1', others => '0');
s_shamt <= "11011";
wait for t_per;
s_shamt <= "11100";
wait for t_per;
s_shamt <= "11101";
wait for t_per;
s_shamt <= "11110";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
-- Test instr_SRAW - OK
s_ctrl <= instr_SRAW;
s_rs1 <= (10 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (63 downto 59 => '1', 30 downto 29 => '1', others => '0');
s_rs2 <= (others => '0');
wait for t_per;
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs2 <= (1 downto 0 => '1', others => '0');
wait for t_per;
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_SRAIW - OK
s_ctrl <= instr_SRAIW;
s_rs1 <= (10 => '1', others => '0');
s_rs2 <= (others => '0');
s_shamt <= "00000";
wait for t_per;
s_shamt <= "00001";
wait for t_per;
s_shamt <= "00010";
wait for t_per;
s_shamt <= "00011";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
s_rs1 <= (63 downto 59 => '1', 30 downto 29 => '1', others => '0');
s_shamt <= "11100";
wait for t_per;
s_shamt <= "11101";
wait for t_per;
s_shamt <= "11110";
wait for t_per;
s_shamt <= "11111";
wait for t_per;
-- Test instr_ADDW - OK
s_ctrl <= instr_ADDW;
s_rs1 <= (others => '0'); -- 0+0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 + -8
s_rs2 <= (2 downto 0 => '0', others => '1');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 + 8
s_rs2 <= (3 => '1', others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 + 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 + 4
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 + -8
s_rs2 <= (2 downto 0 => '0', others => '1');
wait for t_per;
s_rs1 <= (63 downto 31 => '1', others => '1'); -- max32 + 0 ignore upper word test
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
-- Test instr_ADDIW - OK
s_ctrl <= instr_ADDIW;
s_rs1 <= (others => '0'); -- 0+0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 + -8
s_rs2 <= (2 downto 0 => '0', others => '1');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 + 8
s_rs2 <= (3 => '1', others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 + 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 + 4
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 + -8
s_rs2 <= (2 downto 0 => '0', others => '1');
wait for t_per;
s_rs1 <= (63 downto 31 => '0', others => '1'); -- max32 + 0 ignore upper word test
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
-- Test instr_SUBW - OK
s_ctrl <= instr_SUBW;
s_rs1 <= (others => '0'); -- 0-0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 - -8
s_rs2 <= (2 downto 0 => '0', others => '1');
wait for t_per;
s_rs1 <= (others => '0'); -- 0 + -8
s_rs2 <= (3 => '1', others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 - 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 - 4
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (29 => '1', others => '0'); -- 268435456 - -8
s_rs2 <= (2 downto 0 => '0', others => '1');
wait for t_per;
s_rs1 <= (33 => '1', others => '0'); -- ignore upper word test
s_rs2 <= (others => '1');
wait for t_per;
-- Test instr_MUL - OK
s_ctrl <= instr_MUL;
s_rs1 <= (others => '0'); -- 0*0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0*1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0*-1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1 * 1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1 * -1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '1'); -- -1 * 1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- -1 * -1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (31 downto 0 => '1', others => '0'); -- result 1FFFFFFFF
s_rs1 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= (63 => '0', others => '1'); -- overflow positive "ignore arithmetic overflow"
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (63 => '1', others => '0'); -- overflow negative "ignore arithmetic overflow"
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
-- Test instr_MULH (upper half of result written to rd) - OK
s_ctrl <= instr_MULH;
s_rs1 <= (30 => '1', others => '0'); -- result shoud be 0
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (30 downto 0 => '1', others => '0'); -- result should be 1
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (63 downto 31 => '1', others => '0'); -- result should be x0FFFFFFFF
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (63 downto 31 => '1', others => '0'); -- result should be 1
s_rs2 <= (0 => '0', others => '1');
wait for t_per;
-- Test instr_MULHU - OK
s_ctrl <= instr_MULHU;
s_rs1 <= (30 downto 0 => '1', others => '0'); -- result shoud be 0
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (31 => '1', others => '0'); -- result should be 1
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (31 downto 0 => '1', others => '0'); -- result should be 254
s_rs2 <= (7 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= (31 downto 0 => '1', others => '0'); -- result shoud be 4294967294
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= (31 downto 0 => '1', others => '0'); -- result shoud be 0
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
wait for t_per;
-- Test instr_MULHSU - Misses the first computation, correct thereafter. May need to follow this with a NOP or find a different soln.
s_ctrl <= instr_MULHSU;
s_rs1 <= (30 downto 0 => '1', others => '0'); -- result shoud be 0
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (30 downto 0 => '1', others => '0'); -- result should be 1
s_rs2 <= (2 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- result should be 0x0ffffffff
s_rs2 <= (31 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- result shoud be 0x0fffffff
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
-- Test instr_DIV - OK
s_ctrl <= instr_DIV;
s_rs1 <= (others => '0'); -- 0/0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0/-1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- -1/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1/-1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (47 downto 0 => '1', others => '0'); -- FFFFFFFFFFFF/7FFFFFFF = x20000
s_rs2 <= (30 downto 0 => '1', others => '0');
wait for t_per;
-- Test instr_DIVU - OK
s_ctrl <= instr_DIVU;
s_rs1 <= (others => '0'); -- 0/0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0/max
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- max/max
s_rs2 <= (others => '1');
wait for t_per;
wait for t_per;
s_rs1 <= (47 downto 0 => '1', others => '0'); -- FFFFFFFFFFFF/FFFFFFFF = x10000
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= (47 downto 0 => '1', others => '0'); -- FFFFFFFFFFFF/FFFFFFFF = x0
s_rs2 <= (48 downto 0 => '1', others => '0');
wait for t_per;
-- Test instr_REM - OK
s_ctrl <= instr_REM;
s_rs1 <= (others => '0'); -- 0/0 r 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1/0 r 1
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- -1/0 r -1
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0'); -- 2/2 r 0
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (5 downto 0 => '1', others => '0'); -- 63 / 2 r 1
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (5 downto 1 => '0', others => '1'); -- -63/2 r -1
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
-- Test instr_REMU - OK
s_ctrl <= instr_REMU;
s_rs1 <= (others => '0'); -- 0/0 r 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1/0 r 1
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- max/0 r max
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 => '1', others => '0'); -- 1/1 r 0
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (5 downto 0 => '1', others => '0'); -- 63 / 2 r 1
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
-- Test instr_MULW -- truncate result to 32 bits, sign extended
s_ctrl <= instr_MULW;
s_rs1 <= (others => '0'); -- 0*0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0*1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0*-1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1 * 1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1 * -1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '1'); -- -1 * 1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- -1 * -1
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (30 downto 0 => '1', others => '0'); -- result 1
s_rs1 <= (30 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= (31 downto 0 => '1', others => '0'); -- result x80000001
s_rs2 <= (30 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- result xFFFFFFC1
s_rs2 <= (5 downto 0 => '1', others => '0');
wait for t_per;
-- Test instr_DIVW - OK
s_ctrl <= instr_DIVW;
s_rs1 <= (others => '0'); -- 0/0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0/max
s_rs2 <= (63 downto 31=> '0', others => '1');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (63 downto 31=> '0', others => '1'); -- max/max
s_rs2 <= (63 downto 31=> '0', others => '1');
wait for t_per;
s_rs1 <= (62 downto 0 => '1', others => '0'); -- 7FFF FFFF FFFFFFFF/FFFFFFFF = xffffffff80000000
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= (31 downto 0 => '0', 63 => '0', others => '1'); -- 7FFFFFFFF0000000/FFFFFFFF = x0
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
-- Test instr_DIVUW - OK
s_ctrl <= instr_DIVUW;
s_rs1 <= (others => '0'); -- 0/0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '0'); -- 0/max
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (0 => '1', others => '0'); -- 1/1
s_rs2 <= (0 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- max/max
s_rs2 <= (others => '1');
wait for t_per;
s_rs1 <= (others => '1'); -- FFFFFFFF FFFFFFFF/FFFFFFFF = all 1's
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
s_rs1 <= (63 downto 32 => '1', others => '0'); -- FFFFFFFFF0000000/FFFFFFFF = x0
s_rs2 <= (31 downto 0 => '1', others => '0');
wait for t_per;
-- Test instr_REMW - OK
s_ctrl <= instr_REMW;
s_rs1 <= (others => '0'); -- expect 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 downto 0 => '1', others => '0'); -- expect 1
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- expect -1
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (2 => '1', others => '0'); -- expect 0
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (6 => '1', others => '0'); -- expect 4
s_rs2 <= (3 => '1', 1 => '1', others => '0');
wait for t_per;
s_rs1 <= (5 downto 0 => '0', others => '1'); -- expect -4
s_rs2 <= ( 3 => '1', 1 => '1', others => '0');
wait for t_per;
-- Test instr_REMUW - OK
s_ctrl <= instr_REMUW;
s_rs1 <= (others => '0'); -- expect 0
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (1 downto 0 => '1', others => '0'); -- expect 1
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (others => '1'); -- expect xffffffff
s_rs2 <= (others => '0');
wait for t_per;
s_rs1 <= (2 => '1', others => '0'); -- expect the Spanish inquisition
s_rs2 <= (1 => '1', others => '0');
wait for t_per;
s_rs1 <= (6 => '1', others => '0'); -- expect 4
s_rs2 <= (3 => '1', 1 => '1', others => '0');
wait for t_per;
s_rs1 <= (5 downto 0 => '0', others => '1'); -- expect 2
s_rs2 <= ( 3 => '1', 1 => '1', others => '0');
wait for t_per;
wait;
end process;
end Behavioral;
| mit | 31f3be8c92b3d1022bb2119376e871df | 0.424341 | 2.863024 | false | false | false | false |
SLongofono/Senior_Design_Capstone | Demo/ALU.vhd | 1 | 19,776 | ----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 12/04/2017 08:30:06 AM
-- Module Name: ALU - Behavioral
-- Description:
--
-- Additional Comments: Omitted MULSHU because it is a special snowflake.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.NUMERIC_BIT.ALL;
library config;
use work.config.all;
entity ALU is
Port(
clk: in std_logic; -- System clock
rst: in std_logic; -- Reset
halt: in std_logic; -- Do nothing
ctrl: in instr_t; -- Operation
rs1: in doubleword; -- Source 1
rs2: in doubleword; -- Source 2
shamt: in std_logic_vector(4 downto 0); -- shift amount
rout: out doubleword; -- Output Result
error: out std_logic; -- signal exception
overflow: out std_logic; -- signal overflow
zero: out std_logic -- signal zero result
);
end ALU;
architecture Behavioral of ALU is
-- component declaration
component Shifter is
port (
clk : in std_logic;
rst : in std_logic;
ctrl: in instr_t;
i_a1 : in std_logic_vector(63 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
result: out doubleword
);
end component;
-- Signals and constants
constant all_bits_set : doubleword := (others => '1');
signal result: doubleword;
signal feedback: std_logic_vector(2 downto 0); -- (Error, Overflow, Zero)
signal mul_reg: std_logic_vector(127 downto 0);
signal mul_reg_plus: std_logic_vector(129 downto 0); -- Special case for MULSHU
signal add_word: doubleword;
-- Shift unit signals
signal s_shift_amt: std_logic_vector(5 downto 0);
signal s_shift_arg: doubleword;
signal s_shift_result: doubleword;
begin
-- Instantiation
myShifter : Shifter
port map(
clk => clk,
rst => rst,
ctrl => ctrl,
i_a1 => s_shift_arg, -- Operand 1
i_a2 => s_shift_amt, -- Shift bits number
result => s_shift_result
);
process(clk, rst)
variable shift_limit: natural;
begin
-- shift_arg <= to_integer(unsigned(shamt));
feedback <= "000";
if(rising_edge(clk)) then
if('0' = halt) then
if('1' = rst) then
result <= (others => '0');
else
case ctrl is
-- Treat as 32-bit operands
when instr_SLL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
-- shift_limit := to_integer(unsigned(shamt));
-- result <= zero_word & rs1(31 - shift_limit downto 0) & zero_word(shift_limit-1 downto 0);
when instr_SRL =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRA =>
s_shift_amt <= rs2(5 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAI =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADD =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
when instr_ADDI =>
result <= std_logic_vector(signed(rs1) + signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_SUB =>
result <= std_logic_vector(signed(rs1) - signed(rs2));
--if((result < rs1) or (result < rs2)) then
-- case overflow
-- feedback(1) <= '1';
--end if;
when instr_LUI =>
-- In brief: rd = sign_extend(rsimm20 << 12)
-- Load low 20 of immediate value shifted left 12
-- sign extend to fit 64 bit system
result(31 downto 0) <= rs2(19 downto 0) & "000000000000";
result(63 downto 32) <= (others => rs2(19));
when instr_AUIPC =>
-- TODO verify that PC can easily be passed in here as arg 1
-- In brief: rd = PC + (rs << 12)
-- Load 20 MSBs of low word with low 20 of immediate value
-- sign extend (rs << 12) to fit 64 bit
-- NOTE: Here, we use a "qualified expression" to hint at how the compiler should resolve
-- the ambiguity. We give a hint as to which overloaded function should be used,
-- in this case, the one that takes in a bit vector constant and a std_logic_vector
-- and returns a std_logic_vector.
--auipc_ext(31 downto 0) := std_logic_vector'(rs2(19 downto 0) & "000000000000");
result <= std_logic_vector(signed(rs1) + signed(std_logic_vector'(rs2(19 downto 0) & "000000000000")));
when instr_XOR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_XORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 xor rs2;
when instr_OR =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_ORI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 or rs2;
when instr_AND =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_ANDI =>
-- Assumption: immediate value in rs2 is already sign-extended
result <= rs1 and rs2;
when instr_SLT =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTI =>
if(signed(rs1) < signed(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLTIU =>
-- Assumption: immediate value in rs2 is already sign-extended
if(unsigned(rs1) < unsigned(rs2)) then
result <= (0 => '1', others => '0');
else
result <= (others => '0');
end if;
when instr_SLLW =>
-- Since these are word operations instead of double
-- word operations, only use the bottom 5 bits instead of 6
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SLLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRLIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAW =>
s_shift_amt <= '0' & rs2(4 downto 0);
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_SRAIW =>
s_shift_amt <= '0' & shamt;
s_shift_arg <= rs1;
result <= s_shift_result;
when instr_ADDW =>
add_word <= std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_ADDIW =>
add_word <= std_logic_vector(signed(rs1) + signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_SUBW =>
add_word <= std_logic_vector(signed(rs1) - signed(rs2));
result(63 downto 32) <= (others => add_word(31));
result(31 downto 0) <= add_word(31 downto 0);
when instr_MUL =>
mul_reg <= std_logic_vector(signed(rs1) * signed(rs2));
result <= mul_reg(63 downto 0);
when instr_MULH =>
mul_reg <= std_logic_vector(signed(rs1) * signed(rs2));
result <= zero_word & mul_reg(63 downto 32);
when instr_MULHU =>
mul_reg <= std_logic_vector(unsigned(rs1) * unsigned(rs2));
result <= zero_word & mul_reg(63 downto 32);
--when instr_MULHSU =>
-- TODO - verify that this multiplier does not introduce problems on the schematic/layout
--mul_reg_plus <= std_logic_vector(signed(rs1(31) & rs1) * signed('0' & rs2));
--result <= zero_word & mul_reg_plus(63 downto 32);
--
-- Special Values for Divide by Zero and Division Overflow (per 2.2 spec)
-- Situation || Special Return Values for Each Instruction
-- <condition> <Dividend> <Divisor> || <DIVU> <REMU> <DIV> <REM>
-- Divide by 0 x 0 || All bits set x -1 x
-- Overflow -(2^64 -1) -1 || N/A N/A -(2^(64-1)) 0
--
when instr_DIV =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg <= all_bits_set & all_bits_set;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set only MSB
mul_reg <= (63 => '1', others => '0');
else
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1) / signed(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_DIVU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to all ones
mul_reg <= all_bits_set & all_bits_set;
else
mul_reg <= zero_word & zero_word & std_logic_vector(unsigned(rs1) / unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_REM =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
elsif( (all_bits_set = rs1) and (-1 = to_integer(signed(rs2))) ) then
-- case division overflow, set result to 0
mul_reg <= (others => '0');
else
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1) rem signed(rs2));
end if;
result(31 downto 0) <= mul_reg(31 downto 0);
result(63 downto 32) <= (others => mul_reg(31));
when instr_REMU =>
if(zero_word = rs2(31 downto 0) and zero_word = rs2(63 downto 32)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
else
mul_reg <= zero_word & zero_word & std_logic_vector(unsigned(rs1) rem unsigned(rs2));
end if;
result <= mul_reg(63 downto 0);
when instr_MULW =>
mul_reg <= zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) * signed(rs2(31 downto 0)));
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to -1 (all ones)
mul_reg <= all_bits_set & all_bits_set;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set only MSB
mul_reg <= (31 => '1', others => '0');
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) / signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_DIVUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to all ones
mul_reg <= all_bits_set & all_bits_set;
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) / unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
elsif( (all_bits_set(31 downto 0) = rs1(31 downto 0)) and (-1 = to_integer(signed(rs2(31 downto 0)))) ) then
-- case division overflow, set result to 0
mul_reg <= (others => '0');
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(signed(rs1(31 downto 0)) rem signed(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when instr_REMUW =>
if(zero_word = rs2(31 downto 0)) then
-- case divide by zero, set result to dividend
mul_reg <= zero_word & zero_word & rs1;
else
mul_reg <= zero_word & zero_word & zero_word & std_logic_vector(unsigned(rs1(31 downto 0)) rem unsigned(rs2(31 downto 0)));
end if;
result(63 downto 32) <= (others => mul_reg(31));
result(31 downto 0) <= mul_reg(31 downto 0);
when others =>
-- Error condition: unknown control code
feedback(0) <= '1';
result <= (others => '0');
end case;
end if; -- Reset
end if; -- Halt
end if; -- Clock
end process;
error <= feedback(0); -- TODO feedback single bit for error conditions.
overflow <= feedback(1);-- TODO check here, remove from logic above
zero <= '1' when (0 = unsigned(result)) else '0';
rout <= result;
end Behavioral; | mit | b2e17ce24b17acb8dfe545b93a6c3330 | 0.392395 | 4.945236 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_11_19/i2c_xcvr.vhd | 1 | 5,965 | ----------------------------------------------------------------------------------
--
-- I2C Transceiver
--
-- Used to send SSM2603 initialization data via I2C
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_xcvr is
port (
-- with 1 MHz clock SSM2603 reg 9 delay step is 65.535 ms:
clk1M : in std_logic;
-- tie to system reset
res0 : in std_logic;
-- initialization line number
init_line : out unsigned(7 downto 0);
-- initialization data xRRRRRRRxxxxxxxDDDDDDDDD
init_data : in std_logic_vector(19 downto 0);
-- error status
error : out std_logic;
-- tie directly to ac_scl and ac_sda accordingly:
scl : inout std_logic;
sda : inout std_logic
);
end i2c_xcvr;
architecture i2c_init_guts of i2c_xcvr is
subtype byte is std_logic_vector(7 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype slv20 is std_logic_vector(19 downto 0);
subtype slv27 is std_logic_vector(26 downto 0);
constant dac_addr_w : byte := "0011010" & "0";
constant dac_addr_r : byte := "0011010" & "1";
signal dac_buffer : slv27 := x"00" & '1' & x"00" & '1' & x"00" & '1'; --padded for ACKs
signal dac_x_offs : ubyte := x"00";
signal dac_init_line : ubyte := x"00";
signal dac_init_wait : u16 := x"0000";
signal dac_ok : std_logic := '1';
type dacstg_t is (
dac_reset,
dac_i2c_start,
dac_loadbuf,
dac_i2c_send0_c0,
dac_i2c_send1_c0dx,
dac_i2c_send2_c1,
dac_i2c_send3_next,
dac_i2c_stop,
dac_i2c_stop_c1d0,
dac_i2c_stop_c1d1,
dac_idle
);
signal dac_init_stg : dacstg_t := dac_reset;
signal dac_scl_o : std_logic := '1';
signal dac_sda_o : std_logic := '1';
signal dac_scl_i : std_logic;
signal dac_sda_i : std_logic;
begin
dac_scl_i <= scl; -- I2C clock input
dac_sda_i <= sda; -- I2C data input (used to sense ACK by testing for dac_sda_i='0' when dac_sda_o='1')
with dac_scl_o select scl <=
'0' when '0', -- pull down to send '0'
'Z' when others; -- bus is pulled up so '1' is sent by breaking the connection (high-Z)
with dac_sda_o select sda <=
'0' when '0', -- pull down to send '0'
'Z' when others; -- bus is pulled up so '1' is sent by breaking the connection (high-Z)
init_line <= dac_init_line;
error <= not dac_ok;
i2c: process(clk1M,res0,dac_buffer,dac_x_offs,
dac_init_line,dac_init_wait,dac_init_stg) is
variable cur_data : slv20;
variable nack : std_logic;
begin
cur_data := init_data;
nack := dac_sda_i;
if (res0 = '0') then
dac_init_stg <= dac_reset;
elsif (rising_edge(clk1M)) then
case dac_init_stg is
when dac_reset =>
dac_ok <= '1';
dac_scl_o <= '1';
dac_sda_o <= '1';
dac_init_line <= x"00";
dac_init_wait <= x"0000";
dac_init_stg <= dac_loadbuf;
when dac_loadbuf =>
dac_x_offs <= x"1a"; -- position in sequence
dac_buffer <= dac_addr_w & '1' & -- buffer the sequence (ACK bits are constant '1')
cur_data(18 downto 12) & cur_data(8) & '1' &
cur_data(7 downto 0) & '1';
if (cur_data(19 downto 12)=x"09" and dac_init_wait<x"ffff") then
-- since the VMID delay is precondition to setting reg 09
-- the delay is performed when the current initialization
-- data indicate setting of reg 09
dac_init_wait <= dac_init_wait + 1;
elsif (cur_data = x"fffff") then
-- init data of 0xfffff is end sentinel
dac_init_stg <= dac_idle;
else
dac_init_stg <= dac_i2c_start;
end if;
when dac_i2c_start =>
dac_sda_o <= '0';
dac_init_stg <= dac_i2c_send0_c0;
when dac_i2c_send0_c0 =>
dac_scl_o <= '0';
dac_init_stg <= dac_i2c_send1_c0dx;
when dac_i2c_send1_c0dx =>
dac_sda_o <= dac_buffer(to_integer(dac_x_offs));
dac_init_stg <= dac_i2c_send2_c1;
when dac_i2c_send2_c1 =>
dac_scl_o <= '1';
dac_init_stg <= dac_i2c_send3_next;
when dac_i2c_send3_next =>
if ((dac_x_offs=x"00" or dac_x_offs=x"09" or dac_x_offs=x"12") and nack='1') then
dac_ok <= '0';
dac_init_stg <= dac_i2c_stop;
elsif (dac_x_offs = x"00") then
dac_init_stg <= dac_i2c_stop;
else
dac_x_offs <= dac_x_offs - 1;
dac_init_stg <= dac_i2c_send0_c0;
end if;
when dac_i2c_stop =>
dac_scl_o <= '0';
dac_sda_o <= '0';
dac_init_stg <= dac_i2c_stop_c1d0;
when dac_i2c_stop_c1d0 =>
dac_scl_o <= '1';
dac_init_stg <= dac_i2c_stop_c1d1;
when dac_i2c_stop_c1d1 =>
dac_sda_o <= '1';
if (dac_ok = '0') then
dac_init_stg <= dac_idle;
else
dac_init_line <= dac_init_line + 1;
dac_init_stg <= dac_loadbuf;
end if;
when others =>
null;
end case;
end if;
end process i2c;
end i2c_init_guts;
| gpl-3.0 | f99a2efe2a5a0dd38acb25676bc8a7e0 | 0.472925 | 3.319421 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_11_19/chiptest.vhd | 1 | 33,563 | ----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--
-- C64 ROM includes (NOT INCLUDED)
-- See python scripts for converting ROM images to VHDL files.
-- Import the generated sources into a library called "c64roms"
--
library c64roms;
use c64roms.p_char_rom.all; -- for char_rom(addr[11:0]) return byte[7:0]
use c64roms.p_basic_rom.all; -- for basic_rom(addr[12:0]) return byte[7:0]
use c64roms.p_kernal_rom.all; -- for kernal_rom(addr[12:0]) return byte[7:0]
entity chip_test is
port (
clk_125 : in std_logic;
-- audio configure
ac_scl : inout std_logic;
ac_sda : inout std_logic;
-- audio signal
ac_muten : out std_logic;
ac_mclk : out std_logic;
ac_bclk : out std_logic;
ac_pbdat : out std_logic;
ac_pblrc : out std_logic;
ac_recdat : in std_logic;
ac_reclrc : in std_logic;
-- report error in configuring audio
led : out std_logic_vector(3 downto 0);
-- to test waveforms
sw : in std_logic_vector(3 downto 0);
-- for freq/wvfm ramping tests
btn : in std_logic_vector(3 downto 0);
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end chip_test;
architecture testing of chip_test is
component clk_wiz_0
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk160 : out std_logic;
clk20ph1 : out std_logic;
clk20ph2 : out std_logic;
clk20ph3 : out std_logic;
clk20ph4 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
component clk_wiz_1
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk12 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
signal clk12 : std_logic;
signal clk160 : std_logic;
signal clk_lk1 : std_logic;
signal clk_lk2 : std_logic;
signal clk20p000 : std_logic;
signal clk20p010 : std_logic;
signal clk20p100 : std_logic;
signal clk20p110 : std_logic;
signal clk20_ph1 : std_logic;
signal clk20_ph2 : std_logic;
component blk_ram_64k
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
component blk_cram
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv5 is std_logic_vector(4 downto 0);
subtype u5 is unsigned(4 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype slv7 is std_logic_vector(6 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype slv10 is std_logic_vector(9 downto 0);
subtype slv14 is std_logic_vector(13 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype s16 is signed(15 downto 0);
subtype slv20 is std_logic_vector(19 downto 0);
subtype slv24 is std_logic_vector(23 downto 0);
subtype slv27 is std_logic_vector(26 downto 0); -- I2C SSM2603 send with ACK pads
signal res0 : std_logic;
signal res1 : std_logic;
signal cpu_r1w0 : std_logic:='1';
signal cpu_r0w1 : std_logic;
component sid6581 is
port (
res0 : in std_logic;
ph2 : in std_logic;
rga : in std_logic_vector(4 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
s16audio : out signed(15 downto 0)
);
end component;
signal bclk_cnt : pair;
alias bclk_ref : std_logic is bclk_cnt(0);--1
signal audio_frame : u5;
signal hold_sam : s16;
signal hold2 : s16;
function buf_max(frm : u5) return boolean is
begin
case frm is
when "11111" => return true;
when others => return false;
end case;
end buf_max;
function adv_frame(frm: u5) return u5 is
begin
case frm is
when "00000" => return "00001";
when "00001" => return "00010";
when "00010" => return "00011";
when "00011" => return "00100";
when "00100" => return "00101";
when "00101" => return "00110";
when "00110" => return "00111";
when "00111" => return "01000";
when "01000" => return "01001";
when "01001" => return "01010";
when "01010" => return "01011";
when "01011" => return "01100";
when "01100" => return "01101";
when "01101" => return "01110";
when "01110" => return "01111";
when "01111" => return "10000";
when "10000" => return "10001";
when "10001" => return "10010";
when "10010" => return "10011";
when "10011" => return "10100";
when "10100" => return "10101";
when "10101" => return "10110";
when "10110" => return "10111";
when "10111" => return "11000";
when "11000" => return "11001";
when "11001" => return "11010";
when "11010" => return "11011";
when "11011" => return "11100";
when "11100" => return "11101";
when "11101" => return "11110";
when "11110" => return "11111";
when "11111" => return "00000";
when others => return "00000";
end case;
end adv_frame;
signal sid1_rga : slv5;
signal sid1_dw : byte;
signal sid1_dr : byte;
signal sid1_out : s16;
signal sid1_r1w0 : std_logic;
component vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end component;
signal bankctl : slv5 := "11111";
alias exrom : std_logic is bankctl(4);
alias game : std_logic is bankctl(3);
alias charen : std_logic is bankctl(2);
alias hiram : std_logic is bankctl(1);
alias loram : std_logic is bankctl(0);
signal abus : word;
signal rama : word;
signal cpudo : byte;
signal cpudi : byte;
signal r1w0 : std_logic;
signal ram_clk : std_logic;
signal ramclk_init : std_logic := '0';
signal ramclk_cpu : std_logic := '0';
signal ramclk_vic : std_logic := '0';
signal ram_r1w0 : std_logic := '1';
signal ram_r0w1 : std_logic;
signal cram_r1w0 : std_logic := '1';
signal cram_r0w1 : std_logic;
signal ramdr : byte;
signal ramdw : byte;
signal ramen : std_logic := '1';
signal cramdr : nybble;
signal cramdw : nybble;
signal cramen : std_logic := '1';
signal vbank : pair := "00";
signal vic_rga : slv6;
signal vic_regw : byte;
signal vic_regr : byte;
signal vic_r1w0 : std_logic := '1';
signal cpu_ph1 : std_logic;
signal cpu_ph2 : std_logic;
signal vmem_clk : std_logic;
signal vic_ca : slv10;
signal vic_cd : nybble;
signal vic_wcd : nybble;
signal vic_va : slv14;
signal vic_vd : byte;
signal vic_wvd : byte;
signal cpu_on : std_logic;
signal vic_on : std_logic;
signal cpu_ph4x : std_logic;
function catoi(src: slv10) return integer is
begin
return to_integer(unsigned(src));
end catoi;
function vatoi(src: word) return integer is
begin
return to_integer(unsigned(src));
end vatoi;
function xtov6(src: byte) return slv6 is
begin
return src(5 downto 0);
end xtov6;
function xtov5(src: byte) return slv5 is
begin
return src(4 downto 0);
end xtov5;
type mbank_t is (
mbk_ram,
mbk_cram,
mbk_lorom,
mbk_hirom,
mbk_xio2,
mbk_xio1,
mbk_cia2,
mbk_cia1,
mbk_cgrom,
mbk_sid,
mbk_vic
);
function init_bank(addr:u16) return mbank_t is
begin
if (addr(15 downto 10) = "110110") then
return mbk_cram;
else
return mbk_ram;
end if;
end init_bank;
function cpu_bank(addr: u16; bsel: slv5) return mbank_t is
variable b3 : slv3;
variable bb0 : std_logic;
variable ce : std_logic;
variable n3 : nybble;
begin
b3 := bsel(2 downto 0);
bb0 := bsel(1) nor bsel(0);
ce := bsel(2);
n3 := nybble(addr(11 downto 8));
if (addr >= x"e000") then
if (bsel(1)='1') then
return mbk_hirom;
else
return mbk_ram;
end if;
elsif (addr >= x"d000" and addr < x"e000") then
if (bb0 = '1') then
return mbk_ram;
else
if (ce = '0') then
return mbk_cgrom;
else
case n3 is
when x"f" =>
return mbk_xio2;
when x"e" =>
return mbk_xio1;
when x"d" =>
return mbk_cia2;
when x"c" =>
return mbk_cia1;
when x"b" =>
return mbk_cram;
when x"a" =>
return mbk_cram;
when x"9" =>
return mbk_cram;
when x"8" =>
return mbk_cram;
when x"7" =>
return mbk_sid;
when x"6" =>
return mbk_sid;
when x"5" =>
return mbk_sid;
when x"4" =>
return mbk_sid;
when x"3" =>
return mbk_vic;
when x"2" =>
return mbk_vic;
when x"1" =>
return mbk_vic;
when x"0" =>
return mbk_vic;
when others =>
return mbk_ram;
end case;
end if;
end if;
elsif (addr >= x"a000" and addr < x"c000") then
if ((bsel(1) and bsel(0)) = '1') then
return mbk_lorom;
else
return mbk_ram;
end if;
else
return mbk_ram;
end if;
end cpu_bank;
function bank_is_writethru(addr:word; bsel:slv5) return std_logic is
begin
case cpu_bank(u16(addr),bsel) is
when mbk_ram => return '1';
when mbk_cram => return '1';
when mbk_lorom => return '1';
when mbk_hirom => return '1';
when others => return '0';
end case;
end bank_is_writethru;
type init_t is (
initram_wait, initram_xfer, initram_idle);
signal init_stg : init_t := initram_wait;
constant init_wait_to : u16 := x"0014";
signal init_counter : u16 := x"0000";
signal init_addr : word;
signal init_data : byte;
signal init_r1w0 : std_logic := '1';
signal init_r0w1 : std_logic;
function ram_init(lin: u16) return slv24 is
begin
case lin is
when x"0000" => return x"0400" & x"08";
when x"0001" => return x"0401" & x"05";
when x"0002" => return x"0402" & x"0c";
when x"0003" => return x"0403" & x"0c";
when x"0004" => return x"0404" & x"0f";
when x"0005" => return x"0405" & x"2c";
when x"0006" => return x"0406" & x"20";
when x"0007" => return x"0407" & x"17";
when x"0008" => return x"0408" & x"0f";
when x"0009" => return x"0409" & x"12";
when x"000a" => return x"040a" & x"0c";
when x"000b" => return x"040b" & x"04";
when x"000c" => return x"040c" & x"21";
when x"000d" => return x"040d" & x"20";
when x"000e" => return x"05f2" & x"3a";
when x"000f" => return x"05f3" & x"3a";
when x"0010" => return x"05f4" & x"3a";
when x"0011" => return x"05f5" & x"3a";
when x"0012" => return x"07de" & x"30";
when x"0013" => return x"07df" & x"31";
when x"0014" => return x"07e0" & x"32";
when x"0015" => return x"07e1" & x"33";
when x"0016" => return x"07e2" & x"34";
when x"0017" => return x"07e3" & x"35";
when x"0018" => return x"07e4" & x"36";
when x"0019" => return x"07e5" & x"37";
when x"001a" => return x"07e6" & x"38";
when x"001b" => return x"07e7" & x"39";
when x"001c" => return x"d800" & x"01";
when x"001d" => return x"d801" & x"02";
when x"001e" => return x"d802" & x"03";
when x"001f" => return x"d803" & x"04";
when x"0020" => return x"d804" & x"05";
when x"0021" => return x"d805" & x"07";
when x"0022" => return x"d806" & x"0e";
when x"0023" => return x"d807" & x"08";
when x"0024" => return x"d808" & x"09";
when x"0025" => return x"d809" & x"0a";
when x"0026" => return x"d80a" & x"0b";
when x"0027" => return x"d80b" & x"0c";
when x"0028" => return x"d80c" & x"0d";
when x"0029" => return x"d80d" & x"0e";
when x"002a" => return x"d9f2" & x"01";
when x"002b" => return x"d9f3" & x"01";
when x"002c" => return x"d9f4" & x"01";
when x"002d" => return x"d9f5" & x"01";
when x"002e" => return x"dbde" & x"05";
when x"002f" => return x"dbdf" & x"07";
when x"0030" => return x"dbe0" & x"0d";
when x"0031" => return x"dbe1" & x"09";
when x"0032" => return x"dbe2" & x"08";
when x"0033" => return x"dbe3" & x"0a";
when x"0034" => return x"dbe4" & x"0b";
when x"0035" => return x"dbe5" & x"0c";
when x"0036" => return x"dbe6" & x"0f";
when x"0037" => return x"dbe7" & x"0e";
when others => return x"0000" & x"00"; -- 0 (and 1) inaccessible on C64
end case;
end ram_init;
constant ram_init_count : u16 := x"0038";
-- for initial settings for vic/sid
signal c_cycle : ubyte := x"00";
--
-- For setting the SSM2603 via I2C
--
function dac_init(lin : ubyte) return slv20 is
begin
case lin is
when x"00" => return x"06" & x"010";
when x"01" => return x"02" & x"075";
when x"02" => return x"03" & x"075";
when x"03" => return x"04" & x"010";
when x"04" => return x"05" & x"000";
when x"05" => return x"07" & x"001";
when x"06" => return x"09" & x"001";
when x"07" => return x"06" & x"000";
when others => return x"ff" & x"fff";
end case;
end dac_init;
component i2c_xcvr port
(
-- with 1 MHz clock SSM2603 reg 9 delay step is 65.535 ms:
clk1M : in std_logic;
-- tie to system reset
res0 : in std_logic;
-- initialization line number
init_line : out unsigned(7 downto 0);
-- initialization data xRRRRRRRxxxxxxxDDDDDDDDD
init_data : in std_logic_vector(19 downto 0);
-- error status
error : out std_logic;
-- tie directly to ac_scl and ac_sda accordingly:
scl : inout std_logic;
sda : inout std_logic
);
end component;
signal ssm_init_line : ubyte;
signal ssm_init_data : slv20;
signal ssm_error : std_logic;
-- 3-bit counter for dividing 160 MHz into 8-phase 20 MHz clocks
signal clk20_ph : slv3;
function c20_next(src: slv3) return slv3 is
begin
case src is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end c20_next;
function vbk_cgrom(bk: pair; adr: slv14) return std_logic is
variable vsel : slv3;
begin
vsel := bk(0) & adr(13 downto 12);
case vsel is
when "001" => return '1';
when others => return '0';
end case;
end vbk_cgrom;
subtype u12 is unsigned(11 downto 0);
signal reset_wait : u12 := x"000";
constant reset_delay : u12 := x"0fb"; -- number of 125 MHz clocks in 2000 ns
signal cgrom_data : byte;
signal lorom_data : byte;
signal hirom_data : byte;
--
-- Architectural implementation
--
begin
--
-- Coldstart reset for 2000 ns
--
initial_reset: process(clk_125, reset_wait) is -- counts up to 2000 ns
variable not_yet : boolean;
begin
not_yet := (reset_wait < reset_delay);
if rising_edge(clk_125) then
if not_yet then
reset_wait <= reset_wait + 1;
end if;
end if;
if not_yet then -- drive reset accordingly
res0 <= '0';
else
res0 <= '1';
end if;
end process initial_reset;
pixclock: clk_wiz_0 port map (
-- Clock out ports
clk160 => clk160,
clk20ph1 => clk20p010,
clk20ph2 => clk20p100,
clk20ph3 => clk20p110,
clk20ph4 => clk20p000,
-- Status and control signals
reset => res1,
locked => clk_lk1,
-- Clock in ports
clk_in1 => clk_125
);
clk20gen: process(clk160) is
--clk20gen: process(clk20p000,clk20p010,clk20p100,clk20p110) is
variable cnext : slv3;
begin
if (rising_edge(clk160)) then
cnext := c20_next(clk20_ph);
clk20_ph <= cnext;
clk20_ph1 <= cnext(2) and (cnext(1) nor cnext(0));
clk20_ph2 <= not (cnext(2) or cnext(1) or cnext(0));
end if;
--if ( rising_edge(clk20p000)) then
-- clk20_ph <= "000";
--end if;
--if (falling_edge(clk20p000)) then
-- clk20_ph <= "001";
--end if;
--if ( rising_edge(clk20p010)) then
-- clk20_ph <= "010";
--end if;
--if (falling_edge(clk20p010)) then
-- clk20_ph <= "011";
--end if;
--if ( rising_edge(clk20p100)) then
-- clk20_ph <= "100";
--end if;
--if (falling_edge(clk20p100)) then
-- clk20_ph <= "101";
--end if;
--if ( rising_edge(clk20p110)) then
-- clk20_ph <= "110";
--end if;
--if (falling_edge(clk20p110)) then
-- clk20_ph <= "111";
--end if;
end process clk20gen;
--clk20_ph1 <= clk20p100;
--clk20_ph2 <= clk20p000;
--cgrom_latch: process(clk20_ph1,ram_clk) is
--begin
-- if rising_edge(ram_clk) then
-- cgrom_data <= char_rom(rama(11 downto 0));
-- end if;
--end process cgrom_latch;
init_ram: process(clk160,clk20_ph,init_stg) is
begin
if rising_edge(clk160) then
if (init_stg = initram_xfer and (clk20_ph >= "110" and clk20_ph <= "111")) then
init_r1w0 <= '0';
else
init_r1w0 <= '1';
end if;
if (clk20_ph = "011") then
case init_stg is
when initram_wait =>
if (init_counter = init_wait_to) then
init_counter <= x"0000";
init_stg <= initram_xfer;
init_addr <= x"ffff";
init_data <= x"ff";
else
init_counter <= init_counter + 1;
end if;
when initram_xfer =>
if (init_counter = ram_init_count) then
init_counter <= x"0000";
init_stg <= initram_idle;
else
init_addr <= ram_init(init_counter)(23 downto 8);
init_data <= ram_init(init_counter)(7 downto 0);
init_counter <= init_counter + 1;
end if;
when others =>
null;
end case;
end if;
end if;
end process init_ram;
sndclock: clk_wiz_1 port map (
-- Clock out ports
clk12 => clk12,
-- Status and control signals
reset => res1,
locked => clk_lk2,
-- Clock in ports
clk_in1 => clk_125
);
ram64: blk_ram_64k port map(
clka => ram_clk,
addra => rama,
dina => ramdw,
douta => ramdr,
wea(0) => ram_r0w1,
rsta => res1,
ena => ramen
);
color_ram: blk_cram port map(
clka => ram_clk,
addra => rama(9 downto 0),
dina => cramdw,
douta => cramdr,
wea(0) => cram_r0w1,
rsta => res1,
ena => cramen
);
res1 <= not res0;
cpu_r0w1 <= not cpu_r1w0;
ram_r0w1 <= not ram_r1w0;
cram_r0w1 <= not cram_r1w0;
init_r0w1 <= not init_r1w0;
ram_wren: process(cpu_r1w0,abus,bankctl,init_counter,init_addr,init_r1w0,init_stg,cpu_on) is
begin
if (init_stg = initram_xfer and init_counter > x"0000") then
if (init_bank(u16(init_addr)) = mbk_cram) then
cram_r1w0 <= init_r1w0;
ram_r1w0 <= '1';
else
cram_r1w0 <= '1';
ram_r1w0 <= init_r1w0;
end if;
elsif (cpu_on = '1') then
if (cpu_bank(u16(abus),bankctl) = mbk_cram) then
cram_r1w0 <= cpu_r1w0;
ram_r1w0 <= '1';
else
if (bank_is_writethru(abus,bankctl)='1') then
cram_r1w0 <= '1';
ram_r1w0 <= cpu_r1w0;
else
cram_r1w0 <= '1';
ram_r1w0 <= '1';
end if;
end if;
else
cram_r1w0 <= '1';
ram_r1w0 <= '1';
end if;
end process ram_wren;
with init_stg select ramdw <=
init_data when initram_xfer,
cpudo when others;
with init_stg select cramdw <=
init_data(3 downto 0) when initram_xfer,
cpudo(3 downto 0) when others;
abus <= x"fffc";
ram_a_sel: process(init_stg,cpu_on,init_addr,abus,vbank,vic_va) is
begin
if (init_stg = initram_xfer) then
rama <= init_addr;
elsif (cpu_on = '1') then
rama <= abus;
else
rama <= vbank & vic_va;
end if;
end process ram_a_sel;
ram_clk_sel: process(init_stg,cpu_on,ramclk_init,ramclk_cpu,ramclk_vic) is
begin
if (init_stg = initram_xfer) then
ram_clk <= ramclk_init;
elsif (cpu_on = '1') then
ram_clk <= ramclk_cpu;
else
ram_clk <= ramclk_vic;
end if;
end process ram_clk_sel;
with clk20_ph select ramclk_init <=
'1' when "110",
'1' when "000",
'0' when others;
with clk20_ph select ramclk_vic <=
'1' when "110",
'1' when "000",
'0' when others;
with clk20_ph select ramclk_cpu <=
'1' when "110",
'1' when "000",
'0' when others;
vic: vic_ii port map(
clk20_ph1 => clk20_ph1,
clk20_ph2 => clk20_ph2,
rga => vic_rga,
rgdi => vic_regw,
rgdo => vic_regr,
r1w0 => vic_r1w0,
cpu_clk => cpu_ph4x,
cpu_ben => cpu_on,
vic_ben => vic_on,
bus_ph1 => cpu_ph1,
bus_ph2 => cpu_ph2,
va => vic_va,
vd => vic_vd,
cd => vic_cd,
res0 => res0,
vhs => vga_hs,
vvs => vga_vs,
vr => vga_r,
vg => vga_g,
vb => vga_b
);
vic_vd_sel: process(vbank,vic_va,ramdr) is
begin
if (vbk_cgrom(vbank,vic_va) = '1') then
vic_wvd <= char_rom(vic_va(11 downto 0));
--vic_wvd <= cgrom_data;
else
vic_wvd <= ramdr;
end if;
end process vic_vd_sel;
vic_wcd <= cramdr;
vic_vd <= vic_wvd;
vic_cd <= vic_wcd;
vic_regs: process(cpu_on,cpu_ph2,c_cycle) is
begin
if (cpu_on = '1' and rising_edge(cpu_ph2)) then
case c_cycle is
when x"00" =>
vic_r1w0 <= '1';
sid1_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"01" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"02" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"03" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"04" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"05" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"06" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"07" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"08" =>
vic_rga <= xtov6(x"18");
vic_regw <= "00010100";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"09" =>
vic_rga <= xtov6(x"20");
vic_regw <= x"0e";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0a" =>
vic_rga <= xtov6(x"21");
vic_regw <= x"06";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0b" =>
vic_rga <= xtov6(x"11");
vic_regw <= x"1b";
--vic_regw <= x"17";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0c" =>
vic_rga <= xtov6(x"16");
vic_regw <= x"08";
--vic_regw <= x"07";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0d" =>
vic_rga <= xtov6(x"12");
vic_r1w0 <= '1';
sid1_rga <= xtov5(x"0e");
sid1_dw <= x"25";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0e" =>
sid1_rga <= xtov5(x"0f");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0f" =>
sid1_rga <= xtov5(x"10");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"10" =>
sid1_rga <= xtov5(x"11");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"11" =>
sid1_rga <= xtov5(x"12");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"12" =>
sid1_rga <= xtov5(x"13");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"13" =>
sid1_rga <= xtov5(x"14");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"14" =>
sid1_rga <= xtov5(x"07");
sid1_dw <= x"9a";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"15" =>
sid1_rga <= xtov5(x"08");
sid1_dw <= x"15";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"16" =>
sid1_rga <= xtov5(x"09");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"17" =>
sid1_rga <= xtov5(x"0a");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"18" =>
sid1_rga <= xtov5(x"0b");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"19" =>
sid1_rga <= xtov5(x"0c");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1a" =>
sid1_rga <= xtov5(x"0d");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1b" =>
sid1_rga <= xtov5(x"00");
sid1_dw <= x"81";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1c" =>
sid1_rga <= xtov5(x"01");
sid1_dw <= x"19";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1d" =>
sid1_rga <= xtov5(x"02");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1e" =>
sid1_rga <= xtov5(x"03");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1f" =>
sid1_rga <= xtov5(x"04");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"20" =>
sid1_rga <= xtov5(x"05");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"21" =>
sid1_rga <= xtov5(x"06");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"22" =>
sid1_rga <= xtov5(x"18");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when others =>
vic_rga <= xtov6(x"12");
vic_r1w0 <= '1';
sid1_rga <= xtov5(x"12");
sid1_dw <= sw & x"1";
sid1_r1w0 <= '0';
end case;
end if;
end process vic_regs;
sid_1: sid6581 port map (
res0 => res0,
ph2 => cpu_ph2,
rga => sid1_rga,
din => sid1_dw,
dout => sid1_dr,
r1w0 => sid1_r1w0,
s16audio => sid1_out
);
ac_muten <= res0;
ac_mclk <= clk12;
bclk_gen : process(clk12,bclk_cnt,res1) is
variable inc_0 : std_logic;
variable inc_1 : std_logic;
begin
inc_0 := not bclk_cnt(0);
inc_1 := bclk_cnt(1) xor bclk_cnt(0);
if (res1 = '1') then
bclk_cnt <= "00";
elsif (rising_edge(clk12)) then
bclk_cnt <= inc_1 & inc_0;
end if;
end process bclk_gen;
ac_bclk <= bclk_cnt(1);
audio_send : process(bclk_cnt,res1,hold2,hold_sam,sid1_out,audio_frame) is
variable apos : nybble;
begin
if (res1 = '1') then
audio_frame <= "00000";
elsif (falling_edge(bclk_cnt(1))) then
-- flipped frame index to send MSB first
apos := not nybble(audio_frame(3 downto 0));
if (buf_max(audio_frame)) then
hold_sam <= sid1_out;
end if;
if (audio_frame(4) = '1') then
ac_pbdat <= hold2(to_integer(unsigned(apos)));
else
ac_pbdat <= '0';
--ac_pbdat <= hold_sam(to_integer(unsigned(apos)));
hold2(to_integer(unsigned(apos))) <= hold_sam(to_integer(unsigned(apos)));
end if;
ac_pblrc <= audio_frame(4);
audio_frame <= adv_frame(audio_frame);
end if;
end process audio_send;
--
-- I2C config for SSM2603
--
i2c: component i2c_xcvr port map (
clk1M => cpu_ph2,
res0 => res0,
init_line => ssm_init_line,
init_data => ssm_init_data,
error => ssm_error,
scl => ac_scl,
sda => ac_sda
);
ssm_init_data <= dac_init(ssm_init_line);
led(0) <= ssm_error;
end testing;
| gpl-3.0 | 2d8c6867c6ed120d99a5432fa5b62b75 | 0.476507 | 3.196781 | false | false | false | false |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/remote_sources/_/lib/digilent/LocalRst.vhd | 1 | 1,387 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:59:06 04/04/2011
-- Design Name:
-- Module Name: LocalRst - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LocalRst is
Generic ( RESET_PERIOD : natural := 4);
Port ( RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SRST_O : out STD_LOGIC);
end LocalRst;
architecture Behavioral of LocalRst is
signal RstQ : std_logic_vector(RESET_PERIOD downto 0) := (others => '1');
begin
RstQ(0) <= '0';
RESET_LINE: for i in 1 to RESET_PERIOD generate
process(CLK_I, RST_I)
begin
if (RST_I = '1') then
RstQ(i) <= '1';
elsif Rising_Edge(CLK_I) then
RstQ(i) <= RstQ(i-1);
end if;
end process;
end generate;
SRST_O <= RstQ(RESET_PERIOD);
end Behavioral;
| gpl-3.0 | d80137dac3400373ae4ae130dd16cda5 | 0.583273 | 3.520305 | false | false | false | false |
gau-veldt/InsideTheBox | Progress_2017_12_08/vic_ii.vhd | 2 | 28,875 | ----------------------------------------------------------------------------------
--
-- VIC II simulator
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end vic_ii;
architecture vic_ii_impl of vic_ii is
attribute ram_style : string;
attribute gated_clock : string;
--attribute gated_clock of clk20_ph1 : signal is "true";
--attribute gated_clock of clk20_ph2 : signal is "true";
subtype sl is std_logic;
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype u6 is unsigned(5 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype cgptr is std_logic_vector(11 downto 0);
subtype dword is std_logic_vector(31 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype long is unsigned(31 downto 0);
subtype v_addr is std_logic_vector(13 downto 0);
subtype c_addr is std_logic_vector(9 downto 0);
subtype r_addr is std_logic_vector(5 downto 0);
type vregs is array(46 downto 0) of byte;
signal vic_regs : vregs;
attribute ram_style of vic_regs : signal is "registers";
alias vic_M0X : byte is vic_regs( 0);
alias vic_M0X8 : sl is vic_regs(16)(0);
alias vic_M1X : byte is vic_regs( 1);
alias vic_M1X8 : sl is vic_regs(16)(1);
alias vic_M2X : byte is vic_regs( 2);
alias vic_M2X8 : sl is vic_regs(16)(2);
alias vic_M3X : byte is vic_regs( 3);
alias vic_M3X8 : sl is vic_regs(16)(3);
alias vic_M4X : byte is vic_regs( 4);
alias vic_M4X8 : sl is vic_regs(16)(4);
alias vic_M5X : byte is vic_regs( 5);
alias vic_M5X8 : sl is vic_regs(16)(5);
alias vic_M6X : byte is vic_regs( 6);
alias vic_M6X8 : sl is vic_regs(16)(6);
alias vic_M7X : byte is vic_regs( 7);
alias vic_M7X8 : sl is vic_regs(16)(7);
alias vic_M0Y : byte is vic_regs( 8);
alias vic_M1Y : byte is vic_regs( 9);
alias vic_M2Y : byte is vic_regs(10);
alias vic_M3Y : byte is vic_regs(11);
alias vic_M4Y : byte is vic_regs(12);
alias vic_M5Y : byte is vic_regs(13);
alias vic_M6Y : byte is vic_regs(14);
alias vic_M7Y : byte is vic_regs(15);
alias vic_YSCROLL : slv3 is vic_regs(17)(2 downto 0);
alias vic_RSEL : sl is vic_regs(17)(3);
alias vic_DEN : sl is vic_regs(17)(4);
alias vic_BMM : sl is vic_regs(17)(5);
alias vic_ECM : sl is vic_regs(17)(6);
alias vic_RST8 : sl is vic_regs(17)(7);
alias vic_RASTER : byte is vic_regs(18);
alias vic_LPX : byte is vic_regs(19);
alias vic_LPY : byte is vic_regs(20);
alias vic_M0E : sl is vic_regs(21)(0);
alias vic_M1E : sl is vic_regs(21)(1);
alias vic_M2E : sl is vic_regs(21)(2);
alias vic_M3E : sl is vic_regs(21)(3);
alias vic_M4E : sl is vic_regs(21)(4);
alias vic_M5E : sl is vic_regs(21)(5);
alias vic_M6E : sl is vic_regs(21)(6);
alias vic_M7E : sl is vic_regs(21)(7);
alias vic_XSCROLL : slv3 is vic_regs(22)(2 downto 0);
alias vic_CSEL : sl is vic_regs(22)(3);
alias vic_MCM : sl is vic_regs(22)(4);
alias vic_RES : sl is vic_regs(22)(5);
alias vic_M0YE : sl is vic_regs(23)(0);
alias vic_M1YE : sl is vic_regs(23)(1);
alias vic_M2YE : sl is vic_regs(23)(2);
alias vic_M3YE : sl is vic_regs(23)(3);
alias vic_M4YE : sl is vic_regs(23)(4);
alias vic_M5YE : sl is vic_regs(23)(5);
alias vic_M6YE : sl is vic_regs(23)(6);
alias vic_M7YE : sl is vic_regs(23)(7);
alias vic_CB : slv3 is vic_regs(24)(3 downto 1);
alias vic_VM : nybble is vic_regs(24)(7 downto 4);
alias vic_IRQ : sl is vic_regs(25)(7);
alias vic_ILP : sl is vic_regs(25)(3);
alias vic_IMMC : sl is vic_regs(25)(2);
alias vic_IMBC : sl is vic_regs(25)(1);
alias vic_IRST : sl is vic_regs(25)(0);
alias vic_ELP : sl is vic_regs(26)(3);
alias vic_EMMC : sl is vic_regs(26)(2);
alias vic_EMBC : sl is vic_regs(26)(1);
alias vic_ERST : sl is vic_regs(26)(0);
alias vic_M0DP : sl is vic_regs(27)(0);
alias vic_M1DP : sl is vic_regs(27)(1);
alias vic_M2DP : sl is vic_regs(27)(2);
alias vic_M3DP : sl is vic_regs(27)(3);
alias vic_M4DP : sl is vic_regs(27)(4);
alias vic_M5DP : sl is vic_regs(27)(5);
alias vic_M6DP : sl is vic_regs(27)(6);
alias vic_M7DP : sl is vic_regs(27)(7);
alias vic_M0MC : sl is vic_regs(28)(0);
alias vic_M1MC : sl is vic_regs(28)(1);
alias vic_M2MC : sl is vic_regs(28)(2);
alias vic_M3MC : sl is vic_regs(28)(3);
alias vic_M4MC : sl is vic_regs(28)(4);
alias vic_M5MC : sl is vic_regs(28)(5);
alias vic_M6MC : sl is vic_regs(28)(6);
alias vic_M7MC : sl is vic_regs(28)(7);
alias vic_M0XE : sl is vic_regs(29)(0);
alias vic_M1XE : sl is vic_regs(29)(1);
alias vic_M2XE : sl is vic_regs(29)(2);
alias vic_M3XE : sl is vic_regs(29)(3);
alias vic_M4XE : sl is vic_regs(29)(4);
alias vic_M5XE : sl is vic_regs(29)(5);
alias vic_M6XE : sl is vic_regs(29)(6);
alias vic_M7XE : sl is vic_regs(29)(7);
alias vic_M0M : sl is vic_regs(30)(0);
alias vic_M1M : sl is vic_regs(30)(1);
alias vic_M2M : sl is vic_regs(30)(2);
alias vic_M3M : sl is vic_regs(30)(3);
alias vic_M4M : sl is vic_regs(30)(4);
alias vic_M5M : sl is vic_regs(30)(5);
alias vic_M6M : sl is vic_regs(30)(6);
alias vic_M7M : sl is vic_regs(30)(7);
alias vic_M0D : sl is vic_regs(31)(0);
alias vic_M1D : sl is vic_regs(31)(1);
alias vic_M2D : sl is vic_regs(31)(2);
alias vic_M3D : sl is vic_regs(31)(3);
alias vic_M4D : sl is vic_regs(31)(4);
alias vic_M5D : sl is vic_regs(31)(5);
alias vic_M6D : sl is vic_regs(31)(6);
alias vic_M7D : sl is vic_regs(31)(7);
alias vic_EC : nybble is vic_regs(32)(3 downto 0);
alias vic_B0C : nybble is vic_regs(33)(3 downto 0);
alias vic_B1C : nybble is vic_regs(34)(3 downto 0);
alias vic_B2C : nybble is vic_regs(35)(3 downto 0);
alias vic_B3C : nybble is vic_regs(36)(3 downto 0);
alias vic_MM0 : nybble is vic_regs(37)(3 downto 0);
alias vic_MM1 : nybble is vic_regs(38)(3 downto 0);
alias vic_M0C : nybble is vic_regs(39)(3 downto 0);
alias vic_M1C : nybble is vic_regs(40)(3 downto 0);
alias vic_M2C : nybble is vic_regs(41)(3 downto 0);
alias vic_M3C : nybble is vic_regs(42)(3 downto 0);
alias vic_M4C : nybble is vic_regs(43)(3 downto 0);
alias vic_M5C : nybble is vic_regs(44)(3 downto 0);
alias vic_M6C : nybble is vic_regs(45)(3 downto 0);
alias vic_M7C : nybble is vic_regs(46)(3 downto 0);
type clist is array(15 downto 0) of byte;
constant vc_red : clist := (
0=>x"00", 1=>x"FF", 2=>x"a1", 3=>x"6a", 4=>x"a2", 5=>x"5c", 6=>x"50", 7=>x"cb",
8=>x"a3", 9=>x"6e", 10=>x"cc", 11=>x"63", 12=>x"8b", 13=>x"9b", 14=>x"8a", 15=>x"af"
);
constant vc_green : clist := (
0=>x"00", 1=>x"FF", 2=>x"4d", 3=>x"c1", 4=>x"57", 5=>x"ad", 6=>x"44", 7=>x"d6",
8=>x"68", 9=>x"53", 10=>x"7f", 11=>x"63", 12=>x"8b", 13=>x"e3", 14=>x"7f", 15=>x"af"
);
constant vc_blue : clist := (
0=>x"00", 1=>x"FF", 2=>x"43", 3=>x"c8", 4=>x"a5", 5=>x"5f", 6=>x"9c", 7=>x"89",
8=>x"3a", 9=>x"0b", 10=>x"76", 11=>x"63", 12=>x"8b", 13=>x"9d", 14=>x"cd", 15=>x"af"
);
function vcolor_r(color : nybble) return byte is
begin return vc_red(to_integer(unsigned(color))); end vcolor_r;
function vcolor_g(color : nybble) return byte is
begin return vc_green(to_integer(unsigned(color))); end vcolor_g;
function vcolor_b(color : nybble) return byte is
begin return vc_blue(to_integer(unsigned(color))); end vcolor_b;
function count3(org: slv3) return slv3 is
begin
case org is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end count3;
function clk20ph_count(org: u6) return u6 is
begin
case org is
when "000000" => return "000001";
when "000001" => return "000010";
when "000010" => return "000011";
when "000011" => return "000100";
when "000100" => return "000101";
when "000101" => return "000110";
when "000110" => return "000111";
when "000111" => return "001000";
when "001000" => return "001001";
when "001001" => return "010000";
when "010000" => return "010001";
when "010001" => return "010010";
when "010010" => return "010011";
when "010011" => return "010100";
when "010100" => return "010101";
when "010101" => return "010110";
when "010110" => return "010111";
when "010111" => return "011000";
when "011000" => return "011001";
when "011001" => return "100000";
when "100000" => return "100001";
when "100001" => return "100010";
when "100010" => return "100011";
when "100011" => return "100100";
when "100100" => return "100101";
when "100101" => return "100110";
when "100110" => return "100111";
when "100111" => return "101000";
when "101000" => return "101001";
when "101001" => return "110000";
when "110000" => return "110001";
when "110001" => return "110010";
when "110010" => return "110011";
when "110011" => return "110100";
when "110100" => return "110101";
when "110101" => return "110110";
when "110110" => return "110111";
when "110111" => return "111000";
when "111000" => return "111001";
when "111001" => return "000000";
when others => return "000000";
end case;
end clk20ph_count;
signal clk20ph : u6 := "001001";
signal clk20stg : pair;
signal clk20tik : nybble := "0000";
signal cpuclk : std_logic;
signal ph0 : std_logic;
signal ph1 : std_logic;
signal ph2 : std_logic;
signal cpu_slice : std_logic;
signal vic_slice : std_logic;
signal rapos_V : u16 := "0000000000000000";
signal rapos_H : u16 := "0000000000000000";
signal vis_V : u16;
signal vis_H : u16;
signal win_V : u16;
signal win_H : u16;
signal vbdr : std_logic;
signal hbdr : std_logic;
signal bdr : std_logic;
signal en_V : std_logic;
signal en_H : std_logic;
signal en : std_logic;
signal cell_h : ubyte;
signal cell_v : ubyte;
signal cell_ph : ubyte;
signal cell_pv : ubyte;
signal rg_o : byte;
signal rg_i : byte;
function d_to_slv(arg : long) return dword is
begin
return dword(arg);
end d_to_slv;
-- line pixel/color registers
subtype slin is std_logic_vector(23 downto 0);
subtype sptr_t is std_logic_vector(13 downto 0);
type cline is array(39 downto 0) of nybble;
type bline is array(39 downto 0) of byte;
type sptr is array(7 downto 0) of sptr_t;
type sdata is array(7 downto 0) of slin;
signal line_pix : std_logic_vector(319 downto 0) := (others => '0'); -- pixels
signal line_c : cline := (others => x"f"); -- color
signal line_b : bline := (others => x"ff"); -- block (character)
signal line_sprs : sdata := (others => x"000000"); -- sprites
signal spr_ptr : sptr := (others => "00000000000000");
function u8toi(src: ubyte) return integer is
begin
return to_integer(unsigned(src));
end u8toi;
function ratoi(src: slv6) return integer is
begin
return to_integer(unsigned(src));
end ratoi;
function pxtoi(src: slv9) return integer is
begin
return to_integer(unsigned(src));
end pxtoi;
function inc6(src: slv6) return slv6 is
variable conv : unsigned(5 downto 0);
begin
conv := unsigned(src) + 1;
return slv6(conv);
end inc6;
function cpu_read(cbus,cr1w0 : std_logic) return boolean is
begin
case cbus and cr1w0 is
when '1' => return true;
when others => return false;
end case;
end;
function cpu_write(cbus,cr1w0 : std_logic) return boolean is
begin
case cbus and (not cr1w0) is
when '1' => return true;
when others => return false;
end case;
end;
function reg_in_range(rega: slv6) return boolean is
begin
case rega is
when "000000" => return true;
when "000001" => return true;
when "000010" => return true;
when "000011" => return true;
when "000100" => return true;
when "000101" => return true;
when "000110" => return true;
when "000111" => return true;
when "001000" => return true;
when "001001" => return true;
when "001010" => return true;
when "001011" => return true;
when "001100" => return true;
when "001101" => return true;
when "001110" => return true;
when "001111" => return true;
when "010000" => return true;
when "010001" => return true;
when "010010" => return true;
when "010011" => return true;
when "010100" => return true;
when "010101" => return true;
when "010110" => return true;
when "010111" => return true;
when "011000" => return true;
when "011001" => return true;
when "011010" => return true;
when "011011" => return true;
when "011100" => return true;
when "011101" => return true;
when "011110" => return true;
when "011111" => return true;
when "100000" => return true;
when "100001" => return true;
when "100010" => return true;
when "100011" => return true;
when "100100" => return true;
when "100101" => return true;
when "100110" => return true;
when "100111" => return true;
when "101000" => return true;
when "101001" => return true;
when "101010" => return true;
when "101011" => return true;
when "101100" => return true;
when "101101" => return true;
when "101110" => return true;
when others => return false;
end case;
end reg_in_range;
type fstg_t is (
get_idle,
get_m_ptrs,
get_m_data,
get_c_ptrs,
get_c_data
);
signal fetch_stg : fstg_t := get_idle;
signal fetch_m : slv3 := "000";
signal fetch_n : slv6 := "000000";
signal fetch_p : u16;
--
-- "unused vic register bits yield 1 on reading"
--
impure function vic_regs_masked(reg: integer) return byte is
begin
case reg is
when 22 => return ("11" & vic_regs(reg)(5 downto 0));
when 24 => return (vic_regs(reg)(7 downto 1) & '1');
when 25 => return (vic_regs(reg)(7) & "111" & vic_regs(reg)(3 downto 0));
when 26 => return ("1111" & vic_regs(reg)(3 downto 0));
when 32 => return ("1111" & vic_regs(reg)(3 downto 0));
when 33 => return ("1111" & vic_regs(reg)(3 downto 0));
when 34 => return ("1111" & vic_regs(reg)(3 downto 0));
when 35 => return ("1111" & vic_regs(reg)(3 downto 0));
when 36 => return ("1111" & vic_regs(reg)(3 downto 0));
when 37 => return ("1111" & vic_regs(reg)(3 downto 0));
when 38 => return ("1111" & vic_regs(reg)(3 downto 0));
when 39 => return ("1111" & vic_regs(reg)(3 downto 0));
when 40 => return ("1111" & vic_regs(reg)(3 downto 0));
when 41 => return ("1111" & vic_regs(reg)(3 downto 0));
when 42 => return ("1111" & vic_regs(reg)(3 downto 0));
when 43 => return ("1111" & vic_regs(reg)(3 downto 0));
when 44 => return ("1111" & vic_regs(reg)(3 downto 0));
when 45 => return ("1111" & vic_regs(reg)(3 downto 0));
when 46 => return ("1111" & vic_regs(reg)(3 downto 0));
when others => return vic_regs(reg);
end case;
end vic_regs_masked;
begin
clock20ph: process(clk20_ph1,clk20_ph2,clk20ph,rapos_V,rapos_H,res0) is
variable raV : u16;
variable raH : u16;
begin
raV := rapos_V;
raH := rapos_H;
if (res0 = '0') then
clk20ph <= "001001";
rapos_V <= "0000000000000000";
rapos_H <= "0000000000000000";
else
if (falling_edge(clk20_ph2)) then
--if (rising_edge(clk20_ph2)) then
clk20ph <= clk20ph_count(clk20ph);
raV := rapos_V;
raH := raH + 1;
if (raH >= 528) then
raH := "0000000000000000";
raV := raV + 1;
if (raV >= 628) then
raV := "0000000000000000";
end if;
end if;
rapos_V <= raV;
rapos_H <= raH;
end if;
if (falling_edge(clk20_ph1)) then
--if (rising_edge(clk20_ph1)) then
clk20ph <= clk20ph_count(clk20ph);
end if;
end if;
end process clock20ph;
cpu_clocks: process(clk20_ph1,clk20_ph2,clk20ph) is
begin
if (rising_edge(clk20_ph1) or rising_edge(clk20_ph2)) then
case clk20ph is
when "110001" => cpuclk <= '1';
when "110011" => cpuclk <= '1';
when "110101" => cpuclk <= '1';
when "110111" => cpuclk <= '1';
when others => cpuclk <= '0';
end case;
case clk20ph is
when "110001" => ph0 <= '1';
when "110010" => ph0 <= '1';
when "110011" => ph0 <= '1';
when "110100" => ph0 <= '1';
when others => ph0 <= '0';
end case;
case clk20ph is
when "110001" => ph1 <= '1';
when others => ph1 <= '0';
end case;
case clk20ph is
when "110101" => ph2 <= '1';
when others => ph2 <= '0';
end case;
end if;
end process cpu_clocks;
cpu_clk <= cpuclk;
bus_ph0 <= ph0;
bus_ph1 <= ph1;
bus_ph2 <= ph2;
clk20stg <= pair(clk20ph(5 downto 4));
cpu_slice <= clk20stg(1) and clk20stg(0); -- when 1 it's CPU's turn on bus
vic_slice <= clk20stg(1) nand clk20stg(0); -- when 1 it's VIC's turn on bus
cpu_ben <= cpu_slice;
vic_ben <= vic_slice;
poscalc: process(clk20_ph2, rapos_V, rapos_H) is
begin
vis_V <= rapos_V - 5;
--win_V <= rapos_V - 105;
case vic_YSCROLL is
when "000" => win_V <= rapos_V - 99;
when "001" => win_V <= rapos_V - 101;
when "010" => win_V <= rapos_V - 103;
when "011" => win_V <= rapos_V - 105;
when "100" => win_V <= rapos_V - 107;
when "101" => win_V <= rapos_V - 109;
when "110" => win_V <= rapos_V - 111;
when others => win_V <= rapos_V - 113;
end case;
vis_H <= rapos_H - 84;
--win_H <= rapos_H - 124;
case vic_XSCROLL is
when "000" => win_H <= rapos_H - 125;
when "001" => win_H <= rapos_H - 126;
when "010" => win_H <= rapos_H - 127;
when "011" => win_H <= rapos_H - 128;
when "100" => win_H <= rapos_H - 129;
when "101" => win_H <= rapos_H - 130;
when "110" => win_H <= rapos_H - 131;
when others => win_H <= rapos_H - 132;
end case;
end process poscalc;
cell_H <= ubyte(win_H(10 downto 3));
cell_V <= ubyte(win_V(11 downto 4)); -- ignoring bit 0 (so odd lines repeat the even lines)
cell_PH <= ubyte("00000" & win_H(2 downto 0));
cell_PV <= ubyte("00000" & win_V(3 downto 1)); -- ignoring bit 0 (so odd lines repeat the even lines)
hb_calc: process(clk20_ph2, rapos_H, vic_CSEL) is
begin
if (falling_edge(clk20_ph2)) then
if (vic_CSEL='1' and ((rapos_H < 124) or (rapos_H > 443))) then
hbdr <= '1';
elsif (vic_CSEL='0' and ((rapos_H < 131) or (rapos_H > 434))) then
hbdr <= '1';
else
hbdr <= '0';
end if;
end if;
end process hb_calc;
vb_calc: process(clk20_ph2, rapos_V, vic_RSEL) is
begin
if (falling_edge(clk20_ph2)) then
if (vic_RSEL='1' and ((rapos_V < 105) or (rapos_V > 504))) then
vbdr <= '1';
elsif (vic_RSEL='0' and ((rapos_V < 113) or (rapos_V > 496))) then
vbdr <= '1';
else
vbdr <= '0';
end if;
end if;
end process vb_calc;
eh_calc: process(clk20_ph2, rapos_H) is
begin
if (falling_edge(clk20_ph2)) then
if ((rapos_H < 84) or (rapos_H > 483)) then
en_H <= '0';
else
en_H <= '1';
end if;
end if;
end process eh_calc;
ev_calc: process(clk20_ph2, rapos_V) is
begin
if (falling_edge(clk20_ph2)) then
if ((rapos_V < 5) or (rapos_V > 604)) then
en_V <= '0';
else
en_V <= '1';
end if;
end if;
end process ev_calc;
bdr <= vbdr or hbdr;
en <= en_V and en_H;
hsync: process(rapos_H) is
begin
if (rapos_H < 64) then
vhs <= '1';
else
vhs <= '0';
end if;
end process hsync;
vsync: process(rapos_V) is
begin
if (rapos_V < 4) then
vvs <= '1';
else
vvs <= '0';
end if;
end process vsync;
rgdo <= rg_o;
rg_i <= rgdi;
vreg_rd: process(ph2,cpu_slice,rga,vic_regs,r1w0) is
begin
if (rising_edge(ph2)) then
if (cpu_read(cpu_slice,r1w0)) then
-- reading register
if (reg_in_range(rga)) then
--rg_o <= vic_regs(ratoi(rga));
rg_o <= vic_regs_masked(ratoi(rga));
else
rg_o <= x"FF";
end if;
end if;
end if;
end process vreg_rd;
vreg_wr: process(ph2,cpu_slice,rga,r1w0,rg_i) is
begin
if (falling_edge(ph2)) then
if (cpu_write(cpu_slice,r1w0) and reg_in_range(rga)) then
-- writing register
vic_regs(ratoi(rga)) <= rg_i;
end if;
end if;
end process vreg_wr;
fetching: process(clk20_ph1,clk20_ph2,vic_slice,fetch_stg,fetch_m,cell_PV,cd,vd,
win_v,res0,rapos_H,fetch_n,fetch_p,vic_VM,vic_CB,line_c,line_b) is
variable cur_stg : fstg_t;
variable cur_n : slv6;
begin
if (res0 = '0') then
fetch_stg <= get_idle;
else
if (vic_slice='1') then
if (rising_edge(clk20_ph1)) then
case fetch_stg is
when get_idle =>
va <= "11111111111111";
when get_m_ptrs =>
va <= vic_VM & c_addr(fetch_p(9 downto 0));
when get_m_data =>
va <= vic_CB & line_b(ratoi(fetch_n)) & slv3(cell_PV(2 downto 0));
when others =>
null;
end case;
end if;
if (falling_edge(clk20_ph2)) then
cur_stg := fetch_stg;
cur_n := fetch_n;
case cur_stg is
when get_idle =>
if (rapos_H < x"0018" and win_V < x"8000") then
if (win_V(3 downto 0) = "0000") then
fetch_stg <= get_m_ptrs;
fetch_m <= "000";
fetch_n <= "000000";
fetch_p <= (cell_V*40);
else
fetch_stg <= get_m_data;
fetch_m <= "000";
fetch_n <= "000000";
end if;
end if;
when get_m_ptrs =>
line_c(ratoi(cur_n)) <= cd;
line_b(ratoi(cur_n)) <= vd;
if (cur_n < "100111") then
fetch_n <= inc6(cur_n);
fetch_p <= fetch_p + 1;
else
fetch_n <= "000000";
fetch_stg <= get_m_data;
end if;
when get_m_data =>
line_pix(pxtoi(fetch_n & "000")) <= vd(0);
line_pix(pxtoi(fetch_n & "001")) <= vd(1);
line_pix(pxtoi(fetch_n & "010")) <= vd(2);
line_pix(pxtoi(fetch_n & "011")) <= vd(3);
line_pix(pxtoi(fetch_n & "100")) <= vd(4);
line_pix(pxtoi(fetch_n & "101")) <= vd(5);
line_pix(pxtoi(fetch_n & "110")) <= vd(6);
line_pix(pxtoi(fetch_n & "111")) <= vd(7);
if (fetch_n < "100111") then
fetch_n <= inc6(fetch_n);
else
fetch_n <= "000000";
fetch_stg <= get_idle;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process fetching;
pixgen: process(en,bdr,vic_EC,win_H,cell_H,vic_B0C,clk20_ph1) is
variable cur_px_pos : slv9;
begin
cur_px_pos := "000000000";
if (rising_edge(clk20_ph1)) then
if (en = '1') then
if (bdr = '1') then
vr <= vcolor_r(vic_EC)(7 downto 3);
vg <= vcolor_g(vic_EC)(7 downto 2);
vb <= vcolor_b(vic_EC)(7 downto 3);
else
cur_px_pos(8 downto 3) := slv6(win_H(8 downto 3));
cur_px_pos(2 downto 0) := "111" xor slv3(win_H(2 downto 0));
if (line_pix(to_integer(unsigned(cur_px_pos))) = '1') then
vr <= vcolor_r(line_c(u8toi(cell_H)))(7 downto 3);
vg <= vcolor_g(line_c(u8toi(cell_H)))(7 downto 2);
vb <= vcolor_b(line_c(u8toi(cell_H)))(7 downto 3);
else
vr <= vcolor_r(vic_B0C)(7 downto 3);
vg <= vcolor_g(vic_B0C)(7 downto 2);
vb <= vcolor_b(vic_B0C)(7 downto 3);
end if;
end if;
else
vr <= "00000";
vg <= "000000";
vb <= "00000";
end if;
end if;
end process pixgen;
end vic_ii_impl;
| gpl-3.0 | b8dd9ae12bbaf89cec62727dc5ad6f0e | 0.501403 | 3.184977 | false | false | false | false |
PsiStarPsi/firmware-ethernet | Ethernet/General/rtl/UdpBufferRx.vhd | 1 | 8,302 | ---------------------------------------------------------------------------------
-- Title : UDP Buffer RX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : UdpBufferRx.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Connects to IPv4 receiver, demuxes to RX FIFOs for each IP address.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.GigabitEthPkg.all;
entity UdpBufferRx is
generic (
NUM_IP_G : integer := 1;
GATE_DELAY_G : time := 1 ns
);
port (
-- 125 MHz ethernet clock in
ethRxClk : in sl;
ethRxRst : in sl := '0';
-- Settings for this receiver
ipAddr : in IpAddrType;
udpPort : in slv(15 downto 0);
-- Data from the IPv4 header
ipLength : in slv(15 downto 0);
ipId : in slv(15 downto 0);
ipMoreFragments : in sl;
ipFragOffset : in slv(12 downto 0);
ipTtl : in slv( 7 downto 0);
ipProtocol : in slv( 7 downto 0);
ipSrcAddr : in IpAddrType;
ipDstAddr : in IpAddrType;
-- Actual data from the payload
ipData : in slv(31 downto 0);
ipDataValid : in sl;
ipDataLast : in sl;
-- UDP outputs
udpSrcPort : out slv(15 downto 0);
udpDstPort : out slv(15 downto 0);
udpLength : out slv(15 downto 0);
udpChecksum : out slv(15 downto 0);
-- UDP payload data interface
userRxClk : in sl;
userRxData : out slv(31 downto 0);
userRxDataValid : out sl;
userRxDataLast : out sl;
userRxDataReady : in sl
);
end UdpBufferRx;
-- Define architecture
architecture rtl of UdpBufferRx is
type StateType is (IDLE_AND_HEADER_0_S, HEADER_1_S,
PAYLOAD_S, DUMP_S);
type RegType is record
state : StateType;
myIpAddr : IpAddrType;
myUdpPort : slv(15 downto 0);
ipLength : slv(15 downto 0);
ipId : slv(15 downto 0);
ipMoreFragments : sl;
ipFragOffset : slv(12 downto 0);
ipTtl : slv( 7 downto 0);
ipProtocol : slv( 7 downto 0);
ipSrcAddr : IpAddrType;
ipDstAddr : IpAddrType;
udpSrcPort : slv(15 downto 0);
udpDstPort : slv(15 downto 0);
udpLength : slv(15 downto 0);
udpChecksum : slv(15 downto 0);
fifoWrData : slv(31 downto 0);
fifoWrDataValid : sl;
fifoWrDataLast : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_AND_HEADER_0_S,
myIpAddr => IP_ADDR_INIT_C,
myUdpPort => (others => '0'),
ipLength => (others => '0'),
ipId => (others => '0'),
ipMoreFragments => '0',
ipFragOffset => (others => '0'),
ipTtl => (others => '0'),
ipProtocol => (others => '0'),
ipSrcAddr => IP_ADDR_INIT_C,
ipDstAddr => IP_ADDR_INIT_C,
udpSrcPort => (others => '0'),
udpDstPort => (others => '0'),
udpLength => (others => '0'),
udpChecksum => (others => '0'),
fifoWrData => (others => '0'),
fifoWrDataValid => '0',
fifoWrDataLast => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
signal fifoWrDataReady : sl;
begin
------------------------------------------
-- FIFO to write valid UDP payload into --
------------------------------------------
U_UdpRxAxiFifo : entity work.fifo32x512RxAxi
PORT MAP (
m_aclk => userRxClk,
s_aclk => ethRxClk,
s_aresetn => not(ethRxRst),
s_axis_tvalid => r.fifoWrDataValid,
s_axis_tready => fifoWrDataReady,
s_axis_tdata => r.fifoWrData,
s_axis_tlast => r.fifoWrDataLast,
m_axis_tvalid => userRxDataValid,
m_axis_tready => userRxDataReady,
m_axis_tdata => userRxData,
m_axis_tlast => userRxDataLast
);
------------------------------------------
-- State machine to locate valid data --
------------------------------------------
comb : process(r,ethRxRst,ipAddr,udpPort,ipLength,ipId,ipMoreFragments,
ipFragOffset,ipTtl,ipProtocol,ipSrcAddr,ipDstAddr,
ipData,ipDataValid,ipDataLast,fifoWrDataReady) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
-- Register incoming data
v.fifoWrDataValid := '0';
v.fifoWrDataLast := '0';
-- State machine for interpreting 32-bit data
case(r.state) is
when IDLE_AND_HEADER_0_S =>
if ipDataValid = '1' and ipDataLast /= '1' then
v.myIpAddr := ipAddr;
v.myUdpPort := udpPort;
v.ipLength := ipLength;
v.ipId := ipId;
v.ipMoreFragments := ipMoreFragments;
v.ipFragOffset := ipFragOffset;
v.ipTtl := ipTtl;
v.ipProtocol := ipProtocol;
v.ipSrcAddr := ipSrcAddr;
v.ipDstAddr := ipDstAddr;
v.udpSrcPort := ipData(31 downto 16);
v.udpDstPort := ipData(15 downto 0);
v.state := HEADER_1_S;
end if;
when HEADER_1_S =>
-- Dump out of the event if ports don't match, IPs don't match,
-- or if this is our last data
if ipDataValid = '1' then
-- Dump if this is an incomplete packet...
if ipDataLast = '1' then
v.state := IDLE_AND_HEADER_0_S;
-- Or if it turns out it wasn't UDP...
-- Or if the IP addresses don't match...
-- Or if the UDP ports don't match...
elsif ( (r.ipProtocol /= IPV4_PROTO_UDP_C) or
(r.udpDstPort /= r.myUdpPort) or
(r.ipDstAddr /= r.myIpAddr) ) then
v.state := DUMP_S;
-- Otherwise we have a good packet
else
v.udpLength := ipData(31 downto 16);
v.udpChecksum := ipData(15 downto 0);
v.state := PAYLOAD_S;
end if;
end if;
when PAYLOAD_S =>
v.fifoWrData := ipData;
v.fifoWrDataValid := ipDataValid;
v.fifoWrDataLast := ipDataLast;
if ipDataValid = '1' and ipDataLast = '1' then
v.state := IDLE_AND_HEADER_0_S;
end if;
when DUMP_S =>
if ipDataValid = '1' and ipDataLast = '1' then
v.state := IDLE_AND_HEADER_0_S;
end if;
-- Others
when others =>
v.state := IDLE_AND_HEADER_0_S;
end case;
-- Reset logic
if (ethRxRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
udpSrcPort <= r.udpSrcPort;
udpDstPort <= r.udpDstPort;
udpLength <= r.udpLength;
udpChecksum <= r.udpChecksum;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
seq : process (ethRxClk) is
begin
if (rising_edge(ethRxClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | a883cc32e943a28d2a209fb61bf3a3d7 | 0.480005 | 4.427733 | false | false | false | false |
SLongofono/Senior_Design_Capstone | StupidCore/RAM.vhd | 1 | 7,870 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RAM_Controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
done: out STD_LOGIC;
write, read: in STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end RAM_Controller;
architecture Behavioral of RAM_Controller is
component ram2ddrxadc
port(
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
-- The RAM is accessing 2 bytes per access
ram_a : in std_logic_vector(26 downto 0); -- input address
ram_dq_i : in std_logic_vector(15 downto 0); -- input data
ram_dq_o : out std_logic_vector(15 downto 0); -- output data
ram_cen : in std_logic; -- chip enable
ram_oen : in std_logic; -- output enable
ram_wen : in std_logic; -- write enable
ram_ub : in std_logic; -- upper byte
ram_lb : in std_logic; -- lower byte
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
-- Physical RAM Pin Signals
signal ram_cen, ram_oen, ram_wen, ram_ub, ram_lb: std_logic;
signal ram_dq_o, ram_dq_i: std_logic_vector (15 downto 0);
type memory_states IS (IDLE_STATE, PREPARE_STATE, READ_STATE, WRITE_STATE, INTERMITENT_STATE);
-- Where current state and next_state are pretty self-forward, last state will check
signal current_state, next_state, last_state: memory_states := IDLE_STATE;
signal temp_data_write, temp_data_read: std_logic_vector(63 downto 0);
signal ram_a: std_logic_vector(26 downto 0);
-- Result
signal read_out: std_logic_vector(15 downto 0) := (others => '0');
-- Counters
signal hundred_nano_seconds_elapsed, wait_counter : integer range 0 to 150 := 0;
signal s_read : std_logic := '0';
signal writeOnce, readOnce : std_logic := '0';
begin
ram2ddr: ram2ddrxadc
port map(
clk_200MHz_i=>clk_200,
rst_i=>rst,
device_temp_i=>"000000000000",
ram_a=>ram_a,
ram_dq_i=>ram_dq_o,
ram_dq_o=>ram_dq_i,
ram_cen=>ram_cen,
ram_oen=>ram_oen,
ram_wen=>ram_wen,
ram_ub=>ram_ub,
ram_lb=>ram_lb,
ddr2_addr=>ddr2_addr,
ddr2_ba=>ddr2_ba,
ddr2_ras_n=>ddr2_ras_n,
ddr2_cas_n=>ddr2_cas_n,
ddr2_we_n=>ddr2_we_n,
ddr2_ck_p=>ddr2_ck_p,
ddr2_ck_n=>ddr2_ck_n,
ddr2_cke=>ddr2_cke,
ddr2_cs_n=>ddr2_cs_n,
ddr2_dm=>ddr2_dm,
ddr2_odt=>ddr2_odt,
ddr2_dq=>ddr2_dq,
ddr2_dqs_p=>ddr2_dqs_p,
ddr2_dqs_n=>ddr2_dqs_n
);
process(clk_100,rst) begin
if(rst = '1') then
current_state <= IDLE_STATE;
elsif(rising_edge(clk_100)) then
current_state <= next_state;
end if;
end process;
process(current_state, rst, clk_100) begin
if(rst = '1') then
read_out <= (others => '0');
readOnce <= '0';
writeOnce <= '0';
elsif(rising_edge(clk_100)) then
next_state <= current_state;
case current_state is
-- State IDLE_STATE: Disable chip enable, write and read
when IDLE_STATE =>
ram_cen <= '1';
ram_oen <= '1';
ram_wen <= '1';
if(read = '1') then
s_read <= '1';
next_state <= PREPARE_STATE;
elsif(write = '1') then
s_read <= '0';
next_state <= PREPARE_STATE;
end if;
-- State PREPARE_STATE: Assert whatever needs to be asserted
when PREPARE_STATE =>
-- Reset the counters
hundred_nano_seconds_elapsed <= 0;
wait_counter <= 0;
-- Read
if(s_read = '1') then
readOnce <= '1';
ram_oen <= '0';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '1';
next_state <= READ_STATE;
-- Write
else
writeOnce <= '1';
ram_oen <= '1';
ram_cen <= '0';
ram_lb <= '0';
ram_ub <= '0';
ram_wen <= '0';
next_state <= WRITE_STATE;
end if;
-- State READ_STATE: Waits until the delta time indicated by the
-- data sheet has elapsed to finish reading
when READ_STATE =>
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
-- Wait till the necessary clock cycles elapsed while it's recording the data
if(hundred_nano_seconds_elapsed > 22) then
read_out <= ram_dq_i;
next_state <= INTERMITENT_STATE;
end if;
when WRITE_STATE =>
hundred_nano_seconds_elapsed <= hundred_nano_seconds_elapsed + 1;
if(hundred_nano_seconds_elapsed > 27) then
next_state <= INTERMITENT_STATE;
-- Dummy read_out to signal we are done writing
read_out <= (5 => '1', others => '0');
end if;
-- State INTERMITENT_STATE: The done flag will be raised to allow the MMU
-- to continue onto the next byte
when INTERMITENT_STATE =>
read_out <= ram_dq_i;
next_state <= IDLE_STATE;
when others =>
next_state <= IDLE_STATE;
end case;
end if;
end process;
ram_dq_o <= data_in;
ram_a <= contr_addr_in;
data_out <= read_out;
done <= '1' when current_state = INTERMITENT_STATE else '0';
end Behavioral;
| mit | cab7161446b080dda32e0087922c6bc0 | 0.500635 | 3.623389 | false | false | false | false |
Subsets and Splits