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zhlinh/vhdl_course | Assignment/IMG_LSB/simulation/modelsim/TB_IMG_LSB_bak.vhd | 1 | 5,393 | -- Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "07/05/2015 10:58:13"
-- Vhdl Test Bench template for design : IMG_LSB
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.mytype.all;
USE std.textio.all;
USE ieee.std_logic_textio.all;
ENTITY IMG_LSB_vhd_tst IS
END IMG_LSB_vhd_tst;
ARCHITECTURE IMG_LSB_arch OF IMG_LSB_vhd_tst IS
-- constants
-- signals
FILE INTEXT_R: TEXT IS IN "INTEXT_R.txt";
FILE INTEXT_G: TEXT IS IN "INTEXT_G.txt";
FILE INTEXT_B: TEXT IS IN "INTEXT_B.txt";
FILE OUTTEXT_R: TEXT IS OUT "OUTTEXT_R.txt";
FILE OUTTEXT_G: TEXT IS OUT "OUTTEXT_G.txt";
FILE OUTTEXT_B: TEXT IS OUT "OUTTEXT_B.txt";
SIGNAL A_COL : COLOR:=4;
SIGNAL A_ROW : COLOR:=0;
SIGNAL B_COL : COLOR:=10;
SIGNAL B_ROW : COLOR:=0;
SIGNAL C_COL : COLOR:=16;
SIGNAL C_ROW : COLOR:=0;
SIGNAL B_IN : COLOR;
SIGNAL B_OUT : COLOR;
SIGNAL CLK : STD_LOGIC;
SIGNAL DETECT_RESULT : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL G_IN : COLOR;
SIGNAL G_OUT : COLOR;
SIGNAL R_IN : COLOR;
SIGNAL R_OUT : COLOR;
SIGNAL RESET : STD_LOGIC;
SIGNAL SEL : STD_LOGIC:='1';
CONSTANT CLK_PERIOD:TIME:=10 NS;
COMPONENT IMG_LSB
PORT (
A_COL : IN COLOR;
A_ROW : IN COLOR;
B_COL : IN COLOR;
B_IN : IN COLOR;
B_OUT : BUFFER COLOR;
B_ROW : IN COLOR;
C_COL : IN COLOR;
C_ROW : IN COLOR;
CLK : IN STD_LOGIC;
DETECT_RESULT : BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0);
G_IN : IN COLOR;
G_OUT : BUFFER COLOR;
R_IN : IN COLOR;
R_OUT : BUFFER COLOR;
RESET : IN STD_LOGIC;
SEL : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : IMG_LSB
PORT MAP (
-- list connections between master ports and signals
A_COL => A_COL,
A_ROW => A_ROW,
B_COL => B_COL,
B_IN => B_IN,
B_OUT => B_OUT,
B_ROW => B_ROW,
C_COL => C_COL,
C_ROW => C_ROW,
CLK => CLK,
DETECT_RESULT => DETECT_RESULT,
G_IN => G_IN,
G_OUT => G_OUT,
R_IN => R_IN,
R_OUT => R_OUT,
RESET => RESET,
SEL => SEL
);
init : PROCESS
-- variable declarations
BEGIN
--只作为赋初值使用
RESET<='1';
WAIT FOR (CLK_PERIOD/4)*3;
RESET<='0';
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
VARIABLE INLINE_R: LINE;
VARIABLE INLINE_G: LINE;
VARIABLE INLINE_B: LINE;
VARIABLE OUTLINE_R : LINE;
VARIABLE OUTLINE_G : LINE;
VARIABLE OUTLINE_B : LINE;
VARIABLE INR_V,ING_V,INB_V,OUTR_V,OUTG_V,OUTB_V: COLOR;
VARIABLE INCOL: INTEGER RANGE 0 TO 256 :=0;
VARIABLE I: INTEGER RANGE 0 TO 9:=0;
CONSTANT DELAY: INTEGER:=4;
VARIABLE OUTCOL: INTEGER RANGE 0 TO 256 :=0;
VARIABLE OUTROW: INTEGER RANGE 0 TO 256 :=0;
BEGIN
-- code executes for every event on sensitivity list
CLK<='0';
WAIT FOR CLK_PERIOD/2;
CLK<='1';
--读入数据
IF(NOT ENDFILE(INTEXT_R)) THEN
IF(INCOL=0) THEN
READLINE(INTEXT_R,INLINE_R);
END IF;
READ(INLINE_R,INR_V);
R_IN<=INR_V;
END IF;
IF(NOT ENDFILE(INTEXT_G)) THEN
IF(INCOL=0) THEN
READLINE(INTEXT_G,INLINE_G);
END IF;
READ(INLINE_G,ING_V);
G_IN<=ING_V;
END IF;
IF(NOT ENDFILE(INTEXT_B)) THEN
IF(INCOL=0) THEN
READLINE(INTEXT_B,INLINE_B);
END IF;
READ(INLINE_B,INB_V);
B_IN<=INB_V;
END IF;
--写数据
--延迟3个时钟周期
IF (I<DELAY) THEN
I:=I+1;
ELSE
WRITE(OUTLINE_R,R_OUT);
--以TAB分隔，VHDL定义的emum里tab就为HT
WRITE(OUTLINE_R,HT);
WRITE(OUTLINE_G,G_OUT);
WRITE(OUTLINE_G,HT);
WRITE(OUTLINE_B,B_OUT);
WRITE(OUTLINE_B,HT);
IF(OUTCOL=255 AND OUTROW<=255) THEN
OUTROW:=OUTROW+1;
WRITELINE(OUTTEXT_R,OUTLINE_R);
WRITELINE(OUTTEXT_G,OUTLINE_G);
WRITELINE(OUTTEXT_B,OUTLINE_B);
END IF;
IF(OUTCOL<=255) THEN
OUTCOL:=OUTCOL+1;
END IF;
IF(OUTCOL=256) THEN
OUTCOL:=0;
END IF;
END IF;
IF(INCOL<=255) THEN
INCOL:=INCOL+1;
END IF;
IF(INCOL=256) THEN
INCOL:=0;
END IF;
WAIT FOR CLK_PERIOD/2;
END PROCESS always;
END IMG_LSB_arch;
| apache-2.0 | 0df4c4c4a5b1192d9af0623f2f5c3962 | 0.620004 | 3.175805 | false | false | false | false |
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| gpl-3.0 | 6a6228a3ab42f2b0174d805c801a9542 | 0.952324 | 1.833165 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/TB_com_scheduler.vhd | 1 | 2,402 | --------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.myDeclare.all;
ENTITY TB_com_scheduler IS
END TB_com_scheduler;
ARCHITECTURE behavior OF TB_com_scheduler IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT com_scheduler
PORT(
clk : IN std_logic;
reset : IN std_logic;
device_data_array : in device_data_array_type; -- Array of dimension (No. of device x 16bits) data, each 16bits corresponds to 1 device input stream
device_flag_array : in std_logic_vector(0 to NUMBEROFDEVICE-1);
serdes_data_out : OUT std_logic_vector(11 downto 0);
serdes_valid_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal device_data_array : device_data_array_type;
signal device_flag_array : std_logic_vector(0 to NUMBEROFDEVICE-1);
--Outputs
signal serdes_data_out : std_logic_vector(11 downto 0);
signal serdes_valid_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: com_scheduler PORT MAP (
clk => clk,
reset => reset,
device_data_array => device_data_array,
device_flag_array => device_flag_array,
serdes_data_out => serdes_data_out,
serdes_valid_out => serdes_valid_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
device_data_array(0) <= std_logic_vector(to_unsigned(172, 16));
device_data_array(1) <= std_logic_vector(to_unsigned(65, 16));
device_data_array(2) <= std_logic_vector(to_unsigned(32, 16));
device_data_array(3) <= std_logic_vector(to_unsigned(88, 16));
device_flag_array <= (others=>'1');
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
wait;
end process;
END;
| mit | 1cfe5aa7f522746767dcb35a3feb9b22 | 0.566611 | 3.77673 | false | false | false | false |
kacaperek/serdescrc16 | serializer.vhd | 1 | 3,452 | ----------------------------------------------------------------------------------
-- Company: PWr
-- Engineer: Kacper Witkowski
-- Module Name: Serializer
-- Project Name: Nadajnik i odbiornik szeregowy z kontrolą poprawności przesyłu CRC16
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.PCK_CRC16_D1.all;
entity serializer is
Port (
parallel_in : in STD_LOGIC_vector(7 downto 0); --dane wejściowe
serial_out : out STD_LOGIC;
serial_in : in std_logic;
clk : in STD_LOGIC;
reset : in STD_LOGIC);
end serializer;
architecture Behavioral of serializer is
signal cnt : std_logic_vector(2 downto 0):= "000"; -- licznik
signal d : std_logic_vector(7 downto 0) := (others => '0'); -- rejestr danych
signal transmission_running : std_logic := '0'; -- czy transmisja działa? generowane po sygnale 0x7e
signal crc_running : std_logic := '0'; -- po przesłaniu całego pakietu kontrolnego, działa crc
signal pckg_cnt : std_logic_vector(4 downto 0) := (others => '0'); --licznik wysłanych pakietów
signal newCRC : std_logic_vector(15 downto 0) := (others => '0'); -- wektor aktualnej wartosci crc
begin
counter : process (reset, clk)
begin
if reset='0' then
cnt <= ( others => '0' );
elsif (clk'event and clk ='1') then
if transmission_running = '1' then
cnt <= cnt + "01"; -- licznik bitów
if cnt = "111" and pckg_cnt = "10010" then -- po wysłaniu wszystkiego wraz z CRC
pckg_cnt <= "00000";
elsif cnt = "111" then
pckg_cnt <= pckg_cnt + "01"; -- licznik bajtów
end if;
end if;
end if;
end process counter;
transmission_control : process(reset, clk, d)
begin
if reset='0' then
transmission_running <= '0';
crc_running <= '0';
elsif clk'event and clk = '1' then
if d = "01111110" or (pckg_cnt = "00000" and serial_in = '1') then -- wystartuj dopiero po 0x7e
transmission_running <= '1';
end if;
if transmission_running = '1' and cnt = "111" and pckg_cnt = "00000" then
crc_running <= '1'; -- zacznij liczyć crc po wysłaniu nagłówka
elsif pckg_cnt = "10001" and cnt = "000" then
crc_running <= '0'; -- skończ liczyć crc po 16 bajtach
elsif (cnt = "111" and pckg_cnt = "10010") then -- zatrzymaj się i wyzeruj crc po wysłaniu wszystkiego
transmission_running <= '0';
end if;
end if;
end process transmission_control;
crc_calc : process(reset, clk)
begin
if clk'event and clk = '1' then
if crc_running = '1' then
newCRC <= nextCRC16(d(7), newCRC); -- obliczanie crc
elsif pckg_cnt = "10010" and cnt = "111" then
newCRC <= (others => '0');
end if;
end if;
end process crc_calc;
piso : process (reset, clk)
begin
if reset='0' then
d <= (others => '0');
elsif (clk'event and clk = '1') then
if cnt = "000" then -- zareaguj dopiero na 0x7e lub potwierdzenie zgodnosci crc
if pckg_cnt = "10001" then
d <= newCRC(14 downto 7); -- wyslij pierwszą połowę crc
elsif pckg_cnt = "10010" then
d <= newCRC(7 downto 0); -- wyślij drugą połowę crc
else
d <= parallel_in; -- wyślij to co na wejściu
end if;
else
d(7 downto 0) <= d(6 downto 0) & '0'; -- rejestr wysyłanych danych
end if;
end if;
end process piso;
serial_out <= d(7); -- wyślij
end Behavioral;
| gpl-2.0 | c1a1826ac811c6f22a65bb7d5bdb6866 | 0.604386 | 2.953368 | false | false | false | false |
Hyvok/HardHeat | sim/one_wire/one_wire_tb.vhd | 1 | 6,012 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity one_wire_tb is
end entity;
architecture rtl of one_wire_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
constant TX_TEST_DATA : std_logic_vector(7 downto 0) := "10101010";
constant RX_TEST_DATA : std_logic_vector(7 downto 0) := "10101010";
signal clk : std_logic := '0';
signal reset : std_logic;
signal reset_ow : std_logic;
signal ow_in : std_logic;
signal ow_out : std_logic;
signal ow_n_out : std_logic;
signal data : std_logic_vector(8 - 1 downto 0);
signal data_f : std_logic;
signal receive_data_f : std_logic;
signal busy : std_logic;
signal data_out : std_logic_vector(8 - 1 downto 0);
signal data_out_f : std_logic;
-- Signals internal to the test bench, not related to DUT
signal reset_done : std_logic;
signal send_done : std_logic;
signal receive_done : std_logic;
begin
-- Invert the output signal coming from the 1-wire module for display
ow_out <= not ow_n_out;
DUT_inst: entity work.one_wire(rtl)
generic map
(
US_D => 100
)
port map
(
clk => clk,
reset => reset,
reset_ow => reset_ow,
ow_in => ow_in,
data_in => data,
data_in_f => data_f,
receive_data_f => receive_data_f,
ow_out => ow_n_out,
busy_out => busy,
data_out => data_out,
data_out_f => data_out_f
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
-- TODO: Change all these processes to a single state machine!
-- Generate a reset pulse on the 1-wire bus once reset is done
ow_reset_gen: process(clk, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
reset_ow <= '0';
elsif rising_edge(clk) then
reset_ow <= '0';
if done = '0' then
reset_ow <= '1';
done := '1';
end if;
end if;
end process;
-- Pull up flag after reset is sent to the bus (bus is not busy anymore)
ow_reset_done_gen: process(busy, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
reset_done <= '0';
elsif falling_edge(busy) then
if done = '0' then
reset_done <= '1';
done := '1';
end if;
end if;
end process;
-- Send data on OW bus after reset is done
ow_tx_data_gen: process(reset_done, clk, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
data <= (others => '0');
data_f <= '0';
elsif rising_edge(reset_done) then
data <= TX_TEST_DATA;
data_f <= '1';
elsif rising_edge(clk) then
data_f <= '0';
end if;
end process;
-- Pull up flag after done sending data to the bus (bus is not busy anymore)
ow_send_done_gen: process(busy, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
send_done <= '0';
elsif falling_edge(busy) then
if done = '0' and reset_done = '1' then
send_done <= '1';
done := '1';
end if;
end if;
end process;
-- Pull up a flag to indicate we want to receive data from the OW bus
ow_rx_f_gen: process(send_done, clk, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
receive_data_f <= '0';
elsif rising_edge(send_done) then
if done = '0' then
receive_data_f <= '1';
done := '1';
end if;
elsif rising_edge(clk) then
receive_data_f <= '0';
end if;
end process;
-- Send data to OW module after sending is done
ow_rx_data_gen: process(send_done, ow_out, reset)
variable done : std_logic;
variable sending : std_logic;
variable index : natural;
begin
if reset = '1' then
done := '0';
sending := '0';
ow_in <= '0';
index := 0;
elsif rising_edge(send_done) then
-- Only start sending after TX test is done
sending := '1';
elsif rising_edge(ow_out) then
if sending = '1' then
index := index + 1;
if index = 7 then
ow_in <= RX_TEST_DATA(index);
sending := '0';
done := '1';
else
ow_in <= RX_TEST_DATA(index);
end if;
end if;
end if;
end process;
-- Pull up flag after done sending data to the bus (bus is not busy anymore)
ow_receive_done_gen: process(busy, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
receive_done <= '0';
elsif falling_edge(busy) then
if done = '0' and send_done = '1' then
receive_done <= '1';
done := '1';
end if;
end if;
end process;
-- Assert received data is correct
ow_rx_data_assert: process(data_out_f)
begin
if data_out_f = '1' then
assert data_out = RX_TEST_DATA report "RX data does not match!"
severity warning;
end if;
end process;
end;
| mit | 3006ee1e5d479377b6fa38024306a551 | 0.479541 | 3.881214 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ipstatic/hdl/c_mux_bit_v12_0_vh_rfs.vhd | 1 | 239,688 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | e5f3fe93bbfb3dd45cb69ed037e6de61 | 0.95437 | 1.827517 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 1 | 30,077 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect end_protected
| gpl-3.0 | de05059767432c17e4964e8474f166f5 | 0.942714 | 1.870693 | false | false | false | false |
zhlinh/vhdl_course | Assignment/FREQ_CNT/COUNT.vhd | 1 | 2,020 | --Count Frequence
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT IS
PORT( CLK: IN STD_LOGIC;
CLK_OUT_05HZ: IN STD_LOGIC;
RST: IN STD_LOGIC;
D1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY: OUT STD_LOGIC;
READ_EN: OUT STD_LOGIC);
END ENTITY COUNT;
ARCHITECTURE ART1 OF COUNT IS
SIGNAL CNT:STD_LOGIC_VECTOR(15 DOWNTO 0);
-- SIGNAL MEASURE_FLAG:STD_LOGIC;
BEGIN
PROCESS(CLK,RST,CNT,CLK_OUT_05HZ)
BEGIN
IF(RST='1')THEN
CNT<=(OTHERS=>'0');
CARRY<='0';
ELSIF(CLK'EVENT AND CLK='1')THEN
IF (CLK_OUT_05HZ='1') THEN
READ_EN<='0';
IF (CNT(3 DOWNTO 0)/="1001")THEN
CNT(3 DOWNTO 0)<=CNT(3 DOWNTO 0)+'1';
ELSIF(CNT(7 DOWNTO 4)/="1001")THEN
CNT(3 DOWNTO 0)<="0000";
CNT(7 DOWNTO 4)<=CNT(7 DOWNTO 4)+'1';
ELSIF(CNT(11 DOWNTO 8)/="1001")THEN
CNT(3 DOWNTO 0)<="0000";
CNT(7 DOWNTO 4)<="0000";
CNT(11 DOWNTO 8)<=CNT(11 DOWNTO 8)+'1';
ELSIF(CNT(15 DOWNTO 12)/="1001")THEN
CNT(3 DOWNTO 0)<="0000";
CNT(7 DOWNTO 4)<="0000";
CNT(11 DOWNTO 8)<="0000";
CNT(15 DOWNTO 12)<=CNT(15 DOWNTO 12)+'1';
ELSE
CNT<=(OTHERS=>'0');
CARRY<='1';
END IF;
ELSIF(CLK_OUT_05HZ='0')THEN
CNT<=(OTHERS=>'0');
READ_EN<='1';
END IF;
END IF;
D4<=CNT(15 DOWNTO 12);
D3<=CNT(11 DOWNTO 8);
D2<=CNT(7 DOWNTO 4);
D1<=CNT(3 DOWNTO 0);
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | a65ae7f35bef37fd1a10eab33556a298 | 0.468812 | 3.488774 | false | false | false | false |
Hyvok/HardHeat | src/tdc.vhd | 1 | 2,216 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tdc is
generic
(
-- Number of bits in the counter
COUNTER_N : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
up_in : in std_logic;
down_in : in std_logic;
time_out : out signed(COUNTER_N - 1 downto 0);
sig_or_out : out std_logic;
sign_out : out std_logic
);
end tdc;
architecture rtl of tdc is
begin
tdc_p: process(clk, reset)
variable sig_or : std_logic;
variable last_or : std_logic;
variable last_up : std_logic;
variable last_down : std_logic;
variable sign : std_logic;
variable count : signed(COUNTER_N - 1 downto 0);
begin
if reset = '1' then
time_out <= (others => '0');
count := (others => '0');
last_or := '0';
last_up := '0';
last_down := '0';
sign := '0';
sign_out <= sign;
sig_or := '0';
elsif rising_edge(clk) then
if not up_in = last_up and up_in = '1' then
sign := '0';
sign_out <= sign;
elsif not down_in = last_down and down_in = '1' then
sign := '1';
sign_out <= sign;
end if;
last_up := up_in;
last_down := down_in;
sig_or := up_in or down_in;
sig_or_out <= sig_or;
-- Count when the or signal is high
if sig_or = '1' then
count := count + 1;
else
if last_or = '1' then
-- Apply sign
if sign = '1' then
time_out <= not count + 1;
else
time_out <= count;
end if;
count := (others => '0');
end if;
end if;
last_or := sig_or;
end if;
end process;
end;
| mit | 22c380720a80661f322bd25f4db4aee5 | 0.395307 | 4.142056 | false | false | false | false |
iamllama/EE2020 | ee2020.cache/ip/50f89269c3fbefe4/dds_compiler_0_sim_netlist.vhdl | 1 | 194,536 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Mar 28 02:26:33 2017
-- Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_sim_netlist.vhdl
-- Design : dds_compiler_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "artix7";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 11 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 22;
attribute C_AMPLITUDE of i_synth : label is 1;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 7;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS of i_synth : label is 10000;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 0;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH of i_synth : label is 12;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 12;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 24;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "artix7";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(21) <= \<const0>\;
debug_axi_pinc_in(20) <= \<const0>\;
debug_axi_pinc_in(19) <= \<const0>\;
debug_axi_pinc_in(18) <= \<const0>\;
debug_axi_pinc_in(17) <= \<const0>\;
debug_axi_pinc_in(16) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(21) <= \<const0>\;
debug_axi_poff_in(20) <= \<const0>\;
debug_axi_poff_in(19) <= \<const0>\;
debug_axi_poff_in(18) <= \<const0>\;
debug_axi_poff_in(17) <= \<const0>\;
debug_axi_poff_in(16) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(21) <= \<const0>\;
debug_phase(20) <= \<const0>\;
debug_phase(19) <= \<const0>\;
debug_phase(18) <= \<const0>\;
debug_phase(17) <= \<const0>\;
debug_phase(16) <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tdata(15) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(14) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(13) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(12) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(11 downto 0) <= \^m_axis_data_tdata\(11 downto 0);
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const1>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13_viv
port map (
aclk => aclk,
aclken => '0',
aresetn => '0',
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15) => \^m_axis_data_tdata\(11),
m_axis_data_tdata(14 downto 11) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14 downto 11),
m_axis_data_tdata(10 downto 0) => \^m_axis_data_tdata\(10 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 22) => B"00",
s_axis_phase_tdata(21 downto 0) => s_axis_phase_tdata(21 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "dds_compiler_0,dds_compiler_v6_0_13,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "dds_compiler_v6_0_13,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of U0 : label is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of U0 : label is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of U0 : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of U0 : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of U0 : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of U0 : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of U0 : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of U0 : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of U0 : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of U0 : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of U0 : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of U0 : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of U0 : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of U0 : label is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of U0 : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of U0 : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of U0 : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of U0 : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of U0 : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of U0 : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of U0 : label is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of U0 : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of U0 : label is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of U0 : label is 12;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of U0 : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of U0 : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of U0 : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of U0 : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of U0 : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of U0 : label is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
debug_axi_chan_in(0) => NLW_U0_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_U0_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_U0_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_U0_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_U0_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_U0_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_U0_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_U0_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_U0_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_U0_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_U0_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0),
m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_U0_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_U0_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_U0_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_U0_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 0) => s_axis_phase_tdata(23 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
| gpl-3.0 | 5b89c61df8d39ce6d0cc85e85636cc4e | 0.91287 | 1.94799 | false | false | false | false |
Hyvok/HardHeat | sim/temp_controller/temp_controller_tb.vhd | 1 | 2,372 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity temp_controller_tb is
end entity;
architecture rtl of temp_controller_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
constant MICROSECOND_D : natural := 100;
signal clk : std_logic := '0';
signal reset : std_logic;
signal enable : std_logic;
signal ow_in : std_logic;
signal ow_out : std_logic;
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
signal temp_out_f : std_logic;
begin
reset <= '1', '0' after 500 ns;
enable <= '1';
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
DUT_inst: entity work.temp_controller(rtl)
generic map
(
CONV_D => 1000000,
CONV_CMD_D => 100000,
OW_US_D => MICROSECOND_D,
PWM_N => 12,
PWM_MIN_LVL => 2**12 / 4,
PWM_EN_ON_D => 100,
P_SHIFT_N => 4,
I_SHIFT_N => -11,
TEMP_SETPOINT => 320
)
port map
(
clk => clk,
reset => reset,
ow_in => ow_in,
ow_out => ow_out,
enable_in => '1',
temp_out_f => temp_out_f
);
data_gen_p: entity work.ds18b20_data_gen(rtl)
generic map
(
MICROSECOND_D => MICROSECOND_D
)
port map
(
clk => clk,
reset => reset,
ow_in => ow_in,
temp_in => temp,
temp_in_f => temp_f,
ow_out => ow_out
);
temp_gen: process(clk, reset)
variable cur_temp : signed(16 - 1 downto 0);
begin
if reset = '1' then
cur_temp := to_signed(320, temp'length);
temp <= cur_temp;
temp_f <= '0';
elsif rising_edge(clk) then
temp_f <= '0';
if temp_out_f = '1' then
cur_temp := cur_temp + 16;
temp <= cur_temp;
temp_f <= '1';
end if;
end if;
end process;
end;
| mit | 0c3b47f2af09a3a5f0d842b4b43be76c | 0.430438 | 3.753165 | false | false | false | false |
thequbit/af_paper | code/xilinx/pixel_difference_1d.vhd | 1 | 1,935 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pixel_difference_1d is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_R : in STD_LOGIC_VECTOR (7 downto 0);
i_G : in STD_LOGIC_VECTOR (7 downto 0);
i_B : in STD_LOGIC_VECTOR (7 downto 0);
i_framevalid : in STD_LOGIC;
i_linevalid : in STD_LOGIC;
o_focusvalue : out STD_LOGIC_VECTOR(15 downto 0);
o_dv : out STD_LOGIC
);
end pixel_difference_1d;
architecture Behavioral of pixel_difference_1d is
COMPONENT color_space_converter
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_R : IN std_logic_vector(7 downto 0);
i_G : IN std_logic_vector(7 downto 0);
i_B : IN std_logic_vector(7 downto 0);
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
o_Y : OUT std_logic_vector(7 downto 0);
o_framevalid : OUT std_logic;
o_linevalid : OUT std_logic
);
END COMPONENT;
COMPONENT focus_calculation_pixel_difference_1d
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
i_Y : IN std_logic_vector(7 downto 0);
o_focusvalue : OUT std_logic_vector(15 downto 0);
o_dv : OUT std_logic
);
END COMPONENT;
signal s_framevalid : STD_LOGIC;
signal s_linevalid : STD_LOGIC;
signal s_Y : STD_LOGIC_VECTOR(7 downto 0);
begin
Inst_color_space_converter: color_space_converter PORT MAP(
i_clk => i_clk,
i_reset => i_reset,
i_R => i_R,
i_G => i_G,
i_B => i_B,
i_framevalid => i_framevalid,
i_linevalid => i_linevalid,
o_Y => s_Y,
o_framevalid => s_framevalid,
o_linevalid => s_linevalid
);
Inst_focus_calculation: focus_calculation_pixel_difference_1d PORT MAP(
i_clk => i_clk,
i_reset => i_reset,
i_framevalid => s_framevalid,
i_linevalid => s_linevalid,
i_Y => s_Y,
o_focusvalue => o_focusvalue,
o_dv => o_dv
);
end Behavioral;
| gpl-3.0 | a4c9dd19e285497326bcf6364e6a9ea3 | 0.62739 | 2.764286 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/main_sm.vhd | 2 | 9,486 | ----------------------------------------------------------------------------------
--This is the main state machine of the serdes FPGA
--it generates the appropriate command
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity main_sm is
port(
clk_spi : in std_logic;
reset : in std_logic;
miso_reg : in std_logic_vector(15 downto 0);
data_lclkin : in std_logic; --this the signal that signal's end of a SPI command.
spi_start_o : out std_logic;
command_o : out std_logic_vector(15 downto 0);
hsync_o : out std_logic
);
end main_sm;
architecture Behavioral of main_sm is
--state machine
type master_sm_type is (IDLE, REGCONF, ADCCONF, ACQ);
signal master_sm, master_sm_next : master_sm_type;
type hsync_sm_type is (IDLE, CH0);
signal hsync_state, hsync_state_next : hsync_sm_type;
--signals
signal sm_cnt, sm_cnt_next : unsigned(5 downto 0);
signal cmd, cmd_next : std_logic_vector(15 downto 0);
signal cmd_d1, cmd_d2 : std_logic_vector(7 downto 0); --this is the delay version of command. currently only use for checking the configurations
signal spi_start, spi_start_next : std_logic;
signal verify_cnt, verify_cnt_next : unsigned(5 downto 0);
signal hsync_cnt, hsync_cnt_next : unsigned(4 downto 0);
signal hsync, hsync_next : std_logic;
--a bank of all the configuration values
type rom_type is array ( 0 to 21) of std_logic_vector(7 downto 0);
type dummyrom_type is array (0 to 3) of std_logic_vector(15 downto 0);
constant CONVERT: std_logic_vector(1 downto 0) := "00";
constant CALIB: std_logic_vector(15 downto 0) := "0101010100000000";
constant CLEAR: std_logic_vector(15 downto 0) := "0110101000000000";
constant WRITEREG: std_logic_vector(1 downto 0) := "10";
constant READREG: std_logic_vector(1 downto 0) := "11";
constant NO_CONF_REG : integer := 21; --17 for 32 channel
constant DUMMY_ROM : dummyrom_type := (
"11" & std_logic_vector(to_unsigned(40,6)) & "00000000",
"11" & std_logic_vector(to_unsigned(41,6)) & "00000000",
"11" & std_logic_vector(to_unsigned(42,6)) & "00000000",
"11" & std_logic_vector(to_unsigned(43,6)) & "00000000"
);
--generate command
--command <= "11" & std_logic_vector(to_unsigned(41,6)) & "00000000"; --read from 40 to 44 registers
--configuration sequence
-- 7654 3210
--R0 0x80DE "1101 1110"
--R1 0x8102 "0000 0010" -ADC buffer bias, 2 for >700 KS/s sampling rate.
--R2 0x8204 "0000 0100" -MUX bias 4 for >700 KS/s sampling rate
--R3 0x8302 "0000 0010" -digital out HiZ
--R4 0x845F "0101 1111" -MISO pull to highZ when CS is pulled high. twocomp. no absmode, DSP offset remove, k_freq = 0.000004857Hz
--R5 0x8500 "0000 0000" -disable impedance check
--R6 0x8600 "0000 0000" -disable impedance check DAC
--R7 0x8700 "0000 0000" -disable impedance check amplifier
--R8 0x8811 "0001 0001" -RH1 DAC1: 17 upper cutoff 10KHz
--R9 0x8980 "1000 0000" -RH1 DAC2: 0
--R10 0x8A10 "0001 0000" -RH2 DAC1: 16
--R11 0x8B80 "1000 0000" -RH2 DAC2: 0
--R12 0x8C10 "0001 0000" -RL DAC1
--R13 0x8DDC "1101 1100" -RL DAC2:28 DAC3:1 cutoff: 0.1HZ??????????????????????? confirm
--R14 0x8EFF "1111 1111"
--R15 0x8FFF "1111 1111"
--R16 0x90FF "1111 1111"
--R17 0x91FF "1111 1111"
--for 64 channels
--R18 0x8EFF "1111 1111"
--R19 0x8FFF "1111 1111"
--R20 0x90FF "1111 1111"
--R21 0x91FF "1111 1111"
constant CONFIG_ROM : rom_type := (
-- 76543210
"11011110", --0x80DE
"00000010", --0x8102
"00000100", --0x8204
"00000010", --0x8302
"00011111", --0x845F
"00000000", --0x8500
"00000000", --0x8600
"00000000", --0x8700
"00010001", --0x8811
"10000000", --0x8980
"00010000", --0x8A10
"10000000", --0x8B80
"00010000", --0x8C10
"11011100", --0x8DDC
"11111111", --0x8EFF
"11111111", --0x8FFF
"11111111", --0x90FF
"11111111",
"11111111", --0x8EFF
"11111111", --0x8FFF
"11111111", --0x90FF
"11111111"); --0x91FF
begin
--signal mapping
command_o <= cmd;
spi_start_o <= spi_start;
hsync_o <= hsync;
--delay the cmd output with data_lclk
delay_cmd_prc : process(data_lclkin, clk_spi, reset, cmd_d1)
begin
if (reset = '1') then
cmd_d1 <= (others=>'0');
cmd_d2 <= (others=>'0');
elsif (rising_edge(clk_spi)) then
if data_lclkin = '1' then
cmd_d1 <= cmd(7 downto 0);
cmd_d2 <= cmd_d1;
else
cmd_d1 <= cmd_d1;
cmd_d2 <= cmd_d2;
end if;
end if;
end process;
--Main state machine
main_proc: process(clk_spi, reset)
begin
if (reset = '1') then
master_sm <= IDLE;
sm_cnt <= (others=>'0');
cmd <= (others=>'0');
verify_cnt <= (others=>'0');
spi_start <= '0';
elsif (rising_edge(clk_spi)) then --next state logic
master_sm <= master_sm_next;
sm_cnt <= sm_cnt_next;
cmd <= cmd_next;
verify_cnt <= verify_cnt_next;
spi_start <= spi_start_next;
end if;
end process;
--next state logic
main_proc_next: process(data_lclkin, sm_cnt, master_sm, cmd, cmd_d2, miso_reg, verify_cnt)
begin
case master_sm is
when IDLE =>
master_sm_next <= REGCONF;
spi_start_next <= '1';
sm_cnt_next <= sm_cnt + 1;
cmd_next <= WRITEREG & std_logic_vector(sm_cnt) & CONFIG_ROM(to_integer(sm_cnt));
verify_cnt_next <= (others=>'0');
when REGCONF => --go through all the configuration registers (generate command, and spi_start signal, look for data_lclkin before moving to the next state)
if data_lclkin = '1' then
if sm_cnt <= 2 then
sm_cnt_next <= sm_cnt + 1;
master_sm_next <= REGCONF;
cmd_next <= WRITEREG & std_logic_vector(sm_cnt) & CONFIG_ROM(to_integer(sm_cnt));
verify_cnt_next <= verify_cnt;
spi_start_next <= '1';
elsif sm_cnt <= NO_CONF_REG and sm_cnt > 2 then
sm_cnt_next <= sm_cnt + 1;
master_sm_next <= REGCONF;
cmd_next <= WRITEREG & std_logic_vector(sm_cnt) & CONFIG_ROM(to_integer(sm_cnt));
if miso_reg(7 downto 0) = cmd_d2(7 downto 0) then
verify_cnt_next <= verify_cnt + 1;
else
verify_cnt_next <= verify_cnt;
end if;
spi_start_next <= '1';
elsif sm_cnt > NO_CONF_REG and sm_cnt <= (NO_CONF_REG + 3) then --this is the last of the verification period
sm_cnt_next <= sm_cnt + 1;
master_sm_next <= REGCONF;
cmd_next <= (others=>'0');
if miso_reg(7 downto 0) = cmd_d2(7 downto 0) then
verify_cnt_next <= verify_cnt + 1;
else
verify_cnt_next <= verify_cnt;
end if;
spi_start_next <= '1';
else --when sm_cnt > 20
if verify_cnt = 22 then
master_sm_next <= ADCCONF;
sm_cnt_next <= (others=>'0');
spi_start_next <= '1';
cmd_next <= CALIB; --initiate the calibration command
else --otherwise stuck in REGCONF
master_sm_next <= REGCONF; --debug change
sm_cnt_next <= sm_cnt;
spi_start_next <= '0';
cmd_next <= (others=>'0');
end if;
verify_cnt_next <= verify_cnt;
end if;
else
sm_cnt_next <= sm_cnt;
spi_start_next <= '0';
master_sm_next <= master_sm;
cmd_next <= cmd;
verify_cnt_next <= verify_cnt;
end if;
when ADCCONF =>
if data_lclkin = '1' then
if sm_cnt <= 50 then --9
sm_cnt_next <= sm_cnt + 1;
master_sm_next <= ADCCONF;
cmd_next <= DUMMY_ROM(0);
else
sm_cnt_next <= (others=>'0');
master_sm_next <= ACQ;
cmd_next <= cmd;
end if;
spi_start_next <= '1';
else
sm_cnt_next <= sm_cnt;
spi_start_next <= '0'; --debug
master_sm_next <= master_sm;
cmd_next <= cmd;
end if;
verify_cnt_next <= verify_cnt;
when ACQ =>
if data_lclkin = '1' then
if sm_cnt >= 34 then --reset channel count back to 0
sm_cnt_next <= (others=>'0');
else
sm_cnt_next <= sm_cnt + 1;
end if;
cmd_next <= "00" & std_logic_vector(sm_cnt) & "00000000";
--cmd_next <= "11" & std_logic_vector(to_unsigned(59,6)) & "00000000"; --read from 40 to 44 registers --read for INTAN
spi_start_next <= '1';
else
sm_cnt_next <= sm_cnt;
spi_start_next <= '0';
cmd_next <= cmd;
end if;
master_sm_next <= ACQ;
verify_cnt_next <= verify_cnt;
end case;
end process;
--one shot hsync for channel 0
one_shot_hsync : process(clk_spi, reset)
begin
if (reset = '1') then
hsync_state <= IDLE;
hsync_cnt <= (others=>'0');
hsync <= '0';
elsif (rising_edge(clk_spi)) then
hsync_state <= hsync_state_next;
hsync_cnt <= hsync_cnt_next;
hsync <= hsync_next;
end if;
end process;
--hsync
one_shot_next_proc : process(master_sm, hsync_state, sm_cnt, hsync_cnt, data_lclkin)
begin
case hsync_state is
when IDLE =>
if master_sm = ACQ and sm_cnt = 1 and data_lclkin = '1' then
--go to the CH0 state
hsync_state_next <= CH0;
hsync_next <= '1';
else
hsync_state_next <= IDLE ;
hsync_next <= '0';
end if;
hsync_cnt_next <= (others=>'0');
when CH0 =>
if hsync_cnt >= 10 then
hsync_state_next <= IDLE;
hsync_cnt_next <= (others=>'0');
hsync_next <= '0';
else
hsync_state_next <= CH0;
hsync_cnt_next <= hsync_cnt + 1;
hsync_next <= '1';
end if;
end case;
end process;
end Behavioral;
| mit | 843c65ca453e6b7589f42fb1b5b75ce6 | 0.589817 | 2.871935 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/SPI_module.vhd | 2 | 6,748 | ----------------------------------------------------------------------------------
--This is a SPI module that takes a parallel command and stream to SPI outputs
----------------------------------------------------------------------------------
library IEEE;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
entity SPI_module is
port(
clk_spi : in std_logic; --spi clock from toplevel
reset : in std_logic; --reset
spi_start : in std_logic; --spi initiate
command_in : in std_logic_vector(15 downto 0); --parallel command input vector
--SPI inputs
miso_i : in std_logic;
--SPI outputs
cs_o : out std_logic;
sclk_o : out std_logic; --sclk is always 2x slower than clk_spi
mosi_o : out std_logic;
--data latch clock
data_lclk_o : out std_logic;
--data clock
data_rdy_pcie_o : out std_logic;
data_pcie_A_o : out std_logic_vector(15 downto 0);
data_pcie_B_o : out std_logic_vector(15 downto 0);
miso_reg_A_o : out std_logic_vector(15 downto 0);
miso_reg_B_o : out std_logic_vector(15 downto 0)
);
end SPI_module;
architecture Behavioral of SPI_module is
signal cs, cs_next, sclk, sclk_next : std_logic;
signal miso_reg_A, miso_reg_A_next : std_logic_vector(15 downto 0);
signal miso_reg_B, miso_reg_B_next : std_logic_vector(15 downto 0);
signal sm_cnt, sm_cnt_next : unsigned(4 downto 0); --max count is (41-34) = 12
signal cmd_reg, cmd_reg_next : std_logic_vector(15 downto 0);
type spi_states is (IDLE, IDLExN, OP_lo, OP_hi, DATARDY); --state machine definition
signal spi_sm, spi_sm_next : spi_states;
signal data_lclk, data_lclk_next : std_logic;
signal data_rdy_pcie, data_rdy_pcie_next : std_logic;
signal data_pcie_A, data_pcie_A_next : std_logic_vector(15 downto 0);
signal data_pcie_B, data_pcie_B_next : std_logic_vector(15 downto 0);
constant test_miso: std_logic_vector(0 to 15) := "0100000000000000";
begin
--signal mapping
cs_o <= cs;
sclk_o <= sclk;
mosi_o <= cmd_reg(15); --comd_reg is a shift register so bit 15 goes to MOSI output
data_lclk_o <= data_lclk;
data_rdy_pcie_o <= data_rdy_pcie;
data_pcie_A_o <= data_pcie_A;
data_pcie_B_o <= data_pcie_B;
miso_reg_A_o <= miso_reg_A;
miso_reg_B_o <= miso_reg_B;
--SPI state machine
SPI_proc: process(clk_spi, reset)
begin
if (reset = '1') then
cs <= '0';
sclk <= '0';
data_lclk <= '0';
miso_reg_A <= (others=>'0');
miso_reg_B <= (others=>'0');
spi_sm <= IDLE;
cmd_reg <= (others=>'0');
sm_cnt <= (others=>'0'); --sm counter
data_rdy_pcie <= '0';
data_pcie_A <= (others=>'0');
data_pcie_B <= (others=>'0');
elsif (falling_edge(clk_spi)) then --next state logic
cs <= cs_next;
sclk <= sclk_next;
data_lclk <= data_lclk_next;
miso_reg_A <= miso_reg_A_next;
miso_reg_B <= miso_reg_B_next;
spi_sm <= spi_sm_next;
cmd_reg <= cmd_reg_next;
sm_cnt <= sm_cnt_next;
data_rdy_pcie <= data_rdy_pcie_next;
data_pcie_A <= data_pcie_A_next;
data_pcie_B <= data_pcie_B_next;
end if;
end process;
--state machine next state===============================
--on the SPI output side:
--it toggles between OP_lo and OP_hi state until sm_cnt reaches 16 counts then it goes to the DATARDY state.
--The DATARDY state toggles the data clock high, which means the data is ready to be latched. Then it goes back to
--IDLE state to wait for next spi_start signal
--on the SPI input side:
--MISO shifts the incoming bits into a miso shift register
SPI_proc_next: process(SPI_sm, sclk, sm_cnt, cmd_reg, miso_reg_b, data_pcie_b, spi_start, miso_reg_A, command_in, miso_i, data_pcie_A)
begin
case SPI_sm is
when IDLE =>
if spi_start = '1' then
cmd_reg_next <= command_in;
spi_sm_next <= IDLExN;
data_rdy_pcie_next <= '1';
else
cmd_reg_next <= cmd_reg;
spi_sm_next <= IDLE;
data_rdy_pcie_next <= '0';
end if;
cs_next <= '1';
sclk_next <= '0';
sm_cnt_next <= (others=>'0'); --state counter
data_lclk_next <= '0'; --data clock is always '0' unless it is in data_ready state;
miso_reg_A_next <= miso_reg_A; --maintain the last miso values, do not reset
miso_reg_B_next <= miso_reg_B;
data_pcie_A_next <= data_pcie_A;
data_pcie_B_next <= miso_reg_B;
when IDLExN => --loop in here for 24 cycles
if sm_cnt >= 8 then
spi_sm_next <= OP_lo;
cs_next <= '0';
sclk_next <= '0';
sm_cnt_next <= (others=>'0');
miso_reg_A_next <= (others=>'0'); --maintain the last miso values, do not reset
miso_reg_B_next <= (others=>'0');
else
spi_sm_next <= IDLExN;
cs_next <= '1';
sclk_next <= '0';
sm_cnt_next <= sm_cnt + 1;
miso_reg_A_next <= miso_reg_A; --maintain the last miso values, do not reset
miso_reg_B_next <= miso_reg_B;
end if;
cmd_reg_next <= cmd_reg;
data_lclk_next <= '0'; --data clock is always '0' unless it is in data_ready state;
data_rdy_pcie_next <= '1';
data_pcie_A_next <= data_pcie_A;
data_pcie_B_next <= data_pcie_B;
when OP_lo =>
cmd_reg_next <= cmd_reg;
spi_sm_next <= OP_hi;
sclk_next <= not sclk; --toggle sclk
cs_next <= '0';
sm_cnt_next <= sm_cnt;
data_lclk_next <= '0';
data_rdy_pcie_next <= '0';
miso_reg_A_next <= miso_reg_A;
-------------------------------
if sm_cnt = 0 then
miso_reg_B_next <= miso_reg_B;
else
miso_reg_B_next <= miso_reg_B(14 downto 0) & miso_i;
end if;
-------------------------------
data_pcie_A_next <= data_pcie_A;
data_pcie_B_next <= data_pcie_B;
when OP_hi =>
if sm_cnt>=15 then --state counter triggers at 15
spi_sm_next <= DATARDY;
sm_cnt_next <= sm_cnt;
else
spi_sm_next <= OP_lo;
sm_cnt_next <= sm_cnt + 1; --sm counter increment
end if;
cmd_reg_next(15 downto 1) <= cmd_reg(14 downto 0); --shift the command out
cmd_reg_next(0) <= '0'; --pad '0';
sclk_next <= not sclk; --toggle sclk
cs_next <= '0';
data_lclk_next <= '0';
data_rdy_pcie_next <= '0';
miso_reg_A_next <= miso_reg_A(14 downto 0) & miso_i;
data_pcie_A_next <= data_pcie_A;
miso_reg_B_next <= miso_reg_B;
data_pcie_B_next <= data_pcie_B;
when DATARDY =>
spi_sm_next <= IDLE;
sm_cnt_next <= sm_cnt;
cmd_reg_next <= cmd_reg;
sclk_next <= '0';
cs_next <= '1';
data_lclk_next <= '1';
data_rdy_pcie_next <= '0';
miso_reg_A_next <= miso_reg_A;
data_pcie_A_next <= miso_reg_A;
--miso_reg_B_next <= miso_reg_B;
miso_reg_B_next <= miso_reg_B(14 downto 0) & miso_i;
data_pcie_B_next <= data_pcie_B;
end case;
end process;
end Behavioral;
| mit | f52201efa57396ed8a7c35d07b426a11 | 0.575282 | 2.793046 | false | false | false | false |
sudov/options-accel | final_design/fifo.prj/sol/syn/vhdl/dut.vhd | 2 | 11,938 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dut is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
in_fifo_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
in_fifo_V_empty_n : IN STD_LOGIC;
in_fifo_V_read : OUT STD_LOGIC;
out_fifo_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
out_fifo_V_full_n : IN STD_LOGIC;
out_fifo_V_write : OUT STD_LOGIC );
end;
architecture behav of dut is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"dut,hls_ip_2014_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.789000,HLS_SYN_LAT=12,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (3 downto 0) := "1010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (3 downto 0) := "1011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (3 downto 0) := "1100";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
signal tmp_3_reg_119 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal tmp_6_reg_124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_reg_129 : STD_LOGIC_VECTOR (31 downto 0);
signal full_fu_66_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal full_reg_134 : STD_LOGIC_VECTOR (63 downto 0);
signal full_1_fu_83_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal full_1_reg_139 : STD_LOGIC_VECTOR (63 downto 0);
signal data1_reg_154 : STD_LOGIC_VECTOR (31 downto 0);
signal data2_fu_111_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal data2_reg_159 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_fu_115_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_52_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_52_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_56_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal full_fu_66_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_6_reg_124_temp: signed (32-1 downto 0);
signal tmp_s_fu_72_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal full_1_fu_83_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal in_fifo_V_dout_temp: signed (32-1 downto 0);
signal grp_fu_52_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ret_fu_97_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_52_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
component dut_dmul_64ns_64ns_64_6_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
begin
dut_dmul_64ns_64ns_64_6_max_dsp_U1 : component dut_dmul_64ns_64ns_64_6_max_dsp
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_52_p0,
din1 => grp_fu_52_p1,
ce => grp_fu_52_ce,
dout => grp_fu_52_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st11_fsm_10 = ap_CS_fsm)) then
data1_reg_154 <= ret_fu_97_p1(63 downto 32);
data2_reg_159 <= data2_fu_111_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st5_fsm_4 = ap_CS_fsm))) then
full_1_reg_139 <= full_1_fu_83_p2;
full_reg_134 <= full_fu_66_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((in_fifo_V_empty_n = ap_const_logic_0)))) then
tmp_3_reg_119 <= in_fifo_V_dout;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st3_fsm_2 = ap_CS_fsm))) then
tmp_6_reg_124 <= in_fifo_V_dout;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm))) then
tmp_7_reg_129 <= in_fifo_V_dout;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (in_fifo_V_empty_n, out_fifo_V_full_n, ap_CS_fsm)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st5_fsm_4;
else
ap_NS_fsm <= ap_ST_st4_fsm_3;
end if;
when ap_ST_st5_fsm_4 =>
if (not((in_fifo_V_empty_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
if (not((out_fifo_V_full_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st13_fsm_12;
else
ap_NS_fsm <= ap_ST_st12_fsm_11;
end if;
when ap_ST_st13_fsm_12 =>
if (not((out_fifo_V_full_n = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
data2_fu_111_p1 <= ret_fu_97_p1(16 - 1 downto 0);
in_fifo_V_dout_temp <= signed(in_fifo_V_dout);
full_1_fu_83_p1 <= std_logic_vector(resize(in_fifo_V_dout_temp,64));
full_1_fu_83_p2 <= std_logic_vector(unsigned(tmp_s_fu_72_p3) + unsigned(full_1_fu_83_p1));
tmp_6_reg_124_temp <= signed(tmp_6_reg_124);
full_fu_66_p1 <= std_logic_vector(resize(tmp_6_reg_124_temp,64));
full_fu_66_p2 <= std_logic_vector(unsigned(tmp_4_fu_56_p3) + unsigned(full_fu_66_p1));
grp_fu_52_ce <= ap_const_logic_1;
grp_fu_52_p0 <= full_reg_134;
grp_fu_52_p1 <= full_1_reg_139;
-- in_fifo_V_read assign process. --
in_fifo_V_read_assign_proc : process(in_fifo_V_empty_n, ap_CS_fsm)
begin
if ((((ap_ST_st2_fsm_1 = ap_CS_fsm) and not((in_fifo_V_empty_n = ap_const_logic_0))) or (not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st3_fsm_2 = ap_CS_fsm)) or (not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st4_fsm_3 = ap_CS_fsm)) or (not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st5_fsm_4 = ap_CS_fsm)) or (not((in_fifo_V_empty_n = ap_const_logic_0)) and (ap_ST_st1_fsm_0 = ap_CS_fsm)))) then
in_fifo_V_read <= ap_const_logic_1;
else
in_fifo_V_read <= ap_const_logic_0;
end if;
end process;
-- out_fifo_V_din assign process. --
out_fifo_V_din_assign_proc : process(out_fifo_V_full_n, ap_CS_fsm, data1_reg_154, tmp_2_fu_115_p1)
begin
if (not((out_fifo_V_full_n = ap_const_logic_0))) then
if ((ap_ST_st13_fsm_12 = ap_CS_fsm)) then
out_fifo_V_din <= tmp_2_fu_115_p1;
elsif ((ap_ST_st12_fsm_11 = ap_CS_fsm)) then
out_fifo_V_din <= data1_reg_154;
else
out_fifo_V_din <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
out_fifo_V_din <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- out_fifo_V_write assign process. --
out_fifo_V_write_assign_proc : process(out_fifo_V_full_n, ap_CS_fsm)
begin
if ((((ap_ST_st12_fsm_11 = ap_CS_fsm) and not((out_fifo_V_full_n = ap_const_logic_0))) or (not((out_fifo_V_full_n = ap_const_logic_0)) and (ap_ST_st13_fsm_12 = ap_CS_fsm)))) then
out_fifo_V_write <= ap_const_logic_1;
else
out_fifo_V_write <= ap_const_logic_0;
end if;
end process;
ret_fu_97_p1 <= grp_fu_52_p2;
tmp_2_fu_115_p1 <= std_logic_vector(resize(unsigned(data2_reg_159),32));
tmp_4_fu_56_p3 <= (tmp_3_reg_119 & ap_const_lv32_0);
tmp_s_fu_72_p3 <= (tmp_7_reg_129 & ap_const_lv32_0);
end behav;
| apache-2.0 | bba45e98ec32d9309ccb0be349b2cd0f | 0.539454 | 2.885666 | false | false | false | false |
Hyvok/HardHeat | sim/deadtime_gen/deadtime_gen_tb.vhd | 1 | 1,513 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deadtime_gen_tb is
generic
(
TUNING_WORD_N : positive := 22
);
end entity;
architecture rtl of deadtime_gen_tb is
constant CLK_PERIOD : time := 1 sec / 20e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal sig : std_logic;
signal tuning_word : unsigned(TUNING_WORD_N - 1 downto 0);
begin
DUT_inst: entity work.deadtime_gen(rtl)
generic map
(
DT_N => 16,
DT_VAL => 100
)
port map
(
clk => clk,
reset => reset,
sig_in => sig
);
sig_gen_p: entity work.phase_accumulator(rtl)
generic map
(
ACCUM_BITS_N => 32,
TUNING_WORD_N => TUNING_WORD_N
)
port map
(
clk => clk,
reset => reset,
tuning_word_in => tuning_word,
sig_out => sig
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
tuning_word_gen: process(clk)
begin
if reset = '1' then
tuning_word <= to_unsigned(2**TUNING_WORD_N / 2 - 1, TUNING_WORD_N);
elsif rising_edge(clk) then
tuning_word <= tuning_word - 1;
end if;
end process;
end;
| mit | ae19b7bd50c4501df5f83602a2b66106 | 0.477198 | 3.708333 | false | false | false | false |
thequbit/af_paper | code/xilinx/focus_calculation_pixel_difference_2d_tb.vhd | 1 | 4,515 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:07:45 05/01/2014
-- Design Name:
-- Module Name: C:/dev/af_paper/ise/af_alogithms/focus_calculation_pixel_difference_2d_tb.vhd
-- Project Name: af_alogithms
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: focus_calculation_pixel_difference_2d
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY focus_calculation_pixel_difference_2d_tb IS
END focus_calculation_pixel_difference_2d_tb;
ARCHITECTURE behavior OF focus_calculation_pixel_difference_2d_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT focus_calculation_pixel_difference_2d
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
i_Y : IN std_logic_vector(7 downto 0);
o_focusvalue : OUT std_logic_vector(31 downto 0);
o_dv : OUT std_logic
);
END COMPONENT;
--Inputs
signal i_clk : std_logic := '0';
signal i_reset : std_logic := '0';
signal i_framevalid : std_logic := '0';
signal i_linevalid : std_logic := '0';
signal i_Y : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal o_focusvalue : std_logic_vector(31 downto 0);
signal o_dv : std_logic;
-- Clock period definitions
constant i_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: focus_calculation_pixel_difference_2d PORT MAP (
i_clk => i_clk,
i_reset => i_reset,
i_framevalid => i_framevalid,
i_linevalid => i_linevalid,
i_Y => i_Y,
o_focusvalue => o_focusvalue,
o_dv => o_dv
);
-- Clock process definitions
i_clk_process :process
begin
i_clk <= '0';
wait for i_clk_period/2;
i_clk <= '1';
wait for i_clk_period/2;
i_Y <= i_Y + '1';
end process;
--
-- images are 865 x 577
--
-- 128 x 128 is ROI
--
-- ( 865 - 128 ) / 2 = 268
-- ( 577 - 128 ) / 2 = 224
--
-- 224 * 865 top buffer
--
-- 268 left buffer -|
-- 128 line data | - x 128 lines
-- 268 right buffer _|
--
-- 224 * 865 bottom buffer
process
variable x : integer range 0 to 1024 := 0;
variable y : integer range 0 to 1024 := 0;
begin
i_framevalid <= '0';
i_linevalid <= '0';
-- equivilent of 2 lines of invalid frame
wait for i_clk_period*865*2;
i_framevalid <= '1';
i_linevalid <= '0';
-- one line invalid in beginning of frame
for y in 0 to 1 loop
for x in 0 to 577 loop
i_framevalid <= '1';
i_linevalid <= '0';
wait for i_clk_period;
end loop;
end loop;
-- one line invalid in beginning of frame
for y in 0 to 577 loop
-- ten pixels at beginning of line invalid
for x in 0 to 10 loop
i_framevalid <= '1';
i_linevalid <= '0';
wait for i_clk_period;
end loop;
-- 865 valid pixels
for x in 0 to 865 loop
i_framevalid <= '1';
i_linevalid <= '1';
wait for i_clk_period;
end loop;
-- ten pixels at end of line invalid
for x in 0 to 10 loop
i_framevalid <= '1';
i_linevalid <= '0';
wait for i_clk_period;
end loop;
end loop;
-- one line invalid at end of frame
for y in 0 to 1 loop
for x in 0 to 577 loop
i_framevalid <= '1';
i_linevalid <= '0';
wait for i_clk_period;
end loop;
end loop;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--wait for 100 ns;
i_reset <= '1';
wait for i_clk_period*10;
i_reset <= '0';
wait;
end process;
END;
| gpl-3.0 | 25723c69650dd8c0234fa0d84fd1e3bc | 0.585604 | 3.339497 | false | false | false | false |
upci/upci | Simulações/testes_memoria/processor_functions.vhd | 1 | 1,325 | LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
PACKAGE processor_functions IS
TYPE opcode IS (load, store, add, nott, andd, orr, xorr, inc, sub, branch);
FUNCTION Decode (word: STD_LOGIC_VECTOR) RETURN opcode;
CONSTANT n: integer := 12;
CONSTANT wordlen: integer := 12;
CONSTANT oplen: integer := 4;
TYPE memory_array IS ARRAY (0 to 2**(n-oplen-1)) of STD_LOGIC_VECTOR(n-1 DOWNTO 0);
CONSTANT reg_zero: unsigned (n-1 DOWNTO 0) := (OTHERS => '0');
END PACKAGE processor_functions;
PACKAGE BODY processor_functions IS
FUNCTION Decode (word: STD_LOGIC_VECTOR) return opcode IS
VARIABLE opcode_out: opcode;
BEGIN
CASE word(n-1 DOWNTO n-oplen) IS
WHEN "0000" => opcode_out := load;
WHEN "0001" => opcode_out := store;
WHEN "0010" => opcode_out := add;
WHEN "0011" => opcode_out := nott;
WHEN "0100" => opcode_out := andd;
WHEN "0101" => opcode_out := orr;
WHEN "0110" => opcode_out := xorr;
WHEN "0111" => opcode_out := inc;
WHEN "1000" => opcode_out := sub;
WHEN "1001" => opcode_out := branch;
WHEN OTHERS => null;
END CASE;
RETURN opcode_out;
END FUNCTION decode;
END PACKAGE BODY processor_functions; | gpl-2.0 | c23569c8a7187cf269dbb462f8352462 | 0.593208 | 3.701117 | false | false | false | false |
makestuff/blinky | vhdl/top_level.vhdl | 1 | 1,673 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic (
-- This can be overridden to change the refresh rate. The anode pattern will change at a
-- frequency given by F(clk_in) / (2**COUNTER_WIDTH). So for a 50MHz clk_in and
-- COUNTER_WIDTH=18, the anode pattern changes at ~191Hz, which means each digit gets
-- refreshed at ~48Hz.
COUNTER_WIDTH : integer := 27
);
port(
sysClk_in : in std_logic;
led_out : out std_logic_vector(1 downto 0)
);
end entity;
architecture rtl of top_level is
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
begin
-- Infer registers
process(sysClk_in)
begin
if ( rising_edge(sysClk_in) ) then
count <= count_next;
end if;
end process;
count_next <= count + 1;
led_out <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
end architecture;
| lgpl-3.0 | d38066d9a6835e5d1755c6113774c83b | 0.714286 | 3.456612 | false | false | false | false |
Hyvok/HardHeat | sim/pwr_sequencer/pwr_sequencer_tb.vhd | 1 | 3,166 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwr_sequencer_tb is
generic
(
LEVELS_N : natural := 3;
TEST_D : natural := 10000
);
end entity;
architecture rtl of pwr_sequencer_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal main_pwr_en : std_logic;
signal main_pwr_fail : std_logic;
signal start : std_logic;
signal fail : std_logic_vector(LEVELS_N - 1 downto 0);
signal enable : std_logic_vector(LEVELS_N - 1 downto 0);
begin
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
DUT_inst: entity work.pwr_sequencer(rtl)
generic map
(
LEVELS_N => LEVELS_N
)
port map
(
clk => clk,
reset => reset,
start_in => start,
fail_in => fail,
en_out => enable,
main_pwr_en_out => main_pwr_en,
main_pwr_fail_out => main_pwr_fail
);
fail_gen: process(clk, reset)
type state_t is (idle, delay, power_on, cause_fail);
variable state : state_t;
variable timer : natural;
variable cur_level : natural;
begin
if reset = '1' then
state := idle;
timer := 0;
fail <= (others => '1');
cur_level := 0;
start <= '0';
elsif rising_edge(clk) then
if state = idle then
start <= '1';
for i in 0 to enable'high loop
if enable(i) = '1' then
cur_level := i;
state := delay;
end if;
end loop;
elsif state = delay then
timer := timer + 1;
if timer > TEST_D then
fail(cur_level) <= '0';
timer := 0;
if cur_level = enable'high then
state := power_on;
else
state := idle;
end if;
end if;
elsif state = power_on then
timer := timer + 1;
-- After succesfull sequencing cause a failure
if timer > TEST_D then
fail(0) <= '1';
timer := 0;
state := cause_fail;
end if;
elsif state = cause_fail then
timer := timer + 1;
start <= '0';
-- After succesfull power failure, restart
if timer > TEST_D then
start <= '1';
fail <= (others => '1');
timer := 0;
state := idle;
end if;
end if;
end if;
end process;
end;
| mit | 862b9d11cba035ad2f7c59ca6d438b46 | 0.41693 | 4.440393 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/qei.vhd | 1 | 10,555 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
-- c2003 Franks Development, LLC
-- http://www.franks-development.com
-- !This source is distributed under the terms & conditions specified at opencores.org
--resource or companion to this code:
-- Xilinx Application note 12 - "Quadrature Phase Decoder" - xapp012.pdf
-- no longer appears on xilinx website (to best of my knowledge), perhaps it has been superceeded?
--this code was origonally intended for use on Xilinx XPLA3 'coolrunner' CPLD devices
--origonally compiled/synthesized with Xilinx 'Webpack' 5.2 software
--How we 'talk' to the outside world:
entity QuadratureCounterPorts is
Port ( clock : in std_logic; --system clock, i.e. 10MHz oscillator
QuadA : in std_logic; --first input from quadrature device (i.e. optical disk encoder)
QuadB : in std_logic; --second input from quadrature device (i.e. optical disk encoder)
CounterValue : out std_logic_vector(15 downto 0) --just an example debuggin output
);
end entity;
--What we 'do':
architecture QuadratureCounter of QuadratureCounterPorts is
-- local 'variables' or 'registers'
--This is the counter for how many quadrature ticks have gone past.
--the size of this counter is dependant on how far you need to count
--it was origonally used with a circular disk encoder having 2048 ticks/revolution
--thus this 16-bit count could hold 2^15 ticks in either direction, or a total
--of 32768/2048 = 16 revolutions in either direction. if the disk
--was turned more than 16 times in a given direction, the counter overflows
--and the origonal location is lost. If you had a linear instead of
--circular encoder that physically could not move more than 2048 ticks,
--then Count would only need to be 11 downto 0, and you could count
--2048 ticks in either direction, regardless of the position of the
--encoder at system bootup.
signal Count : std_logic_vector(15 downto 0);
--this is the signal from the quadrature logic that it is time to change
--the value of the counter on this clock signal (either + or -)
signal CountEnable : std_logic;
--should we increment or decrement count?
signal CountDirection : std_logic;
--where all the 'work' is done: quadraturedecoder.vhd
component QuadratureDecoderPorts
Port (
clock : in std_logic;
QuadA : in std_logic;
QuadB : in std_logic;
Direction : out std_logic;
CountEnable : out std_logic
);
end component;
begin --architecture QuadratureCounter
--instanciate the decoder
iQuadratureDecoder: QuadratureDecoderPorts
port map (
clock => clock,
QuadA => QuadA,
QuadB => QuadB,
Direction => CountDirection,
CountEnable => CountEnable
);
-- do our actual work every clock cycle
process(clock)
begin
--keep track of the counter
if ( (clock'event) and (clock = '1') ) then
if (CountEnable = '1') then
if (CountDirection = '1') then Count <= Count + "0000000000000001"; end if;
if (CountDirection = '0') then Count <= Count - "0000000000000001"; end if;
end if;
end if; --clock'event
--!!!!!!!!!!!INSERT SOMETHING USEFULL HERE!!!!!!!!!!!
--This is where you do actual work based on the value of the counter
--for instance, I will just output the value of the counter
--led's on an output like this are very useful - you can see the top
--bits light when moved backwards from initial position (count goes negative)
CounterValue <= Count;
end process; --(clock)
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- c2003 Franks Development, LLC
-- http://www.franks-development.com
-- !This source is distributed under the terms & conditions specified at opencores.org
--How we 'talk' to the outside world:
entity QuadratureDecoderPorts is
port (
clock : in std_logic;
QuadA : in std_logic;
QuadB : in std_logic;
Direction : out std_logic;
CountEnable : out std_logic
);
end entity;
--What we 'do':
architecture QuadratureDecoder of QuadratureDecoderPorts is
--local 'variables' or 'registers'
--this runs our state machine: where are we in the decoding process?
--the following constants describe each state
--note that every possible state is not listed. the unused states
--are physically unreachable in a functioning quadratre device, given that the
--clock is fast enough to 'catch' each transition on the quadrature inputs
--LR means left-right, RL = left-right. Of course the two are reversed
--if the two quadratre inputs are switched.
signal state : std_logic_vector(3 downto 0);
constant Wait0 : std_logic_vector(3 downto 0) := "0000";
constant Wait1 : std_logic_vector(3 downto 0) := "0001";
constant Count0 : std_logic_vector(3 downto 0) := "0010";
constant Count1 : std_logic_vector(3 downto 0) := "0011";
constant LR1 : std_logic_vector(3 downto 0) := "1001";
constant LR2 : std_logic_vector(3 downto 0) := "1101";
constant LR3 : std_logic_vector(3 downto 0) := "0101";
constant RL1 : std_logic_vector(3 downto 0) := "0100";
constant RL2 : std_logic_vector(3 downto 0) := "1100";
constant RL3 : std_logic_vector(3 downto 0) := "1000";
--this is a temp where the two quadrature inputs are stored
signal Quad : std_logic_vector(1 downto 0);
--as a single quadrature count is made up of several states, and the decoder
--can remain in a given state indefinately (if the quadrature input
--device is not 'moving'), so we need these 'gate-ing' variables
--to keep us from counting on every clock when we sit idle in the
--'count' state; thusly, we just count on the first clock
--upon entering a 'count' state.
signal counted : std_logic;
signal counting : std_logic;
begin --architecture QuadratureDecoder
process (clock)
begin --(clock)
if ( (clock'event) and (clock = '1') ) then --every rising edge
--convert inputs from asynch to synch by assigning once on each rising edge of clock
Quad(0) <= QuadA;
Quad(1) <= QuadB;
--we are not going to be counting on this clock by default
CountEnable <= '0';
--we are not in a 'count' state
if (Counting = '0') then
Counted <= '0'; --haven't counted when not in count state
CountEnable <= '0'; --are not outputing a count either
end if;
--we are in a count state
if (Counting = '1') then
if (Counted = '1') then --note that this is covered by default, but is included for clarity.
CountEnable <= '0'; --already counted this one, don't output a count
end if;
if (Counted = '0') then --we haven't counted it already
Counted <= '1'; --make sure we dont count it again on next clock
CountEnable <= '1'; --output a count!
end if;
end if;
-- run our state machine
-- the state transitions are governed by the nature of reality -
-- vis-a-vis this is what quadratre is.
-- the '--?' are the physically un-reachable states.
-- note that it is imperative that the clock be at least (4 I recal)
-- times faster than the maximum transition rate on each quadratre
-- input, or else transitions will occur in between clocks, corrupting
-- the state of the decoder. Put differently, the quadratre device must
-- physically remain in each state for at least a single clock
-- or state changes will not be 'captured' and decoder output will be bogus.
-- which is substancially the case with any clock-based logic.
-- the difference is that a normal glitch is any change in input which
-- has duration less than a single clock, but in quadrature, as single
-- transition of the actual device cases 4 transitions in the state,
-- by design of the quadrature encoding process.
case state is
when Wait0 =>
if (Quad = "00") then state <= Wait0; end if;
if (Quad = "01") then state <= RL1; end if;
if (Quad = "10") then state <= LR1; end if;
if (Quad = "11") then state <= Wait0; end if; --?
Counting <= '0';
when Wait1 =>
if (Quad = "00") then state <= Wait0; end if;
if (Quad = "01") then state <= RL1; end if;
if (Quad = "10") then state <= LR1; end if;
if (Quad = "11") then state <= Wait0; end if; --?
Counting <= '0';
when Count0 =>
if (Quad = "00") then state <= Wait0; end if;
if (Quad = "01") then state <= RL1; end if;
if (Quad = "10") then state <= LR1; end if;
if (Quad = "11") then state <= Count0; end if; --?
Counting <= '1';
when Count1 =>
if (Quad = "00") then state <= Wait0; end if;
if (Quad = "01") then state <= RL1; end if;
if (Quad = "10") then state <= LR1; end if;
if (Quad = "11") then state <= Count0; end if; --?
Counting <= '1';
when LR1 =>
if (Quad = "00") then state <= Wait0; end if;
if (Quad = "01") then state <= LR1; end if; --?
if (Quad = "10") then state <= LR1; end if;
if (Quad = "11") then state <= LR2; end if;
Direction <= '0';
Counting <= '0';
when LR2 =>
if (Quad = "00") then state <= LR2; end if; --?
if (Quad = "01") then state <= LR3; end if;
if (Quad = "10") then state <= LR1; end if;
if (Quad = "11") then state <= LR2; end if; --?
Direction <= '0';
Counting <= '0';
when LR3 =>
if (Quad = "00") then state <= Count0; end if;
if (Quad = "01") then state <= LR3; end if;
if (Quad = "10") then state <= LR3; end if; --?
if (Quad = "11") then state <= LR2; end if;
Direction <= '0';
Counting <= '0';
when RL1 =>
if (Quad = "00") then state <= Wait0; end if;
if (Quad = "01") then state <= RL1; end if;
if (Quad = "10") then state <= RL1; end if; --?
if (Quad = "11") then state <= RL2; end if;
Direction <= '1';
Counting <= '0';
when RL2 =>
if (Quad = "00") then state <= RL2; end if; --?
if (Quad = "01") then state <= RL1; end if;
if (Quad = "10") then state <= RL3; end if;
if (Quad = "11") then state <= RL2; end if; --?
Direction <= '1';
Counting <= '0';
when RL3 =>
if (Quad = "00") then state <= Count0; end if;
if (Quad = "01") then state <= RL3; end if; --?
if (Quad = "10") then state <= RL3; end if;
if (Quad = "11") then state <= RL2; end if;
Direction <= '1';
Counting <= '0';
when others => state <= Wait0; -- undefined state; just go back to wait so we don't get stuck here...
end case; --state
end if; --clock'event
end process; --(clock)
end architecture;
| gpl-3.0 | ac8fbe514d3c4a613de41212e5d3e84a | 0.648982 | 3.399356 | false | false | false | false |
luk51000/tg2 | Experimentos/ex1/Sources/static/top.vhd | 1 | 1,129 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity top is
port(
SYSCLK_P : in std_logic;
SYSCLK_N : in std_logic;
GPIO_LED : out std_logic_vector (6 downto 0));
end top;
architecture Behavioral of top is
signal clk_200Mhz : std_logic;
signal clk_5hz : std_logic;
signal clk_2hz : std_logic;
signal clk_1hz : std_logic;
component dynamic
port (
clk_1hz : in std_logic;
leds : out std_logic_vector (3 downto 0)
);
end component;
begin
clock_station_i : entity work.clock_station port map(
clk_p => SYSCLK_P,
clk_n => SYSCLK_N,
clk_5hz => clk_5hz,
clk_2hz => clk_2hz,
clk_1hz => clk_1hz
);
static_i : entity work.static port map(
clk_5hz => clk_5hz,
clk_2hz => clk_2hz,
clk_1hz => clk_1hz,
leds => GPIO_LED(6 downto 4)
);
dynamic_i : dynamic port map(
clk_1hz => clk_1hz,
leds => GPIO_LED(3 downto 0)
);
end Behavioral; | gpl-3.0 | 01bace5bac0baeeb7f6feea2083210d5 | 0.523472 | 3.225714 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/mem_conf_control.vhd | 1 | 3,343 | ----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use WORK.myDeclare.all;
entity mem_conf_control is
port (
bus_clk : in std_logic;
reset : in std_logic;
user_mem_32_addr : in std_logic_vector(3 downto 0);
user_w_mem_32_wren : in std_logic;
user_r_mem_32_rden : in std_logic;
user_w_mem_32_data : in std_logic_vector(31 downto 0);
user_r_mem_32_data : out std_logic_vector(31 downto 0);
dev_reset_out : out std_logic;
conf_ack : out std_logic;
conf_nack : out std_logic;
mem_out : out mem_type
);
end mem_conf_control;
architecture Behavioral of mem_conf_control is
--state machines
type confstate_type is (MEMUD, CONF, ACK, NACK, DEVRESET); --state machine definition
signal confstate : confstate_type;
--memory location and its functions;
constant HS_CONFIG_DEVICE_ID : integer := 0;
constant HS_CONFIG_REG_ADDR : integer := 1;
constant HS_CONFIG_REG_VALUE : integer := 2;
constant HS_CONFIG_RW : integer := 3;
constant HS_CONFIG_TRIG : integer := 4;
constant KC705_RUNNING : integer := 5;
constant KC705_RESET : integer := 6;
constant KC705_SYS_CLK_HZ : integer := 7;
constant KC705_FRAME_CLK_HZ : integer :=8;
constant KC705_FRAME_CLK_M : integer :=9;
constant KC705_FRAME_CLK_D : integer :=10;
signal mem_host : mem_type;
begin
mem_out <= mem_host;
sm_proc: process(bus_clk, reset, user_mem_32_addr, mem_host, user_w_mem_32_wren, user_r_mem_32_rden)
begin
if (reset = '1') then
confstate <= MEMUD;
conf_ack <= '0';
conf_nack <= '0';
dev_reset_out <= '0'; --reset device
for i in 0 to MEMARRAYLENGTH-1 loop
mem_host(i) <= (others=>'0');
end loop;
elsif (rising_edge(bus_clk)) then
case confstate is
when MEMUD =>
--update mem_host
if (user_w_mem_32_wren = '1') then
--if user_mem_32_addr =
mem_host(to_integer(unsigned(user_mem_32_addr))) <= user_w_mem_32_data;
else --user update the read only registers
mem_host(KC705_SYS_CLK_HZ) <= std_logic_vector(to_unsigned(250_000_000,32));
mem_host(KC705_FRAME_CLK_HZ) <= std_logic_vector(to_unsigned(1000,32));
end if;
if (user_r_mem_32_rden = '1') then
user_r_mem_32_data <= mem_host(to_integer(unsigned(user_mem_32_addr)));
else
user_r_mem_32_data <= (others=>'0');
end if;
if (not (mem_host(KC705_RESET) = (x"00000000"))) then
confstate <= DEVRESET;
elsif (not (mem_host(HS_CONFIG_TRIG) = (x"00000000"))) then
confstate <= CONF;
else
confstate <= MEMUD;
end if;
conf_nack <= '0';
conf_ack <= '0';
dev_reset_out <= '0';
when CONF =>
--here initiate configuration to the headstage.
--right now always ACK
confstate <= ACK;
when ACK =>
--send ACK signal
conf_ack <= '1';
mem_host(HS_CONFIG_TRIG) <= (others=>'0'); --reset this to 0.
confstate <= MEMUD;
when NACK =>
conf_nack <= '1';
confstate <= MEMUD;
when DEVRESET => -- here we need to send a fresh device map to the host and set this register back to zero
dev_reset_out <= '1';
confstate <= MEMUD;
mem_host(KC705_RESET) <= (others=>'0');
end case;
end if;
end process;
end Behavioral; | mit | 5f949a6ae21b47d64d9c608209fd8f35 | 0.612324 | 2.917103 | false | true | false | false |
kjellhar/ArtixPi | spi_test/src/sim/spi_tb1.vhd | 1 | 2,829 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/16/2016 06:00:47 AM
-- Design Name:
-- Module Name: spi_tb1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_tb1 is
-- Port ( );
end spi_tb1;
architecture Behavioral of spi_tb1 is
component top
Port ( clk1 : in STD_LOGIC;
clk1_en : out STD_LOGIC;
usr_led1 : out std_logic;
usr_led2 : out std_logic;
PI_GPIO8 : in std_logic; -- SPI SS_N
PI_GPIO9 : in std_logic; -- SPI_CLK
PI_GPIO10 : in std_logic; -- SPI_MOSI
PI_GPIO11 : out std_logic); -- SPI_MISO
end component;
signal clk1 : std_logic := '0';
signal clk1_en : std_logic;
signal usr_led1 : std_logic;
signal usr_led2 : std_logic;
signal spi_ss_n : std_logic := '1';
signal spi_clk : std_logic := '1';
signal spi_mosi : std_logic := '0';
signal spi_miso : std_logic;
signal test_run : std_logic := '0';
signal data : std_logic_vector (7 downto 0) := X"3E";
begin
process
variable index : integer := 0;
begin
wait for 100 ns;
test_run <= '1';
wait for 100 ns;
spi_ss_n <= '0';
wait for 5 us;
for index in 7 downto 0 loop
spi_mosi <= data(index);
spi_clk <= '0';
wait for 1 us;
spi_clk <= '1';
wait for 1 us;
end loop;
wait for 5 us;
spi_ss_n <= '1';
wait for 10 us;
test_run <= '0';
wait;
end process;
u_dut: top
Port map (
clk1 => clk1,
clk1_en => clk1_en,
usr_led1 => usr_led1,
usr_led2 => usr_led2,
PI_GPIO8 => spi_ss_n,
PI_GPIO9 => spi_clk,
PI_GPIO10 => spi_mosi,
PI_GPIO11 => spi_miso);
process
begin
wait until test_run='1';
if test_run='1' then
clk1 <= '0';
wait for 50 ns;
clk1 <= '1';
wait for 50 ns;
else
wait;
end if;
end process;
end Behavioral;
| gpl-3.0 | 856f05e270f3263c6388cd157d6dc5ce | 0.482503 | 3.727273 | false | false | false | false |
samrose3/trex-runner | CDiv.vhd | 1 | 667 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY CDiv IS
PORT ( Cin : IN std_logic ;
Cout : OUT std_logic ) ;
END CDiv ;
ARCHITECTURE Behavior OF CDiv IS
constant TC: integer := 12; --Time Constant
signal c0,c1,c2,c3: integer range 0 to 1000;
signal D: std_logic := '0';
BEGIN
PROCESS(Cin)
BEGIN
if (Cin'event and Cin='1') then
c0 <= c0 + 1;
if c0 = TC then
c0 <= 0;
c1 <= c1 + 1;
elsif c1 = TC then
c1 <= 0;
c2 <= c2 + 1;
elsif c2 = TC then
c2 <= 0;
c3 <= c3 + 1;
elsif c3 = TC then
c3 <= 0;
D <= NOT D;
end if;
end if;
Cout <= D;
END PROCESS ;
END Behavior ;
| mit | d36d67c4164fffa2e1110789863ad005 | 0.532234 | 2.565385 | false | false | false | false |
iamllama/EE2020 | ee2020.ip_user_files/ip/dds_compiler_0/dds_compiler_0_sim_netlist.vhdl | 1 | 213,091 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Mar 28 05:22:50 2017
-- Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/sidxb/FPGA/ee2020/ee2020.runs/dds_compiler_0_synth_1/dds_compiler_0_sim_netlist.vhdl
-- Design : dds_compiler_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dds_compiler_0_dds_compiler_v6_0_13 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of dds_compiler_0_dds_compiler_v6_0_13 : entity is 8;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of dds_compiler_0_dds_compiler_v6_0_13 : entity is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of dds_compiler_0_dds_compiler_v6_0_13 : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of dds_compiler_0_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of dds_compiler_0_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of dds_compiler_0_dds_compiler_v6_0_13 : entity is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of dds_compiler_0_dds_compiler_v6_0_13 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of dds_compiler_0_dds_compiler_v6_0_13 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dds_compiler_0_dds_compiler_v6_0_13 : entity is "dds_compiler_v6_0_13";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds_compiler_0_dds_compiler_v6_0_13 : entity is "yes";
end dds_compiler_0_dds_compiler_v6_0_13;
architecture STRUCTURE of dds_compiler_0_dds_compiler_v6_0_13 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 11 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 22;
attribute C_AMPLITUDE of i_synth : label is 1;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 8;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS of i_synth : label is 10000;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL of i_synth : label is 1;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 0;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH of i_synth : label is 12;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 12;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 24;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "artix7";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(21) <= \<const0>\;
debug_axi_pinc_in(20) <= \<const0>\;
debug_axi_pinc_in(19) <= \<const0>\;
debug_axi_pinc_in(18) <= \<const0>\;
debug_axi_pinc_in(17) <= \<const0>\;
debug_axi_pinc_in(16) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(21) <= \<const0>\;
debug_axi_poff_in(20) <= \<const0>\;
debug_axi_poff_in(19) <= \<const0>\;
debug_axi_poff_in(18) <= \<const0>\;
debug_axi_poff_in(17) <= \<const0>\;
debug_axi_poff_in(16) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(21) <= \<const0>\;
debug_phase(20) <= \<const0>\;
debug_phase(19) <= \<const0>\;
debug_phase(18) <= \<const0>\;
debug_phase(17) <= \<const0>\;
debug_phase(16) <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tdata(15) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(14) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(13) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(12) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(11 downto 0) <= \^m_axis_data_tdata\(11 downto 0);
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const1>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.dds_compiler_0_dds_compiler_v6_0_13_viv
port map (
aclk => aclk,
aclken => '0',
aresetn => '0',
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15) => \^m_axis_data_tdata\(11),
m_axis_data_tdata(14 downto 11) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14 downto 11),
m_axis_data_tdata(10 downto 0) => \^m_axis_data_tdata\(10 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 22) => B"00",
s_axis_phase_tdata(21 downto 0) => s_axis_phase_tdata(21 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dds_compiler_0 is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dds_compiler_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dds_compiler_0 : entity is "dds_compiler_0,dds_compiler_v6_0_13,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds_compiler_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dds_compiler_0 : entity is "dds_compiler_v6_0_13,Vivado 2016.4";
end dds_compiler_0;
architecture STRUCTURE of dds_compiler_0 is
signal NLW_U0_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of U0 : label is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of U0 : label is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of U0 : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of U0 : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of U0 : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of U0 : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of U0 : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of U0 : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of U0 : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of U0 : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of U0 : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of U0 : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 8;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of U0 : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of U0 : label is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of U0 : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of U0 : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of U0 : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of U0 : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of U0 : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of U0 : label is 1;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of U0 : label is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of U0 : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of U0 : label is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of U0 : label is 12;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of U0 : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of U0 : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of U0 : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of U0 : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of U0 : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of U0 : label is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.dds_compiler_0_dds_compiler_v6_0_13
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
debug_axi_chan_in(0) => NLW_U0_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_U0_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_U0_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_U0_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_U0_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_U0_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_U0_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_U0_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_U0_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_U0_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_U0_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0),
m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_U0_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_U0_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_U0_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_U0_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 0) => s_axis_phase_tdata(23 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
| gpl-3.0 | e3fbe56c50a8bc1380c603d661f7c561 | 0.918218 | 1.930067 | false | false | false | false |
samrose3/trex-runner | top.vhd | 1 | 18,379 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
use ieee.numeric_std.ALL;
entity top is
port(
clk: in std_logic;
-- User Input
reset: in std_logic;
jump: in std_logic;
-- VGA
hsync: out std_logic;
vsync: out std_logic;
Red: out std_logic_vector(2 downto 0);
Green: out std_logic_vector(2 downto 0);
Blue: out std_logic_vector(2 downto 1);
-- 7 Seg Display
segments : out std_logic_vector (7 downto 0);
anodes : out std_logic_vector (0 to 3)
);
end top;
architecture Behavioral of top is
constant PIX : integer := 16;
constant ROWS : integer := 30;
constant COLS : integer := 40;
constant T_FAC : integer := 100000;
constant RAN_WIDTH : integer := 5;
-- Speed
constant cloudSpeed : integer := 60;
constant cactusSpeed : integer := 40;
constant pteroSpeed : integer := 30;
constant trexSpeed : integer := 25;
-- VGA Sigs
signal hCount: integer := 640;
signal vCount: integer := 480;
signal nextHCount: integer := 641;
signal nextVCount: integer := 480;
-- T-Rex
signal trexX: integer := 8;
signal trexY: integer := 24;
-- Pterodactyl
signal pteroX: integer := COLS*3;
signal pteroY: integer := 21;
-- Clouds
signal cloudX_1: integer := COLS;
signal cloudY_1: integer := 8;
signal cloudX_2: integer := COLS + (COLS/2);
signal cloudY_2: integer := 18;
-- Cactus
signal resetGame : std_logic := '0';
signal cactusX_1: integer := COLS;
signal cactusX_2: integer := COLS + (COLS/2);
signal cactusX_3: integer := COLS + COLS;
signal cactusY: integer := 24;
-- Game Logic
signal gameOver : std_logic := '0';
signal isJumping : std_logic := '0';
signal gameSpeed: integer := 0;
signal rand_num : integer := 0;
-- COMPONENT SIGNALS
signal sclock, cleanJump : std_logic;
signal d0, d10, d100 : std_logic_vector (3 downto 0);
signal disp1, disp2, disp3 : std_logic_vector (6 downto 0);
-- Sprites
type sprite_block is array(0 to 15, 0 to 15) of integer range 0 to 1;
constant trex_1: sprite_block:=((0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0), -- 0
(0,0,0,0,0,0,0,1,1,0,1,1,1,1,1,1), -- 1
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1), -- 2
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1), -- 3
(0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0), -- 4
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0), -- 5
(0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0), -- 6
(1,0,0,0,0,1,1,1,1,1,1,1,1,1,0,0), -- 7
(1,1,0,0,1,1,1,1,1,1,1,0,0,1,0,0), -- 8
(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0), -- 9
(0,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0), -- 10
(0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0), -- 11
(0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0), -- 12
(0,0,0,0,0,1,0,0,1,1,0,0,0,0,0,0), -- 13
(0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), -- 14
(0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0));-- 15
constant trex_2: sprite_block:=((0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0), -- 0
(0,0,0,0,0,0,0,1,1,0,1,1,1,1,1,1), -- 1
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1), -- 2
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1), -- 3
(0,0,0,0,0,0,0,1,1,1,1,1,0,0,0,0), -- 4
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0), -- 5
(0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0), -- 6
(1,0,0,0,0,1,1,1,1,1,1,1,1,1,0,0), -- 7
(1,1,0,0,1,1,1,1,1,1,1,0,0,1,0,0), -- 8
(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0), -- 9
(0,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0), -- 10
(0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0), -- 11
(0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0), -- 12
(0,0,0,0,0,1,0,0,1,0,0,0,0,0,0,0), -- 13
(0,0,0,0,0,1,1,0,1,0,0,0,0,0,0,0), -- 14
(0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0));-- 15
constant trex_dead: sprite_block:=( (0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0), -- 0
(0,0,0,0,0,0,0,1,0,0,0,1,1,1,1,1), -- 1
(0,0,0,0,0,0,0,1,0,1,0,1,1,1,1,1), -- 2
(0,0,0,0,0,0,0,1,0,0,0,1,1,1,1,1), -- 3
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1), -- 4
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0), -- 5
(0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0), -- 6
(1,0,0,0,0,1,1,1,1,1,1,1,1,1,0,0), -- 7
(1,1,0,0,1,1,1,1,1,1,1,0,0,1,0,0), -- 8
(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0), -- 9
(0,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0), -- 10
(0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0), -- 11
(0,0,0,0,1,1,1,1,1,0,0,0,0,0,0,0), -- 12
(0,0,0,0,0,1,0,0,1,0,0,0,0,0,0,0), -- 13
(0,0,0,0,0,1,0,0,1,0,0,0,0,0,0,0), -- 14
(0,0,0,0,0,1,1,0,1,1,0,0,0,0,0,0));-- 15
constant cactus: sprite_block :=((0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0), -- 0
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0), -- 1
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0), -- 2
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0), -- 3
(0,0,0,0,0,1,0,1,1,1,0,1,0,0,0,0), -- 4
(0,0,0,0,1,1,0,1,1,1,0,1,0,0,0,0), -- 5
(0,0,0,0,1,1,0,1,1,1,0,1,0,0,0,0), -- 6
(0,0,0,0,1,1,0,1,1,1,0,1,0,0,0,0), -- 7
(0,0,0,0,1,1,0,1,1,1,0,1,0,0,0,0), -- 8
(0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0), -- 9
(0,0,0,0,0,1,1,1,1,1,0,0,0,0,0,0), -- 10
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0), -- 11
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0), -- 12
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0), -- 13
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0), -- 14
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0));-- 15
constant ptero_1: sprite_block:=((0,0,0,0,0,0,1,1,0,0,0,0,0,0,0,0), -- 0
(0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0), -- 1
(0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0), -- 2
(0,0,0,1,1,0,0,1,1,1,1,0,0,0,0,0), -- 3
(0,0,1,1,1,0,0,1,1,1,1,1,0,0,0,0), -- 4
(0,1,1,1,1,0,0,1,1,1,1,1,1,0,0,0), -- 5
(1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0), -- 6
(0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1), -- 7
(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0), -- 8
(0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0), -- 9
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 11
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 10
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 12
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 13
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 14
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0));-- 15
constant ptero_2: sprite_block:=((0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 0
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 1
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 2
(0,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0), -- 3
(0,0,1,1,1,0,0,0,0,0,0,0,0,0,0,0), -- 4
(0,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), -- 5
(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0), -- 6
(0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1), -- 7
(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0), -- 8
(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,0), -- 9
(0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0), -- 10
(0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0), -- 11
(0,0,0,0,0,0,1,1,0,0,0,0,0,0,0,0), -- 12
(0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0), -- 13
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 14
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0));-- 15
constant cloud: sprite_block:=( (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 0
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 1
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 2
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 3
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 4
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 5
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 6
(0,0,0,0,0,0,1,1,1,1,1,0,0,0,0,0), -- 7
(0,0,0,0,0,1,1,0,0,0,1,1,1,1,0,0), -- 8
(0,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1), -- 9
(1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1), -- 10
(1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1), -- 11
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 12
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 13
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- 14
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0));-- 15
type color_arr is array(0 to 1) of std_logic_vector(7 downto 0);
constant sprite_color : color_arr := ("11011111", "00000000");
-- COMPONENTS
-- Clock Divider
component Debo
port ( clk : in std_logic;
key : in std_logic;
pulse : out std_logic
);
end component;
-- Clock Divider
component CDiv
port ( Cin : in std_logic;
Cout : out std_logic
);
end component;
-- Counter
component Counter
port ( clk : in std_logic;
countup : in std_logic;
reset: in std_logic;
d0 : out std_logic_vector(3 downto 0);
d10 : out std_logic_vector(3 downto 0);
d100 : out std_logic_vector(3 downto 0));
end component;
--Bcd to Seg Decoder
component BcdSegDecoder
port(clk : in std_logic;
bcd : in std_logic_vector (3 downto 0);
segment7 : out std_logic_vector (6 downto 0));
end component;
--Segment Driver
component SegmentDriver
port(disp1 : in std_logic_vector (6 downto 0);
disp2 : in std_logic_vector (6 downto 0);
disp3 : in std_logic_vector (6 downto 0);
disp4 : in std_logic_vector (6 downto 0);
clk : in std_logic;
display_seg : out std_logic_vector (6 downto 0);
display_ena : out std_logic_vector (3 downto 0));
end component;
-- Behaviour Block
begin
segments(0) <= '1';
-- COMPONENTS
JumpDebo: Debo port map (clk => sclock,
key => jump,
pulse => cleanJump);
SegClock: CDiv port map (Cin => clk,
Cout => sclock);
ScoreCounter: Counter
port map( clk => clk,
countup => not gameOver,
reset => resetGame,
d0 => d0,
d10 => d10,
d100 => d100);
--d1000 => d1000);
Digit1: BcdSegDecoder
port map ( clk => clk,
bcd => d0,
segment7 => disp1);
Digit2: BcdSegDecoder
port map ( clk => clk,
bcd => d10,
segment7 => disp2);
Digit3: BcdSegDecoder
port map ( clk => clk,
bcd => d100,
segment7 => disp3);
Driver: SegmentDriver
port map ( disp1 => disp1,
disp2 => disp2,
disp3 => disp3,
disp4 => "1111111",
clk => sclock,
display_seg => segments(7 downto 1),
display_ena => anodes);
-- PROCESSES
vgaSignal: process(clk)
variable sprite_x : integer := 0;
variable sprite_y : integer := 0;
variable prescalerCount: integer := 0;
variable prescaler: integer := 5000000;
variable divide_by_2 : std_logic := '0';
variable rgbDrawColor : std_logic_vector(7 downto 0) := (others => '0');
begin
if clk'event and clk = '1' then
if reset = '1' then
hsync <= '1';
vsync <= '1';
hCount <= 640;
vCount <= 480;
nextHCount <= 641;
nextVCount <= 480;
rgbDrawColor := (others => '0');
divide_by_2 := '0';
else
-- Running at 25 Mhz (50 Mhz / 2)
if divide_by_2 = '1' then
if(hCount = 799) then
hCount <= 0;
if(vCount = 524) then
vCount <= 0;
else
vCount <= vCount + 1;
end if;
else
hCount <= hCount + 1;
end if;
-- horizontal rollover
if (nextHCount = 799) then
nextHCount <= 0;
-- vertical rollover
if (nextVCount = 524) then
nextVCount <= 0;
else
nextVCount <= vCount + 1;
end if;
else
nextHCount <= hCount + 1;
end if;
-- trigger vsync and hsync pulses
if (vCount >= 490 and vCount < 492) then
vsync <= '0';
else
vsync <= '1';
end if;
if (hCount >= 656 and hCount < 752) then
hsync <= '0';
else
hsync <= '1';
end if;
-- in display range
if (hCount < 640 and vCount < 480) then
-- Default is background
rgbDrawColor := "110" & "111" & "11";
sprite_x := hCount mod PIX;
sprite_y := vCount mod PIX;
-- Cloud1
if ((hCount / PIX) = cloudX_1) and ((vCount / PIX) = cloudY_1) then
rgbDrawColor := sprite_color(cloud(sprite_y, sprite_x));
end if;
-- Cloud2
if ((hCount / PIX) = cloudX_2) and ((vCount / PIX) = cloudY_2) then
rgbDrawColor := sprite_color(cloud(sprite_y, sprite_x));
end if;
-- Cactus1
if ((hCount / PIX) = cactusX_1) and ((vCount / PIX) = cactusY) then
rgbDrawColor := sprite_color(cactus(sprite_y, sprite_x));
end if;
-- Cactus2
if ((hCount / PIX) = cactusX_2) and ((vCount / PIX) = cactusY) then
rgbDrawColor := sprite_color(cactus(sprite_y, sprite_x));
end if;
-- Cactus3
if ((hCount / PIX) = cactusX_3) and ((vCount / PIX) = cactusY) then
rgbDrawColor := sprite_color(cactus(sprite_y, sprite_x));
end if;
-- Pterodactyl
if ((hCount / PIX) = pteroX) and ((vCount / PIX) = pteroY) then
if (gameOver = '1') or (prescalerCount <= prescaler) then
rgbDrawColor := sprite_color(ptero_1(sprite_y, sprite_x));
elsif (prescalerCount > prescaler and prescalerCount <= prescaler*2) then
rgbDrawColor := sprite_color(ptero_2(sprite_y, sprite_x));
else
prescalerCount := 0;
rgbDrawColor := sprite_color(ptero_2(sprite_y, sprite_x));
end if;
end if;
-- T-Rex
if ((hCount / PIX) = trexX) and ((vCount / PIX) = trexY) then
if (gameOver = '1') then
rgbDrawColor := sprite_color(trex_dead(sprite_y, sprite_x));
elsif (prescalerCount <= prescaler) then
rgbDrawColor := sprite_color(trex_1(sprite_y, sprite_x));
elsif (prescalerCount > prescaler and prescalerCount <= prescaler*2) then
rgbDrawColor := sprite_color(trex_2(sprite_y, sprite_x));
else
prescalerCount := 0;
rgbDrawColor := sprite_color(trex_2(sprite_y, sprite_x));
end if;
end if;
-- Ground
if ((vCount / PIX) = 24) then
if ((vCount mod PIX) = (PIX - 4)) then
rgbDrawColor := "000" & "000" & "00";
end if;
end if;
-- Show dem colors
Red <= rgbDrawColor(7 downto 5);
Green <= rgbDrawColor(4 downto 2);
Blue <= rgbDrawColor(1 downto 0);
else
Red <= "000";
Green <= "000";
Blue <= "00";
end if;
end if;
divide_by_2 := not divide_by_2;
prescalerCount := prescalerCount + 1;
end if;
end if;
end process;
gameLogic: process(clk, cleanJump)
variable endGame: std_logic := '0';
variable trexCount: integer := 0;
variable cactusCount: integer := 0;
variable pteroCount: integer := 0;
variable cloudCount: integer := 0;
variable waitCount: integer := 0;
variable waitTime: integer := T_FAC*40*25;
-- Random Number Signals
variable rand_temp : std_logic_vector(RAN_WIDTH - 1 downto 0):=(RAN_WIDTH - 1 => '1',others => '0');
variable temp : std_logic := '0';
begin
if clk'event and clk = '1' then
-- Generate Random Number
temp := rand_temp(RAN_WIDTH - 1) xor rand_temp(RAN_WIDTH - 2);
rand_temp(RAN_WIDTH - 1 downto 1) := rand_temp(RAN_WIDTH - 2 downto 0);
rand_temp(0) := temp;
rand_num <= to_integer(unsigned(rand_temp));
-- Adjust game speed
if gameSpeed < 20 and d0 = "0101" then
gameSpeed <= gameSpeed + 5;
end if;
-- Jump Logic
if cleanJump = '1' and trexY = 24 then
if (gameOver = '0') then
isJumping <= '1';
trexCount := 0;
end if;
end if;
-- Trex Jump animation
if trexCount >= T_FAC * trexSpeed then
if isJumping = '1' then
if (trexY > 20) then
trexY <= trexY - 1;
else
isJumping <= '0';
end if;
trexCount := 0;
else
if (trexY < 24) then
trexY <= trexY + 1;
end if;
trexCount := 0;
end if;
end if;
trexCount := trexCount + 1;
-- Detect Hit Cactus
if (trexY = cactusY) and ((trexX = cactusX_1) or (trexX = cactusX_2) or (trexX = cactusX_3)) then
endGame := '1';
end if;
-- Detect Hit Pterodactyl
if (trexY = pteroY) and (trexX = pteroX) then
endGame := '1';
end if;
gameOver <= endGame;
-- Game Over
if endGame = '1' then
if waitCount >= waitTime then
trexX <= 8;
trexY <= 24;
endGame := '0';
waitCount := 0;
resetGame <= '1';
end if;
waitCount := waitCount + 1;
end if;
if resetGame = '1' then
cactusX_1 <= COLS;
cactusX_2 <= COLS + (COLS/2);
cactusX_3 <= COLS + COLS;
cloudX_1 <= COLS;
cloudX_2 <= COLS + (COLS/2);
pteroX <= COLS + COLS;
gameSpeed <= 0;
resetGame <= '0';
else
-- Cactus Movement
if (endGame = '0') and (cactusCount >= T_FAC * cactusSpeed - gameSpeed) then
if (cactusX_1 <= 0) then
cactusX_1 <= COLS + rand_num;
elsif (cactusX_2 <= 0) then
cactusX_2 <= COLS + rand_num;
elsif (cactusX_3 <= 0) then
cactusX_3 <= COLS + rand_num;
else
cactusX_1 <= cactusX_1 - 1;
cactusX_2 <= cactusX_2 - 1;
cactusX_3 <= cactusX_3 - 1;
end if;
cactusCount := 0;
end if;
cactusCount := cactusCount + 1;
-- Pterodactyl Movement
if (endGame = '0') and (pteroCount >= T_FAC * pteroSpeed - gameSpeed) and (d10 >= "0001") then
if pteroX <= 0 then
pteroX <= COLS + (COLS/2) + rand_num;
else
pteroX <= pteroX - 1;
end if;
pteroCount := 0;
end if;
pteroCount := pteroCount + 1;
-- Cloud Movement
if (endGame = '0') and (cloudCount >= T_FAC * cloudSpeed) then
if cloudX_1 <= 0 then
cloudX_1 <= COLS + (COLS/2);
elsif cloudX_2 <= 0 then
cloudX_2 <= COLS + (COLS/2);
else
cloudX_1 <= cloudX_1 - 1;
cloudX_2 <= cloudX_2 - 1;
end if;
cloudCount := 0;
end if;
cloudCount := cloudCount + 1;
end if;
end if; -- end clock event
end process;
end Behavioral;
| mit | 118f6667f9b5189ce891cec27994ca05 | 0.483704 | 2.304866 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/LSB_DETECT.vhd | 1 | 5,281 | --LSB_DETECT entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.MYTYPE.ALL;
ENTITY LSB_DETECT IS
PORT(ENABLE: IN STD_LOGIC;
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
Y_IN: IN COLOR;
RESULT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY LSB_DETECT;
ARCHITECTURE ART1 OF LSB_DETECT IS
TYPE A_STATETYPE IS (SA1,SA2,SA3,SA4,SA5,SA6);
TYPE B_STATETYPE IS (SB1,SB2,SB3,SB4,SB5,SB6);
TYPE C_STATETYPE IS (SC1,SC2,SC3,SC4,SC5,SC6);
SIGNAL A_PRESENT_STATE,A_NEXT_STATE: A_STATETYPE;
SIGNAL B_PRESENT_STATE,B_NEXT_STATE: B_STATETYPE;
SIGNAL C_PRESENT_STATE,C_NEXT_STATE: C_STATETYPE;
SIGNAL DIN: STD_LOGIC;
BEGIN
COMB_PROCESS_1: PROCESS(DIN,A_PRESENT_STATE)
BEGIN
CASE A_PRESENT_STATE IS
WHEN SA1=> RESULT(0)<='0';
IF DIN='0' THEN
A_NEXT_STATE<=SA2;
ELSE
A_NEXT_STATE<=SA1;
END IF;
WHEN SA2=> RESULT(0)<='0';
IF DIN='0' THEN
A_NEXT_STATE<=SA2;
ELSE
A_NEXT_STATE<=SA3;
END IF;
WHEN SA3=> RESULT(0)<='0';
IF DIN='0' THEN
A_NEXT_STATE<=SA2;
ELSE
A_NEXT_STATE<=SA4;
END IF;
WHEN SA4=> RESULT(0)<='0';
IF DIN='0' THEN
A_NEXT_STATE<=SA5;
ELSE
A_NEXT_STATE<=SA1;
END IF;
WHEN SA5=> RESULT(0)<='0';
IF DIN='0' THEN
A_NEXT_STATE<=SA2;
ELSE
A_NEXT_STATE<=SA6;
END IF;
WHEN SA6=> RESULT(0)<='1';
IF DIN='0' THEN
A_NEXT_STATE<=SA2;
ELSE
A_NEXT_STATE<=SA1;
END IF;
END CASE;
END PROCESS;
COMB_PROCESS_2: PROCESS(DIN,B_PRESENT_STATE)
BEGIN
CASE B_PRESENT_STATE IS
WHEN SB1=> RESULT(1)<='0';
IF DIN='0' THEN
B_NEXT_STATE<=SB1;
ELSE
B_NEXT_STATE<=SB2;
END IF;
WHEN SB2=> RESULT(1)<='0';
IF DIN='0' THEN
B_NEXT_STATE<=SB3;
ELSE
B_NEXT_STATE<=SB2;
END IF;
WHEN SB3=> RESULT(1)<='0';
IF DIN='0' THEN
B_NEXT_STATE<=SB1;
ELSE
B_NEXT_STATE<=SB4;
END IF;
WHEN SB4=> RESULT(1)<='0';
IF DIN='0' THEN
B_NEXT_STATE<=SB5;
ELSE
B_NEXT_STATE<=SB2;
END IF;
WHEN SB5=> RESULT(1)<='0';
IF DIN='0' THEN
B_NEXT_STATE<=SB1;
ELSE
B_NEXT_STATE<=SB6;
END IF;
WHEN SB6=> RESULT(1)<='1';
IF DIN='0' THEN
B_NEXT_STATE<=SB1;
ELSE
B_NEXT_STATE<=SB2;
END IF;
END CASE;
END PROCESS;
COMB_PROCESS_3: PROCESS(DIN,C_PRESENT_STATE)
BEGIN
CASE C_PRESENT_STATE IS
WHEN SC1=> RESULT(2)<='0';
IF DIN='0' THEN
C_NEXT_STATE<=SC1;
ELSE
C_NEXT_STATE<=SC2;
END IF;
WHEN SC2=> RESULT(2)<='0';
IF DIN='0' THEN
C_NEXT_STATE<=SC1;
ELSE
C_NEXT_STATE<=SC3;
END IF;
WHEN SC3=> RESULT(2)<='0';
IF DIN='0' THEN
C_NEXT_STATE<=SC4;
ELSE
C_NEXT_STATE<=SC3;
END IF;
WHEN SC4=> RESULT(2)<='0';
IF DIN='0' THEN
C_NEXT_STATE<=SC5;
ELSE
C_NEXT_STATE<=SC2;
END IF;
WHEN SC5=> RESULT(2)<='0';
IF DIN='0' THEN
C_NEXT_STATE<=SC1;
ELSE
C_NEXT_STATE<=SC6;
END IF;
WHEN SC6=> RESULT(2)<='1';
IF DIN='0' THEN
C_NEXT_STATE<=SC1;
ELSE
C_NEXT_STATE<=SC2;
END IF;
END CASE;
END PROCESS;
DATA_IN: PROCESS(Y_IN)
VARIABLE GREY_REM: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
-- 取出灰度的8 bit 数据
GREY_REM:= CONV_STD_LOGIC_VECTOR(Y_IN, 8);
-- 取出LSB 位
DIN<=GREY_REM(0);
END PROCESS;
CLK_PROCESS: PROCESS(CLK,RESET,ENABLE)
BEGIN
IF(RESET='1'OR ENABLE='0') THEN
A_PRESENT_STATE<=SA1;
B_PRESENT_STATE<=SB1;
C_PRESENT_STATE<=SC1;
ELSIF(CLK'EVENT AND CLK='1') THEN
A_PRESENT_STATE<=A_NEXT_STATE;
B_PRESENT_STATE<=B_NEXT_STATE;
C_PRESENT_STATE<=C_NEXT_STATE;
END IF;
END PROCESS;
END ARCHITECTURE;
| apache-2.0 | 8b1bfeff3c7e4cf57a6a3850f09fe173 | 0.412089 | 3.871229 | false | false | false | false |
Hyvok/HardHeat | src/one_wire.vhd | 1 | 12,210 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity one_wire is
generic
(
-- Number of clock cycles for 1us delay
US_D : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
-- Strobe for generating a reset on the 1-wire bus
reset_ow : in std_logic;
ow_in : in std_logic;
-- Data to be sent to the 1-wire bus
data_in : in std_logic_vector(8 - 1 downto 0);
-- Strobe indicating new data has arrived to be sent out
data_in_f : in std_logic;
-- Flag for starting the process of receiving data
receive_data_f : in std_logic;
crc_out : out std_logic_vector(8 - 1 downto 0);
-- Data received from the 1-wire bus
data_out : out std_logic_vector(8 - 1 downto 0);
-- Strobe indicating new data has been received
data_out_f : out std_logic;
ow_out : out std_logic;
-- Signal indicating the 1-wire bus is busy
busy_out : out std_logic;
-- Signal indicating there has been an error, bus needs to be reset
error_out : out std_logic;
-- ID indicating type of error, 1 = no device on bus
error_id_out : out unsigned(1 downto 0)
);
end entity;
architecture rtl of one_wire is
-- One wire bus delay values in clock cycles
constant RESET_ON_D : positive := US_D * 480;
constant RESET_SAMPLE_D : positive := US_D * 70;
constant RESET_D : positive := US_D * 410;
constant TX_ONE_LOW_D : positive := US_D * 6;
constant TX_ONE_HIGH_D : positive := US_D * 64;
constant TX_ZERO_LOW_D : positive := US_D * 60;
constant TX_ZERO_HIGH_D : positive := US_D * 10;
constant RX_SAMPLE_D : positive := US_D * 9;
constant RX_RELEASE_D : positive := US_D * 55;
signal ow_reset_out : std_logic;
signal ow_send_out : std_logic;
signal ow_receive_out : std_logic;
signal err_no_dev : std_logic;
signal busy_reset : std_logic;
signal busy_send : std_logic;
signal busy_receive : std_logic;
signal last_bit : std_logic;
signal last_bit_f : std_logic;
signal crc_reset : std_logic;
begin
-- Invert and combine signals so application logic matches bus state
ow_out <= not (not ow_reset_out or not ow_send_out or not ow_receive_out);
-- Combine process-specific busy signals
busy_out <= busy_reset or busy_send or busy_receive;
-- Handle and indicate errors
ow_error_p: process(clk, reset)
begin
if reset = '1' then
error_out <= '0';
error_id_out <= (others => '0');
elsif rising_edge(clk) then
if err_no_dev = '1' then
error_id_out <= to_unsigned(1, error_id_out'length);
error_out <= '1';
else
error_out <= '0';
error_id_out <= (others => '0');
end if;
end if;
end process;
ow_rst_p: process(clk, reset)
type ow_rst_state is (idle, reset_on, reset_sample, reset_delay);
variable state : ow_rst_state;
variable timer : unsigned(16 - 1 downto 0);
begin
if reset = '1' then
state := idle;
timer := (others => '0');
err_no_dev <= '0';
busy_reset <= '0';
ow_reset_out <= '1';
elsif rising_edge(clk) then
if state = idle then
if reset_ow = '1' then
state := reset_on;
ow_reset_out <= '0';
busy_reset <= '1';
else
busy_reset <= '0';
end if;
elsif state = reset_on then
if timer < RESET_ON_D then
timer := timer + 1;
else
-- Release bus
ow_reset_out <= '1';
state := reset_sample;
timer := (others => '0');
end if;
elsif state = reset_sample then
if timer < RESET_SAMPLE_D then
timer := timer + 1;
else
-- No device present on bus, indicate error
if ow_in = '1' then
err_no_dev <= '1';
state := idle;
timer := (others => '0');
end if;
state := reset_delay;
timer := (others => '0');
end if;
elsif state = reset_delay then
if timer < RESET_D then
timer := timer + 1;
else
state := idle;
timer := (others => '0');
end if;
end if;
end if;
end process;
ow_send_p: process(clk, reset)
type ow_send_state is (idle, tx_one_low, tx_one_high, tx_zero_low,
tx_zero_high, tx_next_bit);
variable state : ow_send_state;
variable timer : unsigned(16 - 1 downto 0);
variable data : std_logic_vector(data_in'range);
variable data_left : unsigned(ceil_log2(data_in'length) downto 0);
begin
if reset = '1' then
state := idle;
-- Bus is released on reset
ow_send_out <= '1';
busy_send <= '0';
timer := (others => '0');
data := (others => '0');
data_left := (others => '0');
elsif rising_edge(clk) then
if state = idle then
-- Bus always released when idle
ow_send_out <= '1';
if data_in_f = '1' then
data := data_in;
data_left := to_unsigned(data'length, data_left'length);
busy_send <= '1';
state := tx_next_bit;
timer := (others => '0');
-- Pull bus down on both cases
ow_send_out <= '0';
else
busy_send <= '0';
end if;
elsif state = tx_one_low then
if timer < TX_ONE_LOW_D then
timer := timer + 1;
else
-- Release bus
ow_send_out <= '1';
state := tx_one_high;
timer := (others => '0');
end if;
elsif state = tx_one_high then
if timer < TX_ONE_HIGH_D then
timer := timer + 1;
else
state := tx_next_bit;
timer := (others => '0');
end if;
elsif state = tx_zero_low then
if timer < TX_ZERO_LOW_D then
timer := timer + 1;
else
ow_send_out <= '1';
state := tx_zero_high;
timer := (others => '0');
end if;
elsif state = tx_zero_high then
if timer < TX_ZERO_HIGH_D then
timer := timer + 1;
else
state := tx_next_bit;
timer := (others => '0');
end if;
elsif state = tx_next_bit then
if data_left = 0 then
state := idle;
else
if data(data'right) = '1' then
state := tx_one_low;
else
state := tx_zero_low;
end if;
data_left := data_left - 1;
-- Shift data
data := shift_right_vec(data, 1);
-- Pull bus down on both cases
ow_send_out <= '0';
end if;
timer := (others => '0');
end if;
end if;
end process;
ow_receive_p: process(clk, reset)
type ow_receive_state is (idle, rx_low, rx_sample, rx_release,
rx_next_bit);
variable state : ow_receive_state;
variable timer : unsigned(16 - 1 downto 0);
variable data : std_logic_vector(data_in'range);
variable data_left : unsigned(ceil_log2(data_in'length) downto 0);
begin
if reset = '1' then
state := idle;
ow_receive_out <= '1';
busy_receive <= '0';
timer := (others => '0');
data := (others => '0');
data_left := (others => '0');
data_out <= (others => '0');
data_out_f <= '0';
last_bit <= '0';
last_bit_f <= '0';
crc_reset <= '0';
elsif rising_edge(clk) then
if state = idle then
-- Reset data out indicator strobe
data_out_f <= '0';
crc_reset <= '1';
if receive_data_f = '1' then
crc_reset <= '1';
-- Pull bus low
ow_receive_out <= '0';
busy_receive <= '1';
data := (others => '0');
data_left := to_unsigned(data'length, data_left'length);
state := rx_low;
timer := (others => '0');
else
busy_receive <= '0';
end if;
elsif state = rx_low then
-- Delay is same as for transmit low-state
if timer < TX_ONE_LOW_D then
timer := timer + 1;
else
-- Release bus
ow_receive_out <= '1';
state := rx_sample;
timer := (others => '0');
end if;
elsif state = rx_sample then
if timer < RX_SAMPLE_D then
timer := timer + 1;
else
data(data'left) := ow_in;
-- Signal CRC module of the last bit
last_bit <= ow_in;
last_bit_f <= '1';
data_left := data_left - 1;
state := rx_release;
timer := (others => '0');
end if;
elsif state = rx_release then
last_bit_f <= '0';
if timer < RX_RELEASE_D then
timer := timer + 1;
else
-- Release bus
ow_receive_out <= '1';
state := rx_next_bit;
timer := (others => '0');
end if;
elsif state = rx_next_bit then
if data_left = 0 then
state := idle;
data_out <= data;
data_out_f <= '1';
else
data := shift_right_vec(data, 1);
ow_receive_out <= '0';
state := rx_low;
end if;
end if;
end if;
end process;
-- CRC calculator, calculated whenever we receive a new bit
crc_p: process(clk, reset)
variable crc : std_logic_vector(crc_out'range);
begin
if reset = '1' then
crc := (others => '0');
crc_out <= (others => '0');
elsif rising_edge(clk) then
if crc_reset = '1' then
crc := (others => '0');
crc_out <= (others => '0');
end if;
if last_bit_f = '1' then
crc(crc'left) := last_bit xor crc(crc'right);
crc(4) := crc(3) xor crc(crc'left);
crc(5) := crc(4) xor crc(crc'left);
crc := shift_left_vec(crc, 1);
crc_out <= crc;
end if;
end if;
end process;
end;
| mit | a2e0b7e06abb07e439cbd002cb9640dc | 0.420147 | 4.279706 | false | false | false | false |
luk51000/tg2 | Experimentos/ex1/Sources/static/clock_station.vhd | 1 | 1,974 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity clock_station is
port(
clk_p : in std_logic;
clk_n : in std_logic;
clk_1hz : out std_logic;
clk_2hz : out std_logic;
clk_5hz : out std_logic
);
end clock_station;
architecture Behavioral of clock_station is
signal clk_200Mhz : std_logic;
signal max_cnt_5_hz : integer := 19999999; -- divide o clock por 40M, gerando 5Hz no clk_out
signal cnt_5_hz : integer range 0 to max_cnt_5_hz := 0;
signal temp_5_hz : std_logic;
signal max_cnt_2_hz : integer := 49999999; -- divide o clock por 100M, gerando 2Hz no clk_out
signal cnt_2_hz : integer range 0 to max_cnt_2_hz := 0;
signal temp_2_hz : std_logic;
signal max_cnt_1_hz : integer := 99999999; -- divide o clock por 200M, gerando 1Hz no clk_out
signal cnt_1_hz : integer range 0 to max_cnt_1_hz := 0;
signal temp_1_hz : std_logic;
begin
clocks_i : entity work.clocks port map(
CLK_IN_P => clk_p,
CLK_IN_N => clk_n,
CLK_OUT => clk_200Mhz
);
process (clk_200Mhz)
begin
if rising_edge(clk_200Mhz) then
if (cnt_1_hz = max_cnt_1_hz) then
temp_1_hz <= not(temp_1_hz);
cnt_1_hz <= 0;
else
cnt_1_hz <= cnt_1_hz + 1;
end if;
if (cnt_2_hz = max_cnt_2_hz) then
temp_2_hz <= not(temp_2_hz);
cnt_2_hz <= 0;
else
cnt_2_hz <= cnt_2_hz + 1;
end if;
if (cnt_5_hz = max_cnt_5_hz) then
temp_5_hz <= not(temp_5_hz);
cnt_5_hz <= 0;
else
cnt_5_hz <= cnt_5_hz + 1;
end if;
end if;
end process;
clk_1hz <= temp_1_hz;
clk_2hz <= temp_2_hz;
clk_5hz <= temp_5_hz;
end Behavioral; | gpl-3.0 | 3bd19db3ae3a3278acd3cbdd3519481b | 0.504559 | 3.065217 | false | false | false | false |
Hyvok/HardHeat | sim/hardheat/hardheat_tb.vhd | 1 | 6,454 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hardheat_tb is
generic
(
TDC_N : positive := 12;
FILT_P_SHIFT_N : integer := 0;
FILT_I_SHIFT_N : integer := -5;
FILT_INIT_OUT_VAL : positive := 2**11 - 1;
FILT_OUT_OFFSET : natural := 2**21;
FILT_OUT_LIM : positive := 2**22;
ACCUM_BITS_N : positive := 32;
ACCUM_WORD_N : positive := 23;
DT_N : positive := 16;
DT_VAL : natural := 100;
LD_LOCK_N : positive := 20;
LD_ULOCK_N : positive := 16;
LD_LOCK_LIMIT : natural := 100;
TEMP_CONV_D : natural := 1000000;
TEMP_CONV_CMD_D : natural := 750000;
TEMP_OW_US_D : positive := 100;
TEMP_PWM_N : positive := 12;
TEMP_PWM_MIN_LVL : natural := 2**12 / 5;
TEMP_PWM_EN_ON_D : natural := 2000000;
TEMP_P_SHIFT_N : integer := 4;
TEMP_I_SHIFT_N : integer := -11;
TEMP_SETPOINT : integer := 320
);
end entity;
architecture rtl of hardheat_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Reference signal frequency 50 kHz
constant REF_PERIOD : time := 1 sec / 90e3;
signal clk : std_logic := '0';
signal reset : std_logic;
signal ref : std_logic := '0';
signal sig : std_logic;
signal sig_lh : std_logic;
signal sig_ll : std_logic;
signal sig_rh : std_logic;
signal sig_rl : std_logic;
signal mod_lvl : unsigned(2 downto 0);
signal mod_lvl_f : std_logic;
-- Temperature controller related signals
signal ow_in : std_logic;
signal ow_out : std_logic;
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
signal temp_out_f : std_logic;
begin
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
ref_gen: process(ref)
begin
ref <= not ref after REF_PERIOD / 2;
end process;
DUT_inst: entity work.hardheat(rtl)
generic map
(
TDC_N => TDC_N,
FILT_P_SHIFT_N => FILT_P_SHIFT_N,
FILT_I_SHIFT_N => FILT_I_SHIFT_N,
FILT_INIT_OUT_VAL => FILT_INIT_OUT_VAL,
FILT_OUT_OFFSET => FILT_OUT_OFFSET,
FILT_OUT_LIM => FILT_OUT_LIM,
ACCUM_BITS_N => ACCUM_BITS_N,
ACCUM_WORD_N => ACCUM_WORD_N,
LD_LOCK_N => LD_LOCK_N,
LD_ULOCK_N => LD_ULOCK_N,
LD_LOCK_LIMIT => LD_LOCK_LIMIT,
DT_N => DT_N,
DT_VAL => DT_VAL,
TEMP_CONV_D => TEMP_CONV_D,
TEMP_CONV_CMD_D => TEMP_CONV_CMD_D,
TEMP_OW_US_D => TEMP_OW_US_D,
TEMP_PWM_N => TEMP_PWM_N,
TEMP_PWM_MIN_LVL => TEMP_PWM_MIN_LVL,
TEMP_PWM_EN_ON_D => TEMP_PWM_EN_ON_D,
TEMP_P_SHIFT_N => TEMP_P_SHIFT_N,
TEMP_I_SHIFT_N => TEMP_I_SHIFT_N,
TEMP_SETPOINT => TEMP_SETPOINT
)
port map
(
clk => clk,
reset => reset,
ref_in => ref,
sig_in => sig,
mod_lvl_in => mod_lvl,
mod_lvl_in_f => mod_lvl_f,
sig_out => sig,
sig_lh_out => sig_lh,
sig_ll_out => sig_ll,
sig_rh_out => sig_rh,
sig_rl_out => sig_rl,
ow_in => ow_in,
ow_out => ow_out,
temp_out_f => temp_out_f
);
data_gen_p: entity work.ds18b20_data_gen(rtl)
generic map
(
MICROSECOND_D => TEMP_OW_US_D
)
port map
(
clk => clk,
reset => reset,
ow_in => ow_in,
ow_out => ow_out,
temp_in => temp,
temp_in_f => temp_f
);
temp_gen: process(clk, reset)
variable cur_temp : signed(16 - 1 downto 0);
begin
if reset = '1' then
cur_temp := to_signed(320, temp'length);
temp <= cur_temp;
temp_f <= '0';
elsif rising_edge(clk) then
temp_f <= '0';
if temp_out_f = '1' then
cur_temp := cur_temp + 16;
temp <= cur_temp;
temp_f <= '1';
end if;
end if;
end process;
mod_lvl_gen: process(clk, reset)
variable mod_lvl_v : unsigned(2 downto 0);
variable cycle_count : unsigned(3 downto 0);
variable last_state : std_logic;
begin
if reset = '1' then
mod_lvl_v := to_unsigned(4, mod_lvl_v'length);
mod_lvl <= mod_lvl_v;
cycle_count := (others => '0');
last_state := '0';
mod_lvl_f <= '0';
elsif rising_edge(clk) then
if mod_lvl_f = '1' then
mod_lvl_f <= '0';
end if;
if not sig = last_state and sig = '1' then
cycle_count := cycle_count + 1;
-- Increase pulse density every 12 rising edges
if cycle_count = 12 then
cycle_count := (others => '0');
if mod_lvl = 0 then
mod_lvl_v := to_unsigned(4, mod_lvl_v'length);
else
mod_lvl_v := mod_lvl_v - 1;
end if;
mod_lvl <= mod_lvl_v;
mod_lvl_f <= '1';
end if;
end if;
last_state := sig;
end if;
end process;
-- Make sure same side high- and low-side are never on at the same time
assert not (sig_lh = sig_ll and sig_lh = '1')
report "Left h = l" severity warning;
assert not (sig_rh = sig_rl and sig_rh = '1')
report "Right h = l" severity warning;
end;
| mit | ed9edd1ba815a77793f5217f0465ff76 | 0.432135 | 3.613662 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/HIDE_STR.vhd | 1 | 4,444 | --HIDE_STR entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.MYTYPE.ALL;
ENTITY HIDE_STR IS
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
XX: IN COLOR;
YY: IN COLOR;
ZZ: IN INTEGER RANGE 0 TO 2;
--VHDL中string的下标从1开始
STR: IN STRING(1 TO 20);
HR_OUT: OUT COLOR;
HG_OUT: OUT COLOR;
HB_OUT: OUT COLOR);
END ENTITY HIDE_STR;
ARCHITECTURE ART1 OF HIDE_STR IS
SIGNAL INDEX: INTEGER RANGE 0 TO 65535;
SIGNAL LEN: INTEGER RANGE 0 TO 65535;
BEGIN
COMPUTE: PROCESS(XX,YY,STR)
BEGIN
INDEX<=YY+1+256*XX;
LEN<= 8 * STR'LENGTH;
END PROCESS;
CLOCK: PROCESS(CLK,RESET,ENABLE)
VARIABLE FIXED_REM: COLOR;
VARIABLE COLOR_REM: STD_LOGIC_VECTOR(7 DOWNTO 0);
--COUNT的范围是256*256
VARIABLE COUNT: INTEGER RANGE 0 TO 65536;
VARIABLE CHAR_I: INTEGER RANGE 0 TO 8;
--STR_I的范围65535/8
VARIABLE STR_I: INTEGER RANGE 1 TO 8192;
VARIABLE CHAR_REM: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(RESET='1' OR ENABLE='0') THEN
HR_OUT<=0;
HG_OUT<=0;
HB_OUT<=0;
COUNT:=0;
CHAR_I:=0;
--VHDL中string的下标从1开始
STR_I:=1;
ELSIF(COUNT=65536) THEN
HR_OUT<=0;
HG_OUT<=0;
HB_OUT<=0;
ELSIF(CLK'EVENT AND CLK='1') THEN
COUNT:=COUNT+1;
IF(ZZ=0) THEN
IF( (COUNT>=INDEX) AND (COUNT<INDEX+LEN)) THEN
-- 取出8 bit 数据
COLOR_REM := CONV_STD_LOGIC_VECTOR(R_IN, 8);
IF(CHAR_I=0) THEN
CHAR_REM:=CONV_TO_VECTOR(STR(STR_I));
END IF;
-- 更改 LSB位
COLOR_REM(0):= CHAR_REM(CHAR_I);
-- 将更改输出
HR_OUT<= CONV_INTEGER(UNSIGNED(COLOR_REM));
IF(CHAR_I<=7) THEN
CHAR_I:=CHAR_I+1;
END IF;
IF(CHAR_I=8) THEN
CHAR_I:=0;
STR_I:=STR_I+1;
END IF;
ELSE
HR_OUT<=R_IN;
END IF;
HB_OUT<=B_IN;
HG_OUT<=G_IN;
ELSIF(ZZ=1) THEN
IF( (COUNT>=INDEX) AND (COUNT<INDEX+LEN)) THEN
-- 取出8 bit 数据
COLOR_REM := CONV_STD_LOGIC_VECTOR(G_IN, 8);
IF(CHAR_I=0) THEN
CHAR_REM:=CONV_TO_VECTOR(STR(STR_I));
END IF;
-- 更改 LSB位
COLOR_REM(0):= CHAR_REM(CHAR_I);
-- 将更改输出
HG_OUT<= CONV_INTEGER(UNSIGNED(COLOR_REM));
IF(CHAR_I<=7) THEN
CHAR_I:=CHAR_I+1;
END IF;
IF(CHAR_I=8) THEN
CHAR_I:=0;
STR_I:=STR_I+1;
END IF;
ELSE
HG_OUT<=G_IN;
END IF;
HR_OUT<=R_IN;
HB_OUT<=B_IN;
ELSIF(ZZ=2) THEN
IF( (COUNT>=INDEX) AND (COUNT<INDEX+LEN)) THEN
-- 取出8 bit 数据
COLOR_REM := CONV_STD_LOGIC_VECTOR(B_IN, 8);
IF(CHAR_I=0) THEN
CHAR_REM:=CONV_TO_VECTOR(STR(STR_I));
END IF;
-- 更改 LSB位
COLOR_REM(0):= CHAR_REM(CHAR_I);
-- 将更改输出
HB_OUT<= CONV_INTEGER(UNSIGNED(COLOR_REM));
IF(CHAR_I<=7) THEN
CHAR_I:=CHAR_I+1;
END IF;
IF(CHAR_I=8) THEN
CHAR_I:=0;
STR_I:=STR_I+1;
END IF;
ELSE
HB_OUT<=B_IN;
END IF;
HR_OUT<=R_IN;
HG_OUT<=G_IN;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | 4a62e9e548abcdc4b9158f32a140ae9a | 0.406697 | 3.761946 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/data_merge.vhd | 2 | 3,821 | ----------------------------------------------------------------------------------
--this merges the data from different streams onto the serdes interface
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity data_merge is
port(
pclk : in std_logic;
reset : in std_logic;
data_rdy_pcie : in std_logic; --this is generated from the SPI interface. Here we must sample this line using 50MHz clock
vsync_o : out std_logic;
stream1 : in std_logic_vector(15 downto 0);
stream2 : in std_logic_vector(15 downto 0);
stream3 : in std_logic_vector(15 downto 0);
stream4 : in std_logic_vector(15 downto 0);
dout_o : out std_logic_vector(7 downto 0)
);
end data_merge;
architecture Behavioral of data_merge is
signal pclk_data_rdy_pcie : std_logic; --pclk synced data_rdy_pcie signal
signal dout, dout_next : std_logic_vector(7 downto 0); --digital output
signal vsync, vsync_next : std_logic;
type merge_state_type is (IDLE, S1MSB, S1LSB, S2MSB, S2LSB, S3MSB, S3LSB, S4MSB, S4LSB, WAITLOW); --state machine definition:
signal merge_state, merge_state_next : merge_state_type;
signal sm_cnt, sm_cnt_next : unsigned(3 downto 0);
begin
--signal assignment
vsync_o <= vsync;
dout_o <= dout;
--vsync triggers the data spliting process
process(reset, merge_state, pclk)
begin
if (reset='1') then
merge_state <= IDLE;
dout <= (others=>'0');
vsync <= '0';
sm_cnt <= (others=>'0');
elsif (rising_edge(pclk)) then
merge_state <= merge_state_next;
dout <= dout_next;
vsync <= vsync_next;
sm_cnt <= sm_cnt_next;
end if;
end process;
--next states
process(reset, merge_state, data_rdy_pcie, sm_cnt, dout, stream1, stream2, stream3, stream4)
begin
case merge_state is
when IDLE =>
if data_rdy_pcie = '1' then
merge_state_next <= S1MSB;
else
merge_state_next <= IDLE;
end if;
dout_next <= dout;
vsync_next <= '0';
sm_cnt_next <= (others=>'0');
when S1MSB =>
merge_state_next <= S1LSB;
dout_next <= stream1(15 downto 8);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S1LSB =>
merge_state_next <= S2MSB;
dout_next <= stream1(7 downto 0);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S2MSB =>
merge_state_next <= S2LSB;
dout_next <= stream2(15 downto 8);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S2LSB =>
merge_state_next <= S3MSB;
dout_next <= stream2(7 downto 0);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S3MSB =>
merge_state_next <= S3LSB;
dout_next <= stream3(15 downto 8);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S3LSB =>
merge_state_next <= S4MSB;
dout_next <= stream3(7 downto 0);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S4MSB =>
merge_state_next <= S4LSB;
dout_next <= stream4(15 downto 8);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when S4LSB =>
merge_state_next <= WAITLOW;
dout_next <= stream4(7 downto 0);
vsync_next <= '1';
sm_cnt_next <= (others=>'0');
when WAITLOW =>
if data_rdy_pcie = '0' then
if sm_cnt >= 10 then
merge_state_next <= IDLE;
vsync_next <= '0';
sm_cnt_next <= (others=>'0');
else
sm_cnt_next <= sm_cnt + 1;
vsync_next <= '1';
merge_state_next <= WAITLOW;
end if;
else
merge_state_next <= WAITLOW;
vsync_next <= '1';
sm_cnt_next <= sm_cnt;
end if;
dout_next <= (others=>'0');
--sm_cnt_next <= (others=>'0');
end case;
end process;
end Behavioral;
| mit | 61437ef8e785af17ddde5e04f610575c | 0.560325 | 3.030135 | false | false | false | false |
Hyvok/HardHeat | sim/debounce/debounce_tb.vhd | 1 | 814 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity debounce_tb is
end entity;
architecture rtl of debounce_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal sig : std_logic;
begin
reset <= '1', '0' after 500 ns;
sig <= '1';
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
DUT_inst: entity work.debounce(rtl)
generic map
(
DEBOUNCE_D => 1000,
FLIPFLOPS_N => 5
)
port map
(
clk => clk,
reset => reset,
sig_in => sig
);
end;
| mit | adc0dd0f0776a0e5a8f02b8d789ef7bc | 0.496314 | 3.751152 | false | false | false | false |
Hyvok/HardHeat | sim/epdm/epdm_tb.vhd | 1 | 3,137 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity epdm_tb is
generic
(
TUNING_WORD_N : positive := 22
);
end entity;
architecture rtl of epdm_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal sig : std_logic;
signal mod_lvl : unsigned(2 downto 0);
signal mod_lvl_f : std_logic;
signal sig_lh : std_logic;
signal sig_ll : std_logic;
signal sig_rh : std_logic;
signal sig_rl : std_logic;
begin
DUT_inst: entity work.epdm(rtl)
port map
(
clk => clk,
reset => reset,
mod_lvl_in => mod_lvl,
mod_lvl_in_f => mod_lvl_f,
sig_in => sig,
sig_lh_out => sig_lh,
sig_ll_out => sig_ll,
sig_rh_out => sig_rh,
sig_rl_out => sig_rl
);
sig_gen_p: entity work.phase_accumulator(rtl)
generic map
(
ACCUM_BITS_N => 32,
TUNING_WORD_N => TUNING_WORD_N
)
port map
(
clk => clk,
reset => reset,
tuning_word_in => to_unsigned(2**TUNING_WORD_N / 2 - 1,
TUNING_WORD_N),
sig_out => sig
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
mod_lvl_gen: process(clk, reset)
variable mod_lvl_v : unsigned(2 downto 0);
variable cycle_count : unsigned(3 downto 0);
variable last_state : std_logic;
begin
if reset = '1' then
mod_lvl_v := to_unsigned(4, mod_lvl_v'length);
mod_lvl <= mod_lvl_v;
cycle_count := (others => '0');
last_state := sig;
mod_lvl_f <= '0';
elsif rising_edge(clk) then
if mod_lvl_f = '1' then
mod_lvl_f <= '0';
end if;
if not sig = last_state and sig = '1' then
cycle_count := cycle_count + 1;
-- Increase pulse density every 12 rising edges
if cycle_count = 12 then
cycle_count := (others => '0');
if mod_lvl = 0 then
mod_lvl_v := to_unsigned(4, mod_lvl_v'length);
else
mod_lvl_v := mod_lvl_v - 1;
end if;
mod_lvl <= mod_lvl_v;
mod_lvl_f <= '1';
end if;
end if;
last_state := sig;
end if;
end process;
-- Make sure same side high- and low-side are never on at the same time
assert not (sig_lh = sig_ll and sig_lh = '1')
report "Left h = l" severity warning;
assert not (sig_rh = sig_rl and sig_rh = '1')
report "Right h = l" severity warning;
end;
| mit | 0b789a385d93fef090f967672ec1a46a | 0.452981 | 3.725653 | false | false | false | false |
zhlinh/vhdl_course | Exercise/DECODER/DECODER.vhd | 1 | 1,442 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECODER IS
PORT(A,B,C:IN STD_LOGIC;
Y:OUT BIT_VECTOR(7 DOWNTO 0));
END ENTITY DECODER;
--使用SLL逻辑运算符
ARCHITECTURE ART1 OF DECODER IS
SIGNAL SR:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
SR<=C&B&A;
Y<="00000001" SLL(CONV_INTEGER(SR));
END ARCHITECTURE ART1;
--使用PROCESS语句
ARCHITECTURE ART2 OF DECODER IS
SIGNAL SR:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
SR<=C&B&A;
PROCESS(SR) IS
BEGIN
Y<=(OTHERS=>'1');
Y(CONV_INTEGER(SR))<='1';
END PROCESS;
END ARCHITECTURE ART2;
--使用WHEN - ELSE语句
ARCHITECTURE ART3 OF DECODER IS
SIGNAL SR:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
SR<=C&B&A;
Y(0)<='1' WHEN SR="000" ELSE '0';
Y(1)<='1' WHEN SR="001" ELSE '0';
Y(2)<='1' WHEN SR="010" ELSE '0';
Y(3)<='1' WHEN SR="011" ELSE '0';
Y(4)<='1' WHEN SR="100" ELSE '0';
Y(5)<='1' WHEN SR="101" ELSE '0';
Y(6)<='1' WHEN SR="110" ELSE '0';
Y(7)<='1' WHEN SR="111" ELSE '0';
END ARCHITECTURE ART3;
--使用CASE - WHEN 语句
ARCHITECTURE ART4 OF DECODER IS
SIGNAL SR:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
SR<=C&B&A;
PROCESS(SR) IS
BEGIN
CASE SR IS
WHEN "000"=>Y<="00000001";
WHEN "001"=>Y<="00000010";
WHEN "010"=>Y<="00000100";
WHEN "011"=>Y<="00001000";
WHEN "100"=>Y<="00010000";
WHEN "101"=>Y<="00100000";
WHEN "110"=>Y<="01000000";
WHEN "111"=>Y<="10000000";
END CASE;
END PROCESS;
END ARCHITECTURE ART4; | apache-2.0 | 6bcacdc0a0e5e3efbae3f86eb2ad3685 | 0.638177 | 2.511628 | false | false | false | false |
zhlinh/vhdl_course | Exercise/ENCODER/ENCODER.vhd | 1 | 1,547 | --8线-3线优先编码器。A的编码等级最低
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY ENCODER IS
PORT(A,B,C,D,E,F,G,H:IN STD_LOGIC;
Y0,Y1,Y2:OUT STD_LOGIC);
END ENTITY ENCODER;
--使用条件赋值语句
ARCHITECTURE ART1 OF ENCODER IS
SIGNAL SY:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--优先级在此处体现，哈哈
SY(2 DOWNTO 0)<="111" WHEN H='1' ELSE
"110" WHEN G='1' ELSE
"101" WHEN F='1' ELSE
"100" WHEN E='1' ELSE
"011" WHEN D='1' ELSE
"010" WHEN C='1' ELSE
"001" WHEN B='1' ELSE
"000" WHEN A='1' ELSE
"XXX";
Y0<=SY(0);
Y1<=SY(1);
Y2<=SY(2);
END ARCHITECTURE ART1;
--使用LOOP语句
ARCHITECTURE ART2 OF ENCODER IS
BEGIN
PROCESS(A,B,C,D,E,F,G) IS
VARIABLE VSR:STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE I:INTEGER;
BEGIN
VSR:=(H,G,F,E,D,C,B,A);
I:=7;
--不等号是/=,你敢信？
WHILE I>=0 AND VSR(I)/='1' LOOP
I:=I-1;
END LOOP;
(Y2,Y1,Y0)<=CONV_STD_LOGIC_VECTOR(I,3);
END PROCESS;
END ARCHITECTURE ART2;
--使用IF条件语句
ARCHITECTURE ART3 OF ENCODER IS
SIGNAL SY:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(H,G,F,E,D,C,B,A) IS
BEGIN
IF H='1' THEN SY<="111";
ELSIF G='1' THEN SY<="110";
ELSIF F='1' THEN SY<="101";
ELSIF E='1' THEN SY<="100";
ELSIF D='1' THEN SY<="011";
ELSIF C='1' THEN SY<="010";
ELSIF B='1' THEN SY<="001";
ELSIF A='1' THEN SY<="000";
ELSE SY<="XXX";
END IF;
END PROCESS;
Y0<=SY(0);
Y1<=SY(1);
Y2<=SY(2);
END ARCHITECTURE ART3;
| apache-2.0 | d9fec5631ede21e0494dc10c962c1962 | 0.59806 | 2.128319 | false | false | false | false |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/soc_system_inst.vhd | 2 | 18,728 | component soc_system is
port (
clk_clk : in std_logic := 'X'; -- clk
hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents
hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component soc_system;
u0 : component soc_system
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hps_0_f2h_cold_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_cold_reset_req_reset_n, -- hps_0_f2h_cold_reset_req.reset_n
hps_0_f2h_debug_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_debug_reset_req_reset_n, -- hps_0_f2h_debug_reset_req.reset_n
hps_0_f2h_stm_hw_events_stm_hwevents => CONNECTED_TO_hps_0_f2h_stm_hw_events_stm_hwevents, -- hps_0_f2h_stm_hw_events.stm_hwevents
hps_0_f2h_warm_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_warm_reset_req_reset_n, -- hps_0_f2h_warm_reset_req.reset_n
hps_0_h2f_reset_reset_n => CONNECTED_TO_hps_0_h2f_reset_reset_n, -- hps_0_h2f_reset.reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_0_hps_io.hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
| mit | fb595384c8c972d2d02bd257f6f064ab | 0.458565 | 2.883893 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/cobs_encoder.vhd | 1 | 2,537 | --this is the COBS encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.myDeclare.all;
entity cobs_encoder is
Port (
bus_clk : in std_logic;
reset : in std_logic;
--cobs inputs
pre_cobs_data_in : in async_stream_type;
data_in_length : in std_logic_vector(4 downto 0);
cobs_conv_begin : in std_logic;
--cobs outputs
cobs_data_out : out cobs_stream_types;
data_out_length : out std_logic_vector(4 downto 0);
cobs_conv_rdy : out std_logic
);
end cobs_encoder;
architecture Behavioral of cobs_encoder is
type cobs_sm_type is (IDLE, CONV);
signal cobs_sm : cobs_sm_type;
signal vec_cnt : unsigned(4 downto 0);
signal idxreg : unsigned(4 downto 0);
signal cobs_data : cobs_stream_types;
signal pre_cobs_data : cobs_stream_types; --this is put into cobs_data format with the padding for consistency.
begin
cobs_data_out <= cobs_data;
--cobs process
cobs_proc: process(bus_clk, reset, cobs_conv_begin, idxreg, vec_cnt)
begin
if (reset = '1') then
cobs_sm <= IDLE;
vec_cnt <= (others=>'0');
idxreg <= to_unsigned(24,5); --always initialized to 254, last position of the COBS data.
cobs_conv_rdy <= '0';
for i in 0 to 25 loop
cobs_data(i) <= (others=>'0');
pre_cobs_data(i) <= (others=>'0');
end loop;
elsif (rising_edge(bus_clk)) then
case cobs_sm is
when IDLE => --idle state
if cobs_conv_begin = '1' then
cobs_sm <= CONV;
vec_cnt <= unsigned(data_in_length); --initilize the vector count to data_in_length
idxreg <= unsigned(data_in_length)+1; --initlize reg1 to data_in_length
for i in 0 to 23 loop
pre_cobs_data(i+1) <= pre_cobs_data_in(i);
end loop;
pre_cobs_data(25) <= (others=>'0'); --always fill the 255 position with 0.
pre_cobs_data(0) <= (others=>'1');
data_out_length <= (others=>'0');
end if;
cobs_conv_rdy <= '0'; --lower the conv flag
when CONV =>
if vec_cnt >= 1 then
vec_cnt <= vec_cnt - 1;
if pre_cobs_data(to_integer(vec_cnt)) = "00000000" then
cobs_data(to_integer(vec_cnt)) <= "000" & std_logic_vector(idxreg - vec_cnt);
idxreg <= vec_cnt;
else
cobs_data(to_integer(vec_cnt)) <= pre_cobs_data(to_integer(vec_cnt));
end if;
else
cobs_sm <= IDLE;
cobs_data(0) <= "000" & std_logic_vector(idxreg);
cobs_conv_rdy <= '1';
data_out_length <= std_logic_vector(unsigned(data_in_length) + 2);
end if;
end case;
end if;
end process;
end Behavioral;
| mit | 0c0b24adae0e7bc4b6a2ab3a6605b597 | 0.629878 | 2.909404 | false | false | false | false |
cafe-alpha/wasca | obsolete/fpga_firmware_V2/wasca_dev_v1_0/wasca_dev_v1_0.srcs/sources_1/bd/wasca_toplevel/hdl/wasca_toplevel_wrapper.vhd | 2 | 4,975 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
--Date : Thu Mar 02 22:09:48 2017
--Host : Tho running 64-bit Service Pack 1 (build 7601)
--Command : generate_target wasca_toplevel_wrapper.bd
--Design : wasca_toplevel_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity wasca_toplevel_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
abus_address : in STD_LOGIC_VECTOR ( 25 downto 0 );
abus_chipselect : in STD_LOGIC_VECTOR ( 2 downto 0 );
abus_data_dir : out STD_LOGIC;
abus_irq : inout STD_LOGIC_VECTOR ( 0 to 0 );
abus_irq_dir : out STD_LOGIC;
abus_read : in STD_LOGIC;
abus_reset : in STD_LOGIC;
abus_wait : inout STD_LOGIC;
abus_wait_dir : out STD_LOGIC;
abus_write : in STD_LOGIC_VECTOR ( 1 downto 0 );
data_to_and_from_pins : inout STD_LOGIC_VECTOR ( 15 downto 0 )
);
end wasca_toplevel_wrapper;
architecture STRUCTURE of wasca_toplevel_wrapper is
component wasca_toplevel is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
data_to_and_from_pins : inout STD_LOGIC_VECTOR ( 15 downto 0 );
abus_chipselect : in STD_LOGIC_VECTOR ( 2 downto 0 );
abus_read : in STD_LOGIC;
abus_reset : in STD_LOGIC;
abus_irq : inout STD_LOGIC_VECTOR ( 0 to 0 );
abus_write : in STD_LOGIC_VECTOR ( 1 downto 0 );
abus_wait : inout STD_LOGIC;
abus_address : in STD_LOGIC_VECTOR ( 25 downto 0 );
abus_data_dir : out STD_LOGIC;
abus_irq_dir : out STD_LOGIC;
abus_wait_dir : out STD_LOGIC
);
end component wasca_toplevel;
begin
wasca_toplevel_i: component wasca_toplevel
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
abus_address(25 downto 0) => abus_address(25 downto 0),
abus_chipselect(2 downto 0) => abus_chipselect(2 downto 0),
abus_data_dir => abus_data_dir,
abus_irq(0) => abus_irq(0),
abus_irq_dir => abus_irq_dir,
abus_read => abus_read,
abus_reset => abus_reset,
abus_wait => abus_wait,
abus_wait_dir => abus_wait_dir,
abus_write(1 downto 0) => abus_write(1 downto 0),
data_to_and_from_pins(15 downto 0) => data_to_and_from_pins(15 downto 0)
);
end STRUCTURE;
| gpl-2.0 | dda0149f64e25904bd012aebb672185f | 0.601608 | 3.117168 | false | false | false | false |
upci/upci | Projeto/alu.vhd | 1 | 3,059 | ---- Arithmetic Logic Unit ---------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY alu IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
ALU_cmd: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- 3 bits que indicam a operacao a ser executada pela alu
ALU_zero: OUT STD_LOGIC; -- flag que indica se o resultado da alu foi zero
ALU_slt: OUT STD_LOGIC; -- flag que indica se o resultado da alu foi menor que zero
ALU_valid: IN STD_LOGIC; -- sinal que indica que o resultado da ALU deve ser colocado em ALU_bus (ou Z se 0)
ALU_enable: IN STD_LOGIC; -- sinal que indica se a ALU deve realizar alguma operacao
ALU_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); -- barramento de entrada/saida
END ENTITY alu;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE rtl OF alu IS
SIGNAL ACC: STD_LOGIC_VECTOR (n-1 DOWNTO 0); -- acumulador que guardara os resultados da alu
BEGIN
-- Se o ALU_valid = '1', manda o valor do resultado da ALU pro barramento. Caso contrario, manda Z.
ALU_bus <= ACC
WHEN ALU_valid = '1'
ELSE (others => 'Z');
-- Define a flag ALU_zero como 1 caso o acumulador seja todo 0
ALU_zero <= '1'
WHEN UNSIGNED(ACC) = reg_zero
ELSE '0';
ALU_slt <= '1'
WHEN SIGNED(ACC) < 0
ELSE '0';
PROCESS (clk, nrst) IS
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, volta o acumulador para 0
IF nrst = '0' THEN
ACC <= (others => '0');
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF rising_edge(clk) THEN
IF ALU_enable = '1' THEN
-- Verifica o comando para poder decidir o que fazer
CASE ALU_cmd IS
-- Carrega o valor do barramento no ACC (ACC = 0 + BUS)
WHEN "0000" => ACC <= ALU_bus;
-- Soma o valor do barramento ao ACC (ACC = ACC + BUS)
WHEN "0001" => ACC <= ACC + ALU_bus;
-- NOT do valor do barramento (ACC = not BUS)
WHEN "0010" => ACC <= NOT ALU_bus;
-- OR do valor do barramento com o ACC (ACC = ACC or BUS)
WHEN "0011" => ACC <= ACC OR ALU_bus;
-- AND do valor do barramento com o ACC (ACC = ACC and BUS)
WHEN "0100" => ACC <= ACC AND ALU_bus;
-- XOR do valor do barramento com o ACC (ACC = ACC xor BUS)
WHEN "0101" => ACC <= ACC XOR ALU_bus;
-- Incrementa o ACC (ACC = ACC + 1)
WHEN "0110" => ACC <= ACC + 1;
-- Subtracao
WHEN "0111" => ACC <= ACC - ALU_bus;
-- Decremento
WHEN "1000" => ACC <= ACC - 1;
WHEN OTHERS => ACC <= ACC;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
------------------------------------------------------------------------------------------------------------------ | gpl-2.0 | 9fad5f86142e6013a5091528786a0552 | 0.531219 | 3.776543 | false | false | false | false |
zhlinh/vhdl_course | Assignment/CHKSEQ/CHKSEQ.vhd | 1 | 1,422 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHKSEQ IS
PORT(DIN:IN STD_LOGIC;
CLK,RESET:IN STD_LOGIC;
DOUT:OUT STD_LOGIC);
END ENTITY CHKSEQ;
ARCHITECTURE ART OF CHKSEQ IS
TYPE STATETYPE IS(S1,S2,S3,S4,S5,S6,S7,S8);
SIGNAL PRESENT_STATE,NEXT_STATE:STATETYPE;
BEGIN
COMB_PROCESS:PROCESS(DIN,PRESENT_STATE)
BEGIN
CASE PRESENT_STATE IS
WHEN S1=>DOUT<='0';
IF DIN='0' THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S2;
END IF;
WHEN S2=>DOUT<='0';
IF DIN='0' THEN
NEXT_STATE<=S2;
ELSE
NEXT_STATE<=S3;
END IF;
WHEN S3=>DOUT<='0';
IF DIN='0' THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S4;
END IF;
WHEN S4=>DOUT<='0';
IF DIN='0' THEN
NEXT_STATE<=S5;
ELSE
NEXT_STATE<=S4;
END IF;
WHEN S5=>DOUT<='0';
IF DIN='0' THEN
NEXT_STATE<=S6;
ELSE
NEXT_STATE<=S2;
END IF;
WHEN S6=>DOUT<='0';
IF DIN='0' THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S7;
END IF;
WHEN S7=>DOUT<='0';
IF DIN='0' THEN
NEXT_STATE<=S8;
ELSE
NEXT_STATE<=S3;
END IF;
WHEN S8=>DOUT<='1';
IF DIN='0' THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S2;
END IF;
END CASE;
END PROCESS;
CLK_PROCESS:PROCESS(CLK,RESET)
BEGIN
IF(RESET='1') THEN
PRESENT_STATE<=S1;
ELSIF(CLK'EVENT AND CLK='1') THEN
PRESENT_STATE<=NEXT_STATE;
END IF;
END PROCESS;
END ARCHITECTURE ART;
| apache-2.0 | 44fddfabe331ffb8a68add7e8f4c687b | 0.585091 | 2.512367 | false | false | false | false |
upci/upci | Simulações/testes_memoria_16bits/memory.vhd | 1 | 3,655 | ---- Memory ------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY memory IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
MDR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para MDR
MAR_load: IN STD_LOGIC; -- sinal de carregamento do BUS para MAR
MEM_valid: IN STD_LOGIC; -- sinal que indica que o resultado da MDR deve ser colocado em MEM_bus (ou Z se 0)
MEM_en: IN STD_LOGIC; -- ativacao da memorica para operacoes de leitura e escrita
MEM_rw: IN STD_LOGIC; -- flag que indica se a operacao a ser realizada eh de leitura ou escrita
MEM_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)); -- barramento de entrada/saida
END ENTITY memory;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE rtl OF memory IS
SIGNAL mdr: STD_LOGIC_VECTOR(wordlen-1 DOWNTO 0); -- registrador de dados
SIGNAL mar: UNSIGNED(wordlen-oplen-1 DOWNTO 0); -- registrador de enderecos
SIGNAL dataIn: std_logic_vector (wordlen-1 DOWNTO 0);
SIGNAL dataOut: std_logic_vector (wordlen-1 DOWNTO 0);
COMPONENT ram_infer IS
PORT
(
clock: IN std_logic;
data: IN std_logic_vector (wordlen-1 DOWNTO 0);
write_address: IN integer RANGE 0 to 2**(n-oplen-1);
read_address: IN integer RANGE 0 to 2**(n-oplen-1);
we: IN std_logic;
q: OUT std_logic_vector (wordlen-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
mem1: ram_infer PORT MAP (clk, dataIn, to_integer(mar), to_integer(mar), MEM_rw, dataOut);
-- Se o MEM_valid = '1', manda o valor do resultado do MDR pro barramento. Caso contrario, manda Z.
MEM_bus <= mdr
WHEN MEM_valid = '1'
ELSE (others => 'Z');
PROCESS (clk, nrst) IS
-- VARIABLE contents: memory_array; -- conteudo da memoria
-- Definicao do valor padrao da memoria (para simular ROM com programa)
CONSTANT program: memory_array := (0 => "0000000000000011",
1 => "0000001000000100",
2 => "0000000100000101",
3 => "0000000000001100",
4 => "0000000000000011",
5 => "0000000000000000" ,
OTHERS => (OTHERS => '0'));
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, reseta os registradores e conteudo da memoria
IF nrst = '0' THEN
mdr <= (OTHERS => '0');
mar <= (OTHERS => '0');
FOR i IN 0 TO 2**(n-oplen-1) LOOP
dataIn <= program(i);
END LOOP;
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF (clk'EVENT AND clk='1') THEN
-- A ordem de prioridade eh: Carregamento do MAR, Carregamento do MDR e leitura/escrita
IF MAR_load = '1' THEN
mar <= UNSIGNED(MEM_bus(n-oplen-1 DOWNTO 0)); -- Para carregar MAR, basta ler o endereco do que tem no BUS (desconsidera o OPCODE)
ELSIF MDR_load = '1' THEN
mdr <= MEM_bus; -- Para carregar MDR, basta ler direto do BUS
ELSIF MEM_en = '1' THEN
IF MEM_rw = '0' THEN
-- mdr <= contents(to_integer(mar)); -- Se for leitura, pega o conteudo do endereco salvo em MAR e manda para MDR
mdr <= dataOut;
ELSE
-- contents(to_integer(mar)) := mdr; -- Se for escrita, escreve MDR no endereco salvo em MAR
dataIn <= mdr;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
------------------------------------------------------------------------------------------------------------------- | gpl-2.0 | 3dcf1102b4036e01a36fe5d2dc3cd359 | 0.56881 | 3.799376 | false | false | false | false |
thequbit/af_paper | code/xilinx/focus_calculation_pixel_difference_1d.vhd | 1 | 4,432 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity focus_calculation_pixel_difference_1d is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_framevalid : in STD_LOGIC;
i_linevalid : in STD_LOGIC;
i_Y : in STD_LOGIC_VECTOR(7 downto 0);
--i_dv : in STD_LOGIC;
o_focusvalue : out STD_LOGIC_VECTOR (15 downto 0);
o_dv : out STD_LOGIC);
end focus_calculation_pixel_difference_1d;
architecture Behavioral of focus_calculation_pixel_difference_1d is
--
-- images are 865x577
--
-- ROI box size is 128x128
--
-- (865/2) - (128/2) = 368, "0101110000" (note: -1 for inclusive)
-- (865/2) + (128/2) = 496, "0111110000" (note: +1 for inclusive)
-- (577/2) - (128/2) = 224, "0011100000" (note: -1 for inclusive)
-- (577/2) + (128/2) = 352, "0101100000" (note: +1 for inclusive)
constant C_STARTPIXELCOUNT : STD_LOGIC_VECTOR(9 downto 0) := "0101111110";
constant C_STOPPIXELCOUNT : STD_LOGIC_VECTOR(9 downto 0) := "0111110001";
constant C_STARTLINECOUNT : STD_LOGIC_VECTOR(9 downto 0) := "0011111110";
constant C_STOPLINECOUNT : STD_LOGIC_VECTOR(9 downto 0) := "0101100001";
signal r_framevalidlast : STD_LOGIC;
signal r_linevalidlast : STD_LOGIC;
signal r_linecount : STD_LOGIC_VECTOR(9 downto 0);
signal r_pixelcount : STD_LOGIC_VECTOR(9 downto 0);
signal r_pixelvalid : STD_LOGIC;
signal r_y : STD_LOGIC_VECTOR(7 downto 0);
signal r_y1 : STD_LOGIC_VECTOR(7 downto 0);
signal r_pixelsum : STD_LOGIC_VECTOR(15 downto 0);
signal r_dv : STD_LOGIC;
signal r_focusvalue : STD_LOGIC_VECTOR(15 downto 0);
begin
o_focusvalue <= r_focusvalue;
o_dv <= r_dv;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_framevalidlast <= '0';
r_linevalidlast <= '0';
else
r_framevalidlast <= i_framevalid;
r_linevalidlast <= i_linevalid;
end if;
end if;
end process;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_Y <= (others => '0');
r_Y1 <= (others => '0');
else
-- delayed 2 clocks to compensate for r_pixelvalid calculation
r_Y <= i_Y;
r_Y1 <= r_Y;
end if;
end if;
end process;
-- linecount
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_linecount <= (others => '0');
else
r_linecount <= r_linecount;
if ( r_framevalidlast = '0' and i_framevalid = '1' ) then
r_linecount <= (others => '0');
elsif ( i_framevalid = '1' ) then
r_linecount <= r_linecount + '1';
end if;
end if;
end if;
end process;
-- pixelcount
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_pixelcount <= (others => '0');
else
r_pixelcount <= r_pixelcount;
if ( r_linevalidlast = '0' and i_linevalid = '1' ) then
r_pixelcount <= (others => '0');
elsif ( i_framevalid = '1' ) then
r_pixelcount <= r_pixelcount + '1';
end if;
end if;
end if;
end process;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
else
r_pixelvalid <= '0';
if ( r_pixelcount > C_STARTPIXELCOUNT and r_pixelcount < C_STOPPIXELCOUNT and r_linecount > C_STARTLINECOUNT and r_linecount < C_STOPLINECOUNT ) then
r_pixelvalid <= '1';
end if;
end if;
end if;
end process;
-- pixelsum
process( i_clk )
begin
if ( rising_edge ( i_clk ) ) then
if ( i_reset = '1' ) then
r_pixelsum <= (others => '0');
else
r_pixelsum <= r_pixelsum;
if ( r_framevalidlast = '0' and i_framevalid = '1' ) and ( r_linevalidlast = '0' and i_linevalid = '1' ) then
r_pixelsum <= (others => '0');
else
if ( r_pixelvalid = '1' ) then
if ( r_Y > r_Y1 ) then
r_pixelsum <= r_pixelsum + (r_Y - r_Y1);
else
r_pixelsum <= r_pixelsum + (r_Y1 - r_Y);
end if;
end if;
end if;
end if;
end if;
end process;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_dv <= '0';
r_focusvalue <= (others => '0');
else
r_dv <= '0';
r_focusvalue <= r_focusvalue;
if ( r_pixelcount = C_STOPPIXELCOUNT and r_linecount = C_STOPLINECOUNT ) then
r_dv <= '1';
r_focusvalue <= r_pixelsum;
end if;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | ffde90d5ab01f714674b4eb8b23f49b4 | 0.592283 | 2.790932 | false | false | false | false |
summershrimp/VHDLClock | Counter24.vhd | 1 | 1,018 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity Counter24 is
Port(
h:out std_logic_vector(2 downto 0);
l:out std_logic_vector(3 downto 0);
co:out std_logic;
en:in std_logic;
clk:in std_logic;
rst:in std_logic
);
End Entity Counter24;
Architecture ArchCounter24 of Counter24 is
Begin
Process(clk, rst)
Variable tlow:std_logic_vector(3 downto 0);
Variable thigh:std_logic_vector(2 downto 0);
Begin
If rst = '1' then
tlow := (Others => '0' );
thigh := (Others => '0' );
Elsif clk'event and clk='1' Then
co<='0';
If en = '1' Then
If tlow < 10 Then
tlow := tlow + 1;
End If;
If tlow = 10 Then
thigh := thigh + 1;
tlow := (Others => '0' );
End If;
If thigh = 2 Then
if tlow = 4 Then
thigh := (Others => '0');
tlow := (Others => '0');
co<='1';
End If;
End If;
h<=thigh;
l<=tlow;
End If;
End If;
End Process;
End Architecture;
| gpl-2.0 | 09fc4eabca4f2d919097a2c7dd99966c | 0.559921 | 2.796703 | false | false | false | false |
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| gpl-3.0 | 780bc25ad0b3216369f8b0d38c58e613 | 0.955668 | 1.828145 | false | false | false | false |
zhlinh/vhdl_course | Assignment/FREQ_CNT/ALERT.vhd | 1 | 1,321 | --Alert
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALERT IS
PORT( DATA_RANGE :IN STD_LOGIC;
CARRY_LABEL :IN STD_LOGIC;
D1_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D4_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D1_OUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_OUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_OUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
BEEP :OUT STD_LOGIC;
RANGE_DISP :OUT STD_LOGIC);
END ENTITY ALERT;
ARCHITECTURE ART1 OF ALERT IS
BEGIN
PROCESS(DATA_RANGE,D1_IN,D2_IN,D3_IN)
BEGIN
IF (DATA_RANGE='0') THEN
IF (D4_IN /= "0000")THEN
D1_OUT <= "0000";
D2_OUT <= "0000";
D3_OUT <= "0000";
RANGE_DISP <= '0';
BEEP <= '1';
ELSE
D1_OUT <= D1_IN;
D2_OUT <= D2_IN;
D3_OUT <= D3_IN;
RANGE_DISP <= '0';
BEEP <= '0';
END IF;
ELSE
IF (CARRY_LABEL = '1') THEN
D1_OUT <= "0000";
D2_OUT <= "0000";
D3_OUT <= "0000";
RANGE_DISP <= '1';
BEEP <= '1';
ELSE
D1_OUT <= D2_IN;
D2_OUT <= D3_IN;
D3_OUT <= D4_IN;
RANGE_DISP <= '1';
BEEP <= '0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | 5e762fedb4375dfe1dded040571875ef | 0.551098 | 2.406193 | false | false | false | false |
kjellhar/ArtixPi | spi_test/src/hdl/top.vhd | 1 | 6,020 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/16/2016 03:43:39 AM
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk1 : in STD_LOGIC;
clk1_en : out STD_LOGIC;
usr_led1 : out std_logic;
usr_led2 : out std_logic;
PI_GPIO8 : in std_logic; -- SPI SS_N
PI_GPIO9 : out std_logic; -- SPI_MISO
PI_GPIO10 : in std_logic; -- SPI_MOSI
PI_GPIO11 : in std_logic); -- SPI_CLK
end top;
architecture Behavioral of top is
component clk_wiz_0
port (-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic);
end component;
component spi_slave is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 3); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core)
spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
wren_i : in std_logic := 'X'; -- user data write enable
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
--- debug ports: can be removed for the application circuit ---
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end component;
signal clk100m : std_logic;
signal spi_ss_n : std_logic;
signal spi_clk : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
signal di_req : std_logic;
signal di : std_logic_vector(7 downto 0);
signal wren : std_logic;
signal wr_ack : std_logic;
signal do_valid : std_logic;
signal do : std_logic_vector (7 downto 0);
signal di_reg : std_logic_vector (7 downto 0) := X"00";
signal do_reg : std_logic_vector (7 downto 0);
signal di_data_ready : std_logic := '1';
begin
clkgen : clk_wiz_0
port map (
-- Clock in ports
clk_in1 => clk1,
-- Clock out ports
clk_out1 => clk100m
);
clk1_en <= '1';
spi_ss_n <= PI_GPIO8;
spi_clk <= PI_GPIO11;
PI_GPIO9 <= spi_miso;
spi_mosi <= PI_GPIO10;
u_spi_slave : spi_slave
Generic map (
N => 8,
CPOL => '0',
CPHA => '0',
PREFETCH => 3)
Port map(
clk_i => clk100m,
spi_ssel_i => spi_ss_n,
spi_sck_i => spi_clk,
spi_mosi_i => spi_mosi,
spi_miso_o => spi_miso,
di_req_o => di_req,
di_i => di,
wren_i => wren,
wr_ack_o => wr_ack,
do_valid_o => do_valid,
do_o => do);
process
variable counter : integer range 0 to 255 := 0;
begin
wait until rising_edge (clk100m);
if do_valid = '1' then
do_reg <= do;
end if;
if di_data_ready = '1' then
di_reg <= do_reg;
wren <= '1';
di_data_ready <= '0';
else
wren <= '0';
end if;
if wr_ack = '1' then
di_data_ready <= '1';
end if;
end process;
di <= di_reg;
--usr_led1 <= reg_di(0);
--usr_led2 <= reg_di(1);
end Behavioral;
| gpl-3.0 | d5bfb95d909ce0eb52c0b9fa704e05fc | 0.454651 | 4.163209 | false | false | false | false |
Hyvok/HardHeat | src/debounce.vhd | 1 | 1,207 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity debounce is
generic
(
-- Debounce time in clock cycles
DEBOUNCE_D : natural;
FLIPFLOPS_N : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
sig_in : in std_logic;
sig_out : out std_logic
);
end entity;
architecture rtl of debounce is
signal flipflops : std_logic_vector(FLIPFLOPS_N - 1 downto 0);
signal timer_set : std_logic;
signal timer : unsigned(ceil_log2(DEBOUNCE_D) downto 0);
begin
timer_set <= flipflops(flipflops'high) xor flipflops(flipflops'high - 1);
process(clk, reset)
begin
if reset = '1' then
flipflops <= (others => '0');
timer <= (others => '0');
sig_out <= '0';
elsif rising_edge(clk) then
flipflops <= shift_left_vec(flipflops, 1, sig_in);
-- Reset counter, input is changing
if timer_set = '1' then
timer <= (others => '0');
elsif timer < DEBOUNCE_D then
timer <= timer + 1;
else
sig_out <= flipflops(flipflops'high);
end if;
end if;
end process;
end;
| mit | 1be796eb0cc4d4448f157574cd5fe5b6 | 0.584093 | 3.201592 | false | false | false | false |
zhlinh/vhdl_course | Assignment/IMG_LSB/RGB2YUV.vhd | 1 | 1,678 | --RGB2YUV entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.MYTYPE.ALL;
ENTITY RGB2YUV IS
PORT(RESET: IN STD_LOGIC;
CLK: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
Y_OUT: OUT COLOR;
U_OUT: OUT COLOR;
V_OUT: OUT COLOR);
END ENTITY RGB2YUV;
ARCHITECTURE ART1 OF RGB2YUV IS
BEGIN
CLOCK: PROCESS(CLK,RESET,ENABLE)
VARIABLE Y_REG: COLOR;
VARIABLE U_REG: COLOR;
VARIABLE V_REG: COLOR;
VARIABLE TEMP: INTEGER RANGE -512 TO 512;
BEGIN
IF(RESET='1' OR ENABLE='0') THEN
Y_OUT<=0;
U_OUT<=0;
V_OUT<=0;
ELSIF(CLK'EVENT AND CLK='1') THEN
TEMP:=(299*R_IN + 587*G_IN + 114*B_IN)/1000;
--调整
IF(TEMP<0) THEN
Y_REG:=0;
ELSIF(TEMP>255) THEN
Y_REG:=255;
ELSE
Y_REG:=TEMP;
END IF;
TEMP:=(-169*R_IN - 331*G_IN + 500*B_IN)/1000 + 128;
--调整
IF(TEMP<0) THEN
U_REG:=0;
ELSIF(TEMP>255) THEN
U_REG:=255;
ELSE
U_REG:=TEMP;
END IF;
TEMP:=(500*R_IN - 419*G_IN - 81*B_IN)/1000 + 128;
--调整
IF(TEMP<0) THEN
V_REG:=0;
ELSIF(TEMP>255) THEN
V_REG:=255;
ELSE
V_REG:=TEMP;
END IF;
Y_OUT<=Y_REG;
U_OUT<=U_REG;
V_OUT<=V_REG;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | 99196b9d70a414f5b8d276deb5828fda | 0.452581 | 3.352113 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/myDeclare.vhd | 1 | 1,943 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package myDeclare is
constant MEMARRAYLENGTH : integer := 11;
constant HS_MEMARRAY_LENGTH : integer := 5;
constant MAXDEVICENUMBER : integer := 16;
constant LOG2_MAX_DEVICE_NUMBER : integer := 4;
constant LOG2_MAX_DATA_FRAME_PER_DEVICE: integer := 10;
--memory register blocks
type mem_type is array (0 to MEMARRAYLENGTH-1) of std_logic_vector(31 downto 0);
type async_stream_type is array (0 to 23) of std_logic_vector(7 downto 0);
type cobs_stream_types is array (0 to 25) of std_logic_vector(7 downto 0);
--constants below are used at the headstage only
constant NUMBEROFDEVICE : integer := 3;
constant LOG2NUMBEROFDEVICE : integer := 2;
type data_length_array_type is array (0 to NUMBEROFDEVICE-1) of integer;
constant data_length_array : data_length_array_type := (67, 67, 9); --this is in units of 32bits
constant MAXSAMPLES : integer := 10;
constant LOG2MAXSAMPLES : integer := 4;
type device_data_array_type is array (0 to NUMBEROFDEVICE-1) of std_logic_vector(15 downto 0);
--FIFO declarations
COMPONENT fifo_imu_16bits
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_intan_16bits
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC
);
END COMPONENT;
end myDeclare;
package body myDeclare is
end myDeclare;
| mit | fa0a075b5c533a2150fc4af88d49d417 | 0.685538 | 3.164495 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/i2c_slave.vhd | 2 | 18,827 | ----------------------------------------------------------------------------------
-- This slave I2C interface
<<<<<<< HEAD
-- this slave module does not stretch the clock, because it doesn't need to.
-- by: Jie (Jack) Zhang MWL-MIT
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_slave is
generic (
input_clk : integer := 10_000_000; --input clock speed from user logic in Hz
bus_clk : integer := 100_000; --speed the i2c bus (scl) will run at in Hz
ID : std_logic_vector(6 downto 0) := "1010000"); --Device specific ID
port (
clk : in std_logic; --system clock
reset : in std_logic; --active high reset
sda : inout std_logic; --serial data i2c bus
scl : inout std_logic; --serial clock i2c bus
wr_enb : out std_logic; --0: write to slave 1: read from slave
rd_enb : out std_logic;
addrout : out std_logic_vector(7 downto 0);
regin : in std_logic_vector(7 downto 0); --register values to send through i2c
regout : out std_logic_vector(7 downto 0)
);
end i2c_slave;
architecture Behavioral of i2c_slave is
signal clk10x : std_logic;
signal sda_sync, scl_sync, sda_sync_dl, scl_sync_dl : std_logic;
signal rx_cnt, rx_cnt_next : unsigned(3 downto 0);
signal tx_cnt, tx_cnt_next : unsigned(2 downto 0);
signal data_reg, data_reg_next : std_logic_vector(7 downto 0);
signal wr_reg, wr_reg_next : std_logic_vector(7 downto 0);
signal rd_reg, rd_reg_next : std_logic_vector(7 downto 0);
signal addr_reg, addr_reg_next : std_logic_vector(7 downto 0);
signal sda_i, sda_i_next : std_logic;
signal wr_rd, wr_rd_next : std_logic;
signal datacnt, datacnt_next : std_logic;
constant divider : integer := (input_clk/bus_clk)/10; --number of clocks in 1/10 cycle of scl
type machine is(READY, DEVICEID, SLV_ACK1, WRVALUE, SLV_ACK2, RDVALUE, PRESTOP, STOP); --needed states
=======
-- currently only does supports WRITE options
-- by: Jie (Jack) Zhang MWL-MIT
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_slave is
generic (
input_clk : integer := 50_000_000; --input clock speed from user logic in Hz
bus_clk : integer := 500_000; --speed the i2c bus (scl) will run at in Hz
ID : std_logic_vector(6 downto 0) := "1010101"); --Device specific ID
port (
clk : in std_logic; --system clock
reset : in std_logic; --active high reset
sda : inout std_logic; --serial data i2c bus
scl : inout std_logic; --serial clock i2c bus
wr_enb : out std_logic; --0: write to slave 1: read from slave
rd_enb : out std_logic;
addrout : out std_logic_vector(7 downto 0);
regin : in std_logic_vector(7 downto 0); --register values to send through i2c
regout : out std_logic_vector(7 downto 0)
);
end i2c_slave;
architecture Behavioral of i2c_slave is
signal clk4x : std_logic;
signal sda_sync, scl_sync, sda_sync_dl, scl_sync_dl : std_logic;
signal rx_cnt, rx_cnt_next : unsigned(3 downto 0);
signal data_reg, data_reg_next : std_logic_vector(7 downto 0);
signal wr_reg, wr_reg_next : std_logic_vector(7 downto 0);
signal rd_reg, rd_reg_next : std_logic_vector(7 downto 0);
signal addr_reg, addr_reg_next : std_logic_vector(7 downto 0);
signal sda_i, sda_i_next : std_logic;
signal wr_rd, wr_rd_next : std_logic;
signal datacnt, datacnt_next : std_logic;
constant divider : integer := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
type machine is(READY, DEVICEID, SLV_ACK1, WRVALUE, SLV_ACK2, RDVALUE, STOP); --needed states
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
signal slv_state, slv_state_next : machine;
--a general clock divider
component clk_div is
generic (MAXD : natural := 5);
port (
<<<<<<< HEAD
clk : in std_logic;
reset : in std_logic;
div : in integer range 0 to MAXD;
div_clk : out std_logic
=======
clk : in std_logic;
reset : in std_logic;
div : in integer range 0 to MAXD;
div_clk : out std_logic
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
);
end component;
begin
--mapping
addrout <= addr_reg(7 downto 0);
<<<<<<< HEAD
regout <= wr_reg(7 downto 0);
--sync sda and scl inout pins and delay them for 1 clock cycle
i2c_sync_proc : process (clk10x, reset)
begin
if (reset = '1') then
sda_sync <= '0';
scl_sync <= '0';
sda_sync_dl <= '0';
scl_sync_dl <= '0';
elsif (rising_edge(clk10x)) then
sda_sync <= to_x01(sda);
scl_sync <= to_x01(scl);
=======
regout <= wr_reg(7 downto 0);
--sync sda and scl inout pins and delay them for 1 clock cycle
i2c_sync_proc : process (clk4x, reset)
begin
if (reset = '1') then
sda_sync <= '0';
scl_sync <= '0';
sda_sync_dl <= '0';
scl_sync_dl <= '0';
elsif (rising_edge(clk4x)) then
sda_sync <= to_x01(sda);
scl_sync <= to_x01(scl);
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
sda_sync_dl <= sda_sync;
scl_sync_dl <= scl_sync;
end if;
end process;
--get a clock: use 50MHz to divide by the divider
<<<<<<< HEAD
clk_div_10x : clk_div
generic map(MAXD => divider)
port map(clk => clk, reset => reset, div => divider, div_clk => clk10x);
main_slave_sm : process (clk10x, reset)
begin
if reset = '1' then
slv_state <= READY;
rx_cnt <= (others => '0');
tx_cnt <= to_unsigned(7, 3);
data_reg <= (others => '0');
addr_reg <= (others => '0');
wr_reg <= (others => '0');
rd_reg <= (others => '0');
sda_i <= '0';
datacnt <= '0';
elsif rising_edge(clk10x) then
slv_state <= slv_state_next;
rx_cnt <= rx_cnt_next;
tx_cnt <= tx_cnt_next;
data_reg <= data_reg_next;
addr_reg <= addr_reg_next;
wr_reg <= wr_reg_next;
rd_reg <= rd_reg_next;
sda_i <= sda_i_next;
datacnt <= datacnt_next;
end if;
end process;
--next state logics in a two-segmented approach
main_slave_sm_next : process (clk10x, reset, sda_i, tx_cnt, slv_state, sda_sync, scl_sync, sda_sync_dl, datacnt, scl_sync_dl, rx_cnt, data_reg, wr_reg, rd_reg, regin, addr_reg)
=======
clk_div_4x : clk_div
generic map(MAXD => divider)
port map(clk => clk, reset => reset, div => divider, div_clk => clk4x);
main_slave_sm : process (clk4x, reset)
begin
if reset = '1' then
slv_state <= READY;
rx_cnt <= (others => '0');
data_reg <= (others => '0');
addr_reg <= (others => '0');
wr_reg <= (others => '0');
rd_reg <= (others => '0');
sda_i <= '0';
datacnt <= '0';
elsif rising_edge(clk4x) then
slv_state <= slv_state_next;
rx_cnt <= rx_cnt_next;
data_reg <= data_reg_next;
addr_reg <= addr_reg_next;
wr_reg <= wr_reg_next;
rd_reg <= rd_reg_next;
sda_i <= sda_i_next;
datacnt <= datacnt_next;
end if;
end process;
--next state logics in a two-segmented approach
main_slave_sm_next : process (clk4x, reset, slv_state, sda_sync, scl_sync, sda_sync_dl, datacnt, scl_sync_dl, rx_cnt, data_reg, wr_reg, rd_reg, regin, addr_reg)
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
begin
case slv_state is
when READY =>
data_reg_next <= (others => '0'); --reset addr value
<<<<<<< HEAD
rx_cnt_next <= (others => '0');
sda_i_next <= '1'; --sitting high if not used
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
=======
rx_cnt_next <= (others => '0');
sda_i_next <= '1'; --sitting high if not used
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
addr_reg_next <= addr_reg;
if (sda_sync_dl = '1' and sda_sync = '0') and (scl_sync_dl = '1' and scl_sync = '1') then --detects a downward transition on the sda line while no change on scl line
slv_state_next <= DEVICEID;
else
slv_state_next <= READY;
end if;
datacnt_next <= '0';
<<<<<<< HEAD
tx_cnt_next <= to_unsigned(7, 3);
when DEVICEID => --this state gets the device id, if it matches with the id then send ack signal. Otherwise do nothing.
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
addr_reg_next <= addr_reg;
datacnt_next <= datacnt;
tx_cnt_next <= to_unsigned(7, 3);
=======
when DEVICEID => --this state gets the device id, if it matches with the id then send ack signal. Otherwise do nothing.
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
addr_reg_next <= addr_reg;
datacnt_next <= datacnt;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
if rx_cnt < 8 then
if (scl_sync_dl = '0' and scl_sync = '1') then --detects a rising edge of scl
--latch data
data_reg_next <= data_reg(6 downto 0) & sda_sync;
<<<<<<< HEAD
rx_cnt_next <= rx_cnt + 1;
else
data_reg_next <= data_reg; --keep value
rx_cnt_next <= rx_cnt;
end if;
slv_state_next <= DEVICEID; --
sda_i_next <= '1';
else
--wait for the falling edge before making an action ...
if (scl_sync_dl = '1' and scl_sync = '0') then
if data_reg(7 downto 1) = ID then --(7 downto 1) is the id, 0th bit is the R/W bit
slv_state_next <= SLV_ACK1;
sda_i_next <= '1';
rx_cnt_next <= (others => '0');
else
slv_state_next <= READY;
sda_i_next <= '1';
rx_cnt_next <= rx_cnt;
end if;
else
slv_state_next <= DEVICEID;
sda_i_next <= '1';
rx_cnt_next <= rx_cnt;
end if;
data_reg_next <= data_reg;
end if;
when SLV_ACK1 =>
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
addr_reg_next <= addr_reg;
datacnt_next <= datacnt;
--wait for clock falling edge ...
if (scl_sync_dl = '1' and scl_sync = '0') then
if data_reg(0) = '0' then
slv_state_next <= WRVALUE;
data_reg_next <= (others => '0'); --reset data value
sda_i_next <= '0';
tx_cnt_next <= tx_cnt;
else
slv_state_next <= RDVALUE;
data_reg_next <= regin;
sda_i_next <= regin(to_integer(tx_cnt));
tx_cnt_next <= to_unsigned(7, 3);
end if;
else
sda_i_next <= '0';
slv_state_next <= SLV_ACK1;
data_reg_next <= data_reg; --keep addr value
tx_cnt_next <= tx_cnt;
end if;
rx_cnt_next <= rx_cnt;
when WRVALUE =>
rd_reg_next <= rd_reg;
datacnt_next <= datacnt;
tx_cnt_next <= to_unsigned(7, 3);
if rx_cnt < 8 then
if ((sda_sync_dl = '1' and sda_sync = '0') and (scl_sync_dl = '1' and scl_sync = '1')) then --this is a start bit!
slv_state_next <= DEVICEID; --
rx_cnt_next <= (others => '0');
data_reg_next <= data_reg;
elsif (scl_sync_dl = '0' and scl_sync = '1') then --detects a rising edge of scl
--latch data
data_reg_next <= data_reg(6 downto 0) & sda_sync;
rx_cnt_next <= rx_cnt + 1;
slv_state_next <= WRVALUE; --
else
data_reg_next <= data_reg; --keep value
rx_cnt_next <= rx_cnt;
slv_state_next <= WRVALUE; --
end if;
sda_i_next <= '1';
wr_reg_next <= wr_reg;
addr_reg_next <= addr_reg;
else
if (scl_sync_dl = '1' and scl_sync = '0') then
slv_state_next <= SLV_ACK2;
data_reg_next <= data_reg;
rx_cnt_next <= (others => '0');
sda_i_next <= '0';
if datacnt = '0' then
wr_reg_next <= wr_reg;
addr_reg_next <= data_reg;
else
wr_reg_next <= data_reg;
addr_reg_next <= addr_reg;
end if;
else
data_reg_next <= data_reg; --keep value
rx_cnt_next <= rx_cnt;
slv_state_next <= WRVALUE;
sda_i_next <= '1';
wr_reg_next <= wr_reg;
=======
rx_cnt_next <= rx_cnt + 1;
else
data_reg_next <= data_reg; --keep value
rx_cnt_next <= rx_cnt;
end if;
slv_state_next <= DEVICEID; --
sda_i_next <= '1';
else
if data_reg(7 downto 1) = ID then --(7 downto 1) is the id, 0th bit is the R/W bit
slv_state_next <= SLV_ACK1;
sda_i_next <= '0';
else
slv_state_next <= READY;
sda_i_next <= '1';
end if;
rx_cnt_next <= (others => '0');
data_reg_next <= data_reg;
end if;
when SLV_ACK1 =>
sda_i_next <= '0';
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
addr_reg_next <= addr_reg;
datacnt_next <= datacnt;
if rx_cnt < 4 then
sda_i_next <= '0';
slv_state_next <= SLV_ACK1;
rx_cnt_next <= rx_cnt + 1;
data_reg_next <= data_reg; --keep addr value
else
if data_reg(0) = '0' then
slv_state_next <= WRVALUE;
data_reg_next <= (others => '0'); --reset data value
else
slv_state_next <= RDVALUE;
data_reg_next <= regin;
end if;
sda_i_next <= '1';
rx_cnt_next <= (others => '0');
end if;
when WRVALUE =>
rd_reg_next <= rd_reg;
datacnt_next <= datacnt;
if rx_cnt < 8 then
if (scl_sync_dl = '0' and scl_sync = '1') then --detects a rising edge of scl
--latch data
data_reg_next <= data_reg(6 downto 0) & sda_sync;
rx_cnt_next <= rx_cnt + 1;
else
data_reg_next <= data_reg; --keep value
rx_cnt_next <= rx_cnt;
end if;
slv_state_next <= WRVALUE; --
sda_i_next <= '1';
wr_reg_next <= wr_reg;
addr_reg_next <= addr_reg;
else
slv_state_next <= SLV_ACK2;
data_reg_next <= data_reg;
rx_cnt_next <= (others => '0');
sda_i_next <= '0';
if datacnt = '0' then
wr_reg_next <= wr_reg;
addr_reg_next <= data_reg;
else
wr_reg_next <= data_reg;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
addr_reg_next <= addr_reg;
end if;
end if;
when SLV_ACK2 =>
<<<<<<< HEAD
sda_i_next <= '0';
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
addr_reg_next <= addr_reg;
tx_cnt_next <= to_unsigned(7, 3);
data_reg_next <= data_reg; --keep addr value
--wait for the falling edge
if (scl_sync_dl = '1' and scl_sync = '0') then
if datacnt = '0' then
slv_state_next <= WRVALUE;
datacnt_next <= '1';
else
slv_state_next <= STOP;
datacnt_next <= datacnt;
end if;
rx_cnt_next <= (others => '0');
else
slv_state_next <= SLV_ACK2;
rx_cnt_next <= rx_cnt + 1;
datacnt_next <= datacnt;
end if;
when RDVALUE =>
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
datacnt_next <= datacnt;
addr_reg_next <= addr_reg;
data_reg_next <= data_reg;
if (scl_sync_dl = '1' and scl_sync = '0') then
if tx_cnt = 0 then
tx_cnt_next <= tx_cnt;
slv_state_next <= PRESTOP;
else
tx_cnt_next <= tx_cnt - 1;
slv_state_next <= RDVALUE;
end if;
else
tx_cnt_next <= tx_cnt;
slv_state_next <= RDVALUE;
end if;
sda_i_next <= regin(to_integer(tx_cnt));
rx_cnt_next <= rx_cnt;
when PRESTOP =>
--wait for a falling edge
if (scl_sync_dl = '1' and scl_sync = '0') then
slv_state_next <= PRESTOP;
sda_i_next <= sda_i;
rx_cnt_next <= rx_cnt;
else
slv_state_next <= STOP;
sda_i_next <= '1';
rx_cnt_next <= (others => '0');
end if;
tx_cnt_next <= tx_cnt;
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
datacnt_next <= datacnt;
addr_reg_next <= addr_reg;
data_reg_next <= data_reg;
when STOP =>
if (sda_sync_dl = '0' and sda_sync = '1' and scl_sync = '1' and scl_sync_dl = '1') then --detect the stop condition
slv_state_next <= READY;
rx_cnt_next <= rx_cnt;
else
if rx_cnt < 9 then --put a timeout and make it go back to READY state
slv_state_next <= STOP;
rx_cnt_next <= rx_cnt + 1;
else
slv_state_next <= READY;
rx_cnt_next <= rx_cnt;
end if;
end if;
data_reg_next <= data_reg;
sda_i_next <= '1';
wr_reg_next <= wr_reg;
addr_reg_next <= addr_reg;
datacnt_next <= datacnt;
tx_cnt_next <= to_unsigned(7, 3);
=======
sda_i_next <= '0';
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
addr_reg_next <= addr_reg;
if rx_cnt < 4 then
sda_i_next <= '0';
slv_state_next <= SLV_ACK2;
rx_cnt_next <= rx_cnt + 1;
data_reg_next <= data_reg; --keep addr value
datacnt_next <= datacnt;
else
if datacnt = '0' then
slv_state_next <= WRVALUE;
data_reg_next <= (others => '0'); --reset data value
datacnt_next <= '1';
else
slv_state_next <= STOP;
data_reg_next <= (others => '0'); --reset data value
datacnt_next <= datacnt;
end if;
sda_i_next <= '1';
rx_cnt_next <= (others => '0');
end if;
when RDVALUE =>
wr_reg_next <= wr_reg;
rd_reg_next <= rd_reg;
datacnt_next <= datacnt;
addr_reg_next <= addr_reg;
if rx_cnt < 8 then
if (scl_sync_dl = '0' and scl_sync = '1') then --detects a rising edge of scl
--latch data
data_reg_next <= data_reg(6 downto 0) & '0';
rx_cnt_next <= rx_cnt + 1;
else
data_reg_next <= data_reg; --keep value
rx_cnt_next <= rx_cnt;
end if;
slv_state_next <= WRVALUE; --
sda_i_next <= data_reg(7);
rd_reg_next <= rd_reg;
else
slv_state_next <= SLV_ACK2;
data_reg_next <= data_reg;
rx_cnt_next <= (others => '0');
sda_i_next <= '0';
rd_reg_next <= data_reg;
end if;
when STOP =>
if (sda_sync_dl = '0' and sda_sync = '1' and scl_sync = '1' and scl_sync_dl = '1') then --detect the stop condition
slv_state_next <= READY;
rx_cnt_next <= rx_cnt;
else
if rx_cnt < 8 then --put a timeout and make it go back to READY state
slv_state_next <= STOP;
rx_cnt_next <= rx_cnt + 1;
else
slv_state_next <= READY;
rx_cnt_next <= rx_cnt;
end if;
end if;
data_reg_next <= data_reg;
sda_i_next <= '1';
wr_reg_next <= wr_reg;
addr_reg_next <= addr_reg;
datacnt_next <= datacnt;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
end case;
end process;
--set scl and sda outputs
scl <= 'Z';
sda <= '0' when sda_i = '0' else 'Z';
end Behavioral; | mit | 9a2500c5f21e7bc68c9927241c16028c | 0.543687 | 2.826028 | false | false | false | false |
thequbit/af_paper | code/xilinx/focus_calculation_pixel_difference_2d.vhd | 1 | 5,846 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity focus_calculation_pixel_difference_2d is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_framevalid : in STD_LOGIC;
i_linevalid : in STD_LOGIC;
i_Y : in STD_LOGIC_VECTOR(7 downto 0);
--i_dv : in STD_LOGIC;
o_focusvalue : out STD_LOGIC_VECTOR (31 downto 0);
o_dv : out STD_LOGIC);
end focus_calculation_pixel_difference_2d;
architecture Behavioral of focus_calculation_pixel_difference_2d is
--
-- images are 865x577
--
-- ROI box size is 128x128
--
-- (865/2) - (128/2) = 368, "0101110000" (note: -1 for inclusive)
-- (865/2) + (128/2) = 496, "0111110000" (note: +1 for inclusive)
-- (577/2) - (128/2) = 224, "0011100000" (note: -1 for inclusive)
-- (577/2) + (128/2) = 352, "0101100000" (note: +1 for inclusive)
constant C_STARTPIXELCOUNT : STD_LOGIC_VECTOR(9 downto 0) := "0101111110";
constant C_STOPPIXELCOUNT : STD_LOGIC_VECTOR(9 downto 0) := "0111110001";
constant C_STARTLINECOUNT : STD_LOGIC_VECTOR(9 downto 0) := "0011111110";
constant C_STOPLINECOUNT : STD_LOGIC_VECTOR(9 downto 0) := "0101100001";
signal r_framevalidlast : STD_LOGIC;
signal r_linevalidlast : STD_LOGIC;
signal r_linecount : STD_LOGIC_VECTOR(9 downto 0);
signal r_pixelcount : STD_LOGIC_VECTOR(9 downto 0);
signal r_pixelvalid : STD_LOGIC := '0';
signal r_pixelvalid_last : STD_LOGIC := '0';
signal r_y : STD_LOGIC_VECTOR(7 downto 0);
signal r_y1 : STD_LOGIC_VECTOR(7 downto 0);
signal r_pixelsum : STD_LOGIC_VECTOR(31 downto 0);
signal r_dv : STD_LOGIC;
signal r_focusvalue : STD_LOGIC_VECTOR(31 downto 0);
type linetype is array( 0 to 128 ) of std_logic_vector(7 downto 0);
signal lastline : linetype := (others => "00000000");
--signal lineB : linetype;
--signal linepingpong : std_logic := '0';
signal roi_pixelcount : integer range 0 to 129 := 1;
begin
o_focusvalue <= r_focusvalue;
o_dv <= r_dv;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_framevalidlast <= '0';
r_linevalidlast <= '0';
else
r_framevalidlast <= i_framevalid;
r_linevalidlast <= i_linevalid;
end if;
end if;
end process;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_Y <= (others => '0');
r_Y1 <= (others => '0');
else
-- delayed 2 clocks to compensate for r_pixelvalid calculation
r_Y <= i_Y;
r_Y1 <= r_Y;
end if;
end if;
end process;
-- linecount
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_linecount <= (others => '0');
else
r_linecount <= r_linecount;
if ( r_framevalidlast = '0' and i_framevalid = '1' ) then
r_linecount <= (others => '0');
elsif ( i_framevalid = '1' ) then
r_linecount <= r_linecount + '1';
end if;
end if;
end if;
end process;
-- pixelcount
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_pixelcount <= (others => '0');
else
r_pixelcount <= r_pixelcount;
if ( r_linevalidlast = '0' and i_linevalid = '1' ) then
r_pixelcount <= (others => '0');
elsif ( i_framevalid = '1' ) then
r_pixelcount <= r_pixelcount + '1';
end if;
end if;
end if;
end process;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
else
r_pixelvalid <= '0';
if ( r_pixelcount > C_STARTPIXELCOUNT and r_pixelcount < C_STOPPIXELCOUNT and r_linecount > C_STARTLINECOUNT and r_linecount < C_STOPLINECOUNT ) then
r_pixelvalid <= '1';
end if;
r_pixelvalid_last <= r_pixelvalid;
end if;
end if;
end process;
-- pixelsum
process( i_clk )
variable xdiff : std_logic_vector(7 downto 0) := (others => '0');
variable ydiff : std_logic_vector(7 downto 0) := (others => '0');
begin
if ( rising_edge ( i_clk ) ) then
if ( i_reset = '1' ) then
r_pixelsum <= (others => '0');
--roi_pixelcount <= 1;
else
r_pixelsum <= r_pixelsum;
--roi_pixelcount <= roi_pixelcount;
if ( r_framevalidlast = '0' and i_framevalid = '1' ) and ( r_linevalidlast = '0' and i_linevalid = '1' ) then
r_pixelsum <= (others => '0');
else
if ( r_pixelvalid = '1' ) then
if ( r_Y > r_Y1 ) then
xdiff := (r_Y - r_Y1);
else
xdiff := (r_Y1 - r_Y);
end if;
if ( lastline(roi_pixelcount-1) > r_Y1 ) then
ydiff := (lastline(roi_pixelcount-1) - r_Y1);
else
ydiff := (r_Y1 - lastline(roi_pixelcount-1));
end if;
r_pixelsum <= r_pixelsum + ( ( xdiff * xdiff ) + ( xdiff * xdiff ) );
lastline(roi_pixelcount) <= r_Y1;
--roi_pixelcount <= roi_pixelcount + 1;
end if;
end if;
end if;
end if;
end process;
process( i_clk )
begin
if ( rising_edge ( i_clk ) ) then
if ( i_reset = '1' ) then
roi_pixelcount <= 1;
else
roi_pixelcount <= roi_pixelcount;
if ( r_pixelvalid = '0' ) then
roi_pixelcount <= 1;
else
--if ( (r_pixelvalid_last = '1' and r_pixelvalid = '0') or (r_pixelvalid_last = '0' and r_pixelvalid = '1') ) then
-- roi_pixelcount <= 1;
--else
roi_pixelcount <= roi_pixelcount + 1;
--end if;
end if;
end if;
end if;
end process;
process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_reset = '1' ) then
r_dv <= '0';
r_focusvalue <= (others => '0');
else
r_dv <= '0';
r_focusvalue <= r_focusvalue;
if ( r_pixelcount = C_STOPPIXELCOUNT and r_linecount = C_STOPLINECOUNT ) then
r_dv <= '1';
r_focusvalue <= r_pixelsum;
end if;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | 8e6ab335e28e0a8a00144937ad456488 | 0.583647 | 2.851707 | false | false | false | false |
sudov/options-accel | final_design/verilog/ieee_FP_pkg/float_pkg_c.vhd | 2 | 298,081 | -- --------------------------------------------------------------------
-- "float_pkg" package contains functions for floating point math.
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
-- use ieee_proposed.float_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 2.2 $
-- Date : $Date: 2010/09/22 18:26:46 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
package float_pkg is
-- generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
constant float_exponent_width : NATURAL := 8;
constant float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
constant float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
constant float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
constant float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
constant float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- Note that the size of the vector is not defined here, but in
-- the package which calls this one.
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
subtype U_float is UNRESOLVED_float;
subtype float is UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- a number between 1.0 and 2.0
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
-- ===========================================================================
-- string and textio Functions
-- ===========================================================================
-- rtl_synthesis off
-- pragma synthesis_off
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;
end package float_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT float_pkg package
-- This version is optimized for Synthesis, and not for simulation.
-- Note that there are functional differences between the synthesis and
-- simulation packages bodies. The Synthesis version is preferred.
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 2.2 $
-- Date : $Date: 2010/09/22 18:26:46 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
package body float_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- %%% Replicated functions
-- These functions are replicated so that we don't need to reference the new
-- 2006 package std.standard, std_logic_1164 and numeric_std.
function maximum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
function or_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : STD_LOGIC_VECTOR)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function and_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function and_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
function find_leftmost (ARG : UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
function Is_X (s : UNSIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X (s : SIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or_reduce (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or_reduce (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and_reduce (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report float_pkg'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or_reduce (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
-- Converts an fp into an SLV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector (to_sulv (arg));
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or_reduce (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or_reduce(fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report float_pkg'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and_reduce (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or_reduce (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED;
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- 1 downto -fraction_width
expon : out SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or_reduce (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or_reduce (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or_reduce (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or_reduce (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or_reduce (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r;
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or_reduce (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report float_pkg'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or_reduce (urfract (fraction_width-1 downto 0)) = '0')
report float_pkg'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
cfptype := classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_x01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or_reduce (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or_reduce (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or_reduce (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (is_negative (l)) then
remres := - remres;
end if;
if (is_negative (l) = is_negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function \?=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable round : BOOLEAN;
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
variable passguard : NATURAL;
begin
fptype := classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and_reduce (fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable arg_int : UNSIGNED(xarg'range); -- Real version of argument
variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (xarg) then
result := (others => 'X');
elsif (xarg = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(xarg (xarg'high));
arg_int := UNSIGNED(abs (to_01(xarg)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width + 1 downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or_reduce (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable result : SIGNED (size-1 downto 0);
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable result : UNSIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable result : SIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- real and float
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- integer and float
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
constant expon_base : SIGNED (exponent_width-1 downto 0)
:= gen_expon_base(exponent_width); -- exponent offset
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return SIGNED is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := classfp (x, check_error);
validfpy := classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := classfp (x);
rfptype := classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- rtl_synthesis off
-- pragma synthesis_off
--%%% these functions are copied from std_logic_1164 (VHDL-200X edition)
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- %%% Replicated textio functions
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
-- %%% END replicated textio functions
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= value'low) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
report float_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = value'high-1) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
good := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
-- rtl_synthesis on
-- pragma synthesis_on
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
exponent_width => exponent_width,
fraction_width => fraction_width);
end function to_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_slv (result);
end function realtobits;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
end package body float_pkg;
| apache-2.0 | 040ce2e46a6d9a9374b544a7bc7aac72 | 0.556798 | 4.22217 | false | false | false | false |
iamllama/EE2020 | ee2020.cache/ip/b67405368c510ef2/dds_compiler_0_sim_netlist.vhdl | 1 | 218,009 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Mar 28 05:22:49 2017
-- Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_sim_netlist.vhdl
-- Design : dds_compiler_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`protect key_block
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1Ii0/OYJsQ==
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
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`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 136080)
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 8;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "artix7";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 11 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 22;
attribute C_AMPLITUDE of i_synth : label is 1;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 8;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS of i_synth : label is 10000;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL of i_synth : label is 1;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 0;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH of i_synth : label is 12;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 12;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 24;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "artix7";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(21) <= \<const0>\;
debug_axi_pinc_in(20) <= \<const0>\;
debug_axi_pinc_in(19) <= \<const0>\;
debug_axi_pinc_in(18) <= \<const0>\;
debug_axi_pinc_in(17) <= \<const0>\;
debug_axi_pinc_in(16) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(21) <= \<const0>\;
debug_axi_poff_in(20) <= \<const0>\;
debug_axi_poff_in(19) <= \<const0>\;
debug_axi_poff_in(18) <= \<const0>\;
debug_axi_poff_in(17) <= \<const0>\;
debug_axi_poff_in(16) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(21) <= \<const0>\;
debug_phase(20) <= \<const0>\;
debug_phase(19) <= \<const0>\;
debug_phase(18) <= \<const0>\;
debug_phase(17) <= \<const0>\;
debug_phase(16) <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tdata(15) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(14) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(13) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(12) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(11 downto 0) <= \^m_axis_data_tdata\(11 downto 0);
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const1>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13_viv
port map (
aclk => aclk,
aclken => '0',
aresetn => '0',
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15) => \^m_axis_data_tdata\(11),
m_axis_data_tdata(14 downto 11) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14 downto 11),
m_axis_data_tdata(10 downto 0) => \^m_axis_data_tdata\(10 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 22) => B"00",
s_axis_phase_tdata(21 downto 0) => s_axis_phase_tdata(21 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "dds_compiler_0,dds_compiler_v6_0_13,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "dds_compiler_v6_0_13,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of U0 : label is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of U0 : label is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of U0 : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of U0 : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of U0 : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of U0 : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of U0 : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of U0 : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of U0 : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of U0 : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of U0 : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of U0 : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 8;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of U0 : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of U0 : label is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of U0 : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of U0 : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of U0 : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of U0 : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of U0 : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of U0 : label is 1;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of U0 : label is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of U0 : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of U0 : label is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of U0 : label is 12;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of U0 : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of U0 : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of U0 : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of U0 : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of U0 : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of U0 : label is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
debug_axi_chan_in(0) => NLW_U0_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_U0_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_U0_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_U0_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_U0_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_U0_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_U0_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_U0_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_U0_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_U0_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_U0_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0),
m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_U0_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_U0_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_U0_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_U0_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 0) => s_axis_phase_tdata(23 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
| gpl-3.0 | 2636b1e45777b857f7257e996b24adeb | 0.917774 | 1.928242 | false | false | false | false |
Hyvok/HardHeat | src/deadtime_gen.vhd | 1 | 1,459 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity deadtime_gen is
generic
(
-- Number of bits in the counter
DT_N : positive;
-- Amount of deadtime
DT_VAL : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
sig_in : in std_logic;
sig_out : out std_logic;
sig_n_out : out std_logic
);
end entity;
architecture rtl of deadtime_gen is
begin
dt_gen_p: process(clk, reset)
variable count : unsigned(DT_N - 1 downto 0);
variable off : std_logic;
variable last_state : std_logic;
begin
if reset = '1' then
sig_out <= '0';
sig_n_out <= '0';
off := '0';
last_state := '0';
count := (others => '0');
elsif rising_edge(clk) then
if sig_in = last_state then
count := count + 1;
else
count := (others => '0');
end if;
if count <= DT_VAL then
off := '1';
else
off := '0';
end if;
if sig_in = '1' then
sig_out <= off;
else
sig_n_out <= off;
end if;
last_state := sig_in;
end if;
end process;
end;
| mit | 59ae1973dae690a86dcdda568d5d75a1 | 0.412611 | 4.075419 | false | false | false | false |
upci/upci | Projeto/ir.vhd | 1 | 1,467 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.processor_functions.all;
ENTITY ir IS
PORT (clk : IN STD_LOGIC; -- sinal de clock
nrst : IN STD_LOGIC; -- reset ativo em zero
IR_load : IN STD_LOGIC; -- indica se o IR esta no modo load
IR_valid : IN STD_LOGIC; -- indica se o IR esta ativo
IR_opcode : OUT opcode; -- sinal de saida com o opcode decodificado
IR_bus : INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0); -- acesso ao barramento externo
IR_opcode_leds: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY IR;
ARCHITECTURE RTL OF IR IS
SIGNAL IR_internal : STD_LOGIC_VECTOR (n-1 DOWNTO 0); -- sinal interno do IR
BEGIN
-- O IR, por padrao, eh configurado no modo address (passar valor interno para saida)
-- caso valid = 0, saida no barramento deve ir para Z
IR_bus <= IR_internal
WHEN IR_valid = '1'
ELSE (OTHERS => 'Z');
-- O opcode de saida deve ser decodificado assincronamente quando o valor no IR mudar.
IR_opcode <= Decode(IR_internal);
IR_opcode_leds <= IR_internal(n-1 DOWNTO n-oplen);
PROCESS (clk, nrst) IS
BEGIN
-- Se reset for para 0, o valor do registrador interno deve ir para 0s.
IF nrst = '0' THEN
IR_internal <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
IF IR_load = '1' THEN
IR_internal <= IR_bus; -- na borda de subida, o valor do barramento deve ser enviado para o registrador interno (modo load)
END IF;
END IF;
END PROCESS;
END ARCHITECTURE RTL; | gpl-2.0 | 1738bf82400c5cba0cff526d98cb417a | 0.672131 | 3.275168 | false | false | false | false |
Hyvok/HardHeat | sim/pwm/pwm_tb.vhd | 1 | 1,547 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_tb is
end entity;
architecture rtl of pwm_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal enable : std_logic;
signal mod_lvl : unsigned(12 - 1 downto 0);
signal mod_lvl_f : std_logic;
begin
reset <= '1', '0' after 500 ns;
enable <= '1';
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
DUT_inst: entity work.pwm(rtl)
generic map
(
COUNTER_N => 12,
MIN_MOD_LVL => 2**12 / 5,
ENABLE_ON_D => 100
)
port map
(
clk => clk,
reset => reset,
enable_in => enable,
mod_lvl_in => mod_lvl,
mod_lvl_f_in => mod_lvl_f
);
mod_lvl_gen: process(clk)
variable timer : unsigned(12 - 1 downto 0);
begin
if reset = '1' then
timer := (others => '0');
mod_lvl <= to_unsigned(2**12 / 2, mod_lvl'length);
mod_lvl_f <= '0';
elsif rising_edge(clk) then
mod_lvl_f <= '0';
if timer = 2**12 - 1 then
mod_lvl <= mod_lvl - 1;
mod_lvl_f <= '1';
end if;
timer := timer + 1;
end if;
end process;
end;
| mit | b59df2c733e5cd316c6d54aa4849e347 | 0.458306 | 3.589327 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/i2c_master_init.vhd | 2 | 5,691 | -- this is use to initilize the I2C pass through configuration need to communicate with remote I2C devices.
-- this runs on the host PC side.
-- by: Jie (Jack) Zhang MWL-MIT
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity i2c_master_init is
port (
clk : in std_logic; --same clock for the i2c interface
reset : in std_logic;
busy : in std_logic;
ack_error : in std_logic;
i2c_ena_o : out std_logic;
rw_o : out std_logic;
device_id_o : out std_logic_vector(6 downto 0);
addr_o : out std_logic_vector(7 downto 0);
value_o : out std_logic_vector(7 downto 0);
user_rw : in std_logic;
user_device_id : in std_logic_vector(6 downto 0);
user_addr : in std_logic_vector(7 downto 0);
user_value : in std_logic_vector(7 downto 0)
);
end i2c_master_init;
architecture Behavioral of i2c_master_init is
--state machine
type init_sm_type is (IDLE, CONF, TX, ACKERR, CONFBUSY, TXBUSY);
signal init_sm, init_sm_next : init_sm_type;
--signals
signal addr, addr_next : std_logic_vector(7 downto 0);
signal value, value_next : std_logic_vector(7 downto 0);
signal device_id, device_id_next : std_logic_vector(6 downto 0);
signal i2c_ena, i2c_ena_next : std_logic;
signal rw, rw_next : std_logic;
--counters
signal confcnt, confcnt_next : unsigned(3 downto 0); --state counter
constant CONF_SIZE : integer := 6;
type addr_value_rom_type is array (0 to CONF_SIZE - 1) of std_logic_vector(7 downto 0);
type deviceid_rom_type is array (0 to CONF_SIZE - 1) of std_logic_vector(6 downto 0);
constant ADDR_ROM : addr_value_rom_type := (
"00100001", --0x21 (des)
"00000111", --0x7 (des) (serializer alias)
"00001000", --0x8 (des)
"00010000", --0x10 (des)
"00010001", --0x11 (ser)
"00010010" --0x12 (ser)
);
constant VALUE_ROM : addr_value_rom_type := (
"00010111", --7: I2C passthrough (1) 6:4 I2C SDA hold (001) 3:0 I2C filter depth (0111)
"10110000", --0x58<<1 ser alias
"10100000", --0x50<<1 slave device ID
"10100000", --0x50<<1 slave device alias
"01100100", --0x64 for 100KHz SCL rate (high time)
"01100100" --0x64 for 100KHz SCL rate (low time)
);
constant DEVICEID_ROM : deviceid_rom_type := (
"1100000", --"1100000": DES ID "1011000": SER ID
"1100000", --des
"1100000", --des
"1100000", --des
"1011000", --ser
"1011000" --ser
);
begin
device_id_o <= device_id;
addr_o <= addr;
value_o <= value;
i2c_ena_o <= i2c_ena;
rw_o <= rw;
init_proc : process (clk, reset)
begin
if (reset = '1') then
init_sm <= IDLE;
confcnt <= (others => '0');
addr <= (others => '0');
value <= (others => '0');
device_id <= (others => '0');
i2c_ena <= '0';
rw <= '0';
elsif (rising_edge(clk)) then
init_sm <= init_sm_next;
confcnt <= confcnt_next;
addr <= addr_next;
value <= value_next;
device_id <= device_id_next;
i2c_ena <= i2c_ena_next;
rw <= rw_next;
end if;
end process;
init_proc_next : process (clk, reset, rw, user_rw, init_sm, confcnt, i2c_ena, busy, ack_error, value, addr, device_id, user_addr, user_value, user_device_id)
begin
case init_sm is
when IDLE =>
if busy = '0' then
init_sm_next <= CONF;
else
init_sm_next <= IDLE;
end if;
i2c_ena_next <= '0';
confcnt_next <= (others => '0');
addr_next <= (others => '0');
value_next <= (others => '0');
device_id_next <= (others => '0');
rw_next <= '0';
when CONF =>
i2c_ena_next <= '1'; --assert i2c enable signal
rw_next <= '0'; --this is a write
confcnt_next <= confcnt;
if busy = '1' then
init_sm_next <= CONFBUSY;
else
init_sm_next <= CONF;
end if;
addr_next <= ADDR_ROM(to_integer(confcnt));
value_next <= VALUE_ROM(to_integer(confcnt));
device_id_next <= DEVICEID_ROM(to_integer(confcnt));
when CONFBUSY =>
i2c_ena_next <= '0'; --disable enable pin
rw_next <= rw;
if ack_error = '1' then
init_sm_next <= ACKERR;
confcnt_next <= confcnt; --do not increment this
elsif busy = '0' then --wait for busy go to low
if (confcnt = CONF_SIZE - 1) then
init_sm_next <= TX; --configuration is done
confcnt_next <= confcnt;
else
init_sm_next <= CONF; --continue other configuration
confcnt_next <= confcnt + 1; --increment the conf counter
end if;
else
init_sm_next <= CONFBUSY;
confcnt_next <= confcnt;
end if;
addr_next <= addr;
value_next <= value;
device_id_next <= device_id;
when ACKERR =>
if busy = '0' then
init_sm_next <= CONF;
else
init_sm_next <= ACKERR;
end if;
confcnt_next <= confcnt;
i2c_ena_next <= i2c_ena;
addr_next <= addr;
value_next <= value;
device_id_next <= device_id;
rw_next <= rw;
when TX =>
i2c_ena_next <= '1'; --assert i2c enable signal
confcnt_next <= confcnt;
if busy = '1' then
init_sm_next <= TXBUSY;
else
init_sm_next <= TX;
end if;
rw_next <= user_rw;
addr_next <= user_addr;
value_next <= user_value;
device_id_next <= user_device_id;
when TXBUSY =>
i2c_ena_next <= '0';
if busy = '0' then --wait for busy to drop low
init_sm_next <= TX;
else
init_sm_next <= TXBUSY;
end if;
rw_next <= rw;
addr_next <= addr;
value_next <= value;
device_id_next <= device_id;
confcnt_next <= confcnt;
end case;
end process;
end Behavioral; | mit | 118cb4f9519e6cdc9cf9078138abafac | 0.579336 | 2.893238 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/uart.vhd | 1 | 25,117 | --------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART PARITY BIT GENERATOR
-- AUTHORS: Jakub Cabal <[email protected]>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_PARITY is
Generic (
DATA_WIDTH : integer := 8;
PARITY_TYPE : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
PARITY_OUT : out std_logic
);
end UART_PARITY;
architecture FULL of UART_PARITY is
begin
-- -------------------------------------------------------------------------
-- PARITY BIT GENERATOR
-- -------------------------------------------------------------------------
even_parity_g : if (PARITY_TYPE = "even") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '0';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
odd_parity_g : if (PARITY_TYPE = "odd") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '1';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
mark_parity_g : if (PARITY_TYPE = "mark") generate
PARITY_OUT <= '1';
end generate;
space_parity_g : if (PARITY_TYPE = "space") generate
PARITY_OUT <= '0';
end generate;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART RECEIVER
-- AUTHORS: Jakub Cabal <[email protected]>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_RX is
Generic (
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_RXD : in std_logic;
-- USER DATA OUTPUT INTERFACE
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
);
end UART_RX;
architecture FULL of UART_RX is
signal rx_clk_en : std_logic;
signal rx_ticks : unsigned(3 downto 0);
signal rx_clk_divider_en : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_bit_count : unsigned(2 downto 0);
signal rx_bit_count_en : std_logic;
signal rx_data_shreg_en : std_logic;
signal rx_parity_bit : std_logic;
signal rx_parity_error : std_logic;
signal rx_parity_check_en : std_logic;
signal rx_output_reg_en : std_logic;
type state is (idle, startbit, databits, paritybit, stopbit);
signal rx_pstate : state;
signal rx_nstate : state;
begin
-- -------------------------------------------------------------------------
-- UART RECEIVER CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_rx_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (rx_clk_divider_en = '1') then
if (uart_clk_en = '1') then
if (rx_ticks = "1111") then
rx_ticks <= (others => '0');
rx_clk_en <= '0';
elsif (rx_ticks = "0111") then
rx_ticks <= rx_ticks + 1;
rx_clk_en <= '1';
else
rx_ticks <= rx_ticks + 1;
rx_clk_en <= '0';
end if;
else
rx_ticks <= rx_ticks;
rx_clk_en <= '0';
end if;
else
rx_ticks <= (others => '0');
rx_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER BIT COUNTER
-- -------------------------------------------------------------------------
uart_rx_bit_counter : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_bit_count <= (others => '0');
elsif (rx_bit_count_en = '1' AND rx_clk_en = '1') then
if (rx_bit_count = "111") then
rx_bit_count <= (others => '0');
else
rx_bit_count <= rx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER DATA SHIFT REGISTER
-- -------------------------------------------------------------------------
uart_rx_data_shift_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_data <= (others => '0');
elsif (rx_clk_en = '1' AND rx_data_shreg_en = '1') then
rx_data <= UART_RXD & rx_data(7 downto 1);
end if;
end if;
end process;
DATA_OUT <= rx_data;
-- -------------------------------------------------------------------------
-- UART RECEIVER PARITY GENERATOR AND CHECK
-- -------------------------------------------------------------------------
uart_rx_parity_g : if (PARITY_BIT /= "none") generate
uart_rx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => rx_data,
PARITY_OUT => rx_parity_bit
);
uart_rx_parity_check_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_parity_error <= '0';
elsif (rx_parity_check_en = '1') then
rx_parity_error <= rx_parity_bit XOR UART_RXD;
end if;
end if;
end process;
end generate;
uart_rx_noparity_g : if (PARITY_BIT = "none") generate
rx_parity_error <= '0';
end generate;
-- -------------------------------------------------------------------------
-- UART RECEIVER OUTPUT REGISTER
-- -------------------------------------------------------------------------
uart_rx_output_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
DATA_VLD <= '0';
FRAME_ERROR <= '0';
else
if (rx_output_reg_en = '1') then
DATA_VLD <= NOT rx_parity_error AND UART_RXD;
FRAME_ERROR <= NOT UART_RXD;
else
DATA_VLD <= '0';
FRAME_ERROR <= '0';
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RECEIVER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rx_pstate <= idle;
else
rx_pstate <= rx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (rx_pstate, UART_RXD, rx_clk_en, rx_bit_count)
begin
case rx_pstate is
when idle =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '0';
rx_parity_check_en <= '0';
if (UART_RXD = '0') then
rx_nstate <= startbit;
else
rx_nstate <= idle;
end if;
when startbit =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if (rx_clk_en = '1') then
rx_nstate <= databits;
else
rx_nstate <= startbit;
end if;
when databits =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '1';
rx_data_shreg_en <= '1';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if ((rx_clk_en = '1') AND (rx_bit_count = "111")) then
if (PARITY_BIT = "none") then
rx_nstate <= stopbit;
else
rx_nstate <= paritybit;
end if ;
else
rx_nstate <= databits;
end if;
when paritybit =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '1';
if (rx_clk_en = '1') then
rx_nstate <= stopbit;
else
rx_nstate <= paritybit;
end if;
when stopbit =>
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '1';
rx_parity_check_en <= '0';
if (rx_clk_en = '1') then
rx_nstate <= idle;
rx_output_reg_en <= '1';
else
rx_nstate <= stopbit;
rx_output_reg_en <= '0';
end if;
when others =>
rx_output_reg_en <= '0';
rx_bit_count_en <= '0';
rx_data_shreg_en <= '0';
rx_clk_divider_en <= '0';
rx_parity_check_en <= '0';
rx_nstate <= idle;
end case;
end process;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART TRANSMITTER
-- AUTHORS: Jakub Cabal <[email protected]>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_TX is
Generic (
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_TXD : out std_logic;
-- USER DATA INPUT INTERFACE
DATA_IN : in std_logic_vector(7 downto 0);
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
BUSY : out std_logic -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
);
end UART_TX;
architecture FULL of UART_TX is
signal tx_clk_en : std_logic;
signal tx_clk_divider_en : std_logic;
signal tx_ticks : unsigned(3 downto 0);
signal tx_data : std_logic_vector(7 downto 0);
signal tx_bit_count : unsigned(2 downto 0);
signal tx_bit_count_en : std_logic;
signal tx_busy : std_logic;
signal tx_parity_bit : std_logic;
signal tx_data_out_sel : std_logic_vector(1 downto 0);
type state is (idle, txsync, startbit, databits, paritybit, stopbit);
signal tx_pstate : state;
signal tx_nstate : state;
begin
BUSY <= tx_busy;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_tx_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (tx_clk_divider_en = '1') then
if (uart_clk_en = '1') then
if (tx_ticks = "1111") then
tx_ticks <= (others => '0');
tx_clk_en <= '0';
elsif (tx_ticks = "0001") then
tx_ticks <= tx_ticks + 1;
tx_clk_en <= '1';
else
tx_ticks <= tx_ticks + 1;
tx_clk_en <= '0';
end if;
else
tx_ticks <= tx_ticks;
tx_clk_en <= '0';
end if;
else
tx_ticks <= (others => '0');
tx_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER INPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_input_data_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_data <= (others => '0');
elsif (DATA_SEND = '1' AND tx_busy = '0') then
tx_data <= DATA_IN;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER BIT COUNTER
-- -------------------------------------------------------------------------
uart_tx_bit_counter : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_bit_count <= (others => '0');
elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
if (tx_bit_count = "111") then
tx_bit_count <= (others => '0');
else
tx_bit_count <= tx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER PARITY GENERATOR
-- -------------------------------------------------------------------------
uart_tx_parity_g : if (PARITY_BIT /= "none") generate
uart_tx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => tx_data,
PARITY_OUT => tx_parity_bit
);
end generate;
uart_tx_noparity_g : if (PARITY_BIT = "none") generate
tx_parity_bit <= 'Z';
end generate;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER OUTPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_output_data_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
UART_TXD <= '1';
else
case tx_data_out_sel is
when "01" => -- START BIT
UART_TXD <= '0';
when "10" => -- DATA BITS
UART_TXD <= tx_data(to_integer(tx_bit_count));
when "11" => -- PARITY BIT
UART_TXD <= tx_parity_bit;
when others => -- STOP BIT OR IDLE
UART_TXD <= '1';
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_pstate <= idle;
else
tx_pstate <= tx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (tx_pstate, DATA_SEND, tx_clk_en, tx_bit_count)
begin
case tx_pstate is
when idle =>
tx_busy <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '0';
if (DATA_SEND = '1') then
tx_nstate <= txsync;
else
tx_nstate <= idle;
end if;
when txsync =>
tx_busy <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= startbit;
else
tx_nstate <= txsync;
end if;
when startbit =>
tx_busy <= '1';
tx_data_out_sel <= "01";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= databits;
else
tx_nstate <= startbit;
end if;
when databits =>
tx_busy <= '1';
tx_data_out_sel <= "10";
tx_bit_count_en <= '1';
tx_clk_divider_en <= '1';
if ((tx_clk_en = '1') AND (tx_bit_count = "111")) then
if (PARITY_BIT = "none") then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if ;
else
tx_nstate <= databits;
end if;
when paritybit =>
tx_busy <= '1';
tx_data_out_sel <= "11";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (tx_clk_en = '1') then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if;
when stopbit =>
tx_busy <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '1';
if (DATA_SEND = '1') then
tx_nstate <= txsync;
elsif (tx_clk_en = '1') then
tx_nstate <= idle;
else
tx_nstate <= stopbit;
end if;
when others =>
tx_busy <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_divider_en <= '0';
tx_nstate <= idle;
end case;
end process;
end FULL;
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- MODULE: UART TOP MODULE
-- AUTHORS: Jakub Cabal <[email protected]>
-- lICENSE: The MIT License (MIT)
-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- UART FOR FPGA REQUIRES: 1 START BIT, 8 DATA BITS, 1 STOP BIT!!!
-- OTHER PARAMETERS CAN BE SET USING GENERICS.
entity UART is
Generic (
CLK_FREQ : integer := 50e6; -- set system clock frequency in Hz
BAUD_RATE : integer := 115200; -- baud rate value
PARITY_BIT : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- USER DATA INPUT INTERFACE
DATA_IN : in std_logic_vector(7 downto 0);
DATA_SEND : in std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
BUSY : out std_logic; -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
-- USER DATA OUTPUT INTERFACE
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_VLD : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
);
end UART;
architecture FULL of UART is
constant divider_value : integer := CLK_FREQ/(16*BAUD_RATE);
signal uart_ticks : integer range 0 to divider_value-1;
signal uart_clk_en : std_logic;
signal uart_rxd_shreg : std_logic_vector(3 downto 0);
signal uart_rxd_debounced : std_logic;
begin
-- -------------------------------------------------------------------------
-- UART OVERSAMPLING CLOCK DIVIDER
-- -------------------------------------------------------------------------
uart_oversampling_clk_divider : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_ticks <= 0;
uart_clk_en <= '0';
elsif (uart_ticks = divider_value-1) then
uart_ticks <= 0;
uart_clk_en <= '1';
else
uart_ticks <= uart_ticks + 1;
uart_clk_en <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART RXD DEBAUNCER
-- -------------------------------------------------------------------------
uart_rxd_debouncer : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
uart_rxd_shreg <= (others => '1');
uart_rxd_debounced <= '1';
else
uart_rxd_shreg <= UART_RXD & uart_rxd_shreg(3 downto 1);
uart_rxd_debounced <= uart_rxd_shreg(0) OR
uart_rxd_shreg(1) OR
uart_rxd_shreg(2) OR
uart_rxd_shreg(3);
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER
-- -------------------------------------------------------------------------
uart_tx_i: entity work.UART_TX
generic map (
PARITY_BIT => PARITY_BIT
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_CLK_EN => uart_clk_en,
UART_TXD => UART_TXD,
-- USER DATA INPUT INTERFACE
DATA_IN => DATA_IN,
DATA_SEND => DATA_SEND,
BUSY => BUSY
);
-- -------------------------------------------------------------------------
-- UART RECEIVER
-- -------------------------------------------------------------------------
uart_rx_i: entity work.UART_RX
generic map (
PARITY_BIT => PARITY_BIT
)
port map (
CLK => CLK,
RST => RST,
-- UART INTERFACE
UART_CLK_EN => uart_clk_en,
UART_RXD => uart_rxd_debounced,
-- USER DATA OUTPUT INTERFACE
DATA_OUT => DATA_OUT,
DATA_VLD => DATA_VLD,
FRAME_ERROR => FRAME_ERROR
);
end FULL;
| gpl-3.0 | 6cff809a04c819ea4b6408c10f14f5d9 | 0.388223 | 4.554306 | false | false | false | false |
zhlinh/vhdl_course | Assignment/CHK_3BIT/CHK_3BIT.vhd | 1 | 2,917 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHK_3BIT IS
PORT(DIN:IN STD_LOGIC;
CLK,RESET:IN STD_LOGIC;
BIT3:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DOUT:OUT STD_LOGIC);
END ENTITY CHK_3BIT;
ARCHITECTURE ART1 OF CHK_3BIT IS
TYPE STATETYPE IS(S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15);
SIGNAL PRESENT_STATE,NEXT_STATE:STATETYPE;
SIGNAL CHOSEN_SEQ:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
BEGIN
CHOOSE:PROCESS(BIT3)
BEGIN
--使用case语句时一定要列举完所有情况(善于应用others)，否则编译通过但仿真通不过
CASE BIT3 IS
WHEN "000"=>CHOSEN_SEQ<="00000001";
WHEN "001"=>CHOSEN_SEQ<="00000010";
WHEN "010"=>CHOSEN_SEQ<="00000100";
WHEN "011"=>CHOSEN_SEQ<="00001000";
WHEN "100"=>CHOSEN_SEQ<="00010000";
WHEN "101"=>CHOSEN_SEQ<="00100000";
WHEN "110"=>CHOSEN_SEQ<="01000000";
WHEN "111"=>CHOSEN_SEQ<="10000000";
WHEN OTHERS =>CHOSEN_SEQ<="00000000";
END CASE;
END PROCESS;
COMB:PROCESS(PRESENT_STATE,DIN,CHOSEN_SEQ)
BEGIN
CASE PRESENT_STATE IS
WHEN S1=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S2;
ELSE
NEXT_STATE<=S3;
END IF;
WHEN S2=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S4;
ELSE
NEXT_STATE<=S5;
END IF;
WHEN S3=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S6;
ELSE
NEXT_STATE<=S7;
END IF;
WHEN S4=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S8;
ELSE
NEXT_STATE<=S9;
END IF;
WHEN S5=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S10;
ELSE
NEXT_STATE<=S11;
END IF;
WHEN S6=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S12;
ELSE
NEXT_STATE<=S13;
END IF;
WHEN S7=>DOUT<='0';
IF DIN='0'THEN
NEXT_STATE<=S14;
ELSE
NEXT_STATE<=S15;
END IF;
WHEN S8=>DOUT<=CHOSEN_SEQ(0);
IF DIN='0'THEN
NEXT_STATE<=S8;
ELSE
NEXT_STATE<=S9;
END IF;
WHEN S9=>DOUT<=CHOSEN_SEQ(1);
IF DIN='0'THEN
NEXT_STATE<=S10;
ELSE
NEXT_STATE<=S11;
END IF;
WHEN S10=>DOUT<=CHOSEN_SEQ(2);
IF DIN='0'THEN
NEXT_STATE<=S12;
ELSE
NEXT_STATE<=S13;
END IF;
WHEN S11=>DOUT<=CHOSEN_SEQ(3);
IF DIN='0'THEN
NEXT_STATE<=S14;
ELSE
NEXT_STATE<=S15;
END IF;
WHEN S12=>DOUT<=CHOSEN_SEQ(4);
IF DIN='0'THEN
NEXT_STATE<=S8;
ELSE
NEXT_STATE<=S9;
END IF;
WHEN S13=>DOUT<=CHOSEN_SEQ(5);
IF DIN='0'THEN
NEXT_STATE<=S10;
ELSE
NEXT_STATE<=S11;
END IF;
WHEN S14=>DOUT<=CHOSEN_SEQ(6);
IF DIN='0'THEN
NEXT_STATE<=S12;
ELSE
NEXT_STATE<=S13;
END IF;
WHEN S15=>DOUT<=CHOSEN_SEQ(7);
IF DIN='0'THEN
NEXT_STATE<=S14;
ELSE
NEXT_STATE<=S15;
END IF;
END CASE;
END PROCESS;
CLOCK:PROCESS(CLK,RESET)
BEGIN
IF(RESET='1')THEN
PRESENT_STATE<=S1;
ELSIF(CLK'EVENT AND CLK='1')THEN
PRESENT_STATE<=NEXT_STATE;
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | 3184b70b1318a1164d895df7c1965772 | 0.594462 | 2.436379 | false | false | false | false |
JeremySavonet/Eurobot-2017-Moon-Village | software/HPS_FPGA_LED/fpga/debounce.vhd | 1 | 2,422 | --------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 3/26/2012 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic;
| gpl-3.0 | afe42aa588d68616fb6645cb237697fe | 0.59455 | 4.126065 | false | false | false | false |
Hyvok/HardHeat | src/utils.vhd | 1 | 3,726 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package utils_pkg is
function log2(Arg : natural) return natural;
function ceil_log2(Arg : natural) return natural;
function shift_right_vec(Arg : std_logic_vector; Num : positive)
return std_logic_vector;
function shift_left_vec(Arg : std_logic_vector; Num : positive)
return std_logic_vector;
function shift_right_vec( Arg : std_logic_vector;
Num : positive;
NewBit : std_logic)
return std_logic_vector;
function shift_left_vec( Arg : std_logic_vector;
Num : positive;
NewBit : std_logic)
return std_logic_vector;
end package;
package body utils_pkg is
---------------------------------------------------------------------------
-- Function for calculating the base-2 logarithm
---------------------------------------------------------------------------
function log2(Arg : natural) return natural is
variable temp : integer := Arg;
variable ret_val : integer := 0;
begin
while temp > 1 loop
ret_val := ret_val + 1;
temp := temp / 2;
end loop;
return ret_val;
end function;
---------------------------------------------------------------------------
-- Function for calculating the minimum number of bits to represent Arg
---------------------------------------------------------------------------
function ceil_log2(Arg : natural) return natural is
variable RetVal : natural;
begin
RetVal := log2(Arg);
-- Round up
if (Arg > (2**RetVal)) then
return(RetVal + 1);
else
return(RetVal);
end if;
end function;
---------------------------------------------------------------------------
-- Shift an std_logic_vector right
---------------------------------------------------------------------------
function shift_right_vec(Arg : std_logic_vector; Num : positive)
return std_logic_vector is
begin
return(std_logic_vector(shift_right(unsigned(Arg), Num)));
end function;
---------------------------------------------------------------------------
-- Shift an std_logic_vector left
---------------------------------------------------------------------------
function shift_left_vec(Arg : std_logic_vector; Num : positive)
return std_logic_vector is
begin
return(std_logic_vector(shift_left(unsigned(Arg), Num)));
end function;
---------------------------------------------------------------------------
-- Shift an std_logic_vector right and put new bit to 'high
---------------------------------------------------------------------------
function shift_right_vec( Arg : std_logic_vector;
Num : positive;
NewBit : std_logic) return std_logic_vector is
variable vec : std_logic_vector(Arg'range);
begin
vec := std_logic_vector(shift_right(unsigned(Arg), Num));
vec(vec'high) := NewBit;
return(vec);
end function;
---------------------------------------------------------------------------
-- Shift an std_logic_vector left and put new bit to 'low
---------------------------------------------------------------------------
function shift_left_vec( Arg : std_logic_vector;
Num : positive;
NewBit : std_logic) return std_logic_vector is
variable vec : std_logic_vector(Arg'range);
begin
vec := std_logic_vector(shift_left(unsigned(Arg), Num));
vec(vec'low) := NewBit;
return(vec);
end function;
end package body;
| mit | b20b6c414af5e07ae32b72810ff5c0fe | 0.451422 | 4.698613 | false | false | false | false |
aylons/concordic | hdl/modules/cordic_core/inversion_stage.vhd | 1 | 3,539 | -------------------------------------------------------------------------------
-- Title : Inversion stage
-- Project :
-------------------------------------------------------------------------------
-- File : inversion_stage.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-09
-- Last update: 2014-09-29
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The CORDIC algorithm only converges to the proper value if the
-- initial point to be converted is in the right half plane. So, if the point is in
-- the left halfplane, rotate it 180o and apply the rotation value .
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-09 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
entity inversion_stage is
generic (
g_mode : string := "rect_to_polar"
);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
rst_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed;
valid_o : out std_logic := '0'
);
end entity inversion_stage;
-------------------------------------------------------------------------------
architecture str of inversion_stage is
constant width : integer := z_i'length;
constant rotation_angle : signed := to_signed(integer(-2**(width-1)), width);
-- rotate 180o
begin -- architecture str
process(clk_i) is
variable left_halfplane : boolean := false;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
x_o <= (x_o'length-1 downto 0 => '0');
y_o <= (y_o'length-1 downto 0 => '0');
z_o <= (z_o'length-1 downto 0 => '0');
valid_o <= '0';
else
if ce_i = '1' then
left_halfplane := (x_i < 0);
if left_halfplane then
x_o <= -x_i;
y_o <= -y_i;
z_o <= rotation_angle;
else
x_o <= x_i;
y_o <= y_i;
z_o <= to_signed(0, width);
end if; -- left_halfplane
valid_o <= valid_i;
end if; --clock enable
end if; --reset
end if; --rising edge
end process;
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 | 39952759fa2fed8f47fb0be8dd4c8d71 | 0.474145 | 4.163529 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/ipcore_dir/pll/example_design/pll_exdes.vhd | 2 | 6,041 | -- file: pll_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll_exdes;
architecture xilinx of pll_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : pll
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int,
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
| mit | 24efa5ab17a62c22d1839ed57f6c9924 | 0.592121 | 4.046216 | false | false | false | false |
upci/upci | Projeto/clock_divisor.vhd | 1 | 956 | -------- Clock Divisor -----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.processor_functions.all;
----------------------------------------------------------------------------------
ENTITY clock_divisor IS
PORT (clk, nrst : IN STD_LOGIC; -- clock de entrada, que é o de 25MHz da placa
clk_out : BUFFER STD_LOGIC); -- clock de saída, configurável pelo "clk_frequency" de "processor_functions"
END ENTITY clock_divisor;
----------------------------------------------------------------------------------
ARCHITECTURE rtl OF clock_divisor IS
BEGIN
PROCESS (clk, nrst)
VARIABLE count : INTEGER RANGE 0 TO clk_frequency;
BEGIN
IF (nrst = '0') THEN
count := 0;
clk_out <= '0';
ELSIF rising_edge(clk) THEN
count := count + 1;
IF (count = clk_frequency) THEN
clk_out <= NOT clk_out;
count := 0;
END IF;
END IF;
END PROCESS;
END rtl; | gpl-2.0 | b6cd23099df6532e98b7f57cec3904c2 | 0.493179 | 4.125541 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/TB_main_sm.vhd | 2 | 6,922 | --------------------------------------------------------------------------------
--test bench for the main state machine
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY TB_main_sm IS
END TB_main_sm;
ARCHITECTURE behavior OF TB_main_sm IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT main_sm
PORT(
clk_spi : IN std_logic;
reset : IN std_logic;
miso_reg : IN std_logic_vector(15 downto 0);
data_lclkin : IN std_logic;
spi_start_o : OUT std_logic;
command_o : OUT std_logic_vector(15 downto 0);
hsync_o : out std_logic
);
END COMPONENT;
--SPI data merger unit
component data_merge is
port(
pclk : in std_logic;
reset : in std_logic;
data_rdy_pcie : in std_logic; --this is generated from the SPI interface. Here we must sample this line using 50MHz clock
vsync_o : out std_logic;
stream1 : in std_logic_vector(15 downto 0);
stream2 : in std_logic_vector(15 downto 0);
stream3 : in std_logic_vector(15 downto 0);
stream4 : in std_logic_vector(15 downto 0);
dout_o : out std_logic_vector(7 downto 0)
);
end component;
--FIFO module
COMPONENT fifo_test
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
--SPI data split
component data_split is
port(
--dataclk : in std_logic; --100MHz clk
pclk : in std_logic;
reset : in std_logic;
vsync : in std_logic;
din : in std_logic_vector(7 downto 0);
stream1_o : out std_logic_vector(15 downto 0); --this is the output to write to fifo
stream2_o : out std_logic_vector(15 downto 0);
stream3_o : out std_logic_vector(15 downto 0);
stream4_o : out std_logic_vector(15 downto 0);
vsync_pcie_o : out std_logic
);
end component;
--SPI module
component SPI_module is
port(
clk_spi : in std_logic; --spi clock from toplevel
reset : in std_logic; --reset
spi_start : in std_logic; --spi initiate
command_in : in std_logic_vector(15 downto 0); --parallel command input vector
--SPI inputs
miso_i : in std_logic;
--SPI outputs
cs_o : out std_logic;
sclk_o : out std_logic; --sclk is always 2x slower than clk_spi
mosi_o : out std_logic;
--data latch clock
data_lclk_o : out std_logic;
data_rdy_pcie_o : out std_logic;
data_pcie_A_o : out std_logic_vector(15 downto 0);
data_pcie_B_o : out std_logic_vector(15 downto 0);
miso_reg_A_o : out std_logic_vector(15 downto 0);
miso_reg_B_o : out std_logic_vector(15 downto 0)
);
end component;
--Inputs
signal clk_spi : std_logic := '0';
signal reset : std_logic := '0';
signal miso_reg_A, miso_reg_B : std_logic_vector(15 downto 0) := (others => '0');
signal data_lclkin : std_logic := '0';
signal miso : std_logic := '1';
signal clk84M : std_logic := '0';
--Outputs
signal spi_start_o : std_logic;
signal data_rdy_pcie_o : std_logic;
signal data_pcie_A_o, data_pcie_B_o : std_logic_vector(15 downto 0);
signal command_o : std_logic_vector(15 downto 0);
signal cs, sclk, mosi : std_logic;
signal dout_o : std_logic_vector(7 downto 0);
signal vsync_o : std_logic;
signal pclk : std_logic;
signal stream1, stream2, stream3, stream4 : std_logic_vector(15 downto 0);
signal hsync_o : std_logic;
signal vsync_pcie_o : std_logic;
signal fifo_in : std_logic_vector(15 downto 0);
signal fifo_wr_enb_o : std_logic;
signal fifo_rd_enb_o : std_logic;
signal fifo_out_o : std_logic_vector(15 downto 0); --output to the main dataclk statemachine on pci
-- Clock period definitions
--constant clk_spi_period : time := 11.90476 ns;
constant clk84M_period : time := 11.90476 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
mainstatement: main_sm PORT MAP (
clk_spi => clk_spi,
reset => reset,
miso_reg => miso_reg_A,
data_lclkin => data_lclkin,
spi_start_o => spi_start_o,
command_o => command_o,
hsync_o => hsync_o
);
--SPI data merger unit
merge: data_merge port map (
pclk => clk_spi,
reset => reset,
data_rdy_pcie => data_rdy_pcie_o, --this is generated from the SPI interface. Here we must sample this line using 50MHz clock
vsync_o => vsync_o,
stream1 => data_pcie_A_o,
stream2 => data_pcie_B_o,
stream3 => "0011110101010101",
stream4 => "1100000001111110",
dout_o => dout_o
);
-- fifo_block: fifo_test
-- PORT map(
-- rst => reset,
-- wr_clk => pclk,
-- rd_clk => clk84M,
-- din => stream1,
-- wr_en => fifo_wr_enb_o,
-- rd_en => fifo_rd_enb_o,
-- dout => fifo_in,
-- full => open,
-- empty => open);
--SPI data split unit
spliter: data_split port map (
--dataclk => clk84M,
pclk => clk_spi, --2 times slower than clk84M
reset => reset,
vsync => vsync_o,
din => dout_o,
--fifo_in => fifo_in,
--fifo_wr_enb_o => fifo_wr_enb_o,
--fifo_rd_enb_o => fifo_rd_enb_o,
--fifo_out_o => fifo_out_o, --output to the main dataclk statemachine on pci
stream1_o => stream1,
stream2_o => stream2,
stream3_o => stream3,
stream4_o => stream4,
vsync_pcie_o => vsync_pcie_o
);
spimodule: SPI_module PORT MAP (
clk_spi => clk_spi,
reset => reset,
spi_start => spi_start_o,
command_in => command_o, --read from 40 to 44 registers
--SPI inputs
miso_i => miso,
--SPI outputs
cs_o => cs,
sclk_o => sclk, --sclk is always 2x slower than clk_spi
mosi_o => mosi,
--data latch clock
data_lclk_o => data_lclkin,
data_rdy_pcie_o => data_rdy_pcie_o,
data_pcie_A_o => data_pcie_A_o,
data_pcie_B_o => data_pcie_B_o,
miso_reg_A_o => miso_reg_A,
miso_reg_B_o => miso_reg_B
);
-- Clock process definitions
clk_spi_process :process
begin
clk_spi <= '0';
wait for clk84M_period;
clk_spi <= '1';
wait for clk84M_period;
end process;
-- Clock process definitions
clk84M_process :process
begin
clk84M <= '0';
wait for clk84M_period/2;
clk84M <= '1';
wait for clk84M_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk84M_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | a7f7eb3135e84a491700154d4c51f351 | 0.57989 | 3.098478 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/ipcore_dir/pll/simulation/timing/pll_tb.vhd | 2 | 7,391 | -- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity pll_tb is
end pll_tb;
architecture test of pll_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component pll_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : pll_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
end test;
| mit | f9926738f7f79ee948754e322b505d40 | 0.608984 | 4.237959 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/top.vhd | 2 | 13,208 | ----------------------------------------------------------------------------------
--Top module for Headstage SerDes FPGA
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port(
clk_in : in std_logic; --input clock form oscillator
reset : in std_logic; --master system reset
pclk : out std_logic; --PCLK on the FPD chip
dout : out std_logic_vector(11 downto 0); --din on the serializer side of the FPD chip.
--LVDS outputs goes to the intan chips
cs_p : out std_logic;
cs_n : out std_logic;
sclk_p : out std_logic;
sclk_n : out std_logic;
mosi_p : out std_logic;
mosi_n : out std_logic;
--LVDS inputs for driving two 64 channel intan chips
miso_chip1_p : in std_logic;
miso_chip1_n : in std_logic;
miso_chip2_p : in std_logic;
miso_chip2_n : in std_logic;
--VS, HSYNC output - this is named as vsync and hsync just for consistency with the PCB layout
vsync_o : out std_logic; --signal one data block
hsync_o : out std_logic; --signals at only channel 0 for OE synchronization
--POT SPI interface use to config digital POT for LED driver
cs_pot_o : out std_logic; --LEDSPI2 --N5
sclk_pot_o : out std_logic; --LEDSPI0 --N4
din_pot_o :out std_logic; --LEDSPI1 --P5
--LED enable input signals
LED_GPO_0 : in std_logic;
--LED SPI interface
led_clk_o : out std_logic; --LED2
led_data_o : out std_logic; --LED0
led_latch_o : out std_logic; --LED1
--LED active output signals
LED0_active : out std_logic;
LED1_active : out std_logic
);
end top;
architecture Behavioral of top is
signal clk84M, clk42M, clk21M, clk2M, clk50M, clk10M, clk5M, clk1M, clk50K, clk500K, clk_spi, clk_pot_spi, clktest, clk2Hz, clk4Hz: std_logic;
signal count_bit : unsigned(11 downto 0);
signal cs, sclk, mosi, spi_start, data_lclk, mosi_dl : std_logic;
signal miso_chip1, miso_chip2 : std_logic;
signal miso_reg : std_logic_vector(15 downto 0);
signal command, command_dl, pot_command, led_command: std_logic_vector(15 downto 0);
signal pot_state, pot_config_enb: std_logic;
signal cs_pot, sclk_pot, din_pot : std_logic;
signal led_clk, led_data, led_latch : std_logic;
signal data_rdy_pcie : std_logic;
signal data_pcie_A, data_pcie_B, data_pcie_C, data_pcie_D : std_logic_vector(15 downto 0);
signal hsync, vsync : std_logic;
--clock divider
component clk_div is
generic (MAXD: natural:=5);
port(
clk: in std_logic;
reset: in std_logic;
div: in integer range 0 to MAXD;
div_clk: out std_logic
);
end component;
--main state machine
component main_sm
port(
clk_spi : IN std_logic;
reset : IN std_logic;
miso_reg : IN std_logic_vector(15 downto 0);
data_lclkin : IN std_logic;
spi_start_o : OUT std_logic;
command_o : OUT std_logic_vector(15 downto 0);
hsync_o : out std_logic
);
end component;
--SPI data merger unit
component data_merge is
port(
pclk : in std_logic;
reset : in std_logic;
data_rdy_pcie : in std_logic; --this is generated from the SPI interface. Here we must sample this line using 50MHz clock
vsync_o : out std_logic;
stream1 : in std_logic_vector(15 downto 0);
stream2 : in std_logic_vector(15 downto 0);
stream3 : in std_logic_vector(15 downto 0);
stream4 : in std_logic_vector(15 downto 0);
dout_o : out std_logic_vector(7 downto 0)
);
end component;
--"SPI" interface for the LED driver chip
component SPI_LEDdriver
port(
clk_spi : IN std_logic;
reset : IN std_logic;
write_start : IN std_logic;
command_in : IN std_logic_vector(15 downto 0);
led_clk_o : OUT std_logic;
led_data_o : OUT std_logic;
led_latch_o : OUT std_logic
);
end component;
--84MHz clock module
component pll
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
--SPI module
component SPI_module is
port(
clk_spi : in std_logic; --spi clock from toplevel
reset : in std_logic; --reset
spi_start : in std_logic; --spi initiate
command_in : in std_logic_vector(15 downto 0); --parallel command input vector
--SPI inputs
miso_i : in std_logic;
--SPI outputs
cs_o : out std_logic;
sclk_o : out std_logic; --sclk is always 2x slower than clk_spi
mosi_o : out std_logic;
--data latch clock
data_lclk_o : out std_logic;
data_rdy_pcie_o : out std_logic;
data_pcie_A_o : out std_logic_vector(15 downto 0);
data_pcie_B_o : out std_logic_vector(15 downto 0);
miso_reg_A_o : out std_logic_vector(15 downto 0);
miso_reg_B_o : out std_logic_vector(15 downto 0)
);
end component;
begin
--internal signal mapped to pins
pclk <= clk42M;
cs_pot_o <= cs_pot;
sclk_pot_o <= sclk_pot;
din_pot_o <= din_pot;
--debug signals sent through last 4 LSB of dout
dout(1) <= '0';
dout(3) <= sclk;
dout(2) <= miso_chip1;
dout(0) <= hsync;
--h vsync
hsync_o <= hsync;
vsync_o <= vsync;
--led control
led_clk_o <= led_clk;
led_data_o <= led_data;
led_latch_o <= led_latch;
--clock selection
clk_spi <= clk42M; --clk42M;
clk_pot_spi <= clk500K; --for the digital pot
--LVDS mapping ==============================================================
--outputs
lvds_mosi_map : OBUFDS generic map(IOSTANDARD => "LVDS_33") port map(O => mosi_p, OB => mosi_n, I => mosi);
lvds_sclk_map : OBUFDS generic map(IOSTANDARD => "LVDS_33") port map(O => sclk_p, OB => sclk_n, I => sclk);
lvds_cs_map : OBUFDS generic map(IOSTANDARD => "LVDS_33") port map(O => cs_p, OB => cs_n, I => cs);
--inputs
lvds_miso_chip1_map : IBUFGDS generic map (DIFF_TERM => FALSE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "LVDS_33") port map (O => miso_chip1, I => miso_chip1_p, IB => miso_chip1_n);
lvds_miso_chip2_map : IBUFGDS generic map (DIFF_TERM => FALSE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "LVDS_33") port map (O => miso_chip2, I => miso_chip2_p, IB => miso_chip2_n);
--clock dividers
-----------------------------------------------------------------------------
clk_div_84M: pll --from 100MHz to 84MHz
port map(CLK_IN1=>clk_in, reset=>reset,CLK_OUT1=>clk84M, LOCKED=>open);
clk_div_42M: clk_div generic map(MAXD=>2) --from 84MHz to 42MHz
port map(clk=>clk84M, reset=>reset,div=>2, div_clk=>clk42M);
clk_div_50M: clk_div generic map(MAXD=>2) --from 100MHz to 50MHz
port map(clk=>clk84M, reset=>reset,div=>2, div_clk=>clk50M);
clk_div_10M: clk_div generic map(MAXD=>5) --from 50MHz to 10MHz
port map(clk=>clk50M, reset=>reset,div=>5, div_clk=>clk10M);
clk_div_5M: clk_div generic map(MAXD=>2) --from 10MHz to 5MHz
port map(clk=>clk10M, reset=>reset,div=>2, div_clk=>clk5M);
clk_div_1M: clk_div generic map(MAXD=>5) --from 5MHz to 1MHz
port map(clk=>clk5M, reset=>reset,div=>5, div_clk=>clk1M); --not a 50% duty cycle clock
clk_div_500K: clk_div generic map(MAXD=>2) --from 1MHz to 500KHz
port map(clk=>clk1M, reset=>reset,div=>2, div_clk=>clk500K); --not a 50% duty cycle clock
clk_div_debug_only: clk_div generic map(MAXD=>40) --from 5MHz to 1MHz
port map(clk=>clk500K, reset=>reset,div=>40, div_clk=>clktest); --not a 50% duty cycle clock
-----------------------------------------------------------------------------
--map LED active to clk2Hz
LED0_active <= LED_GPO_0;
LED1_active <= LED_GPO_0;
mini_cnt_proc: process(spi_start, reset)
begin
if (reset = '1') then
count_bit <= (others=>'0');
elsif (falling_edge(spi_start)) then
count_bit <= count_bit + 1;
end if;
end process;
--generate command
--command <= "11" & std_logic_vector(to_unsigned(41,6)) & "00000000"; --read from 40 to 44 registers
--configuration sequence
-- 7654 3210
--R0 0x80DE "1101 1110"
--R1 0x8102 "0000 0010" -ADC buffer bias, 2 for >700 KS/s sampling rate.
--R2 0x8204 "0000 0100" -MUX bias 4 for >700 KS/s sampling rate
--R3 0x8302 "0000 0010" -digital out HiZ
--R4 0x845F "0101 1111" -MISO pull to highZ when CS is pulled high. twocomp. no absmode, DSP offset remove, k_freq = 0.000004857Hz
--R5 0x8500 "0000 0000" -disable impedance check
--R6 0x8600 "0000 0000" -disable impedance check DAC
--R7 0x8700 "0000 0000" -disable impedance check amplifier
--R8 0x8811 "0001 0001" -RH1 DAC1: 17 upper cutoff 10KHz
--R9 0x8980 "1000 0000" -RH1 DAC2: 0
--R10 0x8A10 "0001 0000" -RH2 DAC1: 16
--R11 0x8B80 "1000 0000" -RH2 DAC2: 0
--R12 0x8C10 "0001 0000" -RL DAC1
--R13 0x8DDC "1101 1100" -RL DAC2:28 DAC3:1 cutoff: 0.1HZ??????????????????????? confirm
--R14 0x8EFF "1111 1111"
--R15 0x8FFF "1111 1111"
--R16 0x90FF "1111 1111"
--R17 0x91FF "1111 1111"
--main statemachine
--this state machine generates command and puts those commands into the SPI module to serialize to the headstage
mainstatement: main_sm PORT MAP (
clk_spi => clk_spi,
reset => reset,
miso_reg => miso_reg,
data_lclkin => data_lclk,
spi_start_o => spi_start,
command_o => command,
hsync_o => hsync
);
--SPI data merger unit
merge: data_merge port map (
pclk => clk42M, --this gets 50MHz, should be the same as pclk frequency
reset => reset,
data_rdy_pcie => data_rdy_pcie, --this is generated from the SPI interface. Here we must sample this line using 50MHz clock
vsync_o => vsync, --link this directly to vsync_o output
stream1 => data_pcie_A,
stream2 => data_pcie_B,
stream3 => data_pcie_C,
stream4 => data_pcie_D,
dout_o => dout(11 downto 4) ---debug
);
--SPI module------------------------------------------------------
SPI_intan_chip1: SPI_module
port map(
clk_spi => clk_spi,
reset => reset,
spi_start => spi_start,
command_in => command, --read from 40 to 44 registers
--SPI inputs
miso_i => miso_chip1,
--SPI outputs
cs_o => cs,
sclk_o => sclk, --sclk is always 2x slower than clk_spi
mosi_o => mosi,
--data latch clock
data_lclk_o => data_lclk,
data_rdy_pcie_o => data_rdy_pcie,
data_pcie_A_o => data_pcie_A,
data_pcie_B_o => data_pcie_B,
miso_reg_A_o => miso_reg,
miso_reg_B_o => open
);
--SPI module------------------------------------------------------
SPI_intan_chip2: SPI_module
port map(
clk_spi => clk_spi,
reset => reset,
spi_start => spi_start,
command_in => command, --read from 40 to 44 registers
--SPI inputs
miso_i => miso_chip2,
--SPI outputs
cs_o => open,
sclk_o => open, --sclk is always 2x slower than clk_spi
mosi_o => open,
--data latch clock
data_lclk_o => open,
data_rdy_pcie_o => open,
data_pcie_A_o => data_pcie_C,
data_pcie_B_o => data_pcie_D,
miso_reg_A_o => open,
miso_reg_B_o => open
);
--LED development-------------------------------------------------------------
--generate the one shot for configuration
on_shot_pot: process(clk_pot_spi, reset)
begin
if (reset = '1') then
pot_state <= '0';
pot_config_enb <= '0';
elsif (rising_edge(clk_pot_spi)) then
if pot_state = '0' then
pot_state <= '1';
pot_config_enb <= '1';
else
pot_state <= '1';
pot_config_enb <= '0';
end if;
end if;
end process;
--pot command: write wiper information to register A and B.
--[C1 C0]="00"
--[A1 A0]="11"
pot_command <= "00" & "00" & "00" & "11" & "11011010"; --10K Ohm
--variable resistor (POT) SPI module--------------------------------------------------
SPI_imu: SPI_module
port map(
clk_spi => clk_pot_spi, --keep the frequency aroudn 1MHz or even slower
reset => reset,
spi_start => clktest, --generate a 1-shot configuration (get this from the main state_machine?)
command_in => pot_command, --read from 40 to 44 registers
--SPI inputs
miso_i => '0', --ground the miso for the pot because there is no output
--SPI outputs
cs_o => cs_pot,
sclk_o => sclk_pot, --sclk is always 2x slower than clk_spi
mosi_o => din_pot,
--data latch clock
data_lclk_o => open,
data_rdy_pcie_o => open,
data_pcie_A_o => open,
data_pcie_B_o => open,
miso_reg_A_o => open,
miso_reg_B_o => open
);
--LED configuration command
--led_command <= "1111111111111111"; --all on
led_command <= "0000000000000011";
-- Instantiate the Unit Under Test (UUT)
leddirver: SPI_LEDdriver PORT MAP (
clk_spi => clk_pot_spi,
reset => reset,
write_start => clktest,
command_in => led_command,
led_clk_o => led_clk,
led_data_o => led_data,
led_latch_o => led_latch
);
end Behavioral;
| mit | 890da0bfedd9adb7c506986048f5bc8d | 0.589794 | 3.012087 | false | false | false | false |
zhlinh/vhdl_course | Assignment/FREQ_CNT/D_LATCH.vhd | 1 | 720 | --Latch
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY D_LATCH IS
PORT( LATCH_EN: IN STD_LOGIC;
D1_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D1_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY D_LATCH;
ARCHITECTURE ART1 OF D_LATCH IS
BEGIN
PROCESS(LATCH_EN)
BEGIN
IF (LATCH_EN='1') THEN
D1_OUT <= D1_IN;
D2_OUT <= D2_IN;
D3_OUT <= D3_IN;
ELSE
D1_OUT <= "0000";
D2_OUT <= "0000";
D3_OUT <= "0000";
END IF;
END PROCESS;
END ARCHITECTURE ART1;
| apache-2.0 | bce604968974d41907e307963bb327f3 | 0.648611 | 2.376238 | false | false | false | false |
cafe-alpha/wasca | obsolete/fpga_firmware_V2/ip_repo/ABus2AXI4Lite/hdl/ABus2AXI4Lite.vhd | 2 | 15,694 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Master Bus Interface M00_AXI
C_MASTER_AXI_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000";
C_MASTER_AXI_ADDR_WIDTH : integer := 32;
C_MASTER_AXI_DATA_WIDTH : integer := 32;
C_SLAVE_AXI_ADDR_WIDTH : integer := 32;
C_SLAVE_AXI_DATA_WIDTH : integer := 32;
C_FILESYS_AXI_ADDR_WIDTH : integer := 32;
C_FILESYS_AXI_DATA_WIDTH : integer := 32
);
port (
-- abus ports
abus_address : in std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
abus_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_out : out std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_direction : out std_logic := '0'; -- .direction
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_wait : out std_logic := '1'; -- .waitrequest
abus_wait_direction : out std_logic := '0'; -- .direction
abus_irq : out std_logic := '0'; -- .interrupt
abus_irq_direction : out std_logic := '0'; -- .direction
abus_reset : in std_logic := '0'; -- .saturn_reset
-- Ports of Axi Master Bus Interface
master_axi_aclk : in std_logic;
master_axi_aresetn : in std_logic;
master_axi_awaddr : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
master_axi_awprot : out std_logic_vector(2 downto 0);
master_axi_awvalid : out std_logic;
master_axi_awready : in std_logic;
master_axi_wdata : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
master_axi_wstrb : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH/8-1 downto 0);
master_axi_wvalid : out std_logic;
master_axi_wready : in std_logic;
master_axi_bresp : in std_logic_vector(1 downto 0);
master_axi_bvalid : in std_logic;
master_axi_bready : out std_logic;
master_axi_araddr : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
master_axi_arprot : out std_logic_vector(2 downto 0);
master_axi_arvalid : out std_logic;
master_axi_arready : in std_logic;
master_axi_rdata : in std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
master_axi_rresp : in std_logic_vector(1 downto 0);
master_axi_rvalid : in std_logic;
master_axi_rready : out std_logic;
-- Ports of Slave Bus Interface
slave_axi_aclk : in std_logic;
slave_axi_aresetn : in std_logic;
slave_axi_awaddr : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
slave_axi_awprot : in std_logic_vector(2 downto 0);
slave_axi_awvalid : in std_logic;
slave_axi_awready : out std_logic;
slave_axi_wdata : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
slave_axi_wstrb : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH/8-1 downto 0);
slave_axi_wvalid : in std_logic;
slave_axi_wready : out std_logic;
slave_axi_bresp : out std_logic_vector(1 downto 0);
slave_axi_bvalid : out std_logic;
slave_axi_bready : in std_logic;
slave_axi_araddr : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
slave_axi_arprot : in std_logic_vector(2 downto 0);
slave_axi_arvalid : in std_logic;
slave_axi_arready : out std_logic;
slave_axi_rdata : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
slave_axi_rresp : out std_logic_vector(1 downto 0);
slave_axi_rvalid : out std_logic;
slave_axi_rready : in std_logic
-- -- Ports of Filesys Bus Interface
-- filesys_axi_aclk : in std_logic;
-- filesys_axi_aresetn : in std_logic;
-- filesys_axi_awaddr : in std_logic_vector(C_FILESYS_AXI_ADDR_WIDTH-1 downto 0);
-- filesys_axi_awprot : in std_logic_vector(2 downto 0);
-- filesys_axi_awvalid : in std_logic;
-- filesys_axi_awready : out std_logic;
-- filesys_axi_wdata : in std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
-- filesys_axi_wstrb : in std_logic_vector(C_FILESYS_AXI_DATA_WIDTH/8-1 downto 0);
-- filesys_axi_wvalid : in std_logic;
-- filesys_axi_wready : out std_logic;
-- filesys_axi_bresp : out std_logic_vector(1 downto 0);
-- filesys_axi_bvalid : out std_logic;
-- filesys_axi_bready : in std_logic;
-- filesys_axi_araddr : in std_logic_vector(C_FILESYS_AXI_ADDR_WIDTH-1 downto 0);
-- filesys_axi_arprot : in std_logic_vector(2 downto 0);
-- filesys_axi_arvalid : in std_logic;
-- filesys_axi_arready : out std_logic;
-- filesys_axi_rdata : out std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
-- filesys_axi_rresp : out std_logic_vector(1 downto 0);
-- filesys_axi_rvalid : out std_logic;
-- filesys_axi_rready : in std_logic
);
end ABus2AXI4Lite;
architecture arch_imp of ABus2AXI4Lite is
-- component declaration
component ABus2AXI4Lite_Master_AXI is
generic (
C_MASTER_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
C_MASTER_AXI_ADDR_WIDTH : integer := 32;
C_MASTER_AXI_DATA_WIDTH : integer := 32
);
port (
abus_address : in std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
abus_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_out : out std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_direction : out std_logic := '0'; -- .direction
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_wait : out std_logic := '1'; -- .waitrequest
abus_wait_direction : out std_logic := '0'; -- .direction
abus_irq : out std_logic := '0'; -- .interrupt
abus_irq_direction : out std_logic := '0'; -- .direction
abus_reset : in std_logic := '0'; -- .saturn_reset
MASTER_AXI_ACLK : in std_logic;
MASTER_AXI_ARESETN : in std_logic;
MASTER_AXI_AWADDR : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
MASTER_AXI_AWPROT : out std_logic_vector(2 downto 0);
MASTER_AXI_AWVALID : out std_logic;
MASTER_AXI_AWREADY : in std_logic;
MASTER_AXI_WDATA : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
MASTER_AXI_WSTRB : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH/8-1 downto 0);
MASTER_AXI_WVALID : out std_logic;
MASTER_AXI_WREADY : in std_logic;
MASTER_AXI_BRESP : in std_logic_vector(1 downto 0);
MASTER_AXI_BVALID : in std_logic;
MASTER_AXI_BREADY : out std_logic;
MASTER_AXI_ARADDR : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
MASTER_AXI_ARPROT : out std_logic_vector(2 downto 0);
MASTER_AXI_ARVALID : out std_logic;
MASTER_AXI_ARREADY : in std_logic;
MASTER_AXI_RDATA : in std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
MASTER_AXI_RRESP : in std_logic_vector(1 downto 0);
MASTER_AXI_RVALID : in std_logic;
MASTER_AXI_RREADY : out std_logic
);
end component ABus2AXI4Lite_Master_AXI;
component ABus2AXI4Lite_Slave_AXI is
generic (
C_SLAVE_AXI_ADDR_WIDTH : integer := 32;
C_SLAVE_AXI_DATA_WIDTH : integer := 32
);
port (
PCNTR : out std_logic_vector(15 downto 0);
STATUS : out std_logic_vector(15 downto 0);
MODE : in std_logic_vector(15 downto 0);
HWVER : in std_logic_vector(15 downto 0);
SWVER : out std_logic_vector(15 downto 0);
SLAVE_AXI_ACLK : in std_logic;
SLAVE_AXI_ARESETN : in std_logic;
SLAVE_AXI_AWADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
SLAVE_AXI_AWPROT : in std_logic_vector(2 downto 0);
SLAVE_AXI_AWVALID : in std_logic;
SLAVE_AXI_AWREADY : out std_logic;
SLAVE_AXI_WDATA : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
SLAVE_AXI_WSTRB : in std_logic_vector((C_SLAVE_AXI_DATA_WIDTH/8)-1 downto 0);
SLAVE_AXI_WVALID : in std_logic;
SLAVE_AXI_WREADY : out std_logic;
SLAVE_AXI_BRESP : out std_logic_vector(1 downto 0);
SLAVE_AXI_BVALID : out std_logic;
SLAVE_AXI_BREADY : in std_logic;
SLAVE_AXI_ARADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
SLAVE_AXI_ARPROT : in std_logic_vector(2 downto 0);
SLAVE_AXI_ARVALID : in std_logic;
SLAVE_AXI_ARREADY : out std_logic;
SLAVE_AXI_RDATA : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
SLAVE_AXI_RRESP : out std_logic_vector(1 downto 0);
SLAVE_AXI_RVALID : out std_logic;
SLAVE_AXI_RREADY : in std_logic
);
end component;
component ABus2AXI4Lite_Filesys_regs_AXI is
generic (
C_FILESYS_AXI_DATA_WIDTH : integer := 32;
C_FILESYS_AXI_ADDR_WIDTH : integer := 5
);
port (
FILESYS_AXI_ACLK : in std_logic;
FILESYS_AXI_ARESETN : in std_logic;
FILESYS_AXI_AWADDR : in std_logic_vector(C_FILESYS_AXI_ADDR_WIDTH-1 downto 0);
FILESYS_AXI_AWPROT : in std_logic_vector(2 downto 0);
FILESYS_AXI_AWVALID : in std_logic;
FILESYS_AXI_AWREADY : out std_logic;
FILESYS_AXI_WDATA : in std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
FILESYS_AXI_WSTRB : in std_logic_vector((C_FILESYS_AXI_DATA_WIDTH/8)-1 downto 0);
FILESYS_AXI_WVALID : in std_logic;
FILESYS_AXI_WREADY : out std_logic;
FILESYS_AXI_BRESP : out std_logic_vector(1 downto 0);
FILESYS_AXI_BVALID : out std_logic;
FILESYS_AXI_BREADY : in std_logic;
FILESYS_AXI_ARADDR : in std_logic_vector(C_FILESYS_AXI_ADDR_WIDTH-1 downto 0);
FILESYS_AXI_ARPROT : in std_logic_vector(2 downto 0);
FILESYS_AXI_ARVALID : in std_logic;
FILESYS_AXI_ARREADY : out std_logic;
FILESYS_AXI_RDATA : out std_logic_vector(C_FILESYS_AXI_DATA_WIDTH-1 downto 0);
FILESYS_AXI_RRESP : out std_logic_vector(1 downto 0);
FILESYS_AXI_RVALID : out std_logic;
FILESYS_AXI_RREADY : in std_logic
);
end component;
signal PCNTR : std_logic_vector(15 downto 0) := X"0000";
signal STATUS : std_logic_vector(15 downto 0) := X"0000";
signal MODE : std_logic_vector(15 downto 0) := X"0000";
signal HWVER : std_logic_vector(15 downto 0) := X"0100";
signal SWVER : std_logic_vector(15 downto 0) := X"0000";
begin
--the master interface goes to DDR3 memory
--it needs mode signal to disable reading or writing memory in certain modes
ABus2AXI4Lite_Master_AXI_inst : ABus2AXI4Lite_Master_AXI
generic map (
C_MASTER_TARGET_SLAVE_BASE_ADDR => C_MASTER_AXI_TARGET_SLAVE_BASE_ADDR,
C_MASTER_AXI_ADDR_WIDTH => C_MASTER_AXI_ADDR_WIDTH,
C_MASTER_AXI_DATA_WIDTH => C_MASTER_AXI_DATA_WIDTH
)
port map (
abus_address => abus_address,
abus_data_in => abus_data_in,
abus_data_out => abus_data_out,
abus_data_direction => abus_data_direction,
abus_chipselect => abus_chipselect,
abus_read => abus_read,
abus_write => abus_write,
abus_wait => abus_wait,
abus_wait_direction => abus_wait_direction,
abus_irq => abus_irq,
abus_irq_direction => abus_irq_direction,
abus_reset => abus_reset,
MASTER_AXI_ACLK => master_axi_aclk,
MASTER_AXI_ARESETN => master_axi_aresetn,
MASTER_AXI_AWADDR => master_axi_awaddr,
MASTER_AXI_AWPROT => master_axi_awprot,
MASTER_AXI_AWVALID => master_axi_awvalid,
MASTER_AXI_AWREADY => master_axi_awready,
MASTER_AXI_WDATA => master_axi_wdata,
MASTER_AXI_WSTRB => master_axi_wstrb,
MASTER_AXI_WVALID => master_axi_wvalid,
MASTER_AXI_WREADY => master_axi_wready,
MASTER_AXI_BRESP => master_axi_bresp,
MASTER_AXI_BVALID => master_axi_bvalid,
MASTER_AXI_BREADY => master_axi_bready,
MASTER_AXI_ARADDR => master_axi_araddr,
MASTER_AXI_ARPROT => master_axi_arprot,
MASTER_AXI_ARVALID => master_axi_arvalid,
MASTER_AXI_ARREADY => master_axi_arready,
MASTER_AXI_RDATA => master_axi_rdata,
MASTER_AXI_RRESP => master_axi_rresp,
MASTER_AXI_RVALID => master_axi_rvalid,
MASTER_AXI_RREADY => master_axi_rready
);
ABus2AXI4Lite_Slave_AXI_inst : ABus2AXI4Lite_Slave_AXI
generic map (
C_SLAVE_AXI_ADDR_WIDTH => C_SLAVE_AXI_ADDR_WIDTH,
C_SLAVE_AXI_DATA_WIDTH => C_SLAVE_AXI_DATA_WIDTH
)
port map(
PCNTR => PCNTR,
STATUS => STATUS,
MODE => MODE,
HWVER => HWVER,
SWVER => SWVER,
SLAVE_AXI_ACLK => slave_axi_aclk,
SLAVE_AXI_ARESETN => slave_axi_aresetn,
SLAVE_AXI_AWADDR => slave_axi_awaddr,
SLAVE_AXI_AWPROT => slave_axi_awprot,
SLAVE_AXI_AWVALID => slave_axi_awvalid,
SLAVE_AXI_AWREADY => slave_axi_awready,
SLAVE_AXI_WDATA => slave_axi_wdata,
SLAVE_AXI_WSTRB => slave_axi_wstrb,
SLAVE_AXI_WVALID => slave_axi_wvalid,
SLAVE_AXI_WREADY => slave_axi_wready,
SLAVE_AXI_BRESP => slave_axi_bresp,
SLAVE_AXI_BVALID => slave_axi_bvalid,
SLAVE_AXI_BREADY => slave_axi_bready,
SLAVE_AXI_ARADDR => slave_axi_araddr,
SLAVE_AXI_ARPROT => slave_axi_arprot,
SLAVE_AXI_ARVALID => slave_axi_arvalid,
SLAVE_AXI_ARREADY => slave_axi_arready,
SLAVE_AXI_RDATA => slave_axi_rdata,
SLAVE_AXI_RRESP => slave_axi_rresp,
SLAVE_AXI_RVALID => slave_axi_rvalid,
SLAVE_AXI_RREADY => slave_axi_rready
);
--ABus2AXI4Lite_Filesys_AXI_inst : ABus2AXI4Lite_Filesys_regs_AXI
-- generic map (
-- C_FILESYS_AXI_ADDR_WIDTH => C_FILESYS_AXI_ADDR_WIDTH,
-- C_FILESYS_AXI_DATA_WIDTH => C_FILESYS_AXI_DATA_WIDTH
-- )
-- port map(
-- FILESYS_AXI_ACLK => filesys_axi_aclk,
-- FILESYS_AXI_ARESETN => filesys_axi_aresetn,
-- FILESYS_AXI_AWADDR => filesys_axi_awaddr,
-- FILESYS_AXI_AWPROT => filesys_axi_awprot,
-- FILESYS_AXI_AWVALID => filesys_axi_awvalid,
-- FILESYS_AXI_AWREADY => filesys_axi_awready,
-- FILESYS_AXI_WDATA => filesys_axi_wdata,
-- FILESYS_AXI_WSTRB => filesys_axi_wstrb,
-- FILESYS_AXI_WVALID => filesys_axi_wvalid,
-- FILESYS_AXI_WREADY => filesys_axi_wready,
-- FILESYS_AXI_BRESP => filesys_axi_bresp,
-- FILESYS_AXI_BVALID => filesys_axi_bvalid,
-- FILESYS_AXI_BREADY => filesys_axi_bready,
-- FILESYS_AXI_ARADDR => filesys_axi_araddr,
-- FILESYS_AXI_ARPROT => filesys_axi_arprot,
-- FILESYS_AXI_ARVALID => filesys_axi_arvalid,
-- FILESYS_AXI_ARREADY => filesys_axi_arready,
-- FILESYS_AXI_RDATA => filesys_axi_rdata,
-- FILESYS_AXI_RRESP => filesys_axi_rresp,
-- FILESYS_AXI_RVALID => filesys_axi_rvalid,
-- FILESYS_AXI_RREADY => filesys_axi_rready
-- );
-- Add user logic here
-- User logic ends
end arch_imp;
| gpl-2.0 | 71fbca9856401efae22b356e48b095fa | 0.61686 | 3.042062 | false | false | false | false |
seyedmaysamlavasani/GorillaPP | apps/multiProtocolNpu/build/synthesis/asic/FreePDK45/osu_soc/lib/source/signalstorm/files/gscl45nm.vhdl | 3 | 97,387 | LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
LIBRARY IEEE;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
package prim is
CONSTANT DefCombSpikeMsgOn : BOOLEAN := true;
CONSTANT DefCombSpikeXOn : BOOLEAN := true;
CONSTANT DefSeqMsgOn : BOOLEAN := true;
CONSTANT DefSeqXOn : BOOLEAN := true;
CONSTANT DefDummyDelay : VitalDelayType := 1.00 ns;
CONSTANT DefDummySetup : VitalDelayType := 1.00 ns;
CONSTANT DefDummyHold : VitalDelayType := 1.00 ns;
CONSTANT DefDummyWidth : VitalDelayType := 1.00 ns;
CONSTANT DefDummyRecovery : VitalDelayType := 1.00 ns;
CONSTANT DefDummyRemoval : VitalDelayType := 1.00 ns;
CONSTANT DefDummyIpd : VitalDelayType := 0.00 ns;
CONSTANT DefDummyIsd : VitalDelayType := 0.00 ns;
CONSTANT DefDummyIcd : VitalDelayType := 0.00 ns;
CONSTANT udp_dff : VitalStateTableType (1 TO 21, 1 TO 7) := (
-- NOTIFIER D CLK RN S Q(t) Q(t+1)
( 'X', '-', '-', '-', '-', '-', 'X' ),
( '-', '-', '-', '-', '1', '-', '1' ),
( '-', '-', '-', '1', '0', '-', '0' ),
( '-', '0', '/', '-', '0', '-', '0' ),
( '-', '1', '/', '0', '-', '-', '1' ),
( '-', '1', '*', '0', '-', '1', '1' ),
( '-', '0', '*', '-', '0', '0', '0' ),
( '-', '-', '\', '-', '-', '-', 'S' ),
( '-', '*', 'B', '-', '-', '-', 'S' ),
( '-', '-', 'B', '0', '*', '1', '1' ),
( '-', '1', 'X', '0', '*', '1', '1' ),
( '-', '-', 'B', '*', '0', '0', '0' ),
( '-', '0', 'X', '*', '0', '0', '0' ),
( '-', 'B', 'r', '-', '-', '-', 'X' ),
( '-', '/', 'X', '-', '-', '-', 'X' ),
( '-', '-', '-', '-', '*', '-', 'X' ),
( '-', '-', '-', '*', '-', '-', 'X' ),
( '-', '-', 'f', '-', '-', '-', 'X' ),
( '-', '\', 'X', '0', '-', '-', 'X' ),
( '-', 'B', 'X', '-', '-', '-', 'S' ),
( '-', '-', 'S', '-', '-', '-', 'S' ));
CONSTANT udp_tlat : VitalStateTableType (1 TO 20, 1 TO 7) := (
-- NOT D G R S Q(t) Q(t+1)
( 'X', '-', '-', '-', '-', '-', 'X' ),
( '-', '-', '-', '-', '1', '-', '1' ),
( '-', '-', '-', '1', '0', '-', '0' ),
( '-', '1', '1', '0', '-', '-', '1' ),
( '-', '0', '1', '-', '0', '-', '0' ),
( '-', '1', '*', '0', '-', '1', '1' ),
( '-', '0', '*', '-', '0', '0', '0' ),
( '-', '*', '0', '-', '-', '-', 'S' ),
( '-', '-', '0', '0', '*', '1', '1' ),
( '-', '1', '-', '0', '*', '1', '1' ),
( '-', '-', '0', '*', '0', '0', '0' ),
( '-', '0', '-', '*', '0', '0', '0' ),
( '-', '0', '-', '-', '0', '0', '0' ),
( '-', '1', '-', '0', '-', '1', '1' ),
( '-', '*', '-', '-', '-', '-', 'X' ),
( '-', '-', '-', '*', '-', '-', 'X' ),
( '-', '-', '-', '-', '*', '-', 'X' ),
( '-', 'B', 'r', '0', '0', '-', 'X' ),
( '-', 'B', 'X', '0', '0', '-', 'S' ),
( '-', '-', 'S', '-', '-', '-', 'S' ) );
CONSTANT udp_rslat : VitalStateTableType (1 TO 12, 1 TO 5) := (
-- NOT R S Q(t) Q(t+1)
( 'X', '-', '-', '-', 'X' ),
( '-', '-', '1', '-', '1' ),
( '-', '1', '0', '-', '0' ),
( '-', '0', '-', '1', '1' ),
( '-', '-', '0', '0', '0' ),
( '-', '-', '-', '-', 'S' ),
( '-', '0', '*', '1', '1' ),
( '-', '*', '0', '0', '0' ),
( '-', '-', '0', '0', '0' ),
( '-', '0', '-', '1', '1' ),
( '-', '*', '-', '-', 'X' ),
( '-', '-', '*', '-', 'X' ) );
end prim;
package body prim is
end prim;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity AND2X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.335241 ns, 0.243067 ns);
tpd_B_Y : VitalDelayType01 := (0.341203 ns, 0.249226 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of AND2X1 : entity is TRUE;
end AND2X1;
architecture behavioral of AND2X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalAND2(A_ipd, B_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity AND2X2 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.061801 ns, 0.064675 ns);
tpd_B_Y : VitalDelayType01 := (0.0615099 ns, 0.0700575 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of AND2X2 : entity is TRUE;
end AND2X2;
architecture behavioral of AND2X2 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalAND2(A_ipd, B_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity AOI21X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_C : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.366123 ns, 0.202405 ns);
tpd_B_Y : VitalDelayType01 := (0.360918 ns, 0.204079 ns);
tpd_C_Y : VitalDelayType01 := (0.307952 ns, 0.227488 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
C : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of AOI21X1 : entity is TRUE;
end AOI21X1;
architecture behavioral of AOI21X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
SIGNAL C_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
VitalWireDelay( C_ipd, C, tipd_C );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd, C_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE n1_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalAND2(A_ipd, B_ipd);
n1_var := VitalOR2(n0_var, C_ipd);
Y_zd := VitalINV(n1_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE),
2 => ( C_ipd'LAST_EVENT,
tpd_C_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity AOI22X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_C : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_D : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.341706 ns, 0.211527 ns);
tpd_B_Y : VitalDelayType01 := (0.337339 ns, 0.210324 ns);
tpd_C_Y : VitalDelayType01 := (0.32125 ns, 0.19844 ns);
tpd_D_Y : VitalDelayType01 := (0.316696 ns, 0.199983 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
C : in std_ulogic := 'U' ;
D : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of AOI22X1 : entity is TRUE;
end AOI22X1;
architecture behavioral of AOI22X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
SIGNAL C_ipd : std_ulogic := 'X';
SIGNAL D_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
VitalWireDelay( C_ipd, C, tipd_C );
VitalWireDelay( D_ipd, D, tipd_D );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd, C_ipd, D_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE n1_var : std_ulogic;
VARIABLE n2_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalAND2(C_ipd, D_ipd);
n1_var := VitalAND2(A_ipd, B_ipd);
n2_var := VitalOR2(n0_var, n1_var);
Y_zd := VitalINV(n2_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE),
2 => ( C_ipd'LAST_EVENT,
tpd_C_Y,
TRUE),
3 => ( D_ipd'LAST_EVENT,
tpd_D_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity BUFX2 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.0639432 ns, 0.0618965 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of BUFX2 : entity is TRUE;
end BUFX2;
architecture behavioral of BUFX2 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalBUF(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity BUFX4 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.0476551 ns, 0.0696413 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of BUFX4 : entity is TRUE;
end BUFX4;
architecture behavioral of BUFX4 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalBUF(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity CLKBUF1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.121822 ns, 0.104436 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of CLKBUF1 : entity is TRUE;
end CLKBUF1;
architecture behavioral of CLKBUF1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalBUF(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity CLKBUF2 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.143843 ns, 0.127188 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of CLKBUF2 : entity is TRUE;
end CLKBUF2;
architecture behavioral of CLKBUF2 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalBUF(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity CLKBUF3 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.16682 ns, 0.150093 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of CLKBUF3 : entity is TRUE;
end CLKBUF3;
architecture behavioral of CLKBUF3 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalBUF(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity DFFNEGX1 is
generic (
tipd_CLK : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
ticd_CLK : VitalDelayType := DefDummyIcd;
tipd_D : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tisd_D_CLK : VitalDelayType := DefDummyIsd;
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.0937499 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.0937499 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := -0.00000000216744 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0 ns;
tpw_CLK_posedge : VitalDelayType := 0.0404763 ns;
tpw_CLK_negedge : VitalDelayType := 0.127802 ns;
tpd_CLK_Q_negedge : VitalDelayType01 := (0.215846 ns, 0.188439 ns);
TimingChecksOn : BOOLEAN := false;
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
CLK : in std_ulogic := 'U' ;
D : in std_ulogic := 'U' ;
Q : out std_ulogic);
attribute VITAL_LEVEL0 of DFFNEGX1 : entity is TRUE;
end DFFNEGX1;
architecture behavioral of DFFNEGX1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL CLK_dly : std_ulogic := 'X';
SIGNAL CLK_ipd : std_ulogic := 'X';
SIGNAL D_dly : std_ulogic := 'X';
SIGNAL D_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( CLK_ipd, CLK, tipd_CLK );
VitalWireDelay( D_ipd, D, tipd_D );
END BLOCK;
SIGNALDELAY : BLOCK
BEGIN
VitalSignalDelay( CLK_dly, CLK_ipd, ticd_CLK );
VitalSignalDelay( D_dly, D_ipd, tisd_D_CLK );
END BLOCK;
VITALBehavior : PROCESS (CLK_dly, D_dly)
--timing checks section variables
VARIABLE Tviol_D_CLK : std_ulogic := '0';
VARIABLE TimeMarker_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE PWviol_CLK : std_ulogic := '0';
VARIABLE PeriodCheckInfo_CLK : VitalPeriodDataType;
-- functionality section variables
VARIABLE intclk : std_ulogic;
VARIABLE n0_RN_dly : std_ulogic := '0';
VARIABLE n0_SN_dly : std_ulogic := '0';
VARIABLE DS0000 : std_ulogic;
VARIABLE P0000 : std_ulogic;
VARIABLE n0_vec : std_logic_vector( 1 TO 1 );
VARIABLE PrevData_udp_dff_n0 : std_logic_vector( 0 TO 4 );
VARIABLE Q_zd : std_ulogic;
VARIABLE NOTIFIER : std_ulogic := '0';
-- path delay section variables
VARIABLE Q_GlitchData : VitalGlitchDataType;
BEGIN
-- Timing checks section
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => D_dly,
TestSignalName => "D",
RefSignal => CLK_dly,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_posedge_negedge,
SetupLow => tsetup_D_CLK_negedge_negedge,
HoldHigh => thold_D_CLK_posedge_negedge,
HoldLow => thold_D_CLK_negedge_negedge,
CheckEnabled => TRUE,
RefTransition => 'F',
HeaderMsg => InstancePath & "/DFFNEGX1",
TimingData => TimeMarker_D_CLK,
Violation => Tviol_D_CLK,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalPeriodPulseCheck (
TestSignal => CLK_dly,
TestSignalName => "CLK",
Period => 0 ps,
PulseWidthHigh => tpw_CLK_posedge,
PulseWidthLow => tpw_CLK_negedge,
PeriodData => PeriodCheckInfo_CLK,
Violation => PWviol_CLK,
HeaderMsg => InstancePath & "/DFFNEGX1",
CheckEnabled => TRUE,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
END IF;
-- Functionality section
NOTIFIER := (
Tviol_D_CLK OR
PWviol_CLK );
intclk := VitalINV(CLK_dly);
n0_RN_dly := '0';
n0_SN_dly := '0';
VitalStateTable ( StateTable => udp_dff,
DataIn => (NOTIFIER, D_dly, intclk, n0_RN_dly, n0_SN_dly),
NumStates => 1,
Result => n0_vec,
PreviousDataIn => PrevData_udp_dff_n0 );
DS0000 := n0_vec(1);
P0000 := VitalINV(DS0000);
Q_zd := VitalBUF(DS0000);
-- Path delay section
VitalPathDelay01(
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Q_zd,
Paths => (
0 => ( CLK_dly'LAST_EVENT,
tpd_CLK_Q_negedge,
To_X01(CLK_dly) /= '1')),
GlitchData => Q_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity DFFPOSX1 is
generic (
tipd_CLK : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
ticd_CLK : VitalDelayType := DefDummyIcd;
tipd_D : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tisd_D_CLK : VitalDelayType := DefDummyIsd;
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.0937499 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.0937499 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.00000000216744 ns;
tpw_CLK_posedge : VitalDelayType := 0.129905 ns;
tpw_CLK_negedge : VitalDelayType := 0.0554379 ns;
tpd_CLK_Q_posedge : VitalDelayType01 := (0.218831 ns, 0.200897 ns);
TimingChecksOn : BOOLEAN := false;
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
CLK : in std_ulogic := 'U' ;
D : in std_ulogic := 'U' ;
Q : out std_ulogic);
attribute VITAL_LEVEL0 of DFFPOSX1 : entity is TRUE;
end DFFPOSX1;
architecture behavioral of DFFPOSX1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL CLK_dly : std_ulogic := 'X';
SIGNAL CLK_ipd : std_ulogic := 'X';
SIGNAL D_dly : std_ulogic := 'X';
SIGNAL D_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( CLK_ipd, CLK, tipd_CLK );
VitalWireDelay( D_ipd, D, tipd_D );
END BLOCK;
SIGNALDELAY : BLOCK
BEGIN
VitalSignalDelay( CLK_dly, CLK_ipd, ticd_CLK );
VitalSignalDelay( D_dly, D_ipd, tisd_D_CLK );
END BLOCK;
VITALBehavior : PROCESS (CLK_dly, D_dly)
--timing checks section variables
VARIABLE Tviol_D_CLK : std_ulogic := '0';
VARIABLE TimeMarker_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE PWviol_CLK : std_ulogic := '0';
VARIABLE PeriodCheckInfo_CLK : VitalPeriodDataType;
-- functionality section variables
VARIABLE intclk : std_ulogic;
VARIABLE n0_RN_dly : std_ulogic := '0';
VARIABLE n0_SN_dly : std_ulogic := '0';
VARIABLE DS0000 : std_ulogic;
VARIABLE P0000 : std_ulogic;
VARIABLE n0_vec : std_logic_vector( 1 TO 1 );
VARIABLE PrevData_udp_dff_n0 : std_logic_vector( 0 TO 4 );
VARIABLE Q_zd : std_ulogic;
VARIABLE NOTIFIER : std_ulogic := '0';
-- path delay section variables
VARIABLE Q_GlitchData : VitalGlitchDataType;
BEGIN
-- Timing checks section
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => D_dly,
TestSignalName => "D",
RefSignal => CLK_dly,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_posedge_posedge,
SetupLow => tsetup_D_CLK_negedge_posedge,
HoldHigh => thold_D_CLK_posedge_posedge,
HoldLow => thold_D_CLK_negedge_posedge,
CheckEnabled => TRUE,
RefTransition => 'R',
HeaderMsg => InstancePath & "/DFFPOSX1",
TimingData => TimeMarker_D_CLK,
Violation => Tviol_D_CLK,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalPeriodPulseCheck (
TestSignal => CLK_dly,
TestSignalName => "CLK",
Period => 0 ps,
PulseWidthHigh => tpw_CLK_posedge,
PulseWidthLow => tpw_CLK_negedge,
PeriodData => PeriodCheckInfo_CLK,
Violation => PWviol_CLK,
HeaderMsg => InstancePath & "/DFFPOSX1",
CheckEnabled => TRUE,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
END IF;
-- Functionality section
NOTIFIER := (
Tviol_D_CLK OR
PWviol_CLK );
intclk := VitalBUF(CLK_dly);
n0_RN_dly := '0';
n0_SN_dly := '0';
VitalStateTable ( StateTable => udp_dff,
DataIn => (NOTIFIER, D_dly, intclk, n0_RN_dly, n0_SN_dly),
NumStates => 1,
Result => n0_vec,
PreviousDataIn => PrevData_udp_dff_n0 );
DS0000 := n0_vec(1);
P0000 := VitalINV(DS0000);
Q_zd := VitalBUF(DS0000);
-- Path delay section
VitalPathDelay01(
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Q_zd,
Paths => (
0 => ( CLK_dly'LAST_EVENT,
tpd_CLK_Q_posedge,
To_X01(CLK_dly) /= '0')),
GlitchData => Q_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity DFFSR is
generic (
tipd_CLK : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
ticd_CLK : VitalDelayType := DefDummyIcd;
tipd_D : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tisd_D_CLK : VitalDelayType := DefDummyIsd;
tipd_R : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tisd_R_CLK : VitalDelayType := DefDummyIsd;
tipd_S : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tisd_S_CLK : VitalDelayType := DefDummyIsd;
trecovery_R_S_posedge_posedge : VitalDelayType := 0 ns;
trecovery_R_CLK_posedge_posedge : VitalDelayType := 0 ns;
tremoval_R_CLK_posedge_posedge : VitalDelayType := 0.1875 ns;
trecovery_S_R_posedge_posedge : VitalDelayType := 0.0937499 ns;
trecovery_S_CLK_posedge_posedge : VitalDelayType := 0 ns;
tremoval_S_CLK_posedge_posedge : VitalDelayType := 0.0937499 ns;
tsetup_D_CLK_posedge_posedge : VitalDelayType := 0.0937499 ns;
tsetup_D_CLK_negedge_posedge : VitalDelayType := 0.0937499 ns;
thold_D_CLK_posedge_posedge : VitalDelayType := 0 ns;
thold_D_CLK_negedge_posedge : VitalDelayType := 0.00000000216744 ns;
tpw_CLK_posedge : VitalDelayType := 0.262012 ns;
tpw_CLK_negedge : VitalDelayType := 0.125679 ns;
tpw_S_negedge : VitalDelayType := 0.214412 ns;
tpw_R_negedge : VitalDelayType := 0.14159 ns;
tremoval_S_R_posedge_posedge : VitalDelayType := VitalZeroDelay;
tremoval_R_S_posedge_posedge : VitalDelayType := VitalZeroDelay;
tpd_CLK_Q_posedge : VitalDelayType01 := (0.425419 ns, 0.320966 ns);
tpd_R_Q_negedge : VitalDelayType01 := (0 ns, 0.260231 ns);
tpd_R_Q_posedge : VitalDelayType01 := (0.348445 ns, 0 ns);
tpd_S_Q_negedge : VitalDelayType01 := (0.397458 ns, 0 ns);
TimingChecksOn : BOOLEAN := false;
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
CLK : in std_ulogic := 'U' ;
D : in std_ulogic := 'U' ;
R : in std_ulogic := 'U' ;
S : in std_ulogic := 'U' ;
Q : out std_ulogic);
attribute VITAL_LEVEL0 of DFFSR : entity is TRUE;
end DFFSR;
architecture behavioral of DFFSR is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL CLK_dly : std_ulogic := 'X';
SIGNAL CLK_ipd : std_ulogic := 'X';
SIGNAL D_dly : std_ulogic := 'X';
SIGNAL D_ipd : std_ulogic := 'X';
SIGNAL R_dly : std_ulogic := 'X';
SIGNAL R_ipd : std_ulogic := 'X';
SIGNAL S_dly : std_ulogic := 'X';
SIGNAL S_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( CLK_ipd, CLK, tipd_CLK );
VitalWireDelay( D_ipd, D, tipd_D );
VitalWireDelay( R_ipd, R, tipd_R );
VitalWireDelay( S_ipd, S, tipd_S );
END BLOCK;
SIGNALDELAY : BLOCK
BEGIN
VitalSignalDelay( CLK_dly, CLK_ipd, ticd_CLK );
VitalSignalDelay( D_dly, D_ipd, tisd_D_CLK );
VitalSignalDelay( R_dly, R_ipd, tisd_R_CLK );
VitalSignalDelay( S_dly, S_ipd, tisd_S_CLK );
END BLOCK;
VITALBehavior : PROCESS (CLK_dly, D_dly, R_dly, S_dly)
--timing checks section variables
VARIABLE Tviol_rec_R_S_posedge : std_ulogic := '0';
VARIABLE TimeMarker_rec_R_S_posedge : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_rec_CLK_S_posedge : std_ulogic := '0';
VARIABLE TimeMarker_rec_CLK_S_posedge : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_rec_S_R_posedge : std_ulogic := '0';
VARIABLE TimeMarker_rec_S_R_posedge : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_rec_CLK_R_posedge : std_ulogic := '0';
VARIABLE TimeMarker_rec_CLK_R_posedge : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_D_CLK : std_ulogic := '0';
VARIABLE TimeMarker_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE PWviol_S_negedge : std_ulogic := '0';
VARIABLE PeriodCheckInfo_S_negedge : VitalPeriodDataType;
VARIABLE PWviol_R_negedge : std_ulogic := '0';
VARIABLE PeriodCheckInfo_R_negedge : VitalPeriodDataType;
VARIABLE PWviol_CLK : std_ulogic := '0';
VARIABLE PeriodCheckInfo_CLK : VitalPeriodDataType;
-- functionality section variables
VARIABLE intclk : std_ulogic;
VARIABLE n0_CLEAR : std_ulogic;
VARIABLE n0_SET : std_ulogic;
VARIABLE P0002 : std_ulogic;
VARIABLE P0003 : std_ulogic;
VARIABLE D_dly_t : std_ulogic;
VARIABLE n0_vec : std_logic_vector( 1 TO 1 );
VARIABLE PrevData_udp_dff_n0 : std_logic_vector( 0 TO 4 );
VARIABLE Q_zd : std_ulogic;
VARIABLE D_EQ_1_AN_S_EQ_1 : std_ulogic;
VARIABLE n1_var : std_ulogic;
VARIABLE D_EQ_0_AN_R_EQ_1 : std_ulogic;
VARIABLE S_EQ_1_AN_R_EQ_1 : std_ulogic;
VARIABLE NOTIFIER : std_ulogic := '0';
-- path delay section variables
VARIABLE Q_GlitchData : VitalGlitchDataType;
BEGIN
-- Timing checks section
IF (TimingChecksOn) THEN
VitalRecoveryRemovalCheck (
TestSignal => S_dly,
TestSignalName => "S",
RefSignal => R_dly,
RefSignalName => "R",
Recovery => trecovery_S_R_posedge_posedge,
Removal => tremoval_S_R_posedge_posedge,
CheckEnabled => TRUE,
ActiveLow => TRUE,
RefTransition => 'R',
HeaderMsg => InstancePath & "/DFFSR",
TimingData => TimeMarker_rec_R_S_posedge,
Violation => Tviol_rec_R_S_posedge,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalRecoveryRemovalCheck (
TestSignal => S_dly,
TestSignalName => "S",
RefSignal => CLK_dly,
RefSignalName => "CLK",
Recovery => trecovery_S_CLK_posedge_posedge,
Removal => tremoval_S_CLK_posedge_posedge,
CheckEnabled => To_X01(D_EQ_0_AN_R_EQ_1) /= '0',
ActiveLow => TRUE,
RefTransition => 'R',
HeaderMsg => InstancePath & "/DFFSR",
TimingData => TimeMarker_rec_CLK_S_posedge,
Violation => Tviol_rec_CLK_S_posedge,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalRecoveryRemovalCheck (
TestSignal => R_dly,
TestSignalName => "R",
RefSignal => S_dly,
RefSignalName => "S",
Recovery => trecovery_R_S_posedge_posedge,
Removal => tremoval_R_S_posedge_posedge,
CheckEnabled => TRUE,
ActiveLow => TRUE,
RefTransition => 'R',
HeaderMsg => InstancePath & "/DFFSR",
TimingData => TimeMarker_rec_S_R_posedge,
Violation => Tviol_rec_S_R_posedge,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalRecoveryRemovalCheck (
TestSignal => R_dly,
TestSignalName => "R",
RefSignal => CLK_dly,
RefSignalName => "CLK",
Recovery => trecovery_R_CLK_posedge_posedge,
Removal => tremoval_R_CLK_posedge_posedge,
CheckEnabled => To_X01(D_EQ_1_AN_S_EQ_1) /= '0',
ActiveLow => TRUE,
RefTransition => 'R',
HeaderMsg => InstancePath & "/DFFSR",
TimingData => TimeMarker_rec_CLK_R_posedge,
Violation => Tviol_rec_CLK_R_posedge,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalSetupHoldCheck (
TestSignal => D_dly,
TestSignalName => "D",
RefSignal => CLK_dly,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_posedge_posedge,
SetupLow => tsetup_D_CLK_negedge_posedge,
HoldHigh => thold_D_CLK_posedge_posedge,
HoldLow => thold_D_CLK_negedge_posedge,
CheckEnabled => To_X01(S_EQ_1_AN_R_EQ_1) /= '0',
RefTransition => 'R',
HeaderMsg => InstancePath & "/DFFSR",
TimingData => TimeMarker_D_CLK,
Violation => Tviol_D_CLK,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalPeriodPulseCheck (
TestSignal => S_dly,
TestSignalName => "S",
Period => 0 ps,
PulseWidthHigh => 0 ns,
PulseWidthLow => tpw_S_negedge,
PeriodData => PeriodCheckInfo_S_negedge,
Violation => PWviol_S_negedge,
HeaderMsg => InstancePath & "/DFFSR",
CheckEnabled => TRUE,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalPeriodPulseCheck (
TestSignal => R_dly,
TestSignalName => "R",
Period => 0 ps,
PulseWidthHigh => 0 ns,
PulseWidthLow => tpw_R_negedge,
PeriodData => PeriodCheckInfo_R_negedge,
Violation => PWviol_R_negedge,
HeaderMsg => InstancePath & "/DFFSR",
CheckEnabled => TRUE,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalPeriodPulseCheck (
TestSignal => CLK_dly,
TestSignalName => "CLK",
Period => 0 ps,
PulseWidthHigh => tpw_CLK_posedge,
PulseWidthLow => tpw_CLK_negedge,
PeriodData => PeriodCheckInfo_CLK,
Violation => PWviol_CLK,
HeaderMsg => InstancePath & "/DFFSR",
CheckEnabled => TRUE,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
END IF;
-- Functionality section
NOTIFIER := (
Tviol_rec_R_S_posedge OR
Tviol_rec_CLK_S_posedge OR
Tviol_rec_S_R_posedge OR
Tviol_rec_CLK_R_posedge OR
Tviol_D_CLK OR
PWviol_S_negedge OR
PWviol_R_negedge OR
PWviol_CLK );
intclk := VitalBUF(CLK_dly);
n0_CLEAR := VitalINV(R_dly);
n0_SET := VitalINV(S_dly);
D_dly_t := VitalINV(D_dly);
VitalStateTable ( StateTable => udp_dff,
DataIn => (NOTIFIER, D_dly_t, intclk, n0_SET, n0_CLEAR),
NumStates => 1,
Result => n0_vec,
PreviousDataIn => PrevData_udp_dff_n0 );
P0003 := n0_vec(1);
P0002 := VitalINV(P0003);
Q_zd := VitalBUF(P0002);
D_EQ_1_AN_S_EQ_1 := VitalAND2(D_dly, S_dly);
n1_var := VitalINV(D_dly);
D_EQ_0_AN_R_EQ_1 := VitalAND2(n1_var, R_dly);
S_EQ_1_AN_R_EQ_1 := VitalAND2(S_dly, R_dly);
-- Path delay section
VitalPathDelay01(
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Q_zd,
Paths => (
0 => ( CLK_dly'LAST_EVENT,
tpd_CLK_Q_posedge,
To_X01(CLK_dly) /= '0'),
1 => ( R_dly'LAST_EVENT,
tpd_R_Q_negedge,
To_X01(R_dly) /= '1'),
2 => ( R_dly'LAST_EVENT,
tpd_R_Q_posedge,
To_X01(R_dly) /= '0'),
3 => ( S_dly'LAST_EVENT,
tpd_S_Q_negedge,
To_X01(S_dly) /= '1')),
GlitchData => Q_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity FAX1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_C : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_YC : VitalDelayType01 := (0.360088 ns, 0.284056 ns);
tpd_A_YS : VitalDelayType01 := (0.385604 ns, 0.289139 ns);
tpd_B_YC : VitalDelayType01 := (0.360796 ns, 0.282487 ns);
tpd_B_YS : VitalDelayType01 := (0.381334 ns, 0.288096 ns);
tpd_C_YC : VitalDelayType01 := (0.357997 ns, 0.275687 ns);
tpd_C_YS : VitalDelayType01 := (0.374129 ns, 0.282399 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
C : in std_ulogic := 'U' ;
YC : out std_ulogic ;
YS : out std_ulogic);
attribute VITAL_LEVEL0 of FAX1 : entity is TRUE;
end FAX1;
architecture behavioral of FAX1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
SIGNAL C_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
VitalWireDelay( C_ipd, C, tipd_C );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd, C_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE n1_var : std_ulogic;
VARIABLE n2_var : std_ulogic;
VARIABLE n3_var : std_ulogic;
VARIABLE YC_zd : std_ulogic;
VARIABLE n4_var : std_ulogic;
VARIABLE YS_zd : std_ulogic;
-- path delay section variables
VARIABLE YC_GlitchData : VitalGlitchDataType;
VARIABLE YS_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalAND2(A_ipd, B_ipd);
n1_var := VitalAND2(B_ipd, C_ipd);
n2_var := VitalOR2(n0_var, n1_var);
n3_var := VitalAND2(C_ipd, A_ipd);
YC_zd := VitalOR2(n2_var, n3_var);
n4_var := VitalXOR2(A_ipd, B_ipd);
YS_zd := VitalXOR2(n4_var, C_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => YC,
OutSignalName => "YC",
OutTemp => YC_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_YC,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_YC,
TRUE),
2 => ( C_ipd'LAST_EVENT,
tpd_C_YC,
TRUE)),
GlitchData => YC_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
VitalPathDelay01(
OutSignal => YS,
OutSignalName => "YS",
OutTemp => YS_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_YS,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_YS,
TRUE),
2 => ( C_ipd'LAST_EVENT,
tpd_C_YS,
TRUE)),
GlitchData => YS_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity HAX1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_YC : VitalDelayType01 := (0.344948 ns, 0.261591 ns);
tpd_A_YS : VitalDelayType01 := (0.362799 ns, 0.264331 ns);
tpd_B_YC : VitalDelayType01 := (0.345539 ns, 0.256117 ns);
tpd_B_YS : VitalDelayType01 := (0.3572 ns, 0.258583 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
YC : out std_ulogic ;
YS : out std_ulogic);
attribute VITAL_LEVEL0 of HAX1 : entity is TRUE;
end HAX1;
architecture behavioral of HAX1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE YS_zd : std_ulogic;
VARIABLE YC_zd : std_ulogic;
-- path delay section variables
VARIABLE YC_GlitchData : VitalGlitchDataType;
VARIABLE YS_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
YS_zd := VitalXOR2(A_ipd, B_ipd);
YC_zd := VitalAND2(A_ipd, B_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => YC,
OutSignalName => "YC",
OutTemp => YC_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_YC,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_YC,
TRUE)),
GlitchData => YC_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
VitalPathDelay01(
OutSignal => YS,
OutSignalName => "YS",
OutTemp => YS_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_YS,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_YS,
TRUE)),
GlitchData => YS_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity INVX1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.334383 ns, 0.22935 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of INVX1 : entity is TRUE;
end INVX1;
architecture behavioral of INVX1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalINV(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity INVX2 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.0535923 ns, 0.0390769 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of INVX2 : entity is TRUE;
end INVX2;
architecture behavioral of INVX2 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalINV(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity INVX4 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.0542471 ns, 0.0399682 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of INVX4 : entity is TRUE;
end INVX4;
architecture behavioral of INVX4 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalINV(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity INVX8 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.0542926 ns, 0.0399237 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of INVX8 : entity is TRUE;
end INVX8;
architecture behavioral of INVX8 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
END BLOCK;
VITALBehavior : PROCESS (A_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalINV(A_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity LATCH is
generic (
tipd_CLK : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
ticd_CLK : VitalDelayType := DefDummyIcd;
tipd_D : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tisd_D_CLK : VitalDelayType := DefDummyIsd;
tsetup_D_CLK_posedge_negedge : VitalDelayType := 0.1875 ns;
tsetup_D_CLK_negedge_negedge : VitalDelayType := 0.1875 ns;
thold_D_CLK_posedge_negedge : VitalDelayType := -0.00000000216744 ns;
thold_D_CLK_negedge_negedge : VitalDelayType := 0 ns;
tpw_CLK_posedge : VitalDelayType := 0.110989 ns;
tpd_CLK_Q_posedge : VitalDelayType01 := (0.197405 ns, 0.168677 ns);
tpd_D_Q : VitalDelayType01 := (0.204494 ns, 0.178792 ns);
TimingChecksOn : BOOLEAN := false;
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
CLK : in std_ulogic := 'U' ;
D : in std_ulogic := 'U' ;
Q : out std_ulogic);
attribute VITAL_LEVEL0 of LATCH : entity is TRUE;
end LATCH;
architecture behavioral of LATCH is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL CLK_dly : std_ulogic := 'X';
SIGNAL CLK_ipd : std_ulogic := 'X';
SIGNAL D_dly : std_ulogic := 'X';
SIGNAL D_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( CLK_ipd, CLK, tipd_CLK );
VitalWireDelay( D_ipd, D, tipd_D );
END BLOCK;
SIGNALDELAY : BLOCK
BEGIN
VitalSignalDelay( CLK_dly, CLK_ipd, ticd_CLK );
VitalSignalDelay( D_dly, D_ipd, tisd_D_CLK );
END BLOCK;
VITALBehavior : PROCESS (CLK_dly, D_dly)
--timing checks section variables
VARIABLE Tviol_D_CLK : std_ulogic := '0';
VARIABLE TimeMarker_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE PWviol_CLK_posedge : std_ulogic := '0';
VARIABLE PeriodCheckInfo_CLK_posedge : VitalPeriodDataType;
-- functionality section variables
VARIABLE n0_RN_dly : std_ulogic := '0';
VARIABLE n0_SN_dly : std_ulogic := '0';
VARIABLE DS0000 : std_ulogic;
VARIABLE P0000 : std_ulogic;
VARIABLE n0_vec : std_logic_vector( 1 TO 1 );
VARIABLE PrevData_udp_tlat_n0 : std_logic_vector( 0 TO 4 );
VARIABLE Q_zd : std_ulogic;
VARIABLE NOTIFIER : std_ulogic := '0';
-- path delay section variables
VARIABLE Q_GlitchData : VitalGlitchDataType;
BEGIN
-- Timing checks section
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => D_dly,
TestSignalName => "D",
RefSignal => CLK_dly,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_posedge_negedge,
SetupLow => tsetup_D_CLK_negedge_negedge,
HoldHigh => thold_D_CLK_posedge_negedge,
HoldLow => thold_D_CLK_negedge_negedge,
CheckEnabled => TRUE,
RefTransition => 'F',
HeaderMsg => InstancePath & "/LATCH",
TimingData => TimeMarker_D_CLK,
Violation => Tviol_D_CLK,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
VitalPeriodPulseCheck (
TestSignal => CLK_dly,
TestSignalName => "CLK",
Period => 0 ps,
PulseWidthHigh => tpw_CLK_posedge,
PulseWidthLow => 0 ns,
PeriodData => PeriodCheckInfo_CLK_posedge,
Violation => PWviol_CLK_posedge,
HeaderMsg => InstancePath & "/LATCH",
CheckEnabled => TRUE,
XOn => DefSeqXOn,
MsgOn => DefSeqMsgOn,
MsgSeverity => WARNING );
END IF;
-- Functionality section
NOTIFIER := (
Tviol_D_CLK OR
PWviol_CLK_posedge );
n0_RN_dly := '0';
n0_SN_dly := '0';
VitalStateTable ( StateTable => udp_tlat,
DataIn => (NOTIFIER, D_dly, CLK_dly, n0_RN_dly, n0_SN_dly),
NumStates => 1,
Result => n0_vec,
PreviousDataIn => PrevData_udp_tlat_n0 );
DS0000 := n0_vec(1);
P0000 := VitalINV(DS0000);
Q_zd := VitalBUF(DS0000);
-- Path delay section
VitalPathDelay01(
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Q_zd,
Paths => (
0 => ( CLK_dly'LAST_EVENT,
tpd_CLK_Q_posedge,
To_X01(CLK_dly) /= '0'),
1 => ( D_dly'LAST_EVENT,
tpd_D_Q,
TRUE)),
GlitchData => Q_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity MUX2X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_S : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.371168 ns, 0.205438 ns);
tpd_B_Y : VitalDelayType01 := (0.372994 ns, 0.204202 ns);
tpd_S_Y : VitalDelayType01 := (0.365381 ns, 0.2111 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
S : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of MUX2X1 : entity is TRUE;
end MUX2X1;
architecture behavioral of MUX2X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
SIGNAL S_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
VitalWireDelay( S_ipd, S, tipd_S );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd, S_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalMUX2(A_ipd, B_ipd, S_ipd);
Y_zd := VitalINV(n0_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE),
2 => ( S_ipd'LAST_EVENT,
tpd_S_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity NAND2X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.345107 ns, 0.196856 ns);
tpd_B_Y : VitalDelayType01 := (0.336319 ns, 0.19685 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of NAND2X1 : entity is TRUE;
end NAND2X1;
architecture behavioral of NAND2X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalAND2(A_ipd, B_ipd);
Y_zd := VitalINV(n0_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity NAND3X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_C : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.354578 ns, 0.187007 ns);
tpd_B_Y : VitalDelayType01 := (0.350956 ns, 0.186309 ns);
tpd_C_Y : VitalDelayType01 := (0.345234 ns, 0.185511 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
C : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of NAND3X1 : entity is TRUE;
end NAND3X1;
architecture behavioral of NAND3X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
SIGNAL C_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
VitalWireDelay( C_ipd, C, tipd_C );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd, C_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE n1_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalAND2(A_ipd, B_ipd);
n1_var := VitalAND2(n0_var, C_ipd);
Y_zd := VitalINV(n1_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE),
2 => ( C_ipd'LAST_EVENT,
tpd_C_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity NOR2X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.359749 ns, 0.232749 ns);
tpd_B_Y : VitalDelayType01 := (0.355257 ns, 0.227842 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of NOR2X1 : entity is TRUE;
end NOR2X1;
architecture behavioral of NOR2X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalOR2(A_ipd, B_ipd);
Y_zd := VitalINV(n0_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity NOR3X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_C : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.387203 ns, 0.249178 ns);
tpd_B_Y : VitalDelayType01 := (0.378956 ns, 0.24302 ns);
tpd_C_Y : VitalDelayType01 := (0.36077 ns, 0.234046 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
C : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of NOR3X1 : entity is TRUE;
end NOR3X1;
architecture behavioral of NOR3X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
SIGNAL C_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
VitalWireDelay( C_ipd, C, tipd_C );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd, C_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE n1_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalOR2(A_ipd, B_ipd);
n1_var := VitalOR2(n0_var, C_ipd);
Y_zd := VitalINV(n1_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE),
2 => ( C_ipd'LAST_EVENT,
tpd_C_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity OAI21X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_C : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.369203 ns, 0.201265 ns);
tpd_B_Y : VitalDelayType01 := (0.365136 ns, 0.198267 ns);
tpd_C_Y : VitalDelayType01 := (0.340702 ns, 0.177778 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
C : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of OAI21X1 : entity is TRUE;
end OAI21X1;
architecture behavioral of OAI21X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
SIGNAL C_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
VitalWireDelay( C_ipd, C, tipd_C );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd, C_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE n1_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalOR2(A_ipd, B_ipd);
n1_var := VitalAND2(n0_var, C_ipd);
Y_zd := VitalINV(n1_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE),
2 => ( C_ipd'LAST_EVENT,
tpd_C_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity OAI22X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_C : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_D : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.377949 ns, 0.188768 ns);
tpd_B_Y : VitalDelayType01 := (0.374067 ns, 0.183907 ns);
tpd_C_Y : VitalDelayType01 := (0.368706 ns, 0.185444 ns);
tpd_D_Y : VitalDelayType01 := (0.36175 ns, 0.181201 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
C : in std_ulogic := 'U' ;
D : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of OAI22X1 : entity is TRUE;
end OAI22X1;
architecture behavioral of OAI22X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
SIGNAL C_ipd : std_ulogic := 'X';
SIGNAL D_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
VitalWireDelay( C_ipd, C, tipd_C );
VitalWireDelay( D_ipd, D, tipd_D );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd, C_ipd, D_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE n1_var : std_ulogic;
VARIABLE n2_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalOR2(C_ipd, D_ipd);
n1_var := VitalOR2(A_ipd, B_ipd);
n2_var := VitalAND2(n0_var, n1_var);
Y_zd := VitalINV(n2_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE),
2 => ( C_ipd'LAST_EVENT,
tpd_C_Y,
TRUE),
3 => ( D_ipd'LAST_EVENT,
tpd_D_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity OR2X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.342477 ns, 0.243741 ns);
tpd_B_Y : VitalDelayType01 := (0.352883 ns, 0.252976 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of OR2X1 : entity is TRUE;
end OR2X1;
architecture behavioral of OR2X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalOR2(A_ipd, B_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity OR2X2 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.0693921 ns, 0.0656425 ns);
tpd_B_Y : VitalDelayType01 := (0.0764625 ns, 0.0744664 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of OR2X2 : entity is TRUE;
end OR2X2;
architecture behavioral of OR2X2 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalOR2(A_ipd, B_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity TBUFX1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_EN : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.365569 ns, 0.203276 ns);
tpd_EN_Y : VitalDelayType01Z := (VitalZeroDelay, VitalZeroDelay, 0.0107727 ns, 0.356689 ns, 0.0272097 ns, 0.195231 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
EN : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of TBUFX1 : entity is TRUE;
end TBUFX1;
architecture behavioral of TBUFX1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL EN_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( EN_ipd, EN, tipd_EN );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, EN_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalINV(A_ipd);
Y_zd := VitalBUFIF1(n0_var, EN_ipd);
-- Path delay section
VitalPathDelay01Z(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
VitalExtendToFillDelay(tpd_A_Y),
TRUE),
1 => ( EN_ipd'LAST_EVENT,
VitalExtendToFillDelay(tpd_EN_Y),
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity TBUFX2 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_EN : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.0690322 ns, 0.0420601 ns);
tpd_EN_Y : VitalDelayType01Z := (VitalZeroDelay, VitalZeroDelay, 0.0107727 ns, 0.0573587 ns, 0.0252425 ns, 0.0362576 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
EN : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of TBUFX2 : entity is TRUE;
end TBUFX2;
architecture behavioral of TBUFX2 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL EN_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( EN_ipd, EN, tipd_EN );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, EN_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalINV(A_ipd);
Y_zd := VitalBUFIF1(n0_var, EN_ipd);
-- Path delay section
VitalPathDelay01Z(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
VitalExtendToFillDelay(tpd_A_Y),
TRUE),
1 => ( EN_ipd'LAST_EVENT,
VitalExtendToFillDelay(tpd_EN_Y),
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity XNOR2X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.360659 ns, 0.206292 ns);
tpd_B_Y : VitalDelayType01 := (0.371926 ns, 0.210513 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of XNOR2X1 : entity is TRUE;
end XNOR2X1;
architecture behavioral of XNOR2X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE n0_var : std_ulogic;
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
n0_var := VitalXOR2(A_ipd, B_ipd);
Y_zd := VitalINV(n0_var);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
LIBRARY IEEE;
USE IEEE.Std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.prim.all;
entity XOR2X1 is
generic (
tipd_A : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tipd_B : VitalDelayType01 := (DefDummyIpd, DefDummyIpd);
tpd_A_Y : VitalDelayType01 := (0.358317 ns, 0.20642 ns);
tpd_B_Y : VitalDelayType01 := (0.372178 ns, 0.210108 ns);
XOn : BOOLEAN := DefCombSpikeXOn;
MsgOn : BOOLEAN := DefCombSpikeMsgOn;
instancePath : STRING := "*" );
port (
A : in std_ulogic := 'U' ;
B : in std_ulogic := 'U' ;
Y : out std_ulogic);
attribute VITAL_LEVEL0 of XOR2X1 : entity is TRUE;
end XOR2X1;
architecture behavioral of XOR2X1 is
attribute VITAL_LEVEL1 of behavioral : architecture is TRUE;
SIGNAL A_ipd : std_ulogic := 'X';
SIGNAL B_ipd : std_ulogic := 'X';
begin
--Input Path Delays
WIREDELAY : BLOCK
BEGIN
VitalWireDelay( A_ipd, A, tipd_A );
VitalWireDelay( B_ipd, B, tipd_B );
END BLOCK;
VITALBehavior : PROCESS (A_ipd, B_ipd)
-- functionality section variables
VARIABLE Y_zd : std_ulogic;
-- path delay section variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN
-- Functionality section
Y_zd := VitalXOR2(A_ipd, B_ipd);
-- Path delay section
VitalPathDelay01(
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (
0 => ( A_ipd'LAST_EVENT,
tpd_A_Y,
TRUE),
1 => ( B_ipd'LAST_EVENT,
tpd_B_Y,
TRUE)),
GlitchData => Y_GlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn,
MsgSeverity => WARNING );
END PROCESS;
end behavioral;
| bsd-3-clause | 406d78661b7f15d840b1129da48530a1 | 0.487611 | 4.262759 | false | false | false | false |
jz0229/open-ephys-pcie | serdes-interface/firmware/SPI_LEDdriver.vhd | 2 | 3,359 | ----------------------------------------------------------------------------------
--this is an parallel to serial converter
--takes command_in and serilize it for the LED driver
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity SPI_LEDdriver is
port (
clk_spi : in std_logic;
reset : in std_logic;
write_start : in std_logic;
command_in : in std_logic_vector(15 downto 0);
led_clk_o : out std_logic;
led_data_o : out std_logic;
led_latch_o : out std_logic
);
end SPI_LEDdriver;
architecture Behavioral of SPI_LEDdriver is
signal led_clk, led_latch : std_logic;
signal led_clk_next, led_latch_next : std_logic;
signal led_data, led_data_next : std_logic_vector(15 downto 0);
type spi_states is (IDLE, OP_lo, OP_hi, LATCHRDY); --state machine definition
signal spi_sm, spi_sm_next : spi_states;
signal sm_cnt, sm_cnt_next : unsigned(3 downto 0);
signal cycle_cnt, cycle_cnt_next : unsigned(3 downto 0);
begin
--ouput mapping
led_clk_o <= led_clk;
led_data_o <= led_data(15);
led_latch_o <= led_latch;
--SPI state machine
SPI_proc: process(clk_spi, reset)
begin
if (reset = '1') then
led_clk <= '0';
led_data <= (others=>'0');
led_latch <= '0';
spi_sm <= IDLE;
sm_cnt <= (others=>'0');
cycle_cnt <= (others=>'0');
elsif (falling_edge(clk_spi)) then --next state logic
led_clk <= led_clk_next;
led_data <= led_data_next;
led_latch <= led_latch_next;
spi_sm <= spi_sm_next;
sm_cnt <= sm_cnt_next;
cycle_cnt <= cycle_cnt_next;
end if;
end process;
--next state logic for the state machines
SPI_proc_next: process(spi_sm, sm_cnt, write_start, command_in, led_data, led_clk, cycle_cnt)
begin
case spi_sm is
when IDLE =>
if write_start = '1' then
if cycle_cnt <= 10 then
led_data_next <= command_in; --"1011011101111001" for testing.
spi_sm_next <= OP_lo;
else
led_data_next <= command_in; --"1011011101111001" for testing.
spi_sm_next <= IDLE;
end if;
else
led_data_next <= led_data;
spi_sm_next <= IDLE;
end if;
sm_cnt_next <= (others=>'0'); --state counter
led_clk_next <= '0';
led_latch_next <= '0';
cycle_cnt_next <= cycle_cnt;
when OP_lo =>
led_data_next <= led_data;
spi_sm_next <= OP_hi;
led_clk_next <= not led_clk; --toggle sclk
sm_cnt_next <= sm_cnt;
led_latch_next <= '0';
cycle_cnt_next <= cycle_cnt;
when OP_hi =>
if sm_cnt>=15 then --state counter triggers at 15
spi_sm_next <= LATCHRDY;
sm_cnt_next <= sm_cnt;
led_latch_next <= '0';
else
spi_sm_next <= OP_lo;
sm_cnt_next <= sm_cnt + 1; --sm counter increment
led_latch_next <= '0';
end if;
led_data_next(15 downto 1) <= led_data(14 downto 0); --shift the command out
led_data_next(0) <= '0'; --pad '0';
led_clk_next <= not led_clk; --toggle sclk
cycle_cnt_next <= cycle_cnt;
when LATCHRDY =>
led_data_next <= led_data;
spi_sm_next <= IDLE;
led_clk_next <= '0'; --toggle sclk
sm_cnt_next <= sm_cnt;
led_latch_next <= '1';
cycle_cnt_next <= cycle_cnt + 1;
end case;
end process;
end Behavioral;
| mit | 1371537ffab59ce5a78ca8d941aa1c19 | 0.564751 | 2.936189 | false | false | false | false |
Hyvok/HardHeat | src/ds18b20.vhd | 1 | 6,113 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity ds18b20 is
generic
(
-- Conversion delay in clock cycles
CONV_DELAY_VAL : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
-- Request temperature
conv_in_f : in std_logic;
-- Connections to 1-wire module
data_in : in std_logic_vector(8 - 1 downto 0);
data_in_f : in std_logic;
busy_in : in std_logic;
error_in : in std_logic;
error_id_in : in unsigned(1 downto 0);
crc_in : in std_logic_vector(8 - 1 downto 0);
reset_ow_out : out std_logic;
data_out : out std_logic_vector(8 - 1 downto 0);
data_out_f : out std_logic;
receive_data_out_f : out std_logic;
-- Temperature output and associated strobe
temp_out : out signed(16 - 1 downto 0);
temp_out_f : out std_logic;
temp_error_out : out std_logic;
pullup_out : out std_logic
);
end entity;
architecture rtl of ds18b20 is
constant DS18B20_ROM_CMD : std_logic_vector(8 - 1 downto 0) := x"CC";
constant DS18B20_CONV_CMD : std_logic_vector(8 - 1 downto 0) := x"44";
constant DS18B20_READ_CMD : std_logic_vector(8 - 1 downto 0) := x"BE";
begin
handler_p: process(clk, reset)
type ds18b20_state is (idle, wait_busy, reset_ow, reset_error, rom_cmd,
conv_cmd, conv_delay, read_cmd, start_read, read_byte);
type data_array is array (9 - 1 downto 0) of
std_logic_vector(8 - 1 downto 0);
variable state : ds18b20_state;
variable next_state : ds18b20_state;
variable next_cmd : ds18b20_state;
variable data : data_array;
variable bytes_left : unsigned(ceil_log2(data_in'length) downto 0);
variable busy_state : std_logic;
variable timer : unsigned(ceil_log2(CONV_DELAY_VAL) downto 0);
begin
if reset = '1' then
state := idle;
next_state := idle;
next_cmd := conv_cmd;
reset_ow_out <= '0';
busy_state := '0';
data := (others => (others => '0'));
bytes_left := (others => '0');
timer := (others => '0');
receive_data_out_f <= '0';
data_out <= (others => '0');
data_out_f <= '0';
temp_out <= (others => '0');
temp_out_f <= '0';
temp_error_out <= '0';
pullup_out <= '1';
elsif rising_edge(clk) then
if state = idle then
temp_out_f <= '0';
if conv_in_f = '1' then
reset_ow_out <= '1';
state := reset_ow;
end if;
elsif state = wait_busy then
data_out_f <= '0';
if not busy_state = busy_in and busy_in = '0' then
state := next_state;
end if;
busy_state := busy_in;
elsif state = reset_ow then
bytes_left := to_unsigned(data'length, bytes_left'length);
reset_ow_out <= '0';
-- Reset error flag
temp_error_out <= '0';
pullup_out <= '1';
state := wait_busy;
next_state := reset_error;
elsif state = reset_error then
-- No device present on the bus, stop and go back to idle
if error_in = '1' and error_id_in = 1 then
temp_error_out <= '1';
state := idle;
else
state := rom_cmd;
end if;
elsif state = rom_cmd then
data_out <= DS18B20_ROM_CMD;
data_out_f <= '1';
state := wait_busy;
next_state := next_cmd;
elsif state = conv_cmd then
data_out <= DS18B20_CONV_CMD;
data_out_f <= '1';
state := wait_busy;
next_state := conv_delay;
elsif state = conv_delay then
data_out_f <= '0';
pullup_out <= '0';
if timer < CONV_DELAY_VAL then
timer := timer + 1;
else
timer := (others => '0');
next_cmd := read_cmd;
reset_ow_out <= '1';
state := reset_ow;
end if;
elsif state = read_cmd then
data_out <= DS18B20_READ_CMD;
data_out_f <= '1';
state := wait_busy;
next_cmd := conv_cmd;
next_state := start_read;
elsif state = start_read then
receive_data_out_f <= '1';
state := read_byte;
elsif state = read_byte then
receive_data_out_f <= '0';
if data_in_f = '1' then
data(data'length - to_integer(bytes_left)) := data_in;
bytes_left := bytes_left - 1;
if bytes_left = 0 then
-- If CRC is valid
if crc_in = x"00" then
state := idle;
temp_out <= signed(std_logic_vector'(
data(1) & data(0)));
temp_out_f <= '1';
else
state := idle;
temp_error_out <= '1';
end if;
else
state := start_read;
end if;
end if;
end if;
end if;
end process;
end;
| mit | 4232ddbac428d82eba434b8eb0715f08 | 0.422706 | 4.135995 | false | false | false | false |
zhlinh/vhdl_course | Exercise/MUX41/MUX41.vhd | 1 | 451 | --4选1信号选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41 IS
PORT(X:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A,B:IN STD_LOGIC;
Y:OUT STD_LOGIC);
END ENTITY MUX41;
ARCHITECTURE ART OF MUX41 IS
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
SEL<=B&A;
PROCESS(X,SEL) IS
BEGIN
IF(SEL="00") THEN Y<=X(0);
ELSIF(SEL="01") THEN Y<=X(1);
ELSIF(SEL="11") THEN Y<=X(2);
ELSE Y<=X(3);
END IF;
END PROCESS;
END ARCHITECTURE ART; | apache-2.0 | 46224e2d601dfd675e9f9ad140f4dfaa | 0.665148 | 2.347594 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/VGA/20x15/user_logic.vhd | 1 | 14,480 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 20x15 Resolution, User Logic VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Sat Oct 15 15:40:57 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 7
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
hsync: out std_logic;
vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component vga is
port (
clk: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
we: in std_logic;
add_bus1: in std_logic_vector(0 to 8);
add_bus2: in std_logic_vector(0 to 8);
add_bus3: in std_logic_vector(0 to 10);
data_bus1: in std_logic_vector(0 to 4);
data_bus2: in std_logic_vector(0 to 4);
data_bus3: in std_logic_vector(0 to 3) );
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 6);
signal slv_reg_read_sel : std_logic_vector(0 to 6);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
vgamodule: vga port map(
clk => Bus2IP_Clk,
hsync => hsync,
vsync => vsync,
rgb => rgb,
we => slv_reg0(31),
add_bus1 => slv_reg1(23 to 31),
add_bus2 => slv_reg2(23 to 31),
add_bus3 => slv_reg3(21 to 31),
data_bus1 => slv_reg4(27 to 31),
data_bus2 => slv_reg5(27 to 31),
data_bus3 => slv_reg6(28 to 31)
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 6);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 6);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
else
case slv_reg_write_sel is
when "1000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6 ) is
begin
case slv_reg_read_sel is
when "1000000" => slv_ip2bus_data <= slv_reg0;
when "0100000" => slv_ip2bus_data <= slv_reg1;
when "0010000" => slv_ip2bus_data <= slv_reg2;
when "0001000" => slv_ip2bus_data <= slv_reg3;
when "0000100" => slv_ip2bus_data <= slv_reg4;
when "0000010" => slv_ip2bus_data <= slv_reg5;
when "0000001" => slv_ip2bus_data <= slv_reg6;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| gpl-3.0 | d67a0de2778b7f5b7ef83de7f633cba7 | 0.496029 | 3.894298 | false | false | false | false |
kjellhar/ArtixPi | blink_led/src/hdl/blink_led.vhd | 1 | 2,156 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/15/2016 03:17:35 AM
-- Design Name:
-- Module Name: blink_led - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity blink_led is
Port (
clk1 : in STD_LOGIC;
clk1_en : out std_logic;
usr_led1 : out std_logic;
usr_led2 : out std_logic);
end blink_led;
architecture Behavioral of blink_led is
constant div1_period : integer := 100000000;
constant div2_period : integer := 30000000;
component clk_wiz_0
port (-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic);
end component;
signal clk100m : std_logic;
signal clk_en_i : std_logic := '1';
signal div1 : integer range 0 to div1_period/2 - 1 := 0;
signal div2 : integer range 0 to div2_period/2 - 1 := 0;
signal led1 : std_logic := '0';
signal led2 : std_logic := '0';
begin
clkgen : clk_wiz_0
port map (
-- Clock in ports
clk_in1 => clk1,
-- Clock out ports
clk_out1 => clk100m
);
process
begin
wait until rising_edge(clk100m);
div1 <= div1 + 1;
div2 <= div2 + 1;
if div1 = 0 then
led1 <= not led1;
end if;
if div2 = 0 then
led2 <= not led2;
end if;
end process;
usr_led1 <= led1;
usr_led2 <= led2;
clk1_en <= clk_en_i;
end Behavioral;
| gpl-3.0 | 156b64027be1bf43c5ca90c2595dca2f | 0.526438 | 3.802469 | false | false | false | false |
thequbit/af_paper | code/xilinx/pixel_difference_2d.vhd | 1 | 1,935 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pixel_difference_2d is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_R : in STD_LOGIC_VECTOR (7 downto 0);
i_G : in STD_LOGIC_VECTOR (7 downto 0);
i_B : in STD_LOGIC_VECTOR (7 downto 0);
i_framevalid : in STD_LOGIC;
i_linevalid : in STD_LOGIC;
o_focusvalue : out STD_LOGIC_VECTOR(31 downto 0);
o_dv : out STD_LOGIC
);
end pixel_difference_2d;
architecture Behavioral of pixel_difference_2d is
COMPONENT color_space_converter
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_R : IN std_logic_vector(7 downto 0);
i_G : IN std_logic_vector(7 downto 0);
i_B : IN std_logic_vector(7 downto 0);
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
o_Y : OUT std_logic_vector(7 downto 0);
o_framevalid : OUT std_logic;
o_linevalid : OUT std_logic
);
END COMPONENT;
COMPONENT focus_calculation_pixel_difference_2d
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
i_Y : IN std_logic_vector(7 downto 0);
o_focusvalue : OUT std_logic_vector(31 downto 0);
o_dv : OUT std_logic
);
END COMPONENT;
signal s_framevalid : STD_LOGIC;
signal s_linevalid : STD_LOGIC;
signal s_Y : STD_LOGIC_VECTOR(7 downto 0);
begin
Inst_color_space_converter: color_space_converter PORT MAP(
i_clk => i_clk,
i_reset => i_reset,
i_R => i_R,
i_G => i_G,
i_B => i_B,
i_framevalid => i_framevalid,
i_linevalid => i_linevalid,
o_Y => s_Y,
o_framevalid => s_framevalid,
o_linevalid => s_linevalid
);
Inst_focus_calculation: focus_calculation_pixel_difference_2d PORT MAP(
i_clk => i_clk,
i_reset => i_reset,
i_framevalid => s_framevalid,
i_linevalid => s_linevalid,
i_Y => s_Y,
o_focusvalue => o_focusvalue,
o_dv => o_dv
);
end Behavioral;
| gpl-3.0 | ee5f727cd55555903933c30a5f70cf55 | 0.62739 | 2.764286 | false | false | false | false |
zhlinh/vhdl_course | Exercise/BIDIR/BIDIR.vhd | 1 | 738 | --双向总线缓存器，有两个数据输入/输出端A和B，一个方向控制端DIR和一个选通端EN。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BIDIR IS
PORT(A,B:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EN,DIR:IN STD_LOGIC);
END ENTITY;
ARCHITECTURE ART OF BIDIR IS
SIGNAL AOUT,BOUT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(A,EN,DIR) IS
BEGIN
IF((EN='0') AND (DIR='1')) THEN BOUT<=A;
ELSE BOUT<="ZZZZZZZZ";
END IF;
B<=BOUT;
END PROCESS;
PROCESS(B,EN,DIR) IS
BEGIN
IF((EN='0') AND (DIR='1')) THEN AOUT<=B;
ELSE AOUT<="ZZZZZZZZ";
END IF;
A<=AOUT;
END PROCESS;
END ARCHITECTURE ART;
| apache-2.0 | e7fae6c9c1fb0e739a9da07048f3d05c | 0.564179 | 2.875536 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/hs_com_control.vhd | 1 | 11,626 | --hs_com_control.vdh
--Jie Zhang, MWL, MIT.
--This module handles the multi-sensor buffering and multiplexing to the xillybus 32bits data FIFO
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.myDeclare.all;
entity hs_com_control is
port (
bus_clk : in std_logic;
global_reset : in std_logic;
--device_num : in std_logic_vector(LOG2_MAX_DEVICE_NUMBER-1 downto 0);
dev_reset_in : in std_logic;
hs_com_fifo_data : out std_logic_vector(31 downto 0);
hs_com_fifo_enb : out std_logic
);
end hs_com_control;
architecture Behavioral of hs_com_control is
type hscomstate_type is (PAUSE, LOOPCHECK, HEADER, DEVICEMAPINDEX, DEVICEPUSH, NEWDEVICE); --state machine definition
signal hscomstate : hscomstate_type;
signal dev_cnt : unsigned(LOG2_MAX_DEVICE_NUMBER-1 downto 0); --allocate a device counter bounded by MAX DEVICE NUMBER
signal data_cnt : unsigned(LOG2_MAX_DATA_FRAME_PER_DEVICE-1 downto 0); --allocate a data counter
signal data_toggle : std_logic := '0'; --used to merge 16bits data to 32bits bus
signal clk_slow : std_logic := '0';
type intan_data_type is array (0 to 66) of std_logic_vector(15 downto 0);
type intan_device_array_type is array (0 to 3) of intan_data_type;
signal intan_device_array : intan_device_array_type;
signal frame_number : unsigned(63 downto 0);
--sensor specific signals
signal threshold, threshold_buf, sensor_clk, sensor_rd, sensor_wr : std_logic_vector(NUMBEROFDEVICE-1 downto 0);
type sensor_data_array_type is array (0 to NUMBEROFDEVICE-1) of std_logic_vector(15 downto 0);
signal sensor_data_in_array : sensor_data_array_type;
signal sensor_data_out_array : sensor_data_array_type;
component clk_div is
generic (MAXD: natural:=5);
port(
clk: in std_logic;
reset: in std_logic;
div: in integer range 0 to MAXD;
div_clk: out std_logic
);
end component;
begin
clk_div_slow: clk_div generic map (MAXD => 125)
port map ( clk => bus_clk, reset => global_reset, div => 125, div_clk => clk_slow);
clk_div_intan_0: clk_div generic map (MAXD => 2)
port map ( clk => clk_slow, reset => global_reset, div => 2, div_clk => sensor_clk(0));
clk_div_intan_1: clk_div generic map (MAXD => 7)
port map ( clk => clk_slow, reset => global_reset, div => 5, div_clk => sensor_clk(1));
clk_div_imu_2: clk_div generic map (MAXD => 2000)
port map ( clk => clk_slow, reset => global_reset, div => 2000, div_clk => sensor_clk(2));
--some fake intan operations:
intan_proc: process(clk_slow, global_reset, hscomstate)
begin
if (global_reset = '1') then
for i in 0 to 3 loop
for j in 0 to 66 loop
intan_device_array(i)(j) <= (others=>'0');
end loop;
end loop;
elsif (rising_edge(clk_slow)) then
if hscomstate = NEWDEVICE then
for i in 0 to 3 loop
for j in 0 to 66 loop
intan_device_array(i)(j) <= std_logic_vector(unsigned(intan_device_array(i)(j)) + j);
end loop;
end loop;
end if;
end if;
end process;
--instantiate sensor FIFOs
-- 32bit uni-directional data bus to the host
fifo_intan_inst_0 : fifo_intan_16bits
port map(
wr_clk => sensor_clk(0),
rd_clk => bus_clk,
rst => '0',
din => (others=>'0'),
wr_en => '1',
rd_en => sensor_rd(0),
dout => sensor_data_out_array(0),
full => open,
empty => open,
prog_empty => threshold(0)
);
fifo_intan_inst_1 : fifo_intan_16bits
port map(
wr_clk => sensor_clk(1),
rd_clk => bus_clk,
rst => '0',
din => (others=>'0'),
wr_en => '1',
rd_en => sensor_rd(1),
dout => sensor_data_out_array(1),
full => open,
empty => open,
prog_empty => threshold(1)
);
fifo_imu_inst_0 : fifo_imu_16bits
port map(
wr_clk => sensor_clk(2),
rd_clk => bus_clk,
rst => '0',
din => (others=>'0'),
wr_en => '1',
rd_en => sensor_rd(2),
dout => sensor_data_out_array(2),
full => open,
empty => open,
prog_empty => threshold(2)
);
--hs com state machine
hs_com_proc: process(bus_clk, global_reset, data_cnt, threshold_buf, threshold, sensor_clk, sensor_rd)
begin
if (dev_reset_in = '1' or global_reset = '1') then
hscomstate <= PAUSE;
dev_cnt <= (others=>'0');
data_cnt <= (others=>'0');
data_toggle <= '0';
hs_com_fifo_data <= (others=>'0');
hs_com_fifo_enb <= '0';
frame_number <= (others=>'0');
threshold_buf <= (others=>'1');
sensor_rd <= (others=>'0');
elsif (rising_edge(bus_clk)) then
case hscomstate is
when PAUSE =>
if data_cnt >= 500 then --pause 500 cycles
hscomstate <= LOOPCHECK;
threshold_buf <= threshold;
data_cnt <= (others=>'0');
else
data_cnt <= data_cnt + 1;
end if;
hs_com_fifo_data <= (others=>'0');
hs_com_fifo_enb <= '0';
threshold_buf <= (others=>'1');
sensor_rd <= (others=>'0');
dev_cnt <= (others=>'0');
when LOOPCHECK =>
hs_com_fifo_enb <= '0';
data_toggle <= '0';
sensor_rd <= (others=>'0');
--count the number of devices that is not zero.
if data_cnt > NUMBEROFDEVICE-1 then
if dev_cnt > 0 then
hscomstate <= HEADER;
else
hscomstate <= LOOPCHECK;
dev_cnt <= (others=>'0');
threshold_buf <= threshold;
end if;
data_cnt <= (others=>'0');
else
if (threshold_buf(to_integer(data_cnt)) = '0') then
dev_cnt <= dev_cnt + 1;
end if;
hscomstate <= LOOPCHECK;
data_cnt <= data_cnt + 1;
end if;
when HEADER =>
if data_cnt = 0 then --send first 32bits of frame number (bytes 0-3)
hs_com_fifo_data <= std_logic_vector(frame_number(31 downto 0));
--hs_com_fifo_data <= x"01_23_45_67";
--hs_com_fifo_data <= x"00_00_00_01";
elsif data_cnt = 1 then --send the rest 32bits of frame number (bytes 4-7)
--hs_com_fifo_data <= x"00_00_00_00";
hs_com_fifo_data <= std_logic_vector(frame_number(63 downto 32));
elsif data_cnt = 2 then
hs_com_fifo_data(15 downto 0) <= std_logic_vector(to_unsigned(to_integer(dev_cnt), 16)); --3 devices in this frame
hs_com_fifo_data(23 downto 16) <= (others=>'0'); --corrupt
hs_com_fifo_data(31 downto 24) <= (others=>'0'); --reserved
else --reserved
hs_com_fifo_data <= (others=>'0');
end if;
hs_com_fifo_enb <= '1';
if data_cnt >= 7 then
data_cnt <= (others=>'0');
hscomstate <= DEVICEMAPINDEX;
dev_cnt <= (others=>'0');
else
data_cnt <= data_cnt + 1;
hscomstate <= HEADER;
end if;
when DEVICEMAPINDEX =>
if dev_cnt >= NUMBEROFDEVICE-1 then --3 device
dev_cnt <= (others=>'0');
hscomstate <= NEWDEVICE;
else
dev_cnt <= dev_cnt + 1;
hscomstate <= DEVICEMAPINDEX;
end if;
if (threshold_buf(to_integer(dev_cnt)) = '0') then --almost empty flag not asserted
hs_com_fifo_data <= std_logic_vector(to_unsigned(to_integer(dev_cnt),32));
hs_com_fifo_enb <= '1';
else
hs_com_fifo_enb <= '0';
end if;
when DEVICEPUSH =>
if data_cnt >= data_length_array(to_integer(dev_cnt))-1 then
hscomstate <= NEWDEVICE;
dev_cnt <= dev_cnt + 1;
sensor_rd(to_integer(dev_cnt)) <= '0';
else
data_cnt <= data_cnt + 1;
sensor_rd(to_integer(dev_cnt)) <= '1';
end if;
data_toggle <= not data_toggle;
if data_toggle = '0' then
hs_com_fifo_data(15 downto 0) <= intan_device_array(to_integer(dev_cnt))(to_integer(data_cnt));
hs_com_fifo_enb <= '0';
else
hs_com_fifo_data(31 downto 16) <= intan_device_array(to_integer(dev_cnt))(to_integer(data_cnt));
hs_com_fifo_enb <= '1';
end if;
when NEWDEVICE =>
if (dev_cnt > NUMBEROFDEVICE-1) then
if data_toggle = '1' then --needs padding
hs_com_fifo_data(31 downto 16) <= (others=>'0');
hs_com_fifo_enb <= '1';
else
hs_com_fifo_enb <= '0';
end if;
hscomstate <= LOOPCHECK;
frame_number <= frame_number + 1;
dev_cnt <= (others=>'0');
threshold_buf <= threshold;
else
if threshold_buf(to_integer(dev_cnt)) = '0' then --asserted
sensor_rd(to_integer(dev_cnt)) <= '1';
hscomstate <= DEVICEPUSH;
else
dev_cnt <= dev_cnt + 1;
hscomstate <= NEWDEVICE;
end if;
hs_com_fifo_enb <= '0';
end if;
data_cnt <= (others=>'0');
end case;
end if;
end process;
end Behavioral;
| mit | f495f3cc4e568183f9bbbd7bb31e1b2b | 0.434715 | 4.267988 | false | false | false | false |
upci/upci | Projeto/pc.vhd | 1 | 2,554 | ---- Program Counter ---------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE work.processor_functions.all;
------------------------------------------------------------------------------------------------------------------
ENTITY pc IS
PORT (clk, nrst: IN STD_LOGIC; -- reset ativo em zero
PC_inc: IN STD_LOGIC; -- sinal que indica que o PC deve ser incrementado
PC_load: IN STD_LOGIC; -- sinal que indica que PC deve ser substituido pelo valor em PC_bus
PC_valid: IN STD_LOGIC; -- sinal que indica que o valor de PC deve ser colocado em PC_bus (ou Z se 0)
PC_bus: INOUT STD_LOGIC_VECTOR(n-1 DOWNTO 0);
PC_7seg: OUT STD_LOGIC_VECTOR(0 TO 15)); -- barramento de entrada/saida
END ENTITY pc;
------------------------------------------------------------------------------------------------------------------
ARCHITECTURE rtl OF pc IS
SIGNAL counter: INTEGER RANGE 0 to 2**n -1; -- contador em si
SIGNAL counter_vector: STD_LOGIC_VECTOR(n-1 DOWNTO 0);
COMPONENT bcd_to_7seg IS
PORT (bcd: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
en: IN STD_LOGIC;
output: OUT STD_LOGIC_VECTOR (0 TO 7));
END COMPONENT;
BEGIN
-- Se o PC_valid = '1', manda o valor do PC pro barramento. Caso contrario, manda Z.
PC_bus <= counter_vector
WHEN PC_valid = '1'
ELSE (OTHERS => 'Z');
counter_vector <= STD_LOGIC_VECTOR(to_unsigned(counter, PC_bus'length));
-- Gera a visualizacao 7seg
counter7seg_0: bcd_to_7seg PORT MAP(counter_vector(3 DOWNTO 0), seg_en, PC_7seg(0 TO 7));
counter7seg_1: bcd_to_7seg PORT MAP(counter_vector(7 DOWNTO 4), seg_en, PC_7seg(8 TO 15));
PROCESS (clk, nrst) IS
BEGIN
-- De forma assincrona, se o reset ficar em nivel 0, volta o contador pra 0
IF nrst = '0' THEN
counter <= 0;
-- Se teve uma borda de subida no clock, faz as outras coisas
ELSIF rising_edge(clk) THEN
-- A maior prioridade eh do incremento. Se esta em 1, incrementa o PC
IF PC_inc = '1' THEN
counter <= counter + 1;
-- Caso contrario, verifica se eh pra carregar o valor do bus.
ELSIF PC_load = '1' THEN
-- O PC_load deve carregar apenas o endereco, desconsiderando o OPCODE
counter <= TO_INTEGER(UNSIGNED(PC_bus(n-oplen-1 DOWNTO 0))); -- Cast de STD_LOGIC_VECTOR pra INTEGER
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
------------------------------------------------------------------------------------------------------------------ | gpl-2.0 | a04162fbeab07e37907b05e9ddbaaefe | 0.567006 | 3.640514 | false | false | false | false |
upci/upci | Projeto/processor.vhd | 1 | 2,899 | -- The processor --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.processor_functions.all;
ENTITY processor IS
PORT (clk, nrst, WAKE_signal: IN std_logic;
-- Switches
switches: IN std_logic_vector(17 downto 0);
-- Leds vermelhos
red_leds: OUT std_logic_vector(17 downto 0);
-- Leds verdes
green_leds: OUT std_logic_vector(8 downto 0);
-- 7 Seg
hex7: OUT std_logic_vector(0 TO 7);
hex6: OUT std_logic_vector(0 TO 7);
hex5: OUT std_logic_vector(0 TO 7);
hex4: OUT std_logic_vector(0 TO 7);
hex3: OUT std_logic_vector(0 TO 7);
hex2: OUT std_logic_vector(0 TO 7);
hex1: OUT std_logic_vector(0 TO 7);
hex0: OUT std_logic_vector(0 TO 7));
END ENTITY processor;
ARCHITECTURE processor OF processor IS
SIGNAL CONTROL_bus: std_logic_vector(n-1 DOWNTO 0);
SIGNAL clk_out: std_logic;
-- IR
SIGNAL IR_opcode: opcode;
SIGNAL IR_load: std_logic;
SIGNAL IR_valid: std_logic;
SIGNAL IR_opcode_leds: std_logic_vector(3 DOWNTO 0);
-- PC
SIGNAL PC_inc: std_logic;
SIGNAL PC_load: std_logic;
SIGNAL PC_valid: std_logic;
SIGNAL PC_7seg: std_logic_vector(0 TO 15);
-- Memory
SIGNAL MDR_load: std_logic;
SIGNAL MAR_load: std_logic;
SIGNAL MEM_valid: std_logic;
SIGNAL MEM_en: std_logic;
SIGNAL MEM_rw: std_logic;
-- ALU
SIGNAL ALU_zero: std_logic;
SIGNAL ALU_slt: std_logic;
SIGNAL ALU_valid: std_logic;
SIGNAL ALU_enable: std_logic;
SIGNAL ALU_cmd: std_logic_vector(3 DOWNTO 0);
-- IO
SIGNAL IODR_load: std_logic;
SIGNAL IOAR_load: std_logic;
SIGNAL IO_valid: std_logic;
SIGNAL IO_en: std_logic;
SIGNAL IO_rw: std_logic;
BEGIN
-- Para visualizacao
green_leds(0) <= not nrst;
green_leds(7) <= not WAKE_signal;
red_leds(17) <= clk_out;
red_leds(11 DOWNTO 0) <= CONTROL_bus;
red_leds(16 DOWNTO 13) <= IR_opcode_leds;
hex7 <= "01100001";
hex5 <= PC_7seg(8 TO 15);
hex4 <= PC_7seg(0 TO 7);
-- Divisor de clock
clock_divisor : entity work.clock_divisor port map(clk, nrst, clk_out);
-- Entidades internas
controller : entity work.controller port map(clk_out, nrst, CONTROL_bus, hex6, IR_opcode, IR_load, IR_valid, PC_inc, PC_load, PC_valid, MDR_load, MAR_load, MEM_valid, MEM_en, MEM_rw, ALU_zero, ALU_valid, ALU_slt, ALU_enable, ALU_cmd, IODR_load, IOAR_load, IO_valid, IO_en, IO_rw, WAKE_signal, green_leds(8));
memory : entity work.memory port map(clk_out, nrst, MDR_load, MAR_load, MEM_valid, MEM_en, MEM_rw, CONTROL_bus);
alu : entity work.alu port map(clk_out, nrst, ALU_cmd, ALU_zero, ALU_slt, ALU_valid, ALU_enable, CONTROL_bus);
ir : entity work.ir port map(clk_out, nrst, IR_load, IR_valid, IR_opcode, CONTROL_bus, IR_opcode_leds);
pc : entity work.pc port map(clk_out, nrst, PC_inc, PC_load, PC_valid, CONTROL_bus, PC_7seg);
io : entity work.io port map(clk_out, nrst, IODR_load, IOAR_load, IO_valid, IO_en, IO_rw, CONTROL_bus, switches, hex3, hex2, hex1, hex0);
END ARCHITECTURE; | gpl-2.0 | 3a4e73c3c11de759da4e64ce566e7480 | 0.684029 | 2.694238 | false | false | false | false |
upci/upci | Projeto/processor_functions.vhd | 1 | 2,141 | LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
PACKAGE processor_functions IS
TYPE opcode IS (LOAD, STORE, ADD, NOTT, ANDD, ORR, XORR, INC, SUB, JUMP, BZERO, BGREATER, BLESS, DEC, NOP, WAITT);
FUNCTION decode (word: STD_LOGIC_VECTOR) RETURN opcode;
FUNCTION cmdDecode (op: opcode) RETURN STD_LOGIC_VECTOR;
CONSTANT n: integer := 12;
CONSTANT seg_en: STD_LOGIC := '1';
CONSTANT wordlen: integer := 12;
CONSTANT oplen: integer := 4;
CONSTANT clk_frequency : integer := 1000000;
CONSTANT mem_limit: INTEGER := 128;
TYPE memory_array IS ARRAY (0 to 2**(n-oplen-1)) of STD_LOGIC_VECTOR(n-1 DOWNTO 0);
CONSTANT reg_zero: unsigned (n-1 DOWNTO 0) := (OTHERS => '0');
END PACKAGE processor_functions;
PACKAGE BODY processor_functions IS
FUNCTION decode (word: STD_LOGIC_VECTOR) RETURN opcode IS
VARIABLE opcode_out: opcode;
BEGIN
CASE word(n-1 DOWNTO n-oplen) IS
WHEN "0000" => opcode_out := LOAD;
WHEN "0001" => opcode_out := STORE;
WHEN "0010" => opcode_out := ADD;
WHEN "0011" => opcode_out := SUB;
WHEN "0100" => opcode_out := INC;
WHEN "0101" => opcode_out := DEC;
WHEN "0110" => opcode_out := NOTT;
WHEN "0111" => opcode_out := ANDD;
WHEN "1000" => opcode_out := ORR;
WHEN "1001" => opcode_out := XORR;
WHEN "1010" => opcode_out := JUMP;
WHEN "1011" => opcode_out := BZERO;
WHEN "1100" => opcode_out := BGREATER;
WHEN "1101" => opcode_out := BLESS;
WHEN "1110" => opcode_out := WAITT;
WHEN "1111" => opcode_out := NOP;
WHEN OTHERS => NULL;
END CASE;
RETURN opcode_out;
END FUNCTION decode;
FUNCTION cmdDecode (op: opcode) RETURN STD_LOGIC_VECTOR IS
VARIABLE cmd_out: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
CASE op IS
WHEN LOAD => cmd_out := "0000";
WHEN ADD => cmd_out := "0001";
WHEN NOTT => cmd_out := "0010";
WHEN ORR => cmd_out := "0011";
WHEN ANDD => cmd_out := "0100";
WHEN XORR => cmd_out := "0101";
WHEN INC => cmd_out := "0110";
WHEN SUB => cmd_out := "0111";
WHEN DEC => cmd_out := "1000";
WHEN OTHERS => NULL;
END CASE;
RETURN cmd_out;
END FUNCTION cmdDecode;
END PACKAGE BODY processor_functions; | gpl-2.0 | 48dc1d9d7b09053934b5a2d4c7adea1a | 0.642223 | 2.990223 | false | false | false | false |
pren-et/bldc | diskret/vhdl/commutate/commutate.vhd | 1 | 4,517 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:45:53 11/22/2014
-- Design Name:
-- Module Name: commutate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity commutate is
generic (
CLK_FRQ : integer := 50_000_000; -- 50 MHz
PWM_FRQ : integer := 285
);
Port ( clk : in STD_ULOGIC;
rst : in STD_ULOGIC;
sw : in STD_ULOGIC_VECTOR (3 downto 0);
h : in STD_ULOGIC_VECTOR (2 downto 0);
led : out STD_ULOGIC_VECTOR (7 downto 0);
u_l : out STD_ULOGIC;
u_h : out STD_ULOGIC;
v_l : out STD_ULOGIC;
v_h : out STD_ULOGIC;
w_l : out STD_ULOGIC;
w_h : out STD_ULOGIC;
h_b : out STD_ULOGIC);
end commutate;
architecture Behavioral of commutate is
signal h_buffered : STD_ULOGIC_VECTOR (2 downto 0);
signal pwm : STD_ULOGIC;
signal pwm_clk : STD_ULOGIC;
signal div_cnt : unsigned (15 downto 0);
signal pwm_cnt : STD_ULOGIC_VECTOR (3 downto 0);
begin
f_div : process (rst, clk)
begin
if rst = '1' then
div_cnt <= (others => '0');
pwm_clk <= '0';
elsif rising_edge(clk) then
if div_cnt = to_unsigned(0, 16) then
div_cnt <= to_unsigned(156, 16);
pwm_clk <= '1';
else
div_cnt <= div_cnt - 1;
pwm_clk <= '0';
end if;
end if;
end process;
p_pwm : process (rst, clk, pwm_clk, sw)
begin
if rst = '1' then
pwm_cnt <= "0000";
pwm <= '0';
elsif rising_edge(clk) then
if pwm_clk = '1' then
if pwm_cnt = "1111" then
pwm_cnt <= "0000";
else
pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
end if;
if pwm_cnt < sw then
pwm <= '1';
else
pwm <= '0';
end if;
end if;
end if;
end process;
h_buffer : process (pwm, h)
begin
if falling_edge(pwm) then
h_buffered <= h;
else
h_buffered <= h_buffered;
end if;
end process;
h_b <= h_buffered(0);
led(0) <= not h(0);
led(1) <= not h(1);
led(2) <= not h(2);
led(3) <= pwm;
led(4) <= pwm_clk;
led(5) <= '0';
led(6) <= '0';
led(7) <= '0';
comm : process (pwm, h_buffered )
begin
case h_buffered is
when "000" =>
u_l <= '0';
u_h <= '0';
v_l <= '0';
v_h <= '0';
w_l <= '0';
w_h <= '0';
when "001" =>
u_l <= '0';
u_h <= '0';
v_l <= pwm;
v_h <= '0';
w_l <= '0';
w_h <= pwm;
when "010" =>
u_l <= pwm;
u_h <= '0';
v_l <= '0';
v_h <= pwm;
w_l <= '0';
w_h <= '0';
when "011" =>
u_l <= pwm;
u_h <= '0';
v_l <= '0';
v_h <= '0';
w_l <= '0';
w_h <= pwm;
when "100" =>
u_l <= '0';
u_h <= pwm;
v_l <= '0';
v_h <= '0';
w_l <= pwm;
w_h <= '0';
when "101" =>
u_l <= '0';
u_h <= pwm;
v_l <= pwm;
v_h <= '0';
w_l <= '0';
w_h <= '0';
when "110" =>
u_l <= '0';
u_h <= '0';
v_l <= '0';
v_h <= pwm;
w_l <= pwm;
w_h <= '0';
when "111" =>
u_l <= '0';
u_h <= '0';
v_l <= '0';
v_h <= '0';
w_l <= '0';
w_h <= '0';
when others =>
u_l <= '0';
u_h <= '0';
v_l <= '0';
v_h <= '0';
w_l <= '0';
w_h <= '0';
end case;
end process;
end Behavioral;
| gpl-2.0 | 43eaa43edebb775a8f49e24d6fec3080 | 0.395617 | 3.333579 | false | false | false | false |
zhlinh/vhdl_course | Assignment/LED_CNT/SCANNER.vhd | 1 | 1,023 | --Scanner Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SCANNER IS
PORT ( CLK_SCAN : IN STD_LOGIC;
RESET: IN STD_LOGIC;
DIN12 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
NUM : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
SEL : OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END ENTITY SCANNER;
ARCHITECTURE ART1 OF SCANNER IS
SIGNAL SEL_REG : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
PROCESS(SEL_REG)
BEGIN
SEL <= SEL_REG;
END PROCESS;
PROCESS(CLK_SCAN,RESET)
BEGIN
IF(RESET='0') THEN
SEL_REG <= "00";
ELSIF(CLK_SCAN'EVENT AND CLK_SCAN='1') THEN
IF (SEL_REG = "11") THEN
SEL_REG <= "01";
ELSE
SEL_REG <= SEL_REG + 1;
END IF;
END IF;
END PROCESS;
PROCESS(SEL_REG)
BEGIN
CASE(SEL_REG) IS
WHEN "01" =>
NUM <= DIN12(3 DOWNTO 0);
WHEN "10" =>
NUM <= DIN12(7 DOWNTO 4);
WHEN "11" =>
NUM <= DIN12(11 DOWNTO 8);
WHEN OTHERS =>
NUM <= (OTHERS=> '0');
END CASE;
END PROCESS;
END ARCHITECTURE ART1; | apache-2.0 | 89f686f3eb20c3d63643ebd51e01906e | 0.602151 | 2.772358 | false | false | false | false |
sudov/options-accel | zedboard/xillinux-eval-zedboard-1.1/vhdl/src/xillydemo.vhd | 2 | 18,174 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
component xillybus
port (
PS_CLK : IN std_logic;
PS_PORB : IN std_logic;
PS_SRSTB : IN std_logic;
clk_100 : IN std_logic;
otg_oc : IN std_logic;
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
PS_GPIO : INOUT std_logic_vector(55 DOWNTO 0);
DDR_WEB : OUT std_logic;
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
vga4_blue : OUT std_logic_vector(3 DOWNTO 0);
vga4_green : OUT std_logic_vector(3 DOWNTO 0);
vga4_red : OUT std_logic_vector(3 DOWNTO 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_r_audio_rden : OUT std_logic;
user_r_audio_empty : IN std_logic;
user_r_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : IN std_logic;
user_r_audio_open : OUT std_logic;
user_w_audio_wren : OUT std_logic;
user_w_audio_full : IN std_logic;
user_w_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_audio_open : OUT std_logic;
user_r_smb_rden : OUT std_logic;
user_r_smb_empty : IN std_logic;
user_r_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : IN std_logic;
user_r_smb_open : OUT std_logic;
user_w_smb_wren : OUT std_logic;
user_w_smb_full : IN std_logic;
user_w_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_smb_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
component i2s_audio
port (
bus_clk : IN std_logic;
clk_100 : IN std_logic;
quiesce : IN std_logic;
audio_mclk : OUT std_logic;
audio_dac : OUT std_logic;
audio_adc : IN std_logic;
audio_bclk : IN std_logic;
audio_lrclk : IN std_logic;
user_r_audio_rden : IN std_logic;
user_r_audio_empty : OUT std_logic;
user_r_audio_data : OUT std_logic_vector(31 DOWNTO 0);
user_r_audio_eof : OUT std_logic;
user_r_audio_open : IN std_logic;
user_w_audio_wren : IN std_logic;
user_w_audio_full : OUT std_logic;
user_w_audio_data : IN std_logic_vector(31 DOWNTO 0);
user_w_audio_open : IN std_logic);
end component;
component smbus
port (
bus_clk : IN std_logic;
quiesce : IN std_logic;
smb_sclk : OUT std_logic;
smb_sdata : INOUT std_logic;
smbus_addr : OUT std_logic_vector(1 DOWNTO 0);
user_r_smb_rden : IN std_logic;
user_r_smb_empty : OUT std_logic;
user_r_smb_data : OUT std_logic_vector(7 DOWNTO 0);
user_r_smb_eof : OUT std_logic;
user_r_smb_open : IN std_logic;
user_w_smb_wren : IN std_logic;
user_w_smb_full : OUT std_logic;
user_w_smb_data : IN std_logic_vector(7 DOWNTO 0);
user_w_smb_open : IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32 : std_logic;
signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_r_audio_rden : std_logic;
signal user_r_audio_empty : std_logic;
signal user_r_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_r_audio_eof : std_logic;
signal user_r_audio_open : std_logic;
signal user_w_audio_wren : std_logic;
signal user_w_audio_full : std_logic;
signal user_w_audio_data : std_logic_vector(31 DOWNTO 0);
signal user_w_audio_open : std_logic;
signal user_r_smb_rden : std_logic;
signal user_r_smb_empty : std_logic;
signal user_r_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_r_smb_eof : std_logic;
signal user_r_smb_open : std_logic;
signal user_w_smb_wren : std_logic;
signal user_w_smb_full : std_logic;
signal user_w_smb_data : std_logic_vector(7 DOWNTO 0);
signal user_w_smb_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,
-- Ports related to /dev/xillybus_audio
-- FPGA to CPU signals:
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
-- CPU to FPGA signals:
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open,
-- Ports related to /dev/xillybus_smb
-- FPGA to CPU signals:
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
-- CPU to FPGA signals:
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open,
-- General signals
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
clk_100 => clk_100,
otg_oc => otg_oc,
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
MIO => MIO,
PS_GPIO => PS_GPIO,
DDR_WEB => DDR_WEB,
GPIO_LED => GPIO_LED,
bus_clk => bus_clk,
quiesce => quiesce,
vga4_blue => vga4_blue,
vga4_green => vga4_green,
vga4_red => vga4_red,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync
);
-- Xillybus Lite
user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;
-- A simple inferred RAM
ram_addr <= conv_integer(user_mem_8_addr);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
-- 32-bit loopback
fifo_32 : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => user_w_write_32_full,
empty => user_r_read_32_empty
);
reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
user_r_read_32_eof <= '0';
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
audio_ins : i2s_audio
port map(
bus_clk => bus_clk,
clk_100 => clk_100,
quiesce => quiesce,
audio_mclk => audio_mclk,
audio_dac => audio_dac,
audio_adc => audio_adc,
audio_bclk => audio_bclk,
audio_lrclk => audio_lrclk,
user_r_audio_rden => user_r_audio_rden,
user_r_audio_empty => user_r_audio_empty,
user_r_audio_data => user_r_audio_data,
user_r_audio_eof => user_r_audio_eof,
user_r_audio_open => user_r_audio_open,
user_w_audio_wren => user_w_audio_wren,
user_w_audio_full => user_w_audio_full,
user_w_audio_data => user_w_audio_data,
user_w_audio_open => user_w_audio_open
);
smbus_ins : smbus
port map(
bus_clk => bus_clk,
quiesce => quiesce,
smb_sclk => smb_sclk,
smb_sdata => smb_sdata,
smbus_addr => smbus_addr,
user_r_smb_rden => user_r_smb_rden,
user_r_smb_empty => user_r_smb_empty,
user_r_smb_data => user_r_smb_data,
user_r_smb_eof => user_r_smb_eof,
user_r_smb_open => user_r_smb_open,
user_w_smb_wren => user_w_smb_wren,
user_w_smb_full => user_w_smb_full,
user_w_smb_data => user_w_smb_data,
user_w_smb_open => user_w_smb_open
);
end sample_arch;
| apache-2.0 | 023e863018d49abebbdc636d672e25ed | 0.599043 | 2.887512 | false | false | false | false |
luk51000/tg2 | Experimentos/ex1/Sources/static/clocks.vhd | 1 | 7,632 | -- file: clocks.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___200.000______0.000______50.0_______98.146_____89.971
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocks is
port
(-- Clock in ports
CLK_IN_P : in std_logic;
CLK_IN_N : in std_logic;
-- Clock out ports
CLK_OUT : out std_logic
);
end clocks;
architecture xilinx of clocks is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocks,clk_wiz_v3_6,{component_name=clocks,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFGDS
port map
(O => clkin1,
I => CLK_IN_P,
IB => CLK_IN_N);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 5.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 5.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_unused,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT,
I => clkout0);
end xilinx;
| gpl-3.0 | 5e9e10fa15b6b7f43d4983138688cbb1 | 0.584644 | 4.202643 | false | false | false | false |
zhlinh/vhdl_course | Exercise/MUXB41/MUXB41.vhd | 1 | 513 | --4选1数据选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUXB41 IS
PORT(DATA0,DATA1,DATA2,DATA3:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A,B:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
ARCHITECTURE ART OF MUXB41 IS
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
SEL<=B&A;
PROCESS(SEL)
BEGIN
CASE SEL IS
WHEN "00"=>Y<=DATA0;
WHEN "01"=>Y<=DATA1;
WHEN "10"=>Y<=DATA2;
WHEN "11"=>Y<=DATA3;
WHEN OTHERS=>Y<=NULL;
END CASE;
END PROCESS;
END ARCHITECTURE ART; | apache-2.0 | d9c1f5a61e4751318890c62e97a4a06e | 0.674651 | 2.443902 | false | false | false | false |
jz0229/open-ephys-pcie | oepcie_host_firmware/HDLs/async_com_control.vhd | 1 | 11,496 | --async_com_control.vdh
--by Jie Zhang, MWL, MIT.
--this module controls the async communication interface. It sends COBS encoded streams to the 8-bit width communication channel
--it detects a magic word from the headstage, which symbolizes the transmission of configuration details of the headstage.
--This module then encodes them using COBS before transmitting to the host.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use WORK.myDeclare.all;
entity async_com_control is
port (
bus_clk : in std_logic;
reset : in std_logic;
--pclk : in std_logic;
--din : in std_logic_vector(11 downto 0); --headstage communication input from the Deserilizer.
dev_reset_in : in std_logic; --a signal that resets the state machine and gives out a device map data stream.
conf_ack : in std_logic;
conf_nack : in std_logic;
conf_done : in std_logic;
conf_mem_in : in mem_type;
--cobs fifo output
async_fifo_wr_enb : out std_logic;
async_fifo_wr_data : out std_logic_vector(7 downto 0)
);
end async_com_control;
architecture Behavioral of async_com_control is
--COBS encoder declaration
component cobs_encoder is
Port (
bus_clk : in std_logic;
reset : in std_logic;
--cobs inputs
pre_cobs_data_in : in async_stream_type;
data_in_length : in std_logic_vector(4 downto 0);
cobs_conv_begin : in std_logic;
--cobs outputs
cobs_data_out : out cobs_stream_types;
data_out_length : out std_logic_vector(4 downto 0);
cobs_conv_rdy : out std_logic
);
end component;
type async_sm_type is (IDLE, DEVRESET, COBSCONV, COBSWAIT, COBSPUSH);
signal async_sm : async_sm_type;
--CMD array struct
type async_cmd_array_type is array (0 to 8) of std_logic_vector(31 downto 0);
--constant ASYNC_CMD_ARRAY : async_cmd_array_type := (
--x"00_00_00_00", --Configuration write ack
--x"00_00_00_01", --Configuration write Nack
--x"00_00_00_02", --Configuration read ack
--x"00_00_00_04", --Configuration read Nack
--x"00_00_00_08", --Configuration write ack
--x"00_00_00_10", --DEVICE MAP START
--x"00_00_01_00", --FRAME READ SIZE IN BYTES
--x"00_00_10_00", --FRAME WRITE SIZE IN BYTES
--x"00_01_00_00" --DEVICE MAP INSTANT
--);
constant ASYNC_CMD_ARRAY : async_cmd_array_type := (
"00000000000000000000000000000001", --Configuration write ack
"00000000000000000000000000000010", --Configuration write Nack
"00000000000000000000000000000100", --Configuration read ack
"00000000000000000000000000001000", --Configuration read Nack
"00000000000000000000000000010000", --Configuration write ack
"00000000000000000000000000100000", --DEVICE MAP START
"00000000000000000000000001000000", --FRAME READ SIZE IN BYTES
"00000000000000000000000010000000", --FRAME WRITE SIZE IN BYTES
"00000000000000000000000100000000" --DEVICE MAP INSTANT
);
constant DEVICEMAPACK : std_logic_vector(63 downto 0) := ASYNC_CMD_ARRAY(5) & std_logic_vector(to_unsigned(3,32));
constant FRAMERSIZE : std_logic_vector(63 downto 0) := ASYNC_CMD_ARRAY(6) & std_logic_vector(to_unsigned(134,32));
constant FRAMEWSIZE : std_logic_vector(63 downto 0) := ASYNC_CMD_ARRAY(7) & std_logic_vector(to_unsigned(341,32));
constant DEVICEINST_dev0 : std_logic_vector(191 downto 0) := ASYNC_CMD_ARRAY(8) & std_logic_vector(to_unsigned(2,32)) &
std_logic_vector(to_unsigned(134 ,32)) & std_logic_vector(to_unsigned(0,32)) &
std_logic_vector(to_unsigned(0,32)) & std_logic_vector(to_unsigned(0,32));
constant DEVICEINST_dev1 : std_logic_vector(191 downto 0) := ASYNC_CMD_ARRAY(8) & std_logic_vector(to_unsigned(2,32)) &
std_logic_vector(to_unsigned(134 ,32)) & std_logic_vector(to_unsigned(0,32)) &
std_logic_vector(to_unsigned(0,32)) & std_logic_vector(to_unsigned(0,32));
constant DEVICEINST_dev2 : std_logic_vector(191 downto 0) := ASYNC_CMD_ARRAY(8) & std_logic_vector(to_unsigned(3,32)) &
std_logic_vector(to_unsigned(18,32)) & std_logic_vector(to_unsigned(0,32)) &
std_logic_vector(to_unsigned(0,32)) & std_logic_vector(to_unsigned(0,32));
--A function to convert the memory blocks to async stream
function MEM_TO_24BYTE (
memin : mem_type; wr_rd : std_logic; ack : std_logic)
return async_stream_type is
variable bytes24 : async_stream_type;
variable k : integer := 0;
begin
if wr_rd = '0' and ack = '1' then --write and ack
bytes24(0) := ASYNC_CMD_ARRAY(0)(31 downto 24);
bytes24(1) := ASYNC_CMD_ARRAY(0)(23 downto 16);
bytes24(2) := ASYNC_CMD_ARRAY(0)(15 downto 8);
bytes24(3) := ASYNC_CMD_ARRAY(0)(7 downto 0);
elsif wr_rd = '0' and ack = '0' then --write and nack
bytes24(0) := ASYNC_CMD_ARRAY(1)(31 downto 24);
bytes24(1) := ASYNC_CMD_ARRAY(1)(23 downto 16);
bytes24(2) := ASYNC_CMD_ARRAY(1)(15 downto 8);
bytes24(3) := ASYNC_CMD_ARRAY(1)(7 downto 0);
elsif wr_rd = '1' and ack = '1' then --read and ack
bytes24(0) := ASYNC_CMD_ARRAY(2)(31 downto 24);
bytes24(1) := ASYNC_CMD_ARRAY(2)(23 downto 16);
bytes24(2) := ASYNC_CMD_ARRAY(2)(15 downto 8);
bytes24(3) := ASYNC_CMD_ARRAY(2)(7 downto 0);
elsif wr_rd = '1' and ack = '0' then --read and ack
bytes24(0) := ASYNC_CMD_ARRAY(3)(31 downto 24);
bytes24(1) := ASYNC_CMD_ARRAY(3)(23 downto 16);
bytes24(2) := ASYNC_CMD_ARRAY(3)(15 downto 8);
bytes24(3) := ASYNC_CMD_ARRAY(3)(7 downto 0);
end if;
for k in 1 to HS_MEMARRAY_LENGTH loop
bytes24(k*4) := memin(k-1)(31 downto 24);
bytes24(k*4+1) := memin(k-1)(23 downto 16);
bytes24(k*4+2) := memin(k-1)(15 downto 8);
bytes24(k*4+3) := memin(k-1)(7 downto 0);
end loop;
return bytes24;
end MEM_TO_24BYTE;
--a function to conver 192 length std_logic_vector to byte array
function VECTOR_TO_24BYTE (
vecin : std_logic_vector(191 downto 0))
return async_stream_type is
variable bytes24 : async_stream_type;
variable k : integer := 0;
begin
for k in 23 downto 0 loop
bytes24(23-k) := vecin(k*8+7 downto k*8);
end loop;
return bytes24;
end VECTOR_TO_24BYTE;
--a function to convert 64 length std_logic_vector to byte array
function VECTOR_TO_8BYTE (
vecin : std_logic_vector(63 downto 0))
return async_stream_type is
variable bytes8 : async_stream_type;
variable k : integer := 0;
begin
for k in 7 downto 0 loop
bytes8(7-k) := vecin(k*8+7 downto k*8);
end loop;
for k in 8 to 23 loop
bytes8(k) := "00000000";
end loop;
return bytes8;
end VECTOR_TO_8BYTE;
signal DEVICEMAPACK_BYTE : async_stream_type := VECTOR_TO_8BYTE(DEVICEMAPACK);
signal FRAMERSIZE_BYTE : async_stream_type := VECTOR_TO_8BYTE(FRAMERSIZE);
signal FRAMEWSIZE_BYTE : async_stream_type := VECTOR_TO_8BYTE(FRAMEWSIZE);
signal DEVICEINST_dev0_BYTE : async_stream_type := VECTOR_TO_24BYTE(DEVICEINST_dev0);
signal DEVICEINST_dev1_BYTE : async_stream_type := VECTOR_TO_24BYTE(DEVICEINST_dev1);
signal DEVICEINST_dev2_BYTE : async_stream_type := VECTOR_TO_24BYTE(DEVICEINST_dev2);
type async_stream_type_array is array (0 to 5) of async_stream_type;
signal pre_cobs_array : async_stream_type_array := (
DEVICEMAPACK_BYTE,
FRAMERSIZE_BYTE,
FRAMEWSIZE_BYTE,
DEVICEINST_dev0_BYTE,
DEVICEINST_dev1_BYTE,
DEVICEINST_dev2_BYTE
);
type cobs_length_array_type is array (0 to 6) of std_logic_vector(4 downto 0);
signal cobs_length_array : cobs_length_array_type := (
std_logic_vector(to_unsigned(8, 5)),
std_logic_vector(to_unsigned(8, 5)),
std_logic_vector(to_unsigned(8, 5)),
std_logic_vector(to_unsigned(24, 5)),
std_logic_vector(to_unsigned(24, 5)),
std_logic_vector(to_unsigned(24, 5)),
std_logic_vector(to_unsigned(24, 5))
);
signal cobs_begin : std_logic;
signal cobs_conv_rdy : std_logic;
signal array_cnt : unsigned(2 downto 0);
signal pre_cobs_data : async_stream_type;
signal cobs_data, cobs_data_in : cobs_stream_types;
signal data_in_length, cobs_length, data_out_length : std_logic_vector(4 downto 0);
signal fifo_push_cnt : unsigned(4 downto 0);
signal conf_ack_flag : std_logic;
begin
sm_process: process(bus_clk, reset, dev_reset_in)
begin
if (reset = '1') then
async_sm <= IDLE;
array_cnt <= (others=>'0');
fifo_push_cnt <= (others=>'0');
cobs_begin <= '0';
data_in_length <= (others=>'0');
cobs_length <= (others=>'0');
async_fifo_wr_data <= (others=>'0');
async_fifo_wr_enb <= '0';
conf_ack_flag <= '0';
--array initilization
for i in 0 to 25 loop
cobs_data(i) <= (others=>'0');
end loop;
for j in 0 to 23 loop
pre_cobs_data(j) <= (others=>'0');
end loop;
elsif (rising_edge(bus_clk)) then
if dev_reset_in = '1' then --<-- this is a "synchronous reset" that puts the state machine in to RESET state, which then sets a DEVICE map once dev_reset_in is released
async_sm <= DEVRESET;
array_cnt <= (others=>'0');
fifo_push_cnt <= (others=>'0');
cobs_begin <= '0';
data_in_length <= (others=>'0');
cobs_length <= (others=>'0');
async_fifo_wr_data <= (others=>'0');
async_fifo_wr_enb <= '0';
conf_ack_flag <= '0';
--array initilization
for i in 0 to 25 loop
cobs_data(i) <= (others=>'0');
end loop;
for j in 0 to 23 loop
pre_cobs_data(j) <= (others=>'0');
end loop;
else
case async_sm is
when IDLE =>
if (conf_ack = '1') then --go to COBSCONV
async_sm <= COBSCONV;
conf_ack_flag <= '1';
pre_cobs_data <= MEM_TO_24BYTE(conf_mem_in, '0', '1');
else
async_sm <= IDLE;
end if;
cobs_begin <= '0';
async_fifo_wr_enb <= '0';
async_fifo_wr_data <= (others=>'0');
when DEVRESET =>
--currently just go directly to the next state
async_sm <= COBSCONV;
cobs_begin <= '0';
when COBSCONV =>
if conf_ack_flag = '1' then
data_in_length <= std_logic_vector(to_unsigned(24, 5));
else
pre_cobs_data <= pre_cobs_array(to_integer(array_cnt));
data_in_length <= cobs_length_array(to_integer(array_cnt));
end if;
cobs_begin <= '1';
async_fifo_wr_enb <= '0';
async_sm <= COBSWAIT;
when COBSWAIT =>
cobs_begin <= '0';
if cobs_conv_rdy = '1' then --wait for cobs to finish conversion.
async_sm <= COBSPUSH;
cobs_data <= cobs_data_in;
cobs_length <= data_out_length;
cobs_begin <= '0';
end if;
when COBSPUSH => --push COBS to FIFO
cobs_begin <= '0';
if (fifo_push_cnt >= unsigned(cobs_length) - 1) then
fifo_push_cnt <= (others=>'0');
if conf_ack_flag = '1' then
async_sm <= IDLE;
conf_ack_flag <= '0';
else
if array_cnt < 5 then
array_cnt <= array_cnt + 1;
async_sm <= COBSCONV;
else
array_cnt <= (others=>'0');
async_sm <= IDLE;
end if;
end if;
else
fifo_push_cnt <= fifo_push_cnt + 1;
end if;
async_fifo_wr_data <= cobs_data(to_integer(fifo_push_cnt));
async_fifo_wr_enb <= '1';
end case;
end if;
end if;
end process;
COBS_inst: cobs_encoder
port map(
bus_clk => bus_clk,
reset => reset,
--cobs inputs
pre_cobs_data_in => pre_cobs_data,
data_in_length => data_in_length,
cobs_conv_begin => cobs_begin,
--cobs outputs
cobs_data_out => cobs_data_in,
data_out_length => data_out_length,
cobs_conv_rdy => cobs_conv_rdy
);
end Behavioral;
| mit | 406c6a1522b88de639af936d755a5ee3 | 0.641701 | 2.98908 | false | false | false | false |
Hyvok/HardHeat | src/adpll.vhd | 1 | 4,160 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adpll is
generic
(
TDC_N : positive;
FILT_P_SHIFT_N : integer;
FILT_I_SHIFT_N : integer;
FILT_INIT_OUT_VAL : positive;
FILT_OUT_OFFSET : natural;
FILT_OUT_LIMIT : natural;
ACCUM_BITS_N : positive;
ACCUM_WORD_N : positive;
LD_LOCK_N : positive;
LD_ULOCK_N : positive;
LD_LOCK_LIMIT : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
ref_in : in std_logic;
sig_out : out std_logic;
lock_out : out std_logic
);
end entity;
architecture rtl of adpll is
signal up : std_logic;
signal down : std_logic;
signal pid_out : signed(TDC_N - 1 downto 0);
signal phase_time : signed(TDC_N - 1 downto 0);
signal tuning_word : unsigned(ACCUM_WORD_N - 1 downto 0);
signal sig : std_logic;
function trunc_to_unsigned(arg : signed) return unsigned is
begin
return unsigned(std_logic_vector(arg));
end function;
function clamp_to_unsigned(arg : signed) return unsigned is
variable res : unsigned(arg'high - 1 downto 0);
begin
-- Shift value so it is always positive
res := trunc_to_unsigned(resize(arg + to_signed(2**(arg'length - 1) - 1
, arg'length)
, res'length));
return res;
end function;
function clamp(arg : unsigned; limit : natural) return unsigned is
begin
if arg > limit then
return to_unsigned(limit, arg'length);
else
return arg;
end if;
end function;
begin
sig_out <= sig;
pfd_p: entity work.resonant_pfd(rtl)
port map
(
clk => clk,
reset => reset,
sig_in => sig,
ref_in => ref_in,
up_out => up,
down_out => down
);
tdc_p: entity work.tdc(rtl)
generic map
(
COUNTER_N => TDC_N
)
port map
(
clk => clk,
reset => reset,
up_in => up,
down_in => down,
time_out => phase_time
);
filter_p: entity work.pid(rtl)
generic map
(
P_SHIFT_N => FILT_P_SHIFT_N,
I_SHIFT_N => FILT_I_SHIFT_N,
BITS_N => TDC_N,
INIT_OUT_VAL => FILT_INIT_OUT_VAL
)
port map
(
clk => clk,
reset => reset,
upd_clk_in => ref_in,
setpoint_in => to_signed(0, TDC_N),
pid_in => phase_time,
pid_out => pid_out
);
tuning_word <= clamp(shift_left(resize(clamp_to_unsigned(-pid_out)
, tuning_word'length)
, tuning_word'length - phase_time'length)
+ to_unsigned(FILT_OUT_OFFSET
, tuning_word'length)
, FILT_OUT_LIMIT);
phase_accumulator_p: entity work.phase_accumulator(rtl)
generic map
(
ACCUM_BITS_N => ACCUM_BITS_N,
TUNING_WORD_N => ACCUM_WORD_N
)
port map
(
clk => clk,
reset => reset,
tuning_word_in => tuning_word,
sig_out => sig
);
lock_detector_p: entity work.lock_detector(rtl)
generic map
(
PHASE_TIME_IN_N => TDC_N,
LOCK_COUNT_N => LD_LOCK_N,
ULOCK_COUNT_N => LD_ULOCK_N,
LOCK_LIMIT => LD_LOCK_LIMIT
)
port map
(
clk => clk,
reset => reset,
phase_time_in => phase_time,
lock_out => lock_out
);
end;
| mit | e691eccbac8078022bed348eb9b668a3 | 0.442548 | 3.977055 | false | false | false | false |
kacaperek/serdescrc16 | deserializer.vhd | 1 | 2,867 | ----------------------------------------------------------------------------------
-- Company: PWr
-- Engineer: Kacper Witkowski
-- Module Name: Serializer
-- Project Name: Nadajnik i odbiornik szeregowy z kontrolą poprawności przesyłu CRC16
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.PCK_CRC16_D1.all;
entity deserializer is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
serial_in : in STD_LOGIC;
serial_out : out std_logic;
parallel_out : out STD_LOGIC_vector(7 downto 0));
end deserializer;
architecture Behavioral of deserializer is
signal cnt : std_logic_vector(2 downto 0):= (others => '0');
signal d : std_logic_vector(7 downto 0):= (others => '0');
signal transmission_running : std_logic := '0'; -- czy transmisja działa? generowane po sygnale 0x7e
signal crc_running : std_logic := '0'; -- crc, liczone bo odebraniu 0x7e
signal pckg_cnt : std_logic_vector(4 downto 0) := (others => '0'); --licznik odebranych bajtów
signal newCRC : std_logic_vector(15 downto 0) := (others => '0'); -- wektor wartosci crc
begin
counter : process (reset, clk)
begin
if reset = '0' then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if transmission_running = '1' then
cnt <= cnt + "01";
if cnt = "111" and pckg_cnt = "10001" then
pckg_cnt <= "00000";
cnt <= "000";
elsif cnt = "111" then
pckg_cnt <= pckg_cnt + "01";
end if;
end if;
end if;
end process counter;
transmission_control : process(reset, clk)
begin
if reset='0' then
crc_running <= '0';
transmission_running <= '0';
elsif clk'event and clk = '1' then
if d = "01111110" and pckg_cnt = "00000" then
crc_running <= '1';
transmission_running <= '1';
elsif pckg_cnt = "10001" and cnt = "111" then
crc_running <= '0';
transmission_running <= '0';
end if;
end if;
end process transmission_control;
crc_calc : process(reset, clk)
begin
if clk'event and clk = '1' then
if crc_running = '1' then
newCRC <= nextCRC16(d(0), newCRC);
end if;
end if;
end process crc_calc;
sipo : process (reset, clk)
begin
if reset = '0' then
d <= (others => '0');
elsif (clk'event and clk = '1') then
d(7 downto 0) <= d(6 downto 0) & serial_in;
if transmission_running = '1' and pckg_cnt < "10000" and cnt = "111" then
parallel_out <= d;
end if;
end if;
end process sipo;
crcso : process(reset, clk, d)
begin
if reset = '0' then
serial_out <= '0';
elsif (clk'event and clk = '1') then
if pckg_cnt = "10001" and cnt = "111" then
if newCRC = "0000000000000000" then
serial_out <= '1';
end if;
else
serial_out <= '0';
end if;
end if;
end process crcso;
end Behavioral;
| gpl-2.0 | fd23d54a850f76ab4ba1b7df54a58ead | 0.587701 | 3.080732 | false | false | false | false |
Hyvok/HardHeat | sim/tdc/tdc_tb.vhd | 1 | 1,212 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tdc_tb is
end entity;
architecture rtl of tdc_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Up signal frequency 40 kHz
constant UP_PERIOD : time := 1 sec / 40e3;
-- Down signal frequency 50 kHz
constant DOWN_PERIOD : time := 1 sec / 50e3;
signal clk : std_logic := '0';
signal reset : std_logic;
signal up : std_logic := '0';
signal down : std_logic := '0';
begin
DUT_inst: entity work.tdc(rtl)
generic map
(
COUNTER_N => 12
)
port map
(
clk => clk,
reset => reset,
up_in => up,
down_in => down
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
up_gen: process(up)
begin
up <= not up after UP_PERIOD / 2;
end process;
down_gen: process(down)
begin
down <= not down after DOWN_PERIOD / 2;
end process;
end;
| mit | 64c22da86b5db60d4bdb411dc02308bd | 0.50165 | 3.740741 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/NES-Controller/nes_ip_core.vhd | 1 | 22,983 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: NES IP Core VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- nes_ip_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: nes_ip_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Sun Oct 16 17:16:09 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library nes_ip_core_v1_00_a;
use nes_ip_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity nes_ip_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR(0 to 7);
nes_latch : out STD_LOGIC;
nes_clk : out STD_LOGIC;
nes_data : in STD_LOGIC;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity nes_ip_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nes_ip_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity nes_ip_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
reset => reset,
led => led,
nes_latch => nes_latch,
nes_clk => nes_clk,
nes_data => nes_data,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| gpl-3.0 | 5c4af005580d7a1708e49ab679c5f571 | 0.457271 | 4.422167 | false | false | false | false |
albayaty/Video-Game-Engine | EDK/VGA/20x15/vga_ip_core.vhd | 1 | 22,878 | -- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 20x15 Resolution, IP Core VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- vga_ip_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: vga_ip_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Sat Oct 15 15:40:57 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library vga_ip_core_v1_00_a;
use vga_ip_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity vga_ip_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
hsync: out std_logic;
vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity vga_ip_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of vga_ip_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 7;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity vga_ip_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
hsync => hsync,
vsync => vsync,
rgb => rgb,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| gpl-3.0 | 87775a1f9f2fe63b4e97991be89ff1ff | 0.457053 | 4.441274 | false | false | false | false |
luk51000/tg2 | Experimentos/ex1/Sources/dynamic_fsm/dynamic.vhd | 1 | 802 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dynamic is
port (
clk_1hz : in std_logic;
leds : out std_logic_vector(3 downto 0)
);
end dynamic;
architecture Behavioral of dynamic is
type state_type is (s0,s1);
signal current_s,next_s: state_type;
signal output : std_logic_vector(3 downto 0);
begin
process (clk_1hz)
begin
if (rising_edge(clk_1hz)) then
current_s <= next_s;
end if;
end process;
process (current_s)
begin
case current_s is
when s0 =>
next_s <= s1;
output <= "0011";
when s1 =>
next_s <= s0;
output <= "1100";
end case;
end process;
leds <= output;
end Behavioral; | gpl-3.0 | ab5791ebb95645a1a56e1de8d17040db | 0.516209 | 3.645455 | false | false | false | false |
Hyvok/HardHeat | src/ds18b20_data_gen.vhd | 1 | 8,398 | library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity ds18b20_data_gen is
generic
(
MICROSECOND_D : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
ow_out : in std_logic;
-- Test temperature value in, data_gen generates a new data packet from
-- this value and transmits it to the 1-wire bus
temp_in : in signed(16 - 1 downto 0);
temp_in_f : in std_logic;
ow_in : out std_logic
);
end entity;
architecture rtl of ds18b20_data_gen is
subtype data_t is std_logic_vector(8 - 1 downto 0);
type data_array_t is array(natural range <>) of data_t;
function calc_crc(Arg : data_t; NewByte : data_t) return data_t is
variable crc : data_t;
variable bit_num : natural := 0;
begin
while bit_num < 8 loop
crc := Arg;
crc(crc'left) := NewByte(bit_num) xor crc(crc'right);
crc(4) := crc(3) xor crc(crc'left);
crc(5) := crc(4) xor crc(crc'left);
crc := shift_left_vec(crc, 1);
bit_num := bit_num + 1;
end loop;
return(crc);
end function;
function gen_data(Temp : signed(16 - 1 downto 0)) return data_array_t is
variable byte_num : natural := 0;
variable bit_num : natural := 0;
variable data : data_array_t(8 downto 0);
variable crc : data_t := (others => '0');
begin
while byte_num < 9 loop
if byte_num = 0 then
data(byte_num) := std_logic_vector(Temp(7 downto 0));
elsif byte_num = 1 then
data(byte_num) := std_logic_vector(Temp(15 downto 8));
-- Just use some (valid) fixed data for the rest of the bytes
elsif byte_num = 2 then
data(byte_num) := x"4B";
elsif byte_num = 3 then
data(byte_num) := x"46";
elsif byte_num = 4 then
data(byte_num) := x"FF";
elsif byte_num = 5 then
data(byte_num) := x"FF";
elsif byte_num = 6 then
data(byte_num) := x"02";
elsif byte_num = 7 then
data(byte_num) := x"10";
elsif byte_num = 8 then
data(byte_num) := crc;
-- Do not calculate CRC for CRC byte so just return
return(data);
end if;
crc := calc_crc(crc, data(byte_num));
byte_num := byte_num + 1;
end loop;
end function;
constant RESET_D : natural := MICROSECOND_D * 479;
constant RESET_WAIT_D : natural := MICROSECOND_D * 15;
constant RESET_PRESENCE_D : natural := MICROSECOND_D * 239;
constant ZERO_D : natural := MICROSECOND_D * 59;
constant ONE_D : natural := MICROSECOND_D * 1;
constant SKIP_ROM_CMD : std_logic_vector(8 - 1 downto 0) := x"CC";
constant CONV_CMD : std_logic_vector(8 - 1 downto 0) := x"44";
constant READ_CMD : std_logic_vector(8 - 1 downto 0) := x"BE";
begin
data_gen_p: process(clk, reset)
type data_gen_state is (
idle,
reset_wait,
presence,
wait_reset_high,
read,
command,
transmit
);
-- Increment timer value and go to next state when delay is fullfilled
procedure handle_delay( constant delay : in natural;
variable timer : inout natural;
constant next_state : in data_gen_state;
variable state_var : inout data_gen_state) is
begin
timer := timer + 1;
if timer >= delay then
state_var := next_state;
timer := 0;
end if;
end procedure;
procedure new_bit( variable buf : inout data_t;
constant val : in std_logic) is
begin
buf := shift_right_vec(buf, 1);
buf(buf'high) := val;
end procedure;
variable state : data_gen_state;
variable next_state : data_gen_state;
variable byte_num : natural;
variable bit_num : natural;
variable last_out : std_logic;
variable tx_buf : data_array_t(8 downto 0);
variable timer : natural;
variable rx_buf : data_t;
variable rx_bits_left : natural;
begin
if reset = '1' then
state := idle;
next_state := idle;
byte_num := 0;
bit_num := 0;
last_out := '0';
tx_buf := gen_data(temp_in);
timer := 0;
rx_buf := (others => '0');
rx_bits_left := 0;
ow_in <= '1';
elsif rising_edge(clk) then
if state = idle then
ow_in <= '1';
if ow_out = '0' then
handle_delay(RESET_D, timer, reset_wait, state);
else
timer := 0;
end if;
elsif state = reset_wait then
handle_delay(RESET_WAIT_D, timer, presence, state);
elsif state = presence then
ow_in <= '0';
handle_delay(RESET_PRESENCE_D, timer, wait_reset_high, state);
elsif state = wait_reset_high then
ow_in <= '1';
if ow_out = '1' then
state := read;
rx_buf := (others => '0');
rx_bits_left := rx_buf'length;
next_state := command;
end if;
elsif state = read then
ow_in <= '1';
if rx_bits_left > 0 then
if ow_out = '0' then
timer := timer + 1;
elsif ow_out = '1' then
if timer >= ZERO_D then
new_bit(rx_buf, '0');
rx_bits_left := rx_bits_left - 1;
elsif timer >= ONE_D then
new_bit(rx_buf, '1');
rx_bits_left := rx_bits_left - 1;
end if;
timer := 0;
end if;
else
state := next_state;
end if;
elsif state = command then
if rx_buf = SKIP_ROM_CMD then
next_state := command;
state := read;
rx_bits_left := rx_buf'length;
elsif rx_buf = CONV_CMD then
-- Just start waiting for next reset
state := idle;
next_state := idle;
rx_bits_left := rx_buf'length;
elsif rx_buf = READ_CMD then
state := transmit;
rx_bits_left := 0;
else
report "Unknown command" severity warning;
state := idle;
next_state := idle;
rx_bits_left := 0;
end if;
rx_buf := (others => '0');
elsif state = transmit then
if not last_out = ow_out and ow_out = '0' then
ow_in <= tx_buf(byte_num)(bit_num);
bit_num := bit_num + 1;
if bit_num = 8 then
bit_num := 0;
byte_num := byte_num + 1;
if byte_num = tx_buf'length then
state := idle;
next_state := idle;
bit_num := 0;
byte_num := 0;
end if;
end if;
end if;
end if;
last_out := ow_out;
-- Update TX buffer data if temperature has changed
if temp_in_f = '1' then
tx_buf := gen_data(temp_in);
end if;
end if;
end process;
end;
| mit | d18eadd8a37c32ccfe30c6d0d7ae3506 | 0.43427 | 4.286881 | false | false | false | false |
suoto/hdlcc | .ci/test_support/test_project/basic_library/clock_divider.vhd | 1 | 1,392 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic_library;
use basic_library.very_common_pkg.all;
use work.package_with_constants;
entity clock_divider is
generic (
DIVIDER : integer := 10
);
port (
reset : in std_logic;
clk_input : in std_logic;
clk_output : out std_logic
);
end clock_divider;
architecture clock_divider of clock_divider is
signal counter : integer range 0 to DIVIDER - 1 := 0;
signal clk_internal : std_logic := '0';
signal clk_enable_unused : std_logic := '0';
begin
clk_output <= clk_internal;
useless_u : clk_en_generator
generic map (
DIVIDER => DIVIDER)
port map (
reset => reset,
clk_input => clk_input,
clk_en => open);
-- We read 'reset' signal asynchronously inside the process to force
-- msim issuing a synthesis warning
process(clk_input)
begin
if reset = '1' then
counter <= 0;
elsif clk_input'event and clk_input = '1' then
if counter < DIVIDER then
counter <= counter + 1;
else
counter <= 0;
clk_internal <= not clk_internal;
end if;
end if;
end process;
end clock_divider;
| gpl-3.0 | 1cdc644b62760b775232a891d810217f | 0.541667 | 4.130564 | false | false | false | false |
iamllama/EE2020 | ee2020.cache/ip/3d845bac08f84459/dds_compiler_0_sim_netlist.vhdl | 1 | 142,143 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Mar 28 02:08:39 2017
-- Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_sim_netlist.vhdl
-- Design : dds_compiler_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
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52wMbdvDVXAK7Lh69I5oSCOgqn9PANGvIBLbdCImWYxo6U8hcpqV7QST3zxY2pkPsv3qKYeB3PuB
g8Y4iq9TaYFrMf8EjzlaIDyAI9Ry1eb40Ss/envxzTr0J41pUiBQP9rSzpGA240FrwIbHNs3zSfh
p9EfL+Q4
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 5;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 10;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "artix7";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 11 );
signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 22;
attribute C_AMPLITUDE of i_synth : label is 1;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 5;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS of i_synth : label is 10000;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 16;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING of i_synth : label is 1;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 0;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH of i_synth : label is 12;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 10;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 24;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 of i_synth : label is 1;
attribute C_XDEVICEFAMILY of i_synth : label is "artix7";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
debug_axi_chan_in(0) <= \<const0>\;
debug_axi_pinc_in(21) <= \<const0>\;
debug_axi_pinc_in(20) <= \<const0>\;
debug_axi_pinc_in(19) <= \<const0>\;
debug_axi_pinc_in(18) <= \<const0>\;
debug_axi_pinc_in(17) <= \<const0>\;
debug_axi_pinc_in(16) <= \<const0>\;
debug_axi_pinc_in(15) <= \<const0>\;
debug_axi_pinc_in(14) <= \<const0>\;
debug_axi_pinc_in(13) <= \<const0>\;
debug_axi_pinc_in(12) <= \<const0>\;
debug_axi_pinc_in(11) <= \<const0>\;
debug_axi_pinc_in(10) <= \<const0>\;
debug_axi_pinc_in(9) <= \<const0>\;
debug_axi_pinc_in(8) <= \<const0>\;
debug_axi_pinc_in(7) <= \<const0>\;
debug_axi_pinc_in(6) <= \<const0>\;
debug_axi_pinc_in(5) <= \<const0>\;
debug_axi_pinc_in(4) <= \<const0>\;
debug_axi_pinc_in(3) <= \<const0>\;
debug_axi_pinc_in(2) <= \<const0>\;
debug_axi_pinc_in(1) <= \<const0>\;
debug_axi_pinc_in(0) <= \<const0>\;
debug_axi_poff_in(21) <= \<const0>\;
debug_axi_poff_in(20) <= \<const0>\;
debug_axi_poff_in(19) <= \<const0>\;
debug_axi_poff_in(18) <= \<const0>\;
debug_axi_poff_in(17) <= \<const0>\;
debug_axi_poff_in(16) <= \<const0>\;
debug_axi_poff_in(15) <= \<const0>\;
debug_axi_poff_in(14) <= \<const0>\;
debug_axi_poff_in(13) <= \<const0>\;
debug_axi_poff_in(12) <= \<const0>\;
debug_axi_poff_in(11) <= \<const0>\;
debug_axi_poff_in(10) <= \<const0>\;
debug_axi_poff_in(9) <= \<const0>\;
debug_axi_poff_in(8) <= \<const0>\;
debug_axi_poff_in(7) <= \<const0>\;
debug_axi_poff_in(6) <= \<const0>\;
debug_axi_poff_in(5) <= \<const0>\;
debug_axi_poff_in(4) <= \<const0>\;
debug_axi_poff_in(3) <= \<const0>\;
debug_axi_poff_in(2) <= \<const0>\;
debug_axi_poff_in(1) <= \<const0>\;
debug_axi_poff_in(0) <= \<const0>\;
debug_axi_resync_in <= \<const0>\;
debug_core_nd <= \<const0>\;
debug_phase(21) <= \<const0>\;
debug_phase(20) <= \<const0>\;
debug_phase(19) <= \<const0>\;
debug_phase(18) <= \<const0>\;
debug_phase(17) <= \<const0>\;
debug_phase(16) <= \<const0>\;
debug_phase(15) <= \<const0>\;
debug_phase(14) <= \<const0>\;
debug_phase(13) <= \<const0>\;
debug_phase(12) <= \<const0>\;
debug_phase(11) <= \<const0>\;
debug_phase(10) <= \<const0>\;
debug_phase(9) <= \<const0>\;
debug_phase(8) <= \<const0>\;
debug_phase(7) <= \<const0>\;
debug_phase(6) <= \<const0>\;
debug_phase(5) <= \<const0>\;
debug_phase(4) <= \<const0>\;
debug_phase(3) <= \<const0>\;
debug_phase(2) <= \<const0>\;
debug_phase(1) <= \<const0>\;
debug_phase(0) <= \<const0>\;
debug_phase_nd <= \<const0>\;
event_phase_in_invalid <= \<const0>\;
event_pinc_invalid <= \<const0>\;
event_poff_invalid <= \<const0>\;
event_s_config_tlast_missing <= \<const0>\;
event_s_config_tlast_unexpected <= \<const0>\;
event_s_phase_chanid_incorrect <= \<const0>\;
event_s_phase_tlast_unexpected <= \<const0>\;
m_axis_data_tdata(15) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(14) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(13) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(12) <= \^m_axis_data_tdata\(11);
m_axis_data_tdata(11 downto 0) <= \^m_axis_data_tdata\(11 downto 0);
m_axis_data_tlast <= \<const0>\;
m_axis_data_tuser(0) <= \<const0>\;
m_axis_phase_tdata(0) <= \<const0>\;
m_axis_phase_tlast <= \<const0>\;
m_axis_phase_tuser(0) <= \<const0>\;
m_axis_phase_tvalid <= \<const0>\;
s_axis_config_tready <= \<const1>\;
s_axis_phase_tready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13_viv
port map (
aclk => aclk,
aclken => '0',
aresetn => '0',
debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15) => \^m_axis_data_tdata\(11),
m_axis_data_tdata(14 downto 11) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(14 downto 11),
m_axis_data_tdata(10 downto 0) => \^m_axis_data_tdata\(10 downto 0),
m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 22) => B"00",
s_axis_phase_tdata(21 downto 0) => s_axis_phase_tdata(21 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "dds_compiler_0,dds_compiler_v6_0_13,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "dds_compiler_v6_0_13,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of U0 : label is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of U0 : label is 1;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of U0 : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of U0 : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of U0 : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of U0 : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of U0 : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of U0 : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of U0 : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of U0 : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of U0 : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of U0 : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 5;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of U0 : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of U0 : label is 10000;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of U0 : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of U0 : label is 16;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of U0 : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of U0 : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of U0 : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of U0 : label is 1;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of U0 : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of U0 : label is 0;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of U0 : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of U0 : label is 12;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of U0 : label is 10;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of U0 : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of U0 : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of U0 : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of U0 : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of U0 : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of U0 : label is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of U0 : label is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
debug_axi_chan_in(0) => NLW_U0_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_U0_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_U0_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_U0_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_U0_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_U0_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_U0_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_U0_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_U0_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_U0_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_U0_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(15 downto 0) => m_axis_data_tdata(15 downto 0),
m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_U0_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_U0_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_U0_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_U0_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 0) => s_axis_phase_tdata(23 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
| gpl-3.0 | 183fa635117037fb0f0b7bde31a25b1c | 0.896822 | 1.999226 | false | false | false | false |
cafe-alpha/wasca | fpga_firmware/wasca_toplevel.vhd | 1 | 15,410 | -- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
external_sdram_controller_wire_clk : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(25 downto 16) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0'; -- .muxing
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0'); -- .muxing
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0'; -- .direction
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := 'X'; -- b_SD_cmd
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := 'X'; -- b_SD_dat
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := 'X'; -- b_SD_dat3
altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic ; -- o_SD_clock
uart_0_external_connection_txd : out std_logic := '0' ;
spi_stm32_MISO : in std_logic; -- MISO
spi_stm32_MOSI : out std_logic := '0'; -- MOSI
spi_stm32_SCLK : out std_logic := '0'; -- SCLK
spi_stm32_SS_n : out std_logic := '0'; -- SS_n
audio_out_BCLK : in std_logic := '0'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := '0'; -- DACLRCK
audio_SSEL : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'Z'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'Z'; -- read
abus_avalon_sdram_bridge_0_abus_waitrequest : out std_logic; -- waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'Z'); -- addressdata
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'Z'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_disable_out : out std_logic; -- disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'Z'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'Z'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'Z'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
audio_out_BCLK : in std_logic := 'Z'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := 'Z'; -- DACLRCK
clk_clk : in std_logic := 'Z'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := 'Z'; -- b_SD_cmd
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := 'Z'; -- b_SD_dat
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := 'Z'; -- b_SD_dat3
altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic ; -- o_SD_clock
buffered_spi_miso : in std_logic; -- MISO
buffered_spi_mosi : out std_logic := 'Z'; -- MOSI
buffered_spi_clk : out std_logic := 'Z'; -- SCLK
buffered_spi_cs : out std_logic := 'Z'; -- SS_n
uart_0_external_connection_rxd : in std_logic := 'Z'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
reset_reset_n : in std_logic := 'Z'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'Z' ; -- reset
altpll_1_areset_conduit_export : in std_logic := 'Z'; -- export
altpll_1_locked_conduit_export : out std_logic; -- export
altpll_1_phasedone_conduit_export : out std_logic -- export
);
end component;
signal altpll_1_areset_conduit_export : std_logic := '0';
signal altpll_1_locked_conduit_export : std_logic := '0';
signal altpll_1_phasedone_conduit_export : std_logic := '0';
--signal sega_saturn_abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal sega_saturn_abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
signal clock_116_mhz : std_logic := '0';
signal por_counter : unsigned(31 downto 0) := (others => '0');
signal por_reset : std_logic := '0';
signal por_reset_n : std_logic := '0';
begin
--sega_saturn_abus_slave_0_abus_muxing (0) <= not sega_saturn_abus_slave_0_abus_muxing(1);
external_sdram_controller_wire_clk <= not clock_116_mhz;
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
clock_116_mhz_clk => clock_116_mhz,
abus_avalon_sdram_bridge_0_sdram_addr => external_sdram_controller_wire_addr,
abus_avalon_sdram_bridge_0_sdram_ba => external_sdram_controller_wire_ba,
abus_avalon_sdram_bridge_0_sdram_cas_n => external_sdram_controller_wire_cas_n,
abus_avalon_sdram_bridge_0_sdram_cke => external_sdram_controller_wire_cke,
abus_avalon_sdram_bridge_0_sdram_cs_n => external_sdram_controller_wire_cs_n,
abus_avalon_sdram_bridge_0_sdram_dq => external_sdram_controller_wire_dq,
abus_avalon_sdram_bridge_0_sdram_dqm => external_sdram_controller_wire_dqm,
abus_avalon_sdram_bridge_0_sdram_ras_n => external_sdram_controller_wire_ras_n,
abus_avalon_sdram_bridge_0_sdram_we_n => external_sdram_controller_wire_we_n,
abus_avalon_sdram_bridge_0_abus_address => sega_saturn_abus_slave_0_abus_address,
abus_avalon_sdram_bridge_0_abus_chipselect => "1"&sega_saturn_abus_slave_0_abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
abus_avalon_sdram_bridge_0_abus_read => sega_saturn_abus_slave_0_abus_read,
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => sega_saturn_abus_slave_0_abus_write,
abus_avalon_sdram_bridge_0_abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest,
abus_avalon_sdram_bridge_0_abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt,
abus_avalon_sdram_bridge_0_abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata,
abus_avalon_sdram_bridge_0_abus_direction => sega_saturn_abus_slave_0_abus_direction,
abus_avalon_sdram_bridge_0_abus_muxing => sega_saturn_abus_slave_0_abus_muxing,
abus_avalon_sdram_bridge_0_abus_disable_out => sega_saturn_abus_slave_0_abus_disableout,
abus_avalon_sdram_bridge_0_abus_reset => reset_reset_n,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat,
altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock => altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock,
altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd,
altpll_1_areset_conduit_export => altpll_1_areset_conduit_export,
altpll_1_locked_conduit_export => altpll_1_locked_conduit_export,
altpll_1_phasedone_conduit_export => altpll_1_phasedone_conduit_export,
uart_0_external_connection_rxd => '0',
uart_0_external_connection_txd => uart_0_external_connection_txd,
buffered_spi_miso => spi_stm32_MISO,
buffered_spi_mosi => spi_stm32_MOSI,
buffered_spi_clk => spi_stm32_SCLK,
buffered_spi_cs => spi_stm32_SS_n,
audio_out_BCLK => audio_out_BCLK,
audio_out_DACDAT => audio_out_DACDAT,
audio_out_DACLRCK => audio_out_DACLRCK,
reset_reset_n => por_reset_n,
reset_controller_0_reset_in1_reset => por_reset
);
--empty subsystem
-- external_sdram_controller_wire_addr <= (others => 'Z');
-- external_sdram_controller_wire_ba <= (others => 'Z');
-- external_sdram_controller_wire_cas_n <= (others => 'Z');
-- external_sdram_controller_wire_cke <= (others => 'Z');
-- external_sdram_controller_wire_cs_n <= (others => 'Z');
-- external_sdram_controller_wire_dq <= (others => 'Z');
-- external_sdram_controller_wire_dqm <= (others => 'Z');
-- external_sdram_controller_wire_ras_n <= (others => 'Z');
-- external_sdram_controller_wire_we_n <= (others => 'Z');
-- external_sdram_controller_wire_clk <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_addressdata <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_waitrequest <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_interrupt <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_disableout <= '1';
-- sega_saturn_abus_slave_0_abus_muxing <= "00";
-- sega_saturn_abus_slave_0_abus_direction <= '0';
-- spi_sd_card_MOSI <= 'Z';
-- spi_sd_card_SCLK <= 'Z';
-- spi_sd_card_SS_n <= 'Z';
-- uart_0_external_connection_txd <= 'Z';
-- spi_stm32_MISO <= 'Z';
-- audio_out_DACDAT <= 'Z';
audio_SSEL <= '1';
--sega_saturn_abus_slave_0_abus_waitrequest <= '1';
--sega_saturn_abus_slave_0_abus_direction <= '0';
--sega_saturn_abus_slave_0_abus_muxing <= "01";
--por
process (clock_116_mhz)
begin
if std_logic(por_counter(24)) = '0' then
por_counter <= por_counter + 1;
end if;
end process;
por_reset <= (std_logic(por_counter(22)));
por_reset_n <= not (std_logic(por_counter(22)));
end architecture rtl; -- of wasca_toplevel
| gpl-2.0 | 60ad4cda0725e41cf4d64465988cbe8f | 0.500584 | 3.559714 | false | false | false | false |
kacaperek/serdescrc16 | PCK_CRC16_D1.vhd | 1 | 2,023 | --------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose : synthesizable CRC function
-- * polynomial: (0 2 12 16)
-- * data width: 1
--
-- Info : [email protected]
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package PCK_CRC16_D1 is
-- polynomial: (0 2 12 16)
-- data width: 1
-- convention: the first serial bit is D[0]
function nextCRC16
(Data: std_logic;
crc: std_logic_vector(15 downto 0))
return std_logic_vector;
end PCK_CRC16_D1;
package body PCK_CRC16_D1 is
-- polynomial: (0 2 12 16)
-- data width: 1
-- convention: the first serial bit is D[0]
function nextCRC16
(Data: std_logic;
crc: std_logic_vector(15 downto 0))
return std_logic_vector is
variable d: std_logic_vector(0 downto 0);
variable c: std_logic_vector(15 downto 0);
variable newcrc: std_logic_vector(15 downto 0);
begin
d(0) := Data;
c := crc;
newcrc(0) := d(0) xor c(15);
newcrc(1) := c(0);
newcrc(2) := d(0) xor c(1) xor c(15);
newcrc(3) := c(2);
newcrc(4) := c(3);
newcrc(5) := c(4);
newcrc(6) := c(5);
newcrc(7) := c(6);
newcrc(8) := c(7);
newcrc(9) := c(8);
newcrc(10) := c(9);
newcrc(11) := c(10);
newcrc(12) := d(0) xor c(11) xor c(15);
newcrc(13) := c(12);
newcrc(14) := c(13);
newcrc(15) := c(14);
return newcrc;
end nextCRC16;
end PCK_CRC16_D1;
| gpl-2.0 | 3d6270af5bd715205f4e7a5526524e34 | 0.574394 | 3.38861 | false | false | false | false |
Subsets and Splits